Preparation method for semiconductor packaging structure capable of avoiding cu diffusion

Abstract

The present invention provides a preparation method for a semiconductor packaging structure capable of avoiding Cu diffusion. A packaging layer located on a Cu metal pillar is reserved when a first silicon chip is ground for thinning, only a composite interface between the packaging layer and the silicon chip is ground, and then the Cu metal pillar is exposed by patterning the packaging layer, so as to perform electrical connection, so that Cu metal can be prevented from remaining on the first silicon chip during thinning, thereby preventing Cu and Si from being ground at the same time, and avoiding contamination caused by Cu metal diffusion.

Description

Preparation method of semiconductor packaging structure avoiding Cu diffusion Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing and relates to a method for preparing a semiconductor packaging structure that avoids Cu diffusion. Background Art

[0002] The rapid development of electronic products is the main driving force for the evolution of packaging technology today. Miniaturization, high density, high frequency, high speed, high reliability and low cost are the mainstream development directions of advanced packaging.

[0003] Existing consumer electronic product packaging generally adopts Package on Package (POP) stacking packaging. With the increasing functional integration of electronic products, the packaging structure is highly centralized. The heat generated during the operation of the chip will cause irreversible damage to the chip itself. Therefore, the heat dissipation problem of the packaging structure needs to be considered, and the heat dissipation demand of product packaging is becoming increasingly higher.

[0004] As shown in Figures 1 and 2, in a conventional packaging structure, grinding is generally used to thin and expose the backside of the underlying silicon chip 10 to increase heat dissipation. During the grinding process, to facilitate subsequent electrical connections, the copper (Cu) metal pillars 20 surrounding the silicon (Si) chip 10 are simultaneously ground to expose the surface of the Cu metal pillars 20 for subsequent electrical connections. That is, during the grinding process, the composite interface of the Cu metal pillars 20 / silicon chip 10 / encapsulation layer 30 is simultaneously ground, and then the stacking package of the upper chip is performed. However, during the grinding process of the composite interface of the Cu metal pillars 20 / silicon chip 10 / encapsulation layer 30, Cu metal 40 may remain on the backside of the silicon chip 10. Since Cu metal has a large diffusion coefficient, especially Cu metal is extremely easy to diffuse in silicon material, the residual Cu metal 40 will quickly diffuse into the underlying silicon chip 10, causing Cu contamination, resulting in functional failure of Cu-sensitive chips, such as reduced breakdown voltage and leakage.

[0005] Therefore, it is necessary to provide a method for preparing a semiconductor packaging structure that avoids Cu diffusion. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for preparing a semiconductor packaging structure that avoids Cu diffusion, so as to solve the problem of Cu contamination caused by Cu metal diffusion in the prior art.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a semiconductor packaging structure that avoids Cu diffusion, comprising the following steps:

[0008] providing a supporting substrate;

[0009] forming a first redistribution layer on the supporting substrate;

[0010] forming a Cu metal column in the first redistribution layer, wherein the Cu metal column is electrically connected to the first redistribution layer;

[0011] Providing a first silicon chip, and bonding the first silicon chip to the first re-distribution layer in a flip-chip manner, wherein the first silicon chip is electrically connected to the first re-distribution layer;

[0012] forming a first packaging layer, wherein the first packaging layer covers the first rewiring layer, the Cu metal pillar, and the first silicon chip;

[0013] performing grinding to thin the first silicon chip, whereby after grinding, the first packaging layer exposes the first silicon chip and covers the Cu metal pillar;

[0014] Patterning the first packaging layer to form a groove in the first packaging layer to expose the Cu metal column;

[0015] forming a second redistribution layer on the first packaging layer, wherein the second redistribution layer is electrically connected to the Cu metal pillar;

[0016] forming a heat dissipation metal block on the second redistribution layer, wherein a vertical projection of the heat dissipation metal block is located on the first silicon chip;

[0017] Providing a second chip, and bonding the second chip to the second redistribution layer in a flip-chip manner, wherein the second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip;

[0018] forming a second packaging layer, wherein the second packaging layer covers the second redistribution layer, the heat dissipation metal block and the second chip;

[0019] removing the supporting substrate to expose the first rewiring layer;

[0020] A metal bump is formed on the first redistribution layer, wherein the metal bump is electrically connected to the first redistribution layer.

[0021] Optionally, a method of patterning the first packaging layer to form the groove includes a laser drilling method, an etching method or a mechanical drilling method.

[0022] Optionally, the method of forming the Cu metal pillar includes electroplating.

[0023] Optionally, the thickness of the first packaging layer on the Cu metal pillar before grinding is greater than 15 μm.

[0024] Optionally, a method of forming the heat dissipation metal block includes an electroplating method or a thermal conductive bonding method.

[0025] Optionally, the heat dissipation metal block includes a Cu metal block, a Ni metal block or an Au metal block.

[0026] Optionally, the metal wiring in the second rewiring layer includes a metal seed diffusion barrier layer, and the metal seed diffusion barrier layer is in direct contact with the first silicon chip.

[0027] Optionally, the material of the metal seed diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal and Ti metal.

[0028] Optionally, the heat dissipation metal block covers the heat source area of ​​the first silicon chip in a vertical projection.

[0029] Optionally, the semiconductor packaging structure is a wafer-level semiconductor packaging structure, and after forming the metal bumps, a cutting step is further included.

[0030] As described above, the method for preparing a semiconductor package structure that avoids Cu diffusion of the present invention retains the package layer located on the Cu metal pillars when grinding and thinning the first silicon chip, grinds only the composite interface of the package layer / silicon chip, and then exposes the Cu metal pillars by patterning the package layer for electrical connection. Therefore, during thinning, Cu metal residue can be prevented from remaining on the first silicon chip, thereby avoiding simultaneous grinding of Cu / Si and preventing Cu metal diffusion contamination. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 is a schematic diagram showing a structure after forming an encapsulation layer in the prior art.

[0032] FIG2 is a schematic diagram showing the structure after grinding in the prior art.

[0033] FIG. 3 is a schematic diagram showing a process flow for preparing a semiconductor package structure according to an embodiment of the present invention.

[0034] 4 to 13 are schematic structural diagrams showing steps in preparing a semiconductor package structure according to an embodiment of the present invention.

[0035] DESCRIPTION OF REFERENCE NUMERALS 10 silicon chip 20 Cu metal pillar 30 packaging layer 40 residual Cu metal 100 supporting substrate 101 separation layer 210 first redistribution layer 211 first metal wiring 212 first dielectric layer 220 second redistribution layer 221 second metal wiring 222 second dielectric layer 300 Cu metal pillar 410 first silicon chip 420 second chip 510 first underfill layer 520 second underfill layer 610 first packaging layer 611 groove 620 second packaging layer 700 heat dissipation metal block 810 first metal bump 820 second metal bump 830 third metal bump DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0038] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0039] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0040] As shown in FIG3 , this embodiment provides a method for preparing a semiconductor package structure that avoids Cu diffusion, including the following steps:

[0041] S1: providing a supporting substrate;

[0042] S2: forming a first redistribution layer on the supporting substrate;

[0043] S3: forming a Cu metal column in the first redistribution layer, wherein the Cu metal column is electrically connected to the first redistribution layer;

[0044] S4: providing a first silicon chip, and bonding the first silicon chip to the first re-distribution layer in a flip-chip manner, wherein the first silicon chip is electrically connected to the first re-distribution layer;

[0045] S5: forming a first packaging layer, wherein the first packaging layer covers the first rewiring layer, the Cu metal pillar and the first silicon chip;

[0046] S6: performing grinding to thin the first silicon chip, whereby after grinding, the first packaging layer exposes the first silicon chip and covers the Cu metal pillar;

[0047] S7: patterning the first packaging layer to form a groove in the first packaging layer to expose the Cu metal column;

[0048] S8: forming a second redistribution layer on the first packaging layer, wherein the second redistribution layer is electrically connected to the Cu metal pillar;

[0049] S9: forming a heat dissipation metal block on the second redistribution layer, wherein a vertical projection of the heat dissipation metal block is located on the first silicon chip;

[0050] S10: providing a second chip, and bonding the second chip to the second redistribution layer in a flip-chip manner, wherein the second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip;

[0051] S11: forming a second packaging layer, wherein the second packaging layer covers the second redistribution layer, the heat dissipation metal block and the second chip;

[0052] S12: removing the supporting substrate to expose the first rewiring layer;

[0053] S13: forming metal bumps on the first redistribution layer, wherein the metal bumps are electrically connected to the first redistribution layer.

[0054] The preparation of the semiconductor packaging structure will be further introduced below with reference to Figures 4 to 13 of the specification.

[0055] First, referring to FIG. 3 and FIG. 4 , step S1 is performed to provide a support substrate 100 .

[0056] Specifically, the support substrate 100 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so as to provide support for subsequent processes through the support substrate 100. The size of the support substrate 100 is not limited here, and is preferably wafer-level.

[0057] Among them, in order to facilitate the subsequent removal of the supporting substrate 100, in this embodiment, a separation layer 101 is preferably formed on the surface of the supporting substrate 100. The separation layer 101 includes but is not limited to a tape and a polymer layer. For example, the separation layer 101 can be a photothermal conversion layer formed by a photothermal conversion (LTHC) coating material, so that light / radiation (such as laser) can be used to decompose the LTHC coating material under heat to release the supporting substrate 100, thereby improving the convenience of the separation operation.

[0058] Next, referring to FIG. 3 and FIG. 5 , step S2 is performed to form a first redistribution layer 210 on the support substrate 100 .

[0059] Specifically, the first redistribution layer 210 includes a first metal wiring 211 and a first dielectric layer 212. The first dielectric layer 212 can be formed of a polymer such as polybenzoxazole (PBO) or polyimide, or an inorganic dielectric material such as silicon nitride or silicon oxide. The first metal wiring 211 can include copper, tungsten, or alloys thereof. The specific structure and material selection of the first redistribution layer 210 are not particularly limited herein.

[0060] Next, referring to FIG. 3 and FIG. 6 , step S3 is performed to form a Cu metal pillar 300 in the first redistribution layer 210 . The Cu metal pillar 300 is electrically connected to the first redistribution layer 210 .

[0061] Specifically, the Cu metal pillar 300 may be formed by photolithography, etching, and electroplating, but is not limited thereto.

[0062] 3 and 7 , step S4 is performed to provide a first silicon chip 410 . The first silicon chip 410 is flip-chip bonded to the first redistribution layer 210 . The first silicon chip 410 is electrically connected to the first redistribution layer 210 .

[0063] Specifically, the first silicon chip 410 may be a SoC chip, but is not limited thereto. The front surface of the first silicon chip 410 has a first metal bump 810, such as a solder ball bump or a copper pillar bump. After the first silicon chip 410 is flip-chip bonded, one end of the first metal bump 810 is electrically connected to a pad (not shown) of the first silicon chip 410, and the other end of the first metal bump 810 is electrically connected to the first redistribution layer 210. The back surface of the first silicon chip 410 is away from the first redistribution layer 210.

[0064] After bonding the first silicon chip 410, a first underfill layer 510 may be formed between the first silicon chip 410 and the first redistribution layer 210, such as by dispensing. The first underfill layer 510 serves as a protective layer between the first silicon chip 410 and the first redistribution layer 210. The material of the first underfill layer 510 is not particularly limited.

[0065] Next, referring to FIG. 3 and FIG. 8 , step S5 is performed to form a first packaging layer 610 . The first packaging layer 610 covers the first re-distribution layer 210 , the Cu metal pillars 300 , and the first silicon chip 410 .

[0066] Specifically, the method of forming the first packaging layer 610 may include but is not limited to compression molding, transfer molding and spin coating, and the material of the first packaging layer 610 may include but is not limited to epoxy resin and polyamide. There is no excessive restriction on the material and preparation method of the first packaging layer 610.

[0067] Next, referring to FIG. 3 and FIG. 9 , step S6 is performed to perform grinding to thin the first silicon chip 410 . After grinding, the first packaging layer 610 exposes the first silicon chip 410 and covers the Cu metal pillar 300 .

[0068] Specifically, the grinding method may include chemical mechanical polishing (CMP) to remove part of the first packaging layer 610 to expose the back side of the first silicon chip 410, so as to thin the first silicon chip 410 by grinding to facilitate heat dissipation and reduce the packaging size.

[0069] Among them, when grinding the composite interface of the silicon layer / packaging layer composed of the first silicon chip 410 and the first packaging layer 610, since the first packaging layer 610 covers the Cu metal column 300, the Cu metal column 300 is not ground, thereby avoiding the influence of Cu metal on the electrical performance of the first silicon chip 410.

[0070] In order to avoid exposure of the Cu metal column 300 during grinding, the thickness of the first packaging layer 610 located on the Cu metal column 300 must be at least greater than the grinding tolerance, such as 15μm to 30μm, specifically 15μm, 20μm, 25μm, 30μm, etc.

[0071] Next, referring to FIG. 3 and FIG. 10 , step S7 is performed to pattern the first packaging layer 610 to form a groove 611 in the first packaging layer 610 to expose the Cu metal pillar 300 .

[0072] Specifically, the method of patterning the first packaging layer 610 to form the groove 611 may include laser drilling, etching or mechanical drilling, etc. There is no excessive restriction on the patterning method, the size and morphology of the formed groove 611, etc.

[0073] Next, referring to FIG. 3 and FIG. 11 , step S8 is performed to form a second redistribution layer 220 on the first packaging layer 610 . The second redistribution layer 220 is electrically connected to the Cu metal pillars 300 .

[0074] Specifically, the second redistribution layer 220 includes a second metal wiring 221 and a second dielectric layer 222. The second dielectric layer 222 can be formed of a polymer such as polybenzoxazole (PBO) or polyimide, or an inorganic dielectric material such as silicon nitride or silicon oxide. The second metal wiring 221 can include copper, tungsten, or alloys thereof. The specific structure and material selection of the second redistribution layer 220 are not particularly limited herein.

[0075] When the second redistribution layer 220 is prepared, the second metal wiring 221 fills the groove 611 , thereby electrically connecting the second redistribution layer 220 to the Cu metal pillar 300 .

[0076] Among them, it is preferred that when preparing the second rewiring layer 220, the second metal wiring 221 includes a metal seed diffusion barrier layer (not shown), and the metal seed diffusion barrier layer is in direct contact with the first silicon chip 410, so that heat dissipation of the first silicon chip 410 can be achieved through the metal wiring in direct contact with the first silicon chip 410, and the presence of the metal seed diffusion barrier layer can avoid the diffusion of metal wiring such as Cu in the first silicon chip 410.

[0077] The material of the metal seed diffusion barrier layer may include one or a combination of Ni metal, Au metal, Sn metal, Ag metal and Ti metal, and the specific types are not overly limited here.

[0078] Next, referring to FIG. 3 and FIG. 12 , step S9 is performed to form a heat dissipation metal block 700 on the second redistribution layer 220 , and the heat dissipation metal block 700 is vertically projected on the first silicon chip 410 .

[0079] Specifically, the heat dissipation metal block 700 preferably covers the heat source area of ​​the first silicon chip 410 along its vertical projection. The heat dissipation metal block 700 may be formed by, for example, electroplating or thermal bonding. The heat dissipation metal block 700 may include, for example, a Cu metal block, a Ni metal block, or an Au metal block. The preparation method, material, and morphology of the heat dissipation metal block 700 are not limited herein.

[0080] Next, referring to Figures 3 and 12, step S10 is performed to provide a second chip 420, and the second chip 420 is flip-chip bonded to the second redistribution layer 220. The second chip 420 is electrically connected to the second redistribution layer 220, and the heat dissipation metal block 700 is located below the second chip 420.

[0081] Specifically, the second chip 420 may include a silicon chip such as a DDR chip, and the type of the second chip 420 is not particularly limited herein.

[0082] Among them, the front side of the second chip 420 has a second metal bump 820, such as a solder ball bump, a copper pillar bump, etc. After the second chip 420 is bonded in a flip-chip manner, one end of the second metal bump 820 is electrically connected to the solder pad (not shown) of the second chip 420, and the other end of the second metal bump 820 is electrically connected to the second rewiring layer 220. The back side of the second chip 420 is away from the second rewiring layer 220.

[0083] After bonding the second chip 420, a second underfill layer 520 may be formed between the second chip 420 and the second redistribution layer 220, such as by dispensing. The second underfill layer 520 serves as a protective layer between the second chip 420 and the second redistribution layer 220. The material of the second underfill layer 520 is not particularly limited.

[0084] Next, referring to FIG. 3 and FIG. 12 , step S11 is performed to form a second packaging layer 620 . The second packaging layer 620 covers the second re-distribution layer 220 , the heat dissipation metal block 700 , and the second chip 420 .

[0085] Specifically, the method of forming the second packaging layer 620 may include but is not limited to compression molding, transfer molding and spin coating, and the material of the second packaging layer 620 may include but is not limited to epoxy resin and polyamide. There is no excessive restriction on the material and preparation method of the second packaging layer 620.

[0086] Next, referring to FIG. 3 and FIG. 13 , step S12 is performed to remove the support substrate 100 to expose the first redistribution layer 210 , and step S13 is performed to form metal bumps on the first redistribution layer 210 .

[0087] Specifically, the metal bump is a third metal bump 830, and the third metal bump 830 is electrically connected to the first redistribution layer 210. The third metal bump 830 may include, for example, a solder ball bump, a copper pillar bump, etc., and the specific type and material of the third metal bump 830 are not excessively limited herein.

[0088] Furthermore, when the semiconductor packaging structure is prepared at the wafer level, such as 6 inches, 8 inches, 12 inches, etc., after performing step 14 to form the metal bumps, a cutting step, such as mechanical cutting, laser cutting, etc., can also be performed to prepare a single semiconductor packaging structure.

[0089] In summary, the method for preparing a semiconductor packaging structure that avoids Cu diffusion of the present invention retains the packaging layer located on the Cu metal pillars when grinding and thinning the first silicon chip, grinds only the composite interface of the packaging layer / silicon chip, and then exposes the Cu metal pillars by patterning the packaging layer for electrical connection. Therefore, during thinning, Cu metal residue can be prevented from remaining on the first silicon chip, thereby avoiding simultaneous grinding of Cu / Si and preventing Cu metal diffusion contamination.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor package structure to avoid Cu diffusion, characterized in that, The method includes the following steps: Provide a support substrate; Form a first redistribution layer on the support substrate; Form Cu metal pillars on the first redistribution layer, and the Cu metal pillars are electrically connected to the first redistribution layer; Provide a first silicon chip, and bond the first silicon chip to the first redistribution layer in a flip-chip manner, and the first silicon chip is electrically connected to the first redistribution layer; Form a first encapsulation layer, and the first encapsulation layer covers the first redistribution layer, the Cu metal pillars and the first silicon chip; Perform grinding to thin the first silicon chip. After grinding, the first encapsulation layer exposes the first silicon chip and covers the Cu metal pillars; Pattern the first encapsulation layer to form a groove exposing the Cu metal pillars in the first encapsulation layer; Form a second redistribution layer on the first encapsulation layer, and the second redistribution layer is electrically connected to the Cu metal pillars; Form a heat dissipation metal block on the second redistribution layer, and the vertical projection of the heat dissipation metal block is located on the first silicon chip; Provide a second chip, and bond the second chip to the second redistribution layer in a flip-chip manner. The second chip is electrically connected to the second redistribution layer, and the heat dissipation metal block is located below the second chip; Form a second encapsulation layer, and the second encapsulation layer covers the second redistribution layer, the heat dissipation metal block and the second chip; Remove the support substrate to expose the first redistribution layer; Form metal bumps on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.

2. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The method for patterning the first encapsulation layer to form the groove includes a laser drilling method, an etching method or a mechanical drilling method.

3. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The method for forming the Cu metal pillars includes an electroplating method.

4. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The thickness of the first encapsulation layer on the Cu metal pillars before grinding is greater than 15 μm.

5. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, characterized in that: The method for forming the heat dissipation metal block includes an electroplating method or a thermal conductive bonding method.

6. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1, wherein: The heat dissipation metal block includes a Cu metal block, a Ni metal block or an Au metal block.

7. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The metal wiring in the second redistribution layer includes a metal seed diffusion barrier layer, and the metal seed diffusion barrier layer is in direct contact with the first silicon chip.

8. The manufacturing method of the semiconductor package structure for avoiding Cu diffusion according to claim 7, wherein: The material of the metal seed diffusion barrier layer includes one or a combination of Ni metal, Au metal, Sn metal, Ag metal and Ti metal.

9. The method for manufacturing a semiconductor package structure for preventing Cu diffusion according to claim 1, wherein: The vertical projection of the heat dissipation metal block covers the heat source area of the first silicon chip.

10. The method for manufacturing a semiconductor package structure for avoiding Cu diffusion according to claim 1, wherein: The semiconductor package structure is a wafer-level semiconductor package structure. After forming the metal bumps, it further includes a step of dicing.

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