Display device

Abstract

Provided is a novel display device. A first element layer includes a display drive unit and an image data processing unit. A second element layer includes a display unit and a storage unit. The display unit includes a pixel circuit. The storage unit includes a storage circuit. The image data processing unit has the function of generating second image data by performing a product-sum operation, based on a convolutional neural network, on first image data input to the image data processing unit. The display drive unit receives the second image data as input and has the function of driving the pixel circuit to perform display, based on the second image data, in the display unit. Weight data used in the convolutional neural network is data stored in the storage circuit.

Description

display device

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, there has been a demand for higher-definition display devices. Devices requiring high-definition display devices include, for example, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR), which have been actively developed in recent years. VR, AR, SR, and MR are also collectively referred to as xR.

[0004] Display devices used in xR devices are required to be compact as well as high-definition. Examples of display devices for xR include light-emitting devices equipped with light-emitting elements such as organic electroluminescence (EL) elements and light-emitting diodes (LEDs).

[0005] For display devices used in xR devices, configurations have been proposed that are high-definition, compact, and multifunctional. For example, Patent Documents 1 and 2 disclose configurations in which, in addition to configurations related to image display such as pixel circuits and display drive circuits, functional circuits having functions for performing arithmetic processing such as image processing are provided integrally with the pixel circuits, display drive circuits, etc.

[0006] International Publication No. 2022 / 118141 International Publication No. 2022 / 118151

[0007] Display devices used in xR devices are required to display high-resolution images with a large number of pixels and at a high frame rate in order to mitigate problems related to poor display quality, such as VR sickness and the screen door effect. The bus width of the bus used to send and receive image data to the display device is limited. Therefore, while increasing the data transfer rate for sending and receiving image data is effective in meeting the display specifications, this comes at a trade-off with increased power consumption.

[0008] In order to realize transmission and reception of image data that meets display specifications without increasing the data transfer rate, it is effective to use an image data upconversion technique within a display device, which includes AI (Artificial Intelligence; hereinafter referred to as AI) techniques such as a Convolutional Neural Network (hereinafter referred to as CNN).

[0009] The number of weight data (parameters) used in the CNN required for image data upconversion technology is extremely large. If the area for arranging the storage circuit for storing the weight data is small, there is a risk that the necessary weight data cannot be stored.

[0010] Furthermore, it is preferable that image data processed by up-conversion technology be subjected to fine adjustments in the output image or corrections for image quality correction. However, in a configuration in which the weight data used in the CNN is updated all at once to correct the image data, it may take time to update the necessary weight data.

[0011] An object of one embodiment of the present invention is to provide a miniaturized display device.An object of one embodiment of the present invention is to provide a high-resolution display device.An object of one embodiment of the present invention is to provide a highly convenient display device.An object of one embodiment of the present invention is to provide a novel display device.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One aspect of the present invention is a display device including a first element layer and a second element layer over the first element layer, wherein the first element layer includes a first transistor, and the first transistor includes a semiconductor layer having a channel formation region including silicon. The second element layer includes a second transistor, and the second transistor includes a semiconductor layer having a channel formation region including a metal oxide. The first element layer is provided with a display driver and an image data processor. The second element layer is provided with a display unit and a memory unit. The display unit includes a pixel circuit. The memory unit includes a memory circuit. The image data processor has a function of performing product-sum calculation processing using a convolutional neural network to generate second image data from the first image data. The display driver has a function of driving the pixel circuit so that the display unit can display based on the input second image data. Weight data used in the convolutional neural network is data stored in the memory circuit.

[0014] One aspect of the present invention is a display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, and the first transistor has a semiconductor layer having a channel formation region containing silicon. The second element layer has a second transistor, and the second transistor has a semiconductor layer having a channel formation region containing metal oxide. The first element layer is provided with a display driver and an image data processor. The second element layer is provided with a display unit and a memory unit. The display unit has a pixel circuit. The memory unit has a memory circuit. The image data processor has a function of performing first arithmetic processing and second arithmetic processing to generate second image data from image data. The first arithmetic processing performs a product-sum calculation using first weight data. The second arithmetic processing performs a product-sum calculation using second weight data. The display driver has a function of driving the pixel circuit so that the display unit can display based on the input second image data.

[0015] One embodiment of the present invention is a display device including a first element layer, a second element layer on the first element layer, and a third element layer on the second element layer, in which the first element layer includes a first transistor, and a semiconductor layer having a channel formation region includes silicon; the second element layer and the third element layer each include a second transistor, and the semiconductor layer having a channel formation region includes metal oxide; the first element layer includes a display driver unit and an image data processor; the second element layer includes a memory unit, and the memory unit includes a memory circuit; and the third element layer includes a second transistor. The child layer has a display unit, the display unit has a pixel circuit, the image data processing unit has a function of performing first arithmetic processing and second arithmetic processing and generating second image data from the first image data, the first arithmetic processing performs a product-sum calculation using first weight data, and the second arithmetic processing performs a product-sum calculation using second weight data, the display drive unit has a function of driving the pixel circuit so that display based on the input second image data can be performed on the display unit, and each of the first weight data and the second weight data is data stored in a memory circuit, which is a display device.

[0016] In one aspect of the present invention, the display device is preferably such that the number of parameters of the second weighting data is smaller than the number of parameters of the first weighting data.

[0017] In one aspect of the present invention, the display device preferably performs the first arithmetic process and the second arithmetic process by performing a product-sum operation by convolution of input data, nonlinear mapping of the convolved data, and deconvolution of the data to which the nonlinear mapping has been applied.

[0018] In one embodiment of the present invention, the display device is preferably such that the display driver is provided in a region overlapping with the display.

[0019] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0020] According to one embodiment of the present invention, a miniaturized display device can be provided. Alternatively, according to one embodiment of the present invention, a high-resolution display device can be provided. Alternatively, according to one embodiment of the present invention, a highly convenient display device can be provided. Alternatively, according to one embodiment of the present invention, a novel display device can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0022] FIGS. 1A and 1B are block diagrams illustrating an example of the configuration of a display device. FIG. 2 is a schematic diagram illustrating an example of the configuration of a display device. FIG. 3 is a block diagram illustrating an example of the configuration of a display device. FIG. 4 is a block diagram illustrating an example of the configuration of a display device. FIGS. 5A and 5B are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 6A to 6C are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 7A to 7C are block diagrams illustrating an example of the configuration of a display device. FIGS. 8A to 8C are schematic diagrams illustrating an example of the configuration of a display device. FIGS. 9A to 9C are schematic diagrams illustrating an example of the configuration of a display device. FIGS. 10A to 10C are schematic diagrams illustrating an example of the configuration of a display device. FIGS. 11A to 11C are schematic diagrams illustrating an example of the configuration of a display device. FIG. 12 is a schematic diagram illustrating an example of the configuration of a display device. FIGS. 13A to 13C are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 14A to 14C are schematic diagrams illustrating an example of the configuration of a display device. FIGS. 15A to 15D are circuit diagrams illustrating an example of the configuration of a display device. 16A to 16D are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 17A and 17B are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 18A and 18B are block diagrams illustrating an example of the configuration of a display device. FIG. 19 is a schematic diagram illustrating an example of the configuration of a display device. FIGS. 20A and 20B are schematic diagrams illustrating an example of the configuration of a display device. FIG. 21 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIG. 22 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIGS. 23A to 23E are schematic diagrams illustrating an example of an electronic device.

[0023] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0024] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0025] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0026] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0027] Embodiment 1 A display device according to one embodiment of the present invention will be described.

[0028] 1A and 2 are perspective views of a display device 100 according to one embodiment of the present invention. FIG. 1B is a block diagram illustrating a configuration of the display device 100. The display device 100 includes an element layer 30 over an element layer 20 and a sealing substrate 40 over the element layer 30. The element layer 30 includes a memory unit 71 and a display unit 31, and a light-emitting element layer 60 is provided between the sealing substrate 40 and the display unit 31. In FIG. 2, the element layer 20, the element layer 30, the light-emitting element layer 60, the sealing substrate 40, and the like are shown separated from each other to make the configuration of the display device 100 easier to understand.

[0029] The element layer 20 includes a display driver 22 , an image data processor 70 , and a terminal section 29 .

[0030] The display driver 22 and the image data processor 70 are preferably configured using Si CMOS, i.e., transistors (Si transistors) having silicon in their channel formation regions. In other words, the element layer 20 is an element layer having Si transistors. By configuring the display driver 22 and the image data processor 70 using Si transistors, circuits such as the display driver 22 and the image data processor 70, which are preferably highly integrated, can be provided in the element layer 20. Furthermore, by configuring the element layer 20 as an element layer having Si transistors, it is possible to configure the element layer 20 to include various functional circuits such as sensor circuits, communication circuits, and control circuits. Furthermore, by configuring the display driver 22 and the image data processor 70 to be arranged in the same layer, the image data processor 70 can be arranged in an area of ​​the element layer 20 where the display driver 22 is not arranged.

[0031] For the Si transistor, it is preferable to use silicon with high crystallinity, such as single crystal silicon or polycrystalline silicon, since high field effect mobility can be achieved and higher speed operation is possible.

[0032] The element layer 30 is a layer including an OS transistor, that is, a transistor including an oxide semiconductor in a channel formation region. With this structure, the memory portion 71 including the OS transistor and the display portion 31 can be stacked with the element layer 20.

[0033] An OS transistor has a characteristic of having a very low off-state current. Therefore, when an OS transistor is used as a transistor provided in a pixel circuit, written data can be held for a long period of time. Furthermore, when an OS transistor is used as a transistor provided in a memory circuit (also referred to as a memory cell), written data can be held for a long period of time.

[0034] Examples of metal oxides that can be used in OS transistors include Zn oxide, Zn—Sn oxide, Ga—Sn oxide, In—Ga oxide, In—Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for use in OS transistors because they can provide transistors with excellent electrical characteristics, such as field-effect mobility, by adjusting the ratio of elements. The oxide containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0035] The image data processing unit 70 has a function of processing image data, such as upconverting image data (input data) supplied from outside the display device. The image data (output data) upconverted by the image data processing unit 70 is output to the display driver 22. This configuration can reduce the impact of bus width limitations compared to a configuration in which image data is upconverted in a circuit external to the display device and then supplied to the display device. Furthermore, since the connection between the image data processing unit 70 and the display driver 22 is made via wiring within the same element layer 20, there is no impact of bus width limitations. As a result, the data transfer rate from the image data processing unit 70 to the display driver 22 can be increased, and image data can be supplied to a high-definition display unit without delay.

[0036] Image data upconversion refers to a process of increasing the resolution of an image displayed using original image data. For example, this is image processing that converts image data written to 3 rows and 3 columns (3x3) of pixels into image data written to 6x6 pixels. The output data output by this image processing is image data with a larger data volume than the original input data.

[0037] The up-conversion is preferably configured to perform image processing using a CNN-based product-sum operation (also known as convolution operation). Although up-conversion using convolution operation requires more computation than image processing based on algorithms such as bicubic interpolation or Lanczos interpolation, it can generate images that are excellent in image processing of texture surfaces and contours.

[0038] The image data processing unit 70 is connected to a storage unit 71 included in the element layer 30. The storage unit 71 includes a plurality of storage circuits 72. The storage circuits 72 function as storage elements (memory cells). The storage unit 71 including the storage circuits 72 stores weight data used for processing image data in the image data processing unit 70.

[0039] Weight data is data corresponding to a filter in a convolutional neural network, or to the elements of the kernel that constitutes the filter. Weight data is the weight coefficient of the filter. The weight coefficient is a parameter optimized through learning. Increasing the number of weight data increases the amount of information in the filter, allowing the use of a filter with more optimized parameters. A filter with multiple weight data performs a product-sum operation involving multiplication and addition with the input data, resulting in convolved data. The convolved data makes it possible to extract local features from the original data and upconvert image data according to those features.

[0040] The memory circuit 72 includes an OS transistor. The OS transistor has a low off-state current. Therefore, by turning the OS transistor off (off), charge corresponding to the written data potential can be held. By connecting one of the source and drain of the OS transistor to the gate of the Si transistor, the charge can be held by utilizing the gate capacitance of the Si transistor.

[0041] By configuring the memory circuit 72 included in the memory unit 71 to hold charge corresponding to the data potential, the memory circuit 72 can be arranged in a region where the pixel circuit 51 of the display unit 31 is provided, as shown in Figure 2. In the display device 100 illustrated in Figure 2, the display unit 31 and the memory unit 71 are provided in the element layer 30, and the memory circuit 72 included in the memory unit 71 is arranged in the pixel circuit 51 of the pixel 50. This configuration increases the degree of freedom in the layout of OS transistors.

[0042] Since metal oxides used in OS transistors are n-type (n-channel) metal oxides, such as In—Ga—Zn oxide, a complementary metal oxide semiconductor (CMOS) circuit can be formed by combining an OS transistor with a Si transistor to form a memory cell. Therefore, compared to a memory cell formed only with n-channel transistors, a circuit having both high driving capability due to the use of Si transistors and low power consumption due to the low off-state current of an OS transistor can be realized.

[0043] Furthermore, the storage unit 71 may be a nonvolatile oxide semiconductor random access memory (NOSRAM) or a dynamic oxide semiconductor random access memory (DOSRAM).

[0044] "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." NOSRAM refers to a memory in which the memory cell is a two-transistor (2T) or three-transistor (3T) gain cell, and the access transistor is an OS transistor. The current that flows between the source and drain in the off state, that is, the leakage current, is extremely small. NOSRAM allows the stored data to be read without destroying it (non-destructive readout).

[0045] "DOSRAM (registered trademark)" is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. Like NOSRAM, DOSRAM is a memory that utilizes the low off-state current of OS transistors.

[0046] The pixel circuit 51 included in the display unit 31 includes an OS transistor similar to the OS transistor included in the memory circuit 72 included in the memory unit 71. With this configuration, the display unit 31 and the memory unit 71 can be arranged in the element layer 30. By arranging the memory unit 71 and the display unit 31 in the same layer, the memory unit 71 can be arranged in a region of the element layer 30 where the display unit 31 is not arranged.

[0047] The display driver 22 is connected to the display section 31 included in the element layer 30 and has a function of supplying image data to the display section 31. The display driver 22 can use various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, or a logic circuit. As shown in FIG. 2 , a light emitting element layer 60 is provided over the display section 31 included in the element layer 30. The light emitting element layer 60 includes a plurality of light emitting elements, and the light emission brightness is controlled by a pixel circuit 51 provided in the display section 31. Therefore, the light emitting element layer 60 can also be considered as part of the display section 31.

[0048] The display unit 31 includes pixels 50 each having a plurality of pixel circuits 51. The pixels 50 each include a pixel circuit 51 and a light-emitting element (not shown) provided in a light-emitting element layer 60 on the pixel circuit 51. The pixel circuit 51 corresponds to a pixel circuit included in a sub-pixel for displaying color. Details of the pixel circuit 51 and the light-emitting element will be described later.

[0049] Each of the three subpixels controls the amount of light emitted, for example, red light, green light, or blue light. The color of light controlled by each of the three subpixels is not limited to a combination of red (R), green (G), and blue (B), but may also be cyan (C), magenta (M), and yellow (Y). The areas of the three subpixels do not have to be the same. If the luminous efficiency and reliability differ depending on the luminous color, the area of ​​the subpixel may be varied for each luminous color. Four subpixels may be combined to function as a single pixel. For example, a subpixel controlling white light may be added to three subpixels controlling red, green, and blue light, respectively. Adding a subpixel controlling white light can increase the luminance of the display area. A subpixel controlling yellow light may be added to three subpixels controlling red, green, and blue light, respectively. A subpixel controlling white light may be added to three subpixels controlling cyan, magenta, and yellow light, respectively.

[0050] By increasing the number of sub-pixels that function as one pixel and by appropriately combining sub-pixels that control red, green, blue, cyan, magenta, and yellow light, it is possible to improve the reproducibility of intermediate tones, and therefore color reproducibility.

[0051] An FPC (flexible printed circuit) or the like is connected to the terminal portion 29. Therefore, the element layer 30 and the sealing substrate 40 are not formed in the area overlapping with the terminal portion 29.

[0052] 2, the storage unit 71 is provided in the region where the display unit 31 is provided. With this configuration, the storage unit 71 can be arranged so as to fill the region of the element layer 30 where the display unit 31 is not provided. Therefore, the storage capacity can be increased by arranging the storage unit 71 without reducing the area of ​​the display unit 31 or otherwise impairing the display quality.

[0053] In one embodiment of the present invention, an image data processing unit capable of performing convolution calculations is provided in an element layer where a display driver unit is provided. With this configuration, image data input to a display device can be output to the display driver unit as image data upconverted within the display device. Therefore, even if a high-resolution display device with a large number of pixels has a limited bus width for transmitting and receiving image data, the amount of image data transferred to the display device can be reduced and the amount of image data transferred to the display driver unit can be increased, thereby enabling an image with excellent display quality to be displayed.

[0054] In one embodiment of the present invention, an element layer including a memory circuit is disposed over an element layer including an image data processing unit, thereby integrating a circuit for performing arithmetic processing and a circuit for storing weight data. Since OS transistors can be used as transistors in the memory circuit as well as in the pixel circuit, a memory circuit for storing weight data for performing convolution processing can be efficiently disposed in the element layer including the display portion. Therefore, the number of weight data required for CNN, which is necessary for image data upconversion technology, can be secured.

[0055] <Configuration Example 1 of Image Data Processing Unit> Fig. 3 is a block diagram illustrating a configuration example of the image data processing unit 70, the display drive unit 22, and the display unit 31. In Fig. 3, the image data processing unit 70 has an LVDS (Low Voltage Differential Signaling) circuit 68, a serial-parallel conversion circuit 69, and a convolution operation circuit 80. The convolution operation circuit 80 has a plurality of operation circuits corresponding to a plurality of convolution layers 73_1 to 73_N (N is an integer).

[0056] In FIG. 3, the data input to the convolution circuit 80 is data D ＩＮ The data output from the convolution circuit 80 is shown as data D ＯＵＴ The data D ＩＮis data based on image data supplied from outside the display device 100 via the terminal unit 29. ＯＵＴ is image data supplied to the source line driving circuit 33 included in the display driving unit 22 .

[0057] The LVDS circuit 68 is a circuit for receiving data based on LVDS, a signal transmission means. LVDS is a communication technology that allows for relatively high-speed operation, low power consumption due to small-amplitude signals, a reduction in the number of wirings, and mitigation of the effects of noise. Receiving data via LVDS from outside the display device 100 can reduce the effects of noise such as EMI (Electro-Magnetic Interference).

[0058] The serial-parallel conversion circuit 69 is connected to the LVDS circuit 68. The serial-parallel conversion circuit 69 converts the single-ended signal from the LVDS circuit 68 into a parallel signal and outputs the data D to the convolution calculation circuit 80. ＩＮ can be supplied.

[0059] The convolution operation circuit 80 is provided with logic circuits for performing product-sum operation processing of input data and weight data in a plurality of convolution layers 73_1 to 73_N (N is an integer). For example, in the convolution layer 73_1, data D ＩＮ The data obtained in the convolutional layer 73_1 can be used as input data, and the data stored in the storage unit 71 can be used as weight data to perform a product-sum operation. For example, in the convolutional layer 73_2, the data obtained in the convolutional layer 73_1 can be used as input data, and the data stored in the storage unit 71 can be used as weight data to perform a product-sum operation. ＩＮ Data D obtained by arithmetic processing ＯＵＴ can be image data with an increased amount of data based on the original image data.

[0060] As shown in FIG. 3 , an image data processing unit 70 of one embodiment of the present invention includes a convolution operation circuit 80 having multiple convolution layers. Data input and output to the multiple convolution layers can be transmitted in one direction, which is called feedforward image processing. The multipliers and adders provided in the multiple convolution layers have circuit configurations such as combinational circuits and sequential circuits. In the multiplier, a memory circuit that inputs weight data can be arranged as a different element layer, so that a circuit configuration including the multiplier and the memory circuit can be designed as a single unit.

[0061] In one embodiment of the present invention, the storage capacity of the storage unit 71 can be increased, so that the weight data required for the plurality of convolution layers 73_1 to 73_N can be stored. Unlike a storage circuit including Si transistors such as a static RAM (SRAM), the storage unit 71 can also be provided in an element layer 30 that is different from the element layer 20. In addition, while an SRAM generally includes six transistors as part of a storage circuit, a circuit including a combination of OS transistors and Si transistors can increase the amount of data to be stored, so that the weight data required for the plurality of convolution layers 73_1 to 73_N can be stored.

[0062] By including the storage unit 71 that can store a large amount of weight data and the convolution circuit 80, the display device of one embodiment of the present invention can perform image processing to upconvert input image data. In this case, the amount of data transferred from the outside to the display device 100 can be reduced. Furthermore, the amount of data transferred to the display driver 22 can be increased.

[0063] The display drive unit 22 has a gate line drive circuit 32 and a source line drive circuit 33. The circuit included in the gate line drive circuit 32 functions as, for example, a scanning line drive circuit (gate line drive circuit). The circuit included in the source line drive circuit 33 functions as, for example, a signal line drive circuit (source line drive circuit). The gate line drive circuit 32 is a circuit that drives gate lines connected to pixel circuits 51, which will be described later. The source line drive circuit 33 is a circuit that drives source lines connected to pixel circuits 51, which will be described later.

[0064] The display unit 31 has a plurality of pixel circuits 51. A memory circuit 52 (not shown) can be provided in the region of the display unit 31 where the pixel circuits 51 are provided. The pixel circuits 51 can be formed using transistors, capacitors, or the like.

[0065] FIG. 4 shows the data D output from the image data processing unit 70. ＯＵＴ 4 is a block diagram illustrating an example of the configuration of a source line driving circuit 33 included in the display driving unit 22, to which a signal is supplied. In FIG. 4, the source line driving circuit 33 includes a line memory 41, a level shifter 42, a pass transistor logic 43, a digital-to-analog conversion circuit 44, and an amplifier circuit 45.

[0066] 4, the display driver 22 according to one embodiment of the present invention includes circuits such as a line memory 41, a level shifter 42, a pass transistor logic 43, a digital-to-analog conversion circuit 44, and an amplifier circuit 45. Data input to and output from each circuit can be transmitted in one direction, that is, subjected to so-called feedforward image processing.

[0067] The line memory 41 stores the up-converted data D ＯＵＴ and transfers it to the level shifter 42 as a set of data. For example, ＯＵＴ are successively held, and are transferred to the level shifter 42 at the timing when data for one row in the display unit 31 is completed.

[0068] The level shifter 42 is a circuit for increasing the signal level of the data output from the line memory 41, i.e., the amplitude voltage of the signal. This configuration makes it possible to control the on / off state of the transistors in the subsequent pass transistor logic 43.

[0069] The pass transistor logic 43 and the digital-to-analog conversion circuit 44 are circuits that convert digital data into analog data, and the amplifier circuit 45 is a circuit that amplifies the analog data.

[0070] Note that a description of the gate line driving circuit 32 included in the display driving unit 22 will be omitted from the drawings. The gate line driving circuit 32 is a timing signal that controls the conduction state of a transistor whose gate is connected to a gate line in a pixel circuit.

[0071] 5A shows an example of a circuit configuration for performing a sum-of-products operation process in multiple convolution layers 73_1 to 73_N included in the convolution operation circuit 80. Fig. 5A shows a block diagram of a circuit configuration for performing a sum-of-products operation on data for a combination of 3x3 input data and filters, that is, a combination of nine input data and nine weight data, and for performing pooling on the data obtained by the sum-of-products operation.

[0072] 5A includes multipliers 74_1 to 74_9 to which input data in1 to in9 and weight data w1 to w9 are input, registers 75_1 to 75_9 that hold the outputs of the multipliers 74_1 to 74_9, an adder 76 that adds together the outputs of the registers 75_1 to 75_9, and a pooling circuit 77 that performs pooling processing of the outputs of the adder 76. An output signal po of the pooling circuit 77 is an output signal of a block that performs product-sum calculation processing.

[0073] 5B shows an example of the circuit configuration of the multiplier 74 applicable to the multipliers 74_1 to 74_9. The multiplier 74 has an AND circuit 78 and an adder 79. The multiplier 74 shown in FIG. 5B shows input data in1_0 to in1_7 as 8-bit input data and weight data w1_0 to w1_7 (w1_0 to w1_2 are shown) as 8-bit weight data. Note that the "0" input to the adder 79 is an input for carrying over a digit that occurs when data is added.

[0074] It is preferable that a memory for storing data is provided between the circuits performing the sum-of-products operation shown in Fig. 5A, for example, between the adder and the pooling circuit, so that the operation can be performed at a predetermined timing.

[0075] 6A shows a configuration example of an AND circuit 78 in which a memory circuit 72 can be provided by using OS transistors. The AND circuit 78 includes transistors OS1, OS2, PS1, PS2, NS1, and NS2, and capacitors C1 and C2. The transistors and capacitors are connected to the terminals w, in, sw, and out, a wiring that supplies the power supply potential VDD, and a wiring that supplies the power supply potential VSS, as shown in FIG.

[0076] The transistors OS1 and OS2 are n-channel OS transistors. The transistors PS1 and PS2 are p-channel Si transistors. The transistors NS1 and NS2 are n-channel Si transistors. The terminal w is a terminal that supplies weight data. The terminal in is a terminal that supplies input data. The terminal sw is a terminal that supplies a signal that controls updating of the weight data. The terminal out is a terminal that outputs output data.

[0077] The weight data can be stored in the memory circuit 72 connected to the AND circuit 78 by switching the OS transistor to a conductive state and then to a non-conductive state. The memory circuit 72 is provided as shown in FIG. 6B as an example. The memory circuit 72 can also be considered as part of the AND circuit 78 provided in a different element layer. The memory circuit 72 can store data by accumulating charge in the capacitor C1 and in gate capacitance formed between the gate of the transistor and the semiconductor layer depending on whether the transistor OS1 is conductive or non-conductive. In the memory circuit 72, the current flowing through the transistors OS1 and OS2 is extremely small, and once a charge is stored, it can be continuously retained. This significantly reduces the power consumption required to store data associated with arithmetic processing. Note that while FIG. 6B illustrates the transistor OS1, capacitor C1, and transistor PS1 as an example of the memory circuit 72, the transistor OS2, capacitor C2, and transistor NS2 can also function as the memory circuit 72.

[0078] The weight data is changed infrequently. Using OS transistors, it is possible to retain a charge corresponding to the data for a long period of time. Therefore, the weight data is not updated while the data is being processed. Therefore, in the image data processing unit 70 having the multiplier 74, fluctuations in the output data due to updates to the weight data can be eliminated.

[0079] Figure 6C is a diagram showing a schematic hierarchical relationship between the element layer 20 having transistors PS1, PS2, NS1 and NS2, the element layer 30 having transistors OS1, OS2, capacitors C1 and C2, and the light-emitting element layer 60 having the light-emitting element 61 in the AND circuit 78 shown in Figure 6A.

[0080] In the configuration example shown in FIG. 6C , the wiring connecting the transistors OS1, OS2, capacitors C1, and C2 that constitute the memory circuit 72 with the transistors PS2, NS1, and NS2 can be shortened, thereby reducing the wiring resistance of the wiring. Furthermore, the parasitic capacitance of the wiring can be reduced. Therefore, data can be written at high speed, allowing weight data to be updated at high speed. This ensures a sufficient update period even when the number of memory circuits 72 is increased, thereby increasing the memory density of the memory unit 71.

[0081] 7A is a block diagram illustrating a convolution circuit 80A that can be applied to the above-described convolution circuit 80. The convolution circuit 80A, like the convolution circuit 80, receives data D ＩＮ Data D ＯＵＴ The convolution circuit 80A outputs the data D ＩＮ The image data is up-converted to data D ＯＵＴ The image data can be output as:

[0082] The convolution operation circuit 80A has a pre-processing layer 81, an arithmetic processing layer 82, an arithmetic processing layer 83, an arithmetic processing layer 84, and a post-processing layer 85. In the following description, data input to the arithmetic processing layer 82 is referred to as D ８２ The data input to the arithmetic processing layer 83 is expressed as D ８３ The data input to the arithmetic processing layer 84 is expressed as D ８４ The data input to the post-processing layer 85 is expressed as D ８５ It may be expressed as:

[0083] The pre-processing layer 81 processes the data D ＩＮ The calculation processing layer 82 performs a convolution calculation to generate large data size data. ＩＮThe calculation processing layer 83 converts low-resolution features into high-resolution features using nonlinear mapping. The calculation processing layer 84 converts large data into data that reflects the features of the data by performing deconvolution. The post-processing layer 85 averages data that has been duplicated through data processing.

[0084] 7B is a block diagram illustrating an example of the configuration of an arithmetic processing layer 90 applicable to the arithmetic processing layers 82 to 84. The arithmetic processing layer 90 performs arithmetic processing on data provided to an input IN in accordance with weight data, and outputs the result to an output OUT.

[0085] 7C is a diagram illustrating a specific example configuration of the arithmetic processing layer 90. The arithmetic processing layer 90 has a multiplier 91, a multiplier 92, and an adder 93. The multiplier 92 in the arithmetic processing layer 90 can have the circuit configuration of the multiplier 74 having the AND circuit 78 described above. Note that FIG. 7C illustrates an example in which pooling processing is not performed. Therefore, when applying the configuration of FIG. 5A to FIG. 7C, it is preferable to omit the pooling circuit 77.

[0086] Since the AND circuit 78 described above has an OS transistor and can hold a charge corresponding to weight data, stacking it with an element layer having a Si transistor allows a memory cell to be held in a combinational circuit, thereby reducing the power consumption required to hold data associated with arithmetic processing.

[0087] The multiplier 91 in the arithmetic processing layer 90 performs up-conversion based on a convolution operation. The multiplier 92 in the arithmetic processing layer 90 performs up-conversion based on a convolution operation for fine adjustment that cannot be compensated for by the multiplier 91. The adder 93 adds together the data obtained by the respective multipliers (multiplier 91, multiplier 92).

[0088] The multiplier 91 performs a multiply-and-accumulate operation with a larger number of filters or kernels than the multiplier 92. Therefore, the number of weight data (first weight data) used by the multiplier 91 is larger than the number of weight data (second weight data) used by the multiplier 92. The multiplier 91 is sometimes called a main multiplier. The number of weight data is also called the number of parameters.

[0089] The multiplier 92 performs a multiply-and-accumulate operation with a smaller number of filters or kernels than the multiplier 91. For example, data is generated via a layer that expresses data locality. Therefore, the number of weight data used by the multiplier 92 is smaller than the number of weight data used by the multiplier 92. The multiplier 92 is sometimes called a fine-tuning multiplier.

[0090] The arithmetic processing layer 90, which has a multiplier 91 serving as a main multiplier and a multiplier 92 serving as a detail adjustment multiplier, can up-convert image data using convolutional calculation processing, as well as perform fine adjustments to the image data or corrections for image quality correction. The detail adjustments or image quality corrections to the image data are performed by updating the weight data of the multiplier 92. Because the number of weight data used by the multiplier 92 is smaller than the number of weight data used by the multiplier 91, the increase in power consumption and the rewriting period associated with data updating can be suppressed.

[0091] 8A to 8C are diagrams illustrating specific examples of image data processing in the pre-processing layer 81. The pre-processing layer 81 has the function of holding calculation data to be output to the subsequent calculation processing layer 82, and sequentially outputting data that has been subjected to processing such as padding and stride.

[0092] In the pre-processing layer 81, for example, data D ＩＮ Consider the case where 2k (1920 x 1080) 8-bit data is input. When the pre-processing layer 81 outputs data with a stride of 1 and a filter of 3 x 3, the pre-processing layer 81 stores the 1st to 5760th data (3 rows). From the stored data, it sequentially sends out 3 x 3 data to be used for product-sum calculations in the subsequent arithmetic processing layer 82.

[0093] Data input to the pre-processing layer 81 is temporarily stored in the memory of the pre-processing layer 81. The pre-processing layer 81 sequentially transfers the data once the data to be used for the next process is ready. In the pre-processing layer 81, the filter moves to the next row when one row of data is output. In other words, the filter moves from rows 1 to 3 to rows 2 to 4. As a result, the data from rows 1 to 1920, which corresponds to the first row, is no longer needed. Therefore, the pre-processing layer 81 can store data from row 5761 onwards. In this case, if the memory capacity required to store the data stored in the pre-processing layer 81 is 64 kbits, it can handle data for product-sum operations in the subsequent arithmetic processing layer 82.

[0094] In the pre-processing layer 81, as shown in the schematic diagram of FIG. 8A, for example, the data D ＦＩＬ This data D ＦＩＬ The number attached to the data D ＩＮ When 10×10 8-bit data is input, the addresses are numbered from "00" to "99" (see FIG. 8B).

[0095] In the following explanation, as shown in Figures 8A and 8B, in diagrams where data is represented schematically by assigning numbers in the row direction, if the data is 8 bits, one square represents 24 bits (8 x 3 (RGB (red, green, blue))) of data.

[0096] Data D shown in FIG. ＦＩＬ It is preferable that data D is selected including the surrounding data. For example, as shown in FIG. ＦＩＬ When selecting the area (thick solid line), processing is performed to include peripheral information (thick dotted line). In other words, if the target data is 3x3 data, it is preferable to extract 5x5 data.

[0097] For data at the edges, it is preferable to process the data by padding it to fill the outer periphery. The 5x5 data selected in the pre-processing layer 81 is subjected to interpolation processing to add interpolated data COL as shown in Figure 8C. For example, in the case of linear interpolation processing, the interpolated data COL can be generated by performing a product-sum calculation of each data (with a constant weight of 0.5). By performing interpolation processing on the 5x5 data, it becomes 9x9 data. The data D to be processed next is ８２ As mentioned above, the 3×3 data D ＦＩＬ and data D ＦＩＬ 7×7 data including the data D ８２ can be output as 7x7x3 (RGB) data.

[0098] 9A to 9C are diagrams illustrating a specific example of data processing in the arithmetic processing layer 82 that performs convolutional arithmetic processing.

[0099] As described above, the multipliers in the arithmetic processing layer 90 applied to the arithmetic processing layer 82 include a main multiplier 91 and a detail adjustment multiplier 92, as shown in Fig. 7C. Fig. 9A shows data processing by the multiplier 91 shown in Fig. 7C in the arithmetic processing layer 82. Fig. 9B shows data processing by the multiplier 92 shown in Fig. 7C in the arithmetic processing layer 82. Fig. 9C shows data processing by the adder 93 shown in Fig. 7C in the arithmetic processing layer 82.

[0100] Data D input to the arithmetic processing layer 82 ８２ can be expressed as 7×7×3 (for RGB), that is, 1×147 data as shown in FIG. 9A. As an example, as shown in FIG. 9A, the multiplier 91 converts the 147×64 data into weight data W ８２＿９１ Used as data D ８２ and weight data W ８２＿９１ By multiplying with this, 1×64 data D ８２＿９１ get.

[0101] The multiplier 92 uses two filters. One is, as shown in FIG. 9B, an example of which is to use 147×2 data as weight data W ８２＿９２ＡAs another example, as shown in FIG. 9B, 2×64 data is used as weight data W ８２＿９２Ｂ Used as data D ８２ and W ８２＿９２Ａ and weight data W ８２＿９２Ｂ By multiplying with this, 1×64 data D ８２＿９２ get.

[0102] In the adder 93, as shown in FIG. 9C, the 1×64 data D ８２＿９１ and 1x64 data D ８２＿９２ By adding and, 1x64 data D ８３ In this way, the arithmetic processing layer 82 can perform arithmetic processing involving product-sum operations by adding together data obtained by multipliers using different weight data.

[0103] 10A to 10C are diagrams illustrating a specific example of data processing in the arithmetic processing layer 83 that performs nonlinear mapping.

[0104] As described above, the multipliers in the arithmetic processing layer 90 applied to the arithmetic processing layer 83 include a main multiplier 91 and a detail adjustment multiplier 92, as shown in Fig. 7C. Fig. 10A shows data processing by the multiplier 91 shown in Fig. 7C in the arithmetic processing layer 83. Fig. 10B shows data processing by the multiplier 92 shown in Fig. 7C in the arithmetic processing layer 83. Fig. 10C shows data processing by the adder 93 shown in Fig. 7C in the arithmetic processing layer 83.

[0105] Data D input to the arithmetic processing layer 83 ８３ can be expressed as 1×64 data. As an example, the multiplier 91 converts 64×64 data into weight data W ８３＿９１ Used as data D ８３ and weight data W ８３＿９１ By multiplying with this, 1×64 data D ８３＿９１ get.

[0106] The multiplier 92 uses two filters. One is a filter that converts 64×2 data into weight data W as shown in FIG. 10B. ８３＿９２ＡThe other is to use 2×64 data as weight data W as shown in FIG. ８３＿９２Ｂ Used as data D ８３ and W ８３＿９２Ａ and weight data W ８３＿９２Ｂ By multiplying with this, 1×64 data D ８３＿９２ get.

[0107] In the adder 93, as shown in FIG. 10C, the 1×64 data D ８３＿９１ and 1x64 data D ８３＿９２ By adding and, 1x64 data D ８４ In this way, the arithmetic processing layer 83 can perform arithmetic processing involving product-sum operations by adding together data obtained by multipliers using different weight data.

[0108] 11A to 11C are diagrams illustrating a specific example of data processing in the arithmetic processing layer 84 that performs deconvolution (transposed convolution).

[0109] As described above, the multipliers in the arithmetic processing layer 90 applied to the arithmetic processing layer 84 include a main multiplier 91 and a detail adjustment multiplier 92, as shown in Fig. 7C. Fig. 11A shows data processing by the multiplier 91 shown in Fig. 7C in the arithmetic processing layer 84. Fig. 11B shows data processing by the multiplier 92 shown in Fig. 7C in the arithmetic processing layer 84. Fig. 11C shows data processing by the adder 93 shown in Fig. 7C in the arithmetic processing layer 84.

[0110] Data D input to the arithmetic processing layer 84 ８４ can be expressed as 1×64 data. As an example, the multiplier 91 converts 108×64 data into weight data W as shown in FIG. ８４＿９１ Used as data D ８４ and W ８４＿９１ By multiplying with this, 1×108 data D ８４＿９１ get.

[0111] The multiplier 92 uses two filters. One is a filter that converts 64×2 data into weight data W as shown in FIG. ８４＿９２ＡThe other is to use 2×108 data as weight data W as shown in FIG. ８４＿９２Ｂ Used as data D ８４ and W ８４＿９２Ａ and weight data W ８４＿９２Ｂ By multiplying with this, 1×108 data D ８４＿９２ get.

[0112] In the adder 93, as shown in FIG. 11C, the data D ８４＿９１ and 1 x 108 data D ８４＿９２ By adding and, 1 x 108 data D ８５ The original data D ＦＩＬ was 3x3x3 (RGB), while data D ８５ is up-converted to 6x6x3 (RGB) data.

[0113] FIG. 12 is a diagram illustrating a specific example of data processing in the post-processing layer 85, which performs processing to average out overlapping data resulting from data processing.

[0114] In the schematic diagram shown in FIG. 12, data D ＦＩＬ＿１ Data D ＦＩＬ＿３ and the data D input to the post-processing layer 85 ８５＿１ or D ８５＿３ As shown in FIG. ＦＩＬ＿１ Data D ＦＩＬ＿３ When selecting by sliding with a stride number of 1, data D ８５＿１ or D ８５＿３ For example, data D shown with hatching in FIG. ８５＿１ Area D ＯＶ＿１ And Data D ８５＿２ Area D ＯＶ＿２ In the post-processing layer 85, the overlapped area D ＯＶ＿１ and D ＯＶ＿２ are converted into one piece of data by averaging. The data can be averaged by performing a product-sum calculation on each piece of data (with a constant weight of 0.5).

[0115] While the above processing method is merely an example, it can be seen that the configuration of the convolution circuit 80A described with reference to Figures 7A to 12 is feedforward processing. Furthermore, the circuit configuration of the multiplier 74 having the AND circuit 78 described above can be applied to the arithmetic processing in each layer of the convolution circuit 80A. Since the AND circuit 78 described above has an OS transistor and can hold a charge corresponding to weight data, stacking it with an element layer having a Si transistor allows for a configuration in which a memory cell is held within a combinational circuit. As a result, the power consumption required to hold data associated with the arithmetic processing can be reduced.

[0116] The convolution circuit 80A also has an arithmetic processing layer 90, which includes a multiplier 91 as a main multiplier and a multiplier 92 as a detailed adjustment multiplier. The arithmetic processing layer 90 can up-convert image data using convolution processing, as well as perform fine adjustments of the image data or corrections for image quality correction. In this case, the amount of data required for updating the weight data can be reduced.

[0117] 13A is a schematic diagram illustrating the connection relationship between the display driver 22 and the display unit 31. As described above, in one aspect of the present invention, the display driver 22 and the display unit 31 are provided on different layers, so that the display unit 31 can be provided above the display driver 22.

[0118] As described above, the display drive unit 22 has a gate line drive circuit 32 and a source line drive circuit 33. The gate line drive circuit 32 is connected to pixel circuits 51 of the display unit 31 provided above via wiring GL (gate lines). The source line drive circuit 33 is connected to pixel circuits 51 of the display unit 31 provided above via wiring SL (source lines).

[0119] In the display driver 22, the gate line driver circuit 32 and the source line driver circuit 33 are each provided in a vertically long rectangle. In this case, in the element layer 20, the image data processor 70 is preferably arranged so as to fill the area where the display driver 22 is not provided, as shown in Fig. 13B. With this configuration, the image data processor 70 and the display driver 22 can be arranged in the element layer 20 without being separated from each other.

[0120] The schematic diagram shown in FIG. 13C is a configuration example in which a plurality of sets of display units 31, gate line driving circuits 32, and source line driving circuits 33 shown in FIG. 13A are arranged side by side. The display units 31, gate line driving circuits 32, and source line driving circuits 33 are arranged in a matrix of m rows and n columns (m and n are each integers equal to or greater than 1). In this specification, the section in the first row and first column is referred to as display unit 31[1,1], and the section in the mth row and nth column is referred to as display unit 31[m,n]. Display units 31[1,1] to 31[m,n] can be combined to form the display unit 31. Note that display units 31[1,1] to 31[m,n] may also be referred to as sub-display units. The display unit 31 can display a single image by combining multiple sub-display units. FIG. 13C shows a case in which m is 4 and n is 4. That is, the display unit 31 is divided into 16 sections. Each of the divided display portions 31[1,1] to 31[m,n] includes a gate line driver circuit 32 connected to a wiring GL and a source line driver circuit 33 connected to a wiring SL.

[0121] By providing the display section 31 and the display driver 22 in an overlapping region, the connection distance (wiring length) between the pixel circuit and the peripheral driver circuit can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. In addition, power consumption can be reduced. Furthermore, miniaturization and weight reduction can be achieved.

[0122] Furthermore, the display unit 31 is configured to have a gate line driver circuit 32 and a source line driver circuit 33 for each of the display units 31[1,1] to 31[m,n]. Therefore, the display unit 31 can rewrite the image for each of the display units 31[1,1] to 31[m,n]. For example, it is possible to rewrite image data only in sections of the display unit 31 where changes have occurred in the image, and to retain the image data in sections where no changes have occurred, thereby reducing power consumption. In other words, it is possible to reduce the number of times image data is rewritten per unit time in one of the sub-display units 31[1,1] to 31[m,n] compared to the number of times image data is rewritten per unit time in the other sub-display units, thereby reducing power consumption.

[0123] Furthermore, the display device 100 can individually set the drive frequency (frame frequency, frame rate, refresh rate, etc.) for displaying images for each of the display units 31[1,1] to 31[m,n]. Therefore, by combining with eye tracking or the like, it becomes possible to apply foveated rendering, a type of rendering that varies the frame rate for each region depending on the user's line of sight. This allows for a configuration that outputs images with excellent display quality and low load.

[0124] In a display device according to one embodiment of the present invention, pixel circuits and display driver units are stacked and the divided display units 31 are driven at different drive frequencies, thereby achieving low power consumption. For example, the drive frequencies of the divided display units 31 are varied depending on the movement of the gaze. Note that information about the movement of the gaze (gazing point G) can be obtained by an eye tracking method such as a pupil center corneal reflection method or a bright / dark pupil effect method. Alternatively, the information may be obtained by an eye tracking method using a laser, ultrasound, or the like.

[0125] FIG. 14A shows a display unit 31 divided into 32 sections, or 4 rows and 8 columns. FIG. 14A also shows a first region S1 to a third region S3, each centered around a gaze point G. The display unit 31 divides each of the divided sections into either a first section 29A overlapping the first region S1 or the second region S2, or a second section 29B overlapping the third region S3. That is, the display unit 31 divides each of the divided sections into either a first section 29A or a second section 29B. In this case, the first section 29A overlapping the first region S1 and the second region S2 is a display section that includes an area overlapping with the gaze point G, and the second section 29B is located outside the first section 29A and far from the user's gaze point G (see FIG. 14B).

[0126] The gate line driving circuit 32 and the source line driving circuit 33 of each divided display unit 31 can be individually controlled. For example, the display unit corresponding to the second section 29B overlaps with the third region S3, which includes the stable fixation field, the induced field, and the auxiliary field, and is therefore a section with low user discrimination. Therefore, even if the number of times image data is rewritten per unit time (hereinafter also referred to as "image rewriting count") for the display unit belonging to the second section 29B is reduced compared to the display unit corresponding to the first section 29A, the degradation of the actual display quality perceived by the user (hereinafter also referred to as "effective display quality") is minimal. In other words, even if the drive frequency of the display unit corresponding to the second section 29B is reduced compared to the drive frequency of the display unit corresponding to the first section 29A, the degradation of the actual display quality is minimal.

[0127] Lowering the drive frequency can reduce the power consumption of the display device. On the other hand, lowering the drive frequency also reduces the display quality, particularly when displaying moving images. According to one aspect of the present invention, by setting the drive frequency of the display unit corresponding to the second section 29B lower than the drive frequency of the display unit corresponding to the first section 29A, it is possible to reduce the power consumption of sections with low user visibility while suppressing a substantial decrease in display quality. According to one aspect of the present invention, it is possible to maintain display quality while reducing power consumption.

[0128] The drive frequency of the display unit corresponding to the first section 29A can be 30 Hz to 500 Hz, preferably 60 Hz to 500 Hz. The drive frequency of the display unit corresponding to the second section 29B is preferably equal to or lower than the drive frequency of the first section 29A, more preferably equal to or lower than half the drive frequency of the display unit corresponding to the first section 29A, and even more preferably equal to or lower than one-fifth the drive frequency of the display unit corresponding to the first section 29A.

[0129] Furthermore, among the display units corresponding to the third region S3, a third section 29C may be set outside the second section 29B (see FIG. 14C ), and the drive frequency of the display unit corresponding to the third section 29C may be lower than that of the display unit corresponding to the second section 29B. The drive frequency of the display unit corresponding to the third section 29C is preferably equal to or lower than the drive frequency of the display unit corresponding to the second section 29B, more preferably equal to or lower than half the drive frequency of the display unit corresponding to the second section 29B, and even more preferably equal to or lower than one-fifth the drive frequency of the display unit corresponding to the second section 29B. By significantly reducing the number of times the image is rewritten, power consumption can be further reduced. Furthermore, image data rewriting may be stopped as necessary. Stopping image data rewriting can further reduce power consumption.

[0130] When such a driving method is performed, it is preferable to use a transistor with extremely low off-state current as the transistor constituting the pixel circuit 51. For example, an OS transistor is preferable as the transistor constituting the pixel circuit 51. Since the off-state current of an OS transistor is extremely low, image data supplied to the pixel circuit 51 can be held for a long period of time by stopping the output signal output from the gate line driver circuit.

[0131] Furthermore, when the video scene displayed on the display unit 31 changes, an image with significantly different brightness, contrast, or color tone from the immediately preceding image may be displayed. In such a case, a difference occurs in the timing of image switching between the first section 29A and a section with a lower drive frequency than the first section 29A, resulting in a significant difference in brightness, contrast, or color tone between the two sections, which may result in a loss of substantial display quality. In such a case, for example, the image in sections other than the first section 29A may be rewritten at the same drive frequency as the first section 29A, and then the drive frequency of the sections other than the first section 29A may be lowered.

[0132] Furthermore, when it is determined that the amount of change in the gaze point G has exceeded a certain amount, the display units other than the display unit corresponding to first section 29A may also rewrite the images at the same drive frequency as the display unit corresponding to first section 29A, and when it is determined that the amount of change is within the certain amount, the drive frequency of the display units other than the display unit corresponding to first section 29A may be reduced. Furthermore, when it is determined that the amount of change in the gaze point G is small, the drive frequency of the display units other than the display unit corresponding to first section 29A may be further reduced.

[0133] The divided display sections that make up the display unit 31 are not limited to the first section 29A, the second section 29B, and the third section 29C. Four or more sections may be set in the display unit 31. By setting multiple sections in the display unit 31 and gradually lowering the drive frequency, it is possible to further reduce the actual degradation of display quality.

[0134] Furthermore, high-speed rewriting can be realized by simultaneously rewriting image data on all divided display sections 31, instead of rewriting image data on each divided display section 31. In other words, high-speed rewriting can be realized by simultaneously rewriting image data on all divided display sections 31, instead of rewriting image data on each divided display section 31.

[0135] In addition, in the display device 100 exemplified in this embodiment, the display unit 31 is divided into eight sections in the column direction (FIGS. 14A to 14C), so the length of the wiring GL connecting the gate line driving circuit and the pixel circuit is reduced to one-eighth, which reduces the resistance and parasitic capacitance of the wiring GL to one-eighth, improving signal degradation and delay and making it easier to ensure time for rewriting image data.

[0136] According to the display device 100 of one embodiment of the present invention, the time required for writing image data is short, and therefore high-speed rewriting of a display image can be realized. Therefore, a display device with high display quality can be realized, and in particular, a display device excellent in displaying moving images can be realized.

[0137] Furthermore, according to the display device 100 of one embodiment of the present invention, the output signals output by the gate line driver circuit can be controlled independently for each divided display portion, and therefore the divided display portions can have different shapes or sizes. That is, the display portion 31 can be configured with display portions having different shapes or sizes. Therefore, the display portion 31 is not limited to a rectangular shape, and can have a shape with excellent design, such as a circular shape.

[0138] 15 to 17 show configuration examples of pixel circuits applicable to the pixel circuit 51, and light-emitting elements connected to the pixel circuit 51. In the following description, the light-emitting element is not limited to an organic EL element, and may be a self-luminous light-emitting device such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0139] In this specification and the like, the term “element” may be replaced with “device.” For example, a display element and a light-emitting element may be replaced with a display device and a light-emitting device, respectively.

[0140] A pixel circuit 51A shown in Fig. 15A includes a transistor 55A, a transistor 55B, and a capacitor 56. Fig. 15A also illustrates a light-emitting element 61 connected to the pixel circuit 51A. Fig. 15A also illustrates a wiring SL, a wiring GL, a power supply line ANO, and a power supply line VCOM.

[0141] The transistor 55A has a gate connected to the wiring GL, one of its source and drain connected to the wiring SL, and the other connected to the gate of the transistor 55B and one electrode of the capacitor 56. The transistor 55B has one of its source and drain connected to the power supply line ANO, and the other connected to the anode of the light-emitting element 61. The other electrode of the capacitor 56 is connected to the anode of the light-emitting element 61. The light-emitting element 61 has a cathode connected to the power supply line VCOM. The anode and cathode of the light-emitting element 61 can be switched as needed by changing the magnitude of the potential supplied.

[0142] 15B is a pixel circuit 51A including a transistor 55C. The transistor 55C has a gate connected to a wiring GL, one of a source and a drain connected to an anode of the light-emitting element 61, and the other connected to a wiring V0.

[0143] A pixel circuit 51C shown in FIG. 15C is an example in which transistors having a pair of gates are used as the transistors 55A and 55B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 15D is an example in which the same transistors are used in the pixel circuit 51B. This allows the current that the transistors can pass to be increased. Note that, although transistors having a pair of gates are used for all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is connected to the source.

[0144] 16A has a configuration in which a transistor 55D is added to the pixel circuit 51B. Three gate lines (a wiring GL1, a wiring GL2, and a wiring GL3) are connected to the pixel circuit 51E.

[0145] The gate of the transistor 55D is connected to a wiring GL3, one of the source and drain of the transistor 55D is connected to the gate of the transistor 55B, and the other is connected to a wiring V0. The gate of the transistor 55A is connected to a wiring GL1, and the gate of the transistor 55C is connected to a wiring GL2.

[0146] By simultaneously turning on transistors 55C and 55D, the source and gate of transistor 55B have the same potential, and when the threshold voltage of transistor 55B is higher than 0 V, transistor 55B can be turned off. This makes it possible to forcibly cut off the current flowing through light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0147] 16B is an example in which a capacitor 56A is added to the pixel circuit 51E. The capacitor 56A functions as a storage capacitor.

[0148] 16C and 16D are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F, respectively. Transistors each having a pair of gates connected to each other are applied to the transistor 55A, the transistor 55C, and the transistor 55D, and a transistor each having one gate connected to its source is applied to the transistor 55B.

[0149] 16A to 16D show examples in which the circuit can be configured using only n-channel OS transistors. However, one embodiment of the present invention is not limited to this. For example, a pixel circuit may include an OS transistor and a Si transistor. Specifically, in the pixel circuit 51A of FIG. 15A, it is preferable that the transistor 55A be an OS transistor and the transistor 55B be a Si transistor.

[0150] 17A shows an example of the circuit configuration of a pixel circuit (pixel circuit 51J). FIG. 17B is a diagram schematically showing the hierarchical relationship between an element layer 20 including a display driver 22, an element layer 30 including a pixel circuit 51, and a light-emitting element layer 60 including a light-emitting element 61.

[0151] 17A and 17B includes a transistor 55A, a transistor 55B, a transistor 55C, and a capacitor 56. The transistors 55A, 55B, and 55C can be OS transistors. Each of the OS transistors 55A, 55B, and 55C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode.

[0152] The transistor 55B has a gate electrode connected to the transistor 55A, a first electrode connected to the light-emitting element 61, and a second electrode connected to the power supply line ANO. The power supply line ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0153] Transistor 55A has a first electrode connected to the gate electrode of transistor 55B, a second electrode connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0154] The transistor 55C includes a first electrode connected to the wiring V0, a ​​second electrode connected to the light-emitting element 61, and a functional gate electrode that controls the conductive state or non-conductive state based on the potential of the wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the display driver 22.

[0155] The capacitor 56 includes a conductive film connected to the gate electrode of the transistor 55B and a conductive film connected to the second electrode of the transistor 55C.

[0156] The light-emitting element 61 has a first electrode connected to the first electrode of the transistor 55B and a second electrode connected to a power supply line VCOM. The power supply line VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0157] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with an image signal applied to the gate electrode of the transistor 55B. Also, the reference potential of the wiring V0 applied via the transistor 55C can suppress variations in the gate-source potential of the transistor 55B.

[0158] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting to the outside the current flowing through the transistor 55B or the current flowing through the light-emitting element 61. The current output to the wiring V0 may be converted into a voltage by a source follower circuit or the like.

[0159] In the configuration example shown in FIG. 17B , the wiring connecting the pixel circuit 51J and the display driver 22 can be shortened, thereby reducing the wiring resistance of the wiring. Furthermore, the parasitic capacitance of the wiring can be reduced. Therefore, data can be written at high speed, allowing the display unit 31 to be driven at high speed. This ensures a sufficient frame period even when the number of pixel circuits 51 is increased, thereby increasing the pixel density of the display unit 31. Furthermore, increasing the pixel density of the display unit 31 can improve the resolution of images displayed on the display unit 31. For example, the pixel density of the display unit 31 can be set to 1,000 ppi or more, 5,000 ppi or more, or 7,000 ppi or more. Therefore, the display device 100 can be used, for example, as a display device for xR (xR) such as AR or VR. The display device 100 according to one embodiment of the present invention can be suitably applied to electronic devices, such as HMDs, in which the display unit is close to the user.

[0160] As described above, the display device 100 of one embodiment of the present invention has a stacked structure in which an element layer including the display portion 31 and the memory portion 71 and an element layer including the display driver portion 22 and the image data processing portion 70 are stacked. Stacking element layers including the respective circuits enables the miniaturization of the display device 100. Furthermore, by providing the display driver portion 22 overlapping the display portion 31, the width of the frame around the display portion 31 can be significantly narrowed, thereby increasing the area of ​​the display portion 31. Therefore, the resolution of the display portion 31 can be increased. Therefore, the display quality of the display device 100 can be improved.

[0161] Furthermore, when the resolution of the display unit 31 is constant, the occupied area per pixel can be increased. Thus, the luminance of the display unit 31 can be increased. Furthermore, the aperture ratio of the pixel can be increased. For example, the aperture ratio of the pixel can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, by increasing the occupied area per pixel, the current density supplied to the pixel can be reduced. Thus, the load on the pixel is reduced, and the reliability of the display device 100 can be improved.

[0162] Furthermore, by stacking an element layer having the display unit 31 and the storage unit 71 and an element layer having the display driver 22 and the image data processor 70, the wiring connecting them can be shortened. This reduces wiring resistance and parasitic capacitance, enabling the operating speed of the display device 100 to be increased. Furthermore, the power consumption of the display device 100 is reduced.

[0163] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0164] In this embodiment, a modified example of a structure of a display device according to one embodiment of the present invention will be described. Note that in this embodiment, repeated description of components having the same reference numerals as those in the above embodiment may be omitted.

[0165] 18A and 19 are perspective views of a display device 100A according to one embodiment of the present invention. FIG. 18B is a block diagram illustrating a configuration of the display device 100A. The display device 100A includes an element layer 30A on an element layer 20, an element layer 30B on the element layer 30A, and a sealing substrate 40 on the element layer 30B. The element layer 30B includes a display unit 31, and a light-emitting element layer 60 is provided between the sealing substrate 40 and the display unit 31. The element layer 30A also includes a memory unit 71. In FIG. 19 , the element layer 20, the element layer 30A, the element layer 30B, the light-emitting element layer 60, the sealing substrate 40, and the like are shown separated from one another to make the configuration of the display device 100A easier to understand.

[0166] The description of the element layer 20 is the same as that in the first embodiment.

[0167] The memory unit 71 provided in the element layer 30 includes a plurality of memory circuits 72. In the configuration of the display device 100A, the display unit 31 and the memory unit 71 are provided in different layers, that is, the element layer 30A and the element layer 30B, respectively. This allows the display unit 31 to have a larger area and the memory unit 71 to have a larger capacity. Note that although the memory circuits 72 included in the memory unit 71 and the pixel circuits 51 included in the display unit 31 are provided in different layers, they both include OS transistors.

[0168] In one embodiment of the present invention, the storage unit 71 can be provided in the element layer 30A, which is different from the element layer 30B in which the display unit 31 is provided. This increases the storage capacity of the display device 100A and the display area. The storage unit 71 can be used as a storage circuit that stores weight data used in the image data processing unit 70.

[0169] As described above, the display device 100A of one embodiment of the present invention has a stacked structure including an element layer including the display unit 31, an element layer including the memory unit 71, and an element layer including the display driver unit 22 and the image data processing unit 70. Stacking the layers including the circuits can reduce the size of the display device 100A. Furthermore, the display driver unit 22 can be provided overlapping the display unit 31, thereby increasing the area of ​​the display unit 31. Therefore, the resolution of the display unit 31 can be increased, and the display quality of the display device 100A can be improved.

[0170] Furthermore, by stacking an element layer having the display unit 31, an element layer having the memory unit 71, and an element layer having the display driver 22 and the image data processor 70, it is possible to shorten the wiring connecting them. This reduces wiring resistance and parasitic capacitance, enabling the operating speed of the display device 100A to be increased. Furthermore, the power consumption of the display device 100A is reduced.

[0171] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0172] Embodiment 3 In this embodiment, a structural example of a display module to which a display device of one embodiment of the present invention can be applied will be described.

[0173] The display device of this embodiment can be a high-resolution display panel. For example, the display device of one embodiment of the present invention can be used for a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, or a head-mountable wearable device such as a glasses-type AR device.

[0174] 20A shows a perspective view of a display module 980. The display module 980 includes a display device 200A and an FPC 990. Note that the display panel included in the display module 980 is not limited to the display device 200A, and may be a display device 200B described later.

[0175] The display module 980 includes a substrate 991 and a substrate 992. The display module 980 includes a display portion 981. The display portion 981 is a region for displaying an image.

[0176] 20B is a perspective view schematically illustrating the configuration on the substrate 991 side. A circuit portion 982, a display portion 983 on the circuit portion 982, and a pixel portion 984 on the display portion 983 are stacked on the substrate 991. A terminal portion 985 for connecting to an FPC 990 is provided in a portion of the substrate 991 that does not overlap with the pixel portion 984. The terminal portion 985 and the circuit portion 982 are connected by a wiring portion 986 composed of a plurality of wirings.

[0177] The layer including the circuit portion 982 can be applied with circuits having each structure included in the element layer 20 described in the above-described Embodiment 1 and the like. In addition to the pixel circuit 983a, circuits included in the memory portion or the like included in the element layer 30 described in the above-described Embodiment 1 and the like can be applied to the layer including the display portion 983. By appropriately increasing the number of layers in which elements are provided, the circuits having each structure included in the element layer 20 described in the above-described Embodiment 1 and the like can be applied.

[0178] The pixel portion 984 has a plurality of periodically arranged pixels 984a. An enlarged view of one pixel 984a is shown on the right side of Fig. 20B. The pixel 984a has a light-emitting device 410R that emits red light, a light-emitting device 410G that emits green light, and a light-emitting device 410B that emits blue light.

[0179] The display portion 983 includes a plurality of pixel circuits 983a arranged periodically. Each pixel circuit 983a controls light emission of three light-emitting devices included in one pixel 984a. As described in Embodiment 1, a memory portion (not shown) may be provided in the layer where the display portion 983 is provided. Alternatively, the pixel circuit 983a may include a memory cell (not shown) included in the memory portion. Each pixel circuit 983a may include three circuits for controlling light emission of one light-emitting device. For example, the pixel circuit 983a may include at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. A gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This achieves an active matrix display panel.

[0180] The circuit portion 982 includes a circuit for driving each pixel circuit 983a in the display portion 983. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 982 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 982 may constitute part of the pixel circuit 983a. That is, the pixel circuit 983a may be configured using a transistor included in the display portion 983 and a transistor included in the circuit portion 982.

[0181] The FPC 990 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 982. An IC may be mounted on the FPC 990.

[0182] The display module 980 can have a structure in which a layer having a display portion 983 and a layer having a circuit portion 982 are stacked below the pixel portion 984, thereby enabling the aperture ratio (effective display area ratio) of the display portion 981 to be extremely high. For example, the aperture ratio of the display portion 981 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 984a can be arranged at extremely high density, enabling the resolution of the display portion 981 to be extremely high. For example, it is preferable that the pixels 984a be arranged in the display portion 981 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0183] Because such a display module 980 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 980 is viewed through lenses, the display module 980 has an extremely high-resolution display unit 981, so that even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 980 is not limited to this, and can be suitably used in electronic devices having relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0184] [Display Device 200A] A display device 200A shown in FIG. 21 has a stacked structure of a transistor 810 in which a channel is formed in a substrate 801 and a transistor 820 in which a channel is formed and a semiconductor layer containing metal oxide.

[0185] Substrate 801 corresponds to substrate 991 in FIGS. 20A and 20B.

[0186] The transistor 810 has a channel formation region in a substrate 801. The substrate 801 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 810 includes a part of the substrate 801, a conductive layer 811, a low-resistance region 812, an insulating layer 813, and an insulating layer 814. The conductive layer 811 functions as a gate electrode. The insulating layer 813 is located between the substrate 801 and the conductive layer 811 and functions as a gate insulating layer. The low-resistance region 812 is a region in which the substrate 801 is doped with impurities and functions as one of a source and a drain. The insulating layer 814 is provided to cover a side surface of the conductive layer 811.

[0187] An element isolation layer 815 is provided between two adjacent transistors 810 so as to be buried in the substrate 801 .

[0188] An insulating layer 961 is provided to cover the transistor 810, and a conductive layer 951 is provided over the insulating layer 961. An insulating layer 962 is provided to cover the conductive layer 951, and a conductive layer 952 is provided over the insulating layer 962. The conductive layer 951 and the conductive layer 952 each function as a wiring. An insulating layer 963 and an insulating layer 832 are provided to cover the conductive layer 952, and the transistor 820 is provided over the insulating layer 832.

[0189] The transistor 820 is a transistor (OS transistor) in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0190] The transistor 820 includes a semiconductor layer 821 , an insulating layer 823 , a conductive layer 824 , a pair of conductive layers 825 , an insulating layer 826 , and a conductive layer 827 .

[0191] An insulating layer 832 is provided over the insulating layer 963. The insulating layer 832 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 963 to the transistor 820 and prevents oxygen from being released from the semiconductor layer 821 toward the insulating layer 832. The insulating layer 832 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0192] A conductive layer 827 is provided over the insulating layer 832, and an insulating layer 826 is provided to cover the conductive layer 827. The conductive layer 827 functions as a first gate electrode of the transistor 820, and part of the insulating layer 826 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 826 that is in contact with the semiconductor layer 821. The top surface of the insulating layer 826 is preferably planarized.

[0193] The semiconductor layer 821 is provided over the insulating layer 826. The semiconductor layer 821 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 825 is provided over and in contact with the semiconductor layer 821 and functions as a source electrode and a drain electrode.

[0194] An insulating layer 828 is provided to cover top surfaces and side surfaces of the pair of conductive layers 825 and side surfaces of the semiconductor layer 821, and an insulating layer 964 is provided over the insulating layer 828. The insulating layer 828 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 964 or the like to the semiconductor layer 821 and prevents oxygen from being released from the semiconductor layer 821. The insulating layer 828 can be an insulating film similar to the insulating layer 832.

[0195] An opening reaching the semiconductor layer 821 is provided in the insulating layer 828 and the insulating layer 964. An insulating layer 823 in contact with the top surface of the semiconductor layer 821 and a conductive layer 824 are buried in the opening. The conductive layer 824 functions as a second gate electrode, and the insulating layer 823 functions as a second gate insulating layer.

[0196] The top surface of the conductive layer 824, the top surface of the insulating layer 823, and the top surface of the insulating layer 964 are planarized so that their heights are the same or approximately the same, and insulating layers 829 and 965 are provided to cover them.

[0197] The insulating layers 964 and 965 function as interlayer insulating layers. The insulating layer 829 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 965 or the like to the transistor 820. The insulating layer 829 can be formed using an insulating film similar to the insulating layers 828 and 832.

[0198] A plug 974 connected to one of the pair of conductive layers 825 is provided so as to be embedded in the insulating layer 965, the insulating layer 829, and the insulating layer 964. Here, the plug 974 is preferably configured so that the side surfaces of the openings of the insulating layer 965, the insulating layer 829, the insulating layer 964, and the insulating layer 828 and part of the top surface of the conductive layer 825 are covered with the conductive layer. In this case, the conductive layer covering the plug 974 is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0199] Furthermore, a capacitor 840 is provided on the insulating layer 965. The capacitor 840 and the transistor 820 are connected by a plug 974.

[0200] The transistor 820 can be used as a transistor that forms a pixel circuit. The transistor 810 can be used as a transistor that forms a pixel circuit or a transistor that forms a driver circuit (gate line driver circuit, source line driver circuit) for driving the pixel circuit. The transistors 810 and 820 can be used as transistors that form various circuits such as memory cells.

[0201] The capacitor 840 has a conductive layer 941, a conductive layer 945, and an insulating layer 943 located therebetween. The conductive layer 941 functions as one electrode of the capacitor 840, the conductive layer 945 functions as the other electrode of the capacitor 840, and the insulating layer 943 functions as a dielectric of the capacitor 840.

[0202] The conductive layer 941 is provided over the insulating layer 961 and is buried in the insulating layer 954. The conductive layer 941 is connected to one of the source and the drain of the transistor 810 by a plug 971 buried in the insulating layer 961. The insulating layer 943 is provided to cover the conductive layer 941. The conductive layer 945 is provided in a region overlapping with the conductive layer 941 with the insulating layer 943 interposed therebetween.

[0203] An insulating layer 955a is provided to cover the capacitor 840, an insulating layer 955b is provided over the insulating layer 955a, and an insulating layer 955c is provided over the insulating layer 955b.

[0204] An inorganic insulating film can be preferably used for each of the insulating layers 955a, 955b, and 955c. For example, it is preferable to use a silicon oxide film for the insulating layer 955a and the insulating layer 955c, and a silicon nitride film for the insulating layer 955b. This allows the insulating layer 955b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 955c is etched to form a recess, but the insulating layer 955c does not necessarily have to have a recess.

[0205] The light emitting device 410R, the light emitting device 410G, and the light emitting device 410B are provided on the insulating layer 955c.

[0206] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, resulting in minimal change in chromaticity between low-luminance and high-luminance emission. Furthermore, because the organic layers 412R, 412G, and 412B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This allows for the realization of a high-resolution, high-quality display panel.

[0207] In the region between adjacent light emitting devices, an insulating layer 425, a resin layer 426, and a layer 428 are provided.

[0208] The pixel electrodes 411R, 411G, and 411B of the light-emitting device are connected to one of the source and drain of the transistor 810 via a plug 956 embedded in insulating layers 955a, 955b, and 955c, a conductive layer 941 embedded in insulating layer 954, and a plug 971 embedded in insulating layer 961. The height of the top surface of the insulating layer 955c and the height of the plug 956 are the same or approximately the same. Various conductive materials can be used for the plug. Note that the pixel electrodes 411R, 411G, and 411B may be collectively referred to as pixel electrodes 411.

[0209] A protective layer 421 is provided on the light-emitting devices 410R, 410G, and 410B. A substrate 470 is attached to the protective layer 421 with an adhesive layer 471.

[0210] No insulating layer covering the upper end of each pixel electrode 411 is provided between two adjacent pixel electrodes 411. This allows the distance between adjacent light-emitting devices to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0211] With this configuration, not only pixel circuits but also driving circuits etc. can be formed directly below the light-emitting device, which makes it possible to make the display panel smaller than when driving circuits are provided around the periphery of the display area.

[0212] 22 has a stacked structure of a transistor 820A containing a metal oxide in a semiconductor layer in which a channel is formed and a transistor 820B containing a metal oxide in a semiconductor layer in which a channel is formed. This structure allows the use of transistors in which the metal oxide in the semiconductor layer has a different composition of constituent elements. Therefore, a display device using OS transistors with different transistor characteristics can be provided. For example, the upper transistor 820A can be used as a transistor in a pixel circuit that drives a light-emitting device, and the lower transistor 820B can be used as a transistor in a memory cell.

[0213] This configuration allows the circuits located directly below the light-emitting devices to be arranged more densely, making it possible to make the display panel smaller than when the driving circuits are located around the periphery of the display area.

[0214] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0215] Embodiment 4 In this embodiment, electronic devices to which a display device according to one embodiment of the present invention can be applied will be described.

[0216] A display device according to one embodiment of the present invention can be applied to a display portion of an electronic device. Therefore, an electronic device with high display quality, extremely high resolution, or high reliability can be realized.

[0217] Examples of electronic devices using a display device according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Examples of such equipment include image playback devices that play back still images or videos stored on recording media such as a CD (disc), portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet terminals, portable game machines, fixed game machines such as pachinko machines, calculators, electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, air conditioning equipment such as electric rice cookers, electric washing machines, electric vacuum cleaners, hot water heaters, electric fans, hair dryers, air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, and tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids. Mobile bodies propelled by fuel-powered engines or electric motors powered by power from power storage devices may also be included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid vehicles (HVs) equipped with both internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0218] An electronic device according to one embodiment of the present invention may include a secondary battery (battery), and it is preferable that the secondary battery can be charged using contactless power transmission.

[0219] Examples of secondary batteries include lithium ion secondary batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0220] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0221] An electronic device according to one embodiment of the present invention may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0222] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0223] Furthermore, electronic devices having multiple display units can have a function of mainly displaying image information on one part of the display units and mainly displaying text information on another part, or a function of displaying a stereoscopic image by displaying an image taking into account parallax on the multiple display units. Furthermore, electronic devices having an image receiving unit can have a function of capturing a still image or a video, a function of automatically or manually correcting the captured image, a function of storing the captured image in a recording medium (external or built in the electronic device), a function of displaying the captured image on the display unit, etc. Note that the functions of the electronic device of one embodiment of the present invention are not limited to these, and can have various functions.

[0224] A display device according to one embodiment of the present invention can display high-resolution images. Therefore, the display device can be suitably used in portable electronic devices, wearable electronic devices, e-book readers, etc. For example, the display device can be suitably used in xR devices such as VR devices and AR devices.

[0225] 23A shows the appearance of a head-mounted display 710. The head-mounted display 710 includes a mounting portion 711, a lens 712, a main body 713, a display portion 714, a cable 715, and the like. A battery 716 is built into the mounting portion 711. A display device according to one embodiment of the present invention can be applied to the display portion 714.

[0226] A cable 715 supplies power from a battery 716 to the main body 713. The main body 713 is equipped with a wireless receiver and the like, and can display received video information such as image data on a display unit 714. In addition, a camera provided in the main body 713 captures the movement of the user's eyeballs and / or eyelids, and calculates the user's line of sight based on the information, thereby enabling the user's line of sight to be used as an input means.

[0227] The attachment unit 711 may also be provided with a plurality of electrodes at positions that come into contact with the user. The main body 713 may have a function of recognizing the user's line of sight by detecting current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 713 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The attachment unit 711 may also have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc., and may have a function of displaying the user's biological information on the display unit 714. The attachment unit 711 may also detect the movement of the user's head, and change the image displayed on the display unit 714 in accordance with the movement.

[0228] 23B shows the appearance of the head-mounted display 720. The head-mounted display 720 is a goggle-type information processing device.

[0229] The head-mounted display 720 includes a housing 721, operation buttons 723, a band-shaped fixture 724, and two display units 722. The two display units 722 allow the user to view one display unit per eye. This allows high-resolution images to be displayed, even when performing 3D display using parallax. The fixture 724 is also provided with a battery 725. While the battery 725 may be provided in the housing 721, providing the battery 725 in the fixture 724 is preferable because it allows the center of gravity of the head-mounted display 720 to be positioned rearward, improving the wearing comfort for the user. In addition to the battery 725, a drive circuit for operating the display units 722 may also be provided in the fixture 724 to adjust the center of gravity of the head-mounted display 720.

[0230] The operation button 723 has a function of a power button, etc. In addition to the operation button 723, other buttons may be provided.

[0231] A display device according to one embodiment of the present invention can be applied to the display portion 722. The display device according to one embodiment of the present invention has extremely high definition, and therefore, pixels are less visible to a user, and more realistic images can be displayed.

[0232] FIG. 23C shows the exterior of camera 730 with viewfinder 740 .

[0233] The camera 730 includes a housing 731, a display portion 732, operation buttons 733, a shutter button 734, etc. A detachable lens 736 is attached to the camera 730.

[0234] Here, the camera 730 has a structure in which the lens 736 can be detached from the housing 731 and replaced, but the lens 736 and the housing may be integrated.

[0235] The camera 730 can capture an image by pressing a shutter button 734. The display portion 732 also functions as a touch panel, and an image can be captured by touching the display portion 732.

[0236] The housing 731 of the camera 730 has a mount with electrodes, and can be connected to a finder 740 as well as a strobe device and the like.

[0237] The finder 740 includes a housing 741, a display portion 742, a button 743, and the like.

[0238] The housing 741 has a mount that engages with the mount of the camera 730, and the viewfinder 740 can be attached to the camera 730. The mount also has electrodes, and images received from the camera 730 can be displayed on the display unit 742 via the electrodes.

[0239] The button 743 functions as a power button, and can be used to switch the display of the display unit 742 on and off.

[0240] The display device according to one embodiment of the present invention can be applied to the display portion 732 of the camera 730 and the display portion 742 of the finder 740 .

[0241] Note that in FIG. 23C , the camera 730 and the finder 740 are separate electronic devices that are detachable; however, a finder including a display device according to one embodiment of the present invention may be built into the housing 731 of the camera 730.

[0242] 23D includes a housing 751, a display portion 752, a microphone 757, a speaker portion 754, a camera 753, an operation switch 755, and the like. A display device according to one embodiment of the present invention can be used for the display portion 752. The display portion 752 has a touch panel function. The information terminal 750 includes an antenna, a battery, and the like inside the housing 751. The information terminal 750 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an e-book reader, or the like.

[0243] 23E shows an example of a wristwatch-type information terminal. Information terminal 760 includes a housing 761, a display unit 762, a band 763, a buckle 764, operation switches 765, an input / output terminal 766, and the like. Information terminal 760 also includes an antenna, a battery, and the like inside housing 761. Information terminal 760 can execute various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games.

[0244] The display unit 762 also has a touch sensor, allowing operation by touching the screen with a finger or a stylus. For example, an application can be started by touching an icon 767 displayed on the display unit 762. The operation switch 765 can have various functions, such as time setting, power on / off operation, wireless communication on / off operation, silent mode activation / deactivation, and power saving mode activation / deactivation. For example, the functions of the operation switch 765 can be set by an operating system incorporated in the information terminal 760.

[0245] The information terminal 760 is also capable of performing short-range wireless communication according to a communication standard. For example, hands-free conversation is also possible by mutual communication with a wirelessly enabled headset. The information terminal 760 is also provided with an input / output terminal 766, and can transmit and receive data to and from other information terminals via the input / output terminal 766. Charging can also be performed via the input / output terminal 766. Note that charging may be performed by wireless power supply without using the input / output terminal 766.

[0246] 23A to 23E , electronic devices to which the display device according to one embodiment of the present invention can be applied may be connected to an external server via a network. Furthermore, instead of performing processing requiring high computing power in the electronic device itself, the processing requiring high computing power may be performed by a server connected via a network. This type of processing is also called a thin client. A user (client) terminal (the electronic device in this case) performs only limited processing, while the server performs advanced processing, such as application execution and management, thereby reducing the scale of processing required by the client terminal. This eliminates the need for a computing device with high computing power in the electronic device, thereby facilitating cost reduction, weight reduction, and miniaturization. Furthermore, the electronic device according to one embodiment of the present invention may perform processing by combining the thin client and processing requiring high computing power in the electronic device.

[0247] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0248] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes are provided regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0249] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0250] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0251] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0252] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0253] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0254] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0255] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0256] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0257] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0258] In this specification and the like, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0259] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0260] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0261] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0262] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0263] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0264] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0265] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0266] In this specification, "connection" includes, as an example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, as examples, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0267] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0268] Specific examples of "indirect connection" are given below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, it is assumed that there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where there is a time when one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0269] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0270] Another example of a case in which it cannot be said that "A and B are indirectly connected" is when there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. For example, a path from A to B may have multiple transistors connected via their sources and drains, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." Note that if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply, GND, or the like, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and C are indirectly connected" or "B and C are indirectly connected."

[0271] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0272] Next, specific examples of "direct connection" are shown. An example of "A and B are directly connected" is when A and B are connected without any circuit element between them. Note that when A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Note that even when A (or B) is connected to a constant potential V via the source and drain of a transistor, it can still be said that "A and B are directly connected." Note that because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0273] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0274] ANO: power supply line, COL: interpolated data, D82: data, D83: data, D84: data, D85: data, DFIL: data, DFIL_1: data, DFIL_3: data, DFILL: data, DIN: data, DOUT: data, DOV_1: area, DOV_2: area, GL: wiring, IN: input, in: terminal, OUT: output, out: terminal, po: output signal, RAM: static, SL: wiring, sw: terminal, VCOM: power supply line, VDD: power supply potential, Vgs: voltage, VSS: power supply potential, Vth: threshold voltage, 20: element layer, 22: display driver, 29: terminal portion, 29A: first section, 29B: second section, 29C: third section, 30: element layer, 30A: element layer, 30B: element layer, 31[1,1]: display section, 31[m,n]: display section, 31: display section, 31b: display section, 32: gate line driving circuit, 33: source line driving circuit, 40: sealing substrate, 41: line memory, 42: level shifter, 43: pass transistor logic, 44: digital-to-analog conversion circuit, 45: amplifier circuit, 50: pixel, 51: pixel circuit, 51A: pixel circuit, 51B: pixel circuit, 51C: pixel circuit, 51D: pixel circuit, 51E: pixel circuit, 51 F: pixel circuit, 51G: pixel circuit, 51H: pixel circuit, 51J: pixel circuit, 52: memory circuit, 55A: transistor, 55B: transistor, 55C: transistor, 55D: transistor, 56: capacitor, 56A: capacitor, 60: light emitting element layer, 61: light emitting element, 68: LVDS circuit, 69: serial-parallel conversion circuit, 70: image data processing unit, 71: memory unit, 72: memory circuit, 73_1: convolution layer, 73_N: convolution layer, 73_NN: convolution layer, 74: multiplier, 74_1: multiplier, 74_9: multiplier, 75_1: register, 75_9: register register, 76: adder, 77: pooling circuit, 78: AND circuit, 79: adder, 80: convolution operation circuit, 80A: convolution operation circuit, 81: pre-processing layer, 82: operation processing layer, 82B: operation processing layer, 83: operation processing layer, 84: operation processing layer, 85: post-processing layer, 90: operation processing layer, 91: multiplier, 92: multiplier, 93: adder, 100: display device, 100A: display device, 100B: display device, 200A: display device, 200B: display device, 410B: light-emitting device, 410G: light-emitting device, 410R: light-emitting device, 411: pixel electrode, 411B: pixel electrode,411G: pixel electrode, 411R: pixel electrode, 412B: organic layer, 412G: organic layer, 412R: organic layer, 421: protective layer, 425: insulating layer, 426: resin layer, 428: layer, 470: substrate, 471: adhesive layer, 710: head-mounted display, 711: mounting portion, 712: lens, 713: main body, 714: display portion, 715: cable, 716: battery, 720: head-mounted display, 721: housing, 722: display portion, 723: operation button, 724: fixing device, 725 : Battery, 730: Camera, 731: Housing, 732: Display, 733: Operation buttons, 734: Shutter button, 736: Lens, 740: Viewfinder, 741: Housing, 742: Display, 743: Button, 750: Information terminal, 751: Housing, 752: Display, 753: Camera, 754: Speaker, 755: Operation switch, 757: Microphone, 760: Information terminal, 761: Housing, 762: Display, 763: Band, 764: Buckle, 765: Operation switch, 766: Input / output Terminal, 767: Icon, 801: Substrate, 810: Transistor, 811: Conductive layer, 812: Low resistance region, 813: Insulating layer, 814: Insulating layer, 815: Element isolation layer, 820: Transistor, 820A: Transistor, 820B: Transistor, 821: Semiconductor layer, 823: Insulating layer, 824: Conductive layer, 825: Conductive layer, 826: Insulating layer, 827: Conductive layer, 828: Insulating layer, 829: Insulating layer, 832: Insulating layer, 840: Capacitor, 941: Conductive layer, 943: Insulating layer, 945: Conductive layer, 9 51: conductive layer, 952: conductive layer, 954: insulating layer, 955a: insulating layer, 955b: insulating layer, 955c: insulating layer, 956: plug, 961: insulating layer, 962: insulating layer, 963: insulating layer, 964: insulating layer, 965: insulating layer, 971: plug, 974: plug, 980: display module, 981: display section, 982: circuit section, 983: display section, 983a: pixel circuit, 984: pixel section, 984a: pixel, 985: terminal section, 986: wiring section, 990: FPC, 991: substrate, 992: substrate,

Claims

A display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel formation region containing silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel formation region containing a metal oxide, the first element layer is provided with a display driving unit and an image data processing unit, the second element layer is provided with a display unit and a storage unit, the display unit has a pixel circuit, the storage unit has a storage circuit, the image data processing unit has a function of performing a multiplication-accumulation operation process using a convolutional neural network to generate second image data from first image data, the display driving unit has a function of driving the pixel circuit so that display based on the input second image data can be performed by the display unit, weight data used in the convolutional neural network is data stored in the storage circuit, A display device. 　 In claim 1, the display driving unit is provided in a region overlapping with the display unit, a display device. 　 A display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel formation region containing silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel formation region containing a metal oxide, the first element layer is provided with a display driving unit and an image data processing unit, the second element layer is provided with a display unit and a storage unit, the display unit has a pixel circuit, the storage unit has a storage circuit, the image data processing unit has a function of performing a first operation process and a second operation process to generate second image data from first image data, the first operation process performs a multiplication-accumulation operation process using first weight data, the second operation process performs a multiplication-accumulation operation process using second weight data, the display driving unit has a function of driving the pixel circuit so that display based on the input second image data can be performed by the display unit, each of the first weight data and the second weight data is data stored in the storage circuit, A display device. 　 In claim 3, the number of parameters of the second weight data is smaller than the number of parameters of the first weight data, A display device. 　 In claim 4, The first arithmetic processing and the second arithmetic processing perform a sum-of-products operation by convolution of input data, non-linear mapping of the convolved data, and deconvolution of the data to which the non-linear mapping is applied. Display device. 　 In claim 3, The display driving unit is provided in a region overlapping with the display unit. Display device. A display device having a first element layer, a second element layer on the first element layer, and a third element layer on the second element layer, The first element layer has a first transistor, The first transistor has a semiconductor layer having a channel formation region containing silicon, Each of the second element layer and the third element layer has a second transistor, The second transistor has a semiconductor layer having a channel formation region containing a metal oxide, The first element layer has a display driving unit and an image data processing unit, The second element layer has a storage unit, The storage unit has a storage circuit, The third element layer has a display unit, The display unit has a pixel circuit, The image data processing unit has a function of performing first arithmetic processing and second arithmetic processing to generate second image data from first image data, The first arithmetic processing performs a sum-of-products operation using first weight data, The second arithmetic processing performs a sum-of-products operation using second weight data, The display driving unit has a function of driving the pixel circuit so that display based on the input second image data can be performed on the display unit, Each of the first weight data and the second weight data is data stored in the storage circuit. Display device. 　 In claim 7, The number of parameters of the second weight data is smaller than the number of parameters of the first weight data. Display device. 　 In claim 8, The first arithmetic processing and the second arithmetic processing perform a sum-of-products operation by convolution of input data, non-linear mapping of the convolved data, and deconvolution of the data to which the non-linear mapping is applied. Display device. 　 In claim 7, The display driving unit is provided in a region overlapping with the display unit. Display device.

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