Circuit board and semiconductor package

Abstract

This circuit board includes: a build-up layer including a cavity formed in the top surface thereof; a connection member arranged in the cavity; a plurality of second bumps arranged on the connection member; and a protective layer arranged on the build-up layer, wherein the protective layer includes a protrusion arranged between the plurality of second bumps, and the top surface of the protrusion is a concave surface.

Description

Circuit boards and semiconductor packages

[0001] This embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] As the computer industry develops, technology for integrated circuits (dies) that can be produced at higher performance and lower costs is advancing. Consequently, technology for the various circuit boards on which these dies are mounted is also being developed.

[0004] To directly mount circuits on printed circuit boards, various interposer substrates have been developed and used. However, interposer substrates, primarily made of silicon, are expensive and pose challenges during the interposer mounting process.

[0005]

[0006] The present embodiment provides a circuit board and semiconductor package that facilitates the embedding of semiconductor elements in a cavity and enables miniaturization.

[0007]

[0008] A circuit board according to the present embodiment comprises: a build-up layer including a cavity formed on an upper surface; a connecting member arranged within the cavity; a plurality of second bumps arranged on the connecting member; and a protective layer arranged on the build-up layer, wherein the protective layer includes a protrusion arranged between the plurality of second bumps, and an upper surface of the protrusion is a concave surface.

[0009] The build-up layer may include a first insulating layer and a second insulating layer disposed below the first insulating layer, and the cavity may include a through-hole portion penetrating the first insulating layer and a recess portion penetrating a portion of the second insulating layer.

[0010] The above connecting member can be arranged to overlap the penetration portion and the recess portion along the horizontal direction.

[0011] A first vertical length along the vertical direction between the upper surface of the above-mentioned connecting member and the lower surface of the above-mentioned build-up layer may be greater than a second vertical length along the vertical direction between the upper surface of the above-mentioned first insulating layer and the lower surface of the above-mentioned build-up layer.

[0012] It includes a first bump arranged on the above build-up layer, wherein the first bump is arranged to be misaligned with the connecting member in the vertical direction, and the second bump can be arranged to overlap with the connecting member in the vertical direction.

[0013] The first bump is provided in plurality, and the horizontal width between the plurality of first bumps may be different from the horizontal width between the plurality of second bumps.

[0014] The horizontal width between the plurality of first bumps may be greater than the horizontal width between the plurality of second bumps.

[0015] The diameter of the first bump may be larger than the diameter of the second bump.

[0016] A third vertical length along the vertical direction between the upper surface of the first bump and the lower surface of the build-up layer may be the same as a fourth vertical length along the vertical direction between the upper surface of the second bump and the lower surface of the build-up layer.

[0017] A semiconductor package according to the present embodiment comprises: a build-up layer including a cavity formed on an upper surface; a connecting member disposed within the cavity; a first bump disposed on the build-up layer so as to be misaligned with the connecting member and including a first-first bump and a first-second bump; a second bump disposed on the build-up layer so as to overlap with the connecting member and including a second-first bump and a second-second bump; a first element connected to the first-first bump and the second-first bump; a second element connected to the first-second bump and the second-second bump; and a protective layer disposed on the build-up layer, wherein the protective layer includes a protrusion disposed between the second-first bump and the second-second bump, and an upper surface of the protrusion is a concave surface.

[0018]

[0019] In this embodiment, a cavity in a circuit board is implemented through multiple insulating layers, and the height of the connecting member is set higher than the height of the cavity, so that contact reliability can be secured when the connecting member is mounted.

[0020] Additionally, it has the advantage of being able to reduce the vertical height within the circuit board.

[0021] Additionally, since the connecting member can be placed closer to the upper surface of the build-up layer, the signal length between the connecting member and other elements can be reduced, which has the advantage of improving signal efficiency.

[0022] In addition, there is an advantage in that the height deviation between the first and second bumps based on the connecting member is reduced, so that the flatness of the element bonding area can be formed more uniformly.

[0023] Additionally, there is an advantage in that the semiconductor element can be more firmly fixed on the circuit board by increasing the contact area with the protective layer.

[0024]

[0025] Figure 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0026] Figure 2 is a plan view showing the upper surface of a circuit board according to an embodiment of the present invention.

[0027] Figures 3 to 8 are drawings illustrating a manufacturing process of a circuit board according to an embodiment of the present invention.

[0028] Figure 9 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0029] Fig. 10 is a modified example of a circuit board according to an embodiment of the present invention.

[0030]

[0031] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0032] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0033] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0034] In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and / or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

[0035] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0036] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0037] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0038] Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when it is expressed as "above or below", it can include the meaning of the downward direction as well as the upward direction based on one component.

[0039] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a plan view showing the upper surface of a circuit board according to an embodiment of the present invention, FIGS. 3 to 8 are drawings showing a manufacturing process of a circuit board according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0040] Referring to FIGS. 1 to 9, a circuit board (10) according to an embodiment of the present invention may include a build-up layer (12), a connecting member (630), and bumps (120, 160).

[0041] As illustrated in Fig. 9, the build-up layer (12) may include a first insulating layer (100), a second insulating layer (200), a third insulating layer (300), a fourth insulating layer (400), and a fifth insulating layer (500). Each of the first to fifth insulating layers (100, 200, 300, 400, 500) may include glass or plastic. The first to fifth insulating layers (100, 200, 300, 400, 500) may each include chemically strengthened / semi-strengthened glass such as sodalime glass or aluminosilicate glass, or may include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or may include sapphire.

[0042] The first to fifth insulating layers (100, 200, 300, 400, 500) are each formed of any insulator, such as a photocurable and / or thermosetting insulator. As a thermosetting insulator, an insulator in which inorganic and / or organic fillers are dispersed in a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a prepreg (PPG) including glass fibers in a resin can be used. In addition, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and the inorganic and / or organic fillers may be formed of a material such as silica or plastic. When an insulating resin is used as a core, a reinforcing material formed of glass fibers or aramid fibers can be included.

[0043] The above build-up layer (12) may include a circuit pattern and a via.

[0044] The circuit pattern may include a first circuit pattern (not shown) disposed on the first insulating layer (100), a second circuit pattern (210) disposed on the second insulating layer (200), a third circuit pattern (310) disposed on the third insulating layer (300), a fourth circuit pattern (410) disposed on the fourth insulating layer (400), and a fifth circuit pattern (510) disposed on the fifth insulating layer (500).

[0045] The first circuit pattern may be embedded in the upper surface of the first insulating layer (100). The first circuit pattern may be arranged to overlap with the penetration portion (122) of the first bump (120) described later in the horizontal direction. The first circuit pattern may include a plurality of metal patterns spaced apart in the horizontal direction.

[0046] The second circuit pattern (210) may be embedded in the upper surface of the second insulating layer (200). The second circuit pattern (210) may be electrically connected to the first circuit pattern and the third circuit pattern (310).

[0047] The third circuit pattern (310) may be embedded in the upper surface of the third insulating layer (300). The third circuit pattern (310) may be electrically connected to the second circuit pattern (210) and the fourth circuit pattern (410).

[0048] The fourth circuit pattern (410) may be embedded in the upper surface of the fourth insulating layer (400). The fourth circuit pattern (410) may be electrically connected to the third circuit pattern (310) and the fifth circuit pattern (510).

[0049] The fifth circuit pattern (510) may be embedded in the upper surface of the fifth insulating layer (500). The fifth circuit pattern (510) may be electrically connected to the fourth circuit pattern (410).

[0050] The above vias include a first via (112) arranged in the first insulating layer (100) to electrically connect the first bump (120) and the second circuit pattern (210), a second via (212) arranged in the second insulating layer (200) to electrically connect the second circuit pattern (210) and the third circuit pattern (310), a third via (312) arranged in the third insulating layer (300) to connect the third circuit pattern (310) and the fourth circuit pattern (410), a fourth via (412) arranged in the fourth insulating layer (400) to connect the fourth circuit pattern (410) and the fifth circuit pattern (510), and a fifth via (412) arranged in the fifth insulating layer (500) to have one end connected to the fifth circuit pattern (510) and a lower end connected to the It may include a fifth via (512) exposed to the lower surface of the fifth insulating layer (500).

[0051] The structure of the above-described build-up layer (12) is described as being implemented through a five-layer insulating layer, but is not limited thereto, and the build-up layer can be formed to have a circuit pattern and via of various layers and shapes according to the selection of a person skilled in the art.

[0052] The above-mentioned build-up layer (12) may include a cavity (150). The cavity (150) may be formed to be concave downward from the upper surface of the build-up layer (12) compared to other regions. The vertical height of the cavity (150) may be formed to be smaller than the vertical height of the connecting member (630).

[0053] The vertical height of the cavity (150) may be formed to be longer than the vertical thickness of the first insulating layer (100). The vertical height of the cavity (150) may be formed to be longer than the vertical height of each of the second to fifth insulating layers (120, 130, 140, 150).

[0054] As illustrated in FIG. 1, the cavity (150) may include a penetration portion (152) penetrating the first insulating layer (100) and a recess portion (154) formed concavely downward from the upper surface of the second insulating layer (200) compared to other regions.

[0055] The above penetration portion (152) may be a hole shape that penetrates from the upper surface to the lower surface of the first insulating layer (100). At least a portion of the connecting member (630) may be placed within the penetration portion (152).

[0056] The recessed portion (154) may be formed to penetrate at least a portion of the second insulating layer (200). The recessed portion (154) may have a recessed shape that is concave downward from the upper surface of the second insulating layer (200) compared to other regions. The recessed portion (154) may be arranged to overlap the penetrating portion (152) in the vertical direction. The recessed portion (154) may be in communication with the penetrating portion (152). The lower surface of the recessed portion (154) may form the bottom surface of the cavity (150). The lower surface of the recessed portion (154) may be an internal region of the second insulating layer (200). The cross-sectional area of ​​the recessed portion (154) may be the same as the cross-sectional area of ​​the through portion (152), but, conversely, the cross-sectional area of ​​the recessed portion (154) may be smaller than the cross-sectional area of ​​the through portion (152).

[0057] The vertical height of the recessed portion (154) may be smaller than the vertical height of the through portion (152). Accordingly, warpage of the circuit board (10) may be minimized.

[0058] The above connecting member (630) may be arranged within the cavity (150). The connecting member (630) may be arranged to overlap the through-hole (152) and the recessed portion (154) in a horizontal direction. The lower surface of the connecting member (630) is supported by the bottom surface of the cavity (150), and the upper surface of the connecting member (630) may be arranged above the upper surface of the through-hole (152). The upper surface of the connecting member (630) may be arranged so as not to overlap the first insulating layer (100) in the horizontal direction. A pad (not shown) or a circuit pattern may be formed between the lower surface of the connecting member (630) and the bottom surface of the cavity (150). An adhesive member may be placed between the lower surface of the above connecting member (630) and the bottom surface of the cavity (150), and for example, the adhesive member may be a DAF (Die Attach Film).

[0059] As the vertical height of the connecting member (630) is formed to be greater than the vertical height of the cavity (150), the first vertical length along the vertical direction between the upper surface of the connecting member (630) and the lower surface of the build-up layer (12) may be greater than the second vertical length along the vertical direction between the upper surface of the first insulating layer (100) and the lower surface of the build-up layer (12).

[0060] The above connecting member (630) may be an interposer that electrically connects the first element (610) and the second element (620) within the semiconductor package, as illustrated in FIG. 9. In this case, the connecting member (630) may be referred to as a bridge, as it has the function of electrically connecting the first element (610) and the second element (620). In this case, the connecting member (630) may be a Si bridge and / or an organic bridge.

[0061] Alternatively, the connecting member (630) may include an active element or a passive element, and thus may include a transistor, an IC semiconductor chip, a capacitor, a resistor, an inductor, and the like. In this case, the connecting member (630) may also be referred to as a semiconductor element.

[0062]

[0063] The circuit board (10) may include bumps (120, 160). The bumps (120, 160) may include a first bump (120) disposed on the upper surface of the first insulating layer (100), and a second bump (160) disposed in an area of ​​the upper surface of the first insulating layer (100) different from the area where the first bump (120) is disposed. At least a portion of the second bump (160) may be disposed within the cavity (150). The second bump (160) may be disposed on the connecting member (630).

[0064] The first bump (120) may be arranged so as not to overlap the connecting member (630) in the vertical direction. The second bump (160) may be arranged so as to overlap the connecting member (630) in the vertical direction.

[0065] The first bumps (120) may be provided in plurality and may be arranged to be spaced apart from each other in the horizontal direction on the build-up layer (12). For example, the first bumps (120) may be arranged two on each side of the cavity (150). As illustrated in FIG. 9, the first elements (610) may be coupled to the plurality of first bumps (120) arranged on one side of the cavity (150). The second elements (620) may be coupled to the plurality of first bumps (120) arranged on the other side of the cavity (150). The plurality of first bumps (120) to which the first elements (610) are coupled may be referred to as 1-1 bumps. The plurality of first bumps (120) to which the second elements (620) are coupled may be referred to as 1-2 bumps.

[0066] The first bump (120) may be placed on the first insulating layer (100). The first bump (120) may be formed of a metal material. For example, the material of the first bump (120) may be copper (Cu).

[0067] The first bump (120) may be arranged so that at least a portion thereof is embedded within the first insulating layer (100), and another portion thereof protrudes upwardly through the upper surface of the first insulating layer (100).

[0068] In more detail, the first bump (120) may include a penetration portion (122) disposed between the upper surface of the first insulating layer (100) and the lower surface of the first insulating layer (100), and a protrusion portion (124) disposed on the upper surface of the first insulating layer (100) and protruding upward from the penetration portion (122). The horizontal width of the penetration portion (122) may be larger than the horizontal width of the protrusion portion (124). However, this is exemplary, and the horizontal width of the penetration portion (122) may be the same as the horizontal width of the protrusion portion (124).

[0069] The upper surface of the first bump (120) may include a flat surface (not shown) and a curved surface (not shown). Here, the upper surface of the first bump (120) may be the upper surface of the protrusion (124). The flat surface may be arranged at the center of the upper surface of the first bump (120), and the curved surface may be arranged at the edge of the upper surface of the first bump (120). The curved surface may have a predetermined curvature. The curved surface has the advantage of preventing light scattering in an AOI (Automatic Optical Inspection) inspection compared to a conventional square pillar-shaped bump.

[0070] The second bump (160) may be disposed on the connecting member (630). The second bump (160) may be electrically connected to the connecting member (630). The second bump (160) may be provided in plurality and may be disposed to be spaced apart from each other along the horizontal direction of the circuit board (10). One bump among the plurality of second bumps (160) may be disposed relatively close to the 1-1st bump, and another bump may be disposed relatively close to the 1-2nd bump. One bump among the plurality of second bumps (160) may be electrically connected to the first element (610), and another bump among the plurality of second bumps (160) may be electrically connected to the second element (620). The second bump (160) connected to the first element (610) together with the first-1 bump may be named the second-1 bump, and the second bump (160) connected to the second element (620) together with the first-2 bump may be named the second-2 bump.

[0071] The vertical length (L1) from the upper surface of the first insulating layer (100) to the upper surface of the second bump (160) may be the same as the vertical length (L2) from the upper surface of the first insulating layer (100) to the upper surface of the first bump (120). The third vertical length along the vertical direction between the upper surface of the first bump (120) and the lower surface of the build-up layer (12) may be the same as the fourth vertical length along the vertical direction between the upper surface of the second bump (120) and the lower surface of the build-up layer (12).

[0072] The diameter of the first bump (120) may be larger than the diameter of the second bump (160). Here, the diameter of the first bump (120) may be the diameter of the upper surface of the first bump (120), and the diameter of the second bump (160) may be the diameter of the upper surface of the second bump (160).

[0073] The spacing between the plurality of first bumps (120) and the spacing between the plurality of second bumps (160) may be different from each other. Here, the spacing may be a horizontal width between the centers of each bump (120, 160), as illustrated in FIG. 2. Accordingly, the horizontal width (D2) between the plurality of first bumps (120) may be greater than the horizontal width (D1) between the plurality of second bumps (160).

[0074] A protective layer (180) may be disposed on the upper surface of the build-up layer (12), that is, the upper surface of the first insulating layer (100). The protective layer (180) may be disposed to surround the side surface of the first bump (120) and the side surface of the second bump (160) protruding upward from the upper surface of the first insulating layer (100). When a semiconductor element is disposed on the circuit board (10) using a material such as solder, the protective layer (180) may function to prevent a short circuit between solders due to low wettability with the solder. The protective layer (180) may use a photocurable insulating material. For example, the protective layer (180) may use a solder resist.

[0075] As illustrated in FIG. 1, the protective layer (180) may include a protrusion (185) positioned between a plurality of second bumps (160). The upper surface of the protrusion (185) may be positioned to be higher than the upper surface of another region within the protective layer (180). The upper surface of the protrusion (185) may be a concave surface (186) having a concave shape downward.

[0076] FIG. 10 illustrates a modified example of a circuit board according to an embodiment of the present invention. Referring to FIG. 10, the upper surface of the protrusion (185) may be a convex surface (187) having an upwardly convex shape.

[0077] According to the structure as described above, the cavity (150) in the circuit board (10) is implemented through a plurality of insulating layers, and the height of the connecting member (630) is set higher than the height of the cavity (150), so that contact reliability can be secured when the connecting member (630) is mounted.

[0078] In addition, there is an advantage in that the vertical height within the circuit board (10) can be reduced.

[0079] In addition, since the connecting member (630) can be placed closer to the upper surface of the build-up layer, the signal length between the connecting member (630) and other elements can be reduced, which has the advantage of improving signal efficiency.

[0080] In addition, there is an advantage in that the height deviation between the first bump (120) and the second bump (160) based on the connecting member (630) is reduced, so that the flatness of the element bonding area can be formed more uniformly.

[0081] Additionally, there is an advantage in that the semiconductor element can be more firmly fixed on the circuit board by increasing the contact area with the protective layer.

[0082] When explaining the manufacturing process of the circuit board (10), first, as illustrated in FIG. 3, a sacrificial layer (40) is placed on one surface of the core layer (20) under the interposition of a metal layer (30), thereby forming plating of the circuit board (10). In this case, the sacrificial layer (40) may include a flat portion (41) placed on one surface of the core layer (20) and a protrusion (42) protruding from one surface of the flat portion (41). A cavity (150) in the circuit board (10) may be implemented through the protrusion (42).

[0083] The material of the above sacrificial layer (40) may be nickel (Ni), and the strength of the above sacrificial layer (40) may be reinforced through the core layer (20) of a different metal material from the above sacrificial layer (40).

[0084] Next, as illustrated in FIG. 4, a circuit pattern for forming a first bump (120) can be patterned on the surface of the flat portion (41) within the sacrificial layer (40). In this case, a metal area for forming the through portion (122) of the first bump (120) can be patterned on the surface of the flat portion (41).

[0085] Next, as illustrated in FIG. 5, the build-up layer (12) may be formed on the surface of the sacrificial layer (40) on which the metal area for forming the penetration portion (122) is patterned. In this case, the penetration portion (122) may be formed on the surface of the build-up layer (12).

[0086] In addition, the cavity (150) can be implemented within the surface of the build-up layer (12) by the protrusion (42) of the sacrificial layer (40). Meanwhile, by forming the cavity (150) through the sacrificial layer (40), the flatness of the cavity (150) can be easily controlled, the filler within the build-up layer (12) can be prevented from being exposed to the outside through the inner surface of the cavity (150), and there is an advantage in that a separate structure such as a stopper can be omitted during the cavity forming process.

[0087] Next, as shown in FIGS. 6 and 7, the core layer (20) is separated from the surface of the sacrificial layer (40), and the sacrificial layer (40) is removed from the surface of the build-up layer (12) by etching, so that the build-up layer (12) in which the cavity (150) and the through-hole (122) are implemented can be formed.

[0088] Afterwards, as shown in FIG. 8, after placing the connecting member (630) in the cavity (150), the protrusion (124) of the first bump (120) is additionally formed, the second bump (160) is formed on the connecting member (630), and the protective layer (180) is formed, so that the circuit board (10) can be finally implemented as in FIG. 1.

[0089] Although all components constituting the embodiments of the present invention have been described above as being combined or operating in combination, the present invention is not necessarily limited to these embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal sense, unless explicitly defined in the present invention.

[0090] The above description is merely an illustrative description of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of ​​the present invention, and the scope of the technical idea of ​​the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. A build-up layer including a cavity formed on the upper surface; A connecting member arranged within the above cavity; A plurality of second bumps arranged on the above connecting member; and Including a protective layer disposed on the above build-up layer, The above protective layer includes a protrusion disposed between the plurality of second bumps, A circuit board in which the upper surface of the above protrusion is a concave surface.

2. In paragraph 1, The above build-up layer includes a first insulating layer and a second insulating layer disposed below the first insulating layer, A circuit board wherein the cavity includes a through-hole penetrating the first insulating layer and a recess penetrating a portion of the second insulating layer.

3. In paragraph 2, A circuit board in which the above connecting member is arranged to overlap the above penetration portion and the above recess portion in a horizontal direction.

4. In paragraph 2, A circuit board in which a first vertical length along the vertical direction between the upper surface of the above-mentioned connecting member and the lower surface of the above-mentioned build-up layer is longer than a second vertical length along the vertical direction between the upper surface of the above-mentioned first insulating layer and the lower surface of the above-mentioned build-up layer.

5. In paragraph 1, Including a first bump arranged on the above build-up layer, The above first bump is positioned so as to be misaligned with the connecting member in the vertical direction, A circuit board in which the second bump is arranged to overlap the connecting member in a vertical direction.

6. In paragraph 5, Equipped with the above first bump plurality, A circuit board wherein the horizontal width between the plurality of first bumps is different from the horizontal width between the plurality of second bumps.

7. In paragraph 6, A circuit board wherein the horizontal width between the plurality of first bumps is greater than the horizontal width between the plurality of second bumps.

8. In paragraph 6, A circuit board wherein the diameter of the first bump is larger than the diameter of the second bump.

9. In paragraph 5, A circuit board wherein a third vertical length along the vertical direction between the upper surface of the first bump and the lower surface of the build-up layer is the same as a fourth vertical length along the vertical direction between the upper surface of the second bump and the lower surface of the build-up layer.

10. A build-up layer including a cavity formed on the upper surface; A connecting member arranged within the above cavity; A first bump arranged misaligned with the connecting member on the above build-up layer and including a first-1 bump and a first-2 bump; A second bump, which is arranged to overlap the connecting member on the above build-up layer and includes a second-1 bump and a second-2 bump; A first element connected to the above 1-1 bump and the above 2-1 bump; A second element connected to the above 1-2 bump and the above 2-2 bump; and Including a protective layer disposed on the above build-up layer, The above protective layer includes a protrusion positioned between the 2-1 bump and the 2-2 bump, A semiconductor package in which the upper surface of the above protrusion is a concave surface.

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