Shift register, gate driving circuit, driving method, and display apparatus

Abstract

Disclosed is a shift register (100), comprising an input sub-circuit (10), an output sub-circuit (20), a reset sub-circuit (30), and a denoising sub-circuit. The denoising sub-circuit comprises a pull-down control sub-circuit (41), a pull-down denoising sub-circuit (42) and a reset denoising sub-circuit (43), wherein the pull-down control sub-circuit (41) is connected to a first power-supply voltage signal end (VDD) and a pull-down node (PD), the pull-down denoising sub-circuit (42) is connected to the pull-down node (PD), a pull-up node (PU), a second power-supply voltage signal end (VG) and an output signal end (Gout), and the reset denoising sub-circuit (43) is connected to a second reset signal end (TRST), the pull-up node (PU), the second power-supply voltage signal end (VG) and the output signal end (Gout).

Description

Shift register, gate drive circuit, drive method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a driving method, and a display device. Background Art

[0002] As a prime example of next-generation information technology convergence and innovation, virtual reality (VR) is experiencing increasing maturity in key technologies, rapid market development, and a rapidly growing market. In recent years, the global commercialization of VR has become increasingly diverse. Beyond familiar applications like gaming and entertainment, VR has gradually expanded into new sectors such as healthcare, education, and manufacturing, with increasing industry penetration. Display technology is rapidly evolving, and traditional LCD (Liquid Crystal Display) technology has matured. With the rise of VR products, the application of LCD products in VR has brought new technological developments and vitality to the LCD field. LCDs currently utilize a 1T or 2T pixel circuit design, where the T stands for thin-film transistor (TFT). This design is relatively simple and can achieve ultra-high pixel density (PPI). This offers advantages over organic light-emitting diode (OLED) display technology, and LCD's mature process technology also offers cost advantages. Today, VR display technology in the LCD field has completed mass production of 1200PPI-level products and has reserved 1500PPI technology; with the increase in VR market demand, the speed of technology iteration has accelerated, and there is an urgent need for the implementation of PPI technology above 2000, including corresponding Real RGB pixel design, optical innovation and more sophisticated process technology.

[0003] The substrate (base) process of VR display products can be LTPS (Low Temperature Poly-Silicon) or LTPO (Low Temperature Polycrystalline Oxide). Taking the cost into consideration, the oxide Oixde process is one of the future development directions. Among them, the design of Oixde pixel has been solved in LTPO, and the peripheral drive, especially the GOA circuit (Gate on Array, gate integrated drive circuit) adopts Oxide design. However, the main problem at present is that the Oxide GOA circuit uses a relatively larger number of TFTs than LTPS, so the GOA circuit is more complicated, resulting in an increase in the border of the display product. As a wearable display, the border size of VR products directly affects the user's wearing experience, so the requirements for the border are relatively strict, which is also one of the main factors restricting the application of Oxide GOA drive in VR products.

[0004] Summary of the Invention

[0005] By utilizing one or more embodiments of the present disclosure, the technical problem that the oxide GOA circuit requires a wider border and cannot meet the narrow border requirement of display products is solved.

[0006] In a first aspect, the present disclosure provides the following technical solutions through an embodiment:

[0007] A shift register, comprising an input subcircuit, an output subcircuit, a reset subcircuit and a denoising subcircuit; the input subcircuit is respectively connected to an input signal terminal and a pull-up node, and is used to write an input signal to the pull-up node under the control of an input signal of the input signal terminal; the output subcircuit is respectively connected to a clock signal terminal, the pull-up node and an output signal terminal, and is used to output a clock signal of the clock signal terminal to the output signal terminal under the control of an input signal of the pull-up node; the reset subcircuit is respectively connected to a first reset signal terminal, the pull-up node and a second power supply voltage signal terminal, and is used to reset the pull-up node through a second power supply voltage signal of the second power supply voltage signal terminal under the control of a first reset signal of the first reset signal terminal; the denoising subcircuit comprises a pull-down control subcircuit, a pull-down denoising subcircuit and a pull-down denoising subcircuit. circuit and a reset denoising subcircuit; the pull-down control subcircuit is respectively connected to the first power supply voltage signal terminal and the pull-down node, and is used to write the first power supply voltage signal of the first power supply voltage signal terminal into the pull-down node; the pull-down denoising subcircuit is respectively connected to the pull-down node, the pull-up node, the second power supply voltage signal terminal and the output signal terminal, and is used to discharge the pull-up node and the output signal terminal through the second power supply voltage signal terminal under the control of the first power supply voltage signal of the pull-down node; the reset denoising subcircuit is respectively connected to the second reset signal terminal, the pull-up node, the second power supply voltage signal terminal and the output signal terminal, and is used to discharge the pull-up node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal of the second reset signal terminal.

[0008] In some embodiments, the second power supply voltage signal terminal includes a first low-level signal terminal and a second low-level signal terminal; the second power supply voltage signal includes a first low-level signal of the first low-level signal terminal and a second low-level signal of the second low-level signal terminal, and the voltage of the first low-level signal is lower than the voltage of the second low-level signal; the reset sub-circuit is connected to the first low-level signal terminal, and is used to reset the pull-up node through the first low-level signal terminal under the control of a first reset signal of the first reset signal terminal; the pull-down denoising sub-circuit is connected to the first low-level signal terminal and the second low-level signal terminal, and is used to discharge the pull-up node through the first low-level signal terminal and discharge the output signal terminal through the second low-level signal terminal under the control of the first power supply voltage signal of the pull-down node; the reset denoising sub-circuit is connected to the first low-level signal terminal and the second low-level signal terminal, and is used to discharge the pull-up node through the first low-level signal terminal and discharge the output signal terminal through the second low-level signal terminal under the control of the second reset signal of the second reset signal terminal.

[0009] In some embodiments, the pull-down control subcircuit includes a first transistor, and the pull-down denoising subcircuit includes a second transistor and a third transistor; the first electrode of the first transistor is connected to the first power supply voltage signal end, the control electrode is connected to the first electrode, and the second electrode is connected to the pull-down node, and is used to be turned on under the control of the first power supply voltage signal end, and the first power supply voltage signal of the first power supply voltage signal end is written to the pull-down node; the first electrode of the second transistor is connected to the pull-up node, the second electrode is connected to the first low-level signal end, and the control electrode is connected to the pull-down node, and is used to be turned on under the control of the first power supply voltage signal of the pull-down node, and discharge the pull-up node; the first electrode of the third transistor is connected to the output signal end, the second electrode is connected to the second low-level signal end, and the control electrode is connected to the pull-down node, and is used to be turned on under the control of the first power supply voltage signal of the pull-down node, and discharge the output signal end.

[0010] In some embodiments, the reset denoising sub-circuit includes a fourth transistor and a fifth transistor; the first electrode of the fourth transistor is connected to the pull-up node, the control electrode is connected to the second reset signal end, and the second electrode is connected to the first low-level signal end, and is used to be turned on under the control of the second reset signal at the second reset signal end, and discharge the pull-up node; the first electrode of the fifth transistor is connected to the output signal end, the control electrode is connected to the second reset signal end, and the second electrode is connected to the second low-level signal end, and is used to be turned on under the control of the second reset signal at the second reset signal end, and discharge the output signal end.

[0011] In some embodiments, the denoising sub-circuit further includes a sixth transistor and a seventh transistor; the first electrode of the sixth transistor is connected to the pull-down node, the second electrode is connected to the first low-level signal end, and the control electrode is connected to the pull-up node, and is used to be turned on under the control of the input signal of the pull-up node, and discharge the pull-down node through the first low-level signal end; the first electrode of the seventh transistor is connected to the pull-down node, the control electrode is connected to the input signal end, and the second electrode is connected to the first low-level signal end, and is used to be turned on under the control of the input signal end, and discharge the pull-down node through the first low-level signal end.

[0012] In some embodiments, the input sub-circuit includes an eighth transistor, the first electrode of the eighth transistor is connected to the input signal terminal, the second electrode is connected to the pull-up node, and the control electrode is connected to the first electrode; the reset sub-circuit includes a ninth transistor, the first electrode of the ninth transistor is connected to the pull-up node, the second electrode is connected to the first low-level signal terminal, and the control electrode is connected to the first reset signal terminal; the output sub-circuit includes a tenth transistor and a capacitor, the first electrode of the tenth transistor is connected to the clock signal terminal, the second electrode is connected to the output signal terminal, and the control electrode is connected to the pull-up node; one end of the capacitor is connected to the pull-up node, and the other end is connected to the output signal terminal.

[0013] In some embodiments, the control electrode of the tenth transistor includes a first gate and a second gate, and the first gate and the second gate are connected to the pull-up node.

[0014] In a second aspect, based on the same inventive concept, the present disclosure provides the following technical solutions through an embodiment:

[0015] A gate drive circuit includes a plurality of cascaded shift registers provided by the first aspect embodiment.

[0016] In some embodiments, the multiple cascaded shift registers are divided into M driving partitions, M>1 and is an integer; in the same driving partition, the output signal end of the i-th shift register is respectively connected to the input signal end of the i+1-th shift register and the first reset signal end of the i-1-th shift register, i is an integer between 2 and N-1, N≥3 and is an integer; the gate driving circuit also includes M first power supply voltage signal lines and M reset signal lines, and one driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register in the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register in the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition.

[0017] In a third aspect, based on the same inventive concept, the present disclosure provides the following technical solutions through an embodiment:

[0018] A driving method for a gate drive circuit is applied to the gate drive circuit provided by an embodiment of the second aspect, the driving method comprising: controlling an input signal terminal to input an input signal so that the input subcircuit writes the input signal to the pull-up node; controlling a clock signal terminal to input a clock signal so that the output subcircuit outputs the clock signal to the output signal terminal under the control of the input signal of the pull-up node; controlling a first reset signal terminal to input a first reset signal so that the reset subcircuit resets the pull-up node through a second power supply voltage signal at the second power supply voltage signal terminal; and controlling the first power supply voltage signal terminal to input a first power supply voltage signal so that the pull-down control subcircuit writes the first power supply voltage signal to the pull-down node, and the pull-down denoising subcircuit discharges the pull-up node and the output signal terminal through the second power supply voltage signal terminal; or controlling the second reset signal terminal to input a second reset signal so that the reset denoising subcircuit discharges the pull-up node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

[0019] In some embodiments, the plurality of cascaded shift registers are divided into M driving partitions, and the gate driving circuit further includes M first power supply voltage signal lines and M reset signal lines, and one driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register of the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register of the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition; the driving method includes: in a time period of [(j-1)T / M, jT / M], controlling the first power supply voltage signal line corresponding to the j-th driving partition to input the first power supply voltage signal, and the reset signal lines corresponding to the remaining driving partitions to input the second reset signal; T is the display period of one frame, and j is an integer ranging from 1 to M in sequence.

[0020] In a fourth aspect, based on the same inventive concept, the present disclosure provides the following technical solutions through an embodiment:

[0021] An array substrate includes: a base substrate including a display area and a peripheral area; and a plurality of cascaded shift registers provided by the first embodiment arranged in the peripheral area.

[0022] In some embodiments, no more than two columns of the shift registers are arranged in a peripheral area on the same side of the display area, and the area where each column of shift registers is located includes a first sub-area and a second sub-area, the input sub-circuit, the reset sub-circuit and the denoising sub-circuit are located in the first sub-area, and the output sub-circuit is located in the second sub-area, and the second sub-area is closer to the display area than the first sub-area; the denoising sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor, the input sub-circuit includes an eighth transistor, and the reset sub-circuit includes a ninth transistor; the array substrate also includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line and a reset signal line, and the second power supply voltage signal line includes a first low-level signal line and a second low-level signal line; in the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence; the first transistor is arranged on a side of the first power supply voltage signal line away from the second sub-region, the fourth transistor and the second transistor are arranged on a side of the reset signal line close to the second sub-region, the seventh transistor and the sixth transistor are arranged on a side of the first low-level signal line away from the second sub-region, the eighth transistor and the ninth transistor are arranged on a side of the first low-level signal line close to the second sub-region, and the fifth transistor and the third transistor are arranged on a side of the second low-level signal line close to the second sub-region.

[0023] In some embodiments, the output sub-circuit includes a tenth transistor and a capacitor, and in a column direction of a column of the shift register, the tenth transistor and the capacitor are alternately arranged in sequence.

[0024] In some embodiments, a channel width-to-length ratio W:L of the tenth transistor is 120-300:5, where W is the channel width and L is the channel length.

[0025] In some embodiments, the channel of the tenth transistor includes a plurality of sub-channels connected in series, and a width-to-length ratio W:L of each sub-channel is 20:5.

[0026] In a fifth aspect, based on the same inventive concept, the present disclosure provides the following technical solutions through an embodiment:

[0027] A display device includes the array substrate provided by the fourth embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1A shows a schematic diagram of a vertical layout of a shift register;

[0029] FIG1B shows a schematic diagram of an 18T1C shift register;

[0030] FIG1C shows a schematic diagram of timing control corresponding to the shift register of FIG1B ;

[0031] FIG2 shows a wireframe diagram of a shift register provided according to some embodiments of the present disclosure;

[0032] FIG3 shows a schematic structural diagram of a 10T1C shift register provided according to some embodiments of the present disclosure;

[0033] FIG4 shows a schematic diagram of the cascade relationship and corresponding timing control of gate driving circuits of two driving partitions provided according to some embodiments of the present disclosure;

[0034] FIG5 shows a schematic diagram of a timing control simulation of a gate drive circuit according to some embodiments of the present disclosure;

[0035] FIG6 shows a schematic diagram of the layout of a shift register in a peripheral area according to some embodiments of the present disclosure;

[0036] FIG7 shows a schematic diagram of the layout of sub-circuit modules in a shift register according to some embodiments of the present disclosure;

[0037] FIG8 shows a circuit layout of an input subcircuit, a reset subcircuit, and a denoising subcircuit according to some embodiments of the present disclosure;

[0038] FIG9 shows a circuit layout of an output sub-circuit provided according to some embodiments of the present disclosure;

[0039] FIG10 shows a schematic structural diagram of a tenth transistor with a dual-gate structure provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0041] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0043] Currently, LTPS or LTPO processes are commonly used in 1000PPI and 1500PPI pixel designs. When the LTPS process is used in the GOA drive part, the GOA unit in the LTPS GOA circuit, that is, the shift register, can adopt an 8T2C (including 8 transistors and 2 capacitors) structure and use unilateral alternating drive to achieve a border width of ≤1.2mm. However, for the oxide process, the GOA unit often adopts an 18T1C structure. For oxide GOA units with high mobility requirements, the structure has reached 23T2C. Compared with the 8T2C commonly used in LTPS GOA, the 18T1C structure currently commonly used in oxide GOA doubles the number of TFTs, and the border width naturally increases significantly.

[0044] In addition to the limitations of the GOA circuit, the GOA circuit design of ultra-high PPI VR products is also affected by the pitch. Table 1 lists the pixel pitch (pixel pitch) and GOA pitch (GOA pitch) of 1200PPI, 1500PPI and 2117PPI. It can be seen that the higher the PPI, the smaller the pixel pitch; if the GOA circuit adopts unilateral alternating drive, the GOA pitch is twice the pixel pitch. Therefore, the higher the PPI, the smaller the GOA pitch, and the smaller the vertical space of the GOA layout in the border area. Layout can only be performed by stretching the horizontal space, which leads to an increase in the border of the product. Among them, the vertical direction can be the column direction of the pixel array on the display substrate or display panel, and the horizontal direction can be the row direction of the pixel array.

[0045] Table 1: Pixel pitch and GOA pitch corresponding to different PPI products:

[0046] For example, for the 2117 PPI product in Table 1, its real RGB design pixel arrangement is 4×12; the vertical pixel pitch is 12 μm (micrometers), and the GOA pitch is 24 μm. In some embodiments, a delta arrangement with a 6×8 pixel arrangement can also be used to improve transmittance from a pixel design perspective. However, when using this design, the pixel pitch width is only 8 μm, and the corresponding GOA pitch, or vertical space, is only 16 μm, which will result in a serious problem of insufficient vertical space.

[0047] Specifically, please refer to Figure 1A. In the vertical space of the GOA layout, at least one thin-film transistor (TFT), one pull-up line (PU), and one pull-down line (PD) need to be set, and it is necessary to ensure that there is no short circuit between the lines. For example, for the current TFT channel length L of 5μm to 6μm design, the vertical pitch required to set a group of GOA units is at least d = 23μm, of which the pitch d1 occupied by the TFT is about 15.5μm, and the pitch d2 occupied by the PU and PD lines is about 7.5μm; while the GOA pitch currently designed with 2117PPI Delta is only 16μm, which is not enough to place a group of GOA units. This is the GOA layout and border problem caused by the PPI increase.

[0048] Figure 1B provides a circuit diagram of a stable and effective oxide GOA unit / shift register. The GOA unit is an 18T1C structure, consisting of 18 oxide thin-film transistors and a capacitor C. Its main architecture uses a pull-up node PU for output, and two pull-down nodes PD1 and PD2 for alternating discharge. The detailed circuit structure of the 18T1C includes:

[0049] The transistor M1A is connected to the high level signal terminal VDDO and the pull-down node PD1 respectively;

[0050] The transistor M1B is connected to the high level signal terminal VDDE and the pull-down node PD2 respectively;

[0051] The transistor M2A is connected to the pull-up node PU, the pull-down node PD1 and the low-level signal terminal LVGL respectively;

[0052] The transistor M2B is connected to the pull-up node PU, the pull-down node PD2 and the low-level signal terminal LVGL respectively;

[0053] The transistor M3A is connected to the output signal terminal Gout(n), the pull-down node PD1 and the low-level signal terminal VGL respectively;

[0054] The transistor M3B is connected to the output signal terminal Gout(n), the pull-down node PD2 and the low-level signal terminal VGL respectively;

[0055] The transistor M4 is connected to the pull-up node PU, the reset signal terminal TRST and the low-level signal terminal LVGL, respectively. The potential of LVGL is lower than that of VGL.

[0056] The transistor M6A is connected to the pull-down node PD1, the pull-up node PU and the low-level signal terminal LVGL respectively;

[0057] The transistor M6B is connected to the pull-down node PD2, the pull-up node PU and the low-level signal terminal LVGL respectively;

[0058] The transistor M7A is connected to the pull-down node PD1, the input signal terminal STV and the low-level signal terminal LVGL respectively;

[0059] The transistor M7B is connected to the pull-down node PD2, the input signal terminal STV and the low-level signal terminal LVGL respectively;

[0060] The transistor M8 is connected to the input signal terminal STV and the pull-up node PU respectively;

[0061] The transistor M9 is connected to the pull-up node PU, the reset signal terminal RST and the low-level signal terminal LVGL, respectively. The reset signal terminal RST may be the output signal terminal Gout(n+1) of the next-stage shift register.

[0062] The transistor M10 is connected to the clock signal terminal CLK, the pull-up node PU and the output signal terminal Gout(n);

[0063] The transistor M11 is connected to the clock signal terminal CLK, the pull-up node PU and the cascade output signal terminal Out_C(n);

[0064] The transistor M12A is connected to the cascade output signal terminal Out_C(n), the pull-down node PD1 and the low-level signal terminal LVGL respectively;

[0065] The transistor M12B is connected to the cascade output signal terminal Out_C(n), the pull-down node PD2 and the low-level signal terminal LVGL respectively;

[0066] The transistor M13 is connected to the output signal terminals Gout(n), Gout(n+1) and the low level signal terminal VGL respectively;

[0067] The capacitor C is connected to the pull-up node PU and the output signal terminal Gout(n) respectively.

[0068] The output signal terminal Gout(n) is used to output a light emitting control signal, and the output signal terminal Gout(n+1) is used to output an input signal (STV) to the next stage shift register and to output a reset signal (Reset) to the previous stage shift register.

[0069] Figure 1C provides the corresponding timing control diagram, including:

[0070] In the input phase t1, the input signal terminal STV is at a high level. Since the gate and drain of the transistor M8 are connected to form a diode structure, the transistor M8 is turned on and the potential of the pull-up node is pulled high.

[0071] In the output phase t2, the voltage of the pull-up node PU is further pulled up by the capacitor C, turning on the output transistor M10 and outputting the high-level signal of the clock signal terminal to the output signal terminal Gout(n);

[0072] In the reset phase t3, a high-level reset signal is input to the reset signal terminal RST, and the ninth transistor is turned on to reset the pull-up node PU.

[0073] In the t4 de-noising stage, during one frame display time, the high-level signal terminal VDDO or VDDE maintains a high-level power supply voltage signal output, and the drains of transistors M1A and M1B are connected to the gates to form a diode structure. Therefore, one of them is turned on according to the input signal of the corresponding power supply voltage terminal, and discharges the pull-up node PU and the output signal terminal Gout through the pull-down node PD1 or the pull-down node PD2 for de-noising.

[0074] Specifically, during a certain frame display time, the power supply voltage terminal VDDO inputs a high-voltage signal, transistor M1A turns on, and the power supply voltage terminal VDDO directly charges the pull-down node PD1. During operation, the pull-down node PD1 is kept at a high level, thereby using transistor M2A to discharge the pull-up node PU, keeping the pull-up node PU at a low potential state and reducing the noise of the GOA unit. During the next frame time, the power supply voltage terminal VDDE switches to a high level state, and the power supply voltage terminal VDDO switches to a low level state, switching to the pull-down node PD2 to operate, while the pull-down node PD1 is idle. The above-mentioned alternating operation of the pull-down nodes PD1 and PD2 can reduce the voltage stress of the related thin-film transistors (TFTs) such as transistors M1, M2, M12A, and M12B. Because the gates of these TFTs operate in a positive bias state for a long time, and the threshold voltage Vth of the oxide TFT itself is unstable due to voltage stress, it is easy to cause the threshold voltage Vth to drift too much, thereby affecting the normal operation of the GOA circuit and causing multiple output defects.

[0075] In order to solve this problem, in the first aspect, in an optional embodiment, please refer to Figure 2, which provides a shift register 100, including an input sub-circuit 10, an output sub-circuit 20, a reset sub-circuit 30 and a denoising sub-circuit; the input sub-circuit 10 is respectively connected to the input signal terminal INT and the pull-up node PU, and is used to write the input signal to the pull-up node PU under the control of the input signal of the input signal terminal INT; the output sub-circuit 20 is respectively connected to the clock signal terminal CLK, the pull-up node PU and the output signal terminal Gout, and is used to output the clock signal of the clock signal terminal CLK to the output signal terminal Gout under the control of the input signal of the pull-up node PU; the reset sub-circuit 30 is respectively connected to the first reset signal terminal RST, the pull-up node PU and the second power supply voltage signal terminal VG, and is used to reset the pull-up node PU through the second power supply voltage signal of the second power supply voltage signal terminal VG under the control of the first reset signal of the first reset signal terminal RST; The denoising sub-circuit includes a pull-down control sub-circuit 41, a pull-down denoising sub-circuit 42 and a reset denoising sub-circuit 43; the pull-down control sub-circuit 41 is respectively connected to the first power supply voltage signal terminal VDD and the pull-down node PD, and is used to write the first power supply voltage signal of the first power supply voltage signal terminal VDD into the pull-down node PD; the pull-down denoising sub-circuit 42 is respectively connected to the pull-down node PD, the pull-up node PU, the second power supply voltage signal terminal VG and the output signal terminal Gout, and is used to discharge the pull-up node PU and the output signal terminal Gout through the second power supply voltage signal terminal VG under the control of the first power supply voltage signal of the pull-down node PD; the reset denoising sub-circuit 43 is respectively connected to the second reset signal terminal TRST, the pull-up node PU, the second power supply voltage signal terminal VG and the output signal terminal Gout, and is used to discharge the pull-up node PU and the output signal terminal Gout through the second power supply voltage signal terminal VG under the control of the second reset signal of the second reset signal terminal TRST.

[0076] In the GOA (gate drive integration on array substrate) technology, a plurality of shift registers 100 (which may be referred to as GOA units) are cascaded to form a GOA circuit. Therefore, the input signal terminal INT of the current-stage shift register 100 circuit can be connected to the output signal terminal Gout or the cascade output terminal Out_C of the previous-stage shift register 100. Accordingly, the input signal can be the output signal of the previous-stage shift register 100, or the cascade output signal of the previous-stage shift register 100. Therefore, the output signal OutputN of the output signal terminal Gout can be used as a reset signal for the previous row and an input signal for the next row in addition to driving the pixels of the current row. In some embodiments, the first reset signal terminal RST connected to the reset subcircuit 30 can be connected to the output signal terminal Gout of the next-stage shift register 100, and the second reset signal terminal TRST connected to the reset denoising subcircuit 43 can be connected to an independently set reset signal line, and the second reset signal in the reset signal line is output from the timing controller.

[0077] The first power supply voltage signal terminal VDD and the second power supply voltage signal terminal VG are operating voltage signals output by the power management integrated circuit (PMIC). For the GOA circuit, unless otherwise specified, the embodiment of the present disclosure takes the first power supply voltage signal as a high-level digital operating voltage signal DVDD and the second power supply voltage signal as a low-level gate-off voltage VGL as an example for description.

[0078] The timing control process of the shift register 100 can be:

[0079] 1) In the input phase, a valid input signal is input to the input signal terminal INT, so that the input sub-circuit 10 starts working and writes the input signal into the pull-up node PU;

[0080] 2) Output stage: under the control of the input signal of the pull-up node PU, the output sub-circuit 20 starts to work and outputs the clock signal of the clock signal terminal CLK as a valid output signal to the output signal terminal Gout;

[0081] 3) During the reset phase, the first reset signal terminal RST inputs a valid first reset signal to enable the reset sub-circuit 30 to operate and reset the pull-up node PU through the second power supply voltage signal terminal VG; and

[0082] 4) In the denoising stage, the pull-down denoising sub-circuit 42 or the reset denoising sub-circuit 43 can be selectively activated by the valid signal (input signal) at the pull-down node PD or the valid signal (second reset signal) at the second reset signal terminal TRST to perform discharge denoising on the pull-up node PU and the output signal terminal Gout.

[0083] The pull-down de-noising sub-circuit 42 is a circuit that performs discharge de-noising on the pull-up node PU and the output signal terminal Gout under the control of the pull-down node PD. The reset de-noising sub-circuit 43 is a circuit that performs discharge de-noising on the pull-up node PU and the output signal terminal Gout under the control of the second reset signal terminal TRST. Therefore, alternate discharge de-noising can be selectively achieved through the pull-down de-noising sub-circuit 42 or the reset de-noising sub-circuit 43. When a valid signal, such as a high-potential first power supply voltage signal, is written to the pull-down node PD, the pull-down de-noising sub-circuit 42 can be activated, utilizing the low-potential state of the second power supply voltage signal terminal VG to perform discharge de-noising on the pull-up node PU and the output signal terminal Gout. Alternatively, when a valid signal is input to the second reset signal terminal TRST, the reset de-noising sub-circuit 43 can be activated, utilizing the second power supply voltage signal terminal VG to perform discharge de-noising on the pull-up node PU and the output signal terminal Gout.

[0084] Therefore, the shift register 100 of some embodiments of the present disclosure only needs to use a set of pull-down nodes PD and corresponding denoising sub-circuits to achieve alternating discharge denoising of the pull-up node PU and the output signal terminal Gout. Compared with the solution of using two sets of pull-down nodes PD and corresponding denoising circuits for alternating discharge denoising, it can not only reduce the number of components of the denoising sub-circuit and reduce the border size of display products with high PPI requirements, but also avoid the performance drift of the circuit elements in the denoising sub-circuit due to being in a bias state for a long time, thereby improving the reliability performance of the shift register 100.

[0085] In some embodiments, the second power supply voltage signal terminal VG includes a first low-level signal terminal LVGL and a second low-level signal terminal VGL; the second power supply voltage signal includes a first low-level signal of the first low-level signal terminal LVGL and a second low-level signal of the second low-level signal terminal VGL, and the voltage of the first low-level signal is lower than the voltage of the second low-level signal; the reset sub-circuit 30 is connected to the first low-level signal terminal LVGL, and is used to reset the pull-up node PU through the first low-level signal terminal LVGL under the control of the first reset signal of the first reset signal terminal RST; the pull-down denoising sub-circuit 42 is connected to the first low-level signal The terminal LVGL and the second low-level signal terminal VGL are used to discharge the pull-up node PU through the first low-level signal terminal LVGL and discharge the output signal terminal Gout through the second low-level signal terminal VGL under the control of the first power supply voltage signal of the pull-down node PD; the reset denoising sub-circuit 43 is connected to the first low-level signal terminal LVGL and the second low-level signal terminal VGL, and is used to discharge the pull-up node PU through the first low-level signal terminal LVGL and discharge the output signal terminal Gout through the second low-level signal terminal VGL under the control of the second reset signal of the second reset signal terminal TRST.

[0086] In some embodiments, the potential of the first low-level signal can be -10V, and the potential of the second low-level signal can be -8V. By using the first low-level signal terminal LVGL with a lower potential to discharge the pull-up node PU, the effect of discharge denoising can be improved.

[0087] In some embodiments, referring to the shift register 100 shown in FIG. 3, the pull-down control sub-circuit 41 includes a first transistor M1, and the pull-down denoising sub-circuit 42 includes a second transistor M2 and a third transistor M3; a first pole of the first transistor M1 is connected to the first power supply voltage signal terminal VDD, a control pole is connected to the first pole, and a second pole is connected to the pull-down node PD, and is used to be turned on under the control of the first power supply voltage signal of the first power supply voltage signal terminal VDD to write the first power supply voltage signal of the first power supply voltage signal terminal VDD into the pull-down node PD; a first pole of the second transistor M2 is connected to the pull-up node PU, a second pole is connected to the first low-level signal terminal LVGL, and a control pole is connected to the pull-down node PD, and is used to be turned on under the control of the first power supply voltage signal of the pull-down node PD to discharge the pull-up node PU; a first pole of the third transistor M3 is connected to the output signal terminal Gout, a second pole is connected to the second low-level signal terminal VGL, and a control pole is connected to the pull-down node PD, and is used to be turned on under the control of the first power supply voltage signal of the pull-down node PD to discharge the output signal terminal Gout.

[0088] It should be noted that each transistor used in the shift register 100 can be a thin-film transistor (TFT) with an oxide as the active layer (Active). The control pole of each transistor is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetric in structure and can be considered to have no difference in structure, that is to say, the first pole and the second pole of the transistor in the embodiments of the present disclosure can have no difference in structure.

[0089] For example, corresponding to a P-type transistor, the first pole of the transistor is the source, the second pole is the drain, and the control pole is the gate; according to the conduction condition of the P-type transistor: Vg < Vs, Vgs - Vth < 0, where Vg is the gate voltage, Vs is the source voltage, Vgs is the gate-source voltage, and Vth is the threshold voltage; applying a low-level signal to the gate can turn on the transistor. Another example is that in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain, the second pole is the source, and the control pole is the gate; according to the conduction condition of the N-type transistor: Vg > Vs, Vgs - Vth > 0, it can be seen that applying a high-level signal to the gate can turn on the transistor. Unless otherwise specified, the embodiments of the present disclosure are described by taking an N-type transistor as an example.

[0090] After connecting the control electrode of the first transistor M1 to the first electrode, the first transistor M1 can be converted into a diode and turned on when a high-level first power supply voltage signal is input to the first power supply voltage signal terminal VDD, thereby writing the high-level first power supply voltage signal to the pull-down node PD. When the pull-down node PD is in a high-level state, the second transistor M2 and the third transistor M3, whose control electrodes are connected to the pull-down node PD, are turned on, thereby connecting the pull-up node PU to the first low-level signal terminal LVGL and the output signal terminal Gout to the second low-level signal terminal VGL, respectively. This maintains the pull-up node PU and the output signal terminal Gout at a low potential, achieving discharge noise reduction.

[0091] The reset denoising sub-circuit 43 performs discharge denoising on the pull-up node PU and the output signal terminal Gout under the control of the second reset signal terminal TRST. In some embodiments, referring to FIG3 , the reset denoising sub-circuit 43 includes a fourth transistor M4 and a fifth transistor M5. The fourth transistor M4 has a first electrode connected to the pull-up node PU, a control electrode connected to the second reset signal terminal TRST, and a second electrode connected to the first low-level signal terminal LVGL, and is configured to be turned on under the control of the second reset signal terminal TRST to discharge the pull-up node PU. The fifth transistor M5 has a first electrode connected to the output signal terminal Gout, a control electrode connected to the second reset signal terminal TRST, and a second electrode connected to the second low-level signal terminal VGL, and is configured to be turned on under the control of the second reset signal terminal TRST to discharge the output signal terminal Gout.

[0092] Therefore, the shift register 100 of some embodiments of the present disclosure can selectively perform discharge denoising on the pull-up node PU and the output signal terminal Gout through the second transistor M2 and the third transistor M3 of the pull-down denoising sub-circuit 42, or perform discharge denoising on the pull-up node PU and the output signal terminal Gout through the fourth transistor M4 and the fifth transistor M5 in the reset denoising sub-circuit 43. This can prevent some transistors in the pull-down denoising sub-circuit 42 or the reset denoising sub-circuit 43 from working in a biased state for a long time, thereby avoiding the threshold voltage Vth drift of the oxide transistor, which is beneficial to improving control accuracy and reducing control failures.

[0093] In some embodiments, the denoising sub-circuit further includes a sixth transistor M6 and a seventh transistor M7; the sixth transistor M6 has a first electrode connected to the pull-down node PD, a second electrode connected to the first low-level signal terminal LVGL, and a control electrode connected to the pull-up node PU, and is configured to be turned on under the control of an input signal of the pull-up node PU and discharge the pull-down node PD through the first low-level signal terminal LVGL; the seventh transistor M7 has a first electrode connected to the pull-down node PD, a control electrode connected to the input signal terminal INT, and a second electrode connected to the first low-level signal terminal LVGL, and is configured to be turned on under the control of the input signal terminal INT and discharge the pull-down node PD through the first low-level signal terminal LVGL. Therefore, the sixth transistor M6 and the seventh transistor M7 can form a pull-up denoising sub-circuit that performs discharge denoising on the pull-down node PD under the control of the pull-up node PU.

[0094] In some embodiments, the input sub-circuit 10 includes an eighth transistor M8 , wherein a first electrode of the eighth transistor M8 is connected to the input signal terminal INT, a second electrode is connected to the pull-up node PU, and a control electrode is connected to the first electrode. After the control electrode of the eighth transistor M8 is connected to the first electrode, it is converted into a diode structure, and can be turned on when a high-level input signal is input to the output signal terminal Gout, and turned off when the signal at the input signal terminal INT turns low.

[0095] In some embodiments, the reset sub-circuit 30 includes a ninth transistor M9, wherein a first electrode of the ninth transistor M9 is connected to the pull-up node PU, a second electrode is connected to the first low-level signal terminal LVGL, and a control electrode is connected to the first reset signal terminal RST. When the first reset signal terminal RST outputs a valid first reset signal, the ninth transistor M9 is turned on, resetting the pull-up node PU via the first low-level signal terminal LVGL.

[0096] In some embodiments, the output sub-circuit 20 includes a tenth transistor M10 and a capacitor C. The tenth transistor M10 has a first electrode connected to the clock signal terminal CLK, a second electrode connected to the output signal terminal Gout, and a control electrode connected to the pull-up node PU. One end of the capacitor C is connected to the pull-up node PU, and the other end is connected to the output signal terminal Gout. When the pull-up node PU is in a high-level state, the tenth transistor M10 is turned on and outputs the high-level clock signal of the clock signal terminal CLK as the output signal to the output signal terminal Gout. Capacitor C can further increase the voltage of the pull-up node PU during the output phase through bootstrapping or coupling, thereby improving the stability of the signal output.

[0097] In combination with all the aforementioned embodiments, a shift register 100 with a 10T1C architecture and using oxide TFTs is provided. Compared to the discharge noise reduction of the dual pull-down nodes PD1 and PD2 of the 18T1C architecture, the 10T1C shift register 100 provided in the disclosed embodiments uses a single pull-down node PD for discharge, reducing the number of thin-film transistors by eight compared to the 18T1C architecture. Furthermore, the 10T1C shift register 100 omits the cascade output terminal Out_C and adds a fifth transistor M5 to form a reset noise reduction sub-circuit 43. The first electrode (e.g., drain) of the fifth transistor M5 is connected to the output signal terminal Gout, the second electrode (e.g., source) is connected to the second low-level signal terminal VGL, and the control electrode (e.g., gate) is connected to the second reset signal terminal TRST. Discharge noise reduction of the output signal terminal Gout can be achieved through the second reset signal terminal TRST.

[0098] Compared to the 18T1C shift register 100, the 10T1C achieves transistor reduction primarily by eliminating a set of pull-down nodes PD and the corresponding noise reduction transistors, achieving noise reduction through a single pull-down node PD. However, if a single pull-down node PD is consistently used for discharge noise reduction, the threshold voltage Vth drift of the associated first transistor M1, second transistor M2, and third transistor M3 under long-term bias conditions will occur, significantly reducing the reliability of the GOA circuit. Therefore, within a single frame display cycle, discharge noise reduction can be performed by the pull-down noise reduction sub-circuit 42 controlled by the pull-down node PD for a portion of the time, and by the reset noise reduction sub-circuit 43 controlled by the second reset signal terminal TRST for the remaining time, effectively improving this problem.

[0099] Therefore, in the second aspect, based on the same inventive concept, in another optional embodiment, a gate drive circuit (GOA circuit) is provided, comprising a plurality of cascaded shift registers 100 provided in the embodiment of the first aspect. The cascading method can be that the shift registers 100 (GOA units) of adjacent rows are cascaded in sequence, or that the shift registers 100 separated by a certain number of rows are cascaded, which is not limited here. When cascading, the output signal terminal Gout of the shift register 100 of the current stage is not only connected to the light-emitting control circuit EM GOA of the current row, but also connected to the input signal terminal INT of the shift register 100 of the next stage and the first reset signal terminal RST of the shift register 100 of the previous stage.

[0100] Accordingly, in some embodiments, a timing control method for a gate driving circuit includes:

[0101] 1) Input stage: controlling the input signal terminal INT to input the input signal so that the input sub-circuit 10 writes the input signal into the pull-up node PU;

[0102] 2) Output stage: Control the clock signal terminal CLK to input the clock signal, so that the output sub-circuit 20 outputs the clock signal to the output signal terminal Gout under the control of the input signal of the pull-up node PU;

[0103] 3) Reset stage: controlling the first reset signal terminal RST to input the first reset signal, so that the reset sub-circuit 30 resets the pull-up node PU through the second power supply voltage signal of the second power supply voltage signal terminal VG; and

[0104] 4) De-noising stage: Control the first power supply voltage signal terminal VDD to input the first power supply voltage signal, so that the pull-down control sub-circuit 41 writes the first power supply voltage signal to the pull-down node PD, and the pull-down de-noising sub-circuit 42 discharges the pull-up node PU and the output signal terminal Gout through the second power supply voltage signal terminal VG; or, control the second reset signal terminal TRST to input the second reset signal, so that the reset de-noising sub-circuit 43 discharges the pull-up node PU and the output signal terminal Gout through the second power supply voltage signal terminal VG under the control of the second reset signal.

[0105] It should be noted that the input signal, clock signal, first reset signal, second reset signal, and first power supply voltage signal in the above timing control process are effective signals for controlling the conduction of different types of transistors. For the GOA circuit using N-type transistors, the above effective signals are high-level signals, while for the GOA circuit using P-type transistors, the above effective signals are low-level signals.

[0106] In order to better improve the reliability performance of the GOA circuit, the cascade relationship and timing control can be improved. In some embodiments, multiple cascaded shift registers 100 are divided into M driving partitions, M>1 and is an integer; in the same driving partition, the output signal terminal Gout of the i-th stage shift register 100 is respectively connected to the input signal terminal INT of the i+1-th stage shift register 100 and the first reset signal terminal RST of the i-1-th stage shift register 100, i is an integer between 2 and N-1, N≥3 and is an integer; the gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, one driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal terminal TRST of each shift register 100 in the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal terminal VDD of each shift register 100 in the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition.

[0107] After the multiple shift registers 100 are divided into multiple driving partitions, the timing of the valid signals of the first power supply voltage signal line and the reset signal line corresponding to different driving partitions can be controlled to adjust whether each driving partition performs discharge denoising through the pull-down denoising sub-circuit 42 or the reset denoising sub-circuit 43, so as to reduce the problem of threshold voltage Vth drift caused by long-term bias of transistors related to the denoising sub-circuit.

[0108] In some embodiments, in the time period of [(j-1)T / M, jT / M], the first power supply voltage signal line corresponding to the j-th driving partition is controlled to input the first power supply voltage signal, and the reset signal lines corresponding to the remaining driving partitions are controlled to input the second reset signal; wherein T is the display period or display time of a frame of picture, and j is an integer ranging from 1 to M in sequence.

[0109] Specifically, in the display period T of each frame, the display period T is divided into corresponding sub-periods according to the number of drive partitions. In the jth sub-period, the first power supply voltage signal line of the jth drive partition is controlled to input a valid first power supply voltage signal, causing the pull-down denoising sub-circuit 42 to operate, discharging the pull-up node PU and the output signal terminal Gout through the pull-down node PD to perform denoising. The reset signal line corresponding to the jth drive partition does not output a valid signal, placing the reset denoising sub-circuit 43 in a rest state. For other drive partitions, the corresponding reset signal lines are controlled to output a valid second reset signal, while the first power supply voltage signal line does not output a valid signal, causing the reset denoising sub-circuit 43 to operate and the pull-down denoising sub-circuit 42 to rest. This prevents the threshold voltage Vth drift of the oxide TFT caused by long-term biasing.

[0110] For the sake of clarity, in an optional embodiment, the number of drive partitions M = 2 is used as an example for illustration. For a certain display product model, see the left portion of Figure 4 . A GOA circuit is composed of 2880 cascaded shift registers, divided into two drive partitions. The first drive partition DA1 corresponds to the GOA circuit for the upper half of the display product and includes shift registers 100 from stages 1 to 1440. The second drive partition DA2 corresponds to the GOA circuit for the lower half of the display product and includes shift registers 100 from stages 1441 to 2880. The shift registers 100 employ the 10T1C architecture shown in Figure 3 .

[0111] Corresponding to the two driving partitions, two first power supply voltage signal lines and reset signal lines are also provided for controlling the denoising sub-circuit. One first power supply voltage signal line is connected to the control electrodes of the first transistors M1 of all the shift registers 100 in one driving partition, and the other first power supply voltage signal line is connected to the control electrodes of the first transistors M1 of all the shift registers 100 in the other driving partition. Similarly, the reset signal line is connected to the control electrodes of the corresponding fourth transistor M4 and fifth transistor M5.

[0112] The right part of Figure 4 provides the timing control flow of the GOA circuit, which divides a display cycle T into two half-frame sub-cycles: the upper half frame and the lower half frame. Each half-frame sub-cycle includes the input phase t1, the output phase t2, the reset phase t3, and the denoising phase t4.

[0113] For the first driving partition DA1 in the first half frame, the corresponding first power supply voltage signal line VDD1 continuously inputs a high-level first power supply voltage signal, and the reset signal line TRST1 remains in a low-level state. The timing control process includes:

[0114] In the input phase t1, a high-level input signal is input to the input signal terminal INT, turning on the eighth transistor M8 and writing the high-level input signal to the pull-up node PU. Simultaneously, the pull-up node PU in the high-level state turns on the sixth transistor M6, writing the first low-level signal of the first low-level signal terminal LVGL into the pull-down node PD, keeping the pull-down node PD in the low-level state.

[0115] In the output phase t2, the input signal terminal INT changes to a low level state, and the potential of the pull-up node PU is further pulled up by the coupling effect of the capacitor C, so that the tenth transistor M10 is turned on, and the high level clock signal of the clock signal terminal CLK is output to the output signal terminal Gout;

[0116] In the reset phase t3, the first reset signal terminal RST inputs the high-level output signal of the next-stage shift register 100 as the first reset signal, turning on the ninth transistor M9, and the potential of the pull-up node PU is pulled low by the first low-level signal terminal LVGL; and

[0117] In the t4 de-noising stage, after the potential of the pull-up node PU is pulled low, the sixth transistor M6 is turned off, and the first power supply voltage signal of the first power supply voltage signal terminal VDD is written into the pull-down node PD through the first transistor M1, so that the pull-down node PD becomes a high potential state, thereby turning on the second transistor M2 and the third transistor M3, and discharging the pull-up node PU through the first low-level signal terminal LVGL to reduce noise, and discharging the output signal terminal Gout through the second low-level signal terminal VGL to reduce noise.

[0118] Therefore, during the first half frame period, the first drive sub-area DA1 operates at the pull-down node PD, discharging and de-noising the pull-up node PU and the output signal terminal Gout. Signals from level 1 to level 1440 are transmitted via a high-level clock signal at the output signal terminal Gout, while the reset signal line TRST1 corresponding to the first drive sub-area DA1 is in a low-level output state.

[0119] For the second driving partition DA2 in the first half frame, the corresponding first power supply voltage signal line VDD2 remains in a low level state, so that the pull-down node PD remains in a low level state, and the reset signal line TRST2 continues to output a high-level second reset signal, so that the fourth transistor M4 and the fifth transistor M5 remain in the on state. All shift registers 100 in the second driving partition DA2 perform denoising on the pull-up node PU and the output signal terminal Gout through the reset denoising sub-circuit 43.

[0120] When the display cycle reaches the second half frame, the first power supply voltage signal line VDD1 corresponding to the first driving partition DA1 remains in a low level state, so that the pull-down node PD remains in a low level state, and the reset signal line TRST1 continues to output a high-level second reset signal. All shift registers 100 in the first driving partition DA1 continue to denoise the pull-up node PU and the output signal terminal Gout through the reset denoising sub-circuit 43.

[0121] For the second drive sub-area DA2 in the second half frame, the corresponding second power supply voltage signal line VDD2 continuously inputs a high-level first power supply voltage signal, while the reset signal line TRST2 remains in a low-level state. The timing control process is the same as that for the first drive sub-area DA1 in the first half frame. That is, during the second half frame period, the second drive sub-area DA2 is in a state of pulling down the node PD and discharging the pull-up node PU and the output signal terminal Gout for noise reduction. Signal transmission from level 1441 to level 2880 is achieved through the high-level clock signal at the output signal terminal Gout, while the reset signal line TRST2 corresponding to the second drive sub-area DA2 is in a low-level output state.

[0122] In general, during the first half frame, when the GOA circuit performs shift register operation in the first drive sub-area DA1 of the upper half screen, the first power supply voltage signal line VDD1 and the reset signal line TRST2 are in a high state, while the first power supply voltage signal line VDD2 and the reset signal line TRST1 are in a low state. At this time, the output signal terminal Gout of the shift register 100 of stages 1 to 1440 is normally transmitted downward, discharged and de-noised via the pull-down node PD, and the reset signal line TRST1 turns off the fourth transistor M4 and the fifth transistor M5. For the second drive sub-area DA2 of the lower half screen, i.e., stages 1441 to 2880, the shift register 100 uses the reset signal line TRST2 to control the fourth transistor M4 and the fifth transistor M5 for discharge and de-noise. During this phase, the output signal of the GOA circuit is not transmitted in stages 1441 to 2880, so the reset signal line TRST2 can be used for discharge and de-noise.

[0123] When the output signal is transmitted to the 1441th level, it enters the second half frame stage, the first power supply voltage signal line VDD1 switches to a low level state, and the reset signal line TRST1 switches to a high level second reset signal. At this time, the shift register 100 from the 1st row to the 1440th row is controlled by the pull-down node PD to switch to the discharge denoising controlled by the second reset signal terminal TRST; at the same time, the second power supply voltage signal line VDD2 switches to a high level, and the reset signal line TRST2 switches to a low level. The 1441st to 2880th levels are transformed into the discharge denoising controlled by the pull-down node PD to cope with the GOA output signal being transmitted from the 1441st level to the 2880th level, thereby completing the GOA shift register function.

[0124] Therefore, the gate drive circuit provided in this embodiment performs zoned and timed discharge noise reduction on the upper and lower half-screens, utilizing the pull-down node PD and the second reset signal terminal TRST to discharge and noise reduction the pull-up node PU and output signal terminal Gout of the shift register 100 during the display cycle or display time of a single frame. Compared to a discharge circuit with a single pull-down node PD but without the fifth transistor M5, such as a 9T1C structure, the positive bias time PB and negative bias time NB of the first transistor M1, second transistor M2, and third transistor M3 associated with the pull-down node PD, and the fourth transistor M4 and fifth transistor M5 associated with the second reset signal terminal TRST in the shift register 100 disclosed in this disclosure are both 50%. By adjusting the timing of the positive and negative bias voltages, the bias operating states of the key oxide TFTs are balanced, significantly improving the stability of the oxide TFTs and enhancing the yield and reliability of the shift register 100 and the gate drive circuit. Table 2 provides the bias time and nominal size of each oxide TFT in the 10T1C shift register 100 during operation. In Table 2, W / L represents the ratio of channel width W to channel length L, PB time represents the proportion of time with positive bias, and NB time represents the proportion of time with negative bias to minimize bezels. By optimizing the channel width W of each TFT, the minimum W required for proper operation of the gate drive circuit (GOA) is achieved.

[0125] Table 2 Bias time and nominal dimensions of oxide TFTs in 9T1C and 10T1C.

[0126] In the above embodiment, the GOA circuit based on the 10T1C shift register 100 is subjected to partitioned and timed discharge denoising. The main purpose is to divide the GOA circuit in the display product or screen into two drive partitions, and add reset signal lines TRSR1 and TRST2 to achieve discharge denoising. Among them, one drive partition discharges through the pull-down node PD, and the other drive partition can discharge through the reset signal line TRST1 or TRST2. This switching method achieves time-sharing and partitioned discharge. It should be noted that the above two drive partitions are exemplary. On this basis, in some embodiments, the GOA circuit can also be divided into multiple drive partitions for time-sharing discharge denoising, and more first power supply voltage signal lines and reset signal lines can be added to achieve this. In this design, the GOA circuit can achieve signal transmission when discharging through the pull-down node PD, but the GOA circuit cannot perform signal transmission when discharging through the reset signal line TRST. Therefore, it is necessary to allocate whether the discharge denoising is performed by the pull-down node PD or the reset signal line according to the GOA transmission.

[0127] FIG5 is a schematic diagram of a timing control simulation of a GOA circuit. In FIG5 , PU1 represents the pull-up node of the first-stage shift register 100, Gout1 represents the output signal terminal of the first-stage shift register 100, PU1441 represents the pull-up node of the 1441st-stage shift register 100, and Gout1441 represents the output signal terminal of the 1441st-stage shift register 100; PD1 represents the pull-down node in the 1st to 1440th-stage shift register 100, and PD2 represents the pull-down node in the 1441st to 2880th-stage shift register 100. The reset signal line TRST1 switches earlier than the pull-down node PD1 to ensure discharge and noise elimination of the 1st to 1440th-stage shift registers; the reset signal line TRST2 switches to a low level before the 1441st-stage shift register starts working to ensure that the GOA output signal is transmitted to the 1441st-stage shift register. The discharge of the pull-down node PD2 officially starts after the output of the 1441st-stage shift register is completed. The simulation results in FIG5 verify that the 10T1C shift register 100 can meet the normal operation of the GOA circuit.

[0128] In a third aspect, based on the same inventive concept, in another optional embodiment, an array substrate is provided, including:

[0129] The base substrate includes a display area and a peripheral area; and a plurality of cascaded shift registers 100 provided by the first embodiment and arranged in the peripheral area.

[0130] In some embodiments, by combining the cascade mode of the shift register 100 provided by the first embodiment and the shift register 100 provided by the second embodiment, the width of the peripheral area can be effectively reduced, thereby broadening the application of Oxide technology in display products, especially VR display products.

[0131] Some high-PPI display products suffer from insufficient GOA pitch. For example, the aforementioned 2117PPI display product has a GOA pitch of only 16μm, making it impossible to accommodate a single GOA unit. To address this issue, in some embodiments, no more than two columns of shift registers 100 are arranged in the peripheral area on the same side of the display area. For high-PPI display products, arranging the shift registers 100 in two columns effectively resolves the GOA pitch issue.

[0132] Figure 6 provides a schematic layout diagram of a shift register 100. From left to right, the peripheral area includes: a cutting area (Cut), which is the trimming area of ​​the display panel; a signal wiring area (Sig), which is used to arrange various signal traces; a first shift register column LG1 and a second shift register column LG2, which are arranged adjacent to each other. In Figure 6, the first shift register column LG1 is provided with the second and fourth stages of the shift register 100, while the second shift register column LG2 is provided with the first and third stages of the shift register 100; a common voltage area; and a redundant area Com. The display area is located on the side of the Com area away from the second sub-area ZA2.

[0133] In some embodiments, referring to the modular layout diagram of the circuit of the first column of shift registers LG1 provided in FIG7 , the area where each column of shift registers 100 is located includes a first sub-area ZA1 and a second sub-area ZA2. The input sub-circuit 10, the reset sub-circuit 30, and the denoising sub-circuit 40 are located in the first sub-area ZA1, and the output sub-circuit 20 is located in the second sub-area ZA2. The second sub-area ZA2 is closer to the display area than the first sub-area ZA1.

[0134] Taking the 10T1C shift register 100 provided in the embodiment of the first aspect as an example, in some embodiments, the denoising sub-circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, the input sub-circuit 10 includes an eighth transistor M8, and the reset sub-circuit 30 includes a ninth transistor M9; the array substrate further includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line, and a reset signal line, the second power supply voltage signal line includes a first low-level signal line and a second low-level signal line; in the direction from the first sub-region ZA1 to the second sub-region ZA2, the first power supply voltage signal line The signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence; the first transistor M1 is arranged on the side of the first power supply voltage signal line away from the second sub-region ZA2, the fourth transistor M4 and the second transistor M2 are arranged on the side of the reset signal line close to the second sub-region ZA2, the seventh transistor M7 and the sixth transistor M6 are arranged on the side of the first low-level signal line away from the second sub-region ZA2, the eighth transistor M8 and the ninth transistor M9 are arranged on the side of the first low-level signal line close to the second sub-region ZA2, and the fifth transistor M5 and the third transistor M3 are arranged on the side of the second low-level signal line close to the second sub-region ZA2.

[0135] Referring to FIG8 , which shows a schematic circuit layout diagram of the input subcircuit 10, reset subcircuit 30, and denoising subcircuit 40 in the first drive subarea DA1 located in the upper half of the screen, the following components are arranged in order from left to right, i.e., in the direction from the edge of the peripheral area to the edge of the display area (horizontally): first transistor M1, first power supply voltage signal line VDD1, reset signal line TRST1, fourth transistor M4, second transistor M2, seventh transistor M7, sixth transistor M6, first low-level signal line LVGL, eighth transistor M8, ninth transistor M9, two clock signal lines CLK, reset signal line TRST, second low-level signal line VGL, fifth transistor M5, and third transistor M3. This arrangement of the transistors and signal lines represents a currently preferred layout design, which can further reduce the bezel of the display product.

[0136] In some embodiments, the output sub-circuit 20 includes a tenth transistor M10 and a capacitor C. In a column direction of a column of the shift register 100 , the tenth transistor M10 and the capacitor C are alternately arranged in sequence.

[0137] Figure 9 provides a layout design for the output sub-circuit 20. In the column direction, that is, the vertical direction of the peripheral area or the column direction of the pixel array, the tenth transistor M10 is arranged in a sequence with the capacitor C at the top and the capacitor C at the bottom. It should be noted that the "top" and "bottom" here do not refer to the up-down position relationship in the thickness direction of the array substrate, but rather the up-down relationship in the plane direction of the array substrate. By placing the capacitor C below the tenth transistor M10, the capacitor C can be prevented from increasing the border width.

[0138] After the shift register 100 adopts the 10T1C architecture provided by the embodiment of the first aspect, combined with the above-mentioned peripheral area layout design, the border can be compressed to 1.74mm. Specifically, the width L1 of the cutting area Cut is approximately 0.2mm, the width L2 of the signal wiring area Sig is approximately 0.1mm, the width L3 of the first shift register column LG1 is approximately 0.67mm, the width L4 of the second shift register column LG2 is approximately 0.67mm, and the width L5 of the common voltage area and redundant area Com is approximately 0.1mm. The total width L1+L2+L3+L4+L5=1.74mm. Currently, the minimum border width required for the GOA circuit of the 18T1C shift register 100 based on oxide TFT technology is 2.2mm. The 10T1C shift register 100 and the corresponding GOA circuit provided by the embodiment of the present disclosure can narrow the border to 1.74mm, thereby achieving the effect of reducing the border width by 0.46mm, which well meets the requirements of VR display products.

[0139] In some embodiments, the channel width-to-length ratio W:L of the tenth transistor M10 is 120-300:5, where W is the channel width and L is the channel length. The channel width of the tenth transistor M10 affects the frame width, so the channel parameters of the tenth transistor M10 can be determined based on actual needs and PPI design.

[0140] 7 to 9 , it can be seen that approximately 40% of the frame is occupied by the tenth transistor M10 . Currently, the channel width W of the tenth transistor M10 is approximately 300 μm, so further narrowing the frame can be achieved by reducing the channel width W of the tenth transistor M10 .

[0141] In some embodiments, the control electrode of the tenth transistor M10 includes a first gate and a second gate, and the first gate and the second gate are connected to the pull-up node PU. That is, as shown in Figure 10, the tenth transistor M10 can adopt a dual-gate design, including a top gate TG and a bottom gate BG, and the channel CL is flanked by source and drain metal layers SD, one side is the source (Source), and the other side is the drain (Drain). By adding a bottom gate BG and applying a pull-up signal to the top gate TG and the bottom gate BG at the same time, that is, connecting to the pull-up node PU, the on-state current (I on ), thereby supporting the reduction of the channel width W of the tenth transistor M10, and achieving the purpose of reducing the border.

[0142] In some embodiments, referring to FIG9 , the channel of the tenth transistor M10 includes a plurality of sub-channels connected in series, and the channel width-to-length ratio W:L of each sub-channel is 20:5. That is, the channel structure adopts a unit cell segmentation design, and the channel width corresponding to a unit cell, that is, a sub-channel, is 20μm. The plurality of sub-channels are connected in series to form a complete channel structure of the tenth transistor M10. The unit segmentation design in the channel width direction can better cope with the on-state current I on The increase will cause heat dissipation problems for Oxide TFT.

[0143] Table 3 provides the different on-state currents I on The corresponding channel width-to-length ratio W / L and the frame width of the tenth transistor M10. on It reaches 5.5mA (milliampere), an increase of 60%, thereby narrowing the border to 1.38mm.

[0144] Table 3 Different on-state currents I on The channel size and frame width of the tenth transistor M10 are

[0145] In summary, the shift register 100 (GOA unit) provided in the embodiment of the present disclosure has a denoising sub-circuit including a pull-down control sub-circuit 41, a pull-down denoising sub-circuit 42 and a reset denoising sub-circuit 43, which can selectively discharge and denoise the pull-up node PU and the output signal terminal Gout using the second power supply voltage signal terminal VG under the control of the first power supply voltage signal of the pull-down node PD, or discharge and denoise the pull-up node PU and the output signal terminal Gout using the second power supply voltage signal terminal VG under the control of the second reset signal terminal TRST. Therefore, the shift register 100 provided by the present disclosure only needs to use a set of pull-down nodes PD and corresponding denoising sub-circuits to achieve discharge denoising of the pull-up node PU and the output signal terminal Gout. Compared with the solution of using two sets of pull-down nodes PD and corresponding denoising circuits to alternately perform discharge denoising, it can not only reduce the number of components of the denoising sub-circuit, thereby reducing the border size of display products with high PPI requirements, but also avoid the performance drift of the circuit elements in the denoising sub-circuit due to being in a bias state for a long time, thereby improving the reliability performance of the shift register 100.

[0146] On this basis, the gate drive circuit (GOA circuit) and array substrate obtained by using the above-mentioned shift register 100 have the following characteristics:

[0147] 1) Aiming at high PPI applications such as VR display, the oxide process route of LCD is adopted, with a PPI of more than 2000 as the basis. In order to cope with the problem of increased border caused by the significant reduction of GOAPitch brought about by ultra-high PPI, the noise reduction circuit and corresponding timing control of the shift register 100 using oxide TFT are adjusted to reduce the number of oxide TFTs in the shift register 100, thereby reducing the border width, solving the problem of increased border width of ultra-high PPI display products, and providing core technical support for high-end VR display products.

[0148] 2) In order to reduce the left and right borders of the display product, the results of the denoising sub-circuit of the shift register 100, as well as the cascade and timing control of the GOA circuit are improved. Specifically, within a frame display time or display cycle, the pull-down node PD and the second reset signal terminal TRST are used to partition and time-share the discharge denoising of the shift register 100, thereby reducing the bias time of the transistor associated with the pull-down node PD or the second reset signal terminal TRST; reducing the threshold voltage (Vth) drift of the oxide TFT, improving the reliability performance of the GOA circuit while simplifying the GOA circuit and reducing the border width, thereby increasing the service life of the display product.

[0149] 3) Based on the 10T1C circuit architecture, a dual-gate device design is added to the output transistor, i.e., the tenth transistor M10, to increase the on-state current Ion , reducing the size of the transistor to further reduce the border; at the same time, the layout of the shift register 100 in the peripheral area is designed and optimized, and the layout of the oxide TFT and signal wiring is optimized as much as possible to achieve the purpose of minimizing the border.

[0150] In a fourth aspect, based on the same inventive concept, in another optional embodiment, a display device is provided, comprising the array substrate provided in the embodiment of the third aspect. The display device may be a display panel, a display module, or a display device. The display panel may be a liquid crystal display panel. The display module is a module in which various chips and circuit boards are bonded or mounted on the display panel. The display device may be a VR display product, or may be an electronic device with a display screen, such as a monitor, a flat-screen TV, a tablet computer, a mobile phone, or an in-vehicle display.

[0151] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0152] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A shift register, comprising an input sub - circuit, an output sub - circuit, a reset sub - circuit, and a noise - removing sub - circuit; The input sub - circuit is respectively connected to an input signal terminal and a pull - up node, and is configured to write an input signal to the pull - up node under the control of an input signal at the input signal terminal; The output sub - circuit is respectively connected to a clock signal terminal, the pull - up node, and an output signal terminal, and is configured to output a clock signal at the clock signal terminal to the output signal terminal under the control of an input signal at the pull - up node; The reset sub - circuit is respectively connected to a first reset signal terminal, the pull - up node, and a second power - supply voltage signal terminal, and is configured to reset the pull - up node through a second power - supply voltage signal at the second power - supply voltage signal terminal under the control of a first reset signal at the first reset signal terminal; The noise - removing sub - circuit includes a pull - down control sub - circuit, a pull - down noise - removing sub - circuit, and a reset noise - removing sub - circuit; the pull - down control sub - circuit is respectively connected to a first power - supply voltage signal terminal and a pull - down node, and is configured to write a first power - supply voltage signal at the first power - supply voltage signal terminal to the pull - down node; the pull - down noise - removing sub - circuit is respectively connected to the pull - down node, the pull - up node, the second power - supply voltage signal terminal, and the output signal terminal, and is configured to discharge the pull - up node and the output signal terminal through the second power - supply voltage signal terminal under the control of a first power - supply voltage signal at the pull - down node; the reset noise - removing sub - circuit is respectively connected to a second reset signal terminal, the pull - up node, the second power - supply voltage signal terminal, and the output signal terminal, and is configured to discharge the pull - up node and the output signal terminal through the second power - supply voltage signal terminal under the control of a second reset signal at the second reset signal terminal.

2. The shift register according to claim 1, wherein, The second power - supply voltage signal terminal includes a first low - level signal terminal and a second low - level signal terminal; the second power - supply voltage signal includes a first low - level signal at the first low - level signal terminal and a second low - level signal at the second low - level signal terminal, and the voltage of the first low - level signal is lower than the voltage of the second low - level signal; The reset sub - circuit is connected to the first low - level signal terminal, and is configured to reset the pull - up node through the first low - level signal terminal under the control of a first reset signal at the first reset signal terminal; The pull - down noise - removing sub - circuit is connected to the first low - level signal terminal and the second low - level signal terminal, and is configured to discharge the pull - up node through the first low - level signal terminal and discharge the output signal terminal through the second low - level signal terminal under the control of a first power - supply voltage signal at the pull - down node; The reset noise - removing sub - circuit is connected to the first low - level signal terminal and the second low - level signal terminal, and is configured to discharge the pull - up node through the first low - level signal terminal and discharge the output signal terminal through the second low - level signal terminal under the control of a second reset signal at the second reset signal terminal.

3. The shift register according to claim 2, wherein, The pull - down control sub - circuit includes a first transistor, and the pull - down noise - removing sub - circuit includes a second transistor and a third transistor; The first pole of the first transistor is connected to the first power supply voltage signal terminal, the control pole is connected to the first pole, and the second pole is connected to the pull-down node, and is used to conduct under the control of the first power supply voltage signal terminal of the first power supply voltage signal terminal, and write the first power supply voltage signal of the first power supply voltage signal terminal into the pull-down node; The first pole of the second transistor is connected to the pull-up node, the second pole is connected to the first low-level signal terminal, and the control pole is connected to the pull-down node, and is used to conduct under the control of the first power supply voltage signal of the pull-down node, and discharge the pull-up node; The first pole of the third transistor is connected to the output signal terminal, the second pole is connected to the second low-level signal terminal, and the control pole is connected to the pull-down node, and is used to conduct under the control of the first power supply voltage signal of the pull-down node, and discharge the output signal terminal.

4. The shift register according to claim 2, wherein, The reset denoising sub-circuit includes a fourth transistor and a fifth transistor; The first pole of the fourth transistor is connected to the pull-up node, the control pole is connected to the second reset signal terminal, and the second pole is connected to the first low-level signal terminal, and is used to conduct under the control of the second reset signal of the second reset signal terminal, and discharge the pull-up node; The first pole of the fifth transistor is connected to the output signal terminal, the control pole is connected to the second reset signal terminal, and the second pole is connected to the second low-level signal terminal, and is used to conduct under the control of the second reset signal of the second reset signal terminal, and discharge the output signal terminal.

5. The shift register according to claim 2, wherein, The denoising sub-circuit further includes a sixth transistor and a seventh transistor; The first pole of the sixth transistor is connected to the pull-down node, the second pole is connected to the first low-level signal terminal, and the control pole is connected to the pull-up node, and is used to conduct under the control of the input signal of the pull-up node, and discharge the pull-down node through the first low-level signal terminal; The first pole of the seventh transistor is connected to the pull-down node, the control pole is connected to the input signal terminal, and the second pole is connected to the first low-level signal terminal, and is used to conduct under the control of the input signal terminal, and discharge the pull-down node through the first low-level signal terminal.

6. The shift register according to claim 2, wherein, The input sub-circuit includes an eighth transistor, the first pole of the eighth transistor is connected to the input signal terminal, the second pole is connected to the pull-up node, and the control pole is connected to the first pole; The reset sub-circuit includes a ninth transistor, the first pole of the ninth transistor is connected to the pull-up node, the second pole is connected to the first low-level signal terminal, and the control pole is connected to the first reset signal terminal; The output sub-circuit includes a tenth transistor and a capacitor, the first pole of the tenth transistor is connected to the clock signal terminal, the second pole is connected to the output signal terminal, and the control pole is connected to the pull-up node; one end of the capacitor is connected to the pull-up node, and the other end is connected to the output signal terminal.

7. The shift register according to claim 6, wherein, The control pole of the tenth transistor includes a first gate and a second gate, and the first gate and the second gate are connected to the pull-up node.

8. A gate driving circuit includes a plurality of cascaded shift registers as described in any one of claims 1 to 7.

9. The gate driving circuit according to claim 8, wherein, The multiple cascaded shift registers are divided into M driving partitions, where M>1 and M is an integer; in the same driving partition, the output signal terminal of the i-th stage shift register is respectively connected to the input signal terminal of the (i + 1)-th stage shift register and the first reset signal terminal of the (i - 1)-th stage shift register, and i takes an integer value between 2 and N - 1, where N≥3 and N is an integer; The gate driving circuit further includes M first power voltage signal lines and M reset signal lines, and one driving partition corresponds to one first power voltage signal line and one reset signal line; the second reset signal terminals of the shift registers in the same driving partition are connected to the reset signal line corresponding to the driving partition, and the first power voltage signal terminals of the shift registers in the same driving partition are connected to the first power voltage signal line corresponding to the driving partition.

10. A driving method for a gate driving circuit, applied to the gate driving circuit as claimed in claim 8, the driving method comprising: Controlling an input signal terminal to input an input signal, so that the input sub-circuit writes the input signal at the pull-up node; Controlling a clock signal terminal to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the input signal at the pull-up node; Controlling a first reset signal terminal to input a first reset signal, so that the reset sub-circuit resets the pull-up node through the second power voltage signal at the second power voltage signal terminal; And, Controlling the first power voltage signal terminal to input a first power voltage signal, so that the pull-down control sub-circuit writes the first power voltage signal at the pull-down node, and the pull-down noise reduction sub-circuit discharges the pull-up node and the output signal terminal through the second power voltage signal terminal; or, controlling the second reset signal terminal to input a second reset signal, so that the reset noise reduction sub-circuit discharges the pull-up node and the output signal terminal through the second power voltage signal terminal under the control of the second reset signal.

11. The driving method according to claim 10, wherein, The multiple cascaded shift registers are divided into M driving partitions, and the gate driving circuit further includes M first power voltage signal lines and M reset signal lines, and one driving partition corresponds to one first power voltage signal line and one reset signal line; the second reset signal terminals of the shift registers in the same driving partition are connected to the reset signal line corresponding to the driving partition, and the first power voltage signal terminals of the shift registers in the same driving partition are connected to the first power voltage signal line corresponding to the driving partition; The driving method includes: in the time period of [(j - 1)T / M, jT / M], controlling the first power voltage signal line corresponding to the j-th driving partition to input a first power voltage signal, and the reset signal lines corresponding to the remaining driving partitions to input the second reset signal; T is the display period of one frame of picture, and j takes an integer value from 1 to M in sequence.

12. An array substrate, comprising: A substrate, the substrate including a display area and a peripheral area; A plurality of cascaded shift registers as described in any one of claims 1 to 7 are provided in the peripheral region.

13. The array substrate according to claim 12, wherein, In the peripheral region on the same side of the display region, no more than two columns of the shift registers are arranged. The region where each column of shift registers is located includes a first sub-region and a second sub-region. The input sub-circuit, the reset sub-circuit, and the noise reduction sub-circuit are located in the first sub-region, and the output sub-circuit is located in the second sub-region. The second sub-region is closer to the display region than the first sub-region. The noise reduction sub-circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The input sub-circuit includes an eighth transistor, and the reset sub-circuit includes a ninth transistor. The array substrate further includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line, and a reset signal line. The second power supply voltage signal line includes a first low-level signal line and a second low-level signal line. In the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line, and the second low-level signal line are arranged in sequence. The first transistor is provided on the side of the first power supply voltage signal line away from the second sub-region. The fourth transistor and the second transistor are provided on the side of the reset signal line close to the second sub-region. The seventh transistor and the sixth transistor are provided on the side of the first low-level signal line away from the second sub-region. The eighth transistor and the ninth transistor are provided on the side of the first low-level signal line close to the second sub-region. The fifth transistor and the third transistor are provided on the side of the second low-level signal line close to the second sub-region.

14. The array substrate according to claim 13, wherein, The output sub-circuit includes a tenth transistor and a capacitor. In the column direction of one column of the shift registers, the tenth transistor and the capacitor are alternately arranged in sequence.

15. The array substrate according to claim 14, wherein, The channel width-to-length ratio W:L of the tenth transistor is 120 to 300:5, where W is the channel width and L is the channel length.

16. The array substrate according to claim 15, wherein, The channel of the tenth transistor includes a plurality of serially connected sub-channels, and the channel width-to-length ratio W:L of each sub-channel is 20:

5.

17. A display device, including the array substrate as described in any one of claims 12 to 16.

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