Shift register, gate driving circuit, driving method and display device

Abstract

Provided in the present disclosure are a shift register, a gate driving circuit, a driving method and a display device. The shift register comprises a denoising sub-circuit, the denoising sub-circuit comprising a pull-down control sub-circuit, a pull-down denoising sub-circuit and a reset denoising sub-circuit, wherein the pull-down control sub-circuit writes a first power supply voltage signal into a second node; the pull-down denoising sub-circuit is controlled by the electric potential of the second node to perform discharging on a first node and an output signal end by means of a second power supply voltage signal end; and the reset denoising sub-circuit is controlled by a second reset signal to perform discharging on a pull-up node and the output signal end by means of the second power supply voltage signal end. By means of the present disclosure, the number of elements in the denoising sub-circuit can be reduced, and a performance drift caused by circuit elements in the denoising sub-circuit being in a bias state for a long time can also be avoided, thereby improving the reliability performance of the shift register.

Description

Shift register, gate drive circuit, drive method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to PCT application No. PCT / CN2024 / 070169 filed on January 2, 2024, and claims priority to Chinese patent application No. 202411388769.5 filed on September 30, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, a driving method, and a display device. Background Art

[0004] As a prime example of next-generation information technology convergence and innovation, virtual reality (VR) is experiencing increasing maturity in key technologies, rapid market development, and a rapidly growing market. In recent years, global VR commercialization has diversified. Beyond familiar applications like gaming and entertainment, VR is increasingly finding its way into new sectors such as healthcare, education, and manufacturing, with increasing industry penetration. Display technology is rapidly evolving, and traditional LCD (Liquid Crystal Display) technology has matured. With the rise of VR products, the application of LCD products in VR has brought new technological developments and vitality to the LCD field. LCDs currently utilize a 1T or 2T pixel circuit design, where the T stands for thin-film transistor (TFT). These designs are relatively simple and can achieve ultra-high pixel density (pixels per inch, PPI). This offers advantages over organic light-emitting diode (OLED) display technology, and LCD's mature process technology also offers cost advantages. Today, VR display technology in the LCD field has completed mass production of 1200PPI-level products and has reserved 1500PPI technology; with the increase in VR market demand, the speed of technology iteration has accelerated, and there is an urgent need for the implementation of PPI technology above 2000, including corresponding Real RGB pixel design, optical innovation and more sophisticated process technology. Summary of the Invention

[0005] In one aspect, an embodiment of the present disclosure provides a shift register including a denoising subcircuit;

[0006] The denoising subcircuit includes a pull-down control subcircuit, a pull-down denoising subcircuit and a reset denoising subcircuit;

[0007] The pull-down control subcircuit is electrically connected to the first power supply voltage signal terminal and the second node respectively, and is used to write the first power supply voltage signal provided by the first power supply voltage signal terminal into the second node;

[0008] The pull-down denoising sub-circuit is electrically connected to the second node, the first node, the second power supply voltage signal terminal and the output signal terminal respectively, and is configured to discharge the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the potential of the second node;

[0009] The reset denoising sub-circuit is electrically connected to the second reset signal terminal, the first node, the second power supply voltage signal terminal and the output signal terminal, respectively, and is used to discharge the pull-up node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal provided by the second reset signal terminal.

[0010] Optionally, the pull-down control subcircuit is further electrically connected to a third power supply voltage signal terminal, and is configured to write the first power supply voltage signal into the second node under the control of a third power supply voltage signal provided by the third power supply voltage signal terminal.

[0011] Optionally, the denoising subcircuit further includes a second node denoising subcircuit;

[0012] The second node denoising sub-circuit is electrically connected to the denoising control terminal, the second node, and the second power supply voltage signal terminal, respectively, and is configured to control the communication between the second node and the second power supply voltage signal terminal under the control of a denoising control signal provided by the denoising control terminal;

[0013] The denoising control terminal is the second reset signal terminal or the fourth power supply voltage signal terminal.

[0014] Optionally, the reset denoising sub-circuit includes a first transistor and a second transistor;

[0015] The control electrode of the first transistor is electrically connected to the second reset signal terminal, the first electrode of the first transistor is electrically connected to the output signal terminal, and the second electrode of the first transistor is electrically connected to the second power supply voltage signal terminal;

[0016] The control electrode of the second transistor is electrically connected to the second reset signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second power supply voltage signal terminal.

[0017] Optionally, the pull-down control subcircuit includes a third transistor;

[0018] The control electrode of the third transistor is electrically connected to the third power supply voltage signal terminal, the first electrode of the third transistor is electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0019] Optionally, the pull-down control subcircuit includes a third transistor;

[0020] The control electrode of the third transistor and the first electrode of the third transistor are both electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0021] Optionally, the second node denoising sub-circuit includes a fourth transistor;

[0022] The control electrode of the fourth transistor is electrically connected to the noise reduction control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the second power supply voltage signal terminal.

[0023] Optionally, the pull-down denoising sub-circuit includes a fifth transistor and a sixth transistor;

[0024] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second power supply voltage signal terminal;

[0025] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the output signal terminal, and the second electrode of the sixth transistor is electrically connected to the second power supply voltage signal terminal;

[0026] The denoising sub-circuit further includes a seventh transistor and an eighth transistor;

[0027] The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second power supply voltage signal terminal;

[0028] The control electrode of the eighth transistor is electrically connected to the input signal terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the second power supply voltage signal terminal.

[0029] The shift register described in at least one embodiment of the present disclosure further includes an input subcircuit, an output subcircuit, and a reset subcircuit;

[0030] The input subcircuit is electrically connected to the input signal terminal and the first node respectively, and is used to write an input signal to the first node under the control of the input signal provided by the input signal terminal;

[0031] The output sub-circuit is electrically connected to the clock signal terminal, the first node and the output signal terminal respectively, and is used to output the clock signal provided by the clock signal terminal to the output signal terminal under the control of the potential of the first node;

[0032] The reset sub-circuit is electrically connected to the first reset signal terminal, the first node and the second power supply voltage signal terminal respectively, and is used to reset the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal under the control of the first reset signal provided by the first reset signal terminal.

[0033] Optionally, the input sub-circuit includes a ninth transistor; the reset sub-circuit includes a tenth transistor; and the output sub-circuit includes an eleventh transistor and a capacitor;

[0034] The control electrode of the ninth transistor and the first electrode of the ninth transistor are both electrically connected to the input signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0035] The gate of the tenth transistor is electrically connected to the first reset signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second power supply voltage signal terminal;

[0036] The gate of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the output signal terminal;

[0037] The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output signal end.

[0038] Optionally, the control electrode of the eleventh transistor includes a first control electrode and a second control electrode, and the first control electrode and the second control electrode are both electrically connected to the first node.

[0039] In a second aspect, an embodiment of the present disclosure provides a gate driving circuit comprising a plurality of cascaded shift registers as described above.

[0040] Optionally, the shift register includes a first reset signal terminal; the multiple cascaded shift registers are divided into M driving partitions, where M>1 and is an integer; in the same driving partition, the output signal terminal of the i-th stage shift register is electrically connected to the input signal terminal of the i+1-th stage shift register and the first reset signal terminal of the i-1-th stage shift register, respectively, where i is an integer, i is greater than or equal to 2 and less than or equal to N-1, and N is greater than or equal to 3 and is an integer;

[0041] The gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, and each drive partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register in the same drive partition is electrically connected to the reset signal line corresponding to the drive partition, and the first power supply voltage signal end of each shift register in the same drive partition is electrically connected to the first power supply voltage signal line corresponding to the drive partition.

[0042] Optionally, the denoising sub-circuit further includes a second node denoising sub-circuit; the denoising control terminal is a fourth power supply voltage signal terminal;

[0043] The gate driving circuit further includes M fourth power supply voltage signal lines; one driving partition corresponds to one fourth power supply voltage signal line;

[0044] The fourth power supply voltage signal terminal of each shift register in the same driving subarea is electrically connected to the fourth power supply voltage signal line corresponding to the driving subarea.

[0045] Optionally, M is equal to 2; the first fourth power supply voltage signal line and the second first power supply voltage signal line are the same signal line, and the second fourth power supply voltage signal line and the first first power supply voltage signal line are the same signal line;

[0046] The first power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the first first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the second first power supply voltage signal line;

[0047] The first power supply voltage signal terminal of each shift register in the second driving subarea is electrically connected to the second first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the second driving subarea is electrically connected to the first first power supply voltage signal line.

[0048] In a third aspect, an embodiment of the present disclosure provides a driving method of a gate driving circuit, which is applied to the above-mentioned gate driving circuit, and the driving method includes:

[0049] The first power supply voltage signal terminal is controlled to input the first power supply voltage signal, so that the pull-down control sub-circuit writes the first power supply voltage signal to the second node, and the pull-down denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal; or the second reset signal terminal is controlled to input the second reset signal, so that the reset denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

[0050] Optionally, the shift register further includes an input subcircuit, an output subcircuit, and a reset subcircuit; and the driving method further includes:

[0051] Controlling the input signal terminal to input an input signal so that the input sub-circuit writes the input signal at the first node;

[0052] controlling the clock signal terminal to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node;

[0053] The first reset signal terminal is controlled to input the first reset signal, so that the reset sub-circuit resets the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal.

[0054] Optionally, the multiple cascaded shift registers are divided into M driving partitions, and the gate drive circuit further includes M first power supply voltage signal lines and M reset signal lines, with each driving partition corresponding to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register in the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register in the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition;

[0055] The driving method includes: when scanning the shift register in the j-th driving partition,

[0056] The first power supply voltage signal line corresponding to the j-th driving partition is controlled to input a valid first power supply voltage signal; and the reset signal lines corresponding to the remaining driving partitions except the j-th driving partition are controlled to input a valid second reset signal.

[0057] The driving method according to at least one embodiment of the present disclosure further includes: when scanning the shift register in the j-th driving partition,

[0058] The reset signal line corresponding to the jth driving subarea is controlled to input an invalid second reset signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the jth driving subarea are controlled to input an invalid first power supply voltage signal.

[0059] Optionally, the denoising sub-circuit further includes a second node denoising sub-circuit; the denoising control terminal is a fourth power supply voltage signal terminal; the gate drive circuit further includes M fourth power supply voltage signal lines; one of the drive partitions corresponds to one of the fourth power supply voltage signal lines; the fourth power supply voltage signal terminals of each shift register within the same drive partition are electrically connected to the fourth power supply voltage signal line corresponding to the drive partition; and the driving method further includes:

[0060] When scanning the shift register in the j-th driving partition,

[0061] The fourth power supply voltage signal line corresponding to the jth driving subarea is controlled to input an invalid first power supply voltage signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the jth driving subarea are controlled to input a valid fourth power supply voltage signal.

[0062] In a fourth aspect, an embodiment of the present disclosure provides an array substrate, including:

[0063] A base substrate, the base substrate comprising a display area and a peripheral area;

[0064] A plurality of cascaded shift registers according to any one of claims 1 to 11 are provided in the peripheral region.

[0065] Optionally, no more than two columns of the shift registers are arranged in a peripheral area on the same side of the display area, and the area where each column of shift registers is located includes a first sub-area and a second sub-area, the input sub-circuit, the reset sub-circuit, and the denoising sub-circuit are located in the first sub-area, and the output sub-circuit is located in the second sub-area, and the second sub-area is closer to the display area than the first sub-area;

[0066] The denoising subcircuit includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the input subcircuit includes a ninth transistor, and the reset subcircuit includes a tenth transistor;

[0067] The array substrate further includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line and a reset signal line, wherein the second power supply voltage signal line includes a first low-level signal line and a second low-level signal line;

[0068] In the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence; the third transistor is arranged on a side of the first power supply voltage signal line away from the second sub-region, the second transistor and the fifth transistor are arranged on a side of the reset signal line close to the second sub-region, the eighth transistor and the seventh transistor are arranged on a side of the first low-level signal line away from the second sub-region, the ninth transistor and the tenth transistor are arranged on a side of the first low-level signal line close to the second sub-region, and the first transistor and the sixth transistor are arranged on a side of the second low-level signal line close to the second sub-region.

[0069] Optionally, the output sub-circuit includes an eleventh transistor and a capacitor, and in a column direction of a column of the shift registers, the eleventh transistor and the capacitor are alternately arranged in sequence.

[0070] Optionally, a channel width-to-length ratio of the eleventh transistor is greater than or equal to 120:5 and less than or equal to 300:5.

[0071] Optionally, the channel of the eleventh transistor includes a plurality of sub-channels connected in series, and a channel width-to-length ratio of each sub-channel is 20:5.

[0072] In a fifth aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] FIG1A is a schematic diagram of a vertical layout of a shift register;

[0074] FIG1B is a schematic diagram of an 18T1C shift register;

[0075] FIG1C is a schematic diagram of the timing control corresponding to the shift register of FIG1B ;

[0076] FIG2 is a structural diagram of a shift register according to at least one embodiment of the present disclosure;

[0077] FIG3 is a structural diagram of a shift register according to at least one embodiment of the present disclosure;

[0078] FIG4 is a structural diagram of a shift register according to at least one embodiment of the present disclosure;

[0079] FIG5 is a structural diagram of a shift register according to at least one embodiment of the present disclosure;

[0080] FIG6 is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0081] FIG7 is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0082] FIG8 is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0083] FIG9A is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0084] 9B is a simulation timing diagram of the final-stage driving signal provided by the first node PU1 of the first stage, the second node PD1 of the first stage, the first node PUL of the final stage, the second node PDL of the final stage, and the final-stage output signal terminal GTL when the gate driving circuit includes at least one embodiment of the shift register shown in FIG. 9A of the present disclosure at multiple stages;

[0085] FIG10A is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0086] FIG10B is a simulation timing diagram of the final-stage driving signal provided by the first-stage first node PU1, the first-stage second node PD1, the final-stage first node PUL, the final-stage second node PDL, and the final-stage output signal terminal GTL when the gate driving circuit includes multiple stages of at least one embodiment of the shift register shown in FIG10A of the present disclosure;

[0087] FIG11A is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0088] FIG11B is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0089] FIG12A is a circuit diagram of a shift register according to at least one embodiment of the present disclosure;

[0090] FIG12B is a simulation timing diagram of the final-stage driving signal provided by the first node PU1 of the first stage, the second node PD1 of the first stage, the first node PUL of the final stage, the second node PDL of the final stage, and the final-stage output signal terminal GTL when the gate driving circuit includes at least one embodiment of the shift register shown in FIG12 of the present disclosure at multiple stages;

[0091] 13 is a schematic diagram of the cascade relationship and corresponding timing control of gate driving circuits of two driving partitions provided according to at least one embodiment of the present disclosure;

[0092] FIG14A is a schematic diagram of a timing control simulation of a gate driving circuit according to at least one embodiment of the present disclosure;

[0093] FIG14B is a simulation result of the intermediate stage shift register;

[0094] FIG15 is a simulation result of the final shift register; the simulation result is the simulation result of one frame time;

[0095] FIG16 is a schematic diagram of the layout of a shift register in a peripheral area according to at least one embodiment of the present disclosure;

[0096] FIG17 is a schematic diagram of the layout of sub-circuit modules in a shift register provided according to at least one embodiment of the present disclosure;

[0097] FIG18 is a circuit diagram of an input sub-circuit, a reset sub-circuit, and a denoising sub-circuit according to at least one embodiment of the present disclosure;

[0098] FIG19 is a circuit diagram of an output sub-circuit provided according to at least one embodiment of the present disclosure;

[0099] FIG20 is a schematic structural diagram of an eleventh transistor with a dual-gate structure provided according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0100] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0101] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0102] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0103] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0104] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0105] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0106] Currently, in pixel designs with 1000PPI (Pixels Per Inch) and 1500PPI, LTPS (low-temperature polycrystalline silicon) or LTPO (low-temperature polycrystalline oxide) processes are often used. When the LTPS process is used in the driving part of the GOA (Gate On Array, a gate drive circuit provided on an array substrate), the GOA unit in the current LTPS GOA circuit, i.e., the shift register, can adopt an 8T2C (including 8 transistors and 2 capacitors) structure and adopt unilateral alternating drive to achieve a border width of ≤1.2mm. However, for the oxide process, the GOA unit often adopts an 18T1C structure, and for the oxide GOA unit with high mobility requirements, the structure has reached 23T2C. Compared with the 8T2C commonly used in LTPS GOA, the 18T1C structure currently commonly used in oxide GOA doubles the number of TFTs (thin-film transistors), and the border width naturally increases significantly.

[0107] In addition to the limitations of the GOA circuit, the GOA circuit design of ultra-high PPI VR (virtual reality) products is also affected by pitch. Table 1 lists the pixel pitch and GOA pitch of 1200PPI display products, 1500PPI display products, and 2117PPI display products. It can be seen that the higher the PPI, the smaller the pixel pitch; if the GOA circuit adopts unilateral alternating drive, the pitch of the GOA circuit is twice the pixel pitch. Therefore, the higher the PPI, the smaller the pitch of the GOA circuit, and the smaller the vertical space of the GOA layout in the border area. Layout can only be performed by stretching the horizontal space, which leads to an increase in the border of the product. Among them, the vertical direction can be the column direction of the pixel array on the display substrate or display panel, and the horizontal direction can be the row direction of the pixel array.

[0108] Table 1: Pixel pitch and GOA pitch corresponding to different PPI display products:

[0109] For example, for the 2117 PPI product in Table 1, its real RGB design pixel arrangement is 4×12; the vertical pixel pitch is 12 μm (micrometers), and the GOA pitch is 24 μm. In some embodiments, a Delta RGB arrangement with a 6×8 pixel arrangement can also be used to improve transmittance from a pixel design perspective. However, when using this design, the pixel pitch width is only 8 μm, and the corresponding GOA pitch, or vertical space, is only 16 μm, which will result in a serious shortage of vertical space.

[0110] Specifically, referring to Figure 1A, the vertical space of the GOA layout requires at least one thin-film transistor T0, a pull-up trace PUL, and a pull-down trace PDL, and it is necessary to ensure that there is no short circuit between the traces. For example, for the current design where the channel length L of the thin-film transistor T0 is 5μm to 6μm, the vertical pitch required to set up a group of GOA units is at least the total pitch d, where d is equal to 23μm, of which the first pitch d1 occupied by the thin-film transistor T0 is approximately 15.5μm, and the second pitch d2 occupied by the PUL and PDL is approximately 7.5μm; however, the GOA pitch currently used in the 2117PPIDelta RGB design is only 16μm, which is not enough to place a group of GOA units. This is a GOA layout and border problem caused by the PPI increase.

[0111] Figure 1B provides a circuit diagram of a stable and effective oxide GOA unit. The GOA unit has an 18T1C structure, which uses 18 oxide thin-film transistors and one capacitor C. Its main architecture uses a pull-up node PU to control the output, and a first pull-down node PD1 and a second pull-down node PD2 to alternately discharge. As shown in Figure 1B, at least one embodiment of the GOA unit includes:

[0112] A first first transistor M1A is connected to the first control voltage terminal VDDO and the first pull-down node PD1 respectively;

[0113] The second first transistor M1B is connected to the second control voltage terminal VDDE and the second pull-down node PD2 respectively;

[0114] The first second transistor M2A is connected to the pull-up node PU, the first pull-down node PD1 and the first low-level signal terminal LVGL respectively;

[0115] a second second transistor M2B connected to the pull-up node PU, the second pull-down node PD2 and the first low-level signal terminal LVGL respectively;

[0116] The first third transistor M3A is connected to the output signal terminal Gt(n), the first pull-down node PD1 and the second low-level signal terminal VGL respectively;

[0117] The second third transistor M3B is connected to the output signal terminal Gt(n), the second pull-down node PD2 and the second low-level signal terminal VGL respectively;

[0118] a fourth transistor M4 connected to the pull-up node PU, the second reset signal terminal TRST, and the first low-level signal terminal LVGL, respectively. The potential of the first low-level signal provided by LVGL is lower than the potential of the second low-level signal provided by VGL;

[0119] The first sixth transistor M6A is connected to the first pull-down node PD1, the pull-up node PU and the first low-level signal terminal LVGL respectively;

[0120] The second sixth transistor M6B is connected to the second pull-down node PD2, the pull-up node PU and the first low-level signal terminal LVGL respectively;

[0121] The first seventh transistor M7A is connected to the first pull-down node PD1, the input signal terminal STV and the first low-level signal terminal LVGL respectively;

[0122] The second seventh transistor M7B is connected to the second pull-down node PD2, the input signal terminal STV and the first low-level signal terminal LVGL respectively;

[0123] an eighth transistor M8 connected to the input signal terminal INT and the pull-up node PU;

[0124] a ninth transistor M9 connected to the pull-up node PU, the first reset signal terminal RST, and the first low-level signal terminal LVGL, respectively, wherein the first reset signal terminal RST may be an output signal terminal of an adjacent next-stage GOA unit;

[0125] a tenth transistor M10 connected to the clock signal terminal CLK, the pull-up node PU and the output signal terminal Gt(n);

[0126] an eleventh transistor M11 connected to the clock signal terminal CLK, the pull-up node PU and the cascade output signal terminal OC(n);

[0127] The first twelfth transistor M12A is connected to the cascade output signal terminal OC(n), the first pull-down node PD1 and the first low-level signal terminal LVGL respectively;

[0128] The second twelfth transistor M12B is respectively connected to the cascade output signal terminal OC(n), the second pull-down node PD2 and the first low-level signal terminal LVGL;

[0129] The thirteenth transistor M13 is connected to the output signal terminal Gt(n), the (n+1)th output signal terminal Gt(n+1), and the second low-level signal terminal VGL, respectively; n is a positive integer;

[0130] The capacitor C is connected to the pull-up node PU and the output signal terminal Gt(n) respectively.

[0131] The output signal terminal Gt(n) is used to output a light emitting control signal, and OC(n) is used to provide an input signal to the next-stage GOA unit and to provide a first reset signal to the previous-stage GOA unit.

[0132] FIG. 1C is a timing control diagram of at least one embodiment of the GOA unit shown in FIG. 1B .

[0133] As shown in FIG1C , the driving cycle includes an input phase t1 , an output phase t2 , a reset phase t3 , and a denoising phase t4 , which are arranged in sequence;

[0134] In the input phase t1, the input signal terminal INT provides a high voltage. Since the gate of M8 and the drain of M8 are connected to form a diode structure, M8 is turned on and the potential of the pull-up node PU is pulled high.

[0135] In the output phase t2, the potential of the pull-up node PU is bootstrapped by the capacitor C, turning on M10 and providing the high voltage signal provided by the clock signal terminal to the output signal terminal Gt(n);

[0136] In the reset phase t3, the first reset signal terminal RST provides a high voltage signal, T0 is turned on, and the pull-up node PU is reset;

[0137] In the de-noising stage t4, VDDO provides a high voltage signal, the gate of M1A and the drain of M1A are electrically connected to form a diode structure, the potential of PD1 is a high voltage, and the pull-up node PU and the output signal terminal Gt(n) are discharged through PD1 for de-noising.

[0138] Specifically, during a certain frame display time, VDDO inputs a high voltage signal, transistor M1A turns on, and VDDO directly charges the pull-down node PD1. During operation, the potential of the pull-down node PD1 is kept at a high voltage, thereby using M2A to discharge the pull-up node PU, keeping the pull-up node PU at a low potential state and reducing the noise of the GOA unit. During the next frame display time, VDDE switches to a high level state and VDDO switches to a low level state, transitioning to the second pull-down node PD2 working and the first pull-down node PD1 resting. The first pull-down node PD1 and the second pull-down node PD2 work alternately.

[0139] In related technologies, PD1 and PD2 are alternately operated to reduce the bias time of transistors related to the pull-down node, thereby solving the problem of threshold voltage offset of oxide transistors under bias. However, when this GOA unit is applied to display products with high PPI and small pitch, it will bring the problem of excessively large borders.

[0140] In order to solve the above problem, in an optional embodiment, as shown in FIG2 , the shift register according to at least one embodiment of the present disclosure may include a denoising subcircuit;

[0141] The denoising subcircuit includes a pull-down control subcircuit 41, a pull-down denoising subcircuit 42 and a reset denoising subcircuit 43;

[0142] The pull-down control sub-circuit 41 is electrically connected to the first power supply voltage signal terminal VDD and the second node PD, respectively, and is used to write the first power supply voltage signal provided by the first power supply voltage signal terminal VDD into the second node PD;

[0143] The pull-down denoising sub-circuit 42 is electrically connected to the second node PD, the first node PU, the second power supply voltage signal terminal VG, and the output signal terminal GT, respectively, and is configured to discharge the first node PU and the output signal terminal GT through the second power supply voltage signal terminal VG under the control of the potential of the second node PD;

[0144] The reset denoising sub-circuit 43 is electrically connected to the second reset signal terminal TRST, the first node PU, the second power supply voltage signal terminal VG and the output signal terminal GT, respectively, and is used to discharge the pull-up node PU and the output signal terminal GT through the second power supply voltage signal terminal VG under the control of the second reset signal provided by the second reset signal terminal TRST.

[0145] At least one embodiment of the shift register shown in Figure 2 of the present disclosure may include a denoising subcircuit, which may include a pull-down control subcircuit 41, a pull-down denoising subcircuit 42 and a reset denoising subcircuit 43; the reset denoising subcircuit 43 can discharge the pull-up node PU and the output signal terminal GT under the control of a second reset signal, thereby improving the denoising capability of the shift register for the pull-up node and the output signal terminal, so that only one set of pull-down nodes and corresponding denoising subcircuits are required to achieve alternating discharge denoising of the pull-up node PU and the output signal terminal GT. Compared with the solution of using two sets of pull-down nodes and corresponding denoising subcircuits for alternating discharge denoising, this solution can reduce the number of components in the denoising subcircuit and reduce the frame size of display products with high PPI requirements, and avoid performance drift of circuit components in the denoising subcircuit due to being in a bias state for a long time, thereby improving the reliability of the shift register.

[0146] As shown in FIG3 , based on at least one embodiment of the shift register shown in FIG2 , the shift register according to at least one embodiment of the present disclosure further includes an input subcircuit 10 , an output subcircuit 20 , and a reset subcircuit 30 ;

[0147] The input sub-circuit 10 is electrically connected to the input signal terminal INT and the first node PU respectively, and is used to write an input signal to the first node PU under the control of the input signal provided by the input signal terminal INT;

[0148] The output sub-circuit 20 is electrically connected to the clock signal terminal CLK, the first node PU and the output signal terminal GT respectively, and is used to output the clock signal provided by the clock signal terminal CLK to the output signal terminal GT under the control of the potential of the first node PU;

[0149] The reset sub-circuit 30 is electrically connected to the first reset signal terminal RST, the first node PU and the second power supply voltage signal terminal VG, respectively, and is used to reset the first node PU through the second power supply voltage signal provided by the second power supply voltage signal terminal VG under the control of the first reset signal provided by the first reset signal terminal RST.

[0150] In GOA technology, multiple shift registers are cascaded to form a GOA circuit. Therefore, the input signal terminal INT of the current-stage shift register can be connected to the output signal terminal or cascade output terminal of the previous-stage shift register. Accordingly, the input signal can be the output signal of the previous-stage shift register, or the cascade output signal of the previous-stage shift register. Therefore, in addition to being used to drive the pixels in this row, the output signal of the output signal terminal GT can also be used as the reset signal of the previous row and the input signal of the next row. In some embodiments, the first reset signal terminal RST connected to the reset subcircuit 30 can be connected to the output signal terminal of the next-stage shift register, and the second reset signal terminal TRST connected to the reset denoising subcircuit 43 can be connected to an independently set reset signal line, and the second reset signal in the reset signal line is output from the timing controller.

[0151] The first power supply voltage signal terminal VDD and the second power supply voltage signal terminal VG are operating voltage signals output by the power management integrated circuit (PMIC). For the GOA circuit, unless otherwise specified, the embodiment of the present disclosure is described as an example in which the first power supply voltage signal is a high-level operating voltage signal and the second power supply voltage signal is a low-level gate-off voltage.

[0152] The timing control flow of the shift register can be as follows:

[0153] 1) In the input phase, a valid input signal is input to the input signal terminal INT, so that the input sub-circuit 10 starts working and writes the input signal into the pull-up node PU;

[0154] 2) Output stage: under the control of the input signal of the pull-up node PU, the output sub-circuit 20 starts to work and outputs the clock signal provided by the clock signal terminal CLK as a valid output signal to the output signal terminal GT;

[0155] 3) During the reset phase, the first reset signal terminal RST inputs a valid first reset signal to enable the reset sub-circuit 30 to operate and reset the pull-up node PU through the second power supply voltage signal terminal VG; and

[0156] 4) In the denoising stage, the voltage signal of the pull-down node PD or the valid second reset signal provided by the second reset signal terminal TRST can be selectively used to activate either the pull-down denoising sub-circuit 42 or the reset denoising sub-circuit 43 to discharge and denoise the pull-up node PU and the output signal terminal GT.

[0157] The pull-down de-noising sub-circuit 42 is a circuit that performs discharge de-noising on the pull-up node PU and the output signal terminal GT under the control of the pull-down node PD. The reset de-noising sub-circuit 43 is a circuit that performs discharge de-noising on the pull-up node PU and the output signal terminal GT under the control of the second reset signal terminal TRST. Therefore, alternate discharge de-noising can be selectively achieved through the pull-down de-noising sub-circuit 42 or the reset de-noising sub-circuit 43. When a valid signal, such as a high-potential first power supply voltage signal, is written to the pull-down node PD, the pull-down de-noising sub-circuit 42 can be activated, utilizing the low-potential state of the second power supply voltage signal terminal VG to perform discharge de-noising on the pull-up node PU and the output signal terminal GT. Alternatively, when a valid signal is input to the second reset signal terminal TRST, the reset de-noising sub-circuit 43 can be activated, utilizing the second power supply voltage signal terminal VG to perform discharge de-noising on the pull-up node PU and the output signal terminal GT.

[0158] Therefore, the shift register of some embodiments of the present disclosure only needs to use a set of pull-down nodes PD and corresponding denoising sub-circuits to achieve alternating discharge denoising of the pull-up node PU and the output signal terminal GT. Compared with the solution of using two sets of pull-down nodes PD and corresponding denoising circuits for alternating discharge denoising, it can not only reduce the number of components of the denoising sub-circuit and reduce the border size of display products with high PPI requirements, but also avoid the performance drift of the circuit elements in the denoising sub-circuit due to being in a bias state for a long time, thereby improving the reliability performance of the shift register.

[0159] In some embodiments, the second power supply voltage signal terminal VG may include a first low-level signal terminal LVGL and a second low-level signal terminal VGL; the second power supply voltage signal includes a first low-level signal provided by the first low-level signal terminal LVGL and a second low-level signal provided by the second low-level signal terminal VGL, and the voltage value of the first low-level signal is lower than the voltage value of the second low-level signal; the reset sub-circuit 30 is connected to the first low-level signal terminal LVGL, and is used to reset the pull-up node PU through the first low-level signal terminal LVGL under the control of the first reset signal provided by the first reset signal terminal RST; the pull-down denoising sub-circuit 42 The first low-level signal terminal LVGL and the second low-level signal terminal VGL are connected, and are used to discharge the pull-up node PU through the first low-level signal terminal LVGL and discharge the output signal terminal GT through the second low-level signal terminal VGL under the control of the potential of the pull-down node PD; the reset denoising sub-circuit 43 is connected to the first low-level signal terminal LVGL and the second low-level signal terminal VGL, and is used to discharge the pull-up node PU through the first low-level signal terminal LVGL and discharge the output signal terminal GT through the second low-level signal terminal VGL under the control of the second reset signal provided by the second reset signal terminal TRST.

[0160] In some embodiments, the voltage value of the first low level signal may be -10 V, and the voltage value of the second low level signal may be -8 V. By using the first low level signal terminal LVGL with a lower potential to discharge the pull-up node PU, the discharge noise reduction effect can be improved.

[0161] Optionally, the second power supply voltage signal terminal VG may also only include the second low-level signal terminal VGL.

[0162] In at least one embodiment of the present disclosure, the pull-down control subcircuit is also electrically connected to a third power supply voltage signal terminal, and is configured to write the first power supply voltage signal into the second node under control of a third power supply voltage signal provided by the third power supply voltage signal terminal.

[0163] In a specific implementation, the pull-down control circuit can also be electrically connected to a third power supply voltage signal terminal. Under the control of the third power supply voltage signal, the first power supply voltage signal is written to the second node. The third power supply voltage signal can continuously output a high voltage signal, so that the transistor included in the pull-down control subcircuit is always turned on. When the first power supply voltage terminal provides a low voltage signal, the pull-down control subcircuit can directly pull down the potential of the pull-down node.

[0164] As shown in Figure 4, based on at least one embodiment of the shift register shown in Figure 3, the pull-down control sub-circuit 41 is also electrically connected to the third power supply voltage signal terminal VGH, and is used to write the first power supply voltage signal into the second node PD under the control of the third power supply voltage signal provided by the third power supply voltage signal terminal VGH.

[0165] In at least one embodiment of the present disclosure, the denoising subcircuit further includes a second node denoising subcircuit;

[0166] The second node denoising sub-circuit is electrically connected to the denoising control terminal, the second node, and the second power supply voltage signal terminal, respectively, and is configured to control the communication between the second node and the second power supply voltage signal terminal under the control of a denoising control signal provided by the denoising control terminal;

[0167] The denoising control terminal is the second reset signal terminal or the fourth power supply voltage signal terminal.

[0168] In a specific implementation, the denoising sub-circuit may further include a second node denoising sub-circuit, which, under the control of a denoising control signal provided by the denoising control terminal, controls the connection between the second node and the second power supply voltage signal terminal to reset the potential of the second node.

[0169] As shown in FIG5 , based on at least one embodiment of the shift register shown in FIG3 , the shift register according to at least one embodiment of the present disclosure includes a second node denoising subcircuit 51 ;

[0170] The second node denoising sub-circuit 51 is electrically connected to the denoising control terminal ST, the second node PD and the second power supply voltage signal terminal VG, respectively, and is used to control the connection between the second node PD and the second power supply voltage signal terminal VG under the control of the denoising control signal provided by the denoising control terminal ST.

[0171] In at least one embodiment shown in FIG5 , when the second reset signal terminal is the first frame reset terminal, the denoising control terminal may be the first frame reset terminal;

[0172] When the second reset signal terminal is a second frame reset terminal, the denoising control terminal may be a second frame reset terminal.

[0173] In at least one embodiment shown in FIG5 , when the second reset signal terminal is the first frame reset terminal and the first power supply voltage signal terminal is the first control voltage terminal, the denoising control terminal may be the second control voltage terminal;

[0174] When the second reset signal terminal is the second frame reset terminal and the first power supply voltage signal terminal is the second control voltage terminal, the denoising control terminal may be the first control voltage terminal.

[0175] Optionally, the reset denoising sub-circuit includes a first transistor and a second transistor;

[0176] The control electrode of the first transistor is electrically connected to the second reset signal terminal, the first electrode of the first transistor is electrically connected to the output signal terminal, and the second electrode of the first transistor is electrically connected to the second power supply voltage signal terminal;

[0177] The control electrode of the second transistor is electrically connected to the second reset signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second power supply voltage signal terminal.

[0178] Optionally, the pull-down control subcircuit includes a third transistor;

[0179] The control electrode of the third transistor is electrically connected to the third power supply voltage signal terminal, the first electrode of the third transistor is electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0180] Optionally, the pull-down control subcircuit includes a third transistor;

[0181] The control electrode of the third transistor and the first electrode of the third transistor are both electrically connected to the first power supply voltage signal terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0182] Optionally, the second node denoising sub-circuit includes a fourth transistor;

[0183] The control electrode of the fourth transistor is electrically connected to the noise reduction control terminal, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the second power supply voltage signal terminal.

[0184] Optionally, the pull-down denoising sub-circuit includes a fifth transistor and a sixth transistor;

[0185] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second power supply voltage signal terminal;

[0186] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the output signal terminal, and the second electrode of the sixth transistor is electrically connected to the second power supply voltage signal terminal;

[0187] The denoising sub-circuit further includes a seventh transistor and an eighth transistor;

[0188] The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second power supply voltage signal terminal;

[0189] The control electrode of the eighth transistor is electrically connected to the input signal terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the second power supply voltage signal terminal.

[0190] Optionally, the input sub-circuit includes a ninth transistor; the reset sub-circuit includes a tenth transistor; and the output sub-circuit includes an eleventh transistor and a capacitor;

[0191] The control electrode of the ninth transistor and the first electrode of the ninth transistor are both electrically connected to the input signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node;

[0192] The gate of the tenth transistor is electrically connected to the first reset signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second power supply voltage signal terminal;

[0193] The gate of the eleventh transistor is electrically connected to the first node, the first pole of the eleventh transistor is electrically connected to the clock signal terminal, and the second pole of the eleventh transistor is electrically connected to the second power supply voltage signal terminal;

[0194] The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output signal terminal.

[0195] In at least one embodiment of the present disclosure, the control pole of the eleventh transistor includes a first control pole and a second control pole, and both the first control pole and the second control pole are electrically connected to the first node.

[0196] It should be noted that each transistor used in the shift register may be a thin film transistor (TFT) with an oxide as the active layer (Active). The control pole of each transistor is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetric in structure and can be considered indistinguishable in structure, that is to say, the first pole and the second pole of the transistor in the embodiments of the present disclosure can be indistinguishable in structure.

[0197] For example, for a P-type transistor, the first pole of the transistor is the source, the second pole is the drain, and the control pole is the gate; according to the conduction condition of the P-type transistor: Vg < Vs, Vgs - Vth < 0, where Vg is the gate voltage, Vs is the source voltage, Vgs is the voltage between the gate and the source, and Vth is the threshold voltage; applying a low-level signal to the gate can make the transistor conduct. Another example is that when the transistor is an N-type transistor, the first pole of the transistor is the drain, the second pole is the source, and the control pole is the gate; according to the conduction condition of the N-type transistor: Vg > Vs, Vgs - Vth > 0, it can be seen that applying a high-level signal to the gate can make the transistor conduct. Unless otherwise specified, the embodiments of the present disclosure are described by taking N-type transistors as examples.

[0198] After connecting the control pole of the third transistor to the first pole, the third transistor can be converted into a diode connection and conduct when a high-voltage signal is input at the first power supply voltage signal terminal VDD, so that the potential of the second node PD is a high voltage. When the second node PD is in a high-level state, the fifth transistor M5 and the sixth transistor M6 whose control poles are connected to the second node PD conduct, thereby controlling the connection between the first node PU and the first low-level signal terminal LVGL, and controlling the connection between the output signal terminal GT and the second low-level signal terminal VGL, so that the first node PU and the output signal terminal GT are maintained at a low-potential state, realizing discharge and noise reduction.

[0199] The reset and noise reduction sub-circuit discharges and reduces noise for the first node PU and the output signal terminal GT under the control of the second reset signal terminal TRST.

[0200] Therefore, the shift register of some embodiments of the present disclosure can selectively perform discharge denoising on the first node PU and the output signal terminal GT through a pull-down denoising sub-circuit, or perform discharge denoising on the first node PU and the output signal terminal GT through a reset denoising sub-circuit, which can avoid some transistors in the pull-down denoising sub-circuit or the reset denoising sub-circuit working in a biased state for a long time, thereby avoiding the threshold voltage drift of the oxide transistor, which is beneficial to improving control accuracy and reducing control failures.

[0201] As shown in FIG6 , based on at least one embodiment of the shift register shown in FIG3 ,

[0202] The reset denoising sub-circuit includes a first transistor M1 and a second transistor M2;

[0203] The gate of the first transistor M1 is electrically connected to the second reset signal terminal TRST, the drain of the first transistor M1 is electrically connected to the output signal terminal GT, and the source of the first transistor M1 is electrically connected to the second low-level signal terminal VGL;

[0204] The gate of the second transistor M2 is electrically connected to the second reset signal terminal TRST, the drain of the second transistor M2 is electrically connected to the first node PU, and the source of the second transistor M2 is electrically connected to the first low-level signal terminal LVGL;

[0205] The pull-down control subcircuit includes a third transistor M3;

[0206] The gate of the third transistor M3 and the drain of the third transistor M3 are both electrically connected to the first power supply voltage signal terminal VDD, and the source of the third transistor M3 is electrically connected to the second node PD;

[0207] The pull-down denoising sub-circuit includes a fifth transistor M5 and a sixth transistor M6;

[0208] The gate of the fifth transistor M5 is electrically connected to the second node PD, the drain of the fifth transistor M5 is electrically connected to the first node PU, and the source of the fifth transistor M5 is electrically connected to the first low-level signal terminal LVGL;

[0209] The gate of the sixth transistor M6 is electrically connected to the second node PD, the drain of the sixth transistor M6 is electrically connected to the output signal terminal GT, and the source of the sixth transistor M6 is electrically connected to the second low-level signal terminal VGL;

[0210] The denoising sub-circuit further includes a seventh transistor M7 and an eighth transistor M8;

[0211] The gate of the seventh transistor M7 is electrically connected to the first node PU, the drain of the seventh transistor M7 is electrically connected to the second node PD, and the source of the seventh transistor M7 is electrically connected to the first low-level signal terminal LVGL;

[0212] The gate of the eighth transistor M8 is electrically connected to the input signal terminal INT, the drain of the eighth transistor M8 is electrically connected to the second node PD, and the source of the eighth transistor M8 is electrically connected to the first low-level signal terminal LVGL;

[0213] The input sub-circuit includes a ninth transistor M9; the reset sub-circuit includes a tenth transistor M10; and the output sub-circuit includes an eleventh transistor M11 and a capacitor C;

[0214] The gate of the ninth transistor M9 and the drain of the ninth transistor M9 are both electrically connected to the input signal terminal INT, and the source of the ninth transistor M9 is electrically connected to the first node PU;

[0215] The gate of the tenth transistor M10 is electrically connected to the first reset signal terminal RST, the drain of the tenth transistor M10 is electrically connected to the first node PU, and the source of the tenth transistor M10 is electrically connected to the first low-level signal terminal LVGL;

[0216] The gate of the eleventh transistor M11 is electrically connected to the first node PU, the drain of the eleventh transistor M11 is electrically connected to the clock signal terminal CLK, and the source of the eleventh transistor M11 is electrically connected to the second low-level signal terminal VGL;

[0217] A first end of the capacitor C is electrically connected to the first node PU, and a second end of the capacitor C is electrically connected to the output signal terminal GT.

[0218] In at least one embodiment of the shift register shown in FIG. 6 , all transistors are n-type transistors, and all transistors are oxide transistors.

[0219] In at least one embodiment of the present disclosure, the denoising sub-circuit further includes a seventh transistor M7 and an eighth transistor M8;

[0220] The seventh transistor M7 is configured to be turned on under the control of the potential of the first node PU and discharge the second node PD via LVGL. The eighth transistor M8 is configured to be turned on under the control of the input signal terminal INT and discharge the second node PD via LVGL. Therefore, the seventh transistor M7 and the eighth transistor M8 form a pull-up denoising sub-circuit that performs discharge denoising on the second node PD under the control of the first node PU.

[0221] In at least one embodiment of the present disclosure, the input sub-circuit includes a ninth transistor M9; the gate of the ninth transistor M9 and the drain of the ninth transistor M9 are electrically connected to the input signal terminal INT; the ninth transistor M9 is a diode structure, which can be turned on when INT provides a high voltage signal and turned off when INT provides a low voltage signal.

[0222] In at least one embodiment of the present disclosure, the reset sub-circuit includes a tenth transistor M10; when the first reset signal terminal RST outputs a valid first reset signal, M10 is turned on and resets the first node PU through the first low-level signal terminal LVGL.

[0223] In at least one embodiment of the present disclosure, the output subcircuit includes an eleventh transistor M11 and a capacitor C. When the first node PU is at a high level, M11 is turned on, transmitting the high-level clock signal from the clock signal terminal CLK as an output signal to the output signal terminal GT. Capacitor C, through bootstrapping or coupling, can further increase the voltage of the first node PU during the output phase, thereby improving the stability of the signal output.

[0224] At least one embodiment of the present disclosure provides a shift register with a 10T1C architecture that utilizes oxide transistors. Compared to the dual-second-node discharge denoising of the 18T1C architecture, the 10T1C shift register provided by the present disclosure utilizes a single-second-node discharge, reducing the number of thin-film transistors used by the 18T1C shift register by eight. Furthermore, the 10T1C shift register omits the cascade output terminal and adds a first transistor M1 to form a reset denoising subcircuit. The drain of the first transistor M1 is connected to the output signal terminal GT, the source of the first transistor M1 is connected to the second low-level signal terminal VGL, and the gate is connected to the second reset signal terminal TRST. Discharge denoising of the output signal terminal GT can be achieved through the second reset signal terminal TRST.

[0225] Compared with the related 18T1C shift register, the 10T1C shift register achieves a reduction in the number of transistors by reducing a set of second nodes and corresponding denoising transistors, and achieving denoising through a single second node. However, if a single second node is always used for discharge denoising, then the related third transistor M3, fifth transistor M5, and sixth transistor M6 will have the problem of threshold voltage drift under long-term bias, significantly reducing the reliability of the shift-based heater. Therefore, within the display cycle of a frame, discharge denoising can be performed through the pull-down denoising sub-circuit controlled by the second node PD for part of the time, and discharge denoising can be performed through the reset denoising sub-circuit controlled by the second reset signal terminal TRST for the remaining time, which can greatly improve this problem.

[0226] The difference between at least one embodiment of the shift register shown in FIG7 and at least one embodiment of the shift register shown in FIG6 is as follows:

[0227] The source of the second transistor M2 is electrically connected to the second low-level signal terminal VGL;

[0228] The source of the fifth transistor M5 is electrically connected to the second low-level signal terminal VGL;

[0229] The source of the seventh transistor M7 is electrically connected to the second low-level signal terminal VGL;

[0230] The source of the eighth transistor M8 is electrically connected to the second low-level signal terminal VGL;

[0231] A source of the tenth transistor M10 is electrically connected to the second low-level signal terminal VGL.

[0232] The difference between at least one embodiment of the shift register shown in FIG8 and at least one embodiment of the shift register shown in FIG7 is as follows: it further includes a second node denoising subcircuit;

[0233] The second node denoising sub-circuit includes a fourth transistor M4;

[0234] A gate of the fourth transistor M4 is electrically connected to the noise removal control terminal ST, a drain of the fourth transistor M4 is electrically connected to the second node PD, and a source of the fourth transistor M4 is electrically connected to the second low-level signal terminal VGL.

[0235] In at least one embodiment shown in FIG. 8 , M4 is an n-type transistor and M4 is an oxide transistor.

[0236] In at least one embodiment of the shift register shown in FIG8 of the present disclosure, a fourth transistor M4 is added, and the gate of M4 is electrically connected to the de-noising control terminal ST. The de-noising control signal provided by the de-noising control terminal ST can be used to de-noise the second node PD, thereby preventing the potential of the second node PD from being affected by leakage current due to the second node PD being in a floating state when the potential of the first node PU is a low voltage and VDD provides a low voltage signal.

[0237] As shown in FIG9A , based on at least one embodiment of the shift register shown in FIG8 , the denoising control terminal is a second reset signal terminal TRST.

[0238] When the display panel includes at least one embodiment of the shift register unit shown in FIG. 9A ,

[0239] In the first driving module for driving the pixel circuit of the upper half screen, the second reset signal terminal is electrically connected to the first reset signal line, and the first power supply voltage signal terminal is electrically connected to the first first power supply voltage signal line;

[0240] In the second driving module for driving the pixel circuit of the lower half screen, the second reset signal terminal is electrically connected to the second reset signal line, and the first power supply voltage signal terminal is electrically connected to the second first power supply voltage signal line;

[0241] When the first driving module scans the pixel circuits of the upper half of the screen, the first first power supply voltage signal line provides a high voltage signal, the second reset signal line provides a high voltage signal, the second first power supply voltage signal line provides a low voltage signal, and the first reset signal line provides a low voltage signal. At this time, the output signals of the shift registers at each level in the first driving module are normally transmitted downward, and discharge and noise reduction are performed at the first node PD; the first reset signal line turns off M1, M2, and M4; at this time, the second driving module for driving the pixel circuits of the lower half of the screen controls M1, M2, and M4 to discharge and noise reduction via the second reset signal line;

[0242] When the first driving module finishes scanning the pixel circuits of the upper half of the screen, the first first power supply voltage signal line switches to providing a low voltage signal, the second reset signal line switches to providing a low voltage signal, the second first power supply voltage signal line switches to providing a high voltage signal, and the first reset signal line switches to providing a high voltage signal. At this time, in the first driving module, the first reset signal line is switched to discharge and denoise; the shift register in the second driving module is switched to discharge and denoise by the second node, so that the output signals of the shift registers at each level in the second driving module are transmitted downward normally, thereby completing the function of shift registration.

[0243] In at least one embodiment of the shift register shown in FIG. 9A of the present disclosure, a fourth transistor M4 is added to discharge the second node PD, so that during the first half-screen scanning time of a frame time, the potential of the second node in the second driving module is a low voltage, and during the second half-screen scanning time of a frame time, the potential of the second node in the first driving module is a low voltage, so as to balance the bias stress of the TFT related to the second node.

[0244] Figure 9B is a simulation timing diagram of the final-stage driving signal provided by the first-stage first node PU1, the first-stage second node PD1, the final-stage first node PUL, the final-stage second node PDL and the final-stage output signal terminal GTL when the gate driving circuit includes at least one embodiment of the multi-stage shift register shown in Figure 9A of the present disclosure.

[0245] As shown in FIG10A , based on at least one embodiment of the shift register shown in FIG8 , the denoising control terminal may be a fourth power supply voltage signal terminal VD;

[0246] When the first power supply electrical signal terminal is electrically connected to the first first power supply voltage signal line, the fourth power supply voltage signal terminal may be electrically connected to the second first power supply voltage signal line;

[0247] When the first power supply electrical signal terminal is electrically connected to the second first power supply voltage signal line, the fourth power supply voltage signal terminal may be electrically connected to the first first power supply voltage signal line.

[0248] Figure 10B is a simulation timing diagram of the final-stage driving signal provided by the first-stage first node PU1, the first-stage second node PD1, the final-stage first node PUL, the final-stage second node PDL and the final-stage output signal terminal GTL when the gate driving circuit includes at least one embodiment of the multi-stage shift register shown in Figure 10A of the present disclosure.

[0249] As shown in FIG11A , based on at least one embodiment of the shift register shown in FIG8 , the first power supply voltage signal terminal is electrically connected to the first first power supply voltage signal line VDD1 , and the noise reduction control terminal is electrically connected to the second first power supply voltage signal line VDD2 .

[0250] In at least one embodiment of the shift register shown in FIG. 11A of the present disclosure, when VDD1 provides a high voltage signal and VDD2 provides a low voltage signal, the shift register performs scanning normally.

[0251] When VDD1 provides a low voltage signal and VDD2 provides a high voltage signal, M4 is turned on to discharge noise at the second node PD.

[0252] As shown in FIG11B , based on at least one embodiment of the shift register shown in FIG8 , the first power supply voltage signal terminal is electrically connected to the second first power supply voltage signal line VDD2 , and the noise reduction control terminal is electrically connected to the first first power supply voltage signal line VDD1 .

[0253] In at least one embodiment of the shift register shown in FIG. 11B of the present disclosure, when VDD2 provides a high voltage signal and VDD1 provides a low voltage signal, the shift register performs scanning normally.

[0254] When VDD2 provides a low voltage signal and VDD1 provides a high voltage signal, M4 is turned on to discharge noise from the second node PD.

[0255] The difference between at least one embodiment of the shift register shown in FIG. 12A of the present disclosure and at least one embodiment of the shift register shown in FIG. 7 is as follows: the gate of M3 is electrically connected to the third power supply voltage signal terminal VGH.

[0256] When at least one embodiment of the shift register shown in FIG12A of the present disclosure is in operation, the gate of M3 is electrically connected to VGH, VGH always provides a high voltage signal, and M3 always remains in an open state. When VDD provides a high voltage signal, the potential of PD is pulled high; when VDD provides a low voltage signal, VDD can directly pull down the potential of PD, and there is no need for M4 to pull down the potential of PD.

[0257] At least one embodiment of the shift register shown in FIG. 12A of the present disclosure requires an increase in VGH, which requires a stronger bias capability of M3.

[0258] Figure 12B is a simulation timing diagram of the final-stage driving signal provided by the first-stage first node PU1, the first-stage second node PD1, the final-stage first node PUL, the final-stage second node PDL and the final-stage output signal terminal GTL when the gate driving circuit includes at least one embodiment of the multi-stage shift register shown in Figure 12 of the present disclosure.

[0259] The gate driving circuit described in the embodiment of the present disclosure includes a plurality of cascaded shift registers as described above.

[0260] In at least one embodiment of the present disclosure, the shift register includes a first reset signal terminal; a plurality of cascaded shift registers are divided into M driving partitions, where M>1 and is an integer; in the same driving partition, the output signal terminal of the i-th stage shift register is electrically connected to the input signal terminal of the i+1-th stage shift register and the first reset signal terminal of the i-1-th stage shift register, respectively, where i is an integer, i is greater than or equal to 2 and less than or equal to N-1, and N is greater than or equal to 3 and is an integer;

[0261] The gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, and each drive partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register in the same drive partition is electrically connected to the reset signal line corresponding to the drive partition, and the first power supply voltage signal end of each shift register in the same drive partition is electrically connected to the first power supply voltage signal line corresponding to the drive partition.

[0262] In a second aspect, based on the same disclosed concept, in another optional embodiment, a gate drive circuit is provided, comprising a plurality of cascaded shift registers provided by the embodiment of the first aspect. The cascading method can be to cascade adjacent rows of shift registers sequentially, or to cascade shift registers spaced a certain number of rows apart, which is not limited herein. During the cascade, the output signal terminal of the shift register of the current stage is connected to the input signal terminal of the shift register of the next stage and the first reset signal terminal of the shift register of the previous stage.

[0263] Accordingly, in some embodiments, a timing control method for a gate driving circuit includes:

[0264] 1) In the input phase, controlling the input signal terminal to provide an input signal so that the input sub-circuit writes the input signal at the first node;

[0265] 2) in the output phase, controlling the clock signal terminal CLK to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node;

[0266] 3) in the reset phase, controlling the first reset signal terminal to input the first reset signal, so that the reset sub-circuit resets the first node through the second power supply voltage signal at the second power supply voltage signal terminal; and

[0267] 4) In the denoising stage: controlling the first power supply voltage signal terminal to input the first power supply voltage signal, so that the pull-down control sub-circuit writes the first power supply voltage signal to the second node, and the pull-down denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal; or controlling the second reset signal terminal TRST to input the second reset signal, so that the reset denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

[0268] It should be noted that the input signal, clock signal, first reset signal, second reset signal, and first power supply voltage signal in the above timing control process are effective signals for controlling the conduction of different types of transistors. For a shift register using N-type transistors, the above effective signals are high-level signals, while for a shift register using P-type transistors, the above effective signals are low-level signals.

[0269] In order to better improve the reliability performance of the shift register, the cascade relationship and timing control can be improved. In some embodiments, multiple cascaded shift registers are divided into M driving partitions, M>1 and is an integer; in the same driving partition, the output signal end of the i-th shift register is respectively connected to the input signal end of the i+1-th shift register and the first reset signal end of the i-1-th shift register, i is an integer between 2 and N-1, N≥3 and is an integer; the gate drive circuit also includes M first power supply voltage signal lines and M reset signal lines, one driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal end of each shift register in the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal end of each shift register in the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition.

[0270] After the multiple shift registers are divided into multiple drive partitions, the timing of the valid signals of the first power supply voltage signal line and the reset signal line corresponding to the different drive partitions can be controlled to adjust whether each drive partition performs discharge denoising through the pull-down denoising sub-circuit or the reset denoising sub-circuit, thereby reducing the problem of threshold voltage drift caused by long-term bias of the transistors related to the denoising sub-circuit.

[0271] In at least one embodiment of the present disclosure, in the time period of [(j-1)T / M, jT / M], the first power supply voltage signal line corresponding to the j-th driving partition is controlled to input the first power supply voltage signal, and the reset signal lines corresponding to the remaining driving partitions are controlled to input the second reset signal; wherein T is the display period or display time of a frame of image, and j is an integer ranging from 1 to M in sequence.

[0272] Specifically, in the display period T of each frame, the display period T is divided into corresponding sub-periods according to the number of drive partitions. In the jth sub-period, the first power supply voltage signal line of the jth drive partition is controlled to input a valid first power supply voltage signal, causing the pull-down denoising sub-circuit to operate, and discharging the pull-up node and the output signal terminal through the second node to perform denoising. Meanwhile, the reset signal line corresponding to the jth drive partition does not output a valid signal, placing the reset denoising sub-circuit in a rest state. For other drive partitions, the corresponding reset signal lines are controlled to output a valid second reset signal, while the first power supply voltage signal line does not output a valid signal, causing the reset denoising sub-circuit to operate and the pull-down denoising sub-circuit to rest. This prevents threshold voltage drift of the oxide TFT caused by long-term biasing.

[0273] For the sake of clarity, in an optional embodiment, M = 2 is used as an example. For a certain display product model, see the left portion of Figure 13 . 2880 shift registers are cascaded to form the gate drive circuit, which is divided into two drive partitions. The first drive partition, DA1, corresponds to the first drive module for driving the pixel circuits in the upper half of the screen and includes shift registers from stages 1 to 1440. The second drive partition, DA2, corresponds to the second drive module for driving the pixel circuits in the lower half of the screen and includes shift registers from stages 1441 to 2880. The shift registers employ the 10T1C architecture shown in Figure 6 .

[0274] In FIG13 , TRST1 is a first reset signal line, TRST2 is a second reset signal line, VDD1 is a first first power supply voltage signal line, and VDD2 is a second first power supply voltage signal line.

[0275] In Figure 13, the shift register labeled Y1 is the first level, the shift register labeled Y2 is the second level, the shift register labeled Y1439 is the 1439th level, the shift register labeled Y1440 is the 1440th level, the shift register labeled Y1441 is the 1441st level, the shift register labeled Y1442 is the 1442nd level, the shift register labeled Y2879 is the 2879th level, and the shift register labeled Y2880 is the 2880th level.

[0276] Corresponding to the two driving partitions, two first power supply voltage signal lines and reset signal lines are also set up to control the denoising sub-circuit. One first power supply voltage signal line is connected to the control electrodes of the third transistors of all shift registers in one driving partition, and the other first power supply voltage signal line is connected to the control electrodes of the first transistors of all shift registers in the other driving partition; the reset signal line is similarly connected to the control electrodes of the corresponding first transistors and second transistors.

[0277] The right part of Figure 13 provides the timing control flow of the gate drive circuit, which divides a display cycle into two half-frame sub-cycles: the upper half-frame sub-cycle and the lower half-frame sub-cycle. Each half-frame sub-cycle includes an input phase t1, an output phase t2, a reset phase t3, and a denoising phase t4.

[0278] In the first driving partition DA1 corresponding to the first half frame sub-period, the corresponding first first power supply voltage signal line VDD1 continuously inputs the first power supply voltage signal of a high level, and the first reset signal line TRST1 remains in a low level state. The timing control process includes:

[0279] In the input phase t1, the input signal terminal INT inputs a high-level input signal, turning on the ninth transistor and writing the high-level input signal into the first node PU. Simultaneously, the first node PU in the high-level state turns on the seventh transistor, writing the first low-level signal provided by the first low-level signal terminal LVGL into the second node PD, keeping the second node PD in the low-level state.

[0280] In the output phase t2, the input signal terminal INT becomes a low level state, and the potential of the first node PU is further pulled up by the coupling effect of the capacitor, so that the eleventh transistor is turned on and the high level clock signal provided by the clock signal terminal is output to the output signal terminal GT;

[0281] In the reset phase t3, the first reset signal terminal RST inputs the high-level output signal of the next-stage shift register as the first reset signal, turning on the tenth transistor, and the potential of the first node PU is pulled low by the first low-level signal terminal; and

[0282] In the denoising stage t4, after the potential of the first node PU is pulled low, the seventh transistor is turned off, and the first power supply voltage signal provided by the first power supply voltage signal terminal is written into the second node PD through the third transistor, so that the second node PD becomes a high potential state, thereby turning on the fifth transistor and the sixth transistor, and discharging the first node PU through the first low-level signal terminal to reduce noise, and discharging the output signal terminal GT through the second low-level signal terminal to reduce noise.

[0283] Therefore, during the first half-frame sub-period, the first drive sub-area DA1 operates at the second node PD, discharging and de-noising the pull-up node PU and the output signal terminal GT. Signals from level 1 to level 1440 are transmitted via a high-level clock signal from the output signal terminal GT, while the first reset signal line TRST1 corresponding to the first drive sub-area DA1 is in a low-level output state.

[0284] In the second driving partition DA2 corresponding to the second half-frame sub-period, the corresponding second first power supply voltage signal line VDD2 remains in a low level state, so that the second node PD remains in a low level state, and the second reset signal line TRST2 continuously outputs a high-level second reset signal, so that the first transistor and the second transistor remain in the on state, and all shift registers in the second driving partition DA2 denoise the first node PU and the output signal terminal GT through the reset denoising sub-circuit.

[0285] When the display cycle reaches the second half frame, the first first power supply voltage signal line VDD1 corresponding to the first driving partition DA1 remains in a low level state, so that the second node PD remains in a low level state, and the first reset signal line TRST1 continues to output a high-level second reset signal. All shift registers in the first driving partition DA1 continue to denoise the first node PU and the output signal terminal GT through the reset denoising sub-circuit.

[0286] In the second drive sub-area DA2 corresponding to the second half-frame sub-cycle, the corresponding second first power supply voltage signal line VDD2 continuously receives a high-level first power supply voltage signal, while the second reset signal line TRST2 remains in a low-level state. The timing control process is the same as that of the first drive sub-area DA1 in the first half-frame. That is, during the second half-frame to cycle, the second drive sub-area DA2 operates at the second node PD, performing discharge and noise reduction on the first node PU and the output signal terminal GT. Signal transmission from level 1441 to level 2880 is achieved via a high-level clock signal at the output signal terminal GT, while the second reset signal line TRST2 corresponding to the second drive sub-area DA2 remains in a low-level output state.

[0287] Generally speaking, during the top half-frame sub-period, when the first driver module performs shift register operation, the first set of first power supply voltage signal lines VDD1 and second reset signal lines TRST2 are in a high state, while the second set of first power supply voltage signal lines VDD2 and first reset signal lines TRST1 are in a low state. At this point, the output signals of the shift registers from stages 1 to 1440 are normally transmitted downward, discharged and de-noised at the second node PD, and the first reset signal line TRST1 turns off the corresponding first and second transistors. For the second driver sub-area DA2 in the bottom half of the screen, i.e., the shift registers from stages 1441 to 2880, discharge and de-noise are controlled by the second reset signal line TRST2. During this stage, stages 1441 to 2880 do not transmit output signals, so the second reset signal line TRST2 can be used for discharge and de-noise.

[0288] When the output signal is transmitted to the 1441th level, it enters the second half frame sub-cycle, the first first power supply voltage signal line VDD1 switches to a low level state, and the first reset signal line TRST1 switches to a high level state. At this time, the discharge of the 1st-level shift register to the 1440th-level shift register is controlled by the second node PD and switched to the discharge denoising controlled by the second reset signal terminal TRST; at the same time, the second first power supply voltage signal line VDD2 switches to a high level state, and the second reset signal line TRST2 switches to a low level state. The 1441st-level shift register to the 2880th-level shift register is transformed into the discharge denoising controlled by the second node PD to cope with the output signal being transmitted from the 1441st level to the 2880th level, thereby completing the function of the GOA shift register.

[0289] Therefore, the gate drive circuit provided in at least one embodiment of the present disclosure performs zoned and timed discharge denoising on the upper and lower half screens, utilizing the second node PD and the second reset signal terminal TRST to discharge and denoise the first node PU and the output signal terminal GT of the shift register within the display cycle or display time of a frame. Compared to a discharge circuit with a single second node without the second transistor, such as a 9T1C structure, the positive bias time PB and negative bias time NB of the third transistor, fifth transistor, and sixth transistor associated with the second node PD, and the first transistor and second transistor associated with the second reset signal terminal TRST in the shift register described in at least one embodiment of the present disclosure are both 50%. By adjusting the timing of the positive and negative bias voltages, the bias operating state of the key oxide TFT is balanced, significantly improving the stability of the oxide TFT, and improving the yield and reliability of the shift register and the gate drive circuit. Table 2 provides the bias time and nominal size of each oxide TFT in the 9T1C shift register during operation, as well as the bias time and nominal size of each oxide TFT in the 10T1C shift register during operation. In Table 2, W / L represents the ratio of the channel width W to the channel length L of each transistor, PBT represents the positive bias time percentage, and NBT represents the negative bias time percentage. To reduce the bezel, the channel width W of each TFT is optimized to achieve the minimum W required for normal operation of the gate drive circuit.

[0290] Table 2

[0291] In the above embodiment, the gate drive circuit based on the 10T1C shift register is subjected to zoned and timed discharge denoising. This primarily involves dividing the gate drive circuit within a display product or screen into two drive zones, and adding a first reset signal line TRSR1 and a second reset signal line TRST2 to achieve discharge denoising. While one drive zone discharges through the second node PD, the other drive zone can discharge through either the first reset signal line TRST1 or the second reset signal line TRST2. This switching mechanism achieves time-divided and zoned discharge. It should be noted that the two drive zones described above are exemplary. In some embodiments, the gate drive circuit can be divided into multiple or more drive zones for time-divided discharge denoising, and additional first power supply voltage signal lines and reset signal lines can be added. In this design, the gate drive circuit can achieve signal transmission when discharging through the second node PD, but cannot achieve signal transmission when discharging through the reset signal terminal TRST. Therefore, it is necessary to determine whether discharge denoising is performed through the second node PD or the reset signal line based on the drive signal transmission.

[0292] Figure 14A is a schematic diagram of the timing control simulation of the gate drive circuit. In Figure 14A, PU1 represents the first node in the first-level shift register, GT1 represents the output signal end of the first-level shift register, PU1441 represents the first node of the 1441st-level shift register, and GT1441 represents the output signal end of the 1441st-level shift register; PD1 represents the second node in the 1440th-level shift register to the 1441st-level shift register, and PD2 represents the second node in the 2880th-level shift register to the 1441st-level shift register. The first reset signal line TRST1 switches earlier than PD1 to ensure the discharge and denoising of the 1st-level shift register to the 1440th-level shift register; the second reset signal line TRST2 must switch to a low level before the 1441st-level shift register starts working to ensure that the drive signal is transmitted to the 1441st-level shift register. PD2 officially starts discharging after the output of the 1441st-level shift register is completed. The simulation results in FIG14A verify that the 10T1C shift register can satisfy the normal operation of the gate drive circuit.

[0293] In at least one embodiment of the present disclosure, the denoising sub-circuit further includes a second node denoising sub-circuit; the denoising control terminal is a fourth power supply voltage signal terminal;

[0294] The gate driving circuit further includes M fourth power supply voltage signal lines; one driving partition corresponds to one fourth power supply voltage signal line;

[0295] The fourth power supply voltage signal terminal of each shift register in the same driving subarea is electrically connected to the fourth power supply voltage signal line corresponding to the driving subarea.

[0296] In at least one embodiment of the present disclosure, M is equal to 2; the first fourth power supply voltage signal line and the second first power supply voltage signal line are the same signal line, and the second fourth power supply voltage signal line and the first first power supply voltage signal line are the same signal line;

[0297] The first power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the first first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the first driving subarea is electrically connected to the second first power supply voltage signal line;

[0298] The first power supply voltage signal terminal of each shift register in the second driving subarea is electrically connected to the second first power supply voltage signal line, and the fourth power supply voltage signal terminal of each shift register in the second driving subarea is electrically connected to the first first power supply voltage signal line.

[0299] In at least one embodiment of the present disclosure, the structure of the shift register in FIG. 13 may also be as shown in FIG. 7 , 8 , 9 , 10 , and 12 , and the shift register in FIG. 13 may be an 11T1C shift register.

[0300] In the related 18T1C shift register, the channel width-to-length ratio of M8 is 20 / 5, the positive bias time of M8 accounts for less than 1%, and the negative bias time of M8 accounts for more than 99%; the channel width-to-length ratio of M9 is 6 / 5, the positive bias time of M9 accounts for less than 1%, and the negative bias time of M9 accounts for more than 99%; the channel width-to-length ratio of M10 is 600 / 5, the positive bias time of M10 accounts for less than 1%, and the negative bias time of M10 accounts for more than 99%; M1A The channel width-to-length ratio is 6 / 5, the positive bias time of M1A is 50%, and the negative bias time of M1A is 50%; the channel width-to-length ratio of M1B is 6 / 5, the positive bias time of M1B is 50%, and the negative bias time of M1B is 50%; the channel width-to-length ratio of M6A is 30 / 5, the positive bias time of M6A is less than 1%, and the negative bias time of M6A is greater than 99%; the channel width-to-length ratio of M6B is 30 / 5, the positive bias time of M6B is less than 1%, and the negative bias time of M6B is less than 1%. The bias time is greater than 99%; the channel width-to-length ratio of M7A is 30 / 5, the positive bias time of M7A is less than 1%, and the negative bias time of M7A is greater than 99%; the channel width-to-length ratio of M7B is 30 / 5, the positive bias time of M7B is less than 1%, and the negative bias time of M7B is greater than 99%; the channel width-to-length ratio of M2A is 15 / 5, the positive bias time of M2A is 50%, and the negative bias time of M2A is 50%; the channel width-to-length ratio of M2B is 15 / 5, and the M2 The positive bias time of M2B is 50%, and the negative bias time of M2B is 50%; the channel width-to-length ratio of M3A is 20 / 5, the positive bias time of M3A is 50%, and the negative bias time of M3A is 50%; the channel width-to-length ratio of M3B is 20 / 5, the positive bias time of M3B is 50%, and the negative bias time of M3B is 50%; the channel width-to-length ratio of M4 is 600 / 5, the negative bias time of M15 is less than 1%, and the positive bias time of M4 is greater than 99%;

[0301] In the relevant 9T1C pixel circuit, the channel width-to-length ratio of M9 is 20 / 5, the positive bias time of M9 accounts for less than 1%, and the negative bias time of M9 accounts for more than 99%; the channel width-to-length ratio of M10 is 6 / 5, the positive bias time of M10 accounts for less than 1%, and the negative bias time of M10 accounts for more than 99%; the channel width-to-length ratio of M11 is 600 / 5, the positive bias time of M11 accounts for less than 1%, and the negative bias time of M11 accounts for more than 99%; the channel width-to-length ratio of M3 is 6 / 5, and the positive bias time of M3 accounts for 100%; the channel width-to-length ratio of M7 is 30 / 5, and the positive bias time of M7 accounts for less than 1%. The time proportion of M7 is less than 1%, and the negative bias time proportion of M7 is greater than 99%; the channel width-to-length ratio of M8 is 30 / 5, the positive bias time proportion of M8 is less than 1%, and the negative bias time proportion of M8 is greater than 99%; the channel width-to-length ratio of M5 is 15 / 5, the positive bias time proportion of M5 is greater than 99%, and the negative bias time proportion of M5 is less than 1%; the channel width-to-length ratio of M6 is 20 / 5, the positive bias time proportion of M6 is greater than 99%, and the negative bias time proportion of M6 is less than 1%; the channel width-to-length ratio of M2 is 20 / 5, the positive bias time proportion of M2 is less than 1%, and the negative bias time proportion of M2 is greater than 99%.

[0302] In at least one embodiment of the 11T1C shift register of the present disclosure, the channel width-to-length ratio of M9 is 20 / 5, the positive bias time of M9 accounts for less than 1%, and the negative bias time of M9 accounts for more than 99%; the channel width-to-length ratio of M10 is 6 / 5, the positive bias time of M10 accounts for less than 1%, and the negative bias time of M10 accounts for more than 99%; the channel width-to-length ratio of M11 is 600 / 5, the positive bias time of M11 accounts for less than 1%, and the negative bias time of M11 accounts for more than 99%; the channel width-to-length ratio of M3 is 6 / 5, the positive bias time of M3 accounts for 50%, and the negative bias time of M3 accounts for 50%; the channel width-to-length ratio of M7 is 30 / 5, the positive bias time of M7 accounts for less than 1%, and the negative bias time of M7 accounts for more than 99%; the channel width-to-length ratio of M8 is 600 / 5, the positive bias time of M11 accounts for less than 1%, and the negative bias time of M11 accounts for more than 99%; The channel width-to-length ratio of M5 is 15 / 5, the positive bias time of M5 is 50%, and the negative bias time of M5 is 50%; the channel width-to-length ratio of M4 is 15 / 5, the positive bias time of M4 is 50%, and the negative bias time of M4 is 50%; the channel width-to-length ratio of M1 is 20 / 5, the positive bias time of M1 is 50%, and the negative bias time of M1 is 50%; the channel width-to-length ratio of M6 is 20 / 5, the positive bias time of M6 is 50%, and the negative bias time of M6 is 50%; the channel width-to-length ratio of M2 is 20 / 5, the positive bias time of M2 is 50%, and the negative bias time of M2 is 50%.

[0303] From the above comparison, it can be seen that the shift register described in at least one embodiment of the present disclosure can achieve a state of positive and negative bias balance, and the effect of the double second node in the 18T1C shift register is achieved by using the 11T1C shift register.

[0304] In at least one embodiment of the present disclosure, it is assumed that the gate driving circuit includes a 2N-stage shift register (the structure of the shift register is the 11T1C structure in at least one embodiment of the present disclosure), where N is a positive integer; the intermediate stages are the Nth stage and the N+1th stage, where the Nth stage is the last stage in the first driving module and the N+1th stage is the first stage in the second driving module. FIG14B shows the simulation results of the intermediate-stage shift register;

[0305] As shown in FIG14B , the first node PUN of the Nth stage and the second node PDN of the Nth stage are operating normally, and the output signal terminal GTN of the Nth stage included in the Nth stage shift register is outputting the Nth stage driving signal normally. At the same time, the first node PUN+1 of the N+1th stage, the second node PDN+1 of the N+1th stage, and the output signal terminal GTN+1 of the N+1th stage are operating normally, indicating that when the second reset signal and the first power supply voltage signal of the upper and lower half-screens are switched, the driving signal is successfully transmitted from the upper half-screen to the lower half-screen. The timing of the signal provided by VDD1, the signal provided by TRST1, the signal provided by VDD2, and the signal provided by TRST2 is shown in FIG14B .

[0306] After GTN provides a high voltage signal, TRST1 starts to provide a high voltage signal; before the potential of PUN+1 becomes a high voltage, VDD2 starts to provide a high voltage signal. After VDD2 provides a high voltage, after 1H (one row scanning time), TRST2 starts to provide a high voltage signal to ensure signal transmission between the N-stage shift register and the N+1-stage shift register;

[0307] FIG15 is a simulation result of the final shift register; the simulation result is a simulation result of one frame time, wherein the signal provided by VDD1, the signal provided by VDD2, the signal provided by TRST1, and the signal provided by TRST2 are switched in the middle row;

[0308] As shown in Figure 15, the first node PUL of the last-stage shift register and the second node PDL of the last-stage shift register can both operate normally. The timing of the drive signal output by the output signal terminal GTL of the last-stage shift register is also consistent with expectations, proving that the drive signal can be transmitted normally to the last row, the gate drive circuit operates normally, and there is no noise, multiple output, insufficient output, or other problems. The 11T1C shift register is very stable.

[0309] In FIG15 , the terminal labeled STV is a starting voltage terminal.

[0310] In a third aspect, an embodiment of the present disclosure provides a driving method of a gate driving circuit, which is applied to the above-mentioned gate driving circuit, and the driving method includes:

[0311] The first power supply voltage signal terminal is controlled to input the first power supply voltage signal, so that the pull-down control sub-circuit writes the first power supply voltage signal to the second node, and the pull-down denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal; or the second reset signal terminal is controlled to input the second reset signal, so that the reset denoising sub-circuit discharges the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the second reset signal.

[0312] In at least one embodiment of the present disclosure, the shift register further includes an input subcircuit, an output subcircuit, and a reset subcircuit; and the driving method further includes:

[0313] Controlling the input signal terminal to input an input signal so that the input sub-circuit writes the input signal at the first node;

[0314] controlling the clock signal terminal to input a clock signal, so that the output sub-circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node;

[0315] The first reset signal terminal is controlled to input the first reset signal, so that the reset sub-circuit resets the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal.

[0316] In at least one embodiment of the present disclosure, the plurality of cascaded shift registers are divided into M driving partitions, the gate drive circuit further includes M first power supply voltage signal lines and M reset signal lines, and each driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal terminal of each shift register in the same driving partition is connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal terminal of each shift register in the same driving partition is connected to the first power supply voltage signal line corresponding to the driving partition;

[0317] The driving method includes: when scanning the shift register in the j-th driving partition,

[0318] The first power supply voltage signal line corresponding to the j-th driving partition is controlled to input a valid first power supply voltage signal; and the reset signal lines corresponding to the remaining driving partitions except the j-th driving partition are controlled to input a valid second reset signal.

[0319] The driving method according to at least one embodiment of the present disclosure further includes: when scanning the shift register in the j-th driving partition,

[0320] The reset signal line corresponding to the jth driving subarea is controlled to input an invalid second reset signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the jth driving subarea are controlled to input an invalid first power supply voltage signal.

[0321] In at least one embodiment of the present disclosure, the denoising sub-circuit further includes a second node denoising sub-circuit; the denoising control terminal is a fourth power supply voltage signal terminal; the gate drive circuit further includes M fourth power supply voltage signal lines; each drive partition corresponds to one fourth power supply voltage signal line; the fourth power supply voltage signal terminal of each shift register within the same drive partition is electrically connected to the fourth power supply voltage signal line corresponding to the drive partition; and the driving method further includes:

[0322] When scanning the shift register in the j-th driving partition,

[0323] The fourth power supply voltage signal line corresponding to the jth driving subarea is controlled to input an invalid first power supply voltage signal, and the first power supply voltage signal lines corresponding to the remaining driving subareas except the jth driving subarea are controlled to input a valid fourth power supply voltage signal.

[0324] In a fourth aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0325] A base substrate, the base substrate comprising a display area and a peripheral area;

[0326] A plurality of cascaded shift registers are provided in the peripheral area.

[0327] In at least one embodiment of the present disclosure, no more than two columns of shift registers are arranged in a peripheral area on the same side of the display area, and the area where each column of shift registers is located includes a first sub-area and a second sub-area. The input sub-circuit, the reset sub-circuit, and the denoising sub-circuit are located in the first sub-area, and the output sub-circuit is located in the second sub-area. The second sub-area is closer to the display area than the first sub-area.

[0328] The denoising subcircuit includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, the input subcircuit includes a ninth transistor, and the reset subcircuit includes a tenth transistor;

[0329] The array substrate further includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line and a reset signal line, wherein the second power supply voltage signal line includes a first low-level signal line and a second low-level signal line;

[0330] In the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line and the second low-level signal line are arranged in sequence; the third transistor is arranged on a side of the first power supply voltage signal line away from the second sub-region, the second transistor and the fifth transistor are arranged on a side of the reset signal line close to the second sub-region, the eighth transistor and the seventh transistor are arranged on a side of the first low-level signal line away from the second sub-region, the ninth transistor and the tenth transistor are arranged on a side of the first low-level signal line close to the second sub-region, and the first transistor and the sixth transistor are arranged on a side of the second low-level signal line close to the second sub-region.

[0331] In at least one embodiment of the present disclosure, the output sub-circuit includes an eleventh transistor and a capacitor. In a column direction of a column of the shift registers, the eleventh transistor and the capacitor are alternately arranged in sequence.

[0332] In at least one embodiment of the present disclosure, a channel width-to-length ratio of the eleventh transistor is greater than or equal to 120:5 and less than or equal to 300:5.

[0333] In at least one embodiment of the present disclosure, the channel of the eleventh transistor includes a plurality of sub-channels connected in series, and a channel width-to-length ratio of each of the sub-channels is 20:5.

[0334] An array substrate according to at least one embodiment of the present disclosure includes:

[0335] The base substrate includes a display area and a peripheral area; and a plurality of cascaded shift registers provided by the first embodiment and arranged in the peripheral area.

[0336] In some embodiments, by combining the cascade mode of the shift register provided by the first aspect embodiment and the shift register provided by the second aspect embodiment, the width of the peripheral area can be effectively reduced, thereby broadening the application of oxide technology in display products, especially VR (virtual reality) display products.

[0337] Some high-PPI (pixel density) display products have a problem with insufficient GOA (Gate On Array) pitch (gate drive circuitry provided in the array substrate). For example, the aforementioned 2117PPI display product has a GOA pitch of only 16μm, which is insufficient to accommodate a set of shift registers. To address this issue, in some embodiments, no more than two columns of shift registers are arranged in the peripheral area on the same side of the display area. For high-PPI display products, arranging the shift registers in two columns can effectively solve the problem of insufficient GOA pitch.

[0338] Figure 16 provides a schematic diagram of the shift register layout. From left to right, the peripheral area includes: a cutting area CT, which is the trimming area of ​​the display panel; a signal wiring area Sig, which is used to arrange various signal traces; a first shift register column LG1 and a second shift register column LG2, which are arranged adjacent to each other. In Figure 16, the first shift register column LG1 is provided with a second-stage shift register Y2 and a fourth-stage shift register Y4, while the second shift register column LG2 is provided with a first-stage shift register Y1 and a third-stage shift register Y3; a common voltage area; and a redundant area Com. The display area is located on the side of Com away from the second sub-area ZA2.

[0339] In some embodiments, please refer to the modular layout diagram of the circuit of the first column of shift registers LG1 provided in Figure 17. The area where each column of shift registers is located includes a first sub-area ZA1 and a second sub-area ZA2. The input sub-circuit 10, the reset sub-circuit 30 and the denoising sub-circuit 40 are located in the first sub-area ZA1, and the output sub-circuit 20 is located in the second sub-area ZA2. The second sub-area ZA2 is closer to the display area than the first sub-area ZA1.

[0340] Taking the 10T1C shift register provided in the embodiment of the first aspect as an example, in some embodiments, the denoising sub-circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8; the input sub-circuit 10 includes a ninth transistor M9; and the reset sub-circuit 30 includes a tenth transistor M10; the array substrate further includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line, and a reset signal line; the second power supply voltage signal line includes a first low-level signal line and a second low-level signal line; in a direction from the first sub-region ZA1 to the second sub-region ZA2, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line, and the second low-level signal line are arranged in sequence;

[0341] The third transistor M3 is arranged on a side of the first power supply voltage signal line away from the second sub-region ZA2, the second transistor 2 and the fifth transistor M5 are arranged on a side of the reset signal line close to the second sub-region ZA2, the eighth transistor M8 and the seventh transistor M7 are arranged on a side of the first low-level signal line away from the second sub-region ZA2, the ninth transistor M9 and the tenth transistor M10 are arranged on a side of the first low-level signal line close to the second sub-region ZA2, and the first transistor M1 and the sixth transistor M6 are arranged on a side of the second low-level signal line close to the second sub-region ZA2.

[0342] Referring to FIG18 , the circuit layout diagram of the input sub-circuit 10, reset sub-circuit 30, and denoising sub-circuit 40 in the first drive sub-area DA1 located in the upper half of the screen is shown. From left to right, i.e., in the direction from the edge of the peripheral area to the edge of the display area (horizontally), the following are arranged in sequence: the third transistor M3, the first first power supply voltage signal line VDD1, the first reset signal line TRST1, the second transistor M2, the fifth transistor M5, the eighth transistor M7, the seventh transistor M7, the first low-level signal line LVGL, the ninth transistor M9, the tenth transistor M10, the first clock signal line CLK1, the second clock signal line CLK2, the second reset signal line TRST2, the second low-level signal line VGL, the first transistor M1, and the sixth transistor M6. This arrangement of the transistors and signal lines represents a currently preferred layout design, which can further reduce the bezel of the display product.

[0343] In some embodiments, the output sub-circuit 20 includes an eleventh transistor M11 and a capacitor C. In a column direction of a column of shift registers, the eleventh transistor M11 and the capacitor C are alternately arranged in sequence.

[0344] Figure 19 provides a layout design for the output sub-circuit 20. In the column direction, that is, the vertical direction of the peripheral area or the column direction of the pixel array, the eleventh transistor M11 is arranged in a sequence with the capacitor C at the top and the capacitor C at the bottom. It should be noted that the "top" and "bottom" here do not refer to the up-and-down position relationship in the thickness direction of the array substrate, but rather to the up-and-down relationship in the plane direction of the array substrate. By placing the capacitor C below the eleventh transistor M11, the capacitor C can be prevented from increasing the border width.

[0345] After the shift register adopts the 10T1C architecture provided by the embodiment of the first aspect, combined with the above-mentioned peripheral area layout design, the border can be compressed to 1.74mm. Specifically, the width L1 of the cutting area CT is approximately 0.2mm, the width L2 of the signal wiring area Sig is approximately 0.1mm, the width L3 of the first shift register column LG1 is approximately 0.67mm, the width L4 of the second shift register column LG2 is approximately 0.67mm, and the width L5 of the common voltage area and redundant area Com is approximately 0.1mm. The total width L1+L2+L3+L4+L5=1.74mm. Currently, the minimum border width required for the gate drive circuit of the 18T1C shift register based on oxide TFT technology is 2.2mm. The 10T1C shift register and corresponding gate drive circuit provided by at least one embodiment of the present disclosure can narrow the border to 1.74mm, thereby achieving the effect of reducing the border width by 0.46mm, which well meets the needs of VR display products.

[0346] In some embodiments, the channel width-to-length ratio of the eleventh transistor M11 is 120:5 to 300:5. The channel width of the eleventh transistor M11 affects the frame width, so the channel parameters of the eleventh transistor M11 can be determined according to actual needs and PPI design.

[0347] 17 to 19 , it can be seen that approximately 40% of the border is occupied by the eleventh transistor M11. Currently, the channel width W of the eleventh transistor M11 is approximately 300 μm. Therefore, further narrowing the border can be achieved by reducing the channel width W of the eleventh transistor M11.

[0348] In some embodiments, the control electrode of the eleventh transistor M11 includes a first gate and a second gate, and the first gate and the second gate are connected to the first node PU. That is, as shown in Figure 20, the eleventh transistor M11 can adopt a dual-gate design, including a top gate TG and a bottom gate BG, and the channel CL is flanked by source and drain metal layers SD, one side being the source and the other side being the drain. By adding the bottom gate BG and applying a pull-up signal to the top gate TG and the bottom gate BG at the same time, that is, connecting to the pull-up node PU, the on-state current (Ion) of the eleventh transistor M11 can be increased, thereby supporting the reduction of the channel width W of the eleventh transistor M11 and achieving the purpose of reducing the border.

[0349] In some embodiments, as shown in FIG. 19 , the channel of the eleventh transistor M11 includes multiple sub-channels connected in series, each with a width-to-length ratio of 20:5. Specifically, the channel structure utilizes a unit cell segmentation design, where a unit cell, or sub-channel, has a channel width of 20μm. Multiple sub-channels are connected in series to form the complete channel structure of the eleventh transistor M11. This unit cell segmentation design across the channel width can better address heat dissipation issues associated with the oxide TFT due to increased on-state current Ion.

[0350] Table 3 provides the channel width-to-length ratio (W / L) of the eleventh transistor M11 and the corresponding bezel width for different on-state currents (Ion). Using the current dual-gate design, the on-state current (Ion) can reach 5.5 mA (milliamperes), a 60% increase, allowing the bezel to be narrowed to 1.38 mm.

[0351] Table 3

[0352] In summary, the shift register provided in at least one embodiment of the present disclosure has a denoising subcircuit including a pull-down control subcircuit 41, a pull-down denoising subcircuit 42, and a reset denoising subcircuit 43. The denoising subcircuit can selectively perform discharge denoising on the first node PU and the output signal terminal GT using the second power supply voltage signal terminal VG under the control of the potential of the second node PD, or perform discharge denoising on the first node PU and the output signal terminal GT using the second power supply voltage signal terminal VG under the control of the second reset signal terminal TRST. Therefore, the shift register provided in the present disclosure only needs to use a set of second nodes PD and corresponding denoising subcircuits to achieve discharge denoising on the first node PU and the output signal terminal GT. Compared with the solution of using two sets of second nodes and corresponding denoising circuits to alternately perform discharge denoising, it can not only reduce the number of components of the denoising subcircuit, thereby reducing the frame size of display products with high PPI requirements, but also avoid the performance drift of the circuit components in the denoising subcircuit due to being in a bias state for a long time, thereby improving the reliability of the shift register.

[0353] On this basis, the gate drive circuit and array substrate obtained by using the above-mentioned shift register 100 have the following characteristics:

[0354] 1) Aiming at high PPI applications such as VR display, the oxide process route of LCD (liquid crystal display) is adopted, with a PPI of more than 2000 as the basis. In order to cope with the problem of increased border caused by the significant reduction of GOAPitch brought about by ultra-high PPI, the noise reduction sub-circuit and corresponding timing control of the shift register 100 using oxide TFT are adjusted to reduce the number of oxide TFTs in the shift register, thereby reducing the border width, solving the problem of increased border width of ultra-high PPI display products, and providing core technical support for high-end VR display products.

[0355] 2) In order to reduce the left and right borders of the display product, the denoising sub-circuit of the shift register, as well as the cascade and timing control of the gate drive circuit, are improved. Specifically, within a frame display time or display cycle, the second node PD and the second reset signal terminal TRST are used to partition and time-share the discharge denoising of the shift register, thereby reducing the bias time of the transistor associated with the second node PD or the second reset signal terminal TRST; reducing the threshold voltage drift of the oxide TFT, and improving the reliability of the gate drive circuit while simplifying the gate drive circuit and reducing the border width, thereby increasing the service life of the display product.

[0356] 3) Based on the 10T1C circuit architecture, a dual-gate device design was added to the output transistor, the eleventh transistor M11, to increase the on-state current Ion, reduce the transistor size, and further reduce the border. At the same time, the layout of the shift register in the peripheral area was optimized, and the layout of the oxide TFT and signal routing was optimized as much as possible to achieve the goal of minimizing the border.

[0357] In a fifth aspect, based on the same disclosed concept, in another optional embodiment, a display device is provided, comprising the array substrate provided in the embodiment of the fourth aspect. The display device may be a display panel, a display module, or a display device. The display panel may be a liquid crystal display panel. The display module is a module in which various chips and circuit boards are bound or mounted on the display panel. The display device may be a VR display product, or an electronic device with a display screen, such as a monitor, a flat-screen TV, a tablet computer, a mobile phone, or a car display.

[0358] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0359] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A shift register, comprising a noise removing circuit; The noise removing circuit includes a pull-down control sub-circuit, a pull-down noise removing circuit, and a reset noise removing circuit; The pull-down control sub-circuit is electrically connected to a first power supply voltage signal terminal and a second node respectively, and is configured to write a first power supply voltage signal provided by the first power supply voltage signal terminal into the second node; The pull-down noise removing circuit is electrically connected to the second node, a first node, a second power supply voltage signal terminal, and an output signal terminal respectively, and is configured to discharge the first node and the output signal terminal through the second power supply voltage signal terminal under the control of the potential of the second node; The reset noise removing circuit is electrically connected to a second reset signal terminal, the first node, the second power supply voltage signal terminal, and the output signal terminal respectively, and is configured to discharge the pull-up node and the output signal terminal through the second power supply voltage signal terminal under the control of a second reset signal provided by the second reset signal terminal.

2. The shift register according to claim 1, wherein The pull-down control sub-circuit is further electrically connected to a third power supply voltage signal terminal, and is configured to write the first power supply voltage signal into the second node under the control of a third power supply voltage signal provided by the third power supply voltage signal terminal.

3. The shift register according to claim 1, wherein, The noise removing circuit further includes a second node noise removing circuit; The second node noise removing circuit is electrically connected to a noise removing control terminal, the second node, and a second power supply voltage signal terminal respectively, and is configured to control the connection between the second node and the second power supply voltage signal terminal under the control of a noise removing control signal provided by the noise removing control terminal; The noise removing control terminal is the second reset signal terminal or a fourth power supply voltage signal terminal.

4. The shift register according to claim 1, wherein The reset noise removing circuit includes a first transistor and a second transistor; A control electrode of the first transistor is electrically connected to the second reset signal terminal, a first electrode of the first transistor is electrically connected to the output signal terminal, and a second electrode of the first transistor is electrically connected to the second power supply voltage signal terminal; A control electrode of the second transistor is electrically connected to the second reset signal terminal, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the second power supply voltage signal terminal.

5. The shift register according to claim 2, wherein, The pull-down control sub-circuit includes a third transistor; A control electrode of the third transistor is electrically connected to the third power supply voltage signal terminal, a first electrode of the third transistor is electrically connected to the first power supply voltage signal terminal, and a second electrode of the third transistor is electrically connected to the second node.

6. The shift register according to claim 1, wherein, The pull-down control sub-circuit includes a third transistor; Both a control electrode and a first electrode of the third transistor are electrically connected to the first power supply voltage signal terminal, and a second electrode of the third transistor is electrically connected to the second node.

7. The shift register according to claim 3, wherein, The second node noise removing circuit includes a fourth transistor; A control electrode of the fourth transistor is electrically connected to the noise removing control terminal, a first electrode of the fourth transistor is electrically connected to the second node, and a second electrode of the fourth transistor is electrically connected to the second power supply voltage signal terminal.

8. The shift register according to claim 1, wherein, The pull-down noise removing circuit includes a fifth transistor and a sixth transistor; The control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the second power supply voltage signal terminal; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the output signal terminal, and the second electrode of the sixth transistor is electrically connected to the second power supply voltage signal terminal; The noise reduction circuit further includes a seventh transistor and an eighth transistor; The control electrode of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the second power supply voltage signal terminal; The control electrode of the eighth transistor is electrically connected to the input signal terminal, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the second power supply voltage signal terminal.

9. The shift register according to any one of claims 1 to 8, wherein It further includes an input sub-circuit, an output sub-circuit and a reset sub-circuit; The input sub-circuit is respectively electrically connected to the input signal terminal and the first node, and is configured to write an input signal to the first node under the control of the input signal provided by the input signal terminal; The output sub-circuit is respectively electrically connected to the clock signal terminal, the first node and the output signal terminal, and is configured to output the clock signal provided by the clock signal terminal to the output signal terminal under the control of the potential of the first node; The reset sub-circuit is respectively electrically connected to the first reset signal terminal, the first node and the second power supply voltage signal terminal, and is configured to reset the first node by the second power supply voltage signal provided by the second power supply voltage signal terminal under the control of the first reset signal provided by the first reset signal terminal.

10. The shift register according to claim 9, wherein, The input sub-circuit includes a ninth transistor; the reset sub-circuit includes a tenth transistor, and the output sub-circuit includes an eleventh transistor and a capacitor; The control electrode and the first electrode of the ninth transistor are both electrically connected to the input signal terminal, and the second electrode of the ninth transistor is electrically connected to the first node; The gate of the tenth transistor is electrically connected to the first reset signal terminal, the first electrode of the tenth transistor is electrically connected to the first node, and the second electrode of the tenth transistor is electrically connected to the second power supply voltage signal terminal; The gate of the eleventh transistor is electrically connected to the first node, the first electrode of the eleventh transistor is electrically connected to the clock signal terminal, and the second electrode of the eleventh transistor is electrically connected to the output signal terminal; The first end of the capacitor is electrically connected to the first node, and the second end of the capacitor is electrically connected to the output signal terminal.

11. The shift register according to claim 10, wherein, The control electrode of the eleventh transistor includes a first control electrode and a second control electrode, and both the first control electrode and the second control electrode are electrically connected to the first node.

12. A gate driving circuit, comprising a plurality of cascaded shift registers as described in any one of claims 1 to 11.

13. The gate driving circuit according to claim 12, wherein, The shift register includes a first reset signal terminal; the multiple cascaded shift registers are divided into M driving partitions, where M>1 and is an integer; in the same driving partition, the output signal terminal of the i-th stage shift register is electrically connected to the input signal terminal of the (i + 1)-th stage shift register and the first reset signal terminal of the (i - 1)-th stage shift register, i is an integer, i is greater than or equal to 2 and less than or equal to N - 1, N≥3 and is an integer; The gate driving circuit further includes M first power voltage signal lines and M reset signal lines, one driving partition corresponding to one first power voltage signal line and one reset signal line; the second reset signal terminals of the shift registers in the same driving partition are electrically connected to the reset signal line corresponding to the driving partition, and the first power voltage signal terminals of the shift registers in the same driving partition are electrically connected to the first power voltage signal line corresponding to the driving partition.

14. The gate driving circuit according to claim 12, wherein, The noise removal circuit further includes a second node noise removal circuit; the noise removal control terminal is a fourth power voltage signal terminal; The gate driving circuit further includes M fourth power voltage signal lines; one driving partition corresponds to one fourth power voltage signal line; The fourth power voltage signal terminals of the shift registers in the same driving partition are electrically connected to the fourth power voltage signal line corresponding to the driving partition.

15. The gate driving circuit according to claim 14, wherein, M is equal to 2; the first fourth power voltage signal line and the second first power voltage signal line are the same signal line, and the second fourth power voltage signal line and the first first power voltage signal line are the same signal line; The first power voltage signal terminals of the shift registers in the first driving partition are electrically connected to the first first power voltage signal line, and the fourth power voltage signal terminals of the shift registers in the first driving partition are electrically connected to the second first power voltage signal line; The first power voltage signal terminals of the shift registers in the second driving partition are electrically connected to the second first power voltage signal line, and the fourth power voltage signal terminals of the shift registers in the second driving partition are electrically connected to the first first power voltage signal line.

16. A driving method for a gate driving circuit, applied to the gate driving circuit according to any one of claims 12 to 15, the driving method includes: Controlling the first power voltage signal terminal to input a first power voltage signal, so that the pull-down control sub-circuit writes the first power voltage signal into the second node, and the pull-down noise removal circuit discharges the first node and the output signal terminal through the second power voltage signal terminal; or, controlling the second reset signal terminal to input a second reset signal, so that the reset noise removal circuit discharges the first node and the output signal terminal through the second power voltage signal terminal under the control of the second reset signal.

17. The driving method according to claim 16, wherein, The shift register further includes an input sub-circuit, an output sub-circuit and a reset sub-circuit; the driving method further includes: Controlling the input signal terminal to input an input signal, so that the input sub-circuit writes the input signal into the first node; The control clock signal terminal inputs a clock signal, so that the output sub - circuit outputs the clock signal to the output signal terminal under the control of the potential of the first node; The control first reset signal terminal inputs a first reset signal, so that the reset sub - circuit resets the first node through the second power supply voltage signal provided by the second power supply voltage signal terminal.

18. The driving method according to claim 17, wherein, The multiple cascaded shift registers are divided into M driving partitions. The gate driving circuit further includes M first power supply voltage signal lines and M reset signal lines. One driving partition corresponds to one first power supply voltage signal line and one reset signal line; the second reset signal terminals of the shift registers in the same driving partition are connected to the reset signal line corresponding to the driving partition, and the first power supply voltage signal terminals of the shift registers in the same driving partition are connected to the first power supply voltage signal line corresponding to the driving partition; The driving method includes: when scanning the shift registers in the j - th driving partition, Controlling the first power supply voltage signal line corresponding to the j - th driving partition to input an effective first power supply voltage signal; controlling the reset signal lines corresponding to the remaining driving partitions except the j - th driving partition to input effective second reset signals.

19. The driving method according to claim 18, wherein, It further includes: When scanning the shift registers in the j - th driving partition, Controlling the reset signal line corresponding to the j - th driving partition to input an invalid second reset signal, and controlling the first power supply voltage signal lines corresponding to the remaining driving partitions except the j - th driving partition to input invalid first power supply voltage signals.

20. The driving method according to claim 19, wherein, The noise - removing sub - circuit further includes a second - node noise - removing sub - circuit; the noise - removing control terminal is the fourth power supply voltage signal terminal; the gate driving circuit further includes M fourth power supply voltage signal lines; one driving partition corresponds to one fourth power supply voltage signal line; the fourth power supply voltage signal terminals of the shift registers in the same driving partition are electrically connected to the fourth power supply voltage signal line corresponding to the driving partition; the driving method further includes: When scanning the shift registers in the j - th driving partition, Controlling the fourth power supply voltage signal line corresponding to the j - th driving partition to input an invalid first power supply voltage signal, and controlling the first power supply voltage signal lines corresponding to the remaining driving partitions except the j - th driving partition to input effective fourth power supply voltage signals.

21. An array substrate, comprising: A substrate, which includes a display area and a peripheral area; Multiple cascaded shift registers as claimed in any one of claims 1 to 11, which are arranged in the peripheral area.

22. The array substrate according to claim 21, wherein, No more than two columns of the shift registers are arranged in the peripheral area on the same side of the display area. The area where each column of shift registers is located includes a first sub - area and a second sub - area. The input sub - circuit, the reset sub - circuit and the noise - removing sub - circuit are located in the first sub - area, and the output sub - circuit is located in the second sub - area. The second sub - area is closer to the display area than the first sub - area; The noise reduction circuit includes a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The input sub-circuit includes a ninth transistor, and the reset sub-circuit includes a tenth transistor. The array substrate further includes a first power supply voltage signal line, a second power supply voltage signal line, a clock signal line, and a reset signal line. The second power supply voltage signal line includes a first low-level signal line and a second low-level signal line. In the direction from the first sub-region to the second sub-region, the first power supply voltage signal line, the reset signal line, the first low-level signal line, the clock signal line, and the second low-level signal line are arranged in sequence. The third transistor is disposed on a side of the first power supply voltage signal line away from the second sub-region. The second transistor and the fifth transistor are disposed on a side of the reset signal line close to the second sub-region. The eighth transistor and the seventh transistor are disposed on a side of the first low-level signal line away from the second sub-region. The ninth transistor and the tenth transistor are disposed on a side of the first low-level signal line close to the second sub-region. The first transistor and the sixth transistor are disposed on a side of the second low-level signal line close to the second sub-region.

23. The array substrate according to claim 22, wherein, The output sub-circuit includes an eleventh transistor and a capacitor. In the column direction of one column of the shift register, the eleventh transistor and the capacitor are alternately arranged in sequence.

24. The array substrate according to claim 23, wherein, The channel width-to-length ratio of the eleventh transistor is greater than or equal to 120:5 and less than or equal to 300:

5.

25. The array substrate according to claim 24, wherein, The channel of the eleventh transistor includes a plurality of serially connected sub-channels, and the channel width-to-length ratio of each sub-channel is 20:

5.

26. A display device, comprising the array substrate according to any one of claims 21 to 25.

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