Shift register unit and control method therefor, and gate drive circuit

Abstract

The present disclosure provides a shift register unit and a control method therefor, and a gate drive circuit. The shift register unit comprises an input circuit, a control circuit, K output circuits, K' isolation circuits and a pull-down circuit. A first end of the k-th output circuit is connected to a k-th clock signal end, and a second end thereof is connected to a k-th output signal end, wherein K is an integer greater than 1, and k = 1, 2, ..., K. The K' isolation circuits are respectively connected between control ends of K' output circuits among the K output circuits and a pull-up node, wherein K' is a positive integer, and K'≤K. A first end of each isolation circuit is connected to the pull-up node, a second end of the isolation circuit is connected to the control end of a corresponding output circuit, a control end of the isolation circuit is connected to a control signal end, and the isolation circuit is configured to connect or disconnect the first end to or from the second end of the isolation circuit under the control of the voltage between the control end of the isolation circuit and the second end of the isolation circuit.

Description

Shift register unit, control method thereof, and gate drive circuit

[0001] This application claims priority to Chinese patent application No. 202410017378.6, filed on January 4, 2024, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a shift register unit, a gate drive circuit, and a control method for the shift register unit. Background Art

[0003] In display technology, multiple cascaded shift register units are used to generate sequentially shifted output signals to drive pixels for display. This cascaded circuit structure is also known as a gate-on-array (GOA) circuit. With technological advancements, the demand for display quality is becoming increasingly demanding. The current GOA circuit structure struggles to meet these demands. Summary of the Invention

[0004] According to one aspect of an embodiment of the present disclosure, there is provided a shift register unit, comprising:

[0005] an input circuit connected to the input signal terminal and the pull-up node of the shift register, and configured to input the signal at the input signal terminal to the pull-up node;

[0006] a control circuit connected to the pull-up node and the pull-down node, the power signal terminal, and the reference signal terminal of the shift register unit, the control circuit being configured to provide a signal from one of the power signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node;

[0007] K output circuits, connected to K clock signal terminals, K output signal terminals, and a pull-up node of the shift register unit, wherein a first terminal of a k-th output circuit is connected to the k-th clock signal terminal of the shift register unit, and a second terminal of the k-th signal output circuit is connected to the k-th output signal terminal of the shift register unit, and each output circuit is configured to provide a signal at the first terminal of the output circuit to the second terminal of the output circuit under the control of a control terminal of the output circuit, wherein K is an integer greater than 1, and k=1, 2, ..., K;

[0008] K' isolation circuits, respectively connected between the control terminals of K' output circuits among the K output circuits and the pull-up node, wherein a first terminal of each isolation circuit is connected to the pull-up node, a second terminal of the isolation circuit is connected to the control terminal of the corresponding output circuit, the control terminal of the isolation circuit is connected to the control signal terminal, and the isolation circuit is configured to connect or disconnect the first terminal and the second terminal of the isolation circuit under control of a voltage between the control terminal of the isolation circuit and the second terminal of the isolation circuit, wherein K' is a positive integer, and K'≤K;

[0009] The pull-down circuit is connected to the pull-down node, the pull-up node, K output signal terminals and the reference signal terminal. The pull-down sub-circuit is used to provide the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

[0010] In some embodiments, the K output circuits include a cascade output circuit and K' signal output circuits, the output signal terminals connected to the cascade output circuits are used to connect to other shift register units, and the output signal terminals connected to the signal output circuits are used to provide output signals;

[0011] The K′ isolation circuits are respectively connected between the control terminals and the pull-up nodes of the K′ signal output circuits.

[0012] In some embodiments, the K output circuits include a cascade output circuit and K' signal output circuits, one of the K' isolation circuits is connected between the control end of the cascade output circuit and a pull-up node, and the remaining K'-1 isolation circuits are respectively connected between the control end of the K'-1 signal output circuits and the pull-up node.

[0013] In some embodiments, the isolation circuit includes a first transistor, the gate of the first transistor is connected to the control signal terminal, the first electrode of the first transistor serves as the first terminal of the isolation circuit, and the second electrode of the first transistor serves as the second terminal of the isolation circuit.

[0014] In some embodiments, the control signal terminal includes a first control signal terminal and a second control signal terminal, wherein the first control signal terminal is at a first level and the second control signal terminal is at a second level; the isolation circuit also includes a second transistor, wherein the gate of the first transistor is connected to the first control signal terminal, the gate of the second transistor is connected to the second control signal terminal, the first electrode of the first transistor is connected to the first electrode of the second transistor, and the second electrode of the first transistor is connected to the second electrode of the second transistor.

[0015] In some embodiments, K=5, K′=3, 4, or 5.

[0016] In some embodiments, the output circuit includes:

[0017] a third transistor, wherein the gate of the third transistor serves as a control terminal of the output circuit, the first electrode of the third transistor serves as a first terminal of the output circuit, and the second electrode of the third transistor serves as a second terminal of the output circuit;

[0018] A first capacitor, wherein a first electrode of the first capacitor is connected to the gate of the third transistor, and a second electrode of the first capacitor is connected to the second electrode of the third transistor.

[0019] In some embodiments, the input circuit includes a fourth transistor, wherein the gate of the fourth transistor is connected to the input signal terminal, the first electrode of the fourth transistor is connected to the power signal terminal, and the second electrode of the fourth transistor is connected to the pull-up node; or

[0020] The input circuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the input signal terminal, the first electrode of the fourth transistor is connected to the power signal terminal, the second electrode of the fourth transistor is connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the input signal terminal, the first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is connected to the pull-up node.

[0021] In some embodiments, the shift register unit further includes: a reset circuit connected to the reset signal terminal, the pull-up node and the reference signal terminal of the shift register unit, the reset circuit being used to provide the signal of the reference signal terminal to the pull-up node under the control of the reset signal terminal.

[0022] In some embodiments, the reset circuit includes a sixth transistor, a gate of the sixth transistor is connected to the reset signal terminal, a first electrode of the sixth transistor is connected to the reference signal terminal, and a second electrode of the sixth transistor is connected to the pull-up node; or

[0023] The reset circuit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor is connected to the reset signal terminal, the first electrode of the sixth transistor is connected to the reference signal terminal, the second electrode of the sixth transistor is connected to the pull-up node through the seventh transistor, the gate of the seventh transistor is connected to the reset signal terminal, the first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is connected to the pull-up node.

[0024] In some embodiments, the input signal terminal includes a first input signal terminal and a first input signal terminal, the control signal terminal includes a first control signal terminal and a second control signal terminal, and the input circuit includes:

[0025] a first input circuit connected to the first input signal terminal, the pull-up node and the first control signal terminal, the first input circuit being configured to provide a signal from the first control signal terminal to the pull-up node under the control of the first input signal terminal;

[0026] a second input circuit connected to the second input signal terminal, the pull-up node, and the second control signal terminal, the second input circuit being configured to provide a signal from the second control signal terminal to the pull-up node under the control of the second input signal terminal;

[0027] In the forward scanning mode, the first control signal terminal is at the first level and the second control signal terminal is at the second level; in the reverse scanning mode, the first control signal terminal is at the second level and the second control signal terminal is at the first level.

[0028] In some embodiments, the first input circuit includes:

[0029] A fourth transistor, wherein a gate of the fourth transistor is connected to the first input signal terminal, a first electrode of the fourth transistor is connected to the first control signal terminal, and a second electrode of the fourth transistor is connected to the pull-up node.

[0030] In some embodiments, the first input circuit further comprises:

[0031] A fifth transistor, wherein the second electrode of the fourth transistor is connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the first input signal terminal, the first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is connected to the pull-up node.

[0032] In some embodiments, the second input circuit includes:

[0033] A sixth transistor, wherein a gate of the sixth transistor is connected to the second input signal terminal, a first electrode of the sixth transistor is connected to the second control signal terminal, and a second electrode of the sixth transistor is connected to the pull-up node.

[0034] In some embodiments, the second input circuit further comprises:

[0035] A seventh transistor, wherein the gate of the seventh transistor is connected to the second control signal terminal, the first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is connected to the pull-up node.

[0036] In some embodiments, the first input circuit includes a fourth transistor, the second input circuit includes a sixth transistor, and parameters of the fourth transistor are the same as parameters of the sixth transistor.

[0037] In some embodiments, the first input circuit further includes a fifth transistor, the second input circuit further includes a seventh transistor, and parameters of the fifth transistor are the same as parameters of the seventh transistor.

[0038] In some embodiments, the shift register unit further includes:

[0039] a first voltage stabilizing circuit connected to the pull-down node, the second input signal terminal, and the first control signal terminal, the first voltage stabilizing circuit being configured to provide a signal from the first control signal terminal to the pull-down node under the control of the second input signal terminal;

[0040] The second voltage stabilizing circuit is connected to the pull-down node, the first input signal terminal and the second control signal terminal. The second voltage stabilizing circuit is used to provide the signal of the second control signal terminal to the pull-down node under the control of the first input signal terminal.

[0041] In some embodiments, the first voltage stabilizing circuit includes an eighth transistor, the gate of the eighth transistor is connected to the second input signal terminal, the first electrode of the eighth transistor is connected to the first control signal terminal, and the second electrode of the eighth transistor is connected to the pull-down node; the second voltage stabilizing circuit includes a ninth transistor, the gate of the ninth transistor is connected to the first input signal terminal, the first electrode of the ninth transistor is connected to the second control signal terminal, and the second electrode of the ninth transistor is connected to the pull-down node.

[0042] In some embodiments, parameters of the eighth transistor and the ninth transistor are the same.

[0043] In some embodiments, the shift register unit further includes a first voltage stabilizing circuit, a second voltage stabilizing circuit, and an intermediate voltage stabilizing circuit, wherein the first voltage stabilizing circuit, the second voltage stabilizing circuit, and the intermediate voltage stabilizing circuit are connected to an intermediate node, wherein:

[0044] The first voltage stabilizing circuit is connected to the intermediate node, the first input signal terminal and the first control signal terminal, and the first voltage stabilizing circuit is used to provide the signal of the first control signal terminal to the intermediate node under the control of the first input signal terminal;

[0045] The second voltage stabilizing circuit is connected to the intermediate node, the second input signal terminal and the second control signal terminal, and is used for providing the signal of the second control signal terminal to the intermediate node under the control of the second input signal terminal;

[0046] The intermediate voltage stabilization circuit is connected to the pull-down node, the intermediate node and the reference signal terminal. The intermediate voltage stabilization circuit is configured to provide the signal of the reference signal terminal to the intermediate node under the control of the pull-down node, and to provide the signal of the reference signal terminal to the pull-down node under the control of the intermediate node.

[0047] In some embodiments, the first voltage stabilization circuit includes an eighth transistor, the second voltage stabilization circuit includes a ninth transistor, and the intermediate voltage stabilization circuit includes a tenth transistor and an eleventh transistor;

[0048] Among them, the gate of the eighth transistor is connected to the first input signal terminal, the first electrode of the eighth transistor is connected to the first control signal terminal, the second electrode of the eighth transistor is connected to the intermediate node, the gate of the ninth transistor is connected to the second input signal terminal, the first electrode of the ninth transistor is connected to the second control signal terminal, the second electrode of the ninth transistor is connected to the intermediate node, the gate of the tenth transistor is connected to the intermediate node, the first electrode of the tenth transistor is connected to the reference signal terminal, the second electrode of the tenth transistor is connected to the pull-down node, the gate of the eleventh transistor is connected to the pull-down node, the first electrode of the eleventh transistor is connected to the reference signal terminal, and the second electrode of the eleventh transistor is connected to the intermediate node.

[0049] In some embodiments, the control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, wherein:

[0050] The gate and the first electrode of the twelfth transistor are connected to the power signal terminal, and the second electrode of the twelfth transistor is connected to the gate of the thirteenth transistor;

[0051] A first electrode of the thirteenth transistor is connected to the power signal terminal, and a second electrode of the thirteenth transistor is connected to the pull-down node;

[0052] The gate of the fourteenth transistor is connected to the pull-up node, the first electrode of the fourteenth transistor is connected to the gate of the thirteenth transistor, and the second electrode of the fourteenth transistor is connected to the reference signal terminal;

[0053] A gate of the fifteenth transistor is connected to the pull-up node, a first electrode of the fifteenth transistor is connected to the pull-down node, and a second electrode of the fifteenth transistor is connected to the reference signal terminal.

[0054] In some embodiments, the control circuit further comprises:

[0055] A sixteenth transistor, the second electrode of the twelfth transistor is connected to the gate of the thirteenth transistor through the sixteenth transistor, wherein the gate of the sixteenth transistor is connected to the power signal terminal, the first electrode of the sixteenth transistor is connected to the second electrode of the twelfth transistor, and the second electrode of the sixteenth transistor is connected to the gate of the thirteenth transistor.

[0056] In some embodiments, the pull-down circuit includes:

[0057] a first pull-down circuit connected to the pull-down node, the pull-up node, and the reference signal terminal, the first pull-down sub-circuit being configured to provide a signal at the reference signal terminal to the pull-up node under the control of the pull-down node;

[0058] K second pull-down circuits are respectively connected to K output signal terminals, wherein each second pull-down circuit is connected to a pull-down node, a reference signal terminal and a corresponding output signal terminal, and is configured to provide a signal from the reference signal terminal to the corresponding output signal terminal under the control of the pull-down node.

[0059] In some embodiments, the first pull-down circuit includes a seventeenth transistor, a gate of the seventeenth transistor is connected to the pull-down node, a first electrode of the seventeenth transistor is connected to the reference signal terminal, and a second electrode of the seventeenth transistor is connected to the pull-up node; or

[0060] The first pull-down circuit includes a seventeenth transistor and an eighteenth transistor, the gate of the seventeenth transistor is connected to the pull-down node, the first electrode of the seventeenth transistor is connected to the reference signal terminal through the eighteenth transistor, and the second electrode of the seventeenth transistor is connected to the pull-up node, wherein the gate of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the reference signal terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the seventeenth transistor.

[0061] In some embodiments, the second pull-down circuit includes a nineteenth transistor, the gate of the nineteenth transistor is connected to the pull-down node, the first electrode of the nineteenth transistor is connected to the reference signal terminal, and the second electrode of the nineteenth transistor is connected to the corresponding output signal terminal.

[0062] In some embodiments, the shift register unit further includes:

[0063] The total reset circuit is connected to the total reset signal terminal, the pull-up node and the reference signal terminal of the shift register unit. The total reset circuit is configured to provide the signal of the reference signal terminal to the pull-up node under the control of the total reset signal terminal.

[0064] In some embodiments, the total reset circuit includes a twentieth transistor, a gate of the twentieth transistor is connected to the total reset signal terminal, a first electrode of the twentieth transistor is connected to the reference signal terminal, and a second electrode of the twentieth transistor is connected to the pull-up node; or

[0065] The total reset circuit includes a twentieth transistor and a twenty-first transistor, the gate of the twentieth transistor is connected to the total reset signal terminal, the first electrode of the twentieth transistor is connected to the reference signal terminal through the twenty-first transistor, the second electrode of the twentieth transistor is connected to the pull-up node, the gate of the twenty-first transistor is connected to the total reset signal terminal, the first electrode of the twenty-first transistor is connected to the reference signal terminal, and the second electrode of the twenty-first transistor is connected to the first electrode of the twentieth transistor.

[0066] In some embodiments, the shift register unit further includes: a sensing circuit connected to a sensing selection signal terminal, a sensing trigger signal terminal, a sensing control node, an input signal terminal and a pull-up node of the shift register unit, the sensing circuit being configured to write the signal of the input signal terminal to the sensing control node under the control of the sensing selection signal terminal during the display phase, and to provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal during the blanking phase.

[0067] In some embodiments, the sensing circuit includes:

[0068] a selection subcircuit connected to the sensing selection signal terminal, the sensing control node and the input signal terminal, the selection subcircuit being configured to write the signal of the input signal terminal into the sensing control node under the control of the sensing selection signal terminal during a display phase;

[0069] The trigger subcircuit is connected to the sensing trigger signal terminal, the sensing control node and the pull-up node. The trigger subcircuit is used to provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal in the blanking phase.

[0070] In some embodiments, the selection sub-circuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a second capacitor, wherein:

[0071] The gate of the twenty-second transistor is connected to the sensing selection signal terminal, the first electrode of the twenty-second transistor is connected to the input signal terminal, the second electrode of the twenty-second transistor is connected to the first electrode of the twenty-third transistor, the first electrode of the twenty-third transistor is connected to the sensing selection signal terminal, the second electrode of the twenty-third transistor is connected to the sensing control node, the gate of the twenty-fourth transistor is connected to the sensing control node, the first electrode of the twenty-fourth transistor is connected to the second electrode of the twenty-second transistor, the second electrode of the twenty-fourth transistor is connected to the power supply signal terminal, the first electrode of the second capacitor is connected to the power supply signal terminal, and the second electrode of the second capacitor is connected to the gate of the twenty-fourth transistor.

[0072] In some embodiments, the trigger sub-circuit includes a twenty-fifth transistor and a twenty-sixth transistor, the gate of the twenty-fifth transistor is connected to the sensing control node, the first electrode of the twenty-fifth transistor is connected to the power signal terminal, the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor, the gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal, and the second electrode of the twenty-sixth transistor is connected to the pull-up node; or

[0073] The trigger sub-circuit includes a twenty-fifth transistor, a twenty-sixth transistor and a twenty-seventh transistor, the gate of the twenty-fifth transistor is connected to the sensing control node, the first electrode of the twenty-fifth transistor is connected to the power supply signal terminal, the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor, the gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal, the second electrode of the twenty-sixth transistor is connected to the pull-up node through the twenty-seventh transistor, the gate of the twenty-seventh transistor is connected to the sensing trigger signal terminal, the first electrode of the twenty-seventh transistor is connected to the second electrode of the twenty-sixth transistor, and the second electrode of the twenty-seventh transistor is connected to the pull-up node.

[0074] In some embodiments, the sensing circuit further includes: a voltage stabilizing subcircuit connected to the sensing control node, the sensing trigger signal terminal and the reference signal terminal, for providing the signal of the reference signal terminal to the pull-down node under the control of the sensing control node and the sensing trigger signal terminal.

[0075] In some embodiments, the voltage stabilization subcircuit includes a twenty-eighth transistor and a twenty-ninth transistor, the gate of the twenty-eighth transistor is connected to the sensing trigger signal terminal, the first electrode of the twenty-eighth transistor is connected to the pull-up node, the second electrode of the twenty-eighth transistor is connected to the first electrode of the twenty-ninth transistor, the gate of the twenty-ninth transistor is connected to the sensing control node, and the second electrode of the twenty-ninth transistor is connected to the reference signal terminal.

[0076] In some embodiments, the shift register unit further includes: a third voltage stabilizing circuit connected to the voltage stabilizing node, the power signal terminal, and the pull-up node of the shift register unit, the third voltage stabilizing circuit being configured to provide a signal at the power signal terminal to the voltage stabilizing node under control of the pull-up node;

[0077] The input circuit of the shift register unit is connected to the voltage stabilization node.

[0078] In some embodiments, the third voltage stabilizing circuit includes a 30th transistor and a 31st transistor, the gate of the 30th transistor is connected to the pull-up node, the first electrode of the 30th transistor is connected to the power signal terminal, the second electrode of the 30th transistor is connected to the first electrode of the 31st transistor, the gate of the 31st transistor is connected to the pull-up node, and the second electrode of the 31st transistor is connected to the voltage stabilizing node.

[0079] In some embodiments, the input circuit includes a fourth transistor and a fifth transistor and the reset circuit includes a sixth transistor and a seventh transistor, or the input circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0080] The second electrode of the fourth transistor, the first electrode of the fifth transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are connected to the voltage stabilization node.

[0081] In some embodiments, the shift register unit further includes at least one of a pull-down circuit, a general reset circuit, and a sensing circuit, and at least one of the pull-down circuit, the general reset circuit, and the sensing circuit is connected to the regulated voltage node.

[0082] In some embodiments, the shift register unit further includes: a fourth voltage stabilizing circuit, the fourth voltage stabilizing circuit being connected to the pull-down node, the input signal terminal and the reference signal terminal, and being configured to provide the signal of the reference signal terminal to the pull-down node under the control of the input signal terminal.

[0083] In some embodiments, the fourth voltage stabilization circuit includes: a thirty-second transistor, the gate of the thirty-second transistor is connected to the input signal terminal, the first electrode of the thirty-second transistor is connected to the reference signal terminal, and the second electrode of the thirty-second transistor is connected to the pull-down node.

[0084] According to another aspect of the present disclosure, a shift register unit is provided, including:

[0085] a first input circuit connected to the first input signal terminal of the shift register unit, the pull-up node, and the first control signal terminal, the first input circuit being configured to provide a signal from the first control signal terminal to the pull-up node under the control of the first input signal terminal;

[0086] a second input circuit connected to the second input signal terminal of the shift register unit, the pull-up node, and the second control signal terminal, the second input circuit being configured to provide a signal from the second control signal terminal to the pull-up node under the control of the second input signal terminal;

[0087] a control circuit connected to the pull-up node and the pull-down node, the power signal terminal, and the reference signal terminal of the shift register unit, the control circuit being configured to provide a signal from one of the power signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node;

[0088] K output circuits, connected to K clock signal terminals, K output signal terminals, and a pull-up node of the shift register unit, wherein a control terminal of a kth output circuit is connected to the pull-up node, a first terminal of the kth output circuit is connected to the kth clock signal terminal of the shift register unit, and a second terminal of the kth output circuit is connected to the kth output signal terminal of the shift register unit, each output circuit being configured to provide a signal at the first terminal of the output circuit to the second terminal of the output circuit under control of the control terminal of the output circuit, wherein K is an integer greater than 1, and k=1, 2, ..., K;

[0089] a pull-down circuit connected to the pull-down node, the pull-up node, the K output signal terminals, and the reference signal terminal, the pull-down circuit being configured to provide a signal from the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node;

[0090] in,

[0091] In the forward scanning mode, the first control signal terminal is at a first level, and the second control signal terminal is at a second level;

[0092] In the reverse scanning mode, the first control signal terminal is at the second level, and the second control signal terminal is at the first level.

[0093] According to another aspect of an embodiment of the present disclosure, a gate driving circuit is further provided, comprising a plurality of shift register units as described above, wherein the plurality of shift register units are connected in cascade.

[0094] According to another aspect of the present disclosure, a method for controlling a shift register unit is provided, including:

[0095] During the input period, the input circuit inputs the signal of the input signal terminal to the pull-up node, and the control circuit provides the signal of the reference signal terminal to the pull-down node under the control of the pull-up node;

[0096] During an output period, each of the K output circuits provides a signal at a first terminal of the output circuit to a second terminal of the output circuit under control of a control terminal of the output circuit, thereby generating an output signal at the K output signal terminals based on the signals at the K clock signal terminals;

[0097] During a reset period, the control circuit provides a signal from the power signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides a signal from the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

[0098] in,

[0099] Before the output circuit connected to the k'th isolation circuit generates an output signal, the signal at the control signal terminal connects the first control terminal and the second control terminal of the k'th isolation circuit;

[0100] In response to the output circuit connected to the k'th isolation circuit generating an output signal, the potential of the control terminal of the k'th isolation circuit disconnects the first terminal and the second terminal of the k'th isolation circuit, where k'=1, 2, . . . , K'.

[0101] According to another aspect of the present disclosure, a method for controlling a shift register unit is provided, including:

[0102] In the forward scan mode, the first control signal terminal is at a first level, and the second control signal terminal is at a second level, wherein in an input period, the first input circuit provides a signal at the first control signal terminal to a pull-up node under the control of the first input signal terminal; in an output period, each of the K output circuits provides a signal at the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit; in a reset period, the second input circuit provides a signal at the second control signal terminal to the pull-up node under the control of the second input signal terminal, the control circuit provides a signal at the reference signal terminal to the pull-down node under the control of the pull-down node, and the pull-down circuit provides a signal at the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node;

[0103] In the reverse scan mode, the first control signal terminal is at the second level, and the second control signal terminal is at the first level, wherein in the input period, the second input circuit provides the signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal; in the output period, each of the K output circuits provides the signal of the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit; in the reset period, the first input circuit provides the signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal, the control circuit provides the signal of the reference signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] FIG. 1A shows a signal timing diagram of a shift register unit.

[0105] FIG. 1B shows a circuit diagram of a pixel circuit.

[0106] FIG2 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0107] FIG3 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0108] FIG. 4A shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0109] FIG. 4B shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0110] FIG. 4C shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0111] FIG4D shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0112] FIG4E shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0113] FIG. 4F shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0114] FIG5 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure.

[0115] FIG6 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure.

[0116] FIG7 shows a timing diagram of a first control signal and a second control signal according to an embodiment of the present disclosure.

[0117] 8A to 8C show display effects of a spliced ​​screen.

[0118] FIG9 shows a schematic block diagram of a shift register unit according to another embodiment of the present disclosure.

[0119] FIG10 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0120] FIG. 11A shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0121] FIG. 11B shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0122] FIG12 shows a signal timing diagram of a shift register unit in a forward scanning mode according to an embodiment of the present disclosure.

[0123] FIG. 13 shows a signal timing diagram of a shift register unit in a reverse scan mode according to an embodiment of the present disclosure.

[0124] FIG. 14 shows a signal timing diagram of the shift register unit in the display phase and the blanking phase according to an embodiment of the present disclosure.

[0125] FIG. 15 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0126] FIG. 16 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0127] FIG17 shows a schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0128] While the present disclosure will be fully described with reference to the accompanying drawings that contain preferred embodiments of the present disclosure, it should be understood before this description that one of ordinary skill in the art may modify the disclosure described herein while still achieving the technical benefits of the present disclosure. Therefore, it should be understood that the above description is intended to be a broad disclosure for one of ordinary skill in the art and is not intended to limit the exemplary embodiments described herein.

[0129] In addition, in the following detailed description, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments can be practiced without these specific details. In other cases, well-known structures and devices are shown in diagrammatic form to simplify the accompanying drawings.

[0130] In a shift register unit, multiple output circuits can share a pull-up node to simplify the circuit structure. However, because multiple output circuits share the pull-up node, the potential of the pull-up node is repeatedly boosted during the shift register unit's multi-channel output generation process. This causes the voltages at the control terminals of the various output circuits to differ when generating output signals, thereby affecting the display effect.

[0131] Figure 1A shows a signal timing diagram of a shift register unit. Figure 1B shows a circuit diagram of a pixel circuit.

[0132] As shown in Figure 1A, the multiple output circuits of the shift register unit share a pull-up node PU. Each output circuit generates an output signal under the control of the pull-up node PU, allowing the shift register unit to generate multiple output signals OUT1, OUT2, OUT3, and OUT4. Because each output circuit shares the pull-up node PU, the multiple output signals OUT1, OUT2, OUT3, and OUT4 cause the pull-up node PU to be repeatedly bootstrapped by the capacitors in the output circuits at different times, resulting in different voltages at the pull-up node when different pulses are output. As shown in Figure 1, the pulse of output signal OUT1 raises the potential of the pull-up node PU to VU1. The arrival of the pulse of output signal OUT2 further raises the potential of the pull-up node PU from VU1 to VU2. The arrival of the pulse of output signal OUT3 further raises the potential of the pull-up node from VU2 to VU3. Next, each output signal changes from a high level to a low level in sequence, causing the voltage of the pull-up node PU to drop stepwise, resulting in the PU point signal waveform shown in Figure 1.

[0133] Since the pull-up node PU is directly connected to the gate of the output transistor in each output circuit, the step-by-step change of the voltage of the pull-up node PU causes the output capabilities of the output transistors in different output circuits to be different. Then the rising speed and falling speed of the output signal voltage will be different, that is, the rising delay time and the falling delay time are different, which means that the gate line turn-on waveform for writing grayscale data to the pixel is different.

[0134] Taking the pixel circuit shown in FIG1B as an example, the output signal generated by the shift register unit of FIG1A can be used as the gate drive signal G1 and G2 of the pixel circuit. As shown in FIG1B , the pixel circuit includes transistors T1, T2, T3 and a capacitor Cst. Under the control of the gate drive signal G2, the transistor T3 writes the reference voltage into the source S of the transistor T1. The transistor T2 is turned on under the control of the gate drive signal G1, thereby writing the data signal into the gate G of the transistor T1. The transistor T1 generates a driving current based on the voltage of the gate G, thereby driving the light-emitting element EL to emit light. FIG1B also shows the parasitic capacitances Cgs_1, Cgs_2, Cgs_3 (hereinafter collectively referred to as Cgs) and Cgd_1, Coled between each node. The coupling effect between the capacitor Cgs and the capacitor Cgs is different, and the voltage loss of the grayscale writing is different, which will result in brightness differences between pixel rows, that is, different bright and dark horizontal stripes. Taking the gate drive signal G1 as an example, due to the influence of the parasitic capacitance Cgs of transistor T2, when the gate drive signal G1 changes from high to low (transistor T2 is turned off), the voltage of the gate G of transistor T1 will be coupled and pulled down. In other words, the voltage written to transistor T1 will be reduced through capacitive coupling. The magnitude of the reduction is directly related to the amount of change in the voltage of the gate drive signal G1 and the speed of change. The difference in the high and low voltage difference and the fall delay time of the gate drive signal output by the shift register unit, and the difference in the grayscale loss, will ultimately affect the difference in the gate-source voltage Vgs of transistor T1 during the light-emitting stage and the difference in the drive current generated, resulting in the appearance of horizontal bright and dark stripes.

[0135] Therefore, the consistency of the output signals of the shift register unit in aspects such as rise and fall time, high level and low level amplitude, etc. is becoming increasingly important to minimize the differences in gate drive signals of pixel units in each row, thereby improving display uniformity.

[0136] The embodiments of the present disclosure provide a shift register unit that provides an isolation circuit between an output circuit and a pull-up node, thereby reducing differences between output signals caused by multiple bootstrapping of the pull-up node, thereby improving display uniformity.

[0137] FIG2 shows a schematic block diagram of a shift register unit according to an embodiment of the present disclosure.

[0138] As shown in FIG2 , the shift register unit 100 includes an input circuit 110, a control circuit 120, K output circuits, K' isolation circuits, and a pull-down circuit 150. K is an integer greater than 1, k = 1, 2, ..., K. K' is a positive integer, and K' ≤ K. FIG2 shows two output circuits 130_1 and 130_2 and two isolation circuits 140_1 and 140_2, i.e., K = K' = 2. However, this is merely an example, and the embodiments of the present disclosure are not limited thereto. K and K' can be set as needed, as long as K is an integer greater than 1, K' is a positive integer, and K' ≤ K.

[0139] The input circuit 110 is connected to the input signal terminal IN of the shift register and the pull-up node PU, and is configured to input the signal of the input signal terminal IN to the pull-up node PU.

[0140] The control circuit 120 is connected to the pull-up node PU and the pull-down node PD of the shift register unit, the power signal terminal GVDD and the reference signal terminal VGL. The control circuit 120 is used to provide a signal from one of the power signal terminal GVDD and the reference signal terminal VGL to the pull-down node PD under the control of the pull-up node PU.

[0141] K output circuits 130_1 and 130_2 are connected to the K clock signal terminals CLK1 and CLK2, K output signal terminals OUT1 and OUT2, and a pull-up node PU of the shift register unit. The first terminal of the k-th output circuit is connected to the k-th clock signal terminal of the shift register unit, and the second terminal of the k-th signal output circuit is connected to the k-th output signal terminal of the shift register unit. For example, as shown in Figure 2, the first terminal of output circuit 130_1 (first output circuit) is connected to the clock signal terminal CLK1 (first clock signal terminal), and the second terminal of output circuit 130_1 is connected to the output signal terminal OUT1 (first output signal terminal); the first terminal of output circuit 130_2 (second output circuit) is connected to the clock signal terminal CLK2 (second clock signal terminal), and the second terminal of output circuit 130_2 is connected to the output signal terminal OUT2 (second output signal terminal). The control terminal of output circuit 130_1 can be connected to isolation circuit 140_1 (first isolation circuit), and the control terminal of output circuit 130_2 can be connected to isolation circuit 140_2 (second isolation circuit). Each output circuit can provide a signal at a first terminal of the output circuit to a second terminal of the output circuit under the control of a control terminal of the output circuit.

[0142] K' isolation circuits are respectively connected between the control terminals of K' output circuits among the K output circuits and the pull-up node PU. For example, in Figure 2, K=K', and an isolation circuit is provided between each output circuit and the pull-up node. As shown in Figure 2, isolation circuit 140_1 is connected between output circuit 130_1 and the pull-up node PU, and isolation circuit 140_2 is connected between output circuit 130_2 and the pull-up node PU. The first terminal of each isolation circuit is connected to the pull-up node PU, and the second terminal of the isolation circuit is connected to the control terminal of the corresponding output circuit, and the control terminal of the isolation circuit 140 is connected to the control signal terminal. For example, as shown in Figure 2, the first terminals of isolation circuits 140_1 and 140_2 are both connected to the pull-up node PU, the second terminal of isolation circuit 140_1 is connected to the control terminal PU1 of output circuit 130_1, and the second terminal of isolation circuit 140_2 is connected to the control terminal PU2 of output circuit 130_2. The control terminals of isolation circuits 140_1 and 140_2 are both connected to the control signal terminal CN. Each isolation circuit can connect or disconnect its first terminal and second terminal under control of the voltage between the control terminal and the second terminal of the isolation circuit. Taking isolation circuit 140_1 as an example, when the voltage between the control terminal and the second terminal of isolation circuit 140_1 (i.e., the voltage between the control signal terminal CN and the control terminal PU1 of output circuit 130_1) is within a preset range, isolation circuit 140_1 electrically connects pull-up node PU to control terminal PU1 of output circuit 130_1. When the voltage exceeds the preset range, isolation circuit 140_1 disconnects pull-up node PU from control terminal PU1 of output circuit 130_1.

[0143] The pull-down circuit 150 is connected to the pull-down node PD, the pull-up node PU, K output signal terminals OUT and the reference signal terminal VGL. The pull-down sub-circuit is used to provide the signal of the reference signal terminal VGL to the pull-up node PU and the K output signal terminals OUT1 and OUT2 under the control of the pull-down node PD.

[0144] In an embodiment of the present disclosure, an isolation circuit is provided between the output circuit and the pull-up node. The isolation circuit can control the connection or disconnection of the control terminal of the output circuit and the pull-up node by adjusting the voltage between the control terminal of the output circuit and the pull-up node. In this way, the voltage bootstrapping of one output circuit when outputting a signal will not affect the signal output of other output circuits. For example, when the output signal generated by the output circuit 130_1 at the output terminal OUT1 causes the potential of the control terminal PU1 to be raised, the raised potential of the control terminal PU1 can cause the isolation circuit 140_1 to disconnect the output circuit 130_1 from the pull-up node PU, thereby ensuring that the voltage bootstrapping of the output circuit 130_1 does not affect the potential of the pull-up node PU, and thus does not affect the subsequent signal output of the output circuit 130_2. In addition, the raised potential of the control terminal PU1 is also beneficial to the stability of the output signal of the output circuit 130_1. In this way, the differences between the output signals caused by multiple bootstrapping of the pull-up node are reduced, which is conducive to improving display uniformity.

[0145] FIG3 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0146] As shown in FIG3 , the shift register unit 300 includes an input circuit 310, a control circuit 320, K output circuits (five output circuits 330_CR, 330_1, 330_2, 330_3, and 330_4 are shown in FIG3 ), K′ isolation circuits (five isolation circuits 340_CR, 340_1, 340_2, 340_3, and 340_4 are shown in FIG3 ), and a pull-down circuit 150. The descriptions of the input circuit, control circuit, output circuit, isolation circuit, and pull-down circuit in the above embodiments are also applicable to this embodiment.

[0147] The input circuit 310 may include a fourth transistor M4, wherein a gate of the fourth transistor M1 is connected to the input signal terminal IN, a first electrode of the fourth transistor M4 is connected to the power signal terminal GVDD1, and a second electrode of the fourth transistor is connected to the pull-up node PU. In some embodiments, the gate and first electrode of the fourth transistor M1 may both be connected to the input signal terminal IN.

[0148] The control circuit includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The gate and first electrode of the twelfth transistor M12 are connected to the power signal terminal, and the second electrode of the twelfth transistor M12 is connected to the gate of the thirteenth transistor M13. The first electrode of the thirteenth transistor M13 is connected to the power signal terminal, and the second electrode of the thirteenth transistor M13 is connected to the pull-down node PD. The gate of the fourteenth transistor M14 is connected to the pull-up node PU, the first electrode of the fourteenth transistor M14 is connected to the gate of the thirteenth transistor M13, and the second electrode of the fourteenth transistor M14 is connected to the reference signal terminal. The gate of the fifteenth transistor M15 is connected to the pull-up node PU, the first electrode of the fifteenth transistor M15 is connected to the pull-down node PD, and the second electrode of the fifteenth transistor M15 is connected to the reference signal terminal VGL2.

[0149] Each output circuit 330_CR, 330_1, 330_2, 330_3, and 330_4 may include a third transistor and a first capacitor. For example, output circuit 330_CR includes a third transistor M3_CR and a first capacitor C1_CR, output circuit 330_1 includes a third transistor M3_1 and a first capacitor C1_1, output circuit 330_2 includes a third transistor M3_2 and a first capacitor C1_2, output circuit 330_3 includes a third transistor M3_3 and a first capacitor C1_3, and output circuit 330_4 includes a third transistor M3_4 and a first capacitor C1_4.

[0150] In each output circuit, the gate of the third transistor serves as the control terminal of the output circuit, the first electrode of the third transistor serves as the first terminal of the output circuit, and the second electrode of the third transistor serves as the second terminal of the output circuit. The first electrode of the first capacitor is connected to the gate of the third transistor, and the second electrode of the first capacitor is connected to the second electrode of the third transistor. Taking output circuit 330_1 as an example, the gate of the third transistor M3_1 serves as the control terminal of the third transistor M3_1, the first electrode of the third transistor M3_1 serves as the first terminal of the third transistor M3_1, and the second electrode of the third transistor M3_1 serves as the second terminal of the third transistor M3_1; the first electrode of the first capacitor C1_1 is connected to the gate of the third transistor M3_1, and the second electrode of the first capacitor C1_1 is connected to the second electrode of the third transistor M3_1. The same applies to other output circuits and will not be further described here.

[0151] In some embodiments, the K output circuits may include a cascade output circuit and K' signal output circuits. For example, in Figure 3, output circuit 330_CR may be a cascade output circuit, and output circuits 330_1, 330_2, 330_3, and 330_4 may be signal output circuits. The output signal terminal CR connected to cascade output circuit 330_CR is used to connect to other shift register units, and the output signal terminals OUT1 to OUT4 connected to signal output circuits 330_1, 330_2, 330_3, and 330_4 are used to provide output signals.

[0152] The pull-down circuit may include a first pull-down circuit 3501 and K second pull-down circuits, 3502_CR, 3502_1, 3502_2, 3502_3, and 3502_4 (hereinafter collectively referred to as the second pull-down circuit 3502).

[0153] The first pull-down circuit 3501 is connected to the pull-down node PD, the pull-up node PU, and the reference signal terminal VGL2. The first pull-down sub-circuit 3501 is configured to provide a signal from the reference signal terminal VGL2 to the pull-up node PU under the control of the pull-down node PD. The first pull-down circuit 3501 may include a seventeenth transistor M17, wherein a gate of the seventeenth transistor M17 is connected to the pull-down node PD, a first electrode of the seventeenth transistor M17 is connected to the reference signal terminal VGL2, and a second electrode of the seventeenth transistor M17 is connected to the pull-up node PU.

[0154] K second pull-down circuits 3502_CR, 3502_1, 3502_2, 3502_3, and 3502_4 are respectively connected to K output signal terminals CR, OUT1, OUT2, OUT3, and OUT4, wherein each second pull-down circuit is connected to a pull-down node PD, a reference signal terminal VGL1, and a corresponding output signal terminal. For example, second pull-down circuit 3502_CR is connected to output signal terminal CR, second pull-down circuit 3502_1 is connected to output signal terminal OUT1, second pull-down circuit 3502_2 is connected to output signal terminal OUT2, and so on. Each second pull-down circuit can provide a signal from reference signal terminal VGL1 to a corresponding output signal terminal under the control of pull-down node PD. The second pull-down circuit may include a nineteenth transistor, wherein a gate of the nineteenth transistor is connected to the pull-down node, a first electrode of the nineteenth transistor is connected to the reference signal terminal, and a second electrode of the nineteenth transistor is connected to the corresponding output signal terminal. For example, as shown in FIG3 , the second pull-down circuit 3502_CR includes a nineteenth transistor M19_CR, the second pull-down circuit 3502_1 includes the nineteenth transistor M19_1, the second pull-down circuit 3502_2 includes the nineteenth transistor M19_2, and so on. In the second pull-down circuit 3502_CR, the gate of the nineteenth transistor M19_CR is connected to the pull-down node PD, the first electrode of the nineteenth transistor M19_CR is connected to the reference signal terminal VGL2, and the second electrode of the nineteenth transistor M19_CR is connected to the output signal terminal CR. In the second pull-down circuit 3502_1, the gate of the nineteenth transistor M19_1 is connected to the pull-down node PD, the first electrode of the nineteenth transistor M19_1 is connected to the reference signal terminal VGL1, and the second electrode of the nineteenth transistor M19_1 is connected to the output signal terminal OUT2. The nineteenth transistors in the second pull-down circuits 3502_2 through 3502_4 are connected in a similar manner, and are not further described here.

[0155] Isolation circuits 340_CR, 340_1, 340_2, 340_3, and 340_4 can each include a first transistor. For example, isolation circuit 340_CR includes a first transistor M1_CR, isolation circuit 340_1 includes a first transistor M1_1, isolation circuit 340_2 includes a first transistor M1_2, isolation circuit 340_3 includes a first transistor M1_3, and isolation circuit 340_4 includes a first transistor M1_4. Taking isolation circuit 340_CR as an example, the gate of first transistor M1_CR is connected to control signal terminal CN, the first electrode of first transistor M1_CR serves as the first end of the isolation circuit and is connected to pull-up node PU, and the second electrode of first transistor M1_CR serves as the second end of the isolation circuit and is connected to the control terminal of output circuit 330_CR (i.e., the gate of transistor M3_CR). Other isolation circuits are connected in a similar manner and are not further described here.

[0156] In some embodiments, the shift register unit may further include a reset circuit 360. The reset circuit 360 is connected to the reset signal terminal RST, the pull-up node PU, and the reference signal terminal VGL2 of the shift register unit. The reset circuit 360 is configured to provide a signal from the reference signal terminal VGL2 to the pull-up node PU under the control of the reset signal terminal RST. As shown in FIG3 , the reset circuit 360 may include a sixth transistor M6, wherein a gate of the sixth transistor M6 is connected to the reset signal terminal RST, a first electrode of the sixth transistor M6 is connected to the reference signal terminal VGL2, and a second electrode of the sixth transistor M6 is connected to the pull-up node PU.

[0157] In the above embodiment, two groups of power signal terminals and reference signal terminals are shown, namely, the power signal terminal GVDD1 and the reference signal terminal VGL1 and the power signal terminal GVDD2 and the reference signal terminal VGL2, wherein the input circuit is connected to GVDD1, the second pull-down circuit is connected to the reference signal terminal VGL1, the first pull-down circuit and the reset circuit are connected to the reference signal terminal VGL2, and the control circuit is connected to the power signal terminal GVDD2 and the reference signal terminal VGL2. In this way, the input and output of the signal use one group of power signal terminals and reference signal terminals, while the voltage control of the pull-down node and the pull-up node uses another group of power signal terminals and reference signal terminals, which is more conducive to the stability of the output signal. However, the embodiments of the present disclosure are not limited to this. The number of power signal terminals and reference signal terminals can be set as needed, for example, one group of power signal terminals and reference signal terminals is set, or three or more groups of power signal terminals and reference signal terminals are set, and each circuit in the shift register unit can be connected to the corresponding power signal terminal and reference signal terminal as needed.

[0158] During operation, the control signal terminal CN can be a constant high level, causing the transistors M1_CR, M1_1, M1_2, M1_3, and M1_4 of each isolation circuit to be in a conductive state. In the pre-charge phase, the input signal terminal IN is high, and the transistor M4 in the input circuit is turned on, thereby charging the pull-up node PU and the control terminals PUC, PU1, PU2, PU3, and PU4 of each output circuit. At this time, the transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 in the output circuit are all turned on. In the output phase, the high-level pulse signals of the clock signal terminals CLKCR, CLK1, CLK2, CLK3, and CLK4 arrive in sequence, and the turned-on transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 generate high-level output signals at the output signal terminals CR, OUT1, OUT2, OUT3, and OUT4 in sequence. During this process, assuming that clock signal terminal CLK1 reaches a high level, the potential of control terminal PU1 increases due to the bootstrap effect of capacitor C1_1. This causes the potential of PU1 to be greater than the potential of control signal terminal CN, and the difference between the two is greater than the threshold voltage Vth of transistor M1_1, thereby shutting down transistor M1_1. On the one hand, the shutdown of transistor M1_1 prevents the voltage increase at control terminal PU1 from affecting the signal output of other output circuits. On the other hand, the voltage increase at control terminal PU1 causes transistor M3_1 to operate in the linear region, i.e., the gate-source voltage of transistor M3_1 is much greater than the threshold voltage of transistor M3_1, thereby generating a stable output signal. Due to the presence of the isolation circuit, the voltage bootstrap of the control terminals of each output circuit does not affect each other, and the output capabilities of each output circuit are consistent, thereby improving the waveform consistency of the output signals of each output circuit and promoting display uniformity.

[0159] Figure 4A shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure. The shift register unit of Figure 4A is similar to that of Figure 3 , and for ease of description, the following will mainly describe in detail the differences.

[0160] As shown in FIG4A , the shift register unit includes an input circuit 410, a control circuit 420, output circuits 430_CR, 430_1, 430_2, 430_3, and 430_4 (hereinafter collectively referred to as output circuit 430), isolation circuits 440_CR, 440_1, 440_2, 440_3, and 440_4 (hereinafter collectively referred to as isolation circuit 440), and pull-down circuits (including a first pull-down circuit 4501 and second pull-down circuits 4502_CR, 4502_1, 4502_2, 4502_3, and 4502_4). For descriptions of the output circuit 430 and the isolation circuit 440, reference can be made to the output circuit 330 and the isolation circuit 340 of the aforementioned embodiment, and are not further described here.

[0161] Unlike FIG3 , the shift register unit may further include a third voltage stabilizing circuit 490. The third voltage stabilizing circuit 490 is connected to the voltage stabilizing node Q, the power signal terminal GVDD1, and the pull-up node PU of the shift register unit. The third voltage stabilizing circuit 490 can provide a signal from the power signal terminal GVDD1 to the voltage stabilizing node Q under the control of the pull-up node PU. As shown in FIG4A , the third voltage stabilizing circuit includes a 30th transistor M30 and a 31st transistor M31. The gate of the 30th transistor M30 is connected to the pull-up node PU, the first electrode of the 30th transistor M30 is connected to the power signal terminal GVDD1, the second electrode of the 30th transistor M30 is connected to the first electrode of the 31st transistor M31, the gate of the 31st transistor M31 is connected to the pull-up node PU, the first electrode of the 31st transistor M31 is connected to the second electrode of the 30th transistor M30, and the second electrode of the 31st transistor M31 is connected to the voltage stabilizing node.

[0162] In some embodiments, the shift register unit may further include a master reset circuit 470. The master reset circuit 470 is connected to a master reset signal terminal TRST, a pull-up node PU, and a reference signal terminal VGL2. Under the control of the master reset signal terminal TRST, the master reset circuit 470 may provide a signal from the reference signal terminal VGL2 to the pull-up node PU. The master reset circuit 470 may include a 20th transistor M20, wherein a gate of the 20th transistor M20 is connected to the master reset signal terminal TRST, a first electrode of the 20th transistor M20 is connected to the reference signal terminal VGL2, and a second electrode of the 20th transistor M20 is connected to the pull-up node PU. In some embodiments, the master reset circuit 470 may further include a 21st transistor M21, wherein a first electrode of the 20th transistor M20 is connected to the reference signal terminal VGL2 via the 21st transistor M21, wherein a gate of the 21st transistor M21 is connected to the master reset signal terminal TRST, a first electrode of the 21st transistor M21 is connected to the reference signal terminal VGL2, and a second electrode of the 21st transistor M21 is connected to the first electrode of the 20th transistor M20.

[0163] In some embodiments, the shift register unit may further include a sensing circuit. For example, the sensing circuit may include a selection sub-circuit 4801 and a trigger sub-circuit 4802. The sensing circuit is connected to the sensing selection signal terminal OE, the sensing trigger signal terminal CLKA, the sensing control node H, the input signal terminal IN, and the pull-up node PU of the shift register unit. The sensing circuit may write the signal of the input signal terminal IN to the sensing control node H under the control of the sensing selection signal terminal OE during the display phase, and provide the signal of the sensing control node H to the pull-up node PU under the control of the sensing trigger signal terminal CLKA during the blanking phase.

[0164] As shown in FIG4A , the selection sub-circuit 4801 is connected to the sensing selection signal terminal OE, the sensing control node H, and the input signal terminal IN. The selection sub-circuit 4801 is configured to write the signal from the input signal terminal IN to the sensing control node H under the control of the sensing selection signal terminal OE during the display phase. The selection sub-circuit may include a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, and a second capacitor C2. The gate of the twenty-second transistor M22 is connected to the sensing selection signal terminal OE, the first electrode of the twenty-second transistor M22 is connected to the input signal terminal IN, the second electrode of the twenty-second transistor M22 is connected to the first electrode of the twenty-third transistor M23, the first electrode of the twenty-third transistor M23 is connected to the sensing selection signal terminal OE, the second electrode of the twenty-third transistor M23 is connected to the sensing control node H, the gate of the twenty-fourth transistor M24 is connected to the sensing control node H, the first electrode of the twenty-fourth transistor M24 is connected to the second electrode of the twenty-second transistor M22, the second electrode of the twenty-fourth transistor M24 is connected to the power signal terminal GVDD1, the first electrode of the second capacitor C2 is connected to the power signal terminal GVDD1, and the second electrode of the second capacitor C2 is connected to the gate of the twenty-fourth transistor M24.

[0165] The trigger sub-circuit 4802 is connected to the sense trigger signal terminal CLKA, the sense control node H, and the pull-up node PU. The trigger sub-circuit is configured to provide the signal of the sense control node H to the pull-up node PU under the control of the sense trigger signal terminal CLKA during the blanking phase. The trigger sub-circuit 4802 may include a twenty-fifth transistor M25 and a twenty-sixth transistor M26. The gate of the twenty-fifth transistor M25 is connected to the sense control node H, the first electrode of the twenty-fifth transistor M25 is connected to the power supply signal terminal, the second electrode of the twenty-fifth transistor M25 is connected to the first electrode of the twenty-sixth transistor M26, the gate of the twenty-sixth transistor M26 is connected to the sense trigger signal terminal CLKA, and the second electrode of the twenty-sixth transistor M26 is connected to the pull-up node PU. In some embodiments, the trigger sub-circuit 4802 may further include a twenty-seventh transistor M27. The second electrode of the twenty-sixth transistor M26 is connected to the pull-up node PU via the twenty-seventh transistor M27. The gate of the twenty-seventh transistor M27 is connected to the sense trigger signal terminal CLKA, the first electrode of the twenty-sixth transistor M27 is connected to the second electrode of the twenty-sixth transistor M26, and the second electrode of the twenty-seventh transistor M27 is connected to the pull-up node PU.

[0166] In some embodiments, the sensing circuit may further include a voltage stabilization subcircuit 4803. The voltage stabilization subcircuit 4803 is connected to the sensing control node H, the sensing trigger signal terminal CLKA, and the reference signal terminal VGL2. Under the control of the sensing control node H and the sensing trigger signal terminal CLKA, the voltage stabilization subcircuit 4803 may provide a signal from the reference signal terminal VGL2 to the pull-down node. The voltage stabilization subcircuit 4803 may include a twenty-eighth transistor M28 and a twenty-ninth transistor M29. The gate of the twenty-eighth transistor M28 is connected to the sensing trigger signal terminal CLKA, the first electrode of the twenty-eighth transistor M28 is connected to the pull-up node PU, the second electrode of the twenty-eighth transistor M28 is connected to the first electrode of the twenty-ninth transistor M29, the gate of the twenty-ninth transistor M29 is connected to the sensing control node H, and the second electrode of the twenty-ninth transistor M29 is connected to the reference signal terminal VGL2.

[0167] In some embodiments, at least one of the input circuit, the reset circuit, the pull-down circuit, the master reset circuit, and the sense circuit may be connected to the regulated voltage node.

[0168] For example, in addition to the fourth transistor M4, the input circuit 410 may further include a fifth transistor M5. The gate of the fourth transistor M4 is connected to the input signal terminal IN, the first electrode of the fourth transistor M4 is connected to the power signal terminal GVDD1, and the second electrode of the fourth transistor M4 is connected to the pull-up node PU through the fifth transistor M5. The gate of the fifth transistor M5 is connected to the input signal terminal IN, the first electrode of the fifth transistor M5 is connected to the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is connected to the pull-up node PU. The second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5 can be connected to the voltage regulation node Q.

[0169] For example, the reset circuit may further include a seventh transistor M7 in addition to the sixth transistor M6. The gate of the sixth transistor M6 is connected to the reset signal terminal RST, the first electrode of the sixth transistor M6 is connected to the reference signal terminal VGL2, the second electrode of the sixth transistor M6 is connected to the pull-up node PU via the seventh transistor M7, the gate of the seventh transistor M7 is connected to the reset signal terminal RST, the first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7 is connected to the pull-up node PU. The first electrode of the sixth transistor M6 and the first electrode of the seventh transistor M7 may be connected to the voltage stabilization node Q.

[0170] For example, the first pull-down circuit 4501 in the pull-down circuit may also include an eighteenth transistor M18 in addition to the seventeenth transistor M17, the first electrode of the seventeenth transistor M17 is connected to the reference signal terminal VGL2 through the eighteenth transistor M18, the gate of the eighteenth transistor M18 is connected to the pull-down node, the first electrode of the eighteenth transistor M18 is connected to the reference signal terminal VGL2, and the second electrode of the eighteenth transistor M18 is connected to the first electrode of the seventeenth transistor M17.

[0171] For example, the master reset circuit may further include a twenty-first transistor M21 in addition to the twentieth transistor M20 , and a first electrode of the twentieth transistor M20 and a second electrode of the twenty-first transistor M21 are connected to the voltage stabilization node Q.

[0172] For example, the trigger sub-circuit 4802 in the sensing circuit may include a 27th transistor M27 in addition to the 25th transistor M25 and the 26th transistor M26. The second electrode of the 26th transistor M26 and the first electrode of the 27th transistor M27 may be connected to the regulated voltage node Q.

[0173] In some embodiments, different from FIG3 , the control circuit 420 may include, in addition to the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15, a sixteenth transistor M16. The second electrode of the twelfth transistor M12 may be connected to the gate of the thirteenth transistor M13 via the sixteenth transistor M16, wherein the gate of the sixteenth transistor M16 is connected to the power signal terminal GVDD2, the first electrode of the sixteenth transistor M16 is connected to the second electrode of the twelfth transistor M12, and the second electrode of the sixteenth transistor M16 is connected to the gate of the thirteenth transistor M13.

[0174] In some embodiments, the shift register unit may further include a fourth voltage stabilizing circuit 491, the fourth voltage stabilizing circuit 491 being connected to the pull-down node PD, the input signal terminal IN, and the reference signal terminal VGL2, and being configured to provide a signal of the reference signal terminal VGL2 to the pull-down node PD under the control of the input signal terminal IN. The fourth voltage stabilizing circuit 491 may include a thirty-second transistor M32, the gate of the thirty-second transistor M32 being connected to the input signal terminal IN, a first electrode of the thirty-second transistor M32 being connected to the reference signal terminal VGL2, and a second electrode of the thirty-second transistor M32 being connected to the pull-down node PD.

[0175] FIG4B shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure. The shift register unit of FIG4B is similar to that of FIG4A , except that the difference lies at least in the structure of the isolation circuit. For ease of description, the following will mainly describe the differences in detail.

[0176] As shown in FIG4B , the shift register unit also includes multiple isolation circuits 441_CR, 441_1, 441_2, 441_3, and 441_4 (hereinafter collectively referred to as isolation circuit 441). Unlike FIG3 , the isolation circuit includes a second transistor in addition to the first transistor. For example, isolation circuit 441_CR includes a first transistor M1_CR and a second transistor M2_CR, isolation circuit 441_1 includes a first transistor M1_1 and a second transistor M2_1, and so on. Taking isolation circuit 441_1 as an example, the gate of first transistor M1_1 is connected to the first control signal terminal CN, and the gate of second transistor M2_1 is connected to the second control signal terminal CNB. The first electrode of first transistor M1_1 is connected to the first electrode of second transistor M2_1, thereby connecting to the pull-up node. The second electrode of first transistor M1_1 is connected to the second electrode of second transistor M2_1, thereby connecting to the control terminal PU1 of the corresponding output circuit 430_1. The first transistor and the second transistor in other isolation circuits are connected in a similar manner and will not be repeated here.

[0177] The first control signal terminal CN and the second control signal terminal CNB can each be at a first level and a second level, respectively. For example, during a first period, the first control signal terminal CN is at a high level and the second control signal terminal CNB is at a low level; during a second period, the first control signal terminal CN is at a low level and the second control signal terminal CNB is at a high level. By providing a first transistor and a second transistor in the isolation circuit and alternating the levels of the first control signal terminal CN and the second control signal terminal CNB, the first transistor and the second transistor in each isolation circuit can alternately operate, thereby alleviating the degradation of the isolation transistor's characteristics caused by bias stress and extending the circuit's service life.

[0178] In the above embodiment, K=K' is used as an example for schematic illustration, that is, a corresponding isolation circuit is provided for each output circuit and the pull-up node. However, the embodiments of the present disclosure are not limited thereto, and K' may be smaller than K, that is, the isolation circuit may be omitted for one or more output circuits.

[0179] For example, as shown in FIG4C , compared to the embodiment of FIG4A , the isolation circuit 440_CR of output circuit 430_CR, which serves as the cascade output circuit, is omitted. The control terminal PUC of output circuit 430_CR is connected to the pull-up node PU. Corresponding isolation circuits are provided between output circuits 430_1 through 430_4, which serve as signal output circuits, and the pull-up node. Corresponding isolation circuits are provided between the other output circuits 430_1, 430_2, 430_3, and 430_4 and the pull-up node PU. Because the voltages of the control terminals of output circuits 430_1, 430_2, 430_3, and 430_4 are independently bootstrapped and do not affect each other, nor do they affect the pull-up node PU, even if the control terminal of output circuit 430_CR is connected to the pull-up node PU, all output circuits can be isolated from each other, simplifying the circuit structure.

[0180] As another example, as shown in FIG4D , compared to FIG4A , the isolation circuit 440_1 of output circuit 430_1, one of the multiple signal output circuits, is omitted. The control terminal PU1 of output circuit 430_1 is connected to the pull-up node PU; corresponding isolation circuits are provided between the other output circuits 430_CR, 430_2, 430_3, and 430_4 and the pull-up node PU. While the above description uses the example of omitting one isolation circuit as an example, the embodiments of the present disclosure are not limited thereto, and two or more isolation circuits may be omitted as needed. For example, the isolation circuits may be omitted for output circuits 430_1 and 430_4, while corresponding isolation circuits may be provided between output circuits 430_CR, 430_2, and 430_3 and the pull-up node PU. This approach can reduce the number of bootstrap operations at the pull-up node PU. For example, referring to the timing diagram of Figure 1A , when a high-level pulse at output signal terminal OUT1 raises the potential of pull-up node PU to VU1, the subsequent high-level pulses at output signal terminals OUT2 and OUT3 have no effect on the potential of pull-up node PU. Finally, when a high-level pulse at output signal terminal OUT4 arrives, output signal terminal OUT1 has already fallen back to a low level, so pull-up node PU remains at VU1. In this way, pull-up node PU is raised only once.

[0181] The omission of the isolation circuit also applies to the case of dual isolation transistors. For example, for the shift register unit of FIG4B , the isolation circuit 441_CR of the cascade output circuit 430_CR can be omitted, resulting in the structure shown in FIG4E ; or the isolation circuit 441_1 of the signal output circuit 430_1 can be omitted, resulting in the structure shown in FIG4F . These details are not further described here.

[0182] Embodiments of the present disclosure provide a control method for a shift register unit, applicable to the shift register unit of any of the above-described embodiments. During an input period, an input circuit inputs a signal from an input signal terminal to a pull-up node, and a control circuit, under control of the pull-up node, provides a signal from a reference signal terminal to a pull-down node. During an output period, each of K output circuits, under control of the output circuit's control terminal, provides a signal from a first terminal to a second terminal of the output circuit, thereby generating an output signal at K output signal terminals based on signals from K clock signal terminals. During a reset period, the control circuit, under control of the pull-up node, provides a signal from a power signal terminal to a pull-down node, and the pull-down circuit, under control of the pull-down node, provides a signal from a reference signal terminal to the pull-up node and K output signal terminals. In the above process, before an output circuit connected to a k'th isolation circuit generates an output signal, a signal from the control signal terminal connects the first control terminal and the second control terminal of the k'th isolation circuit. In response to the output circuit connected to the k'th isolation circuit generating an output signal, the potential of the control terminal of the k'th isolation circuit disconnects the first and second terminals of the k'th isolation circuit, where k' = 1, 2, ..., K'.

[0183] FIG5 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure. This timing diagram is applicable to the shift register unit of any of the above embodiments. The signal timing diagram of FIG5 is described below using the shift register unit of FIG4A as an example.

[0184] During the input period (corresponding to periods P1 to P3), the input signal terminal IN is at a high level, transistors M4 and M5 are turned on, and thus the high level of the power signal terminal GVDD1 is provided to the pull-up node PU. The control signal terminal CN is at a constant high level, and the transistors M1_CR, M1_1, M1_2, M1_3, and M1_4 (hereinafter collectively referred to as transistors M1) in each isolation circuit are all turned on. As a result, the control terminals PUC, PU1, PU2, PU3, and PU4 of each output circuit are all at a high level, and the transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 (hereinafter collectively referred to as transistors M3) in the output circuit are all turned on.

[0185] During the output period (corresponding to periods P4 to P16), the high-level pulses of the clock signals of the clock signal terminals CLK1, CLK2, CLK3, CLK4, and CLKCR arrive in sequence, and the turned-on transistor M3 provides the clock signals of the corresponding clock signal terminals to the output signal terminals OUT1, OUT2, OUT3, OUT4, and CR.

[0186] During the reset period (corresponding to periods P17 to P19), the reset signal terminal RST is at a high level, transistors M7 and M8 are turned on, thereby providing the low level of the reference signal terminal VGL2 to the pull-up node PU, thereby resetting the pull-up node PU to a low level. The low level of the pull-up node PU also turns off transistors M14 and M15, thereby transistors M12, M13, and M16 provide the high level of the power supply signal terminal GVDD2 to the pull-up node PD. The high level of the pull-up node PD turns on transistors M19_1, M19_2, M19_3, M19_4, and M19_CR, thereby maintaining the output signal terminals OUT1, OUT2, OUT3, OUT4, and CR at a low level.

[0187] During the above process, the control signal terminal CN is at a constant high level, and the transistors M1 in each isolation circuit are all in the on state before generating an output signal. When an output signal terminal generates a high-level output signal, for example, during period P5, when the output signal terminal OUT1 generates a high-level output signal, the bootstrap effect of capacitor C1_1 causes the gate potential of transistor M3_1 (i.e., the control terminal PU1 of output circuit 430_1) to be further raised from GVDD1 to VPU, as shown in FIG4A . This causes the potential of PU1 to be higher than the potential of the control signal terminal CN, and the difference between the potential and the control signal terminal CN is greater than the threshold voltage of transistor M1_1, thereby turning off transistor M1_1. Turning off transistor M1_1 disconnects the control terminal PU1 of output circuit 430_1 from the pull-up node PU, thereby preventing the potential of the pull-up node PU from being affected by the control terminal PU1. As shown in FIG4A , the potential of the pull-up node PU remains at GVDD1. Similarly, when output signal terminal OUT2 generates a high-level output signal during period P6, the bootstrap effect of capacitor C1_2 raises the potential of control terminal PU2. This raised potential of control terminal PU2 turns off transistor M1_2, thereby maintaining the potential of pull-up node PU. Similarly, the presence of transistor M1 ensures that the voltage increases at the control terminals of output circuits 430_2, 430_3, 430_4, and 430_CR do not affect each other, ensuring that the gate-source voltage Vgs of transistor M3 in each output circuit remains within the linear region, consistent with output capability and load, and thus producing output signals with consistent waveforms at each output signal terminal. In some embodiments, each signal output circuit can be configured to have exactly the same structure, for example, transistors M3_1, M3_2, M3_3, and M3_4 are of the same size, drive the same load, and capacitors C1_1, C1_2, C1_3, and C1_4 are the same, so that the voltage after bootstrapping is the same as VPU, ensuring that the driving capabilities of each signal output circuit are the same and the driving waveforms are the same (for example, the rising delay time, the high and low voltage negative values, and the falling delay time are all the same). In some embodiments, the structure of the cascade output circuit can be different from the signal output circuit, for example, the parameters of the transistor M3_CR can be different from the transistors M3_1, M3_2, M3_3, and M3_4 in the signal output circuit, and the capacitor C3_CR can also be different from C3_1, C3_2, C3_3, and C3_4, so the bootstrap voltage VPUC of the control terminal PUC can be different from the bootstrap voltage VPU of the control terminals PU1 to PU4.

[0188] By comparing with the signal timing of FIG1 , it can be seen that the embodiment of the present disclosure avoids step-type voltage conversion caused by multiple self-bootstrapping of the pull-up node PU by providing an isolation circuit, thereby facilitating stable signal output.

[0189] Figure 6 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure. This signal timing diagram can be applied to the shift register unit of Figure 4B. The signal timing diagram of Figure 6 is similar to Figure 5, except that the control signal terminal includes a first control signal terminal CN and a second control terminal CNB. The first control signal terminal CN and the second control terminal CNB can be alternately high and low. For example, as shown in Figure 7, in the first time period, the first control terminal CN is a first level (for example, a high level of the power signal terminal GVDD1), and the second control terminal CNB is a second level (for example, a low level of the reference signal terminal VGL2); then in the second time period, the first control signal terminal CN is a second level, and the second control signal terminal CNB is a first level, and so on.

[0190] When the first control signal terminal CN is high and the second control signal terminal CNB is low, transistor M1 in each isolation circuit operates, while transistor M2 does not. Conversely, when the first control signal terminal CN is low and the second control signal terminal CNB is high, transistor M2 in each isolation circuit operates, while transistor M1 does not. In this way, transistors M1 and M2 in each isolation circuit can operate alternately, thereby alleviating the characteristic degradation caused by bias stress of the transistors in the isolation circuit and extending the circuit's service life.

[0191] According to an embodiment of the present disclosure, the high-low level switching frequency or period of the first control signal terminal CN and the second control signal terminal CNB depends on the characteristics of the device. For example, the switching period can be an integer multiple of the frame time, that is, it alternates once every N*T_frame, where T_frame represents a frame time and N is a positive integer. The high-low level switching of the first control signal terminal CN and the second control signal terminal CNB can be at the beginning of a frame or before the reset signal of the reset signal terminal RST arrives, so as to reduce the noise impact on the pull-up node PU during switching. By switching before the reset signal of the reset signal terminal RST arrives, the noise can be released through the reset process. The reset signal pulse of the reset signal terminal RST will arrive at least once in a frame, that is, a reset is performed at least once in a frame, so the time for the first control signal terminal CN and the second control signal terminal CNB to maintain a high level is an integer multiple of a frame time.

[0192] As the application scenarios of display devices become more and more extensive, the application of splicing multiple display panels to achieve larger display sizes is particularly popular. However, splicing multiple panels may cause the display graphics near the splicing area to tear, which will be explained below with reference to Figures 8A to 8C.

[0193] 8A to 8C show display effects of a spliced ​​screen.

[0194] The output signals generated by the shift register units in the gate drive circuit usually scan the pixel array on the display panel in a unidirectional scanning manner, ie, scanning from the first row to the last row, or from the last row to the first row.

[0195] A spliced ​​screen uses smaller screens that are pieced together edge-to-edge to create a larger screen. Two display panels (also called screens) are spliced ​​together using either end-by-end or in-by-in splicing. As shown in Figure 8A, the shift register units in the gate drive circuits (GOA) of screens A and B are cascaded in reverse scanning mode, meaning the output signals are sequentially scanned from the last row to the first row. The end of screen A (i.e., the end where the last shift register unit is located) is connected to the end of screen B. With this splicing method, graphics near the splicing position are scanned and displayed simultaneously, resulting in a synchronized and relatively complete picture, such as the smiling face shown in Figure 8A below.

[0196] If three screens are spliced ​​together vertically, that is, screens A, B, and C, the borders at the inbound end and the end end are different. To ensure the same width of the splicing gap, only the in-by-end splicing method can be used, as shown in Figures 8B and 8C. If the GOA scanning direction is consistent, as shown in Figure 8B, the smiling face part displayed on screen A is delayed compared to the smiling face part on screen B. If the smiling face image moves quickly to the right, the display will be torn. The same is true for the splicing between screens B and C. If the GOA scanning direction of screen B is opposite to the GOA scanning direction of screens A and C, then the images at the two splicing points will be displayed simultaneously, and there will be no screen tearing. As shown in Figure 8C.

[0197] The embodiments of the present disclosure provide a shift register unit capable of performing both forward scanning (forward scanning) and reverse scanning (reverse scanning) functions, thereby adjusting the signal at the control signal terminal of the shift register unit to achieve forward scanning or reverse scanning. This will be described in detail below with reference to Figures 9 to 14.

[0198] FIG9 shows a schematic block diagram of a shift register unit according to another embodiment of the present disclosure.

[0199] As shown in FIG. 9 , the shift register unit 500 includes a first input circuit 5101 , a second input circuit 5102 , a control circuit 520 , K output circuits 530_1 and 530_2 , and a pull-down circuit 550 .

[0200] The first input circuit 5101 is connected to the first input signal terminal IN1, the pull-up node PU and the first control signal terminal CN of the shift register unit. The first input circuit 5101 is used to provide the signal of the first control signal terminal CN to the pull-up node PU under the control of the first input signal terminal IN1.

[0201] The second input circuit 5102 is connected to the second input signal terminal IN2 of the shift register unit, the pull-up node PU and the second control signal terminal CNB. The second input circuit 5102 is used to provide the signal of the second control signal terminal CNB to the pull-up node PU under the control of the second input signal terminal IN2.

[0202] The control circuit 520 is connected to the pull-up node PU and the pull-down node PD of the shift register unit, the power signal terminal GVDD and the reference signal terminal VGL. The control circuit 520 is used to provide a signal from one of the power signal terminal GVDD and the reference signal terminal VGL to the pull-down node PD under the control of the pull-up node PU.

[0203] K output circuits 530_1 and 530_2 are connected to the K clock signal terminals CLK1 and CLK2, K output signal terminals OUT1 and OUT2, and a pull-up node PU of the shift register unit. The first terminal of the k-th output circuit is connected to the k-th clock signal terminal of the shift register unit, and the second terminal of the k-th signal output circuit is connected to the k-th output signal terminal of the shift register unit. For example, the control terminals of the output circuits 530_1 and 530_2 are both connected to the pull-up node PU. The first terminal of the output circuit 530_1 is connected to the clock signal terminal CLK1, and the second terminal is connected to the output signal terminal OUT1; the first terminal of the output circuit 530_2 is connected to the clock signal terminal CLK2, and the second terminal is connected to the output signal terminal OUT2. Each output circuit is configured to provide a signal at a first terminal of the output circuit to a second terminal of the output circuit under the control of the control terminal of the output circuit, where K is an integer greater than 1, and k=1, 2, ..., K.

[0204] The pull-down circuit 550 is connected to the pull-down node PD, the pull-up node PU, K output signal terminals OUT1 and OUT2, and the reference signal terminal VGL. The pull-down sub-circuit 550 is used to provide the signal of the reference signal terminal VGL to the pull-up node PU and the K output signal terminals OUT1 and OUT2 under the control of the pull-down node PD.

[0205] In the forward scan mode, the first control signal terminal CN is at a first level, and the second control signal terminal CNB is at a second level. Thus, when an input signal arrives from the first input signal terminal IN1, the first input circuit 5101, under the control of the first input signal terminal IN1, provides the first level of the first control signal terminal CN to the pull-up node PU. The signal at the pull-up node PU causes the output circuits 530_1 and 530_2 to generate output signals at the clock signal terminals CLK1 and CLK2, respectively, at the output signal terminals OUT1 and OUT2. When a reset signal arrives from the second input signal terminal IN2, the second input circuit 5102, under the control of the reset signal from the second input signal terminal IN2, provides the second level of the second control signal terminal CNB to the pull-up node PU, thereby resetting the pull-up node PU. In other words, in the forward scan mode, the first input circuit 5101 functions as an input circuit, and the second input circuit 5102 functions as a reset circuit.

[0206] In the reverse scan mode, the first control signal terminal CN is at the second level, and the second control signal terminal CNB is at the first level. Thus, when an input signal arrives from the second input signal terminal IN2, the second input circuit 5102, under the control of the second input signal terminal IN2, provides the first level of the second control signal terminal CNB to the pull-up node PU. The signal at the pull-up node PU causes the output circuits 530_1 and 530_2 to generate output signals at the clock signal terminals CLK1 and CLK2, respectively, at the output signal terminals OUT1 and OUT2. When a reset signal arrives from the first input signal terminal IN1, the first input circuit 5101, under the control of the reset signal from the first input signal terminal IN1, provides the second level of the first control signal terminal CN to the pull-up node PU, thereby resetting the pull-up node PU. In other words, in the reverse scan mode, the second input circuit 5102 functions as an input circuit, and the first input circuit 5101 functions as a reset circuit.

[0207] The embodiments of the present disclosure provide a first control signal terminal and a second control signal terminal that are independent of the power signal terminal and the reference signal terminal. By changing the signals at the first control signal terminal and the second control signal terminal, both forward and reverse scanning modes can be achieved, allowing the shift register unit to be set to forward or reverse scanning mode as needed. This allows the scanning direction of each shift register unit to be designed as needed during screen splicing, thereby avoiding the problem of display tearing at the spliced ​​portion caused by the shift register unit having only a single scanning direction.

[0208] In some embodiments, the shift register unit may further include a first voltage stabilizing circuit 592 and a second voltage stabilizing circuit 593. The first voltage stabilizing circuit 592 is connected to the pull-down node PD, the second input signal terminal IN2, and the first control signal terminal CN. The first voltage stabilizing circuit 592 is configured to provide a signal from the first control signal terminal CN to the pull-down node PD under the control of the second input signal terminal IN2. The second voltage stabilizing circuit 593 is connected to the pull-down node PD, the first input signal terminal IN1, and the second control signal terminal CNB. The second voltage stabilizing circuit 593 is configured to provide a signal from the second control signal terminal CNB to the pull-down node PD under the control of the first input signal terminal IN1. In the forward scan mode, the second voltage stabilizing circuit 593 provides the second voltage level of the second control signal terminal CNB to the pull-down node PD under the control of the first input signal terminal IN1. In the reverse scan mode, the first voltage stabilizing circuit 592 provides the second voltage level of the first control signal terminal CN to the pull-down node PD under the control of the second input signal terminal IN2. By providing the first and second voltage stabilizing circuits, the pull-down node can be stabilized at the second voltage level during the generation of the output signal, thereby facilitating stable signal output.

[0209] FIG10 shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure. The shift register unit of FIG10 is similar to that of FIG3 , with the difference being at least in the input circuit and the isolation circuit. For ease of description, the following will primarily describe the differences in detail.

[0210] As shown in FIG10 , the shift register unit 600 includes a first input circuit 6101, a second input circuit 6102, a control circuit 620, output circuits 630_CR, 630_1, 630_2, 630_3, and 630_4, and a pull-down circuit. The pull-down circuit may include a first pull-down circuit 6501 and second pull-down circuits 6502_CR, 6502_1, 6502_2, 6502_3, and 6502_4 (hereinafter collectively referred to as the second pull-down circuit 6502). The description of the control circuit and the pull-down circuit in the above embodiment with reference to FIG3 is also applicable to this embodiment and will not be repeated here. Each output circuit 330_CR, 330_1, 330_2, 330_3, and 330_4 may include a third transistor M3_CR, M3_1, M3_2, M3_3, and M3_4 (hereinafter collectively referred to as the third transistor M3) and a first capacitor C1_CR, C1_1, C1_2, C1_3, and C1_4 (hereinafter collectively referred to as the first capacitor C1). Unlike FIG3, the shift register unit of FIG10 removes the isolation circuit, and the gate of the third transistor M3 of each output circuit is connected to the pull-up node PU. However, the embodiments of the present disclosure are not limited thereto, and the shift register unit of FIG10 may also include an isolation circuit, and the isolation circuit structure of any of the above embodiments may be adopted.

[0211] 3 , the input signal terminals of the shift register unit 600 include first input signal terminals IN1 and IN2 , and the control signal terminals include first control signal terminals CN and second control signal terminals CNB . The shift register unit 600 includes a first input circuit 6101 and a second input circuit 6102 .

[0212] The first input circuit 6101 may include a fourth transistor M4 , a gate of the fourth transistor M4 connected to the first input signal terminal IN1 , a first electrode of the fourth transistor M4 connected to the first control signal terminal CN, and a second electrode of the fourth transistor M4 connected to the pull-up node PU.

[0213] The second input circuit 6102 may include a sixth transistor M6 , a gate of the sixth transistor M6 connected to the second input signal terminal IN2 , a first electrode of the sixth transistor M6 connected to the second control signal terminal CNB, and a second electrode of the sixth transistor M6 connected to the pull-up node PU.

[0214] In some embodiments, the parameters of the fourth transistor M4 are the same as those of the sixth transistor M6. This allows the first input circuit and the second input circuit for charging the pull-up node PU to have a symmetrical structure, and the shift register unit has the same input capability in the forward scanning mode and the reverse scanning mode, which is beneficial to the stability of the output signal.

[0215] In some embodiments, the shift register unit 600 may further include a first voltage stabilizing circuit 692 and a second voltage stabilizing circuit 693. The first voltage stabilizing circuit 692 may include an eighth transistor M8, wherein a gate of the eighth transistor M8 is connected to the second input signal terminal IN2, a first electrode of the eighth transistor M8 is connected to the first control signal terminal, and a second electrode of the eighth transistor M8 is connected to the pull-down node PD.

[0216] The second voltage stabilizing circuit 693 may include a ninth transistor M9 , a gate of the ninth transistor M9 being connected to the first input signal terminal IN1 , a first electrode of the ninth transistor M9 being connected to the second control signal terminal, and a second electrode of the ninth transistor M9 being connected to the pull-down node PD.

[0217] In some embodiments, the eighth transistor M8 and the ninth transistor M9 have the same parameters. This allows the first voltage stabilization circuit and the second voltage stabilization circuit for discharging the pull-down node PD to have a symmetrical structure, thereby achieving the same discharge capability for the pull-down node in both the forward scan mode and the reverse scan mode, thereby facilitating the stability of the output signal.

[0218] FIG11A shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure. The shift register unit of FIG11A is similar to that of FIG4A , with the difference being at least in the input circuit and the isolation circuit. For ease of description, the following will primarily describe the differences in detail.

[0219] As shown in FIG11A , the shift register unit 700 includes a control circuit 720, output circuits 730_CR, 730_1, 730_2, 730_3, and 730_4 (hereinafter collectively referred to as output circuit 730), a pull-down circuit (including a first pull-down circuit 7501 and second pull-down circuits 7502_CR, 7502_1, 7502_2, 7502_3, and 7502_4), a third voltage stabilization circuit 790, a sensing circuit (including a selection sub-circuit 7801, a trigger sub-circuit 7802, and a voltage stabilization sub-circuit 7803), and a master reset circuit 770. The description of the control circuit, output circuit, pull-down circuit, third voltage stabilization circuit, sensing circuit, and master reset circuit with reference to FIG4A above also applies to this embodiment and is not repeated here.

[0220] Unlike FIG4A , the first input circuit 7101 includes a fourth transistor M4 and a fifth transistor M5. The second electrode of the fourth transistor M4 is connected to a pull-up node PU via the fifth transistor M5. The gate of the fifth transistor M5 is connected to the first input signal terminal IN1, the first electrode of the fifth transistor M5 is connected to the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is connected to the pull-up node PU. The second input circuit 7102 includes a sixth transistor M6 and a seventh transistor M7. The gate of the sixth transistor M6 is connected to the second input signal terminal IN2, the first electrode of the sixth transistor M6 is connected to the second control signal terminal, the second electrode of the sixth transistor M6 is connected to the pull-up node PU, the gate of the seventh transistor M7 is connected to the second control signal terminal, the first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7 is connected to the pull-up node PU. The second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5 can be connected to the voltage stabilization node Q. The second electrode of the sixth transistor M6 and the first electrode of the seventh transistor M7 can be connected to the voltage stabilization node Q.

[0221] In some embodiments, the fourth transistor M4 and the sixth transistor M6 may have the same parameters, and the fifth transistor M5 and the seventh transistor M7 may have the same parameters. In other embodiments, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 may have the same parameters. In this way, the first input circuit and the second input circuit for charging the pull-up node PU can form a symmetrical structure, so that the charging capacity of the pull-up node PU is the same in the forward scanning mode and the reverse scanning mode, which is beneficial to the stability of the potential of the pull-up node PU, and thus beneficial to the stability of the output signal. By setting the first and second input circuits into a dual-transistor structure and connecting them to the voltage stabilizing node, the transistors in the input circuit can be prevented from leaking, which is further beneficial to the stability of the potential of the pull-up node PU.

[0222] FIG11B shows a circuit diagram of a shift register unit according to another embodiment of the present disclosure. The shift register unit of FIG11B is similar to that of FIG11A , with the difference being at least in the structure of the voltage stabilization circuit. For ease of description, the following will primarily describe the differences in detail.

[0223] 11B , the shift register unit includes a first voltage stabilizing circuit 792 and a second voltage stabilizing circuit 793 as well as an intermediate voltage stabilizing circuit 794. The first voltage stabilizing circuit 792, the second voltage stabilizing circuit 793 and the intermediate voltage stabilizing circuit 794 are connected to an intermediate node QQ.

[0224] The first voltage stabilizing circuit 792 is connected to the intermediate node QQ, the first input signal terminal IN1, and the first control signal terminal CN. The first voltage stabilizing circuit 792 is configured to provide a signal from the first control signal terminal CN to the intermediate node QQ under the control of the first input signal terminal IN1. The first voltage stabilizing circuit 792 may include an eighth transistor M8, wherein a gate of the eighth transistor M8 is connected to the first input signal terminal IN1, a first electrode of the eighth transistor M8 is connected to the first control signal terminal CN, and a second electrode of the eighth transistor M8 is connected to the intermediate node QQ.

[0225] The second voltage-stabilizing circuit 793 is connected to the intermediate node QQ, the second input signal terminal IN2, and the second control signal terminal CNB. The second voltage-stabilizing circuit 793 is configured to provide a signal from the second control signal terminal CNB to the intermediate node QQ under the control of the second input signal terminal IN2. The second voltage-stabilizing circuit 793 may include a ninth transistor M9, wherein a gate of the ninth transistor M9 is connected to the second input signal terminal IN2, a first electrode of the ninth transistor M9 is connected to the second control signal terminal CNB, and a second electrode of the ninth transistor M9 is connected to the intermediate node QQ.

[0226] The intermediate voltage regulator circuit 794 is connected to the pull-down node PD, the intermediate node QQ, and the reference signal terminal VGL2. The intermediate voltage regulator circuit 794 can provide a signal from the reference signal terminal VGL2 to the intermediate node QQ under the control of the pull-down node PD, and can also provide a signal from the reference signal terminal VGL2 to the pull-down node PD under the control of the intermediate node QQ. The intermediate voltage regulator circuit 794 can include a tenth transistor M10 and an eleventh transistor M11. The gate of the tenth transistor M10 is connected to the intermediate node QQ, the first electrode of the tenth transistor M10 is connected to the reference signal terminal VGL2, the second electrode of the tenth transistor M10 is connected to the pull-down node PD, the gate of the eleventh transistor M11 is connected to the pull-down node PD, the first electrode of the eleventh transistor M11 is connected to the reference signal terminal VGL2, and the second electrode of the eleventh transistor M11 is connected to the intermediate node QQ.

[0227] In the forward scanning mode, when the first input signal terminal IN1 reaches a high level, transistor M8 is turned on, thereby providing the high level of the first control signal terminal CN to the intermediate node QQ. Transistor M10 is turned on, thereby providing the low level of the reference signal terminal VGL2 to the pull-down node PD. The low level of the pull-down node PD also keeps transistor M11 off. Next, the high level of the second input signal terminal IN2 arrives, the pull-down node PD is high, and transistor M9 is turned on, thereby providing the low level of the second control signal terminal CNB to the intermediate node QQ. Transistor M11 is turned on, thereby maintaining the intermediate node QQ at a low level. The low level of the intermediate node QQ causes transistor M10 to turn off, thereby preventing the intermediate node QQ from being mistakenly raised due to noise, thereby misleadingly turning on the tenth transistor M10, causing abnormal conduction between the power supply signal terminal GVDD2 and the reference signal terminal VGL2 through transistors M13 and M10.

[0228] In the reverse scan mode, when the high level of the second input signal terminal IN2 arrives, the transistor M9 is turned on, thereby providing the high level of the second control signal terminal CNB to the intermediate node QQ, and the transistor M10 is turned on, thereby providing the low level of the reference signal terminal VGL2 to the pull-down node PD. The low level of the pull-down node PD also turns off the transistor M11. Then, the high level of the first input signal terminal IN1 arrives, the pull-down node PD is high, the transistor M8 is turned on, thereby providing the low level of the first control signal terminal CN to the intermediate node QQ, and the transistor M11 is turned on, thereby maintaining the intermediate node QQ at a low level. The low level of the intermediate node QQ causes the transistor M10 to turn off, thereby preventing the intermediate node QQ from being mistakenly raised due to noise, thereby misleadingly turning on the tenth transistor M10, causing the power supply signal terminal GVDD2 to be abnormally connected to the reference signal terminal VGL2 through the transistors M13 and M10.

[0229] The embodiments of the present disclosure enhance the anti-noise capability of the circuit by providing an intermediate voltage stabilization circuit and an intermediate node.

[0230] The embodiments of the present disclosure further provide a control method for a shift register unit, which is applicable to the shift register unit of any of the above embodiments.

[0231] In the forward scan mode, the first control signal terminal is at a first level, and the second control signal terminal is at a second level, wherein in the input period, the first input circuit provides the signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal; in the output period, each of the K output circuits provides the signal of the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit; in the reset period, the second input circuit provides the signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal, the control circuit provides the signal of the reference signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

[0232] In the reverse scan mode, the first control signal terminal is at the second level, and the second control signal terminal is at the first level, wherein in the input period, the second input circuit provides the signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal; in the output period, each of the K output circuits provides the signal of the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit; in the reset period, the first input circuit provides the signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal, the control circuit provides the signal of the reference signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

[0233] FIG12 illustrates a signal timing diagram of a shift register unit in a forward scanning mode according to an embodiment of the present disclosure. FIG13 illustrates a signal timing diagram of a shift register unit in a reverse scanning mode according to an embodiment of the present disclosure. The signal timings of FIG12 and FIG13 are applicable to any shift register unit having forward and reverse scanning functions in any embodiment. The signal timings of FIG12 and FIG13 are described in detail below in conjunction with the shift register unit of FIG11A.

[0234] As shown in Figure 12, in the forward scan mode, the first control signal terminal CN is at a high level, and the second control signal terminal CNB is at a low level. During periods P1 to P3, the first input signal terminal IN1 reaches a high level, transistors M4 and M5 are turned on, the high level of the first control signal terminal CN is provided to the pull-up node PU, and transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 are turned on. During periods P5 to P11, the clock signal terminals CLK1, CLK2, CLK3, CLK4, and CLKCR receive sequentially shifted clock signals. The turned-on transistors M3_1 to M3_4 respectively provide the clock signals from the clock signal terminals CLK1 to CLK4 to the output signal terminals OUT1 to OUT4. The turned-on transistor M3_CR provides the clock signal received by the clock signal terminal CLKCR to the output signal terminal CR. Next, during periods P17 to P19, the second input signal terminal IN receives a high-level reset signal, turning on transistors M6 and M7, thereby resetting the pull-up node PU to the low level of the second control signal terminal CNB. The low level of the pull-up node PU turns off transistors M14 and M15, causing the pull-down node PD to reach a high level. Transistors M19_CR, M19_1, M19_2, M19_3, and M19_4 turn on, causing the output signal terminals OUT1, OUT2, OUT3, OUT4, and CR to all maintain a low level.

[0235] In reverse scan mode, the first control signal terminal CN is at a low level, and the second control signal terminal CNB is at a high level. During periods P1 to P3, the second input signal terminal IN2 reaches a high level, transistors M6 and M7 turn on, and the high level of the second control signal terminal CNB is provided to the pull-up node PU. Transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 turn on. During periods P5 to P11, clock signal terminals CLK4, CLK3, CLK2, CLK1, and CLKCR receive sequentially shifted clock signals. The turned-on transistors M3_1 to M3_4 respectively provide the clock signals from clock signal terminals CLK1 to CLK4 to output signal terminals OUT1 to OUT4. The turned-on transistor M3_CR provides the clock signal received by clock signal terminal CLKCR to output signal terminal CR. Next, during periods P17 to P19, the first input signal terminal IN receives a high-level reset signal, turning on transistors M4 and M5, thereby resetting the pull-up node PU to the low level of the first control signal terminal CN. The low level of the pull-up node PU turns off transistors M14 and M15, causing the pull-down node PD to reach a high level. Transistors M19_CR, M19_1, M19_2, M19_3, and M19_4 turn on, causing the output signal terminals OUT1, OUT2, OUT3, OUT4, and CR to all maintain a low level.

[0236] In this way, the shift register unit can generate pulses of the output signal in the order of OUT1, OUT2, OUT3 and OUT4 in the forward scanning mode, thereby realizing forward scanning; it can also generate pulses of the output signal in the order of OUT4, OUT3, OUT2, OUT1 in the reverse scanning mode, thereby realizing reverse scanning.

[0237] Figure 14 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure during the display phase and the blanking phase. This timing diagram is applicable to any of the above-mentioned embodiments having a sensing circuit. The signal timing diagram of Figure 14 will be described in detail below in conjunction with the shift register unit of Figure 11A. In Figure 14, it is assumed that the shift register unit operates in a forward scanning mode, that is, the first input signal terminal IN1 receives an input signal, and the second input signal terminal IN2 receives a reset signal.

[0238] As shown in Figure 14, a frame may include a display phase and a blanking phase. The shift register unit may generate a display scanning signal for driving pixels to emit light during the display phase, and may generate a sensing scanning signal for sensing during the blanking phase.

[0239] During the display phase, the shift register unit, in response to receiving a high-level input signal at the first input signal terminal IN, generates sequentially shifted output signals at the output signal terminals OUT1, OUT2, OUT3, OUT4, and CR based on the clock signals at the clock signal terminals CLK1, CLK2, CLK3, CLK4, and CR, respectively. During this process, during periods P1 to P3, both the input signal received at the first input signal terminal IN and the select signal received at the sense select signal terminal OE are high, turning on transistors M22 and M23. This causes the high level at the input signal terminal IN to be written to the sense control node H. The high level at the sense control node H then turns on transistor M25.

[0240] During the blanking phase, when the sensing trigger signal terminal CLKA reaches a high level, transistors M26 and M27 are turned on. The high level of the power supply signal terminal GVDD1 is provided to the pull-up node PU through the turned-on transistors M25, M26, and M27, thereby charging the PU node. Transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 are all turned on. Next, the clock signal terminal CLK3 receives a clock signal with a specific waveform. The turned-on transistor M3_3 provides the clock signal from the clock signal terminal CLK3 to the output signal terminal OUT3, thereby generating a sensing scan signal at the output signal terminal OUT3.

[0241] The gate drive circuit includes multiple shift register units connected in cascade. The sensing selection signal, the sensing trigger signal, and the clock signal can be used to select a certain output signal terminal of a certain shift register unit to output the signal in the blanking phase. For example, assuming that the gate drive circuit includes multiple shift register units, each shift register unit has four output signal terminals. If a sensing scan signal is to be generated to turn on the sub-pixels in the 7th row during the blanking phase, the third output signal terminal OUT3 of the second shift register unit needs to be controlled. <2> Generate a sensing scan signal. Then, in the display phase, the sensing selection signal terminals of each shift register receive the same sensing selection signal, wherein the sensing selection signal received by the second-stage shift register is at the same high level as the input signal received by its input signal terminal, thereby writing a high level to the sensing control node H of the second-stage shift register, while the sensing control nodes H of the other shift register units remain at a low level. In this way, when the high level of the sensing trigger signal terminal CLKA arrives during the blanking phase, only the pull-up node PU of the second-stage shift register unit whose sensing control node H is at a high level is charged, thereby controlling the third output signal terminal OUT3 of the second-stage shift register unit by applying a preset clock signal to each clock signal terminal (in this embodiment, a high-level clock signal is applied to the clock signal terminal CLK3, while the other clock signal terminals remain at a low level). <n>A sensing scanning signal is generated, as shown in FIG14 .

[0242] According to the embodiment of the present disclosure, the structure for the forward and reverse scanning function is also applicable to the shift register unit with the isolation circuit. In other words, the shift register unit can include the isolation circuit and have the forward and reverse scanning structure.

[0243] For example, the forward and reverse scan structure shown in FIG11B can be applied to the shift register unit of FIG4B to obtain the circuit structure of the shift register unit as shown in FIG15. As shown in FIG15, the shift register unit 800 is similar to the shift register unit of FIG4B, except that the input circuit and the reset circuit in FIG4B are replaced by a first input circuit 8101 and a second input circuit 8102, and the shift register unit 800 further includes a first voltage stabilizing circuit 892, a second voltage stabilizing circuit 893, and an intermediate voltage stabilizing circuit 894. The above description of the output circuit with reference to FIG4B and the description of the first input circuit, the second input circuit, the first voltage stabilizing circuit, and the intermediate voltage stabilizing circuit with reference to FIG11A are also applicable to this embodiment and are not repeated here.

[0244] For another example, the forward and reverse scan circuit structure shown in FIG11A can be applied to the shift register unit shown in FIG4A to obtain the shift register unit 900 shown in FIG16. As shown in FIG16, the shift register unit 900 is similar to the shift register unit shown in FIG4A, except that the input circuit and the reset circuit are replaced by the first input circuit 910 and the second input circuit 960, and further includes a first voltage stabilizing circuit 992 and a second voltage stabilizing circuit 993. The description of the first input circuit, the second input circuit, the first voltage stabilizing circuit, and the second voltage stabilizing circuit with reference to FIG11A above is also applicable to this embodiment and will not be repeated here.

[0245] The above is merely an illustrative description, and the embodiments of the present disclosure are not limited thereto. The forward and reverse scan structures of any of the above embodiments can be applied to the shift register unit of any embodiment having an isolation circuit. For example, the forward and reverse scan circuit structure of any embodiment described above with reference to Figures 10 to 11B can be applied to the shift register unit of any embodiment having an isolation circuit described above with reference to Figures 3 to 4F.

[0246] In the embodiment of the present disclosure, an isolation circuit is provided in the shift register unit to achieve mutual voltage bootstrapping of the control terminals of the output circuits, and a forward and reverse scanning circuit structure is provided to provide forward and reverse scanning functions.

[0247] It should be noted that, for the sake of convenience in illustrating, in Figures 5, 6, and 12 to 14, the signal waveform at the clock signal end is shown in the form of a single pulse, but this does not constitute a limitation on the waveform of the clock signal. The clock signal received by the clock signal end of the shift register unit in the embodiment of the present disclosure is a periodic signal, and the period and duty cycle of the clock signal can be set as needed.

[0248] An embodiment of the present disclosure further provides a gate driving circuit, comprising a plurality of shift register units connected in cascade. The plurality of shift register units may be implemented by the shift register units of any of the above embodiments.

[0249] FIG17 shows a schematic block diagram of a gate drive circuit according to an embodiment of the present disclosure. As shown in FIG17 , the gate drive circuit includes a plurality of shift register units GOA1, GOA2, GOA3, …. Each shift register unit can be implemented by the shift register unit of any of the above-mentioned embodiments. For ease of description, the shift register units shown in FIG3 to FIG4F will be used as an example for explanation. The plurality of shift register units GOA1, GoA2, GOA3, … in the gate drive circuit are cascaded, wherein the input signal terminal of the n-th shift register unit is connected to the cascade output terminal of the ni-th shift register unit, and the reset signal terminal is connected to the cascade output terminal of the n+j-th shift register unit. Here, i and j can be set as needed, for example, i=j=2. In this case, the cascade output terminal CR of the first-stage shift register unit GOA1 is connected to the input signal terminal IN of the third-stage shift register unit GOA3, the cascade output terminal CR of the second-stage shift register unit GOA2 is connected to the input signal terminal of the fourth-stage shift register unit GOA4, and so on; the cascade output terminal of the third-stage shift register unit GOA3 is connected to the reset signal terminal RST of the first-stage shift register unit GOA1, the cascade output terminal of the fourth-stage shift register unit GOA4 is connected to the reset signal terminal RST of the second-stage shift register unit GOA2, and so on.

[0250] The gate drive circuit can receive multiple clock signals. For example, a shift register unit having four signal output terminals OUT1 to OUT4 and one cascade output terminal CR can receive 12 clock signals Clk1 to Clk12, with three shift register units forming a group to receive these 12 clock signals. As shown in FIG17 , the clock signal terminals CLK1, CLK2, CLK3, CLK4, and CLKCR of the first-stage shift register unit GOA1 receive clock signals Clk1 to Clk5, respectively. The clock signal terminals CLK1, CLK2, CLK3, CLK4, and CLKCR of the second-stage shift register unit GOA2 receive clock signals Clk5 to Clk9, respectively. The clock signal terminals CLK1, CLK2, CLK3, CLK4, and CLKCR of the third-stage shift register unit GOA3 receive clock signals Clk9 to Clk12, respectively. Referring to the signal timing diagrams of the above embodiments, such as the signal timing diagram of FIG. 5 , the shift register units GOA1 , GOA2 , GOA3 , . . . output sequentially shifted output signals G1 , G2 , G3 , G4 , G5 , . . .

[0251] Although the structure of the gate drive circuit is schematically illustrated in the above embodiments using the shift register unit having the input signal terminal IN and the reset signal terminal RST shown in Figures 3 to 4F as an example, the embodiments of the present disclosure are not limited thereto. For the shift register unit having the first input signal terminal IN and the second input signal terminal IN2 as described in Figures 10 to 11B, one of the two can be used as the input signal terminal IN and the other as the reset signal terminal RST to perform cascade connection in the cascade manner as described above.

[0252] In some embodiments, the clock signals Clk1 to Clk12 can be periodic signals with a duty cycle of 1 / 4. The period of the clock signal can be 12H, and the effective level duration can be 3H, where H is the unit scan time, that is, the time required to scan a row of sub-pixels. Adjacent clock signals can be shifted by H. However, the embodiments of the present disclosure are not limited to this, and the number, period and duty cycle of the clock signals can be set as needed. For example, the duty cycle of the clock signal can be set to 33% (1 / 3), 50% (1 / 2), 75% (3 / 4), etc. A corresponding number of output circuits can be set in the shift register unit and a corresponding cascade method can be adopted to generate the required output signal.

[0253] Those skilled in the art will appreciate that the embodiments described above are exemplary and that they may be improved upon. The structures described in the various embodiments may be freely combined without causing any conflict in structure or principle.

[0254] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art will clearly understand that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and that the present disclosure is not limited to the exemplary embodiments described in the specification.< / n>

Claims

1. A shift register unit, comprising: An input circuit, connected to an input signal terminal and a pull-up node of the shift register, for inputting a signal of the input signal terminal to the pull-up node; A control circuit, connected to the pull-up node, a pull-down node, a power supply signal terminal and a reference signal terminal of the shift register unit, the control circuit being configured to provide a signal of one of the power supply signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node; K output circuits, connected to K clock signal terminals, K output signal terminals and the pull-up node of the shift register unit, wherein a first end of the k-th output circuit is connected to the k-th clock signal terminal of the shift register unit, a second end of the k-th signal output circuit is connected to the k-th output signal terminal of the shift register unit, and each output circuit is configured to provide a signal of the first end of the output circuit to the second end of the output circuit under the control of a control terminal of the output circuit, where K is an integer greater than 1, and k = 1, 2,..., K; K' isolation circuits, respectively connected between control terminals of K' output circuits among the K output circuits and the pull-up node, wherein a first end of each isolation circuit is connected to the pull-up node, a second end of the isolation circuit is connected to a control terminal of a corresponding output circuit, a control terminal of the isolation circuit is connected to a control signal terminal, and the isolation circuit is configured to connect or disconnect the first end and the second end of the isolation circuit under the control of a voltage between the control terminal and the second end of the isolation circuit, where K' is a positive integer, and K' ≤ K; A pull-down circuit, connected to the pull-down node, the pull-up node, the K output signal terminals and the reference signal terminal, the pull-down sub-circuit being configured to provide a signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

2. The shift register unit according to claim 1, wherein The K output circuits include a cascaded output circuit and K' signal output circuits, an output signal terminal connected to the cascaded output circuit is configured to be connected to other shift register units, and an output signal terminal connected to the signal output circuit is configured to provide an output signal; Wherein, the K' isolation circuits are respectively connected between control terminals of the K' signal output circuits and the pull-up node.

3. The shift register unit according to claim 1, wherein, The K output circuits include a cascaded output circuit and K' signal output circuits, one of the K' isolation circuits is connected between a control terminal of the cascaded output circuit and the pull-up node, and the remaining K' - 1 isolation circuits are respectively connected between control terminals of K' - 1 signal output circuits and the pull-up node.

4. The shift register unit according to any one of claims 1 to 3, wherein, The isolation circuit includes a first transistor, a gate of the first transistor is connected to the control signal terminal, a first pole of the first transistor serves as the first end of the isolation circuit, and a second pole of the first transistor serves as the second end of the isolation circuit.

5. The shift register unit according to claim 4, wherein, The control signal terminal includes a first control signal terminal and a second control signal terminal, wherein the first control signal terminal is at a first level and the second control signal terminal is at a second level; The isolation circuit further includes a second transistor, wherein the gate of the first transistor is connected to the first control signal terminal, the gate of the second transistor is connected to the second control signal terminal, the first pole of the first transistor and the first pole of the second transistor are connected, and the second pole of the first transistor is connected to the second pole of the second transistor.

6. The shift register unit according to any one of claims 1 to 5, wherein, K = 5, K' = 3, 4 or 5.

7. The shift register unit according to any one of claims 1 to 6, wherein, The output circuit includes: A third transistor, the gate of the third transistor serving as the control terminal of the output circuit, the first pole of the third transistor serving as the first terminal of the output circuit, and the second pole of the third transistor serving as the second terminal of the output circuit; A first capacitor, the first pole of the first capacitor being connected to the gate of the third transistor, and the second pole of the first capacitor being connected to the second pole of the third transistor.

8. The shift register unit according to any one of claims 1 to 7, wherein, The input circuit includes a fourth transistor, the gate of the fourth transistor being connected to the input signal terminal, the first pole of the fourth transistor being connected to the power supply signal terminal, and the second pole of the fourth transistor being connected to the pull-up node; Or The input circuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor being connected to the input signal terminal, the first pole of the fourth transistor being connected to the power supply signal terminal, and the second pole of the fourth transistor being connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the input signal terminal, the first pole of the fifth transistor is connected to the second pole of the fourth transistor, and the second pole of the fifth transistor is connected to the pull-up node.

9. The shift register unit according to any one of claims 1 to 8 further includes: A reset circuit, connected to the reset signal terminal, the pull-up node, and the reference signal terminal of the shift register unit, the reset circuit being configured to provide the signal of the reference signal terminal to the pull-up node under the control of the reset signal terminal.

10. The shift register unit according to claim 9, wherein, The reset circuit includes a sixth transistor, the gate of the sixth transistor being connected to the reset signal terminal, the first pole of the sixth transistor being connected to the reference signal terminal, and the second pole of the sixth transistor being connected to the pull-up node; Or The reset circuit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor being connected to the reset signal terminal, the first pole of the sixth transistor being connected to the reference signal terminal, the second pole of the sixth transistor being connected to the pull-up node through the seventh transistor, the gate of the seventh transistor being connected to the reset signal terminal, the first pole of the seventh transistor being connected to the second pole of the sixth transistor, and the second pole of the seventh transistor being connected to the pull-up node.

11. The shift register unit according to any one of claims 1 to 7, wherein, The input signal terminal includes a first input signal terminal and a first input signal terminal, the control signal terminal includes a first control signal terminal and a second control signal terminal, and the input circuit includes: A first input circuit is connected to the first input signal terminal, a pull-up node, and a first control signal terminal. The first input circuit is configured to provide the signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal; A second input circuit is connected to the second input signal terminal, the pull-up node, and the second control signal terminal. The second input circuit is configured to provide the signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal; Wherein, in the forward scan mode, the first control signal terminal is at a first level and the second control signal terminal is at a second level; in the reverse scan mode, the first control signal terminal is at the second level and the second control signal terminal is at the first level.

12. The shift register unit according to claim 11, wherein, The first input circuit includes: A fourth transistor, the gate of the fourth transistor is connected to the first input signal terminal, the first pole of the fourth transistor is connected to the first control signal terminal, and the second pole of the fourth transistor is connected to the pull-up node.

13. The shift register unit according to claim 12, wherein, The first input circuit further includes: A fifth transistor, the second pole of the fourth transistor is connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the first input signal terminal, the first pole of the fifth transistor is connected to the second pole of the fourth transistor, and the second pole of the fifth transistor is connected to the pull-up node.

14. The shift register unit according to any one of claims 11 to 13, wherein, The second input circuit includes: A sixth transistor, the gate of the sixth transistor is connected to the second input signal terminal, the first pole of the sixth transistor is connected to the second control signal terminal, and the second pole of the sixth transistor is connected to the pull-up node.

15. The shift register unit according to claim 14, wherein, The second input circuit further includes: A seventh transistor, the gate of the seventh transistor is connected to the second control signal terminal, the first pole of the seventh transistor is connected to the second pole of the sixth transistor, and the second pole of the seventh transistor is connected to the pull-up node.

16. The shift register unit according to any one of claims 11 to 15, wherein, The first input circuit includes a fourth transistor, and the second input circuit includes a sixth transistor. The parameters of the fourth transistor are the same as those of the sixth transistor.

17. The shift register unit according to claim 16, wherein, The first input circuit further includes a fifth transistor, and the second input circuit further includes a seventh transistor. The parameters of the fifth transistor are the same as those of the seventh transistor.

18. The shift register unit according to any one of claims 11 to 17 further includes: A first voltage stabilizing circuit is connected to the pull-down node, the second input signal terminal, and the first control signal terminal. The first voltage stabilizing circuit is configured to provide the signal of the first control signal terminal to the pull-down node under the control of the second input signal terminal; A second voltage stabilizing circuit is connected to the pull-down node, the first input signal terminal, and the second control signal terminal. The second voltage stabilizing circuit is configured to provide the signal of the second control signal terminal to the pull-down node under the control of the first input signal terminal.

19. According to the shift register unit of claim 18, wherein, The first voltage stabilizing circuit includes an eighth transistor. The gate of the eighth transistor is connected to the second input signal terminal. The first pole of the eighth transistor is connected to the first control signal terminal. The second pole of the eighth transistor is connected to the pull-down node; The second voltage stabilizing circuit includes a ninth transistor. The gate of the ninth transistor is connected to the first input signal terminal. The first pole of the ninth transistor is connected to the second control signal terminal. The second pole of the ninth transistor is connected to the pull-down node.

20. The shift register unit according to claim 19, wherein, The eighth transistor and the ninth transistor have the same parameters.

21. The shift register unit according to any one of claims 11 to 17 further includes a first voltage stabilizing circuit, a second voltage stabilizing circuit, and an intermediate voltage stabilizing circuit. The first voltage stabilizing circuit and the second voltage stabilizing circuit are connected to the intermediate voltage stabilizing circuit at an intermediate node, wherein: The first voltage stabilizing circuit is connected to the intermediate node, the first input signal terminal, and the first control signal terminal. The first voltage stabilizing circuit is configured to provide the signal of the first control signal terminal to the intermediate node under the control of the first input signal terminal; The second voltage stabilizing circuit is connected to the intermediate node, the second input signal terminal, and the second control signal terminal. The second voltage stabilizing circuit is configured to provide the signal of the second control signal terminal to the intermediate node under the control of the second input signal terminal; The intermediate voltage stabilizing circuit is connected to the pull-down node, the intermediate node, and the reference signal terminal. The intermediate voltage stabilizing circuit is configured to provide the signal of the reference signal terminal to the intermediate node under the control of the pull-down node, and to provide the signal of the reference signal terminal to the pull-down node under the control of the intermediate node.

22. The shift register unit according to claim 21, wherein, The first voltage stabilizing circuit includes an eighth transistor. The second voltage stabilizing circuit includes a ninth transistor. The intermediate voltage stabilizing circuit includes a tenth transistor and an eleventh transistor; Wherein, the gate of the eighth transistor is connected to the first input signal terminal. The first pole of the eighth transistor is connected to the first control signal terminal. The second pole of the eighth transistor is connected to the intermediate node. The gate of the ninth transistor is connected to the second input signal terminal. The first pole of the ninth transistor is connected to the second control signal terminal. The second pole of the ninth transistor is connected to the intermediate node. The gate of the tenth transistor is connected to the intermediate node. The first pole of the tenth transistor is connected to the reference signal terminal. The second pole of the tenth transistor is connected to the pull-down node. The gate of the eleventh transistor is connected to the pull-down node. The first pole of the eleventh transistor is connected to the reference signal terminal. The second pole of the eleventh transistor is connected to the intermediate node.

23. The shift register unit according to any one of claims 1 to 22, wherein The control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, wherein: The gate and the first pole of the twelfth transistor are connected to the power supply signal terminal. The second pole of the twelfth transistor is connected to the gate of the thirteenth transistor; The first pole of the thirteenth transistor is connected to the power supply signal terminal. The second pole of the thirteenth transistor is connected to the pull-down node; The gate of the fourteenth transistor is connected to the pull-up node, the first pole of the fourteenth transistor is connected to the gate of the thirteenth transistor, and the second pole of the fourteenth transistor is connected to the reference signal terminal; The gate of the fifteenth transistor is connected to the pull-up node, the first pole of the fifteenth transistor is connected to the pull-down node, and the second pole of the fifteenth transistor is connected to the reference signal terminal.

24. The shift register unit according to claim 23, wherein, The control circuit further includes: A sixteenth transistor, the second pole of the twelfth transistor is connected to the gate of the thirteenth transistor through the sixteenth transistor, wherein the gate of the sixteenth transistor is connected to the power supply signal terminal, the first pole of the sixteenth transistor is connected to the second pole of the twelfth transistor, and the second pole of the sixteenth transistor is connected to the gate of the thirteenth transistor.

25. The shift register unit according to any one of claims 1 to 24, wherein, The pull-down circuit includes: A first pull-down circuit, connected to the pull-down node, the pull-up node and the reference signal terminal, the first pull-down sub-circuit is configured to provide the signal of the reference signal terminal to the pull-up node under the control of the pull-down node; K second pull-down circuits, respectively connected to the K output signal terminals, wherein each second pull-down circuit is connected to the pull-down node, the reference signal terminal and the corresponding output signal terminal, and is configured to provide the signal of the reference signal terminal to the corresponding output signal terminal under the control of the pull-down node.

26. The shift register unit according to claim 25, wherein, The first pull-down circuit includes a seventeenth transistor, the gate of the seventeenth transistor is connected to the pull-down node, the first pole of the seventeenth transistor is connected to the reference signal terminal, and the second pole of the seventeenth transistor is connected to the pull-up node; Or The first pull-down circuit includes a seventeenth transistor and an eighteenth transistor, the gate of the seventeenth transistor is connected to the pull-down node, the first pole of the seventeenth transistor is connected to the reference signal terminal through the eighteenth transistor, the second pole of the seventeenth transistor is connected to the pull-up node, wherein the gate of the eighteenth transistor is connected to the pull-down node, the first pole of the eighteenth transistor is connected to the reference signal terminal, and the second pole of the eighteenth transistor is connected to the first pole of the seventeenth transistor.

27. The shift register unit according to claim 25 or 26, wherein, The second pull-down circuit includes a nineteenth transistor, the gate of the nineteenth transistor is connected to the pull-down node, the first pole of the nineteenth transistor is connected to the reference signal terminal, and the second pole of the nineteenth transistor is connected to the corresponding output signal terminal.

28. The shift register unit according to any one of claims 1 to 27, further comprising: A total reset circuit, connected to the total reset signal terminal, the pull-up node and the reference signal terminal of the shift register unit, the total reset circuit is configured to provide the signal of the reference signal terminal to the pull-up node under the control of the total reset signal terminal.

29. The shift register unit according to claim 28, wherein, The total reset circuit includes a twentieth transistor. The gate of the twentieth transistor is connected to the total reset signal terminal. The first pole of the twentieth transistor is connected to the reference signal terminal. The second pole of the twentieth transistor is connected to the pull-up node; Or The total reset circuit includes a twentieth transistor and a twenty-first transistor. The gate of the twentieth transistor is connected to the total reset signal terminal. The first pole of the twentieth transistor is connected to the reference signal terminal through the twenty-first transistor. The second pole of the twentieth transistor is connected to the pull-up node. The gate of the twenty-first transistor is connected to the total reset signal terminal. The first pole of the twenty-first transistor is connected to the reference signal terminal. The second pole of the twenty-first transistor is connected to the first pole of the twentieth transistor.

30. The shift register unit according to any one of claims 1 to 29 further comprises: A sensing circuit is connected to the sensing selection signal terminal, the sensing trigger signal terminal, the sensing control node, the input signal terminal, and the pull-up node of the shift register unit. The sensing circuit is configured to write the signal of the input signal terminal to the sensing control node under the control of the sensing selection signal terminal during the display stage, and provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal during the blanking stage.

31. The shift register unit according to claim 30, wherein, The sensing circuit includes: A selection sub-circuit is connected to the sensing selection signal terminal, the sensing control node, and the input signal terminal. The selection sub-circuit is configured to write the signal of the input signal terminal to the sensing control node under the control of the sensing selection signal terminal during the display stage; A trigger sub-circuit is connected to the sensing trigger signal terminal, the sensing control node, and the pull-up node. The trigger sub-circuit is configured to provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal during the blanking stage.

32. The shift register unit according to claim 31, wherein, The selection sub-circuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a second capacitor, where: The gate of the twenty-second transistor is connected to the sensing selection signal terminal. The first pole of the twenty-second transistor is connected to the input signal terminal. The second pole of the twenty-second transistor is connected to the first pole of the twenty-third transistor. The first pole of the twenty-third transistor is connected to the sensing selection signal terminal. The second pole of the twenty-third transistor is connected to the sensing control node. The gate of the twenty-fourth transistor is connected to the sensing control node. The first pole of the twenty-fourth transistor is connected to the second pole of the twenty-second transistor. The second pole of the twenty-fourth transistor is connected to the power supply signal terminal. The first pole of the second capacitor is connected to the power supply signal terminal. The second pole of the second capacitor is connected to the gate of the twenty-fourth transistor.

33. The shift register unit according to claim 31 or 32, wherein, The trigger sub-circuit includes a twenty-fifth transistor and a twenty-sixth transistor. The gate of the twenty-fifth transistor is connected to the sensing control node. The first pole of the twenty-fifth transistor is connected to the power signal terminal. The second pole of the twenty-fifth transistor is connected to the first pole of the twenty-sixth transistor. The gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal. The second pole of the twenty-sixth transistor is connected to the pull-up node; Or The trigger sub-circuit includes a twenty-fifth transistor, a twenty-sixth transistor, and a twenty-seventh transistor. The gate of the twenty-fifth transistor is connected to the sensing control node. The first pole of the twenty-fifth transistor is connected to the power signal terminal. The second pole of the twenty-fifth transistor is connected to the first pole of the twenty-sixth transistor. The gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal. The second pole of the twenty-sixth transistor is connected to the pull-up node through the twenty-seventh transistor. The gate of the twenty-seventh transistor is connected to the sensing trigger signal terminal. The first pole of the twenty-seventh transistor is connected to the second pole of the twenty-sixth transistor. The second pole of the twenty-seventh transistor is connected to the pull-up node.

34. The shift register unit according to any one of claims 31 to 33, wherein, The sensing circuit further includes a voltage stabilizing sub-circuit connected to the sensing control node, the sensing trigger signal terminal, and the reference signal terminal, for providing the signal of the reference signal terminal to the pull-down node under the control of the sensing control node and the sensing trigger signal terminal.

35. The shift register unit according to claim 34, wherein, The voltage stabilizing sub-circuit includes a twenty-eighth transistor and a twenty-ninth transistor. The gate of the twenty-eighth transistor is connected to the sensing trigger signal terminal. The first pole of the twenty-eighth transistor is connected to the pull-up node. The second pole of the twenty-eighth transistor is connected to the first pole of the twenty-ninth transistor. The gate of the twenty-ninth transistor is connected to the sensing control node. The second pole of the twenty-ninth transistor is connected to the reference signal terminal.

36. The shift register unit according to any one of claims 1 to 35 further includes: A third voltage stabilizing circuit is connected to the voltage stabilizing node of the shift register unit, the power signal terminal, and the pull-up node. The third voltage stabilizing circuit is used for providing the signal of the power signal terminal to the voltage stabilizing node under the control of the pull-up node; Wherein, the input circuit of the shift register unit is connected to the voltage stabilizing node.

37. The shift register unit according to claim 36, wherein, The third voltage stabilizing circuit includes a thirtieth transistor and a thirty-first transistor. The gate of the thirtieth transistor is connected to the pull-up node. The first pole of the thirtieth transistor is connected to the power signal terminal. The second pole of the thirtieth transistor is connected to the first pole of the thirty-first transistor. The gate of the thirty-first transistor is connected to the pull-up node. The second pole of the thirty-first transistor is connected to the voltage stabilizing node.

38. The shift register unit according to claim 36 or 37, wherein, The input circuit includes a fourth transistor and a fifth transistor, and the reset circuit includes a sixth transistor and a seventh transistor, or the input circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; Wherein the second pole of the fourth transistor, the first pole of the fifth transistor, the second pole of the sixth transistor, and the first pole of the seventh transistor are connected to the voltage stabilizing node.

39. The shift register unit according to claim 38, wherein, The shift register unit further includes at least one of a pull-down circuit, a total reset circuit, and a sensing circuit, and at least one of the pull-down circuit, the total reset circuit, and the sensing circuit is connected to the regulated voltage node.

40. The shift register unit according to any one of claims 1 to 39 further comprises: A fourth regulated voltage circuit, connected to the pull-down node, the input signal terminal, and the reference signal terminal, for providing the signal of the reference signal terminal to the pull-down node under the control of the input signal terminal.

41. The shift register unit according to claim 40, wherein, The fourth regulated voltage circuit includes: a thirty-second transistor, the gate of the thirty-second transistor is connected to the input signal terminal, the first pole of the thirty-second transistor is connected to the reference signal terminal, and the second pole of the thirty-second transistor is connected to the pull-down node.

42. A shift register unit, comprising: A first input circuit, connected to the first input signal terminal, the pull-up node, and the first control signal terminal of the shift register unit, and the first input circuit is used for providing the signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal; A second input circuit, connected to the second input signal terminal, the pull-up node, and the second control signal terminal of the shift register unit, and the second input circuit is used for providing the signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal; A control circuit, connected to the pull-up node, the pull-down node, the power signal terminal, and the reference signal terminal of the shift register unit, and the control circuit is used for providing the signal of one of the power signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node; K output circuits, connected to the K clock signal terminals, the K output signal terminals, and the pull-up node of the shift register unit, wherein, the control terminal of the k-th output circuit is connected to the pull-up node, the first terminal of the k-th output circuit is connected to the k-th clock signal terminal of the shift register unit, the second terminal of the k-th output circuit is connected to the k-th output signal terminal of the shift register unit, and each output circuit is used for providing the signal of the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit, where K is an integer greater than 1, and k = 1, 2,..., K; A pull-down circuit, connected to the pull-down node, the pull-up node, the K output signal terminals, and the reference signal terminal, and the pull-down circuit is used for providing the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node; Wherein, In the forward scanning mode, the first control signal terminal is at a first level, and the second control signal terminal is at a second level; In the reverse scanning mode, the first control signal terminal is at the second level, and the second control signal terminal is at the first level.

43. A gate driving circuit, comprising a plurality of shift register units as described in any one of claims 1 to 42, and the plurality of shift register units are connected in cascade.

44. A control method for a shift register unit as described in any one of claims 1 to 41, comprising: During the input period, the input circuit inputs the signal at the input signal terminal to the pull-up node, and the control circuit provides the signal at the reference signal terminal to the pull-down node under the control of the pull-up node; During the output period, each of the K output circuits provides the signal at the first end of the output circuit to the second end of the output circuit under the control of the control terminal of the output circuit, so as to generate an output signal at the K output signal terminals based on the signals at the K clock signal terminals; During the reset period, the control circuit provides the signal at the power supply signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal at the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node, wherein, Before the output circuit connected to the k'-th isolation circuit generates an output signal, the signal at the control signal terminal connects the first control terminal and the second control terminal of the k'-th isolation circuit; In response to the output circuit connected to the k'-th isolation circuit generating an output signal, the potential at the control terminal of the k'-th isolation circuit disconnects the first end and the second end of the k'-th isolation circuit, where k' = 1, 2,..., K'.

45. A control method for a shift register unit as claimed in claim 42, comprising: In the forward scan mode, the first control signal terminal is at the first level and the second control signal terminal is at the second level, wherein during the input period, the first input circuit provides the signal at the first control signal terminal to the pull-up node under the control of the first input signal terminal; During the output period, each of the K output circuits provides the signal at the first end of the output circuit to the second end of the output circuit under the control of the control terminal of the output circuit; during the reset period, the second input circuit provides the signal at the second control signal terminal to the pull-up node under the control of the second input signal terminal, the control circuit provides the signal at the reference signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal at the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node; In the reverse scan mode, the first control signal terminal is at the second level and the second control signal terminal is at the first level, wherein during the input period, the second input circuit provides the signal at the second control signal terminal to the pull-up node under the control of the second input signal terminal; During the output period, each of the K output circuits provides the signal at the first end of the output circuit to the second end of the output circuit under the control of the control terminal of the output circuit; during the reset period, the first input circuit provides the signal at the first control signal terminal to the pull-up node under the control of the first input signal terminal, the control circuit provides the signal at the reference signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal at the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

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