Display panel and display device

Abstract

A display panel and a display device. The display panel comprises: a gate drive output line (310) located in a non-display region (B) and connected to a gate drive circuit (1000), the gate drive output line (310) being configured to transmit, during the display panel preparation stage, a gate signal to be detected; a plurality of first-type power supply lines (200) located in the non-display region (B), one first-type power supply line (200) being connected to the end furthest from a multiplexing circuit (100) of each data transmission line (112) among at least two data transmission lines (112); and a first power line (510) located on the side of the gate drive output line (310) furthest from a display region (A). The orthographic projections of the first-type power supply lines (200) on a base substrate (10) are a first projection region, the orthographic projections of the gate drive output line (310) and the first power line (510) on the base substrate (10) are a second projection region, and the first projection region is located within the second projection region. As the gate drive output line (310) and the first power line (510) are both stable signals, the first-type power supply lines (200) are not affected by hopping signals, thereby ensuring the uniformity of display image quality.

Description

Display panel and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display panels (backlight modules) are primarily used in various display devices, such as laptops, flat-screen TVs, mobile phones, automotive dashboards, billboards, and airport terminal displays. To reduce the bezels of display devices, multiplexing circuits are often used to reduce the number of data lines within the bezel, thereby achieving this goal. However, the power supply lines connected to the multiplexing circuits pass over transition signal lines, which can affect the power supply lines and ultimately impact the uniformity of display image quality. Summary of the Invention

[0003] The purpose of this application is to provide a display panel and a display device.

[0004] According to a first aspect of an embodiment of the present application, a display panel is provided, comprising: a base substrate comprising a display area and a non-display area surrounding the display area;

[0005] A plurality of sub-pixels are located in the display area;

[0006] a plurality of data lines, located in the display area and extending to the non-display area, the plurality of data lines being electrically connected to the plurality of sub-pixels;

[0007] A plurality of data transmission lines are located in the non-display area;

[0008] a plurality of multiplexing circuits located in the non-display area, each of the multiplexing circuits comprising a plurality of multiplexing sub-units, one of the plurality of data transmission lines being electrically connected to at least two of the data lines via one of the plurality of multiplexing sub-units, the one multiplexing sub-unit being configured to time-share a data signal transmitted by one of the data transmission lines to the at least two data lines at different time periods;

[0009] a plurality of gate lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to transmit gate signals to the plurality of sub-pixels;

[0010] a gate driving circuit, located in the non-display area and electrically connected to the plurality of gate lines;

[0011] a gate drive output line, located in the non-display area and connected to the gate drive circuit, the gate drive output line being configured to transmit a gate signal to be detected during a display panel preparation stage;

[0012] a plurality of first-type power supply lines, located in the non-display area, wherein one of the first-type power supply lines is connected to an end of each of the at least two data transmission lines that is away from the multiplexing circuit;

[0013] a first power line, located on a side of the gate drive output line away from the display area;

[0014] The orthographic projection of the first type of power supply line on the base substrate is a first projection area, and the orthographic projection of the gate drive output line and the first power supply line on the base substrate is a second projection area;

[0015] The first projection area is located within the second projection area.

[0016] In some embodiments, the extension direction of the first type of power supply line coincides with the extension direction of some line segments in the gate drive output line, and in the direction perpendicular to the extension direction of the first type of power supply line, the orthographic projection of the first type of power supply line on the substrate and the orthographic projection of some line segments in the gate drive output line on the substrate at least partially overlap.

[0017] In some embodiments, the orthographic projection of the first-type power supply line on the substrate is located within a portion of the gate driving output line's orthographic projection on the substrate.

[0018] In some embodiments, along a direction perpendicular to an extension direction of the first-type power supply line, a ratio of a width of the first-type power supply line to a width of a portion of line segments in the gate driving output line is less than or equal to 1.

[0019] In some embodiments, along a direction perpendicular to the extension direction of the first-type power supply line, opposite side boundaries of some line segments of the gate driving output line exceed opposite side boundaries of the corresponding first-type power supply line.

[0020] In some embodiments, the orthographic projection of the first-type power supply line on the substrate coincides with the orthographic projection of a portion of the gate driving output line on the substrate.

[0021] In some embodiments, the orthographic projection of the first type power supply line on the substrate at least partially overlaps with the orthographic projection of some line segments of the first power supply line on the substrate.

[0022] In some embodiments, the orthographic projection of the first type power supply line on the substrate is located within the orthographic projection of the substrate.

[0023] In some embodiments, the multiple data transmission lines include multiple first data transmission lines and multiple second data transmission lines, the multiple first data transmission lines and the multiple second data transmission lines are respectively located on both sides of the multiple first-type power supply lines, and each second data transmission line is connected to at least two first data transmission lines through one of the first-type power supply lines.

[0024] In some embodiments, the plurality of multiplexing circuits include at least a first multiplexing circuit and a second multiplexing circuit, and the first multiplexing circuit and the second multiplexing circuit each include a same number of the plurality of multiplexing subunits;

[0025] The plurality of multiplexing subunits in the first multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the first multiplexing circuit is used as a first line;

[0026] The plurality of multiplexing subunits in the second multiplexing circuit are connected via the first type power supply line, and the first type power supply line connected to the plurality of multiplexing subunits in the second multiplexing circuit is used as a second line;

[0027] The length of the first wire is greater than the length of the second wire; and a ratio of a resistance of the first wire to a resistance of the second wire is used as a first ratio, a ratio of a length of the first wire to a length of the second wire is used as a second ratio, and a ratio of a length of the second wire to a length of the first wire is used as a third ratio;

[0028] The first ratio is smaller than the second ratio, and the first ratio is larger than the third ratio.

[0029] In some embodiments, the resistivity of the first wire is smaller than the resistivity of the second wire, and / or the cross-sectional area of ​​the first wire is smaller than the cross-sectional area of ​​the second wire.

[0030] In some embodiments, the orthographic projection of the second line on the substrate falls within the orthographic projection of the gate drive output line on the substrate, and the orthographic projection area of ​​the first line on the substrate is larger than the orthographic projection area of ​​the gate drive output line on the substrate.

[0031] In some embodiments, the first ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0032] In some embodiments, the gate driving circuit includes a plurality of gate driving sub-circuits, and at least one gate driving sub-circuit of the plurality of gate driving sub-circuits is disposed between two adjacent multiplexing sub-units in the first multiplexing circuit.

[0033] In some embodiments, the display panel further includes a compensation line, the multiple multiplexing circuits include at least a first multiplexing circuit and a second multiplexing circuit, and the first multiplexing circuit and the second multiplexing circuit each include a same number of multiple multiplexing subunits;

[0034] The plurality of multiplexing subunits in the first multiplexing circuit are connected via the first type of power supply line, and the first type of power supply line connected to the plurality of multiplexing subunits in the first multiplexing circuit is used as a first line;

[0035] The plurality of multiplexing subunits in the second multiplexing circuit are connected via the first type power supply line, and the first type power supply line connected to the plurality of multiplexing subunits in the second multiplexing circuit is used as a second line;

[0036] The second line includes a first portion and a second portion;

[0037] The length of the first line is greater than that of the second line, and the compensation line is disposed between the first portion and the second portion and connected to the first portion and the second portion.

[0038] In some embodiments, a ratio of the sum of the length of the compensation line and the length of the second line to the length of the first line is used as a fourth ratio, and the fourth ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0039] In some embodiments, the display device further includes a plurality of light-emitting control lines located in the display area and electrically connected to the plurality of sub-pixels, wherein the plurality of light-emitting control lines are configured to transmit light-emitting control signals to the plurality of sub-pixels;

[0040] a light emitting control circuit, located in the non-display area and electrically connected to the plurality of light emitting control lines;

[0041] a light emitting control output line, located in the non-display area and connected to the light emitting control circuit, wherein the light emitting control output line is configured to transmit a light emitting control signal to be detected during a display panel manufacturing stage;

[0042] a plurality of second-type power supply lines, located in the non-display area, and one second-type power supply line is connected to an end of each of the at least two data transmission lines away from the multiplexing circuit;

[0043] a second power line, located on a side of the light emitting control output line away from the display area;

[0044] The orthographic projection of the second type power supply line on the base substrate is a third projection area, and the orthographic projection of the light emitting control output line and the second power supply line on the base substrate is a fourth projection area;

[0045] The third projection area is located within the fourth projection area.

[0046] In some embodiments, the extension direction of the second type of power supply line coincides with the extension direction of some line segments in the light-emitting control output line, and in the direction perpendicular to the extension direction of the second type of power supply line, the orthographic projection of the second type of power supply line on the substrate and the orthographic projection of some line segments in the light-emitting control output line on the substrate at least partially overlap.

[0047] In some embodiments, the orthographic projection of the second-type power supply line on the base substrate is located within a portion of the light-emitting control output line in the orthographic projection of the base substrate.

[0048] In some embodiments, along a direction perpendicular to an extension direction of the second-type power supply line, a ratio of a width of the second-type power supply line to a width of a portion of line segments in the light-emitting control output line is less than or equal to 1.

[0049] In some embodiments, along a direction perpendicular to the extension direction of the second-type power supply line, opposite side boundaries of some line segments in the light-emitting control output line exceed opposite side boundaries of the corresponding second-type power supply line.

[0050] In some embodiments, the orthographic projection of the second-type power supply line on the base substrate coincides with the orthographic projection of a portion of the light-emitting control output line on the base substrate.

[0051] In some embodiments, the orthographic projection of the second-type power supply line on the substrate at least partially overlaps with the orthographic projection of some line segments of the second power supply line on the substrate.

[0052] In some embodiments, the orthographic projection of the second-type power supply line on the substrate is located within the orthographic projection of the substrate in a portion of the second power supply line.

[0053] In some embodiments, each of the multiplexing circuits includes a first control unit and a second control unit, the first control unit and the second control unit are respectively connected to one of the data lines, and the first control unit and the second control unit share one of the data transmission lines.

[0054] In some embodiments, the multiplexing circuit further includes a third control unit, the first control unit, the second control unit and the third control unit are respectively connected to one of the data lines, and the first control unit, the second control unit and the third control unit share one of the data transmission lines.

[0055] In some embodiments, the plurality of multiplexing circuits include at least a third multiplexing circuit and a fourth multiplexing circuit, and the third multiplexing circuit and the fourth multiplexing circuit each include a same number of the plurality of multiplexing subunits;

[0056] The plurality of multiplexing subunits in the third multiplexing circuit are connected via the second-type power supply line, and the second-type power supply line in the third multiplexing circuit is used as a third line;

[0057] The plurality of multiplexing subunits in the fourth multiplexing circuit are connected via the second-type power supply line, and the second-type power supply line in the fourth multiplexing circuit is used as a fourth line;

[0058] The third line length is greater than the fourth line length; and a ratio of the third line resistance to the fourth line resistance is used as a fifth ratio, a ratio of the third line length to the fourth line length is used as a sixth ratio, and a ratio of the fourth line length to the third line length is used as a seventh ratio;

[0059] The fifth ratio is greater than the seventh ratio, and the fifth ratio is less than the sixth ratio.

[0060] In some embodiments, the resistivity of the third wire is smaller than the resistivity of the fourth wire, and / or the cross-sectional area of ​​the third wire is smaller than the cross-sectional area of ​​the fourth wire.

[0061] In some embodiments, the orthographic projection of the fourth line on the substrate falls within the orthographic projection of the light-emitting control output line on the substrate, and the orthographic projection area of ​​the third line on the substrate is larger than the orthographic projection area of ​​the light-emitting control output line on the substrate.

[0062] In some embodiments, the fifth ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0063] In some embodiments, the display panel further includes a compensation line, the multiple multiplexing circuits include at least a third multiplexing circuit and a fourth multiplexing circuit, and the third multiplexing circuit and the fourth multiplexing circuit each include a same number of multiple multiplexing subunits;

[0064] The plurality of multiplexing subunits in the third multiplexing circuit are connected via the second-type power supply line, and the second-type power supply line connected to the plurality of multiplexing subunits in the third multiplexing circuit is used as a third line;

[0065] The plurality of multiplexing subunits of the fourth multiplexing circuit are connected via the second-type power supply line, and the second-type power supply line connecting the plurality of multiplexing subunits in the fourth multiplexing circuit is used as a fourth line;

[0066] The fourth line includes the third and fourth parts;

[0067] The length of the third line is greater than that of the fourth line, and the compensation line is disposed between the third portion and the fourth portion and connected to the third portion and the fourth portion.

[0068] In some embodiments, a ratio of the sum of the length of the compensation line and the length of the fourth line to the length of the third line is used as an eighth ratio, and the eighth ratio is greater than or equal to 0.8 and less than or equal to 1.2.

[0069] According to a second aspect of the embodiments of the present application, a display device is provided, comprising the display panel as described in the above embodiments.

[0070] The display panel of the present application arranges the first type of power supply line between the gate drive output line, the first power supply line and the part between the two along the orthographic projection of the substrate substrate. Since the gate drive output line and the first power supply line are both stable signals, the first type of power supply line will not be affected by the jump signal, thereby ensuring the uniformity of the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0072] FIG1 is a schematic structural diagram of a display device according to the present application.

[0073] FIG2 is a schematic structural diagram of an exemplary multiplexing circuit at C in FIG1 .

[0074] FIG3 is a schematic structural diagram of a multiplexing circuit at C in FIG1 .

[0075] FIG4 is a schematic structural diagram of another multiplexing circuit at C in FIG1 .

[0076] FIG5 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0077] FIG6 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0078] FIG. 7 is a schematic structural diagram of another multiplexing circuit at E in FIG. 1 .

[0079] FIG8 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0080] FIG9 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0081] FIG10 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0082] FIG11 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0083] FIG12 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0084] FIG13 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0085] FIG14 is a schematic structural diagram of a multiplexing circuit at D in FIG1 .

[0086] FIG15 is a schematic structural diagram of another multiplexing circuit at D in FIG1 .

[0087] FIG16 is a schematic structural diagram of another multiplexing circuit at point F in FIG1 .

[0088] FIG17 is a schematic structural diagram of another multiplexing circuit at F in FIG1 .

[0089] FIG18 is a schematic structural diagram of another multiplexing circuit at F in FIG1 .

[0090] FIG19 is a schematic structural diagram of another multiplexing circuit at F in FIG1 .

[0091] FIG20 is a schematic structural diagram of another multiplexing circuit at point F in FIG1 .

[0092] FIG21 is a schematic structural diagram of another multiplexing circuit at point F in FIG1 .

[0093] FIG22 is a schematic structural diagram of another multiplexing circuit at F in FIG1 .

[0094] FIG23 is a schematic structural diagram of another multiplexing circuit at F in FIG1 .

[0095] FIG24 is a schematic structural diagram of another multiplexing circuit at F in FIG1 .

[0096] FIG. 25 is a cross-sectional view taken along line aa′ of a sub-pixel S in the display area A of FIG. 1 .

[0097] FIG26 is a schematic structural diagram of another multiplexing circuit at E in FIG1 .

[0098] FIG. 27 is a plan view schematically showing the semiconductor layer after forming the multiplexing circuit in FIG. 26 .

[0099] FIG28 is a plan view schematically illustrating the process of forming the first gate metal layer of the multiplexing circuit in FIG26 .

[0100] FIG29 is a plan view schematically showing the second gate metal layer of the multiplexing circuit after it is formed in FIG26 .

[0101] FIG30 is a schematic plan view of FIG26 after forming an insulating layer between multiplexing circuit layers.

[0102] FIG31 is a plan view schematically showing the multiplexing circuit in FIG26 after the first source / drain metal layer is formed. DETAILED DESCRIPTION

[0103] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0104] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. Unless otherwise defined, technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the art to which this application belongs. The use of "a" or "an," and similar terms in this specification and claims does not indicate a limitation of quantity, but rather indicates the presence of at least one. "Multiple" means two or more. "Include" or "comprising," and similar terms mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising," and their equivalents, and do not exclude other elements or objects. "Connected" or "connected," and similar terms are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect. "On" and / or "below," and similar terms are for convenience only and are not limited to a single position or spatial orientation. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0105] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0106] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0107] The use of "adapted to" or "configured to" in this specification is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0108] The triangles, rectangles, trapezoids, pentagons or hexagons used in the specification and claims of this application are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0109] The term "about" as used in the present specification and claims refers to a numerical value that is not strictly limited and allows for process and measurement errors.

[0110] The transistors used in this application can be triodes, thin film transistors, field effect transistors or other devices with the same characteristics. In the embodiments of this application, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0111] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0112] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0113] In an exemplary embodiment, with reference to Figures 1 and 2, Figure 1 is an overall view of the display panel, and Figure 2 is an example view at point C in Figure 1. Narrow-border display panels, such as display panels on wearable products, are often designed to use a multiplexing circuit 100 to reduce the number of data lines 600 on the border, thereby achieving the purpose of reducing the border. The data lines 600 extend from the display area A to the multiplexing circuit 100 in the non-display area B. After passing through the multiplexing circuit 100, the number of the originally large number of data lines 600 is reduced, thereby achieving a reduction in the border. The data lines 600 are used to transmit data signals. The line segment of the data line 600 located in the non-display area B after passing through the multiplexing circuit 100 can also be referred to as a data transmission line (for example, a data transmission line 112), which is used to transmit data signals. As shown in Figure 2, the multiplexing circuit 100 generally includes multiple multiplexing sub-units 110, each of the multiplexing sub-units 110 is connected to multiple data lines 600 and is used to control the pixel units located in the display area A, and the multiple data transmission lines connected to the multiple multiplexing sub-units 110 are interconnected through the first type of power supply line 200.

[0114] The multiplexing subunit 110 includes multiple multiplexing control lines 111, a data transmission line 112 and multiple control units (for example, a first control unit 113, a second control unit 114 and a third control unit 115). The multiple data lines 600, the multiple multiplexing control lines 111 and the data transmission line 112 are electrically connected to a multiplexing subunit 110 respectively. The multiple control units and the multiple multiplexing control lines 111 in a multiplexing subunit 110 are arranged between the gate drive output line 310 and the display area A, and the multiple control units are located on the side of the multiple multiplexing control lines 111 close to the display area A and are located in the non-display area B. The data transmission line 112 spans the multiple multiplexing control lines 111 and is electrically connected to the first type power supply line 200, and one first type power supply line 200 is connected to the multiple data transmission lines 112.

[0115] As shown in Figure 2, the multiplexing subunit 110 has multiple multiplexing control lines 111, wherein the first-type power supply line 200 connects the data transmission lines 112 corresponding to at least two adjacent multiplexing subunits 110. However, because the multiplexing control line 111 is a transition signal line, the first-type power supply line 200 passing over the multiplexing control line 111 may be affected by the transition signal. Therefore, it is necessary to minimize the overlap of the first-type power supply line 200 with the multiplexing control line 111. Furthermore, the first-type power supply line 200 is overlapped with the gate drive output line 310 and / or the first power line 510 to prevent the first-type power supply line 200 from being affected by the transition signal.

[0116] The present application provides a display panel, including: a base substrate 10, multiple sub-pixels S, multiple data lines 600, multiple data transmission lines 112, multiple multiplexing circuits 100, multiple gate lines 1010, a gate driving circuit 1000, a gate driving output line 310, multiple first-class power supply lines 200 and a first power supply line 510. In which, the base substrate 10 includes a display area A and a non-display area B surrounding the display area A; a plurality of sub-pixels S are located in the display area A; a plurality of data lines 600 are located in the display area A and extend to the non-display area B, the plurality of data lines 600 are electrically connected to the plurality of sub-pixels S, and the plurality of data lines 600 are configured to provide data signals to the plurality of sub-pixels S; a plurality of data transmission lines 112 are located in the non-display area B; a plurality of multiplexing circuits 100 are located in the non-display area B, one of the plurality of data transmission lines 112 is electrically connected to at least two of the data lines 600 through a multiplexing sub-unit 110 in the multiplexing circuit 100, and the multiplexing sub-unit 110 is configured to time-share the data signal transmitted by one of the data transmission lines 112 to the at least two data lines 600 at different time periods; a plurality of gate lines 1010 are located in the display area A and electrically connected to the plurality of sub-pixels S, and the plurality of gate lines 1010 are configured to provide data signals to the plurality of The gate drive circuit 1000 is located in the non-display area B and is electrically connected to the multiple gate lines 1010; the gate drive output line 310 is located in the non-display area B and is connected to the gate drive circuit 1000, and the gate drive output line 310 is configured to transmit the gate signal to be tested to an external detection device during the display panel preparation stage; multiple first-class power supply lines 200 are located in the non-display area B, and one first-class power supply line 200 is connected to an end of each of the at least two data transmission lines 112 away from the multiplexing sub-unit 110; the first power line 510 is located on the side of the gate drive output line 310 away from the display area A; wherein the orthographic projection of the first-class power supply line 200 on the base substrate 10 is a first projection area, and the orthographic projection of the gate drive output line 310 and the first power line 510 on the base substrate 10 is a second projection area; the first projection area is located within the second projection area.

[0117] Referring to Figures 3 and 4, the first projection area is the area from the side of the first type of power supply line 200 close to the display area A to the side of the first type of power supply line 200 away from the display area A, and the second projection area is the area from the end of the gate drive output line 310 close to the display area A to the first power line 510 away from the display area A.

[0118] Based on the above description, the first projection area overlaps with the second projection area, for example, the first projection area is located within the second projection area. Since the gate drive output line 310 and the first power line 510 are both stable signals, the first type of power supply line 200 will not be affected by the jump signal, thereby ensuring the uniformity of the display quality.

[0119] Optionally, as shown in FIG4 , the extension direction of the first-type power supply line 200 coincides with the extension direction of some segments of the gate drive output line 310. In a direction perpendicular to the extension direction of the first-type power supply line 200, the orthographic projection of the first-type power supply line 200 on the substrate 10 at least partially overlaps with the orthographic projection of some segments of the gate drive output line 310 on the substrate 10. It should be noted that the extension direction is the direction of travel of the gate drive output line 310 and the first-type power supply line 200 in FIG3 or FIG4 , meaning that their trajectories are substantially the same and substantially parallel. Based on the above description, since the orthographic projection of the first-type power supply line 200 on the substrate 10 at least partially overlaps with the orthographic projection of some segments of the gate drive output line 310 on the substrate 10, during layout design, the first-type power supply line 200 can be arranged close to the gate drive output line 310, thereby reserving more space for other traces provided on the first power line 510.

[0120] Furthermore, referring to FIG6 , the orthographic projection of the first-type power supply line 200 on the base substrate 10 is located within the orthographic projection of a portion of the gate drive output line 310. This means that, along a direction perpendicular to the extension direction of the first-type power supply line 200, the ratio of the width of the first-type power supply line 200 to the width of the portion of the gate drive output line 310 is less than or equal to 1.

[0121] Based on the above setting, the orthographic projection of the first type of power supply line 200 on the base substrate 10 is completely located within the orthographic projection of the gate drive output line 310. Since the gate drive output line 310 is a stable signal, the first type of power supply line 200 will not be affected by the jump signal, thereby ensuring the uniformity of the display quality.

[0122] Continuing with FIG. 6 , along a direction perpendicular to the extension direction of the first-type power supply line 200, the opposing side boundaries of some segments of the gate drive output line 310 extend beyond the opposing side boundaries of their corresponding first-type power supply line 200. This arrangement ensures that the orthographic projection of the first-type power supply line 200 on the substrate 10 is completely within the orthographic projection of some segments of the gate drive output line 310, thereby minimizing interference from transition signals.

[0123] 5 , the orthographic projection of the first-type power supply line 200 on the base substrate 10 coincides with the orthographic projection of a portion of the gate driving output line 310 on the base substrate 10 .

[0124] That is, the first type power supply line 200 is arranged above the gate driving output line 310 along the thickness direction. Such arrangement can free up more area of ​​the base substrate 10 for wiring.

[0125] As shown in FIG7 , the orthographic projection of the first-type power supply line 200 on the base substrate 10 at least partially overlaps with the orthographic projection of a portion of the first power line 510 on the base substrate 10. Because the orthographic projection of the first-type power supply line 200 on the base substrate 10 at least partially overlaps with the orthographic projection of a portion of the first power line 510 on the base substrate 10, during layout design, the first-type power supply line 200 can be placed close to the first power line 510, thereby reserving more space for other routing.

[0126] As shown in FIG8 , the orthographic projection of the first-type power supply line 200 on the base substrate 10 is located within the orthographic projection of a portion of the first power line 510. That is, the first-type power supply line 200 is disposed above the first power line 510 along the thickness direction. This arrangement frees up more area on the base substrate 10 for wiring.

[0127] In one embodiment, referring to Figures 3 to 7, the multiple data transmission lines 112 include multiple first data transmission lines 112a and multiple second data transmission lines 112b. The multiple first data transmission lines 112a and the multiple second data transmission lines 112b are respectively located on both sides of the multiple first-type power supply lines 200. Each second data transmission line 112b is connected to at least two first data transmission lines 112a through one first-type power supply line 200. For example, one first-type power supply line 200 is connected to two or three first data transmission lines 112a.

[0128] Based on the above configuration, one second data transmission line 112b corresponds to multiple first data transmission lines 112a, and the first data transmission line 112a is connected to multiple data lines 600 via a multiplexing subunit 110. This allows multiple data lines 600 to correspond to one first data transmission line 112a, and multiple first data transmission lines 112a to correspond to one second data transmission line 112b. This structure reduces the routing of data signals within the non-display area B. Specifically, multiple data lines 600 are connected to one multiplexing subunit 110, and one multiplexing subunit 110 is connected to one first data transmission line 112a. The number of first data transmission lines 112a is reduced relative to the number of data lines 600, thereby achieving a narrow bezel. Multiple first data transmission lines 112a are connected to one first-type power supply line 200, and one first-type power supply line 200 is connected to one second data transmission line 112b. The number of second data transmission lines 112b is reduced relative to the number of first data transmission lines 112a, thereby achieving a narrow bezel.

[0129] The ratio of the number of the first data transmission lines 112a corresponding to each multiplexing subunit 110 to the number of the plurality of data lines 600 may be 1 / n, where n is an integer greater than or equal to 2, for example, n may be 2, 3, 6, etc. The ratio of the number of the second data transmission lines 112b corresponding to each multiplexing subunit 110 to the number of the plurality of first data transmission lines 112a may be 1 / m, where m is an integer greater than or equal to 2, for example, m may be 2, 3, 4, 5, etc.

[0130] In one embodiment, as shown in FIG5 and FIG9 , the multiplexing circuit 100 includes at least a first multiplexing circuit 410 and a second multiplexing circuit 420. The first multiplexing circuit 410 and the second multiplexing circuit 420 each include an equal number of multiplexing subunits 110. The multiple multiplexing subunits 110 in the first multiplexing circuit 410 are connected via a first-type power supply line 200, with the first-type power supply line 200 connected to the multiple multiplexing subunits 110 in the first multiplexing circuit 410 serving as a first line 210. The multiple multiplexing subunits 110 in the second multiplexing circuit 420 are connected via the first-type power supply line 200, with the first-type power supply line 200 connected to the multiple multiplexing subunits 110 in the second multiplexing circuit 420 serving as a second line 220. The length L1 of the first line is greater than the length L2 of the second line. Furthermore, the resistance of the first wire and the resistance of the second wire are used as a first ratio M1, the ratio of the length L1 of the first wire to the length L2 of the second wire is used as a second ratio M2, and the ratio of the length L2 of the second wire to the length L1 of the first wire is used as a third ratio M3. The first ratio M1 is greater than the third ratio M3, and the first ratio M1 is less than the second ratio M2.

[0131] It should be noted that, referring to Figures 5 and 9 , when the first and second wires 210 and 220 are made of the same material and have the same cross-sectional area S, the cross-sectional area S here refers to the cross-section along the width direction H. The first ratio M1 should be equal to the second ratio M2. In this embodiment, the first ratio M1 is set to be greater than the third ratio M3, and the first ratio M1 is set to be less than the second ratio M2, which means that the values ​​of the first wire resistance R1 and the second wire resistance R2 are closer. For example, if the length L1 of the first wire is set to 2 and the length L2 of the second wire is set to 1, the corresponding second ratio M2 value is 2. The lengths L1 and L2 of the first wire can be in μm or mm, without limitation. Under normal circumstances, the first ratio M1 and the second ratio M2 are equal, so the value of the first ratio M1 is 2 and the value of the third ratio M3 is 1 / 2. Since the first ratio M1 is set to be smaller than the second ratio M2 in this embodiment, the value of the second ratio M2 should be less than 2. There are two ways to reduce the value of the second ratio M2: first, increasing the value of the second resistor R2; second, reducing the value of the first resistor R1. Both methods can reduce the difference between the first and second resistors R1 and R2. However, if the value of the second resistor R2 is increased too much or reduced too little, the difference between the first and second resistors R1 and R2 may increase. For example, if the original value of the first resistor R1 is 2 and the original value of the second resistor R2 is 1. If the value of the second resistor R2 is increased to 5 or the value of the first resistor R1 is reduced to 0.1, although the first ratio M1 is smaller than the second ratio M2, the difference between the first and second resistors R1 and R2 becomes larger. Therefore, by setting the first ratio M1 to be greater than the third ratio M3, the increase in the second resistor R2 and the decrease in the first resistor R1 can only fall within the range where the ratio decreases. For example, the original first line resistance R1 is set to 2, and the original second line resistance R2 is set to 1. Increasing the second line resistance R2 to 2, or reducing the first line resistance R1 to 1, can reduce the difference between the first line resistance R1 and the second line resistance R2. This reduced difference between the first line resistance R1 and the second line resistance R2 compensates for the inconsistent transmission and loading speeds between the two lines caused by the difference in the lengths L1 and L2 of the first line, thereby improving image quality consistency.

[0132] Through extensive experiments, the inventors discovered that when the first ratio M1 is too small or too large, the transmission and loading speeds between the first line 210 and the second line 220 differ significantly, resulting in inconsistent image quality and a poor user experience. In this embodiment, the first ratio M1 is set to be greater than or equal to 0.8 and less than or equal to 1.2. Within this range, the transmission and loading speeds between the first line 210 and the second line 220 are essentially consistent, resulting in a nearly identical visual quality, thus improving the user experience.

[0133] It should be noted that the formula for resistance is R = ρL / S, where R is resistance, S is the cross-sectional area, L is the length, and ρ is the resistivity. Under the premise that the length L1 of the first wire is greater than the length L2 of the second wire, in order to make the value of the first ratio M1 within the range of greater than or equal to 0.8 and less than or equal to 1.2, on the one hand, the resistivity of the first wire 210 can be set to be smaller than the resistivity of the second wire 220. On the other hand, the cross-sectional area of ​​the first wire 210 can be set to be larger than the cross-sectional area of ​​the second wire 220. According to the above formula, it can be seen that, under the premise that other conditions remain unchanged, setting the resistivity of the first wire 210 to be smaller than the resistivity of the second wire 220 can increase the resistance of the first wire 210, thereby making the value of the first ratio M1 closer to 1, and thus making the transmission and loading speeds between the first wire 210 and the second wire 220 closer. Similarly, according to the above formula, under the premise that other conditions remain unchanged, setting the cross-sectional area of ​​the first line 210 to be larger than the cross-sectional area of ​​the second line 220 can reduce the resistance of the first line 210, thereby making the value of the first ratio M1 closer to 1, and thus making the transmission and loading speeds between the first line 210 and the second line 220 close.

[0134] In order to achieve the above purpose, as shown in Figure 6, the orthographic projection of the second line 220 on the base substrate 10 can be set to fall within the orthographic projection of the gate drive output line 310 on the base substrate 10. As shown in Figure 9, the orthographic projection area of ​​the first line 210 on the base substrate 10 is set to be larger than the orthographic projection area of ​​the partial line segment of the gate drive output line 310 on the base substrate 10.

[0135] Through the above configuration, when the first wire 210 and the second wire 220 have the same thickness, it can be seen that the cross-sectional area of ​​the first wire 210 is larger than the cross-sectional area of ​​the second wire 220. According to the formula R = ρL / S, the resistance R2 of the second wire becomes larger than the resistance of the first wire 210, thereby making the value of the first ratio M1 closer to 1, and thus making the transmission and loading speeds between the first wire 210 and the second wire 220 closer.

[0136] 1 and 9 , the gate driver circuit 1000 includes multiple gate driver sub-circuits. Because the length L1 of the first line is greater than the length L2 of the second line, the display panel gate driver sub-circuit can be positioned between two adjacent multiplexing sub-units 110 in the first multiplexing circuit 410. This arrangement fully utilizes the space between the multiplexing sub-units 110, thereby making the non-display area B of the display panel more compact. This, in turn, reduces the display panel frame while providing more functionality for the display panel.

[0137] In one embodiment, as shown in Figures 10, 11, and 12, the second line 220 includes a first portion 221 and a second portion 222. The first line 210 is longer than the second line 220. The compensation line 700 is disposed between the first portion 221 and the second portion 222 and is connected to the first portion 221 and the second portion 222. As a result, the transmission and loading speeds of the connections between the multiplexing subunits 110 of the first multiplexing circuit 410 are slower, while the transmission and loading speeds of the connections between the multiplexing subunits 110 of the second multiplexing circuit 420 are faster. Because the compensation line 700 has a certain resistance, the provision of the compensation line 700 can slow the transmission and loading speeds of the connections between the multiplexing subunits 110 of the second multiplexing circuit 420, thereby bringing the transmission and loading speeds of the connections between the multiplexing subunits 110 of the second multiplexing circuit 420 closer together. This arrangement can change the transmission and loading speeds of the connections between the multiplexing subunits 110 while essentially maintaining the original design.

[0138] 12 , a dummy line 800 may be provided between the first line 210 and the second line 220. The dummy line 800 is not connected to the first line 210 and the second line 220. The provision of the dummy line 800 can avoid a difference in reflectivity caused by a difference in density between the first multiplexing circuit 410 and the second multiplexing circuit 420.

[0139] In this embodiment, when the ratio of the total length of the compensation line 700 and the second line 220 to the length of the first line 210 is too small or too large, the transmission and loading speeds between the first line 210 and the second line 220 differ significantly, resulting in inconsistent image quality and a poor user experience. In this embodiment, the ratio of the total length of the compensation line 700 and the second line 220 to the length of the first line 210 is used as a fourth ratio M4, which is set to be greater than or equal to 0.8 and less than or equal to 1.2. With other conditions remaining unchanged, within this range, the transmission and loading speeds between the first line 210 and the second line 220 are essentially consistent, resulting in nearly identical visual quality, thereby improving the user experience.

[0140] In one embodiment, with reference to FIG1 and FIG14 , the display panel further includes a plurality of light-emitting control lines 1100, a light-emitting control circuit 1200, a light-emitting control output line 320, a plurality of second-type power supply lines 900, and a second power supply line 520. The plurality of light-emitting control lines 1100 are located in the display area A and are electrically connected to the plurality of sub-pixels S. The plurality of light-emitting control lines 1100 are configured to transmit light-emitting control signals to the plurality of sub-pixels S; the light-emitting control circuit 1200 is located in the non-display area B and is electrically connected to the plurality of light-emitting control lines 1100; the light-emitting control output line 320 is located in the non-display area B and is connected to the light-emitting control circuit 1200. The light-emitting control output line 320 is configured to transmit light-emitting control signals to be detected during the display panel preparation stage; the plurality of second-type power supply lines 900 are located in the non-display area B. , and a second-type power supply line 900 is connected to the end of each of the at least two data transmission lines 112 away from the multiplexing circuit 100; the second power supply line 520 is located on the side of the light-emitting control output line 320 away from the display area A; wherein the orthographic projection of the second-type power supply line 900 on the base substrate 10 is a third projection area, and the orthographic projection of the light-emitting control output line 320, the second power supply line 520, and the area between the two on the base substrate 10 is a fourth projection area; the third projection area is located within the fourth projection area. It should be noted that, with reference to FIG1 , the first power supply line 510 and the second power supply line 520 are an integrated structure, and the signals of the first power supply line 510 and the second power supply line 520 are both negative power signal lines (i.e., VSS signal lines).

[0141] As shown in Reference Figure 14, the third projection area is the area from the side of the second type of power supply line 900 close to the display area A to the side of the second type of power supply line 900 away from the display area A, and the fourth projection area is the area from one end of the light-emitting control output line 320 close to the display area A to the area from the second power line 520 away from the display area A.

[0142] Based on the above description, the third projection area overlaps with the fourth projection area, for example, the third projection area is located within the fourth projection area. Since the light-emitting control output line 320 and the second power line 520 are both stable signals, the second power line 520 will not be affected by the jump signal, thereby ensuring the uniformity of the display quality.

[0143] As shown in Figures 14 and 15 , the extension direction of the second-type power supply line 900 coincides with the extension direction of some segments of the light-emission control output line 320. In a direction perpendicular to the extension direction of the second-type power supply line 900, the orthographic projection of the second-type power supply line 900 on the substrate 10 at least partially overlaps with the orthographic projection of some segments of the light-emission control output line 320 on the substrate 10. It should be noted that this overlap in extension direction means that the second-type power supply line 900 and the light-emission control output line 320 have substantially the same trajectory and are substantially parallel to each other.

[0144] Based on the above description, since the orthographic projection of the second-type power supply line 900 on the base substrate 10 at least partially overlaps with the orthographic projection of some line segments in the light-emitting control output line 320 on the base substrate 10, when performing layout design, the second-type power supply line 900 can be arranged close to the light-emitting control output line 320, thereby reserving more space for other routing lines set on the second power supply line 520.

[0145] As shown in FIG17 , the orthographic projection of the second-type power supply line 900 on the base substrate 10 is located within the orthographic projection of a portion of the light-emission control output line 320. This means that, along a direction perpendicular to the extension direction of the second-type power supply line 900, the ratio of the width of the second-type power supply line 900 to the width of the portion of the light-emission control output line 320 is less than or equal to 1.

[0146] Based on the above setting, the orthographic projection of the second type of power supply line 900 on the base substrate 10 is completely located within the orthographic projection of the light-emitting control output line 320. Since the light-emitting control output line 320 is a stable signal, the second type of power supply line 900 will not be affected by the jump signal, thereby ensuring the uniformity of the display image quality.

[0147] As shown in FIG. 17 , along a direction perpendicular to the extension direction of the second-type power supply line 900, the opposing side boundaries of some segments of the light-emitting control output line 320 extend beyond the opposing side boundaries of the corresponding second-type power supply line 900. This arrangement ensures that the orthographic projection of the second-type power supply line 900 on the substrate 10 is completely within the orthographic projection of the segment of the light-emitting control output line 320, thereby minimizing interference from transition signals.

[0148] 16 , the orthographic projection of the second-type power supply line 900 on the base substrate 10 coincides with the orthographic projection of a portion of the light-emitting control output line 320 on the base substrate 10 .

[0149] That is, the second type power supply line 900 is arranged above the light emitting control output line 320 along the thickness direction. Such arrangement can free up more area of ​​the base substrate 10 for wiring.

[0150] As shown in FIG18 , the orthographic projection of the second-type power supply line 900 on the base substrate 10 at least partially overlaps with the orthographic projection of a portion of the second power supply line 520 on the base substrate 10. Because the orthographic projection of the second-type power supply line 900 on the base substrate 10 at least partially overlaps with the orthographic projection of a portion of the second power supply line 520 on the base substrate 10, during layout design, the second-type power supply line 900 can be placed close to the second power supply line 520, thereby reserving more space for other routing lines.

[0151] As shown in FIG19 , the orthographic projection of the second-type power supply line 900 on the base substrate 10 is located within the second power line 520. That is, the second-type power supply line 900 is disposed above the second power line 520 along the thickness direction. This arrangement frees up more area on the base substrate for wiring.

[0152] 2-18 , the multiplexing circuit 100 includes a first control unit 113 and a second control unit 114. The first control unit 113 and the second control unit 114 are each connected to one of the data lines 600, and the first control unit 113 and the second control unit 114 share one first data transmission line 112a. It should be noted that the first control unit 113 and the second control unit 114 may be semiconductor circuits. In this configuration, one first data transmission line 112a corresponds to two data lines 600, reducing the number of first data transmission lines 112a to half the number of data lines 600.

[0153] Furthermore, the multiplexing circuit 100 further includes a third control unit 115. The first control unit 113, the second control unit 114, and the third control unit 115 are each connected to one data line 600. The first control unit 113, the second control unit 114, and the third control unit 115 share one first data transmission line 112a. In this case, one first data transmission line 112a corresponds to three data lines 600, reducing the number of first data transmission lines 112a to one-third of the number of data lines 600.

[0154] The above three data lines 600 can be respectively connected to at least three columns of sub-pixels in the display area A. For example, among the three data lines 600, the first data line 600 is connected to a column of red sub-pixels and blue sub-pixels, and the red sub-pixels and the blue sub-pixels can be arranged alternately in the column direction, the second data line 600 is connected to a column of green sub-pixels, and the third data line 600 is connected to a column of red sub-pixels and blue sub-pixels, and the red sub-pixels and the blue sub-pixels can be arranged alternately in the column direction.

[0155] It should be noted that the sub-pixels here can be white sub-pixels, red sub-pixels, blue sub-pixels, and green sub-pixels, and the multiplexing sub-unit 110 is connected to four data lines 600. These four data lines 600 are connected to the red sub-pixels, blue sub-pixels, green sub-pixels, and white sub-pixels to control the red sub-pixels, blue sub-pixels, green sub-pixels, and white sub-pixels. In addition, the sub-pixels can also include any one or more of the red sub-pixels, blue sub-pixels, and green sub-pixels, and the multiplexing sub-unit 110 is connected to the data line 600 that matches it, so that one multiplexing sub-unit 110 controls one data line. The arrangement of this embodiment can make corresponding connections more convenient, as well as adjusting data and control more convenient.

[0156] In one embodiment, as shown in FIG16 and FIG20 , the multiplexing circuit 100 includes at least a third multiplexing circuit 430 and a fourth multiplexing circuit 440. The third multiplexing circuit 430 and the fourth multiplexing circuit 440 each include an equal number of multiplexing subunits 110. The multiple multiplexing subunits 110 in the third multiplexing circuit 430 are connected via the second-type power supply line 900, with the second-type power supply line 900 connected to the multiple multiplexing subunits 110 in the third multiplexing circuit 430 serving as a third line 910. The multiple multiplexing subunits 110 in the fourth multiplexing circuit 440 are connected via the second-type power supply line 900, with the second-type power supply line 900 connected to the multiple multiplexing subunits 110 in the fourth multiplexing circuit 430 serving as a fourth line 920. The length L3 of the third line is greater than the length L4 of the fourth line. Furthermore, a ratio of the third line resistance R3 to the fourth line resistance R4 is used as a fifth ratio M5, a ratio of the third line length L3 to the fourth line length L4 is used as a sixth ratio M6, and a ratio of the fourth line length L4 to the third line length L3 is used as a seventh ratio M7. The fifth ratio M5 is greater than the seventh ratio M7, and the fifth ratio M5 is less than the sixth ratio M6.

[0157] It should be noted that, if the third wire 910 and the fourth wire 920 are made of the same material and have the same cross-sectional area S, the fifth ratio M5 should be equal to the sixth ratio M6. In this embodiment, the fifth ratio M5 is set to be greater than the seventh ratio M7 and smaller than the sixth ratio M6, which means that the values ​​of the third wire resistance R3 and the fourth wire resistance R4 are closer. For example, if the length L3 of the third wire is set to 2 and the length L4 of the fourth wire is set to 1, the corresponding value of the sixth ratio M6 is 2. Under normal circumstances, the fifth ratio M5 and the sixth ratio M6 are equal, so the value of the fifth ratio M5 is 2, and the value of the seventh ratio M7 is 1 / 2. Since the fifth ratio M5 is set to be smaller than the sixth ratio M6 in this embodiment, the value of the sixth ratio M6 should be less than 2. There are two ways to reduce the value of the fifth ratio M5: first, increasing the value of the fourth resistor R4; second, decreasing the value of the third resistor R3. Both methods can reduce the difference between the third and fourth resistors R3 and R4. However, if the value of the fourth resistor R4 is increased too much or decreased too little, the difference between the third and fourth resistors R3 and R4 may increase. For example, if the original value of the third resistor R3 is set to 2 and the original value of the fourth resistor R4 is set to 1. If the value of the fourth resistor R4 is increased to 5 or the value of the third resistor R3 is decreased to 0.1, although the fifth ratio M5 is smaller than the sixth ratio M6, the difference between the third and fourth resistors R3 and R4 becomes larger. Therefore, by setting the fifth ratio M5 to be greater than the seventh ratio M7, the increase in the value of the fourth resistor R4 and the decrease in the value of the third resistor R3 can only fall within the range where the ratio decreases. For example, if the original value of the third resistor R3 is set to 2 and the original value of the fourth resistor R4 is set to 1. Increasing the value of the third line resistor R3 to 2 or reducing it to 1 can reduce the difference between the third line resistor R3 and the fourth line resistor R4. This reduced difference between the third line resistor R3 and the fourth line resistor R4 compensates for the inconsistent transmission and loading speeds between the two lines caused by the difference in the lengths L3 and L4 of the third line, thereby improving image quality consistency.

[0158] Through extensive experiments, the inventors discovered that when the fifth ratio M5 is too small or too large, the transmission and loading speeds between the third line 910 and the fourth line 920 differ significantly, resulting in inconsistent image quality and a poor user experience. In this embodiment, the fifth ratio M5 is set to be greater than or equal to 0.8 and less than or equal to 1.2. Within this range, the transmission and loading speeds between the third line 910 and the fourth line 920 are substantially consistent, resulting in a nearly uniform visual quality, thus improving the user experience.

[0159] It should be noted that the formula for resistance is R=ρL / S, where R is resistance, S is cross-sectional area, L is length, and ρ is resistivity. Under the premise that the length L3 of the third line is greater than the length L4 of the fourth line, in order to make the value of the fifth ratio M5 greater than or equal to 0.8 and less than or equal to 1.2, on the one hand, the resistivity of the third line 910 can be set to be smaller than the resistivity of the fourth line 920. On the other hand, the cross-sectional area of ​​the third line 910 can be set to be larger than the cross-sectional area of ​​the fourth line 920. According to the above formula, it can be seen that under the premise that other conditions remain unchanged, setting the resistivity of the third line 910 to be smaller than the resistivity of the fourth line 920 can increase the resistance of the third line 910, thereby making the value of the fifth ratio M5 closer to 1, and thus making the transmission and loading speeds between the third line 910 and the fourth line 920 close. Similarly, according to the above formula, under the premise that other conditions remain unchanged, setting the cross-sectional area of ​​the third line 910 to be larger than the cross-sectional area of ​​the fourth line 920 can reduce the resistance of the third line 910, thereby making the value of the fifth ratio M5 closer to 1, and thus making the transmission and loading speeds between the third line 910 and the fourth line 920 close.

[0160] In order to achieve the above purpose, as shown in Figure 17, the orthographic projection of the fourth line 920 on the base substrate 10 can be set to fall within the orthographic projection of the light-emitting control output line 320 on the base substrate 10. As shown in Figure 20, the orthographic projection area of ​​the third line 910 on the base substrate 10 is set to be larger than the orthographic projection area of ​​the partial line segment of the light-emitting control output line 320 on the base substrate 10.

[0161] Through the above settings, when the third wire 910 and the fourth wire 920 have the same thickness, it can be seen that the cross-sectional area of ​​the third wire 910 is larger than the cross-sectional area of ​​the fourth wire 920. According to the formula R=ρL / S, the resistance R4 of the fourth wire is larger than the resistance of the third wire 910, thereby making the value of the fifth ratio M5 closer to 1, and thus making the transmission and loading speeds between the third wire 910 and the fourth wire 920 closer.

[0162] 1 and 20 , the light control circuit 1200 includes multiple light control sub-circuits. Because the length L3 of the third line is greater than the length L4 of the fourth line, the light control sub-circuit can be positioned between two adjacent multiplexing sub-units 110 in the third multiplexing circuit 430. This arrangement fully utilizes the space between the multiplexing sub-units 110, thereby making the non-display area B of the display panel more compact. This, in turn, reduces the overall bezel of the display panel while providing more functionality for the display panel.

[0163] In one embodiment, as shown in Figures 21, 22, and 23, the fourth line 920 includes a third portion 921 and a fourth portion 922, and is connected to the third portion 921 and the fourth portion 922. The length of the third line 910 is greater than that of the fourth line 920, and the compensation line 700 is disposed between the third portion 921 and the fourth portion 922. Because the transmission and loading speeds of the connections between the multiplexing subunits 110 of the third multiplexing circuit 430 are slower, the transmission and loading speeds of the connections between the multiplexing subunits 110 of the fourth multiplexing circuit 440 are faster. Because the compensation line 700 has a certain resistance, the provision of the compensation line 700 can slow down the transmission and loading speeds of the connections between the multiplexing subunits 110 of the fourth multiplexing circuit 440, thereby bringing the transmission and loading speeds of the connections between the multiplexing subunits 110 of the fourth multiplexing circuit 440 closer together. Such a configuration can change the transmission and loading speed of the connection between the multiplexing sub-units 110 while substantially not changing the original design of other parts.

[0164] 23 , a dummy line 800 may be provided between the third line 910 and the fourth line 920. The dummy line 800 is not connected to the third line 910 and the fourth line 920. The provision of the dummy line 800 can avoid a reflectivity difference caused by a density difference between the third multiplexing circuit 430 and the fourth multiplexing circuit 440.

[0165] In this embodiment, when the ratio of the total length of the compensation line 700 and the fourth line 920 to the length of the third line 910 is too small or too large, the transmission and loading speeds between the third line 910 and the fourth line 920 differ significantly, resulting in inconsistent image quality and a poor user experience. In this embodiment, the ratio of the total length of the compensation line 700 and the fourth line 920 to the length of the third line 910 is used as an eighth ratio M8, which is set to be greater than or equal to 0.8 and less than or equal to 1.2. With other conditions remaining unchanged, within this range, the transmission and loading speeds between the third line 910 and the fourth line 920 are essentially consistent, resulting in nearly identical visual quality, thereby improving the user experience.

[0166] FIG25 is a schematic partial cross-sectional view of the display region of a display panel according to at least one embodiment of the present disclosure. The cross-sectional view a-a' of a sub-pixel in the display region of FIG1 is used as an example for illustration. In this example, the multiple transistors in the sub-pixel circuit are of the same type. For example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors or oxide thin-film transistors.

[0167] In some examples, as shown in FIG25 , in a direction perpendicular to the display panel, the display area of ​​the display panel may include: a base substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, an encapsulation structure layer 14, and a touch structure layer 15 sequentially disposed on the base substrate 10. The display structure layer may include at least: a circuit structure layer 12 and a light-emitting structure layer 13. The circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. The light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels.

[0168] In some examples, FIG25 illustrates a sub-pixel including a thin film transistor 21 and a capacitor 22 as an example. In some examples, the circuit structure layer 12 of the display area may include: a semiconductor layer 25, a first gate metal layer 26, a second gate metal layer 27, a first source / drain metal layer 29, and a second source / drain metal layer 30, disposed on the base substrate 10. A first gate insulating layer 101 may be disposed between the semiconductor layer 25 and the first gate metal layer 26, a second gate insulating layer 102 may be disposed between the first gate metal layer 26 and the second gate metal layer 27, an interlayer insulating layer 103 may be disposed between the second gate metal layer 27 and the first source / drain metal layer 29, a passivation layer 104 and a first planarizing layer 105 may be disposed between the first source / drain metal layer 29 and the second source / drain metal layer 30, and a second planarizing layer 106 may be disposed on the side of the second source / drain metal layer 30 away from the base substrate 10. Among them, the first gate insulating layer 101, the second gate insulating layer 102, the interlayer insulating layer 103 and the passivation layer 104 can be inorganic insulating layers, and the first flat layer 105 and the second flat layer 106 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be provided on the side of the semiconductor layer 25 close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also increase the adhesion of the film layer in the display panel to the substrate. In other examples, the passivation layer can be omitted between the first source and drain metal layer 29 and the second source and drain metal layer 30, and only the first flat layer can be provided. In other examples, the second source and drain metal layer 30 and the second flat layer can be omitted.

[0169] In some examples, as shown in FIG. 25 , the semiconductor layer 25 in the display area may include at least the active layer 210a of the thin-film transistor 21. The active layer 210a of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer 26 may include at least the gate electrode 213 of the thin-film transistor 21 and the first plate 221a of the capacitor 22. The orthographic projection of the gate electrode 213 of the thin-film transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the active layer 210a on the substrate 10. The second gate metal layer 27 may include at least the second plate 222a of the capacitor 22. The orthographic projections of the second plate 222a and the first plate 221a of the capacitor 22 on the substrate 10 may at least partially overlap, for example, they may coincide. The first source / drain metal layer 29 may include at least the first electrode 211 and the second electrode 212 of the thin-film transistor 21. The interlayer insulating layer 103 may have multiple vias 28 (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210a. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210a. The first electrode 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210a through the first pixel via, and the second electrode 212 may be electrically connected to the second region 2102 of the active layer 210a through the second pixel via. The second source-drain metal layer 30 may include at least an anode connection electrode 23. The anode connection electrode 23 can be connected to the second electrode 212 of the thin film transistor 21 through a via formed in the passivation layer 104 and the first planar layer 105. In some examples, the gate line 1010 of the display area can be located in the first gate metal layer 26, and the data line and high-potential power supply line of the display area can be located in the second source-drain metal layer 30. However, this embodiment is not limited to this. In other examples, the second source-drain metal layer 30 can be omitted, and the data line and high-potential power supply line of the display area can be located in the first source-drain metal layer 29.

[0170] In some examples, as shown in FIG25 , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the second planar layer 106 and electrically connected to the anode connection electrode 23 through a pixel via provided in the second planar layer 106. The pixel definition layer 134 is disposed on the first electrode 131 and the second planar layer 106. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light-emitting layer 132 and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0171] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and one or more of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0172] In some examples, the light-emitting layers of light-emitting elements emitting light of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0173] In some examples, as shown in FIG25 , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, and the second encapsulation layer 142 may be made of organic materials. The second encapsulation layer 142 may be disposed between the first encapsulation layer 141 and the third encapsulation layer 143 to prevent external water vapor from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0174] Referring to Figures 26 to 31, Figures 27 to 31 are diagrams of the manufacturing process of the display panel, wherein Figure 27 is a plan view schematic diagram after the semiconductor layer 25 of the multiplexing circuit is formed in Figure 26. Figure 28 is a plan view schematic diagram after the first gate metal layer 26 of the multiplexing circuit 100 is formed in Figure 26. The first gate metal layer 26 may include at least: the gate electrode 213 of the thin film transistor 21 located in the sub-pixel S in the display area, and the first electrode plate 221a of the capacitor 22. Figure 29 is a plan view schematic diagram after the second gate metal layer 27 of the multiplexing circuit 100 is formed in Figure 26. The second gate metal layer 27 may include at least: the second electrode plate 222a of the capacitor 22 located in the sub-pixel S in the display area. Figure 30 is a plan view schematic diagram of Figure 26 showing that multiple vias 28 can be opened in the display area of ​​the interlayer insulating layer 103. 31 is a plan view schematically illustrating the multiplexing circuit 100 after forming the first source / drain metal layer 29 in FIG. 26 . The first source / drain metal layer 29 may include at least a first electrode 211 and a second electrode 212 of the thin film transistor 21 located in the sub-pixel S in the display area.

[0175] In some examples, as shown in Figures 26-31, the active layers of the nine multiplexing transistors of the multiplexing circuit 100 are located in the semiconductor layer 25. The active layer of each multiplexing transistor may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The channel region 2100 is the region blocked by the transistor gate. For example, the first active layer M10 of the first multiplexing transistor M1 includes the first region 2101, the second region 2102, and the channel region 2100 located between the first region 2101 and the second region 2102. The channel region 2100 is the region where the orthographic projection of the gate M13 of the first multiplexing transistor M1 on the substrate overlaps with the orthographic projection of the first active layer M10 on the substrate. The third active layer M30 of the third multiplexing transistor M3, the second active layer M20 of the second multiplexing transistor M2, the first active layer M10 of the first multiplexing transistor M1, the fourth active layer M40 of the fourth multiplexing transistor M4, the fifth active layer M50 of the fifth multiplexing transistor M5, the sixth active layer M60 of the sixth multiplexing transistor M6, the seventh active layer M70 of the seventh multiplexing transistor M7, the eighth active layer M80 of the eighth multiplexing transistor M8, and the ninth active layer M90 of the ninth multiplexing transistor M9 can be arranged in sequence along the first direction X. Among them, the second active layer M20 and the third active layer M30 can be an integrated structure connected to each other, the fifth active layer M50 and the sixth active layer M60 can be an integrated structure connected to each other, and the eighth active layer M80 and the ninth active layer M90 can be an integrated structure connected to each other, thereby reducing the occupied space of the multiplexing circuit 100. However, this embodiment is not limited to this. For example, the active layers of the nine multiplexing transistors can be independently provided.

[0176] In some examples, as shown in Figures 25-30, the gates of the nine multiplexing transistors of the multiplexing circuit 100 can be located in the first gate metal layer 26. The orthographic projection of the gate of each multiplexing transistor on the substrate can cover the orthographic projection of the channel region 2100 of the corresponding active layer on the substrate. The gate M13 of the first multiplexing transistor M1, the gate M23 of the second multiplexing transistor M2, the gate M33 of the third multiplexing transistor M3, the gate M43 of the fourth multiplexing transistor M4, the gate M53 of the fifth multiplexing transistor M5, the gate M63 of the sixth multiplexing transistor M6, the gate M73 of the seventh multiplexing transistor M7, the gate M83 of the eighth multiplexing transistor M8, and the gate M93 of the ninth multiplexing transistor M9 can all extend along the second direction Y and be arranged in sequence along the first direction X.

[0177] In some examples, as shown in Figures 26-31, the first and second electrodes of the nine multiplexing transistors of the multiplexing circuit 100 can be located on the first source-drain metal layer 29. The first electrode M21 of the second multiplexing transistor M2 can also serve as the first electrode M31 of the third multiplexing transistor M3. The first electrode M21 can be electrically connected to the data transmission line 112. The second electrode M22 of the second multiplexing transistor M2 and the second electrode M32 of the third multiplexing transistor M3 are respectively connected to different data lines 600. The first electrode M11 of the first multiplexing transistor M1 can be connected to the first region 2101 of the first active layer M10 of the first multiplexing transistor M1 through multiple vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101. The second electrode M12 of the first multiplexing transistor M1 can be connected to the second region 2102 of the first active layer M10 of the first multiplexing transistor M1 through multiple vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101. The first electrode M11 of the first multiplexing transistor M1 can also be electrically connected to the data transmission line 112 located in the second gate metal layer 27 through a via hole defined in the interlayer insulating layer 103. The second electrode M12 of the first multiplexing transistor M1 can also be electrically connected to the data line 600 located in the first gate metal layer 26 through a via hole defined in the interlayer insulating layer 103 and the second gate insulating layer 102.

[0178] In some examples, the second electrode M12 of the first multiplexing transistor M1 can be connected to the second region 2102 of the first active layer M10 of the first multiplexing transistor M1 through a plurality of vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through a via defined in the interlayer insulating layer 103 and the second gate insulating layer 102. The second electrode M22 of the second multiplexing transistor M2 can be connected to the second region 2102 of the second active layer M20 of the second multiplexing transistor M2 through a plurality of vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through a via defined in the interlayer insulating layer 103. The second electrode M32 of the third multiplexing transistor M3 can be connected to the second region 2102 of the third active layer M30 through multiple vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through vias opened in the interlayer insulating layer 103 and the second gate insulating layer 102.

[0179] In some examples, the first electrode M51 of the fifth multiplexing transistor M5 can also serve as the first electrode M61 of the sixth multiplexing transistor M6. The first electrode M41 of the fourth multiplexing transistor M4 can be connected to the first region 2101 of the fourth active layer M40 of the fourth multiplexing transistor M4 through multiple vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data transmission line 112 located in the second gate metal layer 27 through a via defined in the interlayer insulating layer 103.

[0180] In some examples, the second electrode M42 of the fourth multiplexing transistor M4 can be connected to the second region 2102 of the fourth active layer M40 of the fourth multiplexing transistor M4 through a plurality of vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through a via defined in the interlayer insulating layer 103. The second electrode M52 of the fifth multiplexing transistor M5 can be connected to the second region 2102 of the fifth active layer M50 of the fifth multiplexing transistor M5 through a plurality of vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through a via defined in the interlayer insulating layer 103 and the second gate insulating layer 102. The second electrode M62 of the sixth multiplexing transistor M6 can be connected to the second region 2102 of the sixth active layer M60 through multiple vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through the vias opened in the interlayer insulating layer 103.

[0181] In some examples, the first electrode M81 of the eighth multiplexing transistor M8 can also serve as the first electrode of the ninth multiplexing transistor M9. The first electrode M71 of the seventh multiplexing transistor M7 can be connected to the first region 2101 of the seventh active layer M70 of the seventh multiplexing transistor M7 through multiple vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101. The first electrode M71 can also be electrically connected to the data transmission line 112 located in the second gate metal layer 27 through vias defined in the interlayer insulating layer 103.

[0182] In some examples, the second electrode M72 of the seventh multiplexing transistor M7 can be connected to the second region 2102 of the first active layer M70 of the seventh multiplexing transistor M7 through a plurality of vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through a via defined in the interlayer insulating layer 103 and the second gate insulating layer 102. The second electrode M82 of the eighth multiplexing transistor M8 can be connected to the second region 2102 of the eighth active layer M80 of the eighth multiplexing transistor M8 through a plurality of vias 28 defined in the interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the second gate metal layer 27 through a via defined in the interlayer insulating layer 103. The second electrode M92 of the ninth multiplexing transistor M9 can be connected to the second region 2102 of the ninth active layer M90 through multiple vias 28 opened in the interlayer insulating layer 103, the second gate insulating layer 102 and the first gate insulating layer 101, and can also be electrically connected to the data line 600 located in the first gate metal layer 26 through vias opened in the interlayer insulating layer 103 and the second gate insulating layer 102.

[0183] In some examples, as shown in Figures 25-30, multiple data lines 600 may be alternately arranged in the first gate metal layer 26 and the second gate metal layer 27. Multiple data transmission lines 112 may be alternately arranged in the first gate metal layer 26 and the second gate metal layer 27. This embodiment is not limited to this.

[0184] In some examples, as shown in Figures 26-31, the gate M13 of the first multiplexing transistor M1 can be electrically connected to the first multiplexing control line 1111 through a via hole defined in the interlayer insulating layer 103 and the second gate insulating layer 102. The gate M23 of the second multiplexing transistor M2 can be electrically connected to the second multiplexing control line 1112. The gate M33 of the third multiplexing transistor M3 can be electrically connected to the third multiplexing control line 1113. The gate M43 of the fourth multiplexing transistor M4 can be electrically connected to the fourth multiplexing control line 1114. The gate M53 of the fifth multiplexing transistor M5 can be electrically connected to the fifth multiplexing control line 1115. The gate M63 of the sixth multiplexing transistor M6 can be electrically connected to the sixth multiplexing control line 1116. The gate M73 of the seventh multiplexing transistor M7 can be electrically connected to the seventh multiplexing control line 1117. The gate M83 of the eighth multiplexing transistor M8 can be electrically connected to the eighth multiplexing control line 1118. A gate M93 of the ninth multiplexing transistor M9 may be electrically connected to a ninth multiplexing control line 1119 .

[0185] In some examples, the ninth multiplexing control line 1119, the eighth multiplexing control line 1118, the seventh multiplexing control line 1117, the sixth multiplexing control line 1116, the fifth multiplexing control line 1115, the fourth multiplexing control line 1114, the third multiplexing control line 1113, the second multiplexing control line 1112, and the first multiplexing control line 1111 can be located on the first source-drain metal layer 29. A third low-voltage lead line 577, a second scan clock second lead line 834, a first scan clock second lead line 824, and a third high-voltage lead line 587 can be disposed on a side of a group of multiplexing control lines 111 close to the multiplexing circuit 100; the third low-voltage lead line 577, the second scan clock second lead line 834, the first scan clock second lead line 824, and the third high-voltage lead line 587 can be disposed sequentially in a direction away from the multiplexing circuit 100. A gate driving output line 310 may be provided on a side of the group of multiplexing control lines 111 away from the multiplexing circuit 100 .

[0186] In some examples, the third low-voltage lead-out line 577 can be electrically connected to the first low-voltage lead-out line, and the third low-voltage lead-out line 577 can provide a first voltage signal to the gate drive circuit in the left frame area. The third high-voltage lead-out line 587 can be electrically connected to the first high-voltage lead-out line, and the third high-voltage lead-out line 587 can provide a second voltage signal to the gate drive circuit in the left frame area. The first scan clock second lead-out line 824 can be electrically connected to the first scan clock lead-out line, and the second scan clock second lead-out line 834 can be electrically connected to the second scan clock lead-out line. The first scan clock second lead-out line 824 and the second scan clock second lead-out line 834 can provide scan clock signals to the gate drive circuit. The gate drive output line 310 can be electrically connected to the first scan output lead-out line.

[0187] The structure of the multiplexing circuit 100 disposed in the right area of ​​the first power line 510 is similar to that of the multiplexing circuit 100 disposed in the left area, and therefore will not be described in detail here.

[0188] The present application also provides a display device comprising the display panel described in the above embodiments. Because the display device comprises the display panel described in the above embodiments, the display device also possesses the functions and advantages of the display panel. The display device can be an electronic device with a display function, such as a mobile phone, computer, or tablet computer.

[0189] In this application, the structural embodiments and method embodiments may complement each other if they do not conflict.

[0190] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of their solutions) can be used in combination with each other. For example, those of ordinary skill in the art may use other embodiments when reading the above description. In addition, in the above-mentioned specific embodiments, various features can be grouped together to simplify the application. This should not be interpreted as an intention that the features of an application that does not require protection are necessary for any claim. On the contrary, the subject matter of the present application may be less than all the features of the embodiments of a specific application. Thus, the following claims are incorporated into the specific embodiments as examples or embodiments, wherein each claim is independently a separate embodiment, and it is considered that these embodiments can be combined with each other in various combinations or arrangements. The scope of the present application should be determined with reference to the appended claims and the full scope of equivalents to which these claims are entitled.

[0191] This application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this application, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0192] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0193] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The terms "plurality" and "several" refer to two or more, unless otherwise clearly defined.

[0194] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the disclosure of this application. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of this application are indicated by the following claims.

[0195] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display panel, characterized in that, Comprising: A substrate substrate, including a display area and a non-display area surrounding the display area; A plurality of sub-pixels, located in the display area; A plurality of data lines, located in the display area and extending to the non-display area, the plurality of data lines being electrically connected to the plurality of sub-pixels; A plurality of data transmission lines, located in the non-display area; A plurality of multiplexing circuits, located in the non-display area, each multiplexing circuit including a plurality of multiplexing sub-units, one data transmission line among the plurality of data transmission lines being electrically connected to at least two of the data lines through one multiplexing sub-unit among the plurality of multiplexing sub-units, the one multiplexing sub-unit being configured to time-divisionally transmit the data signal transmitted by one data transmission line to the at least two data lines at different time periods; A plurality of gate lines, located in the display area and electrically connected to the plurality of sub-pixels, the plurality of gate lines being configured to transmit gate signals to the plurality of sub-pixels; A gate driving circuit, located in the non-display area and electrically connected to the plurality of gate lines; A gate driving output line, located in the non-display area and connected to the gate driving circuit, the gate driving output line being configured to transmit a gate signal to be detected during the display panel manufacturing stage; A plurality of first type power supply lines, located in the non-display area, and one first type power supply line being connected to one end of each data transmission line among at least two data transmission lines away from the multiplexing circuit; A first power supply line, located on a side of the gate driving output line facing away from the display area; Wherein, the orthographic projection of the first type power supply line on the substrate substrate is a first projection area, and the orthographic projections of the gate driving output line and the first power supply line on the substrate substrate are a second projection area; The first projection area is located within the second projection area.

2. The display panel according to claim 1, wherein The extending direction of the first type power supply line coincides with the extending direction of a part of the line segments of the gate driving output line. Along the direction perpendicular to the extending direction of the first type power supply line, the orthographic projection of the first type power supply line on the substrate substrate and the orthographic projection of a part of the line segments of the gate driving output line on the substrate substrate at least partially overlap.

3. The display panel according to claim 2, wherein The orthographic projection of the first type power supply line on the substrate substrate is located within the orthographic projection of a part of the line segments of the gate driving output line on the substrate substrate.

4. The display panel according to claim 2, wherein Along the direction perpendicular to the extending direction of the first type power supply line, the ratio of the width of the first type power supply line to the width of a part of the line segments of the gate driving output line is less than or equal to 1.

5. The display panel according to claim 2, wherein Along the direction perpendicular to the extending direction of the first type power supply line, the two side boundaries of a part of the line segments of the gate driving output line extend beyond the two side boundaries of the corresponding first type power supply line.

6. The display panel according to claim 2, characterized in that, The orthographic projection of the first type power supply line on the substrate substrate coincides with the orthographic projection of a part of the line segments of the gate driving output line on the substrate substrate.

7. The display panel according to claim 1, wherein The orthographic projection of the first type power supply line on the substrate substrate and the orthographic projection of a part of the line segments of the first power supply line on the substrate substrate at least partially overlap.

8. The display panel according to claim 7, characterized in that, The orthographic projection of the first type power supply line on the substrate substrate is located within the orthographic projection of a part of the line segments of the first power supply line on the substrate substrate.

9. The display panel according to claim 1, characterized in that, The multiple data transmission lines include multiple first data transmission lines and multiple second data transmission lines. The multiple first data transmission lines and the multiple second data transmission lines are respectively located on two sides of the multiple first-type power supply lines. Each second data transmission line is connected to at least two first data transmission lines through one of the first-type power supply lines.

10. The display panel according to claim 1, characterized in that, The multiple multiplexing circuits at least include a first multiplexing circuit and a second multiplexing circuit. Both the first multiplexing circuit and the second multiplexing circuit include the same number of multiple multiplexing sub-units. The multiple multiplexing sub-units in the first multiplexing circuit are connected through the first-type power supply lines. The first-type power supply lines connected to the multiple multiplexing sub-units in the first multiplexing circuit are used as the first line. The multiple multiplexing sub-units in the second multiplexing circuit are connected through the first-type power supply lines. The first-type power supply lines connected to the multiple multiplexing sub-units in the second multiplexing circuit are used as the second line. The length of the first line is greater than the length of the second line. And, the ratio of the resistance of the first line to the resistance of the second line is used as the first ratio, the ratio of the length of the first line to the length of the second line is used as the second ratio, and the ratio of the length of the second line to the length of the first line is used as the third ratio. Wherein, the first ratio is less than the second ratio, and the first ratio is greater than the third ratio.

11. The display panel according to claim 10, wherein The resistivity of the first line is less than the resistivity of the second line, and / or the cross-sectional area of the first line is less than the cross-sectional area of the second line.

12. The display panel according to claim 10, wherein The orthographic projection of the second line on the substrate falls within the orthographic projection of the gate driving output line on the substrate, and the orthographic projection area of the first line on the substrate is greater than the orthographic projection area of the gate driving output line on the substrate.

13. The display panel according to claim 10, characterized in that, The first ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

14. The display panel according to claim 10, characterized in that, The gate driving circuit includes multiple gate driving sub-circuits. At least one gate driving sub-circuit among the multiple gate driving sub-circuits is disposed between two adjacent multiplexing sub-units in the first multiplexing circuit.

15. The display panel according to claim 1, wherein The display panel further includes a compensation line. The multiple multiplexing circuits include a first multiplexing circuit and a second multiplexing circuit. Both the first multiplexing circuit and the second multiplexing circuit include the same number of multiple multiplexing sub-units. The multiple multiplexing sub-units in the first multiplexing circuit are connected through the first-type power supply lines. The first-type power supply lines connected to the multiple multiplexing sub-units in the first multiplexing circuit are used as the first line. The multiple multiplexing sub-units in the second multiplexing circuit are connected through the first-type power supply lines. The first-type power supply lines connected to the multiple multiplexing sub-units in the second multiplexing circuit are used as the second line. The second line includes a first part and a second part. The length of the first line is greater than the length of the second line. The compensation line is disposed between the first part and the second part and is connected to the first part and the second part.

16. The display panel according to claim 15, characterized in that, Taking the ratio of the sum of the length of the compensation line and the length of the second line to the length of the first line as a fourth ratio, the fourth ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

17. The display panel according to claim 1, characterized in that, It further includes a plurality of light-emitting control lines located in the display area and electrically connected to the plurality of sub-pixels, and the plurality of light-emitting control lines are configured to transmit light-emitting control signals to the plurality of sub-pixels; A light-emitting control circuit located in the non-display area and electrically connected to the plurality of light-emitting control lines; A light-emitting control output line located in the non-display area and connected to the light-emitting control circuit, and the light-emitting control output line is configured to transmit a light-emitting control signal to be detected during the display panel manufacturing stage; A plurality of second-type power supply lines located in the non-display area, and one second-type power supply line is connected to one end of each data transmission line among at least two data transmission lines far from the multiplexing circuit; A second power supply line located on a side of the light-emitting control output line away from the display area; Wherein, the orthographic projection of the second-type power supply line on the substrate is a third projection area, and the orthographic projections of the light-emitting control output line and the second power supply line on the substrate are a fourth projection area; The third projection area is located within the fourth projection area.

18. The display panel according to claim 17, wherein, The extending direction of the second-type power supply line coincides with the extending direction of a part of the line segments of the light-emitting control output line. Along the direction perpendicular to the extending direction of the second-type power supply line, the orthographic projection of the second-type power supply line on the substrate at least partially overlaps with the orthographic projection of a part of the line segments of the light-emitting control output line on the substrate.

19. The display panel according to claim 17, wherein The orthographic projection of the second-type power supply line on the substrate is located within the orthographic projection of a part of the line segments of the light-emitting control output line on the substrate.

20. The display panel according to claim 17, characterized in that, Along the direction perpendicular to the extending direction of the second-type power supply line, the ratio of the width of the second-type power supply line to the width of a part of the line segments of the light-emitting control output line is less than or equal to 1.

21. The display panel according to claim 17, wherein Along the direction perpendicular to the extending direction of the second-type power supply line, the two opposite side boundaries of a part of the line segments of the light-emitting control output line exceed the two opposite side boundaries of the corresponding second-type power supply line.

22. The display panel according to claim 17, wherein The orthographic projection of the second-type power supply line on the substrate coincides with the orthographic projection of a part of the line segments of the light-emitting control output line on the substrate.

23. The display panel according to claim 17, characterized in that, The orthographic projection of the second-type power supply line on the substrate at least partially overlaps with the orthographic projection of a part of the line segments of the second power supply line on the substrate.

24. The display panel according to claim 23, characterized in that, The orthographic projection of the second-type power supply line on the substrate is located within the orthographic projection of a part of the line segments of the second power supply line on the substrate.

25. The display panel according to claim 1, wherein Each of the multiplexing circuits includes a first control unit and a second control unit. The first control unit and the second control unit are respectively connected to one data line, and the first control unit and the second control unit share one data transmission line.

26. The display panel according to claim 25, wherein, The multiplexing circuit further includes a third control unit. The first control unit, the second control unit, and the third control unit are respectively connected to one of the data lines, and the first control unit, the second control unit, and the third control unit share one data transmission line.

27. The display panel according to claim 17, wherein The plurality of multiplexing circuits at least include a third multiplexing circuit and a fourth multiplexing circuit. Both the third multiplexing circuit and the fourth multiplexing circuit include the same number of multiplexing sub-units. The multiplexing sub-units in the third multiplexing circuit are connected by the second type of power supply line, and the second type of power supply line connected to the multiplexing sub-units in the third multiplexing circuit is used as the third line. The multiplexing sub-units in the fourth multiplexing circuit are connected by the second type of power supply line, and the second type of power supply line in the fourth multiplexing circuit is used as the fourth line. The length of the third line is greater than the length of the fourth line; and, the ratio of the resistance of the third line to the resistance of the fourth line is used as the fifth ratio, the ratio of the length of the third line to the length of the fourth line is used as the sixth ratio, and the ratio of the length of the fourth line to the length of the third line is used as the seventh ratio. Wherein, the fifth ratio is greater than the seventh ratio, and the fifth ratio is less than the sixth ratio.

28. The display panel according to claim 27, wherein, The resistivity of the third line is less than the resistivity of the fourth line, and / or, the cross-sectional area of the third line is less than the cross-sectional area of the fourth line.

29. The display panel according to claim 27, wherein, The orthographic projection of the fourth line on the substrate falls within the orthographic projection of the light emission control output line on the substrate, and the orthographic projection area of the third line on the substrate is greater than the orthographic projection area of the light emission control output line on the substrate.

30. The display panel according to claim 27, wherein, The fifth ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

31. The display panel according to claim 17, wherein, The display panel further includes a compensation line. The plurality of multiplexing circuits at least include a third multiplexing circuit and a fourth multiplexing circuit. Both the third multiplexing circuit and the fourth multiplexing circuit include the same number of multiplexing sub-units. The multiplexing sub-units in the third multiplexing circuit are connected by the second type of power supply line, and the second type of power supply line connected to the multiplexing sub-units in the third multiplexing circuit is used as the third line. The multiplexing sub-units of the fourth multiplexing circuit are connected by the second type of power supply line, and the second type of power supply line connecting the multiplexing sub-units in the fourth multiplexing circuit is used as the fourth line. The fourth line includes a third part and a fourth part. The length of the third line is greater than the length of the fourth line, and the compensation line is disposed between the third part and the fourth part and connected to the third part and the fourth part.

32. The display panel according to claim 31, wherein The ratio of the sum of the length of the compensation line and the length of the fourth line to the length of the third line is used as the eighth ratio. The eighth ratio is greater than or equal to 0.8 and less than or equal to 1.

2.

33. A display device, characterized in that, The display device includes the display panel according to any one of claims 1-32.

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