Display substrate and driving method therefor, and display apparatus

Abstract

A display substrate and a driving method therefor, and a display apparatus. The display substrate comprises: a data unit, pixel driving circuits arranged in an array, a plurality of first scanning signal lines, and a plurality of data signal lines. In a refresh frame of at least one display frame, when the pixel driving circuit at the i-th row and j-th column performs display, the data unit is configured to, in a first time period, provide an effective level signal to the first scanning signal line connected to the pixel driving circuit at the i-th row and j-th column and provide a first data signal to the data signal line connected to the pixel driving circuit at the i-th row and j-th column; and in a second time period, provide the effective level signal to the first scanning signal line connected to the pixel driving circuit at the i-th row and j-th column and provide a second data signal to the data signal line connected to the pixel driving circuit at the i-th row and j-th column, wherein the first time period is before the second time period; and in the first time period, a voltage value of a signal of a second node is greater than a voltage value of a signal of a first node.

Description

Display substrate, driving method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 3, 2024, with application number 202410010285.0 and invention name “Display substrate, driving method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a driving method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a display substrate, wherein content displayed by the display substrate includes multiple display frames, at least one display frame includes a refresh frame, the display substrate includes a data unit, a pixel driving circuit arranged in an array, a plurality of first scan signal lines, and a plurality of data signal lines, the at least one pixel driving circuit includes a driving transistor and a writing transistor, the driving transistor being respectively connected to a first node and a second node, and the writing transistor being respectively electrically connected to the first scan signal line, the data signal line, and the second node;

[0006] In a refresh frame of at least one display frame, when the pixel driving circuit in the i-th row and j-th column displays, the data unit is configured to provide an effective level signal to a first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and provide a first data signal to a data signal line connected to the pixel driving circuit in the i-th row and j-th column in a first time period, and to provide an effective level signal to the first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and provide a second data signal to the data signal line connected to the pixel driving circuit in the i-th row and j-th column in a second time period, wherein the first time period occurs before the second time period;

[0007] During the first time period, the voltage value of the signal of the second node is greater than the voltage value of the signal of the first node, the first data signal is the data signal corresponding to the pixel driving circuit of the kth row and jth column, and the second data signal is the data signal corresponding to the pixel driving circuit of the ith row and jth column, k is at least one value less than i, 1≤i≤M, 1≤j≤N, M is the total number of rows of pixel driving circuits, and N is the total number of columns of pixel driving circuits.

[0008] In an exemplary embodiment, there is a gap between the end time of the first time period and the start time of the second time period.

[0009] In an exemplary embodiment, further comprising: a plurality of second scan signal lines, at least one pixel driving circuit further comprising: a compensation transistor, the driving transistor being further connected to the third node, the compensation transistor being electrically connected to the second scan signal line, the first node, and the third node respectively;

[0010] The data unit is further configured to provide an invalid level signal to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column in a third time period, and provide a valid level signal to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column in a fourth time period;

[0011] The end time of the third time period is the start time of the fourth time period, the first time period and the third time period at least partially overlap, and the second time period and the fourth time period at least partially overlap.

[0012] In an exemplary embodiment, the duration of the third time period is greater than the duration of the first time period, and the duration of the fourth time period is greater than the duration of the second time period;

[0013] The first time period is within the third time period, and the second time period is within the fourth time period.

[0014] In an exemplary embodiment, the data unit is further configured to provide a valid level signal to the second scan signal line connected to the pixel driving circuit in the i-th row and j-th column in a fifth time period, the fifth time period occurs before the third time period, and the end time of the fifth time period is the start time of the third time period.

[0015] In an exemplary embodiment, further comprising: a plurality of first reset signal lines, at least one pixel driving circuit further comprising: a first reset transistor, the first reset transistor being connected to the first reset signal line and the third node respectively;

[0016] The data unit is further configured to provide an active level signal to the first reset signal line connected to the pixel driving circuit in the i-th row and j-th column in a sixth time period, and the sixth time period at least partially overlaps with the fifth time period.

[0017] In an exemplary embodiment, the duration of the fifth time period is greater than the duration of the sixth time period, and the sixth time period is within the fifth time period.

[0018] In an exemplary embodiment, further comprising: a plurality of second reset signal lines, at least one pixel driving circuit further comprising: a second reset transistor and a third reset transistor, the second reset transistor being connected to the second reset signal line and the fourth node, respectively, and the third reset transistor being connected to the second reset signal line and the second node, respectively;

[0019] The data unit is further configured to provide an active level signal to the second reset signal line connected to the pixel driving circuit in the i-th row and j-th column in a seventh time period, wherein the seventh time period occurs after the fourth time period.

[0020] In an exemplary embodiment, there is a gap between the end time of the fourth time period and the start time of the seventh time period.

[0021] In an exemplary embodiment, the data unit is further configured to provide an invalid level signal to the first reset signal line and the second reset signal line connected to the i-th row and j-th column pixel driving circuit in a third time period and a fourth time period, provide an invalid level signal to the first scan signal line and the second reset signal line connected to the i-th row and j-th column pixel driving circuit in a fifth time period, and provide an invalid level signal to the first scan signal line, the second scan signal line, and the first reset signal line connected to the i-th row and j-th column pixel driving circuit in a seventh time period.

[0022] In an exemplary embodiment, the data unit is further configured to provide an inactive level signal to the first scan signal line, the second scan signal line, the first reset signal line, and the second reset signal line connected to the pixel driving circuit in the i-th row and j-th column in an eighth time period.

[0023] In an exemplary embodiment, the present invention further includes: a plurality of light emitting signal lines, at least one pixel driving circuit including: a first light emitting transistor and a second light emitting transistor, the first light emitting transistor being connected to the light emitting signal line and the second node, respectively, and the second light emitting transistor being connected to the light emitting signal line and the third node, respectively;

[0024] The data unit is further configured to provide a valid level signal to the light-emitting signal line connected to the pixel driving circuit in the i-th row and j-th column in a ninth time period, and provide an invalid level signal to the first scan signal line, the second scan signal line, the first reset signal line, and the second reset signal line connected to the pixel driving circuit in the i-th row and j-th column, and provide an invalid level signal to the light-emitting signal line connected to the pixel driving circuit in the i-th row and j-th column in a third time period, a fourth time period, a fifth time period, a seventh time period, and an eighth time period, wherein the ninth time period occurs after the eighth time period.

[0025] In an exemplary embodiment, the present invention further comprises: a plurality of light emitting signal lines, a plurality of first reset signal lines, a plurality of second reset signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, a plurality of second scanning signal lines, and a plurality of first power supply lines; and at least one pixel driving circuit further comprises: a compensation transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first light emitting transistor, a second light emitting transistor, and a capacitor;

[0026] The control electrode of the compensation transistor is connected to the second scanning signal line, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the third node;

[0027] The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node;

[0028] The control electrode of the write transistor is connected to the first scan signal line, the first electrode of the write transistor is connected to the data signal line, and the second electrode of the write transistor is connected to the second node;

[0029] The control electrode of the first reset transistor is connected to the first reset signal line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the third node;

[0030] The control electrode of the second reset transistor is connected to the second reset signal line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the fourth node;

[0031] The control electrode of the third reset transistor is connected to the second reset signal line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the second node;

[0032] The control electrode of the first light emitting transistor is connected to the light emitting signal line, the first electrode of the first light emitting transistor is connected to the first power line, and the second electrode of the first light emitting transistor is connected to the second node;

[0033] The control electrode of the second light emitting transistor is connected to the light emitting signal line, the first electrode of the second light emitting transistor is connected to the third node, and the second electrode of the second light emitting transistor is connected to the fourth node;

[0034] One end of the capacitor is connected to the first power line, and the other end of the capacitor is connected to the first node.

[0035] In an exemplary embodiment, at least one transistor in at least one pixel driving circuit is a P-type transistor or an N-type transistor, the first light-emitting transistor and the second light-emitting transistor are of the same transistor type, and the second reset transistor and the third reset transistor are of the same transistor type.

[0036] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0037] In a third aspect, the present disclosure further provides a method for driving a display substrate, configured to drive the display substrate, the method comprising:

[0038] In a first time period, an effective level signal is provided to a first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and a first data signal is provided to a data signal line connected to the pixel driving circuit in the i-th row and j-th column;

[0039] In the second time period, an effective level signal is provided to the first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and a second data signal is provided to the data signal line connected to the pixel driving circuit in the i-th row and j-th column. The first time period occurs before the second time period.

[0040] In an exemplary embodiment, the method further comprises:

[0041] In a third time period, an invalid level signal is provided to the second scanning signal line, the first reset signal line, the second reset signal line and the light emitting signal line connected to the pixel driving circuit in the i-th row and the j-th column;

[0042] In a fourth time period, a valid level signal is provided to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and an invalid level signal is provided to the first reset signal line, the second reset signal line, and the light emitting signal line connected to the pixel driving circuit in the i-th row and j-th column;

[0043] In a fifth time period, a valid level signal is provided to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and an invalid level signal is provided to the first scanning signal line, the second reset signal line, and the light emitting signal line connected to the pixel driving circuit in the i-th row and j-th column;

[0044] providing an effective level signal to the first reset signal line connected to the pixel driving circuit in the i-th row and j-th column in a sixth time period;

[0045] In the seventh time period, a valid level signal is provided to the second reset signal line connected to the pixel driving circuit in the i-th row and j-th column, and an invalid level signal is provided to the first scanning signal line, the second scanning signal line, the first reset signal line and the light emitting signal line;

[0046] In an eighth time period, an invalid level signal is provided to the first scanning signal line, the second scanning signal line, the first reset signal line, the second reset signal line and the light emitting signal line connected to the pixel driving circuit in the i-th row and the j-th column;

[0047] In a ninth time period, a valid level signal is provided to the light emitting signal line connected to the pixel driving circuit in the i-th row and the j-th column, and an invalid level signal is provided to the first scanning signal line, the second scanning signal line, the first reset signal line, and the second reset signal line connected to the pixel driving circuit in the i-th row and the j-th column;

[0048] The first time period and the third time period at least partially overlap, the second time period and the fourth time period at least partially overlap, the fifth time period occurs before the third time period, the sixth time period at least partially overlaps with the fifth time period, the seventh time period occurs after the fourth time period, the eighth time period occurs after the seventh time period, and the ninth time period occurs after the eighth time period.

[0049] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0050] Summary of the Figures

[0051] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0052] FIG1 is a schematic structural diagram of a display substrate;

[0053] FIG2A is a schematic diagram of a planar structure of a display substrate;

[0054] FIG2B is a second schematic diagram of a planar structure of a display substrate;

[0055] FIG2C is a third schematic diagram of a planar structure of a display substrate;

[0056] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0057] FIG4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate provided by an embodiment of the present disclosure;

[0058] FIG5 is a timing diagram of the operation of the pixel driving circuit provided in FIG4 ;

[0059] FIG6 is a schematic diagram of the operation of the pixel driving circuit in the first stage;

[0060] FIG7 is a schematic diagram of the operation of the pixel driving circuit in the second stage;

[0061] FIG8 is a schematic diagram of the operation of the pixel driving circuit in the third stage;

[0062] FIG9 is a schematic diagram of the operation of the pixel driving circuit in the fourth stage;

[0063] FIG10 is a schematic diagram of the operation of the pixel driving circuit in the fifth stage;

[0064] FIG11 is a schematic diagram showing the operation of the pixel driving circuit in the sixth stage.

[0065] Details

[0066] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0067] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0068] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0069] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0070] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0071] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0072] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0073] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0074] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0075] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0076] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0077] Figure 1 is a schematic diagram of the structure of a display substrate. As shown in Figure 1, the display substrate may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to multiple data signal lines, the scan driver is connected to multiple scan signal lines, and the light-emitting driver is connected to multiple light-emitting signal lines. The pixel array may include multiple sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, a clock signal and a scan start signal suitable for the specifications of the scan driver to the scan driver, and a clock signal and an emission stop signal suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines. For example, a data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines in units of pixel rows. A scan driver can generate scan signals to be provided to scan signal lines by receiving clock signals, scan start signals, and the like from a timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to the scan signal lines. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal to generate scan signals. A light-emitting driver can generate emission signals to be provided to light-emitting signal lines by receiving clock signals, emission stop signals, and the like from a timing controller. For example, the light-emitting driver can sequentially provide emission signals having off-level pulses to the light-emitting signal lines. For example, the light-emitting driver can be configured as a shift register and can sequentially transmit emission stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal to generate emission signals.

[0078] Figure 2A is a schematic diagram of a planar structure of a display substrate (I), Figure 2B is a schematic diagram of a planar structure of a display substrate (II), and Figure 2C is a schematic diagram of a planar structure of a display substrate (III). As shown in Figures 2A to 2C, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P includes a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2 and the third subpixel P3 are respectively connected to the pixel driving circuits of the subpixels, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of the subpixels.

[0079] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0080] In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a diamond, a pentagon, or a hexagon, which is not limited in the present disclosure.

[0081] In an exemplary embodiment, a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a herringbone pattern, without limitation in this disclosure. FIG2A illustrates an example in which a pixel unit includes three sub-pixels arranged horizontally, while FIG2B illustrates an example in which a pixel unit includes three sub-pixels arranged in a herringbone pattern.

[0082] In an exemplary embodiment, a pixel unit may include four sub-pixels, which may be arranged horizontally, vertically, in a square, or in a diamond pattern, etc., which is not limited in this disclosure. FIG2C illustrates an example in which a pixel unit includes four sub-pixels, and the four sub-pixels are arranged in a square pattern.

[0083] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0084] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels on the display substrate. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0085] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. FIG3 shows only one transistor 101 and one capacitor 101A as an example. The light-emitting structure layer 103 may include an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of the corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0086] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and metal foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0087] In an exemplary embodiment, the organic light-emitting layer 303 may include a light-emitting layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0088] In an exemplary embodiment, the touch structure layer of each sub-pixel may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be connected to the bridging electrode through a via.

[0089] The pixel driving circuit in the display substrate includes: a driving transistor. When the pixel driving circuit drives the light-emitting device to emit light, due to the influence of the previous display frame, the driving transistor is in a negative bias state for a long time, so that the brightness of the display substrate cannot reach the required brightness when the current display frame is displayed, resulting in an afterimage on the display substrate, affecting the display effect of the display substrate.

[0090] Figure 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate provided in an embodiment of the present disclosure, and Figure 5 is an operating timing diagram of the pixel driving circuit provided in Figure 4. The present disclosure provides a display substrate, wherein the content displayed by the display substrate includes multiple display frames, at least one display frame includes a refresh frame, and the display substrate includes a data unit, an array-arranged pixel driving circuit, a plurality of first scan signal lines Gate1, and a plurality of data signal lines Data.

[0091] In an exemplary embodiment, as shown in Figures 4 and 5, at least one pixel driving circuit includes: a driving transistor T3 and a writing transistor T4, wherein the driving transistor T3 is respectively connected to a first node N1 and a second node N2, and the writing transistor T4 is respectively electrically connected to a first scanning signal line Gate1, a data signal line Data, and a second node N2. In a refresh frame of at least one display frame, when the pixel driving circuit in the i-th row and j-th column displays, the data unit is configured to provide an active-level signal to the first scanning signal line Gate1 connected to the pixel driving circuit in the i-th row and j-th column, and provide a first data signal to the data signal line Data connected to the pixel driving circuit in the i-th row and j-th column during a first time period t1, and to provide an active-level signal to the first scanning signal line Gate1 connected to the pixel driving circuit in the i-th row and j-th column, and provide a second data signal to the data signal line Data connected to the pixel driving circuit in the i-th row and j-th column during a second time period t2, wherein the first time period t1 occurs before the second time period t2.

[0092] In the first time period t1, the voltage value of the signal of the second node N2 is greater than the voltage value of the signal of the first node N1, the first data signal is the data signal corresponding to the pixel driving circuit of the kth row and jth column, and the second data signal is the data signal corresponding to the pixel driving circuit of the ith row and jth column, k is at least one value less than i, 1≤i≤M, 1≤j≤N, M is the total number of rows of pixel driving circuits, and N is the total number of columns of pixel driving circuits.

[0093] Here, k may be greater than or equal to i-1 and less than or equal to i-8.

[0094] In the first time period t1 , the voltage value of the signal at the second node N2 is greater than the voltage value of the signal at the first node N1 , that is, the driving transistor is in a bias state.

[0095] In an exemplary embodiment, if the image displayed by the display frame is a low grayscale image, the data voltage of the data signal corresponding to the pixel driving circuit in the i-1th row and jth column is relatively high, that is, the voltage value of the signal at the second node N2 will be much greater than the voltage value of the signal at the first node N1, which will cause the bias voltage applied to the driving transistor to be relatively large, thereby improving the influence of the previous display frame on the characteristics of the driving transistor. If the image displayed by the display frame is a high grayscale image, the data voltage of the data signal corresponding to the pixel driving circuit in the i-1th row and jth column is relatively low, but the voltage value of the signal at the second node N2 will still be greater than the voltage value of the signal at the first node N1, thereby causing the bias voltage applied to the driving transistor to be relatively small, thereby still improving the influence of the previous display frame on the characteristics of the driving transistor.

[0096] In an exemplary embodiment, an active level signal of a signal line refers to a signal that can turn on a transistor connected to the signal line, and an inactive level signal of a signal line refers to a signal that can turn off a transistor connected to the signal line.

[0097] In an exemplary embodiment, the data unit may be a scan driver, which is not limited in the present disclosure.

[0098] The display substrate provided by the embodiments of the present disclosure includes a first drive mode and a second drive mode. The refresh rate of the first drive mode is lower than that of the second drive mode. For example, the refresh rate of the first drive mode can be 1 Hz to 120 Hz, while the refresh rate of the second drive mode can be 120 Hz to 480 Hz. The content displayed by the display substrate includes multiple display frames. In the first drive mode, the display frames include a refresh frame and at least one hold frame. In the second drive mode, the display frames include only the refresh frame.

[0099] In an exemplary embodiment, the first driving mode may be referred to as a low-frequency driving mode, and the second driving mode may be referred to as a high-frequency driving mode.

[0100] In an exemplary embodiment, the refresh rate refers to the number of times a display substrate refreshes data in one second. The refresh rate in the first drive mode configured for the same display substrate is fixed, while the refresh rate in the first drive mode configured for different display substrates may vary. For example, the refresh rate in the first drive mode may be approximately 10 Hz.

[0101] In an exemplary embodiment, to reduce product power consumption, the display substrate employs a first drive mode and a second drive mode to alternately display data. In the first drive mode, the display substrate refreshes display data during a refresh frame and maintains the display data refreshed during a hold frame. In the second drive mode, a display frame may include a refresh frame but not a hold frame. In the second drive mode, the display substrate refreshes display data during a refresh frame.

[0102] In an exemplary embodiment, the second time period t2 provides a data signal corresponding to the i-th row and j-th column pixel driving circuit to the data signal line Data connected to the i-th row and j-th column pixel driving circuit, that is, the time period in which the second time period t2 is located can be called the data writing stage of the i-th row and j-th column pixel driving circuit.

[0103] The present disclosure writes a first data signal in a first time period t1 that occurs before a second time period t2, so that the voltage value of the signal at the second node N2 is greater than the voltage value of the signal at the first node N1, thereby achieving a bias state, i.e., a positive bias state, for the driving transistor. This can improve the influence of the previous display frame of the current display frame on the driving transistor, avoid afterimages on the display substrate, and enhance the display effect of the display substrate.

[0104] As shown in FIG4 , the pixel driving circuit may include eight transistors (a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a writing transistor T4 , a first light emitting transistor T5 , a second light emitting transistor T6 , a second reset transistor T7 and a third reset transistor T4 ) and a capacitor Cst.

[0105] In an exemplary embodiment, the display substrate may further include: a plurality of second scan signal lines Gate2, a plurality of first reset signal lines Reset1, a plurality of second reset signal lines Reset2, a plurality of emission signal lines EM, a plurality of first initial signal lines Vinit1, a plurality of second initial signal lines Vinit2, a plurality of third initial signal lines Vinit3, and a plurality of first power lines VDD.

[0106] In an exemplary embodiment, the scan signal lines may include a first scan signal line Gate1 , a second scan signal line Gate2 , a first reset signal line Reset1 , and a second reset signal line Reset2 .

[0107] In an exemplary embodiment, as shown in FIG4 , one end of a capacitor Cst is electrically connected to a first node N1, and the other end of the capacitor Cst is electrically connected to a first power supply line VDD. A control electrode of a first reset transistor T1 is electrically connected to a first reset signal line Reset1, a first electrode of the first reset transistor T1 is electrically connected to a first initialization signal line Vinit1, and a second electrode of the first reset transistor T1 is electrically connected to a third node N3. A control electrode of a compensation transistor T2 is electrically connected to a second scan signal line Gate2, a first electrode of the compensation transistor T2 is electrically connected to a first node N1, and a second electrode of the compensation transistor T2 is electrically connected to a second node N2. A control electrode of a drive transistor T3 is electrically connected to a first node N1, a first electrode of the drive transistor T3 is electrically connected to a second node N2, and a second electrode of the drive transistor T3 is electrically connected to a third node N3. A control electrode of a write transistor T4 is electrically connected to a first scan signal line Gate1, a first electrode of the write transistor T4 is electrically connected to a data signal line Data, and a second electrode of the write transistor T4 is electrically connected to a second node N2. The control electrode of the first light-emitting transistor T5 is electrically connected to the light-emitting signal line EM, the first electrode of the first light-emitting transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the first light-emitting transistor T5 is electrically connected to the second node N2. The control electrode of the second light-emitting transistor T6 is electrically connected to the light-emitting signal line EM, the first electrode of the second light-emitting transistor T6 is electrically connected to the third node N3, and the second electrode of the second light-emitting transistor T6 is electrically connected to the fourth node N4. The control electrode of the second reset transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4. The control electrode of the third reset transistor T8 is electrically connected to the second reset signal line Reset2, the first electrode of the third reset transistor T8 is electrically connected to the third initialization signal line Vinit3, and the second electrode of the third reset transistor T8 is electrically connected to the second node N2.

[0108] In an exemplary embodiment, the second reset signal line Reset2 connected to the second reset transistor T7 and the second reset signal line Reset2 connected to the third reset transistor T8 may be the same signal line, or may be different signal lines with the same signal, which is not limited in the present disclosure.

[0109] 4 , the display substrate may further include a second power line VSS. The light emitting device L may be electrically connected to the fourth node N4 and the second power line VSS.

[0110] In an exemplary embodiment, the light-emitting element L may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The OLED may include a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), wherein the first electrode of the OLED is connected to the fourth node N4, and the second electrode of the OLED is electrically connected to the second power line VSS.

[0111] In an exemplary embodiment, the signal of the first power line VDD is a continuously high level signal, and the signal of the second power line VSS is a low level signal.

[0112] In an exemplary embodiment, when the first reset signal line Reset1 provides an active level signal, the first reset transistor T1 transmits the first initial signal of the first initial signal line Vinit1 to the third node N3 to initialize the charge amount of the third node N3.

[0113] In an exemplary embodiment, when the second scan signal line Gate2 provides an active level signal, the compensation transistor T2 transmits the signal of the third node N3 to the first node N1 to perform threshold compensation on the driving transistor T3 or initialize the charge amount of the first node N1.

[0114] In an exemplary embodiment, the driving transistor T3 determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between the control electrode and the first electrode.

[0115] In an exemplary embodiment, when the first scan signal line Gate1 inputs an active level signal, the write transistor T4 allows the data voltage of the data signal line Data to be input to the second node N2.

[0116] In an exemplary embodiment, when the light emitting signal line EM inputs an active level signal, the first and second light emitting transistors T5 and T6 enable the light emitting element to emit light by forming a driving current path between the first and second power lines VDD and VSS.

[0117] In an exemplary embodiment, the second reset transistor T7 can be referred to as an anode reset transistor. When the second reset signal line Reset2 provides an effective level signal, the second reset transistor T7 transmits the second initial signal of the second initial signal line Vinit2 to the anode of the light-emitting element L to initialize the charge amount of the anode of the light-emitting element.

[0118] In an exemplary embodiment, the third reset transistor T8 can be referred to as a second node reset transistor. When the second reset signal line Reset2 provides an effective level signal, the third reset transistor T8 transmits the third initial signal of the third initial signal line Vinit3 to the second node N2, and can initialize the charge amount of the second node N2.

[0119] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0120] In an exemplary embodiment, at least one transistor in at least one pixel driving circuit is a P-type transistor or an N-type transistor, the first light-emitting transistor T5 and the second light-emitting transistor T6 are of the same transistor type, and the second reset transistor T71 and the third reset transistor T8 are of the same transistor type. FIG. 4 illustrates an example in which the compensation transistor T2 is an N-type transistor and the remaining transistors are P-type transistors.

[0121] In an exemplary embodiment, the first reset transistor T1 may be a P-type transistor or an N-type transistor. For example, the P-type transistor may be a low-temperature polysilicon transistor, and the N-type transistor may be a metal oxide transistor.

[0122] In an exemplary embodiment, the compensation transistor T2 may be a P-type transistor or an N-type transistor. For example, the compensation transistor T2 may be an N-type transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0123] In an exemplary embodiment, when all transistors in the pixel driving circuit are P-type transistors, the display substrate uses low-temperature polysilicon (LTPS) technology. LTPS technology offers advantages such as high resolution, high response speed, high brightness, and high aperture ratio. In an exemplary embodiment, when all transistors in the pixel driving circuit are P-type and N-type transistors, the display substrate uses low-temperature polycrystalline oxide (LTPS) technology. Compared to LTPS technology, LTPO technology offers lower leakage current and faster pixel response. The display substrate incorporates an additional oxide layer, reducing the energy required to activate the pixels, thereby reducing power consumption during screen display.

[0124] In an exemplary embodiment, as shown in FIG5 , there is a gap between the end time of the first time period t1 and the start time of the second time period t2 .

[0125] In an exemplary embodiment, as shown in FIG5 , the data unit is further configured to provide an invalid level signal to the second scan signal line Gate2 connected to the pixel driving circuit in the i-th row and j-th column in a third time period t3, and to provide a valid level signal to the second scan signal line Gate2 connected to the pixel driving circuit in the i-th row and j-th column in a fourth time period t4; wherein the end time of the third time period t3 is the start time of the fourth time period t4, the first time period t1 and the third time period t3 at least partially overlap, and the second time period t2 and the fourth time period t4 at least partially overlap.

[0126] In an exemplary embodiment, as shown in FIG5 , the duration of the third time period t3 is greater than the duration of the first time period t1, and the duration of the fourth time period t4 is greater than the duration of the second time period t2; wherein, the first time period t1 is within the third time period t3, and the second time period t2 is within the fourth time period t4.

[0127] In an exemplary embodiment, as shown in Figure 5, the data unit is further configured to provide a valid level signal to the second scan signal line Gate2 connected to the pixel driving circuit in the i-th row and j-th column in a fifth time period t5, wherein the fifth time period t5 occurs before the third time period t3, and the end time of the fifth time period t5 is the start time of the third time period t3.

[0128] 5 , the data unit is further configured to provide an active level signal to the first reset signal line Reset1 connected to the pixel driving circuit in the i-th row and j-th column in the sixth time period t6 , which at least partially overlaps with the fifth time period t5 .

[0129] In an exemplary embodiment, as shown in FIG. 5 , the duration of the fifth time period t5 is greater than the duration of the sixth time period t6 , and the sixth time period t6 is located within the fifth time period t5 .

[0130] In an exemplary embodiment, as shown in FIG5 , the data unit is further configured to provide an active level signal to the second reset signal line Reset2 connected to the i-th row and j-th column pixel driving circuit in a seventh time period t7 , which occurs after the fourth time period t4 .

[0131] In an exemplary embodiment, as shown in FIG5 , there is a gap between the end time of the fourth time period t4 and the start time of the seventh time period t7 .

[0132] In an exemplary embodiment, as shown in FIG5 , the data unit is further configured to provide an invalid level signal to the first reset signal line Reset1 and the second reset signal line Reset2 connected to the pixel driving circuit in the i-th row and j-th column during a third time period t3 and a fourth time period t4, provide an invalid level signal to the first scan signal line Gate1 and the second reset signal line Reset2 connected to the pixel driving circuit in the i-th row and j-th column during a fifth time period t5, and provide an invalid level signal to the first scan signal line Gate1, the second scan signal line Gate2, and the first reset signal line Reset1 connected to the pixel driving circuit in the i-th row and j-th column during a seventh time period t7.

[0133] In an exemplary embodiment, as shown in FIG5 , the data unit is further configured to provide an invalid level signal to the first scan signal line Gate1 , the second scan signal line Gate2 , the first reset signal line Reset1 , and the second reset signal line Reset2 connected to the pixel driving circuit in the i-th row and j-th column in the eighth time period t8 .

[0134] In an exemplary embodiment, in the eighth period t8 , the voltage value of the signal at the second node N2 is greater than the voltage value of the signal at the first node N1 , and the driving transistor is in the second bias state.

[0135] In an exemplary embodiment, as shown in FIG5 , the data unit is further configured to provide a valid level signal to the light emitting signal line connected to the pixel driving circuit in the i-th row and j-th column in a ninth time period t9, provide an invalid level signal to the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, and the second reset signal line Reset2 connected to the pixel driving circuit in the i-th row and j-th column, and provide an invalid level signal to the light emitting signal line connected to the pixel driving circuit in the i-th row and j-th column in a third time period t3, a fourth time period t4, a fifth time period t5, a seventh time period t7, and an eighth time period t8, and the ninth time period t9 occurs after the eighth time period t8.

[0136] In an exemplary embodiment, the first initial signal line Vinit1 connected to at least one pixel circuit provides a first initial signal in a refresh frame and a hold frame. The first initial signal is a DC signal, and a voltage value of the first initial signal is constant.

[0137] In an exemplary embodiment, the second initial signal line Vinit2 connected to at least one pixel circuit provides a second initial signal in a refresh frame and a hold frame, the second initial signal is a DC signal, and a voltage value of the second initial signal is constant.

[0138] In an exemplary embodiment, a third initial signal line Vinit3 connected to at least one pixel circuit provides a third initial signal during a refresh frame and a hold frame. The third initial signal is a DC signal, and the voltage of the third initial signal is constant. Exemplarily, the voltage of the third initial signal provided by the third initial signal line Vinit3 may be approximately the same as the voltage of the signal on the first power line VDD. The voltage of the third initial signal may be approximately 5 volts to 8 volts.

[0139] In an exemplary embodiment, as shown in FIG5 , the first scanning signal line Gate1 connected to the at least one pixel circuit is a two-pulse signal in a refresh frame, and the signals in the first time period t1 and the second time period t2 are active level signals. The first scanning signal line Gate1 connected to the at least one pixel circuit is an inactive level signal in a hold frame.

[0140] In an exemplary embodiment, as shown in FIG5 , the second scanning signal line Gate2 connected to at least one pixel circuit is a two-pulse signal in a refresh frame, and the signal in the fifth time period t5 and the fourth time period t4 is an active level signal. The signal of the second scanning signal line Gate2 connected to at least one pixel circuit is an inactive level signal in a hold frame.

[0141] In an exemplary embodiment, as shown in FIG5 , the first reset signal line Reset1 connected to at least one pixel circuit is a single pulse signal during the refresh frame, and the signal during the sixth time period t6 is an active level signal. The signal of the first reset signal line Reset1 connected to at least one pixel circuit during the hold frame can be an inactive level signal, a single pulse signal, or a multi-pulse signal. The signal of the first reset signal line Reset1 connected to at least one pixel circuit during the hold frame can be determined based on the actual debugging effect of the display substrate.

[0142] In an exemplary embodiment, as shown in FIG5 , the second reset signal line Reset2 connected to at least one pixel circuit is a single pulse signal during the refresh frame, and the signal during the seventh time period t7 is an active level signal. The signal of the second reset signal line Reset2 connected to at least one pixel circuit during the hold frame can be a single pulse signal or a multiple pulse signal. The signal of the second reset signal line Reset2 connected to at least one pixel circuit during the hold frame can be determined based on the actual debugging effect of the display substrate.

[0143] In an exemplary embodiment, as shown in FIG5 , the luminescence signal line EM connected to the at least one pixel circuit is a single pulse signal during the refresh frame, and the signal during the ninth time period t9 is an active level signal. The signal of the luminescence signal line EM connected to the at least one pixel circuit during the hold frame may be a single pulse signal, or may be a multi-pulse signal. The signal of the luminescence signal line EM connected to the at least one pixel circuit during the hold frame may be determined based on the actual debugging effect of the display substrate.

[0144] In an exemplary embodiment, as shown in FIG. 5 , during the holding frame, when the data unit provides a valid level signal to the second reset signal line Reset2 , the signal of the light emitting signal line EM is an invalid level signal.

[0145] In an exemplary embodiment, Figure 6 is a schematic diagram of the operation of the pixel driving circuit in the first stage, Figure 7 is a schematic diagram of the operation of the pixel driving circuit in the second stage, Figure 8 is a schematic diagram of the operation of the pixel driving circuit in the third stage, Figure 9 is a schematic diagram of the operation of the pixel driving circuit in the fourth stage, Figure 10 is a schematic diagram of the operation of the pixel driving circuit in the fifth stage, and Figure 11 is a schematic diagram of the operation of the pixel driving circuit in the sixth stage. Taking the pixel driving circuit of FIG4 as an example, in combination with FIG4 to FIG11 , the compensation transistor T2 is an N-type transistor, and the first reset transistor T1, the driving transistor T3, the write transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the second reset transistor T7, and the eighth reset transistor T8 are P-type transistors as an example to illustrate the working process of the pixel driving circuit provided by an exemplary embodiment. As shown in FIG5 , in a refresh frame of at least one display frame, the working process of at least one pixel driving circuit may include: a first stage S1, a second stage S2, a third stage S3, a fourth stage S4, a fifth stage S5, and a sixth stage S6, wherein the first stage S1 is a stage where the fifth time period t5 is located, the second stage S2 is a stage where the third time period t3 is located, the third stage S3 is a stage where the fourth time period t4 is located, the fourth stage S4 is a stage where the seventh time period t7 is located, the fifth stage S5 is a stage where the eighth time period t8 is located, and the sixth stage S6 is a stage where the ninth time period t9 is located. FIG5 is illustrated by taking the pixel circuit of the i-th row and j-th column as an example.

[0146] In the first stage S1, i.e., the first initialization stage, the signals of the first scanning signal line Gate1, the second scanning signal line Gate2, the second reset signal line Reset2, and the light-emitting signal line EM are all high-level signals, and the signal of the first reset signal line Reset1 is a low-level signal. The signal of the first reset signal line Reset1 is a low-level signal, the first reset transistor T1 is turned on, and the first initialization signal of the first initialization signal line Vinit1 is written to the third node N3, initializing (resetting) the third node N3 and clearing the pre-stored voltage therein, completing initialization. The signal of the second scanning signal line Gate2 is a high-level signal, the compensation transistor T2 is turned on, and the signal of the third node N3 is written to the first node N1, initializing (resetting) the first node N1 and clearing the pre-stored voltage therein, completing initialization. In this stage, the driving transistor T3 is turned on. The signals of the first scanning signal line Gate1, the second reset signal line Reset2, and the light-emitting signal line EM are all high-level signals, and the write transistor T4, the first light-emitting transistor T5, the second light-emitting transistor T6, the second reset transistor T7, and the third reset transistor T8 are turned off. At this stage, the light emitting element L does not emit light.

[0147] In the second phase S2, i.e., the debiasing phase, the signals on the first reset signal line Reset1, the second reset signal line Reset2, and the emission signal line EM are all high-level signals. The signals on the first scan signal line Gate1 and the second scan signal line Gate2 are low-level signals. A first data voltage is written to the data signal line Data. The first data voltage is the voltage of the data signal corresponding to the pixel circuit in the i-1th row and jth column. The signal on the first scan signal line Gate1 is low-level, the write transistor T4 is turned on, and the first data voltage is written to the second node N2. Since the signal on the second scan signal line Gate2 is low-level, the compensation transistor T2 is turned off. Therefore, during this phase, the first node N1 remains low-level, and the drive transistor T3 remains on. In this phase, the voltage value of the signal on the second node N2 is greater than the voltage value of the signal on the first node N1, and the drive transistor T3 is in the first bias state. The signals on the first reset signal line Reset1, the second reset signal line Reset2, and the emission signal line EM are all high-level signals. The first reset transistor T1, the second reset transistor T7, the third reset transistor T8, the first emission transistor T5, and the sixth emission transistor T6 are turned off. At this stage, the light emitting element L does not emit light.

[0148] In the third phase S3, i.e., the data writing phase, the signals on the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2, and the emission signal line EM are all high-level signals, the signal on the first scan signal line Gate1 is low-level, and the data signal line Data is written with a second data voltage, which is the voltage of the data signal corresponding to the pixel circuit in the i-th row and j-th column. The signal on the first scan signal line Gate1 is low-level, the write transistor T4 is turned on, the signal on the second scan signal line Gate2 is high-level, and the compensation transistor T2 is turned on. The second data voltage output by the data signal line Data is written to the first node N1 through the turned-on write transistor T4, the second node N2, the turned-on drive transistor T3, the third node N3, and the turned-on compensation transistor T2. The difference between the second data voltage output by the data signal line Data and the threshold voltage of the drive transistor T3 is charged into the capacitor Cst until the voltage at the first node N1 reaches Vdata-|Vth|, where Vdata is the second data voltage output by the data signal line Data and Vth is the threshold voltage of the drive transistor T3. The signals on the first reset signal line Reset1, the second reset signal line Reset2, and the light-emitting signal line EM are all high-level signals. The first reset transistor T1, the second reset transistor T7, the third reset transistor T8, the first light-emitting transistor T5, and the sixth light-emitting transistor T6 are turned off. During this stage, the light-emitting element L does not emit light. During this stage, the light-emitting element L does not emit light.

[0149] In the fourth stage S4, i.e., the second initialization stage, the signals of the first scanning signal line Gate1, the first reset signal line Reset1, and the light-emitting signal line EM are all high-level signals, and the signals of the second scanning signal line Gate2 and the second reset signal line Reset2 are low-level signals. The signal of the second reset signal line Reset2 is a low-level signal, the second reset transistor T7 and the third reset transistor T8 are turned on, and the second initial signal of the second initial signal line Vinit2 is written to the fourth node N4, initializing (resetting) the fourth node N4 (that is, the first electrode of the light-emitting device), clearing the pre-stored voltage therein, and completing the initialization. Since the driving transistor T3 is turned on, the third initial signal of the third initial signal line Vinit3 is written to the second node N2 and the third node N3, initializing (resetting) the second node N2 and the third node N3, clearing the pre-stored voltage therein, and completing the initialization. The signals on the first reset signal line Reset1, the first scan signal line Gate1, and the emission signal line EM are all high-level signals. The signal on the second scan signal line Gate2 is also high-level. The compensation transistor T2, the write transistor T4, the first reset transistor T1, the first emission transistor T5, and the sixth emission transistor T6 are turned off. During this phase, the light-emitting element L does not emit light. During this phase, the light-emitting element L does not emit light.

[0150] In the fifth stage S5, i.e., the hold stage, the signals on the first scan signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2, and the light-emitting signal line EM are all high-level signals, while the signal on the second scan signal line Gate2 is a low-level signal. The signals on the first scan signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2, and the light-emitting signal line EM are all high-level signals, while the signal on the second scan signal line Gate2 is a low-level signal. The first reset transistor T1, the compensation transistor T2, the write transistor T4, the first light-emitting transistor T5, the sixth light-emitting transistor T6, the second reset transistor T7, and the third reset transistor T8 are turned off. During this stage, the drive transistor T3 is turned on, allowing the third initial signal on the third initial signal line Vinit3 sufficient time to act on the first and second electrodes of the drive transistor T3. During this stage, the voltage value of the signal on the second node N2 is greater than the voltage value of the signal on the first node N1, allowing the drive transistor T3 to remain in a biased state for a long time, thereby improving the hysteresis state of the drive transistor T3 and, in turn, the low-frequency flicker problem of the display substrate.

[0151] In the sixth stage S6, i.e., the light-emitting stage, the signals on the first scanning signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are all high-level signals, while the signals on the second scanning signal line Gate2 and the light-emitting signal line EM are low-level signals. The signal on the light-emitting signal line EM is low-level, and the first light-emitting transistor T5 and the sixth light-emitting transistor T6 are turned on. The power supply voltage output by the first power line VDD provides a driving voltage to the fourth node N4 through the turned-on first light-emitting transistor T5, the driving transistor T3, and the sixth light-emitting transistor T6, thereby driving the light-emitting device L to emit light.

[0152] During the refresh frame of the pixel driving circuit, the driving current flowing through the driving transistor T3 is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the driving transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vdata+|Vth|)-Vth] 2 =K*[(Vdd-Vdata] 2

[0153] Wherein, I is the driving current flowing through the driving transistor T3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the driving transistor T3, Vth is the threshold voltage of the driving transistor T3, Vdata is the second data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply terminal VDD.

[0154] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0155] In the present disclosure, the pixel driving circuit is in a bias state in the fifth stage of the refresh frame of the mth display frame, which can improve the hysteresis state of the driving transistor T3, and thus improve the low-frequency flicker problem of the display substrate. Being in a bias state in the second stage can improve the afterimage problem caused by being in the second bias state in the fifth stage of the refresh frame of the m-1th display frame.

[0156] The present disclosure also provides a method for driving a display substrate, which is configured to drive the display substrate. The method for driving the display substrate may include:

[0157] In a first time period, an effective level signal is provided to a first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and a first data signal is provided to a data signal line connected to the pixel driving circuit in the i-th row and j-th column;

[0158] In the second time period, an effective level signal is provided to the first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and a second data signal is provided to the data signal line connected to the pixel driving circuit in the i-th row and j-th column. The first time period occurs before the second time period.

[0159] In an exemplary embodiment, the method for driving a display substrate may further include the following steps:

[0160] In a third time period, an invalid level signal is provided to the second scanning signal line, the first reset signal line, the second reset signal line and the light emitting signal line connected to the pixel driving circuit in the i-th row and the j-th column;

[0161] In a fourth time period, a valid level signal is provided to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and an invalid level signal is provided to the first reset signal line, the second reset signal line, and the light emitting signal line connected to the pixel driving circuit in the i-th row and j-th column;

[0162] In a fifth time period, a valid level signal is provided to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and an invalid level signal is provided to the first scanning signal line, the second reset signal line, and the light emitting signal line connected to the pixel driving circuit in the i-th row and j-th column;

[0163] providing an effective level signal to the first reset signal line connected to the pixel driving circuit in the i-th row and j-th column in a sixth time period;

[0164] In the seventh time period, a valid level signal is provided to the second reset signal line connected to the pixel driving circuit in the i-th row and j-th column, and an invalid level signal is provided to the first scanning signal line, the second scanning signal line, the first reset signal line and the light emitting signal line;

[0165] In an eighth time period, an invalid level signal is provided to the first scanning signal line, the second scanning signal line, the first reset signal line, the second reset signal line and the light emitting signal line connected to the pixel driving circuit in the i-th row and the j-th column;

[0166] In the ninth time period, a valid level signal is provided to the light-emitting signal line connected to the pixel driving circuit of the i-th row and j-th column, and an invalid level signal is provided to the first scanning signal line, the second scanning signal line, the first reset signal line and the second reset signal line connected to the pixel driving circuit of the i-th row and j-th column.

[0167] In an exemplary embodiment, the first time period and the third time period at least partially overlap, the second time period and the fourth time period at least partially overlap, the fifth time period occurs before the third time period, the sixth time period at least partially overlaps with the fifth time period, the seventh time period occurs after the fourth time period, the eighth time period occurs after the seventh time period, and the ninth time period occurs after the eighth time period.

[0168] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0169] An embodiment of the present disclosure further provides a display device, including: a display substrate.

[0170] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and implementation effect are similar, which will not be repeated here.

[0171] In an exemplary embodiment, the display device may be a monitor, a television, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product, or any product or component having a display function.

[0172] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0173] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0174] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A display substrate, the content displayed on the display substrate includes a plurality of display frames, and at least one display frame includes: Refresh frame, the display substrate includes: a data unit, pixel driving circuits arranged in an array, a plurality of first scanning signal lines, and a plurality of data signal lines. At least one pixel driving circuit includes: a driving transistor and a writing transistor. The driving transistor is respectively connected to a first node and a second node. The writing transistor is respectively electrically connected to the first scanning signal line, the data signal line, and the second node; In the refresh frame of at least one display frame, when the pixel driving circuit in the i-th row and j-th column is displaying, the data unit is configured to provide an effective level signal to the first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column in a first time period, and provide a first data signal to the data signal line connected to the pixel driving circuit in the i-th row and j-th column. In a second time period, provide an effective level signal to the first scanning signal line connected to the pixel driving circuit in the i-th row and j-th column, and provide a second data signal to the data signal line connected to the pixel driving circuit in the i-th row and j-th column. The first time period occurs before the second time period; During the first time period, the voltage value of the signal of the second node is greater than the voltage value of the signal of the first node. The first data signal is the data signal corresponding to the pixel driving circuit in the k-th row and j-th column, and the second data signal is the data signal corresponding to the pixel driving circuit in the i-th row and j-th column. k is at least one value less than i, 1≤i≤M, 1≤j≤N, M is the total number of rows of pixel driving circuits, and N is the total number of columns of pixel driving circuits.

2. The display substrate according to claim 1, wherein, There is an interval between the end time of the first time period and the start time of the second time period.

3. The display substrate according to claim 1 further comprises: A plurality of second scanning signal lines. At least one pixel driving circuit further includes: a compensation transistor. The driving transistor is further connected to a third node. The compensation transistor is respectively electrically connected to the second scanning signal line, the first node, and the third node; The data unit is further configured to provide an invalid level signal to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column in a third time period, and provide an effective level signal to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column in a fourth time period; The end time of the third time period is the start time of the fourth time period. The first time period and the third time period at least partially overlap, and the second time period and the fourth time period at least partially overlap.

4. The display substrate according to claim 3, wherein The duration of the third time period is greater than the duration of the first time period, and the duration of the fourth time period is greater than the duration of the second time period; The first time period is located within the third time period, and the second time period is located within the fourth time period.

5. The display substrate according to claim 3, wherein, The data unit is further configured to provide an effective level signal to the second scanning signal line connected to the pixel driving circuit in the i-th row and j-th column in a fifth time period. The fifth time period occurs before the third time period, and the end time of the fifth time period is the start time of the third time period.

6. The display substrate according to claim 5 further comprises: A plurality of first reset signal lines. At least one pixel driving circuit further includes: a first reset transistor. The first reset transistor is respectively connected to the first reset signal line and the third node; The data unit is further configured to provide an effective level signal to a first reset signal line connected to the pixel driving circuit of the i-th row and j-th column during a sixth time period, and the sixth time period at least partially overlaps with the fifth time period.

7. The display substrate according to claim 6, wherein, The duration of the fifth time period is greater than the duration of the sixth time period, and the sixth time period is located within the fifth time period.

8. The display substrate according to claim 6 further comprises: For multiple second reset signal lines, at least one pixel driving circuit further includes: a second reset transistor and a third reset transistor, where the second reset transistor is respectively connected to a second reset signal line and a fourth node, and the third reset transistor is respectively connected to the second reset signal line and a second node; The data unit is further configured to provide an effective level signal to a second reset signal line connected to the pixel driving circuit of the i-th row and j-th column during a seventh time period, and the seventh time period occurs after the fourth time period.

9. The display substrate according to claim 8, wherein, There is an interval between the end time of the fourth time period and the start time of the seventh time period.

10. The display substrate according to claim 8, wherein, The data unit is further configured to provide an ineffective level signal to the first reset signal line and the second reset signal line connected to the pixel driving circuit of the i-th row and j-th column during a third time period and a fourth time period, provide an ineffective level signal to the first scan signal line and the second reset signal line connected to the pixel driving circuit of the i-th row and j-th column during a fifth time period, and provide an ineffective level signal to the first scan signal line, the second scan signal line, and the first reset signal line connected to the pixel driving circuit of the i-th row and j-th column during a seventh time period.

11. The display substrate according to claim 8, wherein, The data unit is further configured to provide an ineffective level signal to the first scan signal line, the second scan signal line, the first reset signal line, and the second reset signal line connected to the pixel driving circuit of the i-th row and j-th column during an eighth time period.

12. The display substrate according to claim 8 further comprises: For multiple light-emitting signal lines, at least one pixel driving circuit includes: a first light-emitting transistor and a second light-emitting transistor, where the first light-emitting transistor is respectively connected to a light-emitting signal line and a second node, and the second light-emitting transistor is respectively connected to the light-emitting signal line and a third node; The data unit is further configured to provide an effective level signal to the light-emitting signal line connected to the pixel driving circuit of the i-th row and j-th column during a ninth time period, provide an ineffective level signal to the first scan signal line, the second scan signal line, the first reset signal line, and the second reset signal line connected to the pixel driving circuit of the i-th row and j-th column, and provide an ineffective level signal to the light-emitting signal line connected to the pixel driving circuit of the i-th row and j-th column during a third time period, a fourth time period, a fifth time period, a seventh time period, and an eighth time period, and the ninth time period occurs after the eighth time period.

13. The display substrate according to claim 1 further comprises: For multiple light-emitting signal lines, multiple first reset signal lines, multiple second reset signal lines, multiple first initial signal lines, multiple second initial signal lines, multiple third initial signal lines, multiple second scan signal lines, and multiple first power supply lines, at least one pixel driving circuit further includes: a compensation transistor, a first reset transistor, a second reset transistor, a third reset transistor, a first light-emitting transistor, a second light-emitting transistor, and a capacitor; The control electrode of the compensation transistor is connected to the second scan signal line, the first electrode of the compensation transistor is connected to the first node, and the second electrode of the compensation transistor is connected to the third node; The control electrode of the driving transistor is connected to the first node, the first electrode of the driving transistor is connected to the second node, and the second electrode of the driving transistor is connected to the third node; The control electrode of the writing transistor is connected to the first scan signal line, the first electrode of the writing transistor is connected to the data signal line, and the second electrode of the writing transistor is connected to the second node; The control electrode of the first reset transistor is connected to the first reset signal line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the third node; The control electrode of the second reset transistor is connected to the second reset signal line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the fourth node; The control electrode of the third reset transistor is connected to the second reset signal line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the second node; The control electrode of the first light-emitting transistor is connected to the light-emitting signal line, the first electrode of the first light-emitting transistor is connected to the first power supply line, and the second electrode of the first light-emitting transistor is connected to the second node; The control electrode of the second light-emitting transistor is connected to the light-emitting signal line, the first electrode of the second light-emitting transistor is connected to the third node, and the second electrode of the second light-emitting transistor is connected to the fourth node; One end of the capacitor is connected to the first power supply line, and the other end of the capacitor is connected to the first node.

14. The display substrate according to claim 13, wherein, At least one transistor in at least one pixel driving circuit is a P-type transistor or an N-type transistor. The transistor types of the first light-emitting transistor and the second light-emitting transistor are the same, and the transistor types of the second reset transistor and the third reset transistor are the same.

15. A display device, comprising: The display substrate according to any one of claims 1 to 14.

16. A driving method for a display substrate, configured to drive the display substrate according to any one of claims 1 to 14, the method comprising: Providing an effective level signal to the first scan signal line connected to the pixel driving circuit of the i-th row and the j-th column, and providing a first data signal to the data signal line connected to the pixel driving circuit of the i-th row and the j-th column in a first time period; Providing an effective level signal to the first scan signal line connected to the pixel driving circuit of the i-th row and the j-th column, and providing a second data signal to the data signal line connected to the pixel driving circuit of the i-th row and the j-th column in a second time period, the first time period occurring before the second time period.

17. The method according to claim 16, further comprising: Providing an invalid level signal to the second scan signal line, the first reset signal line, the second reset signal line, and the light-emitting signal line connected to the pixel driving circuit of the i-th row and the j-th column in a third time period; During a fourth time period, an active level signal is provided to a second scan signal line connected to the pixel driving circuit of the i-th row and j-th column, and inactive level signals are provided to a first reset signal line, a second reset signal line, and a light-emitting signal line connected to the pixel driving circuit of the i-th row and j-th column; During a fifth time period, an active level signal is provided to the second scan signal line connected to the pixel driving circuit of the i-th row and j-th column, and inactive level signals are provided to the first scan signal line, the second reset signal line, and the light-emitting signal line connected to the pixel driving circuit of the i-th row and j-th column; During a sixth time period, an active level signal is provided to the first reset signal line connected to the pixel driving circuit of the i-th row and j-th column; During a seventh time period, an active level signal is provided to the second reset signal line connected to the pixel driving circuit of the i-th row and j-th column, and inactive level signals are provided to the first scan signal line, the second scan signal line, the first reset signal line, and the light-emitting signal line; During an eighth time period, inactive level signals are provided to the first scan signal line, the second scan signal line, the first reset signal line, the second reset signal line, and the light-emitting signal line connected to the pixel driving circuit of the i-th row and j-th column; During a ninth time period, an active level signal is provided to the light-emitting signal line connected to the pixel driving circuit of the i-th row and j-th column, and inactive level signals are provided to the first scan signal line, the second scan signal line, the first reset signal line, and the second reset signal line connected to the pixel driving circuit of the i-th row and j-th column; The first time period and the third time period at least partially overlap, the second time period and the fourth time period at least partially overlap, the fifth time period occurs before the third time period, the sixth time period and the fifth time period at least partially overlap, the seventh time period occurs after the fourth time period, the eighth time period occurs after the seventh time period, and the ninth time period occurs after the eighth time period.

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