Gate drive circuit, display substrate, and display apparatus

Abstract

A gate drive circuit, a display substrate, and a display apparatus. The gate drive circuit comprises a shift register circuit (100) arranged on a silicon base (101), and the shift register circuit (100) comprises a plurality of transistor groups sequentially arranged in a first direction, wherein at least one transistor group comprises a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction, the P-type transistor at least comprises a P-type active region, the N-type transistor at least comprises an N-type active region, a gap region (50) is provided between the P-type active region and the N-type active region in the second direction, and the gap region (50) has a gap center line (OC), the first direction intersecting the second direction; and the plurality of transistor groups form at least one transmission gate, at least one NAND gate and at least one inverter, and the gap center lines (OC) of the transistor groups in the at least one transmission gate, the at least one NAND gate and the at least one inverter are in the same straight line extending in the first direction.

Description

Gate driving circuit, display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a gate driving circuit, a display substrate, and a display device. Background Art

[0002] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of microdisplay that has been developed in recent years, with silicon-based OLEDs being one of them. Silicon-based OLEDs are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as substrates for manufacturing OLED devices. By combining the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLEDs not only offer a high pixel density (PPI), but also high brightness, low power consumption, fast response time, a wide color gamut, and excellent thermal stability.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, an embodiment of the present disclosure provides a gate drive circuit, including a shift register circuit arranged on a silicon substrate, the shift register circuit including at least a plurality of transistor groups arranged in sequence along a first direction, at least one transistor group including a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction, the first direction and the second direction intersecting; the P-type transistor including at least a P-type active area, the N-type transistor including at least an N-type active area, in the second direction, a gap region is provided between the P-type active area and the N-type active area, the gap region having a gap centerline, the gap centerline being a straight line that bisects the gap region in the second direction and extends in the first direction; the plurality of transistor groups form at least one transmission gate, at least one NAND gate and at least one inverter, the gap centerlines of the transistor groups in the at least one transmission gate, the at least one NAND gate and the at least one inverter being on the same straight line extending in the first direction.

[0006] In an exemplary embodiment, a plurality of transistor groups form a first transmission gate, a first NAND gate, a third inverter, a second transmission gate, a third transmission gate, a second NAND gate, a fourth inverter, a second inverter, and a first inverter, which are arranged in sequence along the first direction; the widths of the gap regions of the transistor groups in the same type of devices are the same, the center lines of the gaps of the transistor groups in the same type of devices are on the same straight line extending along the first direction, and the width of the gap regions is the dimension in the second direction.

[0007] In an exemplary embodiment, the width-to-length ratios of P-type transistors in devices of the same type are the same, and the width-to-length ratios of N-type transistors in devices of the same type are the same.

[0008] In an exemplary embodiment, in at least one of the first inverter, the second inverter, the third inverter, and the fourth inverter, a ratio of a width-to-length ratio of the P-type transistor to a width-to-length ratio of the N-type transistor is greater than 1 and less than 3.

[0009] In an exemplary embodiment, the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first NAND gate is greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter, and the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter is greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first transmission gate.

[0010] In an exemplary embodiment, the shift register circuit further includes a power active region and a ground active region, the power active region being arranged on a side of the P-type active region away from the N-type active region, and the ground active region being arranged on a side of the N-type active region away from the P-type active region, the power active region having a first center line, and the ground active region having a second center line, the first center line being a straight line that bisects the power active region in the second direction and extends along the first direction, the second center line being a straight line that bisects the ground active region in the second direction and extends along the first direction, and in the second direction, a distance between the first center line and the second center line is less than or equal to 6.3 μm.

[0011] In an exemplary embodiment, in at least one transistor group, a first width is provided between the first center line and an edge of the P-type active area on a side close to the first center line, and a second width is provided between the second center line and an edge of the N-type active area on a side close to the second center line. The first width is greater than 1 μm and less than 3 μm, and the second width is greater than 1 μm and less than 3 μm. The first width and the second width are dimensions in the second direction.

[0012] In an exemplary embodiment, in at least one transistor group, a third width is present between an edge of the P-type active region away from the first center line and an edge of the N-type active region away from the second center line, and the third width is greater than or equal to 1.5 μm, and the third width is a dimension in the second direction.

[0013] In an exemplary embodiment, in at least one transistor group, a P-type active area width is provided between an edge of the P-type active area on a side close to the first center line and an edge of the P-type active area on a side away from the first center line; an N-type active area width is provided between an edge of the N-type active area on a side close to the second center line and an edge of the N-type active area on a side away from the second center line; the P-type active area width is greater than 1 μm and less than 3 μm, and the N-type active area width is greater than 1 μm and less than 3 μm, and the P-type active area width and the N-type active area width are dimensions in the second direction.

[0014] In an exemplary embodiment, the gate drive circuit further includes a logic operation circuit, a level converter, and a row drive enhancer arranged on a silicon substrate, wherein the shift register circuit is configured to generate a row-by-row shift timing according to a timing signal, the logic operation circuit is configured to generate a target timing through a logic operation, the level converter is configured to perform voltage domain conversion on the target timing, and the row drive enhancer is configured to enhance the converted signal and output it to the scan signal line of the display area.

[0015] On the other hand, an embodiment of the present disclosure provides a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the aforementioned gate driving circuit.

[0016] On the other hand, embodiments of the present disclosure provide a display device including the aforementioned display substrate.

[0017] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0019] FIG1 is a schematic structural diagram of a silicon-based OLED display device;

[0020] FIG2 is a schematic diagram of a planar structure of a display area in a silicon-based OLED display device;

[0021] FIG3 is a schematic diagram of the cross-sectional structure of a display area in a silicon-based OLED display device;

[0022] FIG4 is an equivalent circuit diagram of a pixel driving circuit;

[0023] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0024] FIG6 is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0025] FIG7 is a working principle diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0026] FIG8 is an equivalent circuit diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0027] FIG9 is a schematic structural diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0028] 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming patterns of an N-well region and an active region;

[0029] FIG10C is an enlarged view of the region where the first NAND gate and the third inverter are located in FIG10A ;

[0030] 11A and 11B are schematic diagrams of an embodiment of the present disclosure after a gate conductive layer pattern is formed;

[0031] FIG11C is an enlarged view of the twelfth P-type gate electrode and the twelfth N-type gate electrode in FIG11A;

[0032] 12A and 12B are schematic diagrams of a P-type doping region pattern formed according to an embodiment of the present disclosure;

[0033] 13A and 13B are schematic diagrams of an embodiment of the present disclosure after forming an N-type doping region pattern;

[0034] FIG14 is a schematic diagram of an embodiment of the present disclosure after forming a second insulating layer pattern;

[0035] 15A and 15B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0036] FIG15C is an enlarged view of area A in FIG15A ;

[0037] FIG15D is an enlarged view of area B in FIG15A;

[0038] FIG16 is a schematic diagram of an embodiment of the present disclosure after forming a third insulating layer pattern;

[0039] 17A and 17B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern.

[0040] DESCRIPTION OF NUMERALS: 10—N-well region; 31—first P-type doped region; 32—second P-type doped region; 41—first N-type doped region; 42—second N-type doped region; 51—first power line; 52—ground line; 100—shift register circuit; 101—silicon substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—first packaging layer; 105—color filter structure layer; 106—second packaging layer; 107—cover layer; 200—logic operation circuit; 300—level shifter; 201—first transmission gate; 202—second transmission gate; 203—third transmission gate; 301—first NAND gate; 302—second NAND gate; 400—row driver booster; 401—first inverter; 402—second inverter; 403—third inverter; 404 — fourth inverter; DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0042] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0043] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0044] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0045] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0046] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0047] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" can be interchanged.

[0048] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0049] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0050] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0051] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0052] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0053] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0054] FIG1 is a schematic diagram of the structure of a silicon-based OLED display device. As shown in FIG1 , the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel in the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scan signal line and the j-th data signal line, where i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a data driver (SD). The display driver circuit may include at least a timing controller (TCON). The timing controller is configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send the timing signals to the gate driver. The gate driver is respectively connected to a plurality of scan signal lines in the display area, and the gate driver is configured to provide the required timing signals (timing) to the connected pixel driver circuit to realize the display progressive scanning function. The data driver is respectively connected to a plurality of data signal lines in the display area, and the data driver is configured to provide the required data signals (data) to the connected pixel driver circuit to realize the switching and control of the display screen.

[0055] In one exemplary embodiment, a silicon-based OLED display device may utilize a single-chip display architecture ("One Chip"), integrating a gate driver, data driver, clock control unit, image processing unit, and storage unit on a single chip. A chip with a One Chip architecture includes both digital and analog components, making it a mixed-signal chip.

[0056] In another exemplary embodiment, the silicon-based OLED display device can be a dual-chip display architecture (Two Chip), in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the storage unit are integrated in one chip, which is bonded to the display substrate through the COC process.

[0057] Figure 2 is a schematic diagram of the planar structure of a display area in a silicon-based OLED display device. As shown in Figure 2, the display area may include multiple pixel units P arranged in a matrix on a plane parallel to the display device. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0058] In an exemplary embodiment, the first subpixel P1 may be a red (R) subpixel emitting red light, the second subpixel P2 may be a blue (B) subpixel emitting blue light, and the third subpixel P3 may be a green (G) subpixel emitting green light.

[0059] In an exemplary embodiment, the shape of the sub-pixels can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. The three sub-pixels can be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a herringbone arrangement, etc., which is not limited in this disclosure. In other possible embodiments, the pixel unit can include four sub-pixels, which is not limited in this disclosure.

[0060] FIG3 is a schematic diagram of the cross-sectional structure of the display area in a silicon-based OLED display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0061] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the silicon substrate 101 by a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 shows only one transistor as an example. The transistor may include a gate electrode G, a source electrode S, and a drain electrode D. The gate electrode G, the source electrode S, and the drain electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), respectively, and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0062] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the drain electrode D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0063] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be encapsulated using a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is set in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is set in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is set in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic material such as colorless polyimide.

[0064] Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit has a 4T2C structure, which can include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power line VDD, and a second power line VSS).

[0065] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2, respectively. The third node N3 is connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, respectively.

[0066] In an exemplary embodiment, the first transistor T1 can be referred to as a write switch transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line DATA, and a second electrode of the first transistor T1 is connected to the first node N1.

[0067] In an exemplary embodiment, the second transistor T2 is called a display switch transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2.

[0068] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0069] In an exemplary embodiment, the fourth transistor T4 can be referred to as a reset (Auto Zero) transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the second power line VSS, and a second electrode of the fourth transistor T4 is connected to the third node N3.

[0070] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the second node N2, a first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the first power line VDD.

[0071] In an exemplary embodiment, the light emitting device XL may be an organic light emitting diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device XL is connected to the third node N3, and the second electrode of the light emitting device XL is connected to the common voltage line VCOM.

[0072] In an exemplary embodiment, the signal of the first power line VDD may be a continuously provided high level signal, and the signals of the second power line VSS and the common voltage line VCOM may be continuously provided low level signals.

[0073] In an exemplary embodiment, the first to fourth transistors T1 to T4 may be P-type transistors (PMOS) or N-type transistors (NMOS). For example, the first to fourth transistors T1 to T4 are all P-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0074] In an exemplary embodiment, the first to fourth transistors T1 to T4 may include P-type transistors and N-type transistors. For example, the first to third transistors T1 to T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as shown in FIG4 .

[0075] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0076] The first phase A1 can be called the initialization phase. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1 is turned on so that the bias voltage Vofs output by the data signal line DATA is written into the first capacitor C1, and the potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vofs. The second transistor T2 is turned on so that the first power supply voltage ELVDD output by the first power line VDD is written into the second node N2, and the potential Vg of the second node N2 (i.e., the first electrode of the third transistor T3) is ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is ELVDD-Vofs, and the storage voltage V of the first capacitor C1 is V cs=ELVDD-Vofs, the potential Vd of the third node N3 (ie, the second electrode of the third transistor T3) = Vg+Vth, preparing for the next stage of discharge. ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0077] The second stage A2 can be called the self-discharge stage. The signal of the third scanning signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scanning signal line S13 changes from a low-level signal to a high-level signal, causing the first transistor T1 to be disconnected first, and the first node N1 to float. Subsequently, the signal of the second scanning signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to be disconnected, and the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and begins to discharge, and the potential of the second node N2 drops. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged, and thus the potential of the first node N1 drops as the potential of the second node N2 drops. Due to the back-gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, and thus the equivalent threshold voltage |V th_EF |As the potential of the second node N2 decreases, the equivalent threshold voltage of the third transistor T3 gradually increases. th_EF |=α(ELVDD-Vs)+|Vth|, α is the back gate coefficient. When the equivalent threshold voltage of the third transistor T3 |V th_EF When Vgs increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off and the second node N2 stops discharging.

[0078] The third stage A3 can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 is continuously off. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 is continuously on. The signal of the first scan signal line S13 changes from a high-level signal to a low-level signal, turning on the first transistor T1. Turning on the first transistor T1 causes the data voltage Vdata output by the data signal line DATA to be written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Because the second node N2 is floating, threshold compensation can be achieved in this stage.

[0079] The fourth phase A4 can be referred to as the light-emitting phase. The signals on the second and third scan signal lines S2 and S3 are low-level signals, while the signal on the first scan signal line S1 is high-level. This turns on the second transistor T2, while the first and fourth transistors T1 and T4 are off. Turning on the second transistor T2 causes the power supply voltage output from the first power line VDD to provide a driving voltage to the first electrode of the light-emitting device EL through the turned-on second and third transistors T2 and T3, driving the light-emitting device EL to emit light.

[0080] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0081] An exemplary embodiment of the present disclosure provides a display substrate, comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel comprises a pixel driving circuit and at least one scan signal line, the scan signal line being configured to provide a scan signal to the pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit being connected to a scan signal line in a pixel row in the display area; at least one gate driving circuit comprises a shift register circuit, a logic operation circuit, a level converter, and a row driver enhancer sequentially arranged in a direction close to the display area, the shift register circuit being configured to generate a row-by-row shifted timing according to a timing signal, the logic operation circuit being configured to generate a target timing through a logic operation, the level converter being configured to perform voltage domain conversion on the target timing, and the row driver enhancer being configured To enhance the converted signal; the shift register circuit includes at least a plurality of transistor groups arranged in sequence along a first direction, at least one transistor group includes a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction, and the first direction and the second direction intersect; the P-type transistor includes at least a P-type active area, and the N-type transistor includes at least an N-type active area. In the second direction, there is a gap area between the P-type active area and the N-type active area, and the gap area has a gap center line, which is a straight line that bisects the gap area in the second direction and extends in the first direction; the plurality of transistor groups form at least one transmission gate, at least one NAND gate and at least one inverter, and the gap center lines of the transistor groups in the at least one transmission gate, the at least one NAND gate and the at least one inverter are on the same straight line extending along the first direction.

[0082] In an exemplary embodiment, a plurality of transistor groups form a first transmission gate, a first NAND gate, a third inverter, a second transmission gate, a third transmission gate, a second NAND gate, a fourth inverter, a second inverter, and a first inverter, which are sequentially arranged along a direction close to the display area; the widths of the gap regions of the transistor groups in the same type of devices are the same, the center lines of the gaps of the transistor groups in the same type of devices are on the same straight line extending along the first direction, and the width of the gap regions is the dimension in the second direction.

[0083] In an exemplary embodiment, the width-to-length ratios of P-type transistors in devices of the same type are the same, and the width-to-length ratios of N-type transistors in devices of the same type are the same.

[0084] In an exemplary embodiment, in at least one of the first inverter, the second inverter, the third inverter, and the fourth inverter, a ratio of a width-to-length ratio of the P-type transistor to a width-to-length ratio of the N-type transistor is greater than 1 and less than 3.

[0085] In an exemplary embodiment, the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first NAND gate is greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter, and the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter is greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first transmission gate.

[0086] In an exemplary embodiment, the shift register circuit further includes a power active region and a ground active region, the power active region being arranged on a side of the P-type active region away from the N-type active region, and the ground active region being arranged on a side of the N-type active region away from the P-type active region, the power active region having a first center line, and the ground active region having a second center line, the first center line being a straight line that bisects the power active region in the second direction and extends along the first direction, the second center line being a straight line that bisects the ground active region in the second direction and extends along the first direction, and in the second direction, a distance between the first center line and the second center line is less than or equal to 6.3 μm.

[0087] In an exemplary embodiment, in at least one transistor group, the P-type transistor includes at least a P-type active area, and the N-type transistor includes at least an N-type active area; a first width is provided between the first center line and an edge of the P-type active area on a side close to the first center line, and a second width is provided between the second center line and an edge of the N-type active area on a side close to the second center line. The first width may be greater than 1 μm and less than 3 μm, and the second width may be greater than 1 μm and less than 3 μm. The first width and the second width are dimensions in the second direction.

[0088] In an exemplary embodiment, in at least one transistor group, a third width is present between an edge of the P-type active region away from the first center line and an edge of the N-type active region away from the second center line, and the third width is greater than or equal to 1.5 μm, and the third width is a dimension in the second direction.

[0089] In an exemplary embodiment, the P-type active area has a P-type active area width between an edge of the P-type active area close to the first center line and an edge of the P-type active area away from the first center line; the N-type active area has an N-type active area width between an edge of the N-type active area close to the second center line and an edge of the N-type active area away from the second center line; the P-type active area width may be greater than 1 μm and less than 3 μm, and the N-type active area width may be greater than 1 μm and less than 3 μm, and the P-type active area width and the N-type active area width are dimensions in the second direction.

[0090] The technical solution of the display substrate disclosed herein is described below through exemplary embodiments.

[0091] Figure 6 is a structural schematic diagram of a gate drive circuit of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the gate drive device can be arranged in a non-display area, can be located on one side of the pixel row direction of the display area, or can be located on both sides of the pixel row direction of the display area. The gate drive device can include multiple cascaded gate drive circuits, at least one gate drive circuit is connected to the scan signal line in a pixel row in the display area, and provides a scan signal to the connected scan signal line. When the gate drive device is arranged on both sides of the pixel row direction of the display area, the scan signal line in the pixel row is driven by two gate drive circuits to form a bilateral drive structure, which can ensure the driving capability of high pixel density and avoid distortion of the drive signal. As shown in Figure 6, the gate drive circuit may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level converter (Level shifter) 300 and a line driver enhancer (Line Driver) 400.

[0092] In an exemplary embodiment, the shift register circuit 100 may be a shift register circuit composed of flip-flops (D Flip Flops). The shift register circuit 100 is connected to the display driver circuit and receives timing signals generated by the display driver circuit. The timing signals may include a start signal STV and a clock signal CKV. The shift register circuit 100 is configured to shift and register the received timing signals to initially generate a timing sequence that can be shifted row by row. The logic operation circuit 200 is connected to the shift register circuit 100 and configured to perform a logic operation on the shifted signals to generate a plurality of target timing sequences with different waveforms. The level converter 300 is connected to the logic operation circuit 200 and configured to perform voltage domain conversion on the target timing sequences. The row driver booster 400 is connected to the level converter 300 and configured to boost the converted signals to enhance output capability and output scan signals to the display area.

[0093] In an exemplary embodiment, for a pixel driving circuit in a display area including a first scan signal line S1, a second scan signal line S2, and a third scan signal line S3, the output circuit composed of the level converter 300 and the row driver enhancer 400 may include three output sub-circuits, one output sub-circuit being connected to the first scan signal line S1 of a pixel row in the display area and being configured to output a first scan signal to the display area, another output sub-circuit being connected to the second scan signal line S2 of a pixel row in the display area and being configured to output a second scan signal to the display area, and yet another output sub-circuit being connected to the third scan signal line S3 of a pixel row in the display area and being configured to output a third scan signal to the display area.

[0094] In an exemplary embodiment, the first scan signal may be referred to as a write switch (WS) signal, configured to control the on / off switching of a first transistor T1 in a pixel driving circuit. The second scan signal may be referred to as a display switch (DS) signal, configured to control the on / off switching of a second transistor T2 in the pixel driving circuit. The third scan signal may be referred to as a display reset (Auto Zero, AZ) signal, configured to control the on / off switching of a fourth transistor T4 in the pixel driving circuit.

[0095] In an exemplary embodiment, since signals such as the start signal and the clock signal are output by the display driver circuit, their voltage domains are inconsistent with the voltage domains of the pixel driver circuit. By converting the voltage through a level converter, the required voltage (0V to -2V & -5V) is introduced to ensure that the voltage of the output gate drive signal matches the pixel driver circuit.

[0096] In an exemplary embodiment, the start signal STV may be referred to as a frame start signal, with a period of one frame, and the clock signal CKV may be referred to as a row driving clock signal, with a period of one row.

[0097] FIG7 is a diagram illustrating the operating principle of a shift register circuit according to an exemplary embodiment of the present disclosure. The shift register circuit may be a shift register circuit composed of a flip-flop (D Flip Flop), and may include nine parts, namely three transmission gates (TG), four inverters (INVX), and two NAND gates (NAND). The inverters may also be referred to as NOT gates. As shown in FIG7 , the shift register circuit may include a first transmission gate 201, a second transmission gate 202, a third transmission gate 203, a first NAND gate 301, a second NAND gate 302, a first inverter 401, a second inverter 402, a third inverter 403, and a fourth inverter 404.

[0098] In an exemplary embodiment, the input terminal of the first inverter 401 is connected to the clock signal terminal CK of the shift register circuit, and the output terminal of the first inverter 401 is connected to the first node CK_. The input terminal of the second inverter 402 is connected to the first node CK_, and the output terminal of the second inverter 402 is connected to the second node CK'. The first terminal of the first transmission gate 201 is connected to the input terminal D of the shift register circuit, the second terminal of the first transmission gate 201 is connected to the output terminal of the third inverter 403 and the first input terminal of the first NAND gate 301, respectively, the high-level active enable terminal of the first transmission gate 201 is connected to the first node CK_, and the low-level active enable terminal of the first transmission gate 201 is connected to the second node CK'. The second input terminal of the first NAND gate 301 is connected to the reset terminal RN of the shift register circuit. The output terminal of the first NAND gate 301 is respectively connected to the input terminal of the third inverter 403 and the first terminal of the second transmission gate 202. The high-level active enable terminal of the third inverter 403 is connected to the second node CK', and the low-level active enable terminal of the third inverter 403 is connected to the first node CK_. The second terminal of the second transmission gate 202 is respectively connected to the input terminal of the fourth inverter 404 and the first terminal of the third transmission gate 203. The high-level active enable terminal of the second transmission gate 202 is connected to the second node CK', and the low-level active enable terminal of the second transmission gate 202 is connected to the first node CK_. An output terminal of the fourth inverter 404 is connected to a first input terminal of the second NAND gate 302 and a first output terminal Q of the shift register circuit. A second terminal of the third transmission gate 203 is respectively connected to an output terminal of the second NAND gate 302 and a second output terminal Q_ of the shift register circuit. A high-level effective enable terminal of the third transmission gate 203 is connected to a first node CK_. A low-level effective enable terminal of the third transmission gate 203 is connected to a second node CK'. A second input terminal of the second NAND gate 302 is connected to a reset terminal RN of the shift register circuit.

[0099] In an exemplary embodiment, the shift register circuit is valid on a rising edge. When each rising edge arrives, the output maintains the state of the D input in the previous stage. N is reset, and the shift register circuit is valid when the high level is high. The working principle of the shift register circuit is:

[0100] (1) When the input signal of the clock signal terminal CK of the shift register circuit is 0 and the input signal of the input terminal D of the shift register circuit is 0, the first transmission gate 201 is turned on, the second transmission gate 202 is turned off, and the third transmission gate 203 is turned on. The output of the first output terminal Q of the shift register circuit is 0, and the output of the second output terminal Q_ of the shift register circuit is 1.

[0101] (2) When the input signal of the clock signal terminal CK of the shift register circuit is 1 and the input signal of the input terminal D of the shift register circuit is 0, the first transmission gate 201 is disconnected, the second transmission gate 202 is turned on, and the third transmission gate 203 is disconnected. The output of the first output terminal Q of the shift register circuit is 0, and the output of the second output terminal Q_ of the shift register circuit is 1.

[0102] (3) When the input signal of the clock signal terminal CK of the shift register circuit is 0 and the input signal of the input terminal D of the shift register circuit is 1, the first transmission gate 201 is turned on, the second transmission gate 202 is turned off, and the third transmission gate 203 is turned on. The second transmission gate 202 latches back and maintains the output;

[0103] (4) When the input signal of the clock signal terminal CK of the shift register circuit is 1 and the input signal of the input terminal D of the shift register circuit is 0, the first transmission gate 201 is disconnected, the second transmission gate 202 is turned on, and the third transmission gate 203 is disconnected. The output of the first output terminal Q of the shift register circuit is 0, and the output of the second output terminal Q_ of the shift register circuit is 1.

[0104] (5) When the input signal of the clock signal terminal CK of the shift register circuit is 0 and the input signal of the input terminal D of the shift register circuit is 1, the first transmission gate 201 is turned on, the second transmission gate 202 is turned off, and the third transmission gate 203 is turned on. The second transmission gate 202 latches back and maintains the output;

[0105] (6) When the input signal of the clock signal terminal CK of the shift register circuit is 1 and the input signal of the input terminal D of the shift register circuit is 0, the first transmission gate 201 is turned off, the second transmission gate 202 is turned on, and the third transmission gate 203 is turned off, and the output of the first output terminal Q of the shift register circuit is high level.

[0106] Figure 8 is an equivalent circuit diagram of a shift register circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 8, the shift register circuit of the gate driver circuit in the display substrate of the present embodiment can include 24 transistors. The first transmission gate 201, the second transmission gate 202, the third transmission gate 203, the first inverter 401, the second inverter 402, and the fourth inverter 404 each include one P-type transistor and one N-type transistor, and the first NAND gate 301, the second NAND gate 302, and the third inverter 403 each include two P-type transistors and two N-type transistors.

[0107] In an exemplary embodiment, the first transmission gate 201, the first NAND gate 301, the third inverter 403, the second transmission gate 202, the third transmission gate 203, the second NAND gate 302, the fourth inverter 404, the second inverter 402 and the first inverter 401 can be arranged in sequence along the first direction X (the direction close to the display area).

[0108] In an exemplary embodiment, the first P-type transistor P1 and the first N-type transistor N1 constitute a first transmission gate 201. The gate electrode of the first P-type transistor P1 is connected to the gate electrode of the fifth N-type transistor N5, the gate electrode of the sixth N-type transistor N6, the gate electrode of the seventh P-type transistor P7, the second electrode of the eleventh P-type transistor P11, and the second electrode of the eleventh N-type transistor N11, respectively. The gate electrode of the first N-type transistor N1 is connected to the gate electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, the gate electrode of the seventh N-type transistor N7, the gate electrode of the eleventh P-type transistor P11, the gate electrode of the eleventh N-type transistor N11, respectively. The first electrode of the first P-type transistor P1 and the first electrode of the first N-type transistor N1 are connected to the gate electrode of the second P-type transistor P2, the gate electrode of the second N-type transistor N2, the second electrode of the fifth P-type transistor P5 and the second electrode of the fifth N-type transistor N5, respectively.

[0109] In an exemplary embodiment, the second P-type transistor P2 , the third P-type transistor P3 , the second N-type transistor N2 , and the third N-type transistor N3 constitute a first NAND gate 301 . The gate electrode of the second P-type transistor P2 and the gate electrode of the second N-type transistor N2 are connected to each other, and are respectively connected to the second electrode of the first P-type transistor P1, the second electrode of the first N-type transistor N1, the second electrode of the fifth P-type transistor P5, and the second electrode of the fifth N-type transistor N5. The gate electrode of the third P-type transistor P3 and the gate electrode of the third N-type transistor N3 are connected to each other and to the reset terminal RN. The first electrode of the second P-type transistor P2 and the first electrode of the third P-type transistor P3 are both connected to the first power supply line VDD. The second electrode of the second P-type transistor P2 and the second electrode of the third P-type transistor P3 are connected to each other, and are respectively connected to the second electrode of the second N-type transistor N2, the gate electrode of the fourth P-type transistor P4, the gate electrode of the fourth N-type transistor N4, the first electrode of the sixth P-type transistor P6, and the first electrode of the sixth N-type transistor N6. The first electrode of the third N-type transistor N3 is connected to the ground line GND, and the second electrode of the third N-type transistor N3 is connected to the first electrode of the second N-type transistor N2.

[0110] In an exemplary embodiment, the fourth P-type transistor P4, the fifth P-type transistor P5, the fourth N-type transistor N4, and the fifth N-type transistor N5 constitute a third inverter 403. The gate electrode of the fourth P-type transistor P4 and the gate electrode of the fourth N-type transistor N4 are connected to each other, and are respectively connected to the second electrode of the second P-type transistor P2, the second electrode of the second N-type transistor N2, the second electrode of the third P-type transistor P3, the first electrode of the sixth P-type transistor P6, and the first electrode of the sixth N-type transistor N6. The gate electrode of the fifth P-type transistor P5 is respectively connected to the gate electrode of the first N-type transistor N1, the gate electrode of the sixth P-type transistor P6, the gate electrode of the seventh N-type transistor N7, the gate electrode of the eleventh P-type transistor P11, the gate electrode of the eleventh N-type transistor N11, the second electrode of the twelfth P-type transistor P12, and the second electrode of the twelfth N-type transistor N12. The gate electrode of the fifth N-type transistor N5 is respectively connected to the gate electrode of the first P-type transistor P1, The gate electrode of the sixth N-type transistor N6, the gate electrode of the seventh P-type transistor P7, the second electrode of the eleventh P-type transistor P11 and the second electrode of the eleventh N-type transistor N11 are connected, the first electrode of the fourth P-type transistor P4 is connected to the first power line VDD, the second electrode of the fourth P-type transistor P4 is connected to the first electrode of the fifth P-type transistor P5, the first electrode of the fourth N-type transistor N4 is connected to the ground line GND, the second electrode of the fourth N-type transistor N4 is connected to the first electrode of the fifth N-type transistor N5, the second electrode of the fifth P-type transistor P5 and the second electrode of the fifth N-type transistor N5 are connected to each other, and are respectively connected to the second electrode of the first P-type transistor P1, the second electrode of the first N-type transistor N1, the gate electrode of the second P-type transistor P2 and the gate electrode of the second N-type transistor N2.

[0111] In an exemplary embodiment, the sixth P-type transistor P6 and the sixth N-type transistor N6 constitute the second transmission gate 202. The gate electrode of the sixth P-type transistor P6 is respectively connected to the gate electrode of the first N-type transistor N1, the gate electrode of the fifth P-type transistor P5, the gate electrode of the seventh N-type transistor N7, the gate electrode of the eleventh P-type transistor P11, the gate electrode of the eleventh N-type transistor N11, the second electrode of the twelfth P-type transistor P12, and the second electrode of the twelfth N-type transistor N12, and the gate electrode of the sixth N-type transistor N6 is respectively connected to the gate electrode of the first P-type transistor P1, the gate electrode of the fifth N-type transistor N5, the gate electrode of the seventh P-type transistor P7, the second electrode of the eleventh P-type transistor P11, and the second electrode of the eleventh N-type transistor N1 1, the first electrode of the sixth P-type transistor P6 and the first electrode of the sixth N-type transistor N6 are connected to each other, and are respectively connected to the second electrode of the second P-type transistor P2, the second electrode of the third P-type transistor P3, the second electrode of the second N-type transistor N2, the gate electrode of the fourth P-type transistor P4, and the gate electrode of the fourth N-type transistor N4; the second electrode of the sixth P-type transistor P6 and the second electrode of the sixth N-type transistor N6 are connected to each other, and are respectively connected to the first electrode of the seventh P-type transistor P7, the first electrode of the seventh N-type transistor N7, the gate electrode of the tenth P-type transistor P10, and the gate electrode of the tenth N-type transistor N10.

[0112] In the exemplary embodiment, the seventh P-type transistor P7 and the seventh N-type transistor N7 constitute the third transmission gate 203. The gate electrode of the seventh P-type transistor P7 is respectively connected to the gate electrode of the first P-type transistor P1, the gate electrode of the fifth N-type transistor N5, the gate electrode of the sixth N-type transistor N6, the second electrode of the eleventh P-type transistor P11, and the second electrode of the eleventh N-type transistor N11, and the gate electrode of the seventh N-type transistor N7 is respectively connected to the gate electrode of the first N-type transistor N1, the gate electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, the gate electrode of the eleventh P-type transistor P11, the gate electrode of the eleventh N-type transistor N11, and the gate electrode of the twelfth P-type transistor P12. The second electrode is connected to the second electrode of the twelfth N-type transistor N12, the first electrode of the seventh P-type transistor P7 and the first electrode of the seventh N-type transistor N7 are connected to each other, and are respectively connected to the second electrode of the sixth P-type transistor P6, the second electrode of the sixth N-type transistor N6, the gate electrode of the tenth P-type transistor P10 and the gate electrode of the tenth N-type transistor N10, the second electrode of the seventh P-type transistor P7 and the second electrode of the seventh N-type transistor N7 are connected to each other, and are respectively connected to the second electrode of the eighth P-type transistor P8, the second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9.

[0113] In an exemplary embodiment, an eighth P-type transistor P8, a ninth P-type transistor P9, an eighth N-type transistor N8, and a ninth N-type transistor N9 form a second NAND gate 302. A gate electrode of the eighth P-type transistor P8 and a gate electrode of the eighth N-type transistor N8 are connected to each other and to a reset terminal RN of the shift register circuit. A gate electrode of the ninth P-type transistor P9 and a gate electrode of the ninth N-type transistor N9 are connected to each other and to the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10, respectively. A first electrode of the eighth P-type transistor P8 and a first electrode of the ninth P-type transistor P9 are both connected to a first power supply line VDD. A second electrode of the eighth P-type transistor P8 and a second electrode of the ninth P-type transistor P9 are connected to each other and to the second electrode of the ninth N-type transistor N9, the second electrode of the seventh P-type transistor P7, and the second electrode of the seventh N-type transistor N7, respectively. A first electrode of the eighth N-type transistor N8 is connected to a ground line GND, and a second electrode of the eighth N-type transistor N8 is connected to a first electrode of the ninth N-type transistor N9.

[0114] In an exemplary embodiment, a tenth P-type transistor P10 and a tenth N-type transistor N10 form a fourth inverter 404. The gate electrode of the tenth P-type transistor P10 and the gate electrode of the tenth N-type transistor N10 are connected to each other and are respectively connected to the second electrode of the sixth P-type transistor P6, the second electrode of the sixth N-type transistor N6, the first electrode of the seventh P-type transistor P7, and the first electrode of the seventh N-type transistor N7. The first electrode of the tenth P-type transistor P10 is connected to the first power supply line VDD, the first electrode of the tenth N-type transistor N10 is connected to the ground line GND, and the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10 are connected to each other and are respectively connected to the gate electrode of the ninth P-type transistor P9 and the gate electrode of the ninth N-type transistor N9.

[0115] In an exemplary embodiment, an eleventh P-type transistor P11 and an eleventh N-type transistor N11 constitute a second inverter 402. The gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11 are connected to each other, and are connected to the gate electrode of the first N-type transistor N1, the gate electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, the gate electrode of the seventh N-type transistor N7, the second electrode of the twelfth P-type transistor P12, and the second electrode of the twelfth N-type transistor N12, respectively. A first electrode of the eleventh P-type transistor P11 is connected to a first power supply line VDD, a first electrode of the eleventh N-type transistor N11 is connected to a ground line GND, and a second electrode of the eleventh P-type transistor P11 and the second electrode of the eleventh N-type transistor N11 are connected to each other, and are connected to the gate electrode of the first P-type transistor P1, the gate electrode of the fifth N-type transistor N5, the gate electrode of the sixth N-type transistor N6, and the gate electrode of the seventh P-type transistor P7, respectively.

[0116] In the exemplary embodiment, the twelfth P-type transistor P12 and the twelfth N-type transistor N12 form a first inverter 401. The gate electrode of the twelfth P-type transistor P12 and the gate electrode of the twelfth N-type transistor N12 are connected to each other and to the clock signal terminal CK of the shift register circuit. The first electrode of the twelfth P-type transistor P12 is connected to the first power supply line VDD, the first electrode of the twelfth N-type transistor N12 is connected to the ground line GND, and the second electrode of the twelfth P-type transistor P12 and the second electrode of the twelfth N-type transistor N12 are connected to each other and to the gate electrode of the first N-type transistor N1, the gate electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, the gate electrode of the seventh N-type transistor N7, the gate electrode of the eleventh P-type transistor P11, and the gate electrode of the eleventh N-type transistor N11, respectively.

[0117] FIG9 is a schematic diagram of the structure of a shift register circuit according to an exemplary embodiment of the present disclosure. In an exemplary embodiment, the display substrate of the exemplary embodiment of the present disclosure may include at least a display area and a non-display area. The display area may include a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, at least one sub-pixel including a pixel driver circuit and at least one scan signal line, the scan signal line being configured to provide a scan signal to the connected pixel driver circuit. The non-display area may include a plurality of cascaded gate driver circuits, at least one gate driver circuit being connected to a scan signal line in a pixel row in the display area. The at least one gate driver circuit may include a shift register circuit, a logic operation circuit, a level shifter, and a row driver enhancer disposed on a silicon substrate. The shift register circuit is configured to generate a row-by-row shift timing based on a timing signal, the logic operation circuit is configured to generate a target timing through a logic operation, the level shifter is configured to perform voltage domain conversion on the target timing, and the row driver enhancer is configured to enhance the converted signal and output it to the scan signal line in the display area.

[0118] As shown in Figure 9, the shift register circuit may include a plurality of transistor groups arranged in sequence along a first direction X (the direction of pixel rows in the display area), at least one transistor group may include a P-type transistor and an N-type transistor arranged on one side of the P-type transistor in a second direction Y (the direction of pixel columns in the display area), and the first direction X and the second direction Y intersect.

[0119] In an exemplary embodiment, the P-type transistor may include at least a P-type active region, and the N-type transistor may include at least an N-type active region. In the second direction Y, a gap region 50 is provided between the P-type active region and the N-type active region. The gap region 50 has a gap center line OC. The gap center line OC may be a straight line that bisects the gap region 50 in the second direction Y and extends in the first direction X.

[0120] In an exemplary embodiment, the plurality of transistor groups may form at least one transmission gate, at least one NAND gate, and at least one inverter, and gap center lines OC of the transistor groups in the at least one transmission gate, the at least one NAND gate, and the at least one inverter may be on the same straight line extending along the first direction X.

[0121] In an exemplary embodiment, a plurality of transistor groups form a first transmission gate 201, a first NAND gate 301, a third inverter 403, a second transmission gate 202, a third transmission gate 203, a second NAND gate 302, a fourth inverter 404, a second inverter 402, and a first inverter 401, which are sequentially arranged in a direction close to the display area. The widths of the gap regions of the transistor groups in the same type of device may be substantially the same, and the center lines of the gaps of the transistor groups in the same type of device may be substantially on the same straight line extending in the first direction X. The width of the gap region may be a dimension in the second direction Y.

[0122] In an exemplary embodiment, the first transmission gate 201 may include a first P-type transistor P1 and a second P-type transistor P2, the first NAND gate 301 may include a second P-type transistor P2, a third P-type transistor P3, a second N-type transistor N2, and a third N-type transistor N3, the third inverter 403 may include a fourth P-type transistor P4, a fifth P-type transistor P5, a fourth N-type transistor N4, and a fifth N-type transistor N5, the second transmission gate 202 may include a sixth P-type transistor P6 and a sixth N-type transistor N6, and the third transmission gate 203 may include a sixth P-type transistor P7 and a sixth N-type transistor N8. 03 may include a seventh P-type transistor P7 and a seventh N-type transistor N7, the second NAND gate 302 may include an eighth P-type transistor P8, a ninth P-type transistor P9, an eighth N-type transistor N8 and a ninth N-type transistor N9, the fourth inverter 404 may include a tenth P-type transistor P10 and a tenth N-type transistor N10, the second inverter 402 may include an eleventh P-type transistor P11 and an eleventh N-type transistor N11, and the first inverter 401 may include a twelfth P-type transistor P12 and a twelfth N-type transistor N12.

[0123] In an exemplary embodiment, in at least one transistor group, the P-type transistor may include a P-type gate electrode, a P-type active region, a P-type source electrode (first electrode), and a P-type drain electrode (second electrode), wherein the P-type source electrode is connected to the first region of the P-type active region through a via, and the P-type drain electrode is connected to the second region of the P-type active region through a via. The N-type transistor may include an N-type gate electrode, an N-type active region, an N-type source electrode (first electrode), and an N-type drain electrode (second electrode), wherein the N-type source electrode is connected to the first region of the N-type active region through a via, and the N-type drain electrode is connected to the second region of the N-type active region through a via.

[0124] In an exemplary embodiment, the shift register circuit may further include a power active region 100P, a ground active region 100N, a first power line 51, and a ground line 52. The power active region 100P and the first power line 51 may be in the shape of a straight line or a zigzag line extending along a first direction X, and may be located on one side of the plurality of transistor groups in the opposite direction of a second direction Y. The first power line 51 may be connected to the power active region 100P via a plurality of vias. The ground active region 100N and the ground line 52 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be located on one side of the plurality of transistor groups in the second direction Y. The ground line 52 may be connected to the ground active region 100N via a plurality of vias.

[0125] In an exemplary embodiment, the power active area 100P and the ground active area 100N may be disposed on the same layer as the P-type active area and the N-type active area, and the first power line 51 and the ground line 52 may be disposed on the same layer as the P-type source electrode, the P-type drain electrode, the N-type source electrode, and the N-type drain electrode.

[0126] In an exemplary embodiment, the shift register circuit has a circuit width W0, which may be a distance between the first center line O1 and the second center line O2, and may be a dimension in the second direction Y. In an exemplary embodiment, the first center line O1 may be a straight line that bisects the power active area 100P in the second direction Y and extends along the first direction X, and the second center line O2 may be a straight line that bisects the ground active area 100N in the second direction Y and extends along the first direction X.

[0127] In an exemplary embodiment, the circuit width W0 may be less than or equal to the width of a pixel row in the display area.

[0128] In an exemplary embodiment, the circuit width W0 may be less than or equal to 6.3 μm, so that the width of the gate driving circuit is substantially consistent with the width of the sub-pixel in the pixel area, meeting the display requirement of a pixel density of 4000.

[0129] In an exemplary embodiment, in at least one transistor group, a first width W1 is provided between an edge of the P-type active region of the P-type transistor on a side close to the first center line O1 and the first center line O1, a second width W2 is provided between an edge of the N-type active region of the N-type transistor on a side close to the second center line O2 and the second center line O2, and a third width W3 is provided between an edge of the P-type active region on a side away from the first center line O1 and an edge of the N-type active region on a side away from the second center line O2. The first width W1, the second width W2, and the third width W3 may be dimensions in the second direction Y.

[0130] In exemplary embodiments, the first width W1 may be greater than or equal to 0.2 μm.

[0131] In exemplary embodiments, the second width W2 may be greater than or equal to 0.2 μm.

[0132] In exemplary embodiments, the third width W3 may be greater than or equal to 1.5 μm.

[0133] In an exemplary embodiment, in at least one transistor group, a P-type active region width WP is defined between an edge of the P-type active region on a side closer to the first center line O1 and an edge of the P-type active region on a side further from the first center line O1. The P-type active region width WP is the P-type channel width of the P-type transistor and may be the dimension in the second direction Y. An N-type active region width WN is defined between an edge of the N-type active region on a side closer to the second center line O2 and an edge of the N-type active region on a side further from the second center line O2. That is, the N-type active region width WN is the N-type channel width of the N-type transistor and may be the dimension in the second direction Y.

[0134] In example embodiments, the P-type active region width WP may be greater than 0.556 μm, and the N-type active region width WN may be greater than 0.556 μm.

[0135] In an exemplary embodiment, the circuit width W0 may be the sum of the first width W1 , the P-type active region width WP, the third width W3 , the N-type active region width WN, and the second width W2 .

[0136] In an exemplary embodiment, in at least one transistor group, a width-to-length ratio of a P-type transistor may be greater than a width-to-length ratio of an N-type transistor.

[0137] In an exemplary embodiment, a ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor may be greater than 1 and less than 3.

[0138] The following is an illustrative explanation through the preparation process of the display device. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display device. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0139] In an exemplary embodiment, a process of preparing a display substrate may include the following steps.

[0140] (1) Provide a silicon substrate. In an exemplary embodiment, the silicon substrate may be a P-type silicon substrate. In an exemplary embodiment, the P-type silicon substrate may serve as a channel region of an N-type transistor.

[0141] In some possible implementations, the silicon substrate may be an N-type silicon material, which may serve as a channel region of a P-type transistor, and this disclosure does not limit this.

[0142] (2) Sequentially forming N-type well (NW) region and active area (AA) patterns. In an exemplary embodiment, a photoresist pattern including an opening region can be formed by coating a photoresist on a P-type silicon substrate, exposing and developing the photoresist, removing the photoresist in the opening region to expose the surface of the P-type silicon substrate, and implanting n-type dopant ions in the opening region by ion implantation. The remaining photoresist is stripped off to form an N-type well region 10 pattern on the P-type silicon substrate. Subsequently, an active area pattern is formed on the silicon substrate on which the aforementioned pattern is formed, as shown in FIG10A and FIG10B , FIG10B being a schematic diagram of the active area in FIG10A .

[0143] In an exemplary embodiment, the N-well region 10 is configured to form a P-type transistor and a P-type device, and the region other than the N-well region 10 is configured to form an N-type transistor and an N-type device.

[0144] In an exemplary embodiment, n-type dopant ions may be implanted using ion implanters such as phosphorus or arsenic. The depth and doping concentration of the ion implantation can be controlled by controlling the implantation energy and dose. The process for forming the N-well region may also include annealing and other processes to allow the ion implanter to diffuse into the P-type silicon substrate, forming a stable N-well structure.

[0145] In example embodiments, the active area pattern may include at least first to twelfth P-type active regions 101P to 112P, first to twelfth N-type active regions 101N to 112N, a power active region 100P, and a ground active region 100N.

[0146] In an exemplary embodiment, the first P-type active region 101P may be located within the region where the N-well region 10 is located, and the orthographic projection of the first P-type active region 101P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The first P-type active region 101P may be in the shape of a strip extending along the first direction X, and the first P-type active region 101P may serve as the active region of the first P-type transistor P1.

[0147] In an exemplary embodiment, the first N-type active region 101N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the first N-type active region 101N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The first N-type active region 101N may be in the shape of a strip extending along a first direction X and located on one side of the first P-type active region 101P in the second direction Y. The first N-type active region 101N may serve as the active region of the first N-type transistor N1.

[0148] In an exemplary embodiment, the second P-type active region 102P may be located within the region where the N-well region 10 is located, and the orthographic projection of the second P-type active region 102P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The second P-type active region 102P may be in the shape of a strip extending along the first direction X, and the second P-type active region 102P may serve as the active region of the second P-type transistor P2.

[0149] In an exemplary embodiment, the second N-type active region 102N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the second N-type active region 102N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The second N-type active region 102N may be in the shape of a strip extending along the first direction X and located on one side of the second P-type active region 102P in the second direction Y. The second N-type active region 102N may serve as the active region of the second N-type transistor N2.

[0150] In an exemplary embodiment, the third P-type active region 103P may be located within the region where the N-well region 10 is located, and the orthographic projection of the third P-type active region 103P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The third P-type active region 103P may be in the shape of a strip extending along the first direction X, and the third P-type active region 103P may serve as the active region of the third P-type transistor P3.

[0151] In an exemplary embodiment, the second P-type active region 102P and the third P-type active region 103P may be an integral structure connected to each other.

[0152] In an exemplary embodiment, the third N-type active region 103N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the third N-type active region 103N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The third N-type active region 103N may be in the shape of a strip extending along the first direction X and located on one side of the third P-type active region 103P in the second direction Y. The third N-type active region 103N may serve as the active region of the third N-type transistor N3.

[0153] In an exemplary embodiment, the second N-type active region 102N and the third N-type active region 103N may be an integral structure connected to each other.

[0154] In an exemplary embodiment, the fourth P-type active region 104P may be located within the region where the N-well region 10 is located, and the orthographic projection of the fourth P-type active region 104P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The fourth P-type active region 104P may be in the shape of a strip extending along the first direction X, and the fourth P-type active region 104P may serve as the active region of the fourth P-type transistor P4.

[0155] In an exemplary embodiment, the fourth N-type active region 104N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the fourth N-type active region 104N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The fourth N-type active region 104N may be in the shape of a strip extending along the first direction X and located on one side of the fourth P-type active region 104P in the second direction Y. The fourth N-type active region 104N may serve as the active region of the fourth N-type transistor N4.

[0156] In an exemplary embodiment, the fifth P-type active region 105P may be located within the region where the N-well region 10 is located, and the orthographic projection of the fifth P-type active region 105P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The fifth P-type active region 105P may be in the shape of a strip extending along the first direction X, and the fifth P-type active region 105P may serve as the active region of the fifth P-type transistor P5.

[0157] In an exemplary embodiment, the fourth P-type active region 104P and the fifth P-type active region 105P may be an integral structure connected to each other.

[0158] In an exemplary embodiment, the fifth N-type active region 105N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the fifth N-type active region 105N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The fifth N-type active region 105N may be in the shape of a strip extending along the first direction X and located on one side of the fifth P-type active region 105P in the second direction Y. The fifth N-type active region 105N may serve as the active region of the fifth N-type transistor N5.

[0159] In an exemplary embodiment, the fourth N-type active region 104N and the fifth N-type active region 105N may be an integral structure connected to each other.

[0160] In an exemplary embodiment, the sixth P-type active region 106P may be located within the region where the N-well region 10 is located, and the orthographic projection of the sixth P-type active region 106P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The sixth P-type active region 106P may be in the shape of a strip extending along the first direction X, and the sixth P-type active region 106P may serve as the active region of the sixth P-type transistor P6.

[0161] In an exemplary embodiment, the sixth N-type active region 106N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the sixth N-type active region 106N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The sixth N-type active region 106N may be in the shape of a strip extending along the first direction X and located on one side of the sixth P-type active region 106P in the second direction Y. The sixth N-type active region 106N may serve as the active region of the sixth N-type transistor N6.

[0162] In an exemplary embodiment, the seventh P-type active region 107P may be located within the region where the N-well region 10 is located, and the orthographic projection of the seventh P-type active region 107P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The seventh P-type active region 107P may be in the shape of a strip extending along the first direction X, and the seventh P-type active region 107P may serve as the active region of the seventh P-type transistor P7.

[0163] In an exemplary embodiment, the seventh N-type active region 107N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the seventh N-type active region 107N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The seventh N-type active region 107N may be in the shape of a strip extending along the first direction X and located on one side of the seventh P-type active region 107P in the second direction Y. The seventh N-type active region 107N may serve as the active region of the seventh N-type transistor N7.

[0164] In an exemplary embodiment, the eighth P-type active region 108P may be located within the region where the N-well region 10 is located, and the orthographic projection of the eighth P-type active region 108P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The eighth P-type active region 108P may be in the shape of a strip extending along the first direction X, and the eighth P-type active region 108P may serve as the active region of the eighth P-type transistor P8.

[0165] In an exemplary embodiment, the eighth N-type active region 108N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the eighth N-type active region 108N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The eighth N-type active region 108N may be in the shape of a strip extending along the first direction X and located on one side of the eighth P-type active region 108P in the second direction Y. The eighth N-type active region 108N may serve as the active region of the eighth N-type transistor N8.

[0166] In an exemplary embodiment, the ninth P-type active region 109P may be located within the region where the N-well region 10 is located, and the orthographic projection of the ninth P-type active region 109P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The ninth P-type active region 109P may be in the shape of a strip extending along the first direction X, and the ninth P-type active region 109P may serve as the active region of the ninth P-type transistor P9.

[0167] In an exemplary embodiment, the eighth P-type active region 108P and the ninth P-type active region 109P may be an integral structure connected to each other.

[0168] In an exemplary embodiment, the ninth N-type active region 109N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the ninth N-type active region 109N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The ninth N-type active region 109N may be in the shape of a strip extending along the first direction X and located on one side of the ninth P-type active region 109P in the second direction Y. The ninth N-type active region 109N may serve as the active region of the ninth N-type transistor N9.

[0169] In an exemplary embodiment, the eighth N-type active region 108N and the ninth N-type active region 109N may be an integral structure connected to each other.

[0170] In an exemplary embodiment, the tenth P-type active region 110P may be located within the region where the N-well region 10 is located, and the orthographic projection of the tenth P-type active region 110P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The tenth P-type active region 110P may be in the shape of a strip extending along the first direction X, and the tenth P-type active region 110P may serve as the active region of the tenth P-type transistor P10.

[0171] In an exemplary embodiment, the tenth N-type active region 110N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the tenth N-type active region 110N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The tenth N-type active region 110N may be in the shape of a strip extending along the first direction X and located on one side of the tenth P-type active region 110P in the second direction Y. The tenth N-type active region 110N may serve as the active region of the tenth N-type transistor N10.

[0172] In an exemplary embodiment, the eleventh P-type active region 111P may be located within the region where the N-well region 10 is located, and the orthographic projection of the eleventh P-type active region 111P on the silicon substrate is located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The eleventh P-type active region 111P may be in the shape of a strip extending along the first direction X. The eleventh P-type active region 111P may serve as the active region of the eleventh P-type transistor P11.

[0173] In an exemplary embodiment, the eleventh N-type active region 111N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the eleventh N-type active region 111N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The eleventh N-type active region 111N may be in the shape of a strip extending along the first direction X and located on one side of the eleventh P-type active region 111P in the second direction Y. The eleventh N-type active region 111N may serve as the active region of the eleventh N-type transistor N11.

[0174] In an exemplary embodiment, the twelfth P-type active region 112P may be located within the region where the N-well region 10 is located, and the orthographic projection of the twelfth P-type active region 112P on the silicon substrate may be located within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The twelfth P-type active region 112P may be in the shape of a strip extending along the first direction X, and the twelfth P-type active region 112P may serve as the active region of the twelfth P-type transistor P12.

[0175] In an exemplary embodiment, the twelfth N-type active region 112N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the twelfth N-type active region 112N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The twelfth N-type active region 112N may be in the shape of a strip extending along the first direction X and located on one side of the twelfth P-type active region 112P in the second direction Y. The twelfth N-type active region 112N may serve as the active region of the twelfth N-type transistor N12.

[0176] In an exemplary embodiment, multiple N-type active regions can be located on one side of the multiple P-type active regions in the second direction Y, forming a compact arrangement layout that is separated in the second direction Y (separated up and down) and arranged sequentially in the first direction X (in a long strip shape).

[0177] In an exemplary embodiment, in the second direction Y, a gap region 50 may be provided between the P-type active region and the N-type active region in a transistor group. The gap region 50 is configured to serve as an isolation region between the P-type transistor and the N-type transistor on the one hand, and is configured to accommodate a gate via connecting the gate conductive layer and the first conductive layer on the other hand, thereby optimizing the structural layout of the gate drive circuit.

[0178] In an exemplary embodiment, the widths of the gap regions 50 in some transistor groups may be substantially the same, and the widths of the gap regions 50 in other transistor groups may be different. The width of the gap region may be a dimension in the second direction Y.

[0179] In an exemplary embodiment, the widths of the gap regions 50 of devices of the same type may be substantially the same. For example, the widths of the gap regions 50 in the first, second, and third transmission gates may be substantially the same. For another example, the widths of the gap regions 50 in the first and second NAND gates may be substantially the same. For another example, the widths of the gap regions 50 in the first, second, third, and fourth inverters may be substantially the same.

[0180] In an exemplary embodiment, the widths of the gap region 50 may differ between different types of devices. For example, the widths of the gap region 50 may differ between the first transmission gate and the first inverter. For another example, the widths of the gap region 50 may differ between the first transmission gate and the first NAND gate. For another example, the widths of the gap region 50 may differ between the first NAND gate and the first inverter.

[0181] In example embodiments, the gap region 50 in one transistor group may have a gap center line OC, which may be a straight line bisecting the gap region 50 in the second direction Y and extending in the first direction X.

[0182] In an exemplary embodiment, the gap center lines OC in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially on the same straight line extending along the first direction X, the gap center lines OC in the first NAND gate and the second NAND gate may be substantially on the same straight line extending along the first direction X, and the gap center lines OC in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially on the same straight line extending along the first direction X. That is, the gap center lines OC of devices of the same type may be substantially on the same straight line extending along the first direction X.

[0183] In an exemplary embodiment, the gap centerlines of the transistor groups in at least one transmission gate, at least one NAND gate, and at least one inverter are located on the same straight line extending along the first direction. That is, the gap centerlines OC of different types of devices may be substantially located on the same straight line extending along the first direction X. For example, the gap centerlines OC of the first transmission gate, the first inverter, and the first NAND gate may be substantially located on the same straight line extending along the first direction X. By arranging the positions of the transmission gates, inverters, and NAND gates, the present disclosure can effectively ensure the shortest possible connection lines between devices, optimize the layout design space, ensure that the resistance and capacitance loading (RC loading) of the gate electrodes of the P-type transistors and the N-type transistors are substantially consistent, and improve uniformity.

[0184] In an exemplary embodiment, the distance between the P-type active region and the N-type active region in one transistor group may be equivalent to the distance between the P-type transistors and the N-type transistors in the transistor group.

[0185] In an exemplary embodiment, the power active region 100P may be located within the region where the N-well region 10 is located, and the orthographic projection of the power active region 100P on the silicon substrate may be within the range of the orthographic projection of the N-well region 10 on the silicon substrate. The power active region 100P may be in the shape of a straight line or a broken line extending along a first direction X. The power active region 100P may be located on one side of the plurality of P-type active regions opposite to the second direction Y, that is, on a side of the plurality of P-type active regions away from the plurality of N-type active regions. The power active region 100P is configured to be connected to a first power line to be formed subsequently.

[0186] In an exemplary embodiment, the grounding active region 100N may be located outside the region where the N-well region 10 is located, and the orthographic projection of the grounding active region 100N on the silicon substrate does not overlap with the orthographic projection of the N-well region 10 on the silicon substrate. The grounding active region 100N may be in the shape of a straight line or a broken line extending along a first direction X. The grounding active region 100N may be located on one side of the multiple N-type active regions in the second direction Y, that is, on a side of the multiple N-type active regions away from the multiple P-type active regions. The grounding active region 100N is configured to be connected to a ground line to be formed later.

[0187] In an exemplary embodiment, the first P-type active region 101P to the twelfth P-type active region 112P may be sequentially arranged along the first direction X (along the direction close to the display area). The second P-type active region 102P and the third P-type active region 103P of the integrated structure may be located on one side of the first P-type active region 101P in the first direction X, the fourth P-type active region 104P and the fifth P-type active region 105P of the integrated structure may be located on one side of the first direction X of the second P-type active region 102P and the third P-type active region 103P of the integrated structure, the sixth P-type active region 106P may be located on one side of the first direction X of the fourth P-type active region 104P and the fifth P-type active region 105P of the integrated structure, and the seventh P-type active region 107P may be located on the sixth P-type active region. The eighth P-type active region 108P and the ninth P-type active region 109P of the integrated structure may be located on one side of the first direction X of the seventh P-type active region 107P, the tenth P-type active region 110P may be located on one side of the first direction X of the eighth P-type active region 108P and the ninth P-type active region 109P of the integrated structure, the eleventh P-type active region 111P may be located on one side of the first direction X of the tenth P-type active region 110P, and the twelfth P-type active region 112P may be located on one side of the first direction X of the eleventh P-type active region 111P.

[0188] In an exemplary embodiment, the first N-type active region 101N to the twelfth N-type active region 112N may be sequentially arranged along the first direction X (along the direction close to the display area). The second N-type active region 102N and the third N-type active region 103N of the integrated structure may be located on one side of the first N-type active region 101N in the first direction X, the fourth N-type active region 104N and the fifth N-type active region 105N of the integrated structure may be located on one side of the second N-type active region 102N and the third N-type active region 103N of the integrated structure in the first direction X, the sixth N-type active region 106N may be located on one side of the fourth N-type active region 104N and the fifth N-type active region 105N of the integrated structure in the first direction X, and the seventh N-type active region 107N may be located on the sixth N-type active region. The eighth N-type active region 108N and the ninth N-type active region 109N of the integrated structure may be located on one side of the first direction X of the seventh N-type active region 107N, the tenth N-type active region 110N may be located on one side of the first direction X of the eighth N-type active region 108N and the ninth N-type active region 109N of the integrated structure, the eleventh N-type active region 111N may be located on one side of the first direction X of the tenth N-type active region 110N, and the twelfth N-type active region 112N may be located on one side of the first direction X of the eleventh N-type active region 111N.

[0189] FIG10C is an enlarged view of the region where the first NAND gate and the third inverter are located in FIG10A . As shown in FIG10C , the power active area 100P may have a first centerline O1, and the ground active area 100N may have a second centerline O2. The distance between the first centerline O1 and the second centerline O2 is the circuit width W0, which may be the dimension in the second direction Y. The first centerline O1 may be a straight line that bisects the power active area 100P in the second direction Y and extends along the first direction X. The second centerline O2 may be a straight line that bisects the ground active area 100N in the second direction Y and extends along the first direction X.

[0190] In an exemplary embodiment, the circuit width W0 may be less than or equal to the width of a pixel row in the display area.

[0191] In an exemplary embodiment, the circuit width W0 may be less than or equal to 6.3 μm, so that the width of the gate circuit is substantially consistent with the width of a sub-pixel in the pixel region, meeting the display requirement of a pixel density of 4000.

[0192] In an exemplary embodiment, taking the second transistor group as an example, a first width W1 is defined between the first center line O1 and the edge of the second P-type active region 102P on the side close to the power active region 100P (the first center line O1), a second width W2 is defined between the second center line O2 and the edge of the second N-type active region 102N on the side close to the ground active region 100N (the second center line O2), and a second width W2 is defined between the edge of the second P-type active region 102P on the side away from the power active region 100P (the first center line O1) and the edge of the second N-type active region 102N on the side away from the ground active region 100N (the second center line O2). The third width W3 is defined between the edges of the second P-type active region 102P on the side close to the power active region 100P (the first center line O1) and the edge of the second P-type active region 102P on the side away from the power active region 100P (the first center line O1). The third width W3 is defined between the edges of the second N-type active region 102N on the side close to the ground active region 100N (the second center line O2) and the edge of the second N-type active region 102N on the side away from the ground active region 100N (the second center line O2). Therefore:

[0193] W0=W1+WP+W3+WN+W2.

[0194] In an exemplary embodiment, the first width W1 of the first transmission gate, the second transmission gate, and the third transmission gate may be substantially the same, the first width W1 of the first NAND gate and the second NAND gate may be substantially the same, and the first width W1 of the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same, that is, the first width W1 of the same type of devices may be substantially the same.

[0195] In an exemplary embodiment, the first width W1 in the first transmission gate and the first NAND gate may be different, the first width W1 in the first NAND gate and the first inverter may be different, and the first width W1 in the first transmission gate and the first inverter may be different, that is, the first width W1 of different types of devices may be different.

[0196] In an exemplary embodiment, W1+WP+W3+WN+W2 may be less than or equal to 6.3 μm.

[0197] In exemplary embodiments, the first width W1 may be greater than 0.2 μm to meet process requirements.

[0198] In an exemplary embodiment, the first width W1 may be 15%*W0 to 45%*W0. For example, the first width W1 may be approximately 34%*W0.

[0199] In an exemplary embodiment, the first width W1 may be greater than 1 μm and less than 3 μm to ensure a distance between the second P-type transistor P6 and the first power line and reduce mutual interference therebetween. For example, the first width W1 may be approximately 2.1 μm to 2.2 μm.

[0200] In an exemplary embodiment, the second width W2 of the first transmission gate, the second transmission gate, and the third transmission gate may be substantially the same, the second width W2 of the first NAND gate and the second NAND gate may be substantially the same, and the second width W2 of the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same, that is, the second width W2 of the same type of devices may be substantially the same.

[0201] In an exemplary embodiment, the second width W2 in the first transmission gate and the first NAND gate may be different, the second width W2 in the first NAND gate and the first inverter may be different, and the second width W2 in the first transmission gate and the first inverter may be different, that is, the second width W2 of different types of devices may be different.

[0202] In exemplary embodiments, the second width W2 may be greater than 0.2 μm to meet process requirements.

[0203] In an exemplary embodiment, the second width W2 may be 15%*W0 to 45%*W0. For example, the first width W1 may be approximately 34%*W0.

[0204] In an exemplary embodiment, the second width W2 may be greater than 1 μm and less than 3 μm to ensure the distance between the second N-type transistor N6 and the ground line and reduce mutual interference therebetween. For example, the second width W2 may be approximately 2.1 μm to 2.2 μm.

[0205] In an exemplary embodiment, the third width W3 in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially the same, the third width W3 in the first NAND gate and the second NAND gate may be substantially the same, and the third width W3 in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same, that is, the third width W3 of the same type of devices may be substantially the same.

[0206] In an exemplary embodiment, the third width W3 in the first transmission gate and the first NAND gate may be different, the third width W3 in the first NAND gate and the first inverter may be different, and the third width W3 in the first transmission gate and the first inverter may be different, that is, the third width W3 of different types of devices may be different.

[0207] In an exemplary embodiment, the third width W3 can be greater than or equal to 1.5 μm, which not only ensures the distance between the second P-type transistor P6 and the second N-type transistor N6, reducing the mutual interference between the two, but also can accommodate the subsequently formed signal transfer lines and ensure that the signal transfer lines have appropriate routing width and distance, reducing the mutual interference between the transfer lines.

[0208] In an exemplary embodiment, the P-type active area width WP in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially the same, the P-type active area width WP in the first NAND gate and the second NAND gate may be substantially the same, and the P-type active area width WP in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same, that is, the P-type active area width WP of the same type of devices may be substantially the same.

[0209] In an exemplary embodiment, the N-type active area width WN in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially the same, the N-type active area width WN in the first NAND gate and the second NAND gate may be substantially the same, and the N-type active area width WN in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same, that is, the N-type active area width WN of the same type of devices may be substantially the same.

[0210] In an exemplary embodiment, the P-type active area width WP in the first transmission gate and the first NAND gate may be different, the P-type active area width WP in the first NAND gate and the first inverter may be different, and the P-type active area width WP in the first transmission gate and the first inverter may be different, that is, the P-type active area width WP of different types of devices may be different.

[0211] In an exemplary embodiment, the N-type active area width WN in the first transmission gate and the first NAND gate may be different, the N-type active area width WN in the first NAND gate and the first inverter may be different, and the N-type active area width WN in the first transmission gate and the first inverter may be different, that is, the N-type active area width WN of different types of devices may be different.

[0212] In an exemplary embodiment, the P-type active region width WP in the first NAND gate may be greater than the P-type active region width WP in the first transmission gate, and the P-type active region width WP in the first NAND gate may be greater than the P-type active region width WP in the first inverter.

[0213] In an exemplary embodiment, the N-type active region width WN in the first transmission gate may be greater than the N-type active region width WN in the first NAND gate, and the N-type active region width WN in the first NAND gate may be greater than the N-type active region width WN in the first inverter.

[0214] In an exemplary embodiment, the P-type active region width WP may be greater than 0.556 μm, and the N-type active region width WN may be greater than 0.556 μm to meet process requirements.

[0215] In an exemplary embodiment, the P-type active region width WP may be 15%*W0 to 45%*W0, and the N-type active region width WN may be 15%*W0 to 45%*W0. For example, the P-type active region width WP may be approximately 30%*W0, and the N-type active region width WN may be approximately 30%*W0.

[0216] In an exemplary embodiment, the P-type active region width WP may be greater than 1 μm and less than 3 μm, and the N-type active region width WN may be greater than 1 μm and less than 3 μm. For example, the P-type active region width WP may be approximately 2 μm, and the N-type active region width WN may be approximately 2 μm.

[0217] By setting the minimum width of each area, the present disclosure can effectively reduce the mutual influence between the P-type active area and the N-type active area, between the P-type active area and the first power line, between the N-type active area and the ground line, and between the first power line and the ground line, thereby improving the working reliability of the shift register circuit and ensuring the signal output quality of the gate drive circuit.

[0218] In an exemplary embodiment, a first distance S1 is present between an edge of the third P-type active region 103P on a side close to the first center line O1 and an edge of the fourth P-type active region 104P on a side close to the first center line O1, and a second distance S2 is present between an edge of the third P-type active region 103P on a side away from the first center line O1 and an edge of the fourth P-type active region 104P on a side away from the first center line O1. The second distance S2 may be greater than the first distance S1.

[0219] The present disclosure reduces the mutual influence between the NAND gate and the inverter by setting the positional relationship between the P-type active area of ​​the first NAND gate and the P-type active area of ​​the third inverter, improves the working reliability of the shift register circuit, and ensures the signal output quality of the gate drive circuit.

[0220] In example embodiments, in the second direction Y, at least one P-type active region may have a P-type active center line OP, which may be a straight line bisecting the P-type active region in the second direction Y and extending in the first direction X.

[0221] In an exemplary embodiment, the P-type active center lines OP in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially on the same straight line extending along the first direction X, the P-type active center lines OP in the first NAND gate and the second NAND gate may be substantially on the same straight line extending along the first direction X, and the P-type active center lines OP in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially on the same straight line extending along the first direction X. That is, the P-type active center lines OP of devices of the same type may be substantially on the same straight line extending along the first direction X.

[0222] In an exemplary embodiment, the P-type active center lines OP in the first transmission gate, the first inverter, and the first NAND gate may not be on the same straight line extending along the first direction X, that is, the P-type active center lines OP of different types of devices are not on the same straight line extending along the first direction X.

[0223] In an exemplary embodiment, in the second direction Y, the N-type active region in one transistor group may have an N-type active center line ON, which may be a straight line bisecting the N-type active region in the second direction Y and extending in the first direction X.

[0224] In an exemplary embodiment, the N-type active center lines ON in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially on the same straight line extending along the first direction X. The N-type active center lines ON in the first NAND gate and the second NAND gate may be substantially on the same straight line extending along the first direction X. The N-type active center lines ON in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially on the same straight line extending along the first direction X. That is, the N-type active center lines ON of devices of the same type may be substantially on the same straight line extending along the first direction X.

[0225] In an exemplary embodiment, the N-type active center lines ON in the first transmission gate, the first inverter, and the first NAND gate may not be on the same straight line extending along the first direction X, that is, the N-type active center lines ON of different types of devices are not on the same straight line extending along the first direction X.

[0226] (3) Forming a gate conductive layer pattern. In an exemplary embodiment, forming the gate conductive layer pattern may include: sequentially depositing a first insulating film and a polysilicon film on the silicon substrate on which the aforementioned pattern is formed, first patterning the polysilicon film through a patterning process to form a first insulating layer covering the silicon substrate and a polysilicon layer disposed on the first insulating layer, and then doping the polysilicon layer to form a gate conductive layer pattern, as shown in FIG11A and FIG11B , where FIG11B is a schematic diagram of the gate conductive layer in FIG11A .

[0227] In example embodiments, the gate conductive layer pattern may include at least first to twelfth P-type gate electrodes 201P to 212P and first to twelfth N-type gate electrodes 201N to 212N.

[0228] In an exemplary embodiment, the shape of the first P-type gate electrode 201P can be a strip shape extending along the second direction Y, the orthographic projection of the first P-type gate electrode 201P on the silicon substrate at least partially overlaps with the orthographic projection of the first P-type active region 101P on the silicon substrate, and the first P-type gate electrode 201P can serve as the gate electrode of the first P-type transistor P1.

[0229] In an exemplary embodiment, the shape of the first N-type gate electrode 201N can be a strip shape extending along the second direction Y, the orthographic projection of the first N-type gate electrode 201N on the silicon substrate at least partially overlaps with the orthographic projection of the first N-type active region 101N on the silicon substrate, and the first N-type gate electrode 201N can serve as the gate electrode of the first N-type transistor N1.

[0230] In an exemplary embodiment, the shape of the second P-type gate electrode 202P can be a strip shape extending along the second direction Y, and the orthographic projection of the second P-type gate electrode 202P on the silicon substrate at least partially overlaps with the orthographic projection of the second P-type active region 102P on the silicon substrate. The second P-type gate electrode 202P can serve as the gate electrode of the second P-type transistor P2.

[0231] In an exemplary embodiment, the second N-type gate electrode 202N may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the second N-type gate electrode 202N on the silicon substrate at least partially overlaps with the orthographic projection of the second N-type active region 102N on the silicon substrate. The second N-type gate electrode 202N may serve as the gate electrode of the second N-type transistor N2.

[0232] In an exemplary embodiment, the second P-type gate electrode 202P and the second N-type gate electrode 202N may be an integral structure connected to each other.

[0233] In an exemplary embodiment, the shape of the third P-type gate electrode 203P can be a strip shape extending along the second direction Y, and the orthographic projection of the third P-type gate electrode 203P on the silicon substrate at least partially overlaps with the orthographic projection of the third P-type active area 103P on the silicon substrate, and the third P-type gate electrode 203P can serve as the gate electrode of the third P-type transistor P3.

[0234] In an exemplary embodiment, the shape of the third N-type gate electrode 203N can be a strip shape extending along the second direction Y, the orthographic projection of the third N-type gate electrode 203N on the silicon substrate at least partially overlaps with the orthographic projection of the third N-type active region 103N on the silicon substrate, and the third N-type gate electrode 203N can serve as the gate electrode of the third N-type transistor N3.

[0235] In an exemplary embodiment, the third P-type gate electrode 203P and the third N-type gate electrode 203N may be an integral structure connected to each other.

[0236] In an exemplary embodiment, the shape of the fourth P-type gate electrode 204P can be a strip shape extending along the second direction Y, and the orthographic projection of the fourth P-type gate electrode 204P on the silicon substrate at least partially overlaps with the orthographic projection of the fourth P-type active region 104P on the silicon substrate, and the fourth P-type gate electrode 204P can serve as the gate electrode of the fourth P-type transistor P4.

[0237] In an exemplary embodiment, the fourth N-type gate electrode 204N may be in the shape of a strip extending along the second direction Y, and the orthographic projection of the fourth N-type gate electrode 204N on the silicon substrate at least partially overlaps with the orthographic projection of the fourth N-type active region 104N on the silicon substrate. The fourth N-type gate electrode 204N may serve as the gate electrode of the fourth N-type transistor N4.

[0238] In an exemplary embodiment, the fourth P-type gate electrode 204P and the fourth N-type gate electrode 204N may be an integral structure connected to each other.

[0239] In an exemplary embodiment, the shape of the fifth P-type gate electrode 205P can be a strip shape extending along the second direction Y, and the orthographic projection of the fifth P-type gate electrode 205P on the silicon substrate at least partially overlaps with the orthographic projection of the fifth P-type active region 105P on the silicon substrate, and the fifth P-type gate electrode 205P can serve as the gate electrode of the fifth P-type transistor P5.

[0240] In an exemplary embodiment, the shape of the fifth N-type gate electrode 205N can be a strip shape extending along the second direction Y, the orthographic projection of the fifth N-type gate electrode 205N on the silicon substrate at least partially overlaps with the orthographic projection of the fifth N-type active region 105N on the silicon substrate, and the fifth N-type gate electrode 205N can serve as the gate electrode of the fifth N-type transistor N5.

[0241] In an exemplary embodiment, the shape of the sixth P-type gate electrode 206P can be a strip shape extending along the second direction Y, the orthographic projection of the sixth P-type gate electrode 206P on the silicon substrate at least partially overlaps with the orthographic projection of the sixth P-type active region 106P on the silicon substrate, and the sixth P-type gate electrode 206P can serve as the gate electrode of the sixth P-type transistor P6.

[0242] In an exemplary embodiment, the shape of the sixth N-type gate electrode 206N can be a strip shape extending along the second direction Y, and the orthographic projection of the sixth N-type gate electrode 206N on the silicon substrate at least partially overlaps with the orthographic projection of the sixth N-type active region 106N on the silicon substrate. The sixth N-type gate electrode 206N can serve as the gate electrode of the sixth N-type transistor N6.

[0243] In an exemplary embodiment, the shape of the seventh P-type gate electrode 207P can be a strip shape extending along the second direction Y, and the orthographic projection of the seventh P-type gate electrode 207P on the silicon substrate at least partially overlaps with the orthographic projection of the seventh P-type active region 107P on the silicon substrate, and the seventh P-type gate electrode 207P can serve as the gate electrode of the seventh P-type transistor P7.

[0244] In an exemplary embodiment, the shape of the seventh N-type gate electrode 207N can be a strip shape extending along the second direction Y, the orthographic projection of the seventh N-type gate electrode 207N on the silicon substrate at least partially overlaps with the orthographic projection of the seventh N-type active region 107N on the silicon substrate, and the seventh N-type gate electrode 207N can serve as the gate electrode of the seventh N-type transistor N7.

[0245] In an exemplary embodiment, the shape of the eighth P-type gate electrode 208P can be a strip shape extending along the second direction Y, the orthographic projection of the eighth P-type gate electrode 208P on the silicon substrate at least partially overlaps with the orthographic projection of the eighth P-type active region 108P on the silicon substrate, and the eighth P-type gate electrode 208P can serve as the gate electrode of the eighth P-type transistor P8.

[0246] In an exemplary embodiment, the shape of the eighth N-type gate electrode 208N can be a strip shape extending along the second direction Y, the orthographic projection of the eighth N-type gate electrode 208N on the silicon substrate at least partially overlaps with the orthographic projection of the eighth N-type active region 108N on the silicon substrate, and the eighth N-type gate electrode 208N can serve as the gate electrode of the eighth N-type transistor N8.

[0247] In an exemplary embodiment, the eighth P-type gate electrode 208P and the eighth N-type gate electrode 208N may be an integral structure connected to each other.

[0248] In an exemplary embodiment, the shape of the ninth P-type gate electrode 209P can be a strip shape extending along the second direction Y, and the orthographic projection of the ninth P-type gate electrode 209P on the silicon substrate at least partially overlaps with the orthographic projection of the ninth P-type active region 109P on the silicon substrate, and the ninth P-type gate electrode 209P can serve as the gate electrode of the ninth P-type transistor P9.

[0249] In an exemplary embodiment, the shape of the ninth N-type gate electrode 209N can be a strip shape extending along the second direction Y, and the orthographic projection of the ninth N-type gate electrode 209N on the silicon substrate at least partially overlaps with the orthographic projection of the ninth N-type active region 109N on the silicon substrate. The ninth N-type gate electrode 209N can serve as the gate electrode of the ninth N-type transistor N9.

[0250] In an exemplary embodiment, the ninth P-type gate electrode 209P and the ninth N-type gate electrode 209N may be an integral structure connected to each other.

[0251] In an exemplary embodiment, the shape of the tenth P-type gate electrode 210P can be a strip shape extending along the second direction Y, and the orthographic projection of the tenth P-type gate electrode 210P on the silicon substrate at least partially overlaps with the orthographic projection of the tenth P-type active region 110P on the silicon substrate, and the tenth P-type gate electrode 210P can serve as the gate electrode of the tenth P-type transistor P10.

[0252] In an exemplary embodiment, the shape of the tenth N-type gate electrode 210N can be a strip shape extending along the second direction Y, and the orthographic projection of the tenth N-type gate electrode 210N on the silicon substrate at least partially overlaps with the orthographic projection of the tenth N-type active region 110N on the silicon substrate. The tenth N-type gate electrode 210N can serve as the gate electrode of the tenth N-type transistor N10.

[0253] In example embodiments, the tenth P-type gate electrode 210P and the tenth N-type gate electrode 210N may be an integral structure connected to each other.

[0254] In an exemplary embodiment, the shape of the eleventh P-type gate electrode 211P can be a strip shape extending along the second direction Y, the orthographic projection of the eleventh P-type gate electrode 211P on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh P-type active region 111P on the silicon substrate, and the eleventh P-type gate electrode 211P can serve as the gate electrode of the eleventh P-type transistor P11.

[0255] In an exemplary embodiment, the shape of the eleventh N-type gate electrode 211N can be a strip shape extending along the second direction Y, the orthographic projection of the eleventh N-type gate electrode 211N on the silicon substrate at least partially overlaps with the orthographic projection of the eleventh N-type active region 111N on the silicon substrate, and the eleventh N-type gate electrode 211N can serve as the gate electrode of the eleventh N-type transistor N11.

[0256] In exemplary embodiments, the eleventh P-type gate electrode 211P and the eleventh N-type gate electrode 211N may be an integral structure connected to each other.

[0257] In an exemplary embodiment, the shape of the twelfth P-type gate electrode 212P can be a strip shape extending along the second direction Y, the orthographic projection of the twelfth P-type gate electrode 212P on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth P-type active region 112P on the silicon substrate, and the twelfth P-type gate electrode 212P can serve as the gate electrode of the twelfth P-type transistor P12.

[0258] In an exemplary embodiment, the shape of the twelfth N-type gate electrode 212N can be a strip shape extending along the second direction Y, the orthographic projection of the twelfth N-type gate electrode 212N on the silicon substrate at least partially overlaps with the orthographic projection of the twelfth N-type active region 112N on the silicon substrate, and the twelfth N-type gate electrode 212N can serve as the gate electrode of the twelfth N-type transistor N12.

[0259] In exemplary embodiments, the twelfth P-type gate electrode 212P and the twelfth N-type gate electrode 212N may be an integral structure connected to each other.

[0260] In example embodiments, the first to twelfth P-type gate electrodes 201P to 212P may be sequentially disposed along the first direction X, and the first to twelfth N-type gate electrodes 201N to 212N may be sequentially disposed along the first direction X.

[0261] In example embodiments, the widths of the first to twelfth P-type gate electrodes 201P to 212P may be substantially equal, and the widths of the first to twelfth N-type gate electrodes 201N to 212N may be substantially equal.

[0262] In an exemplary embodiment, the width-to-length ratios of the P-type transistors in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially the same, the width-to-length ratios of the P-type transistors in the first NAND gate and the second NAND gate may be substantially the same, and the width-to-length ratios of the P-type transistors in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same, that is, the width-to-length ratios of the P-type transistors of the same type of devices may be substantially the same.

[0263] In an exemplary embodiment, the width-to-length ratios of the N-type transistors in the first transmission gate, the second transmission gate, and the third transmission gate may be substantially the same, the width-to-length ratios of the N-type transistors in the first NAND gate and the second NAND gate may be substantially the same, and the width-to-length ratios of the N-type transistors in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same, that is, the width-to-length ratios of the N-type transistors of the same type of devices may be substantially the same.

[0264] In an exemplary embodiment, the width-to-length ratios of the P-type transistors in the first transmission gate and the first NAND gate may be different, the width-to-length ratios of the P-type transistors in the first NAND gate and the first inverter may be different, and the width-to-length ratios of the P-type transistors in the first transmission gate and the first inverter may be different, that is, the width-to-length ratios of the P-type transistors of different types of devices may be different.

[0265] In an exemplary embodiment, the width-to-length ratios of the N-type transistors in the first transmission gate and the first NAND gate may be different, the width-to-length ratios of the N-type transistors in the first NAND gate and the first inverter may be different, and the width-to-length ratios of the N-type transistors in the first transmission gate and the first inverter may be different, that is, the width-to-length ratios of the N-type transistors of different types of devices may be different.

[0266] In an exemplary embodiment, in at least one transistor group, a width-to-length ratio of a P-type transistor is greater than a width-to-length ratio of an N-type transistor.

[0267] In an exemplary embodiment, in at least one transistor group, a ratio of a width-to-length ratio of a P-type transistor to a width-to-length ratio of an N-type transistor may be greater than 1 and less than 3.

[0268] FIG11C is an enlarged view of the twelfth P-type gate electrode and the twelfth N-type gate electrode in FIG11A . As shown in FIG11C , the first inverter may include a twelfth P-type transistor P12 and a twelfth N-type transistor N12. The twelfth P-type active region 112P may serve as the P-type active region of the twelfth P-type transistor P12. The twelfth P-type active region 112P has a P-type active region width WP. The twelfth P-type gate electrode 212P may serve as the P-type gate electrode of the twelfth P-type transistor P12. The twelfth P-type gate electrode 212P has a P-type gate electrode width LP. The width-to-length ratio of the twelfth P-type transistor P12 is WP / LP. The twelfth N-type active region 112N can serve as the N-type active region of the twelfth N-type transistor N12, and the twelfth N-type active region 112N has an N-type active region width WN. The twelfth N-type gate electrode 212N can serve as the N-type gate electrode of the twelfth N-type transistor N12, and the twelfth N-type gate electrode 212N has an N-type gate electrode width LN. The width-to-length ratio of the twelfth N-type transistor is WN / LN.

[0269] In an exemplary embodiment, the ratio between the width-to-length ratio (WP / LP) of the twelfth P-type transistor P12 and the width-to-length ratio (WN / LN) of the twelfth N-type transistor N12 is K, 1 <K<3。

[0270] In an exemplary embodiment, the P-type gate electrode width LP and the N-type gate electrode width LN may be substantially equal, and thus K=WP / WN, that is, the ratio of the P-type active region width WP to the twelfth N-type active region 112N may be greater than 1 and less than 3.

[0271] In an exemplary embodiment, K may be approximately equal to about 2.

[0272] In an exemplary embodiment, K in the first inverter, the second inverter, the third inverter, and the fourth inverter may be substantially the same.

[0273] The present disclosure makes the propagation delay symmetrical by setting the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the inverter, so that the rise and fall times of the P-type transistor and the N-type transistor are basically equal, the high and low level noise margins are basically the same, and the charge and discharge times are basically consistent, thereby improving the electrical performance of the inverter.

[0274] In an exemplary embodiment, the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first, second, and third transmission gates may be substantially the same, and the ratio K of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor may be greater than 0.9 and less than 1.1. For example, K may be approximately 1.0.

[0275] In an exemplary embodiment, the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first NAND gate and the second NAND gate may be substantially the same, and the ratio K of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor may be greater than 1.3 and less than 3.3. For example, K may be approximately 2.3.

[0276] In an exemplary embodiment, the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first NAND gate may be greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter, and the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter may be greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first transmission gate.

[0277] The present disclosure can ensure that the load is basically consistent and improve the electrical performance of the shift register circuit by setting the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in different devices.

[0278] (4) Forming a P-type doped (SP) region pattern. In an exemplary embodiment, forming the P-type doped region pattern may include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist within the plurality of opening regions, and forming a plurality of P-type doped regions within the opening regions by a doping process, as shown in FIG12A and FIG12B , where FIG12B is a schematic diagram of the P-type doped region in FIG12A .

[0279] In example embodiments, the plurality of P-type doping regions may include at least a first P-type doping region 31 and a second P-type doping region 32 .

[0280] In an exemplary embodiment, the first P-type doping region 31 can be located within the area where the N-well region 10 is located, and the orthographic projection of the first P-type doping region 31 on the silicon substrate includes the orthographic projections of the first P-type active region 101P to the twelfth P-type active region 112P on the silicon substrate, so that a P-type source region and a P-type drain region are respectively formed on both sides of the first direction X of the P-type gate electrode.

[0281] In an exemplary embodiment, the active region between some adjacent P-type gate electrodes can serve as the P-type source region of a P-type transistor and the P-type source region of another P-type transistor at the same time, or can serve as the P-type drain region of a P-type transistor and the P-type drain region of another P-type transistor at the same time, or can serve as the P-type source region of a P-type transistor and the P-type drain region of another P-type transistor at the same time.

[0282] In an exemplary embodiment, the P-type source region and the P-type drain region of each P-type transistor are both P-type heavily doped regions P+.

[0283] In an exemplary embodiment, the second P-type doping region 32 may be located outside the N-well region 10 , and the orthographic projection of the second P-type doping region 32 on the silicon substrate includes the orthographic projection of the grounded active region 100N on the silicon substrate.

[0284] (5) Forming an N-type doping (SN) region pattern. In an exemplary embodiment, forming the N-type doping region pattern may include: coating a photoresist on the silicon substrate on which the aforementioned pattern is formed, forming a plurality of opening regions by exposure and development, removing the photoresist within the plurality of opening regions, and forming a plurality of N-type doping regions within the opening regions by a doping process, as shown in FIG13A and FIG13B , where FIG13B is a schematic diagram of the N-type doping region in FIG13A .

[0285] In example embodiments, the plurality of N-type doping regions may include at least a first N-type doping region 41 and a second N-type doping region 42 .

[0286] In an exemplary embodiment, the first N-type doping region 41 may be located outside the region where the N-well region 10 is located. The orthographic projection of the first N-type doping region 41 on the silicon substrate includes the orthographic projections of the first N-type active region 101N to the ninth N-type active region 109N on the silicon substrate, so that an N-type source region and an N-type drain region are respectively formed on both sides of the N-type gate electrode in the first direction X.

[0287] In an exemplary embodiment, the active region between some adjacent N-type gate electrodes can serve as both the N-type source region of an N-type transistor and the N-type source region of another N-type transistor, or can serve as both the N-type drain region of an N-type transistor and the N-type drain region of another N-type transistor, or can serve as both the N-type source region of an N-type transistor and the N-type drain region of another N-type transistor.

[0288] In an exemplary embodiment, the N-type source region and the N-type drain region of each N-type transistor are both N-type heavily doped regions N+.

[0289] In an exemplary embodiment, the second N-type doping region 42 may be located within the N-well region 10 , and the orthographic projection of the second N-type doping region 42 on the silicon substrate includes the orthographic projection of the power active region 100P on the silicon substrate.

[0290] (6) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the silicon substrate having the aforementioned pattern formed thereon, patterning the second insulating film through a patterning process to form a second insulating layer covering the gate conductive layer pattern, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG. 14 .

[0291] In an exemplary embodiment, the plurality of via holes may include at least first to sixtieth via holes V1 to V60 .

[0292] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the silicon substrate may be located within the range of the orthographic projection of the first P-type source region of the first P-type transistor P1 on the silicon substrate, the first insulating layer and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first P-type source region, and the first via hole V1 is configured to connect the subsequently formed seventeenth connecting electrode to the first P-type source region through the via hole.

[0293] In an exemplary embodiment, the orthographic projection of the second via V2 on the silicon substrate can be located within the range of the orthographic projection of the first P-type drain region of the first P-type transistor P1 on the silicon substrate, the first insulating layer and the second insulating layer in the second via V2 are etched away to expose the surface of the first P-type drain region, and the second via V2 is configured to connect the subsequently formed eighteenth connecting electrode to the first P-type drain region through the via.

[0294] In an exemplary embodiment, the orthographic projection of the third via V3 on the silicon substrate can be located within the range of the orthographic projection of the first N-type source region of the first N-type transistor N1 on the silicon substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the first N-type source region, and the third via V3 is configured to connect the subsequently formed seventeenth connecting electrode to the first N-type source region through the via.

[0295] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the silicon substrate can be located within the range of the orthographic projection of the first N-type drain region of the first N-type transistor N1 on the silicon substrate, the first insulating layer and the second insulating layer within the fourth via V4 are etched away to expose the surface of the first N-type drain region, and the fourth via V4 is configured to connect the subsequently formed eighteenth connecting electrode to the first N-type drain region through the via.

[0296] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the silicon substrate can be located within the range of the orthographic projection of the second P-type source region of the second P-type transistor P2 on the silicon substrate, the second insulating layer and the second insulating layer within the fifth via V5 are etched away to expose the surface of the second P-type source region, and the fifth via V5 is configured to connect the subsequently formed nineteenth connecting electrode to the second P-type source region through the via.

[0297] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the silicon substrate can be located within the range of the orthographic projection of the second P-type drain region of the second P-type transistor P2 (also the third P-type drain region of the third P-type transistor P3) on the silicon substrate, the first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second P-type drain region (also the third P-type drain region), and the sixth via V6 is configured to connect the subsequently formed twentieth connecting electrode to the second P-type drain region (also the third P-type drain region) through the via.

[0298] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the silicon substrate can be located within the range of the orthographic projection of the third P-type source region of the third P-type transistor P3 on the silicon substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the third P-type source region, and the seventh via V7 is configured to connect the subsequently formed twenty-first connecting electrode to the third P-type source region through the via.

[0299] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the silicon substrate can be located within the range of the orthographic projection of the second N-type drain region of the second N-type transistor N2 on the silicon substrate, the second insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the second N-type drain region, and the eighth via V8 is configured to connect the subsequently formed twenty-second connecting electrode to the second N-type drain region through the via.

[0300] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the silicon substrate can be located within the range of the orthographic projection of the second N-type source region of the second N-type transistor N2 (also the third N-type drain region of the third N-type transistor N3) on the silicon substrate, and the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the second N-type source region (also the third N-type drain region), and the ninth via V9 is configured to connect the subsequently formed twenty-third connecting electrode to the second N-type source region (also the third N-type drain region) through the via.

[0301] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the silicon substrate can be located within the range of the orthographic projection of the third N-type source region of the third N-type transistor N3 on the silicon substrate. The first insulating layer and the second insulating layer in the tenth via V10 are etched away to expose the surface of the third N-type source region. The tenth via V10 is configured to connect the subsequently formed twenty-fourth connecting electrode to the third N-type source region through the via.

[0302] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type source region of the fourth P-type transistor P4 on the silicon substrate, the first insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the fourth P-type source region, and the eleventh via V11 is configured to connect the subsequently formed twenty-fifth connecting electrode to the fourth P-type source region through the via.

[0303] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type drain region of the fourth P-type transistor P4 (also the fifth P-type source region of the fifth P-type transistor P5) on the silicon substrate, and the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the fourth P-type drain region (also the fifth P-type source region), and the twelfth via V12 is configured to connect the subsequently formed twenty-sixth connecting electrode to the fourth P-type drain region (also the fifth P-type source region) through the via.

[0304] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the silicon substrate can be located within the range of the orthographic projection of the fifth P-type drain region of the fifth P-type transistor P5 on the silicon substrate, the first insulating layer and the second insulating layer in the thirteenth via V13 are etched away to expose the surface of the fifth P-type drain region, and the thirteenth via V13 is configured to connect the subsequently formed twenty-seventh connecting electrode to the fifth P-type drain region through the via.

[0305] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the silicon substrate can be located within the range of the orthographic projection of the fourth N-type source region of the fourth N-type transistor N4 on the silicon substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the fourth N-type source region, and the fourteenth via V14 is configured to connect the subsequently formed twenty-eighth connecting electrode to the fourth N-type source region through the via.

[0306] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the silicon substrate can be located within the range of the orthographic projection of the fourth N-type drain region of the fourth N-type transistor N4 (also the fifth N-type source region of the fifth N-type transistor N5) on the silicon substrate, the first insulating layer and the second insulating layer within the fifteenth via V15 are etched away to expose the surface of the fourth N-type drain region (also the fifth N-type source region), and the fifteenth via V15 is configured to connect the subsequently formed twenty-ninth connecting electrode to the fourth N-type drain region (also the fifth N-type source region) through the via.

[0307] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the silicon substrate can be located within the range of the orthographic projection of the fifth N-type drain region of the fifth N-type transistor N5 on the silicon substrate, the first insulating layer and the second insulating layer within the sixteenth via V16 are etched away to expose the surface of the fifth N-type drain region, and the sixteenth via V16 is configured to connect the subsequently formed thirtieth connecting electrode to the fifth N-type drain region through the via.

[0308] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type source region of the sixth P-type transistor P6 on the silicon substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the sixth P-type source region, and the seventeenth via V17 is configured to connect the subsequently formed thirty-first connecting electrode to the sixth P-type source region through the via.

[0309] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type drain region of the sixth P-type transistor P6 on the silicon substrate, the first insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the sixth P-type drain region, and the eighteenth via V18 is configured to connect the subsequently formed thirty-second connecting electrode to the sixth P-type drain region through the via.

[0310] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the silicon substrate can be located within the range of the orthographic projection of the sixth N-type source region of the sixth N-type transistor N6 on the silicon substrate, the first insulating layer and the second insulating layer in the nineteenth via V19 are etched away to expose the surface of the sixth N-type source region, and the nineteenth via V19 is configured to connect the subsequently formed thirty-third connecting electrode to the sixth N-type source region through the via.

[0311] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the silicon substrate may be located within the range of the orthographic projection of the sixth N-type drain region of the sixth N-type transistor N6 on the silicon substrate, the first insulating layer and the second insulating layer within the twentieth via V20 are etched away to expose the surface of the sixth N-type drain region, and the twentieth via V20 is configured to connect the subsequently formed thirty-fourth connecting electrode to the sixth N-type drain region through the via.

[0312] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type source region of the seventh P-type transistor P7 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-first via V21 are etched away to expose the surface of the seventh P-type source region, and the twenty-first via V21 is configured to connect the subsequently formed thirty-fifth connecting electrode to the seventh P-type source region through the via.

[0313] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type drain region of the seventh P-type transistor P7 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-second via V22 are etched away to expose the surface of the seventh P-type drain region, and the twenty-second via V22 is configured to connect the subsequently formed thirty-sixth connecting electrode to the seventh P-type drain region through the via.

[0314] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the silicon substrate can be located within the range of the orthographic projection of the seventh N-type source region of the seventh N-type transistor N7 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-third via V23 are etched away to expose the surface of the seventh N-type source region, and the twenty-third via V23 is configured to connect the subsequently formed thirty-seventh connecting electrode to the seventh N-type source region through the via.

[0315] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the silicon substrate can be located within the range of the orthographic projection of the seventh N-type drain region of the seventh N-type transistor N7 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-fourth via V24 are etched away to expose the surface of the seventh N-type drain region, and the twenty-fourth via V24 is configured to connect the subsequently formed thirty-eighth connecting electrode to the seventh N-type drain region through the via.

[0316] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the silicon substrate can be located within the range of the orthographic projection of the eighth P-type source region of the eighth P-type transistor P8 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-fifth via V25 are etched away to expose the surface of the eighth P-type source region, and the twenty-fifth via V25 is configured to connect the subsequently formed thirty-ninth connecting electrode to the eighth P-type source region through the via.

[0317] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the silicon substrate can be located within the range of the orthographic projection of the eighth P-type drain region of the eighth P-type transistor P8 (also the ninth P-type drain region of the ninth P-type transistor P9) on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-sixth via V26 are etched away to expose the surface of the eighth P-type drain region (also the ninth P-type drain region), and the twenty-sixth via V26 is configured to connect the subsequently formed fortieth connecting electrode to the eighth P-type drain region (also the ninth P-type drain region) through the via.

[0318] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the silicon substrate can be located within the range of the orthographic projection of the ninth P-type source region of the ninth P-type transistor P9 on the silicon substrate, the first insulating layer and the second insulating layer within the twenty-seventh via V27 are etched away to expose the surface of the ninth P-type source region, and the twenty-seventh via V27 is configured to connect the subsequently formed forty-first connecting electrode to the ninth P-type source region through the via.

[0319] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the silicon substrate can be located within the range of the orthographic projection of the eighth N-type source region of the eighth N-type transistor N8 on the silicon substrate, the first insulating layer and the second insulating layer in the twenty-eighth via V28 are etched away to expose the surface of the eighth N-type source region, and the twenty-eighth via V28 is configured to connect a subsequently formed ground wire to the eighth N-type source region through the via.

[0320] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the silicon substrate can be located within the range of the orthographic projection of the eighth N-type drain region of the eighth N-type transistor N8 (also the ninth N-type source region of the ninth N-type transistor N9) on the silicon substrate, and the first insulating layer and the second insulating layer within the twenty-ninth via V29 are etched away to expose the surface of the eighth N-type drain region (also the ninth N-type source region), and the twenty-ninth via V29 is configured to connect the subsequently formed forty-third connecting electrode to the eighth N-type drain region (also the ninth N-type source region) through the via.

[0321] In an exemplary embodiment, the orthographic projection of the 30th via V30 on the silicon substrate can be located within the range of the orthographic projection of the ninth N-type drain region of the ninth N-type transistor N9 on the silicon substrate, the first insulating layer and the second insulating layer within the 30th via V30 are etched away to expose the surface of the ninth N-type drain region, and the 30th via V30 is configured to connect the subsequently formed forty-fourth connecting electrode to the ninth N-type drain region through the via.

[0322] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type drain region of the tenth P-type transistor P10 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-first via V31 are etched away to expose the surface of the tenth P-type drain region, and the thirty-first via V31 is configured to connect the subsequently formed forty-fifth connecting electrode to the tenth P-type drain region through the via.

[0323] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type source region of the tenth P-type transistor P10 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-second via V32 are etched away to expose the surface of the tenth P-type source region, and the thirty-second via V32 is configured to connect the subsequently formed forty-sixth connecting electrode to the tenth P-type source region through the via.

[0324] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the silicon substrate can be located within the range of the orthographic projection of the tenth N-type drain region of the tenth N-type transistor N10 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-third via V33 are etched away to expose the surface of the tenth N-type drain region, and the thirty-third via V33 is configured to connect the subsequently formed forty-seventh connecting electrode to the tenth N-type drain region through the via.

[0325] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the silicon substrate can be located within the range of the orthographic projection of the tenth N-type source region of the tenth N-type transistor N10 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-fourth via V34 are etched away to expose the surface of the tenth N-type source region, and the thirty-fourth via V34 is configured to connect the subsequently formed forty-eighth connecting electrode to the tenth N-type source region through the via.

[0326] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type drain region of the eleventh P-type transistor P11 on the silicon substrate, the first insulating layer and the second insulating layer within the thirty-fifth via V35 are etched away to expose the surface of the eleventh P-type drain region, and the thirty-fifth via V35 is configured to connect the subsequently formed forty-ninth connecting electrode to the eleventh P-type drain region through the via.

[0327] In an exemplary embodiment, the orthographic projection of the thirty-sixth via V36 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type source region of the eleventh P-type transistor P11 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-sixth via V36 are etched away to expose the surface of the eleventh P-type source region, and the thirty-sixth via V36 is configured to connect the subsequently formed fiftieth connecting electrode to the eleventh P-type source region through the via.

[0328] In an exemplary embodiment, the orthographic projection of the thirty-seventh via V37 on the silicon substrate can be located within the range of the orthographic projection of the eleventh N-type drain region of the eleventh N-type transistor N11 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-seventh via V37 are etched away to expose the surface of the eleventh N-type drain region, and the thirty-seventh via V37 is configured to connect the subsequently formed fifty-first connecting electrode to the eleventh N-type drain region through the via.

[0329] In an exemplary embodiment, the orthographic projection of the thirty-eighth via V38 on the silicon substrate can be located within the range of the orthographic projection of the eleventh N-type source region of the eleventh N-type transistor N11 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-eighth via V38 are etched away to expose the surface of the eleventh N-type source region, and the thirty-eighth via V38 is configured to connect the subsequently formed fifty-second connecting electrode to the eleventh N-type source region through the via.

[0330] In an exemplary embodiment, the orthographic projection of the thirty-ninth via V39 on the silicon substrate can be located within the range of the orthographic projection of the twelfth P-type drain region of the twelfth P-type transistor P12 on the silicon substrate, the first insulating layer and the second insulating layer in the thirty-ninth via V39 are etched away to expose the surface of the twelfth P-type drain region, and the thirty-ninth via V39 is configured to connect the subsequently formed fifty-third connecting electrode to the twelfth P-type drain region through the via.

[0331] In an exemplary embodiment, the orthographic projection of the fortieth via V40 on the silicon substrate can be located within the range of the orthographic projection of the twelfth P-type source region of the twelfth P-type transistor P12 on the silicon substrate, the first insulating layer and the second insulating layer in the fortieth via V40 are etched away to expose the surface of the twelfth P-type source region, and the fortieth via V40 is configured to connect the subsequently formed fifty-fourth connecting electrode to the twelfth P-type source region through the via.

[0332] In an exemplary embodiment, the orthographic projection of the forty-first via V41 on the silicon substrate can be located within the range of the orthographic projection of the twelfth N-type drain region of the twelfth N-type transistor N12 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-first via V41 are etched away to expose the surface of the twelfth N-type drain region, and the forty-first via V41 is configured to connect the subsequently formed fifty-fifth connecting electrode to the twelfth N-type drain region through the via.

[0333] In an exemplary embodiment, the orthographic projection of the forty-second via V42 on the silicon substrate can be located within the range of the orthographic projection of the twelfth N-type source region of the twelfth N-type transistor N12 on the silicon substrate, the first insulating layer and the second insulating layer within the forty-second via V42 are etched away to expose the surface of the twelfth N-type source region, and the forty-second via V42 is configured to connect the subsequently formed fifty-sixth connecting electrode to the twelfth N-type source region through the via.

[0334] In an exemplary embodiment, the orthographic projection of the forty-third via V43 on the silicon substrate can be located within the range of the orthographic projection of the first P-type gate electrode 201P on the silicon substrate, the second insulating layer in the forty-third via V43 is etched away to expose the surface of the first P-type gate electrode 201P, and the forty-third via V43 is configured to connect the subsequently formed first connecting electrode to the first P-type gate electrode 201P through the via.

[0335] In an exemplary embodiment, the orthographic projection of the forty-fourth via V44 on the silicon substrate can be located within the range of the orthographic projection of the first N-type gate electrode 201N on the silicon substrate, the second insulating layer in the forty-fourth via V44 is etched away to expose the surface of the first N-type gate electrode 201N, and the forty-fourth via V44 is configured to connect the subsequently formed second connecting electrode to the first N-type gate electrode 201N through the via.

[0336] In an exemplary embodiment, the orthographic projection of the forty-fifth via V45 on the silicon substrate can be located within the range of the orthographic projection of the second P-type gate electrode 202P (also the second N-type gate electrode 202N) on the silicon substrate, and the second insulating layer in the forty-fifth via V45 is etched away to expose the surface of the second P-type gate electrode 202P (also the second N-type gate electrode 202N), and the forty-fifth via V45 is configured to connect the subsequently formed third connecting electrode to the second P-type gate electrode 202P (also the second N-type gate electrode 202N) through the via.

[0337] In an exemplary embodiment, the orthographic projection of the forty-sixth via V46 on the silicon substrate can be located within the range of the orthographic projection of the third P-type gate electrode 203P (also the third N-type gate electrode 203N) on the silicon substrate, and the second insulating layer in the forty-sixth via V46 is etched away to expose the surface of the third P-type gate electrode 203P (also the third N-type gate electrode 203N), and the forty-sixth via V46 is configured to connect the subsequently formed fourth connecting electrode to the third P-type gate electrode 203P (also the third N-type gate electrode 203N) through the via.

[0338] In an exemplary embodiment, the orthographic projection of the forty-seventh via V47 on the silicon substrate can be located within the range of the orthographic projection of the fourth P-type gate electrode 204P (also the fourth N-type gate electrode 204N) on the silicon substrate, and the second insulating layer in the forty-seventh via V47 is etched away to expose the surface of the fourth P-type gate electrode 204P (also the fourth N-type gate electrode 204N), and the forty-seventh via V47 is configured to connect the subsequently formed fifth connecting electrode to the fourth P-type gate electrode 204P (also the fourth N-type gate electrode 204N) through the via.

[0339] In an exemplary embodiment, the orthographic projection of the forty-eight via V48 on the silicon substrate can be located within the range of the orthographic projection of the fifth P-type gate electrode 205P on the silicon substrate, the second insulating layer in the forty-eight via V48 is etched away to expose the surface of the fifth P-type gate electrode 205P, and the forty-eight via V48 is configured to connect the subsequently formed sixth connecting electrode to the fifth P-type gate electrode 205P through the via.

[0340] In an exemplary embodiment, the orthographic projection of the forty-ninth via V49 on the silicon substrate can be located within the range of the orthographic projection of the fifth N-type gate electrode 205N on the silicon substrate, the second insulating layer in the forty-ninth via V49 is etched away to expose the surface of the fifth N-type gate electrode 205N, and the forty-ninth via V49 is configured to connect the subsequently formed seventh connecting electrode to the fifth N-type gate electrode 205N through the via.

[0341] In an exemplary embodiment, the orthographic projection of the fiftieth via V50 on the silicon substrate can be located within the range of the orthographic projection of the sixth P-type gate electrode 206P on the silicon substrate, the second insulating layer in the fiftieth via V50 is etched away to expose the surface of the sixth P-type gate electrode 206P, and the fiftieth via V50 is configured to connect the subsequently formed eighth connecting electrode to the sixth P-type gate electrode 206P through the via.

[0342] In an exemplary embodiment, the orthographic projection of the fifty-first via V51 on the silicon substrate can be located within the range of the orthographic projection of the sixth N-type gate electrode 206N on the silicon substrate, the second insulating layer in the fifty-first via V51 is etched away to expose the surface of the sixth N-type gate electrode 206N, and the fifty-first via V51 is configured to connect the subsequently formed ninth connecting electrode to the sixth N-type gate electrode 206N through the via.

[0343] In an exemplary embodiment, the orthographic projection of the fifty-second via V52 on the silicon substrate can be located within the range of the orthographic projection of the seventh P-type gate electrode 207P on the silicon substrate, the second insulating layer in the fifty-second via V52 is etched away to expose the surface of the seventh P-type gate electrode 207P, and the fifty-second via V52 is configured to connect the subsequently formed tenth connecting electrode to the seventh P-type gate electrode 207P through the via.

[0344] In an exemplary embodiment, the orthographic projection of the fifty-third via V53 on the silicon substrate can be located within the range of the orthographic projection of the seventh N-type gate electrode 207N on the silicon substrate, the second insulating layer in the fifty-third via V53 is etched away to expose the surface of the seventh N-type gate electrode 207N, and the fifty-third via V53 is configured to connect the subsequently formed eleventh connecting electrode to the seventh N-type gate electrode 207N through the via.

[0345] In an exemplary embodiment, the orthographic projection of the fifty-fourth via V54 on the silicon substrate can be located within the range of the orthographic projection of the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N) on the silicon substrate, and the second insulating layer in the fifty-fourth via V54 is etched away to expose the surface of the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N). The fifty-fourth via V54 is configured to connect the subsequently formed twelfth connecting electrode to the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N) through the via.

[0346] In an exemplary embodiment, the orthographic projection of the fifty-fifth via V55 on the silicon substrate can be located within the range of the orthographic projection of the ninth P-type gate electrode 209P (also the ninth N-type gate electrode 209N) on the silicon substrate, and the second insulating layer in the fifty-fifth via V55 is etched away to expose the surface of the ninth P-type gate electrode 209P (also the ninth N-type gate electrode 209N). The fifty-fifth via V55 is configured to connect the subsequently formed thirteenth connecting electrode to the ninth P-type gate electrode 209P (also the ninth N-type gate electrode 209N) through the via.

[0347] In an exemplary embodiment, the orthographic projection of the fifty-sixth via V56 on the silicon substrate can be located within the range of the orthographic projection of the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N) on the silicon substrate, and the second insulating layer in the fifty-sixth via V56 is etched away to expose the surface of the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N). The fifty-sixth via V56 is configured to connect the subsequently formed fourteenth connecting electrode to the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N) through the via.

[0348] In an exemplary embodiment, the orthographic projection of the fifty-seventh via V57 on the silicon substrate can be located within the range of the orthographic projection of the eleventh P-type gate electrode 211P (also the eleventh N-type gate electrode 211N) on the silicon substrate, and the second insulating layer in the fifty-seventh via V57 is etched away to expose the surface of the eleventh P-type gate electrode 211P (also the eleventh N-type gate electrode 211N). The fifty-seventh via V57 is configured to connect the subsequently formed fifteenth connecting electrode to the eleventh P-type gate electrode 211P (also the eleventh N-type gate electrode 211N) through the via.

[0349] In an exemplary embodiment, the orthographic projection of the fifty-eighth via V58 on the silicon substrate can be located within the range of the orthographic projection of the twelfth P-type gate electrode 212P (also the twelfth N-type gate electrode 212N) on the silicon substrate, and the second insulating layer in the fifty-eighth via V58 is etched away to expose the surface of the twelfth P-type gate electrode 212P (also the twelfth N-type gate electrode 212N), and the fifty-eighth via V58 is configured to connect the subsequently formed sixteenth connecting electrode to the twelfth P-type gate electrode 212P (also the twelfth N-type gate electrode 212N) through the via.

[0350] In an exemplary embodiment, one or more of the first to fifty-eighth via holes V1 to V58 may be plural to reduce contact resistance and increase connection reliability.

[0351] In an exemplary embodiment, the forty-third via V43 to the fifty-eighth via V58 can be referred to as gate vias, and one or more of the above-mentioned gate vias can be located in the gap region 50 between the P-type active area and the N-type active area, so as to facilitate the arrangement of multiple connecting electrodes formed subsequently, optimize the connection structure between the first conductive layer and the gate conductive layer, and reduce the occupied area of ​​the gate drive circuit.

[0352] In an exemplary embodiment, the gate vias of the fourth transistor group in the third inverter may be referred to as first gate vias. The first gate vias are configured to connect a subsequently formed first gate connection electrode to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through the first gate vias. The first gate vias may be disposed in the gap region 50. The first gate vias may include a forty-seventh via V47.

[0353] In an exemplary embodiment, the gate vias in the first inverter, the second inverter, and the fourth inverter may be referred to as second gate vias. The second gate vias are configured to connect a subsequently formed second gate connection electrode to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through the second gate vias. The second gate vias may be disposed in the gap region 50. The second gate vias may include a fifty-sixth via V56, a fifty-seventh via V57, and a fifty-eighth via V58.

[0354] In an exemplary embodiment, the gate vias in the first NAND gate and the second NAND gate may be referred to as third gate vias. The third gate vias are configured to connect a subsequently formed third gate connection electrode to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through the third gate vias. The third gate vias may be disposed in the gap region 50. The third gate vias may include a 45th via V45, a 46th via V46, a 54th via V54, and a 55th via V55.

[0355] In an exemplary embodiment, the gate vias in the first, second, and third transmission gates may be referred to as fourth gate vias. The fourth gate vias may include a fourth P-type gate via and a fourth N-type gate via. The fourth P-type gate via is configured to connect a subsequently formed fourth P-type gate connection electrode to the P-type gate electrode of the P-type transistor through the fourth P-type gate via. The fourth N-type gate via is configured to connect a subsequently formed fourth N-type gate connection electrode to the N-type gate electrode of the N-type transistor through the fourth N-type gate via. The fourth P-type gate via and the fourth N-type gate via may be disposed in the gap region 50. The fourth P-type gate via may include a forty-third via V43, a fiftieth via V50, and a fifty-second via V52. The fourth N-type gate via may include a forty-fourth via V44, a fifty-first via V51, and a fifty-third via V53.

[0356] In example embodiments, the gate via of the fifth transistor group in the third inverter may be referred to as a fourth gate via.

[0357] In an exemplary embodiment, the first gate via may be located substantially on the gap centerline OC, and an orthographic projection of the first gate via on the silicon substrate at least partially overlaps with an orthographic projection of the gap centerline OC on the silicon substrate.

[0358] In an exemplary embodiment, at least one second gate via is closer to the N-type active area of ​​the N-type transistor than the first gate via in the second direction Y. For example, the fifty-eighth via V58 (the second gate via in the first inverter) is closer to the N-type active area of ​​the N-type transistor than the forty-seventh via V47 (the first gate via in the third inverter).

[0359] In an exemplary embodiment, at least one third gate via is closer to the P-type active area of ​​the P-type transistor than the first gate via in the second direction Y. For example, the forty-fifth via V45 (the third gate via in the first NAND gate) is closer to the P-type active area of ​​the P-type transistor than the forty-seventh via V47 (the first gate via in the third inverter).

[0360] In an exemplary embodiment, at least one fourth P-type gate via is closer to the P-type active area of ​​the P-type transistor than the first gate via in the second direction Y. For example, the forty-third via V43 (the fourth P-type gate via in the first transmission gate) is closer to the P-type active area of ​​the P-type transistor than the forty-seventh via V47 (the first gate via in the third inverter).

[0361] In an exemplary embodiment, at least one fourth N-type gate via is closer to the N-type active area of ​​the N-type transistor than the first gate via in the second direction Y. For example, the forty-fourth via V44 (the fourth N-type gate via in the first transmission gate) is closer to the N-type active area of ​​the N-type transistor than the forty-seventh via V47 (the first gate via in the third inverter).

[0362] In an exemplary embodiment, the plurality of second gate vias in the first inverter, the second inverter, and the fourth inverter may be located on the same straight line extending along the first direction X.

[0363] In an exemplary embodiment, the plurality of third gate vias in the first NAND gate and the second NAND gate may be located on the same straight line extending along the first direction X.

[0364] In an exemplary embodiment, in the first transmission gate, the second transmission gate, and the third transmission gate, the plurality of fourth P-type gate vias may be located on the same straight line extending along the first direction X, and the plurality of fourth N-type gate vias may be located on the same straight line extending along the first direction X.

[0365] The present disclosure not only facilitates process uniformity and signal transmission uniformity by setting the position of the gate via, but also facilitates the arrangement of multiple connection electrodes formed subsequently, and optimizes the connection structure between the first conductive layer and the gate conductive layer.

[0366] In an exemplary embodiment, the orthographic projection of the fifty-ninth via V59 on the silicon substrate can be located within the range of the orthographic projection of the power active area 100P on the silicon substrate, the first insulating layer and the second insulating layer in the fifty-ninth via V59 are etched away to expose the surface of the power active area 100P, and the fifty-ninth via V59 is configured to connect a subsequently formed first power line to the power active area 100P through the via.

[0367] In an exemplary embodiment, there are a plurality of fifty-ninth via holes V59 , and the plurality of fifty-ninth via holes V59 are sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0368] In an exemplary embodiment, the orthographic projection of the 60th via V60 on the silicon substrate can be located within the range of the orthographic projection of the 1st grounding active area 100N on the silicon substrate, the first insulating layer and the second insulating layer in the 60th via V60 are etched away to expose the surface of the grounding active area 100N, and the 60th via V60 is configured to connect a subsequently formed grounding line to the grounding active area 100N through the via.

[0369] In an exemplary embodiment, there are a plurality of sixtieth via holes V60 , and the plurality of sixtieth via holes V60 are sequentially arranged along the first direction X to reduce contact resistance and increase connection reliability.

[0370] In an exemplary embodiment, a plurality of fifty-ninth vias V59 arranged sequentially along the first direction X form a first via row, and a plurality of sixtieth vias V60 arranged sequentially along the first direction X form a second via row, and the first via row and the second via row are respectively located on both sides of the second direction of the plurality of transistors, so that the plurality of transistors are located between the first via row and the second via row, which can effectively avoid mutual interference between different gate drive circuits.

[0371] (7) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a first conductive film on the silicon substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the second insulating layer, as shown in FIG. 15A and FIG. 15B , where FIG. 15B is a schematic diagram of the first conductive layer in FIG. 15A . In an exemplary embodiment, the first conductive layer may be referred to as a first metal (Metal 1) layer.

[0372] In an exemplary embodiment, the first conductive layer pattern may include at least a first power supply line 51 , a ground line 52 , first to fifty-sixth connection electrodes 601 to 656 , and first to sixth connection lines 701 to 706 .

[0373] In an exemplary embodiment, the shape of the first power line 51 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side opposite to the second direction Y of the multiple transistors. The first power line 51 is connected to the power active area 100P through multiple fifty-ninth vias V59.

[0374] In an exemplary embodiment, since the power active area 100P is located within the area where the N-well region 10 is located, the first power line 51 can write the first power signal into the N-well region 10, which not only provides better current driving capability and response speed to meet the operating requirements of the output circuit, but also reduces the voltage drop and power loss in the output circuit, thereby improving the overall efficiency of the output circuit.

[0375] In an exemplary embodiment, the ground line 52 may be in the shape of a straight line or a broken line extending along the first direction X, and may be disposed on one side of the plurality of transistors in the second direction Y. The ground line 52 is connected to the ground active region 100N through a plurality of sixtieth vias V60.

[0376] In an exemplary embodiment, since the ground active region 100N is located outside the area where the N-well region 10 is located, the ground line 52 can not only achieve a more stable potential reference, ensuring that the output circuit has consistent and reliable performance under different operating conditions, but also provide better signal isolation effect, reduce the influence of interconnection capacitance, reduce signal crosstalk and interference, and improve the stability and reliability of the circuit.

[0377] In an exemplary embodiment, the shape of the first connecting electrode 601 can be block-shaped (such as rectangular), and the first connecting electrode 601 is connected to the first P-type gate electrode 201P through the forty-third via V43. The first connecting electrode 601 is configured to be connected to the first signal transfer line formed subsequently.

[0378] In an exemplary embodiment, the shape of the second connection electrode 602 can be block-shaped (such as rectangular), and the second connection electrode 602 is connected to the first N-type gate electrode 201N through the forty-fourth via V44. The second connection electrode 602 is configured to be connected to the second signal transfer line formed subsequently.

[0379] In an exemplary embodiment, the third connection electrode 603 may be in a strip shape extending along the first direction X, and the third connection electrode 603 is connected to the second P-type gate electrode 202P (also the second N-type gate electrode 202N) through the forty-fifth via hole V45 .

[0380] In an exemplary embodiment, the shape of the fourth connecting electrode 604 can be block-shaped (such as rectangular), and the fourth connecting electrode 604 is connected to the third P-type gate electrode 203P (also the third N-type gate electrode 203N) through the forty-sixth via V46, and the fourth connecting electrode 604 is configured to be connected to the third signal transfer line formed subsequently.

[0381] In an exemplary embodiment, the fifth connection electrode 605 may be in a strip shape extending along the second direction Y, and the fifth connection electrode 605 is connected to the fourth P-type gate electrode 204P (also the fourth N-type gate electrode 204N) through the forty-seventh via hole V47 .

[0382] In an exemplary embodiment, the shape of the sixth connecting electrode 606 can be block-shaped (such as rectangular), and the sixth connecting electrode 606 is connected to the fifth P-type gate electrode 205P through the forty-eighth via V48. The sixth connecting electrode 606 is configured to be connected to the second signal transfer line formed subsequently.

[0383] In an exemplary embodiment, the shape of the seventh connecting electrode 607 can be a broken line extending along the first direction X, the first end of the seventh connecting electrode 607 is connected to the fifth N-type gate electrode 205N through the forty-ninth via V49, and the second end of the seventh connecting electrode 607 extends in the direction of the fourth P-type gate electrode 204P. The second end of the seventh connecting electrode 607 is configured to be connected to the first signal transfer line formed subsequently.

[0384] In an exemplary embodiment, the shape of the eighth connecting electrode 608 can be an "L" shape, the first end of the eighth connecting electrode 608 is connected to the sixth P-type gate electrode 206P through the fiftieth via V50, the second end of the eighth connecting electrode 608 extends toward the direction of the sixth N-type gate electrode 206N, and the second end of the eighth connecting electrode 608 is configured to be connected to the second signal transfer line formed subsequently.

[0385] In an exemplary embodiment, the shape of the ninth connecting electrode 609 can be an "L" shape, the first end of the ninth connecting electrode 609 is connected to the sixth N-type gate electrode 206N through the fifty-first via V51, the second end of the ninth connecting electrode 609 extends toward the direction of the sixth P-type gate electrode 206P, and the second end of the ninth connecting electrode 609 is configured to be connected to the first signal transfer line formed subsequently.

[0386] In an exemplary embodiment, the shape of the tenth connecting electrode 610 can be block-shaped (such as rectangular), and the tenth connecting electrode 610 is connected to the seventh P-type gate electrode 207P through the fifty-second via V52. The tenth connecting electrode 610 is configured to be connected to the first signal transfer line formed subsequently.

[0387] In an exemplary embodiment, the shape of the eleventh connecting electrode 611 can be block-shaped (such as rectangular), and the eleventh connecting electrode 611 is connected to the seventh N-type gate electrode 207N through the fifty-third via V53. The eleventh connecting electrode 611 is configured to be connected to the second signal transfer line formed subsequently.

[0388] In an exemplary embodiment, the shape of the twelfth connecting electrode 612 can be block-shaped (such as rectangular), and the twelfth connecting electrode 612 is connected to the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N) through the fifty-fourth via V54. The twelfth connecting electrode 612 is configured to be connected to the third signal transfer line formed subsequently.

[0389] In an exemplary embodiment, the thirteenth connection electrode 613 may be in a block shape (eg, rectangular) and is connected to the ninth P-type gate electrode 209P (also the ninth N-type gate electrode 209N) through a fifty-fifth via hole V55.

[0390] In an exemplary embodiment, the shape of the fourteenth connecting electrode 614 can be block-shaped (such as rectangular), and the fourteenth connecting electrode 614 is connected to the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N) through the fifty-sixth via V56. The fourteenth connecting electrode 614 is configured to be connected to the fifth signal transfer line formed subsequently.

[0391] In an exemplary embodiment, the fifteenth connection electrode 615 may be in a block shape (eg, rectangular) and is connected to the eleventh P-type gate electrode 211P (also the eleventh N-type gate electrode 211N) through the fifty-seventh via hole V57.

[0392] In an exemplary embodiment, the sixteenth connection electrode 616 may be in a block shape (e.g., a rectangle) and is connected to the twelfth P-type gate electrode 212P (also the twelfth N-type gate electrode 212N) via the fifty-eighth via V58. In an exemplary embodiment, the sixteenth connection electrode 616 may be connected to the clock signal terminal CK of a subsequently formed shift register circuit, thereby enabling the clock signal terminal CK of the shift register circuit to write a clock signal to the gate electrode of the twelfth P-type transistor P12 and the gate electrode of the twelfth N-type transistor N12.

[0393] In exemplary embodiments, the first to sixteenth connection electrodes 601 to 616 may be referred to as gate connection electrodes, and the gate connection electrodes are connected to corresponding gate electrodes through corresponding gate vias.

[0394] In an exemplary embodiment, the gate connection electrodes in the third inverter may include a fifth connection electrode 605 , a sixth connection electrode 606 , and a seventh connection electrode 607 , and the fifth connection electrode 605 may be referred to as a first gate connection electrode.

[0395] In an exemplary embodiment, the gate connection electrodes in the first, second, and fourth inverters may include a fourteenth, fifteenth, and sixteenth connection electrodes 614 , 615 , and 616 , which may be referred to as second gate connection electrodes.

[0396] In an exemplary embodiment, the gate connection electrode in the first NAND gate may include a third connection electrode 603 and a fourth connection electrode 604, and the gate connection electrode in the second NAND gate may include a twelfth connection electrode 612 and a thirteenth connection electrode 613, which may be referred to as a third gate connection electrode.

[0397] In an exemplary embodiment, the P-type gate connection electrodes in the first, second, and third transmission gates may include a first connection electrode 601, an eighth connection electrode 608, and a tenth connection electrode 610, and these gate connection electrodes may be referred to as fourth P-type gate connection electrodes. The N-type gate connection electrodes in the first, second, and third transmission gates may include a second connection electrode 602, a ninth connection electrode 609, and an eleventh connection electrode 611, and these gate connection electrodes may be referred to as fourth N-type gate connection electrodes.

[0398] In an exemplary embodiment, the shape of the seventeenth connecting electrode 617 can be a strip shape extending along the second direction Y, the first end of the seventeenth connecting electrode 617 is connected to the first P-type source region through the first via V1, and the second end of the seventeenth connecting electrode 617 is connected to the first N-type source region through the third via V3. The seventeenth connecting electrode 617 realizes the mutual connection between the first pole (source electrode) of the first P-type transistor P1 and the first pole (source electrode) of the first N-type transistor N1.

[0399] In an exemplary embodiment, the seventeenth connection electrode 617 can be connected to the input terminal D of a subsequently formed shift register circuit, so that the input terminal D of the shift register circuit writes the input signal into the first electrode of the first P-type transistor P1 and the first electrode of the first N-type transistor N1.

[0400] In an exemplary embodiment, the shape of the eighteenth connecting electrode 618 can be a strip shape extending along the second direction Y, the first end of the eighteenth connecting electrode 618 is connected to the first P-type drain region through the second via V2, and the second end of the eighteenth connecting electrode 618 is connected to the first N-type drain region through the fourth via V4.

[0401] In an exemplary embodiment, a first bump k1 is connected to the eighteenth connection electrode 618 , and the first bump k1 is configured to be connected to a fourth signal transfer line formed subsequently.

[0402] In an exemplary embodiment, the shape of the nineteenth connecting electrode 619 can be a strip shape extending along the second direction Y, the first end of the nineteenth connecting electrode 619 is connected to the first power line 51, and the second end of the nineteenth connecting electrode 619 is connected to the second P-type source region through the fifth via V5, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the second P-type transistor P2.

[0403] In an exemplary embodiment, the twentieth connecting electrode 620 may be in the shape of a strip extending along the second direction Y. The twentieth connecting electrode 620 is connected to the second P-type drain region (also the third P-type drain region) through a sixth via V6. In an exemplary embodiment, the second P-type drain region (the second region of the second P-type active region) and the third P-type drain region (the second region of the third P-type active region) share the same active region. The twentieth connecting electrode 620 may simultaneously serve as the second P-type drain electrode of the second P-type transistor P2 and the second P-type drain electrode of the third P-type transistor P3. That is, the second P-type drain electrode and the third P-type drain electrode share the same connecting electrode.

[0404] In an exemplary embodiment, the shape of the twenty-first connecting electrode 621 can be a strip shape extending along the second direction Y, the first end of the twenty-first connecting electrode 621 is connected to the first power line 51, and the second end of the twenty-first connecting electrode 621 is connected to the third P-type source region through the seventh via V7, so that the first power line 51 writes the first power signal into the first pole (source electrode) of the third P-type transistor P3.

[0405] In an exemplary embodiment, the shape of the twenty-second connection electrode 622 may be a bar shape extending along the second direction Y, and the twenty-second connection electrode 622 is connected to the second N-type drain region through the eighth via hole V8.

[0406] In an exemplary embodiment, the twenty-third connection electrode 623 may be in a strip shape extending along the second direction Y, and the twenty-third connection electrode 623 is connected to the second N-type source region (also the third N-type drain region) through the ninth via hole V9.

[0407] In an exemplary embodiment, the shape of the twenty-fourth connecting electrode 624 can be a strip shape extending along the second direction Y, the first end of the twenty-fourth connecting electrode 624 is connected to the ground line 52, and the second end of the twenty-fourth connecting electrode 624 is connected to the third N-type source region through the tenth via V10, thereby realizing the grounding of the first pole (source electrode) of the third N-type transistor N3.

[0408] In an exemplary embodiment, the shape of the twenty-fifth connecting electrode 625 can be a strip shape extending along the second direction Y, the first end of the twenty-fifth connecting electrode 625 is connected to the first power line 51, and the second end of the twenty-fifth connecting electrode 625 is connected to the fourth P-type source region through the eleventh via V11, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the fourth P-type transistor P4.

[0409] In an exemplary embodiment, the twenty-sixth connection electrode 626 may be in a strip shape extending along the second direction Y, and the twenty-sixth connection electrode 626 is connected to the fourth P-type drain region (also the fifth P-type source region) through the twelfth via hole V12 .

[0410] In an exemplary embodiment, the shape of the twenty-seventh connection electrode 627 may be a bar shape extending along the second direction Y, and the twenty-seventh connection electrode 627 is connected to the fifth P-type drain region through the thirteenth via hole V13 .

[0411] In an exemplary embodiment, a second bump k2 is connected to the twenty-seventh connection electrode 627 , and the second bump k2 is configured to be connected to a fourth signal transfer line formed subsequently.

[0412] In an exemplary embodiment, the shape of the twenty-eighth connecting electrode 628 can be a strip shape extending along the second direction Y, the first end of the twenty-eighth connecting electrode 628 is connected to the ground line 52, and the second end of the twenty-eighth connecting electrode 628 is connected to the fourth N-type source region through the fourteenth via V14, thereby realizing the grounding of the first pole (source electrode) of the fourth N-type transistor N4.

[0413] In an exemplary embodiment, the twenty-ninth connection electrode 629 may be in a strip shape extending along the second direction Y, and the twenty-ninth connection electrode 629 is connected to the fourth N-type drain region (also the fifth N-type source region) through the fifteenth via hole V15 .

[0414] In an exemplary embodiment, the shape of the thirtieth connection electrode 630 may be a bar shape extending along the second direction Y, and the thirtieth connection electrode 630 is connected to the fifth N-type drain region through the sixteenth via hole V16 .

[0415] In an exemplary embodiment, the twenty-seventh connection electrode 627 and the thirtieth connection electrode 630 may be an integral structure connected to each other, thereby achieving mutual connection between the second electrode (drain electrode) of the fifth P-type transistor P5 and the second electrode (drain electrode) of the fifth N-type transistor N5.

[0416] In an exemplary embodiment, the shape of the thirty-first connection electrode 631 may be a bar shape extending along the second direction Y, and the thirty-first connection electrode 631 is connected to the sixth P-type source region through the seventeenth via hole V17 .

[0417] In an exemplary embodiment, the shape of the thirty-second connection electrode 632 may be a bar shape extending along the second direction Y, and the thirty-second connection electrode 632 is connected to the sixth P-type drain region through the eighteenth via hole V18 .

[0418] In an exemplary embodiment, the shape of the thirty-third connection electrode 633 may be a bar shape extending along the second direction Y, and the thirty-third connection electrode 633 is connected to the sixth N-type source region through the nineteenth via hole V19 .

[0419] In an exemplary embodiment, the thirty-first connection electrode 631 and the thirty-third connection electrode may be an integral structure connected to each other, thereby achieving mutual connection between the first electrode (source electrode) of the sixth P-type transistor P6 and the first electrode (source electrode) of the sixth N-type transistor N6.

[0420] In an exemplary embodiment, the shape of the thirty-fourth connection electrode 634 may be a bar shape extending along the second direction Y, and the thirty-fourth connection electrode 634 is connected to the sixth N-type drain region through the twentieth via hole V20 .

[0421] In an exemplary embodiment, the thirty-second connection electrode 632 and the thirty-fourth connection electrode 634 may be an integral structure connected to each other, thereby realizing the interconnection between the second electrode (drain electrode) of the sixth P-type transistor P6 and the second electrode (drain electrode) of the sixth N-type transistor N6.

[0422] In an exemplary embodiment, the sixth P-type drain region is the second region of the sixth P-type active region, the sixth N-type drain region is the second region of the sixth P-type active region, the thirty-second connecting electrode 632 can serve as the sixth P-type drain electrode, and the thirty-fourth connecting electrode 634 can serve as the sixth N-type drain electrode, so that the sixth P-type drain electrode and the sixth N-type drain electrode are an integrated structure connected to each other.

[0423] In an exemplary embodiment, the shape of the thirty-fifth connection electrode 635 may be a bar shape extending along the second direction Y, and the thirty-fifth connection electrode 635 is connected to the seventh P-type source region through the twenty-first via hole V21 .

[0424] In an exemplary embodiment, the shape of the thirty-sixth connection electrode 636 may be a bar shape extending along the second direction Y, and the thirty-sixth connection electrode 636 is connected to the seventh P-type drain region through the twenty-second via hole V22 .

[0425] In an exemplary embodiment, the shape of the thirty-seventh connection electrode 637 may be a bar shape extending along the second direction Y, and the thirty-seventh connection electrode 637 is connected to the seventh N-type source region through the twenty-third via hole V23 .

[0426] In an exemplary embodiment, the thirty-fifth connection electrode 635 and the thirty-seventh connection electrode 637 may be an integral structure connected to each other, thereby realizing the interconnection between the first electrode (source electrode) of the seventh P-type transistor P7 and the first electrode (source electrode) of the seventh N-type transistor N7.

[0427] In an exemplary embodiment, the sixth P-type source region is the first region of the seventh P-type active region, the seventh N-type source region is the first region of the seventh P-type active region, the thirty-fifth connecting electrode 635 can serve as the seventh P-type source electrode, and the thirty-seventh connecting electrode 637 can serve as the seventh N-type source electrode, so that the seventh P-type source electrode and the seventh N-type source electrode are an integrated structure connected to each other.

[0428] In an exemplary embodiment, the shape of the thirty-eighth connection electrode 638 may be a bar shape extending along the second direction Y, and the thirty-eighth connection electrode 638 is connected to the seventh N-type drain region through the twenty-fourth via hole V24 .

[0429] In an exemplary embodiment, the thirty-sixth connection electrode 636 and the thirty-eighth connection electrode 638 can be an integrated structure connected to each other, thereby realizing the interconnection between the second electrode (drain electrode) of the seventh P-type transistor P7 and the second electrode (drain electrode) of the seventh N-type transistor N7.

[0430] In an exemplary embodiment, the shape of the thirty-ninth connecting electrode 639 can be a strip shape extending along the second direction Y, the first end of the thirty-ninth connecting electrode 639 is connected to the first power line 51, and the second end of the thirty-ninth connecting electrode 639 is connected to the eighth P-type source region through the twenty-fifth via V25, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the eighth P-type transistor P8.

[0431] In an exemplary embodiment, the fortieth connection electrode 640 may be in a strip shape extending along the second direction Y, and the fortieth connection electrode 640 is connected to the eighth P-type drain region (also the ninth P-type drain region) through the twenty-sixth via hole V26 .

[0432] In an exemplary embodiment, the shape of the forty-first connecting electrode 641 can be a strip shape extending along the second direction Y, the first end of the forty-first connecting electrode 641 is connected to the first power line 51, and the second end of the forty-first connecting electrode 641 is connected to the ninth P-type source region through the twenty-seventh via V27, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the ninth P-type transistor P9.

[0433] In an exemplary embodiment, the shape of the forty-second connecting electrode 642 can be a strip shape extending along the second direction Y, the first end of the forty-second connecting electrode 642 is connected to the ground line 52, and the second end of the forty-second connecting electrode 642 is connected to the eighth N-type source region through the twenty-eighth via V28, thereby realizing the grounding of the first pole (source electrode) of the eighth N-type transistor N8.

[0434] In an exemplary embodiment, the forty-third connection electrode 643 may be in a strip shape extending along the second direction Y, and the forty-third connection electrode 643 is connected to the eighth N-type drain region (also the ninth N-type source region) through the twenty-ninth via hole V29 .

[0435] In an exemplary embodiment, the forty-fourth connection electrode 644 may have a bar shape extending along the second direction Y, and the forty-fourth connection electrode 644 is connected to the ninth N-type drain region through the thirtieth via hole V30 .

[0436] In an exemplary embodiment, the forty-fifth connection electrode 645 may have a bar shape extending along the second direction Y, and the forty-fifth connection electrode 645 is connected to the tenth P-type drain region through the thirty-first via hole V31 .

[0437] In an exemplary embodiment, the shape of the forty-sixth connecting electrode 646 can be a strip shape extending along the second direction Y, the first end of the forty-sixth connecting electrode 646 is connected to the first power line 51, and the second end of the forty-sixth connecting electrode 646 is connected to the tenth P-type source region through the thirty-second via V32, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the tenth P-type transistor P10.

[0438] In an exemplary embodiment, the forty-seventh connection electrode 647 may have a bar shape extending along the second direction Y, and the forty-seventh connection electrode 647 is connected to the tenth N-type drain region through the thirty-third via hole V33 .

[0439] In an exemplary embodiment, the forty-fifth connection electrode 645 and the forty-seventh connection electrode 647 may be an integral structure connected to each other, thereby achieving interconnection between the second electrode (drain electrode) of the tenth P-type transistor P10 and the second electrode (drain electrode) of the tenth N-type transistor N10.

[0440] In an exemplary embodiment, the shape of the forty-eighth connecting electrode 648 can be a strip shape extending along the second direction Y, the first end of the forty-eighth connecting electrode 648 is connected to the ground line 52, and the second end of the forty-eighth connecting electrode 648 is connected to the tenth N-type source region through the thirty-fourth via V34, thereby realizing the grounding of the first pole (source electrode) of the tenth N-type transistor N10.

[0441] In an exemplary embodiment, the forty-ninth connection electrode 649 may be in the shape of a strip extending along the second direction Y. The forty-ninth connection electrode 649 is connected to the eleventh P-type drain region through the thirty-fifth via hole V35. In an exemplary embodiment, the forty-ninth connection electrode 649 serves as the second electrode of the eleventh P-type transistor P11.

[0442] In an exemplary embodiment, the shape of the fiftieth connecting electrode 650 can be a strip shape extending along the second direction Y, the first end of the fiftieth connecting electrode 650 is connected to the first power line 51, and the second end of the fiftieth connecting electrode 650 is connected to the eleventh P-type source region through the thirty-sixth via V36, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the eleventh P-type transistor P11.

[0443] In an exemplary embodiment, the fifty-first connection electrode 651 may be in the shape of a strip extending along the second direction Y. The fifty-first connection electrode 651 is connected to the eleventh N-type drain region through the thirty-seventh via hole V37. In an exemplary embodiment, the fifty-first connection electrode 651 is connected to the second electrode of the eleventh N-type transistor N11.

[0444] In an exemplary embodiment, the forty-ninth connection electrode 649 and the fifty-first connection electrode 651 may be an integral structure connected to each other, thereby realizing the interconnection between the second electrode (drain electrode) of the eleventh P-type transistor P11 and the second electrode (drain electrode) of the eleventh N-type transistor N11.

[0445] In an exemplary embodiment, a third bump k3 is connected to the forty-ninth connection electrode 649 and the fifty-first connection electrode 651 of the integrated structure. The third bump k3 is configured to be connected to a first signal transfer line formed subsequently.

[0446] In an exemplary embodiment, the forty-ninth connection electrode 649 , the fifty-first connection electrode 651 , and the third bump k3 may be an integral structure connected to each other.

[0447] In an exemplary embodiment, the shape of the fifty-second connecting electrode 652 can be a strip shape extending along the second direction Y, the first end of the fifty-second connecting electrode 652 is connected to the ground line 52, and the second end of the fifty-second connecting electrode 652 is connected to the eleventh N-type source region through the thirty-eighth via V38, thereby realizing the grounding of the first pole (source electrode) of the eleventh N-type transistor N11.

[0448] In an exemplary embodiment, the fifty-third connection electrode 653 may have a bar shape extending along the second direction Y, and the fifty-third connection electrode 653 is connected to the twelfth P-type drain region through the thirty-ninth via hole V39 .

[0449] In an exemplary embodiment, the shape of the fifty-fourth connecting electrode 654 can be a strip shape with the main portion extending along the second direction Y, the first end of the fifty-fourth connecting electrode 654 is connected to the first power line 51, and the second end of the fifty-fourth connecting electrode 654 is connected to the twelfth P-type source region through the fortieth via V40, thereby enabling the first power line 51 to write the first power signal into the first pole (source electrode) of the twelfth P-type transistor P12.

[0450] In an exemplary embodiment, the fifty-fifth connection electrode 655 may have a bar shape extending along the second direction Y, and the fifty-fifth connection electrode 655 is connected to the twelfth N-type drain region through the forty-first via hole V41 .

[0451] In an exemplary embodiment, the fifty-third connection electrode 653 and the fifty-fifth connection electrode 655 can be an integrated structure connected to each other, thereby realizing the interconnection between the second electrode (drain electrode) of the twelfth P-type transistor P12 and the second electrode (drain electrode) of the twelfth N-type transistor N12.

[0452] In an exemplary embodiment, the shape of the fifty-sixth connecting electrode 656 can be a strip shape with the main portion extending along the second direction Y, the first end of the fifty-sixth connecting electrode 656 is connected to the ground line 52, and the second end of the fifty-sixth connecting electrode 656 is connected to the twelfth N-type source region through the forty-second via V42, thereby realizing the grounding of the first pole (source electrode) of the twelfth N-type transistor N12.

[0453] In an exemplary embodiment, the first connection line 701 may be in the shape of a bar extending along the first direction X. A first end of the first connection line 701 is connected to the eighteenth connection electrode 618, and a second end of the first connection line 701 is connected to the third connection electrode 603. In an exemplary embodiment, the first connection line 701 interconnects the second electrode (drain electrode) of the first P-type transistor P1, the second electrode (drain electrode) of the first N-type transistor N1, the gate electrode of the second P-type transistor P2, and the gate electrode of the second N-type transistor N2.

[0454] In an exemplary embodiment, the third connection electrode 603 , the eighteenth connection electrode 618 , and the first connection line 701 may be an integral structure connected to each other.

[0455] In an exemplary embodiment, the second connection line 702 may be in the shape of a strip extending along the first direction X. A first end of the second connection line 702 is connected to the 22nd connection electrode 622, a second end of the second connection line 702 is connected to the fifth connection electrode 605, and a portion between the first and second ends of the second connection line 702 is connected to the 20th connection electrode 620. In an exemplary embodiment, the second connection line 702 interconnects the second electrode of the second P-type transistor P2, the second electrode of the second N-type transistor N2, the second electrode of the third P-type transistor P3, the gate electrode of the fourth P-type transistor P4, and the gate electrode of the fourth N-type transistor N4.

[0456] In an exemplary embodiment, the fifth connection electrode 605 , the twentieth connection electrode 620 , the twenty-second connection electrode 622 , and the second connection line 702 may be an integral structure connected to each other.

[0457] In an exemplary embodiment, the orthographic projection of the second connecting line 702 on the silicon substrate at least partially overlaps with the orthographic projection of the second P-type gate electrode 202P and the second N-type gate electrode 202N of the integrated structure on the silicon substrate, and the orthographic projection of the second connecting line 702 on the silicon substrate at least partially overlaps with the orthographic projection of the third P-type gate electrode 203P and the third N-type gate electrode 203N of the integrated structure on the silicon substrate, that is, the second connecting line 702 crosses the gate electrodes of the second transistor group (the second P-type transistor P2 and the second N-type transistor N2) and the gate electrodes of the third transistor group (the third P-type transistor P3 and the third N-type transistor N3) and is connected to the gate electrodes of the fourth transistor group (the fourth P-type transistor P4 and the fourth N-type transistor N4).

[0458] In an exemplary embodiment, the third connection line 703 may be in the shape of a strip extending along the first direction X. A first end of the third connection line 703 is connected to the thirty-second connection electrode 632 and the thirty-fourth connection electrode 634 of the integrated structure, and a second end of the third connection line 703 is connected to the thirty-fifth connection electrode 635 and the thirty-seventh connection electrode 637 of the integrated structure. In an exemplary embodiment, the third connection line 703 interconnects the second electrode of the sixth P-type transistor P6, the second electrode of the sixth N-type transistor N6, the first electrode of the seventh P-type transistor P7, and the first electrode of the seventh N-type transistor N7.

[0459] In exemplary embodiments, the thirty-second connection electrode 632 , the thirty-fourth connection electrode 634 , the thirty-fifth connection electrode 635 , the thirty-seventh connection electrode 637 , and the third connection line 703 may be an integral structure connected to one another.

[0460] In an exemplary embodiment, the fourth connection line 704 may be in the shape of a strip extending along the first direction X. A first end of the fourth connection line 704 is connected to the thirty-sixth connection electrode 636 and the thirty-eighth connection electrode 638 of the integrated structure, a second end of the fourth connection line 704 is connected to the forty-fourth connection electrode 644, and a connection is made between the first and second ends of the fourth connection line 704 and the fortieth connection electrode 640. The fourth connection line 704 interconnects the second electrode of the seventh P-type transistor P7, the second electrode of the seventh N-type transistor N7, the second electrode of the eighth P-type transistor P8, the second electrode of the ninth P-type transistor P9, and the second electrode of the ninth N-type transistor N9.

[0461] In an exemplary embodiment, the thirty-sixth connection electrode 636 , the thirty-eighth connection electrode 638 , the fortieth connection electrode 640 , the forty-fourth connection electrode 644 , and the fourth connection line 704 may be an integral structure connected to one another.

[0462] In an exemplary embodiment, the fourth connecting line 704 of the integrated structure, the second electrode of the seventh P-type transistor P7, the second electrode of the seventh N-type transistor N7, the second electrode of the eighth P-type transistor P8, the second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9 can serve as the second output terminal Q_ of the shift register circuit, which is connected to the second input terminal of the logic operation circuit, thereby enabling the shift register circuit to transmit the second output signal to the logic operation circuit.

[0463] In an exemplary embodiment, the orthographic projection of the fourth connecting line 704 on the silicon substrate at least partially overlaps with the orthographic projections of the eighth P-type gate electrode 208P and the eighth N-type gate electrode 208N of the integrated structure on the silicon substrate, and the orthographic projection of the fourth connecting line 704 on the silicon substrate at least partially overlaps with the orthographic projections of the ninth P-type gate electrode 209P and the ninth N-type gate electrode 209N of the integrated structure on the silicon substrate, that is, the fourth connecting line 704 crosses the gate electrode of the eighth transistor group (the eighth P-type transistor P8 and the eighth N-type transistor N8) and the gate electrode of the ninth transistor group (the ninth P-type transistor P9 and the ninth N-type transistor N9) and is connected to the second electrode of the ninth N-type transistor N9.

[0464] In an exemplary embodiment, the fifth connection line 705 may be in the shape of a bar extending along the first direction X. A first end of the fifth connection line 705 is connected to the thirteenth connection electrode 613, and a second end of the fifth connection line 705 is connected to the forty-fifth connection electrode 645 and the forty-seventh connection electrode 647 of the integrated structure. The fifth connection line 705 interconnects the gate electrode of the ninth P-type transistor P9, the gate electrode of the ninth N-type transistor N9, the second electrode of the tenth P-type transistor P10, and the second electrode of the tenth N-type transistor N10.

[0465] In exemplary embodiments, the thirteenth connection electrode 613 , the forty-fifth connection electrode 645 , the forty-seventh connection electrode 647 , and the fifth connection line 705 may be an integral structure connected to one another.

[0466] In an exemplary embodiment, the fifth connecting line 705 of the integrated structure, the gate electrode of the ninth P-type transistor P9, the gate electrode of the ninth N-type transistor N9, the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10 can serve as the first output terminal Q of the shift register circuit, which is connected to the first input terminal of the logic operation circuit, thereby enabling the shift register circuit to transmit the first output signal to the logic operation circuit.

[0467] In an exemplary embodiment, the sixth connection line 706 may be in the shape of a bar extending along the first direction X. A first end of the sixth connection line 706 is connected to the fifteenth connection electrode 615, and a second end of the sixth connection line 706 is connected to the fifty-third connection electrode 653 and the fifty-fifth connection electrode 655 of the integrated structure. The sixth connection line 706 interconnects the gate electrode of the eleventh P-type transistor P11, the gate electrode of the eleventh N-type transistor N11, the second electrode of the twelfth P-type transistor P12, and the second electrode of the twelfth N-type transistor N12.

[0468] In an exemplary embodiment, the fifteenth connection electrode 615 , the fifty-third connection electrode 653 , the fifty-fifth connection electrode 655 , and the sixth connection line 706 may be an integral structure connected to one another.

[0469] In an exemplary embodiment, the seventh connection line 707 may be in the shape of a strip extending along the first direction X. A first end of the seventh connection line 707 is connected to the fifth connection electrode 605, and a second end of the seventh connection line 707 is connected to the thirty-first connection electrode 631 and the thirty-third connection electrode 633 of the integrated structure. The seventh connection line 707 interconnects the gate electrode of the fourth P-type transistor P4, the gate electrode of the fourth N-type transistor N4, the first electrode of the sixth P-type transistor P6, and the first electrode of the sixth N-type transistor N6.

[0470] In an exemplary embodiment, the fifth connection electrode 605 , the thirty-first connection electrode 631 , the thirty-third connection electrode 633 , and the seventh connection line 707 may be an integral structure connected to one another.

[0471] In an exemplary embodiment, the seventh connection line 707 may be located on a side of the fifth N-type active region 105N away from the fifth P-type active region 105P, and the orthographic projection of the seventh connection line 707 on the silicon substrate does not overlap with the orthographic projection of the fifth N-type gate electrode 205N on the silicon substrate.

[0472] In an exemplary embodiment, since the second connection line 702 and the seventh connection line 707 are both connected to the fifth connection electrode 605, the second connection line 702 realizes the mutual connection between the second electrode of the second P-type transistor P2, the second electrode of the third P-type transistor P3, the second electrode of the second N-type transistor N2, the gate electrode of the fourth P-type transistor P4, and the gate electrode of the fourth N-type transistor N4, and the seventh connection line 707 realizes the mutual connection between the gate electrode of the fourth P-type transistor P4, the gate electrode of the fourth N-type transistor N4, the first electrode of the sixth P-type transistor P6, and the first electrode of the sixth N-type transistor N6, thereby realizing the mutual connection between the second electrode of the second P-type transistor P2, the second electrode of the second N-type transistor N2, the second electrode of the third P-type transistor P3, the gate electrode of the fourth P-type transistor P4, the gate electrode of the fourth N-type transistor N4, the first electrode of the sixth P-type transistor P6, and the first electrode of the sixth N-type transistor N6.

[0473] In exemplary embodiments, the fifth connection electrode 605 , the twentieth connection electrode 620 , the twenty-second connection electrode 622 , the thirty-first connection electrode 631 , the thirty-third connection electrode 633 , the second connection line 702 , and the seventh connection line 707 may be an integral structure connected to one another.

[0474] In an exemplary embodiment, one or more of the first to sixth connection lines 701 to 706 may be located in the gap region 50 between the P-type active region and the N-type active region, which is not only beneficial for optimizing the connection structure but also can reduce the impact on the transistor channel region.

[0475] FIG15C is an enlarged view of area A in FIG15A . As shown in FIG15A , FIG15B , and FIG15C , for a first strip-shaped connecting line 701 extending along a first direction X, at least a portion of the first connecting line 701 is disposed between the first P-type active region 101P and the first N-type active region 101N in the second direction Y, and at least a portion of the first connecting line 701 is disposed between the second P-type active region 102P and the second N-type active region 102N. For a second strip-shaped connecting line 702 extending along the first direction X, at least a portion of the second connecting line 702 is disposed between the second P-type active region 102P and the second N-type active region 102N in the second direction Y, and at least a portion of the second connecting line 702 is disposed between the third P-type active region 103P and the third N-type active region 103N. The second connecting line 702 may be disposed on one side of the first connecting line 701 in the second direction Y (proximal to the second N-type active region 102N).

[0476] In an exemplary embodiment, there is an electrode distance D between the edge of the first connecting line 701 close to the second connecting line 702 and the edge of the second connecting line 702 close to the first connecting line 701. The electrode distance D can be greater than or equal to 0.256 μm, avoiding metal adhesion between the electrodes while meeting the process requirements.

[0477] In an exemplary embodiment, a third distance S3 is provided between an edge of the first connection line 701 on a side close to the first P-type active region 101P and an edge of the first P-type active region 101P on a side close to the first connection line 701, and a fourth distance S4 is provided between an edge of the first connection line 701 on a side close to the first N-type active region 101N and an edge of the first N-type active region 101N on a side close to the first connection line 701. The third distance S3 may be less than or equal to the fourth distance S4.

[0478] In an exemplary embodiment, a ratio of the third distance S3 to the fourth distance S4 may be approximately 0.8 to 1.0.

[0479] In this exemplary embodiment, since the first connection line 701 is connected to the eighteenth connection electrode 618, and the eighteenth connection electrode 618 is connected to the first P-type drain region and the first N-type drain region, respectively, the eighteenth connection electrode 618 serves as both the first P-type drain electrode of the first P-type transistor and the first N-type drain electrode of the first N-type transistor. Therefore, the placement of the first connection line 701 can affect the signal writing quality. The present disclosure arranges the distance between the first connection line and the first P-type active region and the first N-type active region so that the first connection line is substantially positioned in the middle region between the two active regions, thereby ensuring synchronization of signal writing.

[0480] Figure 15D is an enlarged view of area B in Figure 15A. As shown in Figures 15A, 15B, and 15D, a strip-shaped third connection line 703 extending along the first direction X is disposed between the P-type active region and the N-type active region. A first end of the third connection line 703 is connected to the 32nd connection electrode 632 and the 34th connection electrode 634 of the integrated structure, and a second end of the third connection line 703 is connected to the 35th connection electrode 635 and the 37th connection electrode 637 of the integrated structure.

[0481] In an exemplary embodiment, a fifth distance S5 is provided between an edge of the third connection line 703 on a side close to the sixth P-type active region 106P and an edge of the sixth P-type active region 106P on a side close to the third connection line 703, or a fifth distance S5 is provided between an edge of the third connection line 703 on a side close to the seventh P-type active region 107P and an edge of the seventh P-type active region 107P on a side close to the third connection line 703, a sixth distance S6 is provided between an edge of the third connection line 703 on a side close to the sixth N-type active region 106N and an edge of the sixth N-type active region 106N on a side close to the third connection line 703, or a sixth distance S6 is provided between an edge of the third connection line 703 on a side close to the seventh N-type active region 107N and an edge of the seventh N-type active region 107N on a side close to the third connection line 703, and the ratio of the fifth distance S5 to the sixth distance S6 can be approximately 0.9 to 1.1.

[0482] In an exemplary embodiment, the fifth distance S5 and the sixth distance S6 may be substantially equal in distance.

[0483] In this exemplary embodiment, since the thirty-second connecting electrode 632 is connected to the sixth P-type drain region, the thirty-fourth connecting electrode 634 is connected to the sixth N-type drain region, the thirty-fifth connecting electrode 635 is connected to the seventh P-type source region, and the thirty-seventh connecting electrode 637 is connected to the seventh N-type source region, the placement of the third connecting line 703 can affect signal writing quality. The present disclosure arranges the distance between the third connecting line 703 and the P-type active region and the N-type active region so that the third connecting line 703 is substantially positioned in the middle between the two active regions, thereby ensuring synchronization of signal writing.

[0484] (8) Forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: depositing a third insulating film on the silicon substrate having the aforementioned pattern formed thereon, patterning the third insulating film through a patterning process to form a third insulating layer covering the first conductive layer pattern, wherein a plurality of vias are provided on the third insulating layer, as shown in FIG. 16 .

[0485] In an exemplary embodiment, the plurality of via holes may include a seventy-first via hole V71 to an eighty-sixth via hole V86 .

[0486] In an exemplary embodiment, the orthographic projection of the seventy-first via V71 on the silicon substrate is located within the range of the orthographic projection of the first connecting electrode 601 on the silicon substrate, the third insulating layer in the seventy-first via V71 is etched away to expose the surface of the first connecting electrode 601, and the seventy-first via V71 is configured to connect the subsequently formed first signal transfer line to the first connecting electrode 601 through the via.

[0487] In an exemplary embodiment, the orthographic projection of the seventy-second via V72 on the silicon substrate is located within the range of the orthographic projection of the second connecting electrode 602 on the silicon substrate, the third insulating layer in the seventy-second via V72 is etched away to expose the surface of the second connecting electrode 602, and the seventy-second via V72 is configured to connect a subsequently formed second signal transfer line to the second connecting electrode 602 through the via.

[0488] In an exemplary embodiment, the orthographic projection of the seventy-third via V73 on the silicon substrate is located within the range of the orthographic projection of the fourth connecting electrode 604 on the silicon substrate, the third insulating layer in the seventy-third via V73 is etched away to expose the surface of the fourth connecting electrode 604, and the seventy-third via V73 is configured to connect the subsequently formed third signal transfer line to the fourth connecting electrode 604 through the via.

[0489] In an exemplary embodiment, the orthographic projection of the seventy-fourth via V74 on the silicon substrate is located within the range of the orthographic projection of the second end of the seventh connecting electrode 607 on the silicon substrate, the third insulating layer in the seventy-fourth via V74 is etched away to expose the surface of the second end of the seventh connecting electrode 607, and the seventy-fourth via V74 is configured to connect the subsequently formed first signal transfer line to the second end of the seventh connecting electrode 607 through the via.

[0490] In an exemplary embodiment, the orthographic projection of the seventy-fifth via V75 on the silicon substrate is located within the range of the orthographic projection of the sixth connecting electrode 606 on the silicon substrate, the third insulating layer in the seventy-fifth via V75 is etched away to expose the surface of the sixth connecting electrode 606, and the seventy-fifth via V75 is configured to connect the subsequently formed second signal transfer line to the sixth connecting electrode 606 through the via.

[0491] In an exemplary embodiment, the orthographic projection of the seventy-sixth via V76 on the silicon substrate is located within the range of the orthographic projection of the second end of the ninth connecting electrode 609 on the silicon substrate, the third insulating layer in the seventy-sixth via V76 is etched away to expose the surface of the second end of the ninth connecting electrode 609, and the seventy-sixth via V76 is configured to connect the subsequently formed first signal transfer line to the second end of the ninth connecting electrode 609 through the via.

[0492] In an exemplary embodiment, the orthographic projection of the seventy-seventh via V77 on the silicon substrate is located within the range of the orthographic projection of the second end of the eighth connecting electrode 608 on the silicon substrate, the third insulating layer in the seventy-seventh via V77 is etched away to expose the surface of the second end of the eighth connecting electrode 608, and the seventy-seventh via V77 is configured to connect the subsequently formed second signal transfer line to the second end of the eighth connecting electrode 608 through the via.

[0493] In an exemplary embodiment, the orthographic projection of the seventy-eighth via V78 on the silicon substrate is located within the range of the orthographic projection of the tenth connecting electrode 610 on the silicon substrate, the third insulating layer in the seventy-eighth via V78 is etched away to expose the surface of the tenth connecting electrode 610, and the seventy-eighth via V78 is configured to connect the subsequently formed first signal transfer line to the tenth connecting electrode 610 through the via.

[0494] In an exemplary embodiment, the orthographic projection of the seventy-ninth via V79 on the silicon substrate is located within the range of the orthographic projection of the eleventh connecting electrode 611 on the silicon substrate, the third insulating layer in the seventy-ninth via V79 is etched away to expose the surface of the eleventh connecting electrode 611, and the seventy-ninth via V79 is configured to connect a subsequently formed second signal transfer line to the eleventh connecting electrode 611 through the via.

[0495] In an exemplary embodiment, the orthographic projection of the 80th via V80 on the silicon substrate is located within the range of the orthographic projection of the twelfth connecting electrode 612 on the silicon substrate, the third insulating layer in the 80th via V80 is etched away to expose the surface of the twelfth connecting electrode 612, and the 80th via V80 is configured to connect a subsequently formed third signal transfer line to the twelfth connecting electrode 612 through the via.

[0496] In an exemplary embodiment, the orthographic projection of the eighty-first via V81 on the silicon substrate is located within the range of the orthographic projection of the fourteenth connecting electrode 614 on the silicon substrate, the third insulating layer in the eighty-first via V81 is etched away to expose the surface of the fourteenth connecting electrode 614, and the eighty-first via V81 is configured to connect the subsequently formed fifth signal transfer line to the fourteenth connecting electrode 614 through the via.

[0497] In an exemplary embodiment, the orthographic projection of the eighty-second via V82 on the silicon substrate is located within the range of the orthographic projection of the fifteenth connecting electrode 615 on the silicon substrate, the third insulating layer in the eighty-second via V82 is etched away to expose the surface of the fifteenth connecting electrode 615, and the eighty-second via V82 is configured to enable a subsequently formed second signal transfer line to be connected to the fifteenth connecting electrode 615 through the via.

[0498] In an exemplary embodiment, the orthographic projection of the eighty-third via V83 on the silicon substrate is located within the range of the orthographic projection of the first bump k1 on the silicon substrate, the third insulating layer in the eighty-third via V83 is etched away to expose the surface of the first bump k1, and the eighty-third via V83 is configured to connect the subsequently formed fourth signal transfer line to the first bump k1 through the via.

[0499] In an exemplary embodiment, the orthographic projection of the eighty-fourth via V84 on the silicon substrate is located within the range of the orthographic projection of the second bump k2 on the silicon substrate, the third insulating layer in the eighty-fourth via V84 is etched away to expose the surface of the second bump k2, and the eighty-fourth via V84 is configured to connect the subsequently formed fourth signal transfer line to the second bump k2 through the via.

[0500] In an exemplary embodiment, the orthographic projection of the eighty-fifth via V85 on the silicon substrate is located within the range of the orthographic projection of the third connecting line 703 on the silicon substrate, the third insulating layer in the eighty-fifth via V85 is etched away to expose the surface of the third connecting line 703, and the eighty-fifth via V85 is configured to connect the subsequently formed fifth signal transfer line to the third connecting line 703 through the via.

[0501] In an exemplary embodiment, the orthographic projection of the eighty-sixth via V86 on the silicon substrate is located within the range of the orthographic projection of the third bump k3 on the silicon substrate, the third insulating layer in the eighty-sixth via V86 is etched away to expose the surface of the third bump k3, and the eighty-sixth via V86 is configured to connect the subsequently formed first signal transfer line to the third bump k3 through the via.

[0502] In an exemplary embodiment, one or more of the seventy-first to eighty-sixth via holes V71 to V86 may be plural to reduce contact resistance and improve connection reliability.

[0503] (9) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the silicon substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process, and forming a second conductive layer pattern on the third insulating layer, as shown in FIG. 17A and FIG. 17B , where FIG. 17B is a schematic diagram of the second conductive layer in FIG. 17A . In an exemplary embodiment, the second conductive layer may be referred to as a second metal (Metal 2) layer.

[0504] In an exemplary embodiment, the second conductive layer pattern may include at least a first signal transition line 801 , a second signal transition line 802 , a third signal transition line 803 , a fourth signal transition line 804 , and a fifth signal transition line 805 .

[0505] In an exemplary embodiment, the shape of the first signal transfer line 801 can be a straight line or a broken line extending along the first direction X, and the first signal transfer line 801 can be connected to the first connection electrode 601 through the seventy-first via V71, connected to the second end of the seventh connection electrode 607 through the seventy-fourth via V74, connected to the second end of the ninth connection electrode 609 through the seventy-sixth via V76, connected to the tenth connection electrode 610 through the seventy-eighth via V78, and connected to the third bump k3 through the eighty-sixth via V86.

[0506] In an exemplary embodiment, since the first connecting electrode 601 is connected to the first P-type gate electrode through a via, the seventh connecting electrode 607 is connected to the fifth N-type gate electrode through a via, the ninth connecting electrode 609 is connected to the sixth N-type gate electrode through a via, the tenth connecting electrode 610 is connected to the seventh P-type gate electrode through a via, and the third bump k3 is connected to the eleventh P-type drain region and the eleventh N-type drain region, the first signal transfer line 801 realizes the mutual connection between the gate electrode of the first P-type transistor P1, the gate electrode of the fifth N-type transistor N5, the gate electrode of the sixth N-type transistor N6, the gate electrode of the seventh P-type transistor P7, the second electrode of the eleventh P-type transistor P11 and the second electrode of the eleventh N-type transistor N11.

[0507] In an exemplary embodiment, along the first direction X, the first signal transfer line 801 may have a first signal transmission length LT1, and the first signal transmission length LT1 may be the distance between the geometric center of the seventy-first via V71 close to the side of the eighty-sixth via V86 and the geometric center of the eighty-sixth via V86 close to the side of the seventy-first via V71.

[0508] In an exemplary embodiment, the seventy-first via V71 close to the side of the eighty-sixth via V86 can serve as the first transfer via of the present disclosure, and the eighty-sixth via V86 close to the side of the seventy-first via V71 can serve as the second transfer via of the present disclosure, and the area between the first transfer via and the second transfer via in the first signal transfer line 801 is the minimum distance for signal transmission.

[0509] In an exemplary embodiment, the first signal trace 801 may have a first trace width WT1 , which may be a dimension in the second direction Y.

[0510] In an exemplary embodiment, the shape of the second signal transfer line 802 can be a straight line or a broken line extending along the first direction X. The second signal transfer line 802 can be connected to the second connection electrode 602 through the seventy-second via V72, connected to the sixth connection electrode 606 through the seventy-fifth via V75, connected to the second end of the eighth connection electrode 608 through the seventy-seventh via V77, connected to the eleventh connection electrode 611 through the seventy-ninth via V79, and connected to the fifteenth connection electrode 615 through the eighty-second via V82.

[0511] In the exemplary embodiment, the second connection electrode 602 is connected to the first N-type gate electrode 201N through a via hole, the sixth connection electrode 606 is connected to the fifth P-type gate electrode 205P through a via hole, the first end of the eighth connection electrode 608 is connected to the sixth P-type gate electrode 206P through a via hole, the eleventh connection electrode 611 is connected to the seventh N-type gate electrode 207N through a via hole, and the fifteenth connection electrode 615 is connected to the eleventh P-type gate electrode 211P and the eleventh N-type gate electrode 211N through a via hole. The second signal transfer line 802 is connected to the fifty-third connection electrode 653 and the fifty-fifth connection electrode 655 of the integrated structure through the sixth connection line 706, so that the gate electrode of the first N-type transistor N1, the gate electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, the gate electrode of the seventh N-type transistor N7, the gate electrode of the eleventh P-type transistor P11, the gate electrode of the eleventh N-type transistor N11, the second electrode of the twelfth P-type transistor P12 and the second electrode of the twelfth N-type transistor N12 are interconnected.

[0512] In an exemplary embodiment, along the first direction X, the second signal transfer line 802 may have a second signal transmission length LT2, and the second signal transmission length LT2 may be the distance between the geometric center of the seventy-second via V72 near the side of the eighty-second via V82 and the geometric center of the eighty-second via V82 near the side of the seventy-second via V72.

[0513] In an exemplary embodiment, the seventy-second via V72 close to the side of the eighty-second via V82 can serve as the third transfer via of the present disclosure, and the eighty-second via V82 close to the side of the seventy-second via V72 can serve as the fourth transfer via of the present disclosure, and the area between the third transfer via and the fourth transfer via in the second signal transfer line 802 is the minimum distance for signal transmission.

[0514] In an exemplary embodiment, the second signal trace 802 may have a second trace width WT2 , which may be a dimension in the second direction Y.

[0515] In an exemplary embodiment, a ratio of the first patch line width WT1 to the second patch line width WT2 may be approximately 0.95 to 1.05.

[0516] In an exemplary embodiment, the first patch line width WT1 and the second patch line width WT2 may be substantially equal.

[0517] In exemplary embodiments, the second signal transmission length LT2 may be greater than the first signal transmission length LT1 .

[0518] In an exemplary embodiment, the difference between the second signal transmission length LT2 and the first signal transmission length LT1 may be greater than or equal to 0.8 μm. For example, LT2 − LT1 may be approximately 1.0 μm.

[0519] In an exemplary embodiment, the clock signal clk output from the clock signal terminal CK in the shift register circuit passes through the twelfth P-type transistor P12 and the twelfth N-type transistor N12 (the first inverter) to become the inverted clock signal clkb. A portion of the signal in the inverted clock signal clkb passes through the eleventh P-type transistor P11 and the eleventh N-type transistor N11 (the second inverter) to become the clock signal clk, which is transmitted to the first transmission gate, the second transmission gate, and the third transmission gate by the first signal transfer line 801, respectively. Another portion of the signal in the inverted clock signal clkb is transmitted to the first transmission gate, the second transmission gate, and the third transmission gate, respectively, by the second signal transfer line 802. The present disclosure can offset the clock signal delay of the second inverter by setting the relationship between the signal transmission lengths in the first signal transfer line 801 and the second signal transfer line 802, thereby ensuring the consistency of the clock signal delay and improving the electrical performance of the shift register circuit.

[0520] In an exemplary embodiment, at least one of the first signal transfer line 801 and the second signal transfer line 802 may be located in the gap region 50 between the P-type active region and the N-type active region, which can not only optimize the connection structure but also reduce the impact on the transistor channel region.

[0521] In an exemplary embodiment, the first signal transfer line 801 may be disposed on a side of the gap region 50 close to the P-type active region, and the second signal transfer line 802 may be disposed on a side of the gap region 50 close to the N-type active region.

[0522] In an exemplary embodiment, the orthographic projections of the first signal transfer line 801 and the second signal transfer line 802 on the silicon substrate do not overlap with the orthographic projection of the first connecting line 701 on the silicon substrate, and the orthographic projections of the first signal transfer line 801 and the second signal transfer line 802 on the silicon substrate do not overlap with the orthographic projection of the fifth connecting line 705 on the silicon substrate, thereby reducing the interference of the clock signal on the shift register circuit.

[0523] In an exemplary embodiment, the shape of the third signal transfer line 803 can be a straight line or a broken line extending along the first direction X, the first end of the third signal transfer line 803 is connected to the fourth connection electrode 604 through the seventy-third via V73, and the second end of the third signal transfer line 803 is connected to the twelfth connection electrode 612 through the eightieth via V80.

[0524] In an exemplary embodiment, since the fourth connection electrode 604 is connected to the third P-type gate electrode 203P (also the third N-type gate electrode 203N) through a via, and the twelfth connection electrode 612 is connected to the eighth P-type gate electrode 208P (also the eighth N-type gate electrode 208N) through a via, the third signal routing line 803 realizes the interconnection between the gate electrode of the third P-type transistor P3, the gate electrode of the third N-type transistor N3, the gate electrode of the eighth P-type transistor P8, and the gate electrode of the eighth N-type transistor N8. In an exemplary embodiment, the third signal routing line 803 is configured to be connected to the reset terminal RN of the shift register circuit via a connecting line formed subsequently.

[0525] In an exemplary embodiment, the orthographic projection of the third signal transfer line 803 on the silicon substrate at least partially overlaps with the orthographic projection of the P-type gate electrodes in the third inverter (fourth P-type transistor P4, fifth P-type transistor P5), the second transmission gate (sixth P-type transistor P6) and the third transmission gate (seventh P-type transistor P7) on the silicon substrate, that is, the third signal transfer line 803 crosses four P-type transistors to achieve connection between the third transistor group and the eighth transistor group.

[0526] In an exemplary embodiment, the shape of the fourth signal transfer line 804 can be a straight line or a broken line extending along the first direction X, the first end of the fourth signal transfer line 804 is connected to the first bump k1 through the eighty-third via V83, and the second end of the fourth signal transfer line 804 is connected to the second bump k2 through the eighty-fourth via V84.

[0527] In an exemplary embodiment, the fourth signal transfer line 804 realizes the interconnection between the second electrode of the first P-type transistor P1, the second electrode of the first N-type transistor N1, the gate electrode of the second P-type transistor P2, the gate electrode of the second N-type transistor N2, the second electrode of the fifth P-type transistor P5 and the second electrode of the fifth N-type transistor N5.

[0528] In an exemplary embodiment, the orthographic projection of the fourth signal transfer line 804 on the silicon substrate at least partially overlaps with the orthographic projection of the P-type gate electrodes in the first NAND gate (the second P-type transistor P2 and the third P-type transistor P3) and the third inverter (the fourth P-type transistor P4 and the fifth P-type transistor P5) on the silicon substrate, that is, the fourth signal transfer line 804 crosses the four P-type transistors to achieve interconnection between the first transistor group, the second transistor group and the fifth transistor group.

[0529] In an exemplary embodiment, the shape of the fifth signal transfer line 805 can be a straight line or a broken line extending along the first direction X, the first end of the fifth signal transfer line 805 is connected to the third connection line 703 through the eighty-fifth via V85, and the second end of the fifth signal transfer line 805 is connected to the fourteenth connection electrode 614 through the eighty-first via V81.

[0530] In an exemplary embodiment, since the third connecting line 703 realizes the interconnection between the second electrode of the sixth P-type transistor P6, the second electrode of the sixth N-type transistor N6, the first electrode of the seventh P-type transistor P7 and the first electrode of the seventh N-type transistor N7, the fourteenth connecting electrode 614 is connected to the tenth P-type gate electrode 210P (also the tenth N-type gate electrode 210N) through a via, the fifth signal transfer line 805 realizes the interconnection between the second electrode of the sixth P-type transistor P6, the second electrode of the sixth N-type transistor N6, the first electrode of the seventh P-type transistor P7, the first electrode of the seventh N-type transistor N7, the gate electrode of the tenth P-type transistor P10 and the gate electrode of the tenth N-type transistor N10.

[0531] In an exemplary embodiment, the fifth signal transfer line 805 connects the sixth transistor group, the seventh transistor group, and the tenth transistor group across three P-type transistors (the seventh P-type transistor P7 , the eighth P-type transistor P8 , and the ninth P-type transistor P9 ).

[0532] In an exemplary embodiment, the fifth signal transfer line 805 can be located in the gap area 50 between the P-type active area and the N-type active area, and the orthographic projection of the fifth signal transfer line 805 on the silicon substrate does not overlap with the orthographic projection of the P-type active area in the third transmission gate (seventh P-type transistor P7) and the second NAND gate (eighth P-type transistor P8 and ninth P-type transistor P9) on the silicon substrate, and the orthographic projection of the fifth signal transfer line 805 on the silicon substrate does not overlap with the orthographic projection of the N-type active area in the third transmission gate (seventh N-type transistor N7) and the second NAND gate (eighth N-type transistor N8 and ninth N-type transistor N9) on the silicon substrate, thereby reducing the impact of the fifth signal transfer line 805 on the transistor channel area.

[0533] In an exemplary embodiment, the fourth signal patching line 804 , the third signal patching line 803 , the first signal patching line 801 , the fifth signal patching line 805 , and the second signal patching line 802 may be sequentially disposed along the second direction Y.

[0534] At this point, the preparation of the display substrate according to the exemplary embodiment of the present disclosure is completed.

[0535] In an exemplary embodiment, the first to third insulating layers may be made of silicon oxide SiOx, silicon nitride SiNx, or silicon oxynitride SiON, and may be a single-layer structure or a multi-layer composite structure. The first metal layer and the second metal layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), or molybdenum (Mo), or may be an alloy material composed of a metal such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb). The alloy material may be a single-layer structure or a multi-layer composite structure, such as a composite structure composed of a Mo layer, a Cu layer, and a Mo layer. In an exemplary embodiment, the planar shape of the via hole may be rectangular, circular, or elliptical, and the sizes of the multiple via holes may be substantially the same or different, which is not limited in this disclosure.

[0536] An existing shift register circuit has complex design and lacks a reset terminal, making it incapable of meeting the requirements of gate drive circuits in display substrates. The exemplary embodiments of the present disclosure provide a display substrate in which a shift register circuit in a gate drive circuit utilizes fewer transistors to implement a shift register function while also providing a reset function. This shift register circuit can drive display panels with pixel densities of 4K or higher, and is suitable for use in silicon-based OLED display devices with pixel densities of 4K or higher.

[0537] The present disclosure makes the propagation delay symmetrical by setting the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor, so that the rise and fall times of the P-type transistor and the N-type transistor are basically equal, the noise margins of the high and low levels are basically the same, and the charge and discharge times are basically consistent, thereby improving the electrical performance of the inverter in the shift register circuit.

[0538] The present invention can reduce the mutual influence between the NAND gate and the inverter by setting the position relationship between the P-type active area of ​​the first NAND gate and the P-type active area of ​​the third inverter, improve the working reliability of the shift register circuit, and ensure the signal of the gate drive circuit.

[0539] By setting the minimum width of each area, the present disclosure can effectively reduce the mutual influence between the P-type active area and the N-type active area, between the P-type active area and the first power line, between the N-type active area and the ground line, and between the first power line and the ground line, thereby improving the working reliability of the shift register circuit and ensuring the signal output quality of the gate drive circuit.

[0540] The present disclosure sets the distance relationship between the first connection electrode and the first P-type active area and the first N-type active area so that the first connection electrode is basically set in the middle area between the two active areas, thereby ensuring synchronization of signal writing.

[0541] The present disclosure sets the distance relationship between the third connection line and the P-type active area and the N-type active area so that the third connection line is basically set in the middle area between the two active areas, thereby ensuring synchronization of signal writing.

[0542] The present disclosure can offset the clock signal delay of the second inverter by setting the relationship between the signal transmission lengths in the first signal adapter and the second signal adapter, thereby ensuring the consistency of the clock signal delay and improving the electrical performance of the shift register circuit.

[0543] The present disclosure sets the positions of multiple gate connection vias, which not only ensures process uniformity and signal transmission uniformity, but also facilitates the arrangement of connection electrodes, optimizes the connection structure between the first conductive layer and the gate conductive layer, and reduces the occupied area of ​​the gate drive circuit.

[0544] The present disclosure sets the positions of the connecting lines and the signal adapter lines, which can facilitate layout, optimize the connection structure, reduce the impact on the transistor channel area, and improve the circuit quality and signal quality of the gate drive circuit.

[0545] The present disclosure optimizes the layout of the gate drive circuit through the above-mentioned structural design, optimizes the layout space, reduces the occupied area of ​​the gate drive circuit, improves the circuit quality and signal quality, and can achieve higher display quality and display effect.

[0546] The preparation process disclosed herein can be realized using mature preparation equipment, requires little process improvement, has high compatibility, is simple to realize, is easy to implement, has high production efficiency, low production cost, and high yield rate.

[0547] The structure of the substrate and its preparation process shown in the exemplary embodiment of the present disclosure are merely exemplary descriptions. The corresponding structure can be changed and the patterning process can be increased or decreased according to actual conditions, and the present disclosure does not limit them here.

[0548] The exemplary embodiments of the present disclosure further provide a display device including the aforementioned display substrate. The display device of the present disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights, rangefinders, and the like.

[0549] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A gate drive circuit, comprising a shift register circuit disposed on a silicon substrate, the shift register circuit comprising at least a plurality of transistor groups sequentially arranged along a first direction, at least one transistor group comprising a P-type transistor and an N-type transistor disposed to one side of the P-type transistor in a second direction, the first direction intersecting the second direction; the P-type transistor comprising at least a P-type active region, the N-type transistor comprising at least an N-type active region, a gap region being defined between the P-type active region and the N-type active region in the second direction, the gap region having a gap centerline, the gap centerline being a straight line bisecting the gap region in the second direction and extending in the first direction; the plurality of transistor groups forming at least one transmission gate, at least one NAND gate, and at least one inverter, the gap centerlines of the transistor groups in the at least one transmission gate, the at least one NAND gate, and the at least one inverter being located on the same straight line extending in the first direction.

2. The gate drive circuit according to claim 1, wherein: A plurality of transistor groups form a first transmission gate, a first NAND gate, a third inverter, a second transmission gate, a third transmission gate, a second NAND gate, a fourth inverter, a second inverter and a first inverter which are arranged in sequence along the first direction; the widths of the gap regions of the transistor groups in devices of the same type are the same, the center lines of the gaps of the transistor groups in devices of the same type are on the same straight line extending along the first direction, and the width of the gap regions is the dimension in the second direction.

3. The gate driving circuit according to claim 2, wherein: The width of the gap region between transistor groups varies between different device types.

4. The gate driving circuit according to claim 2, wherein: The width-to-length ratios of P-type transistors in the same type of devices are the same, and the width-to-length ratios of N-type transistors in the same type of devices are the same.

5. The gate driving circuit according to claim 2, wherein: The width-to-length ratios of P-type transistors in different types of devices are different, and the width-to-length ratios of N-type transistors in different types of devices are different.

6. The gate driving circuit according to claim 2, wherein: In at least one of the first inverter, the second inverter, the third inverter, and the fourth inverter, a ratio of a width-to-length ratio of the P-type transistor to a width-to-length ratio of the N-type transistor is greater than 1 and less than 3.

7. The gate driving circuit according to claim 2, wherein: In at least one of the first NAND gate and the second NAND gate, a ratio of a width-to-length ratio of the P-type transistor to a width-to-length ratio of the N-type transistor is greater than 1.3 and less than 3.

3.

8. The gate driving circuit according to claim 2, wherein: In at least one of the first transmission gate, the second transmission gate, and the third transmission gate, a ratio of a width-to-length ratio of the P-type transistor to a width-to-length ratio of the N-type transistor is greater than 0.9 and less than 1.

1.

9. The gate driving circuit according to claim 2, wherein: The ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first NAND gate is greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter, and the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first inverter is greater than the ratio of the width-to-length ratio of the P-type transistor to the width-to-length ratio of the N-type transistor in the first transmission gate.

10. The gate driving circuit according to claim 1, wherein: The shift register circuit also includes a power active region and a ground active region. The power active region is arranged on a side of the P-type active region away from the N-type active region, and the ground active region is arranged on a side of the N-type active region away from the P-type active region. The power active region has a first center line, and the ground active region has a second center line. The first center line is a straight line that bisects the power active region in the second direction and extends along the first direction. The second center line is a straight line that bisects the ground active region in the second direction and extends along the first direction. In the second direction, the distance between the first center line and the second center line is less than or equal to 6.3 μm.

11. The gate driving circuit according to claim 10, wherein: In at least one transistor group, a first width is provided between the first center line and the edge of the P-type active area close to the first center line, and a second width is provided between the second center line and the edge of the N-type active area close to the second center line. The first width is greater than 1 μm and less than 3 μm, and the second width is greater than 1 μm and less than 3 μm. The first width and the second width are dimensions in the second direction.

12. The gate driving circuit according to claim 10, wherein: In at least one transistor group, a third width exists between an edge of the P-type active region away from the first center line and an edge of the N-type active region away from the second center line. The third width is greater than or equal to 1.5 μm, and the third width is the dimension in the second direction.

13. The gate driving circuit according to claim 10, wherein: In at least one transistor group, a P-type active area width is provided between an edge of the P-type active area close to the first center line and an edge of the P-type active area away from the first center line; an N-type active area width is provided between an edge of the N-type active area close to the second center line and an edge of the N-type active area away from the second center line; the P-type active area width is greater than 1 μm and less than 3 μm, and the N-type active area width is greater than 1 μm and less than 3 μm, and the P-type active area width and the N-type active area width are dimensions in the second direction.

14. The gate driving circuit according to claim 13, wherein: Multiple transistor groups form a first transmission gate, a first NAND gate, a third inverter, a second transmission gate, a third transmission gate, a second NAND gate, a fourth inverter, a second inverter and a first inverter arranged in sequence along the first direction; the P-type active area widths in devices of the same type are the same, the N-type active area widths in devices of the same type are the same, the P-type active area widths in devices of different types are different, and the N-type active area widths in devices of different types are different.

15. The gate driving circuit according to claim 14, wherein: At least one P-type active area has a P-type active center line, which is a straight line that bisects the P-type active area in the second direction and extends in the first direction; the P-type active center lines in devices of the same type are on the same straight line extending along the first direction, and the P-type active center lines in devices of different types are not on the same straight line extending along the first direction X.

16. The gate driving circuit according to claim 14, wherein: At least one N-type active region has an N-type active centerline, where the N-type active centerline is a straight line that bisects the N-type active region in the second direction and extends in the first direction; the N-type active centerlines in devices of the same type are on the same straight line extending in the first direction, and the N-type active centerlines in devices of different types are not on the same straight line extending in the first direction X.

17. The gate driving circuit according to claim 2, wherein: The first NAND gate includes at least a third P-type transistor, and the third P-type transistor includes at least a third P-type active area; the third inverter includes at least a fourth P-type transistor, and the fourth P-type transistor includes at least a fourth P-type active area; there is a first distance between an edge of the third P-type active area away from the gap area and an edge of the fourth P-type active area away from the gap area, and there is a second distance between an edge of the third P-type active area close to the gap area and an edge of the fourth P-type active area close to the gap area, the first distance is greater than the second distance, and the first distance and the second distance are dimensions in the second direction.

18. The gate driving circuit according to claim 2, wherein: The first transmission gate includes a first P-type transistor and a first N-type transistor, and the first NAND gate includes a second P-type transistor, a second N-type transistor, a third P-type transistor and a third N-type transistor; The first P-type transistor includes at least a first P-type active area and a first P-type drain electrode, and the first P-type drain electrode is connected to the second area of ​​the first P-type active area through a via; the first N-type transistor includes at least a first N-type active area and a first N-type drain electrode, and the first N-type drain electrode is connected to the second area of ​​the first N-type active area through a via; the shift register circuit also includes a first connecting line, the first connecting line is in the shape of a strip extending along the first direction, the first end of the first connecting line is respectively connected to the first P-type drain electrode and the first N-type drain electrode, and the second end of the first connecting line is respectively connected to the P-type gate electrode of the second P-type transistor P2 and the N-type gate electrode of the second N-type transistor N2; in the second direction, the first connecting line is arranged in the gap area.

19. The gate driving circuit according to claim 18, wherein: There is a third distance between the edge of the first connecting line close to the first P-type active region and the edge of the first P-type active region close to the first connecting line; there is a fourth distance between the edge of the first connecting line close to the first N-type active region and the edge of the first N-type active region close to the first connecting line, the third distance is less than or equal to the fourth distance, and the third distance and the fourth distance are dimensions in the second direction.

20. The gate driving circuit according to claim 19, wherein: A ratio of the third distance to the fourth distance is 0.8 to 1.

0.

21. The gate driving circuit according to claim 18, wherein: The second P-type transistor includes at least a second P-type active area and a second P-type drain electrode, and the second P-type drain electrode is connected to the second area of ​​the second P-type active area through a via. The second N-type transistor includes at least a second N-type active area and a second N-type drain electrode, and the second N-type drain electrode is connected to the second area of ​​the second N-type active area through a via. The third P-type transistor includes at least a third P-type active area and a third P-type drain electrode, and the third P-type drain electrode is connected to the second area of ​​the third P-type active area through a via. The shift register circuit also includes a second connecting line, and the second connecting line is in the shape of a strip extending along the first direction. The first end of the second connecting line is connected to the second N-type drain electrode, and the second end of the second connecting line is respectively connected to the second P-type drain electrode and the third P-type drain electrode. In the second direction, the second connecting line is arranged in the gap area.

22. The gate driving circuit according to claim 21, wherein: The second connecting line is arranged on a side of the first connecting line close to the second N-type active region, and an electrode distance is provided between an edge of the second connecting line close to the first connecting line and an edge of the first connecting line close to the second connecting line. The electrode distance is greater than or equal to 0.256 μm, and the electrode distance is the dimension in the second direction.

23. The gate driving circuit according to claim 21, wherein: The orthographic projection of the second connecting line on the silicon substrate at least partially overlaps with the orthographic projections of the P-type gate electrode of the second P-type transistor and the N-type gate electrode of the second N-type transistor on the silicon substrate, and the orthographic projection of the second connecting line on the silicon substrate at least partially overlaps with the orthographic projections of the P-type gate electrode of the third P-type transistor and the N-type gate electrode of the third N-type transistor on the silicon substrate.

24. The gate driving circuit according to claim 2, wherein: The second transmission gate includes a sixth P-type transistor and a sixth N-type transistor, and the third transmission gate includes a seventh P-type transistor and a seventh N-type transistor; The sixth P-type transistor at least includes a sixth P-type active area and a sixth P-type drain electrode, and the sixth P-type drain electrode is connected to the second area of ​​the sixth P-type active area through a via hole. The sixth N-type transistor at least includes a sixth N-type active area and a sixth N-type drain electrode, and the sixth N-type drain electrode is connected to the second area of ​​the sixth N-type active area through a via hole. The seventh P-type transistor at least includes a seventh P-type active area and a seventh P-type source electrode, and the seventh P-type source electrode is connected to the first area of ​​the seventh P-type active area through a via hole. The seventh N-type transistor at least includes The shift register circuit further comprises a seventh N-type active region and a seventh N-type source electrode, the seventh N-type source electrode being connected to the first region of the seventh N-type active region through a via; the shift register circuit further comprises a third connecting line, the third connecting line being in the shape of a strip extending along the first direction, the first end of the third connecting line being respectively connected to the sixth P-type drain electrode and the sixth N-type drain electrode, the second end of the third connecting line being respectively connected to the seventh P-type source electrode and the seventh N-type source electrode; in the second direction, the third connecting line is arranged in the gap region.

25. The gate driving circuit according to claim 24, wherein: There is a fifth distance between the edge of the third connecting line close to the sixth P-type active region and the edge of the sixth P-type active region close to the third connecting line, and there is a sixth distance between the edge of the third connecting line close to the sixth N-type active region and the edge of the sixth N-type active region close to the third connecting line. The ratio of the fifth distance to the sixth distance is 0.9 to 1.

1.

26. The gate driving circuit according to claim 2, wherein: The third transmission gate includes a seventh P-type transistor and a seventh N-type transistor, and the second NAND gate includes an eighth P-type transistor, an eighth N-type transistor, a ninth P-type transistor and a ninth N-type transistor; The seventh P-type transistor includes at least a seventh P-type active area and a seventh P-type drain electrode, and the seventh P-type drain electrode is connected to the second area of ​​the seventh P-type active area through a via. The seventh N-type transistor includes at least a seventh N-type active area and a seventh N-type drain electrode, and the seventh N-type drain electrode is connected to the second area of ​​the seventh N-type active area through a via. The eighth P-type transistor includes at least an eighth P-type active area and an eighth P-type drain electrode, and the eighth P-type drain electrode is connected to the second area of ​​the eighth P-type active area through a via. The ninth P-type transistor includes at least a ninth P-type active area and a ninth P-type drain electrode, and the ninth P-type drain electrode is connected to the second area of ​​the ninth P-type active area through a via. , the ninth N-type transistor at least includes a ninth N-type active region and a ninth N-type drain electrode, the ninth N-type drain electrode is connected to the second region of the ninth N-type active region through a via; the shift register circuit also includes a fourth connecting line, the fourth connecting line is in the shape of a strip extending along the first direction, the first end of the fourth connecting line is respectively connected to the seventh P-type drain electrode and the seventh N-type drain electrode, and the second end of the fourth connecting line is connected to the ninth N-type drain electrode; the area between the first end and the second end of the fourth connecting line is respectively connected to the eighth P-type drain electrode and the ninth P-type drain electrode; in the second direction, the fourth connecting line is arranged in the gap area.

27. The gate driving circuit according to claim 26, wherein: The orthographic projection of the fourth connecting line on the silicon substrate at least partially overlaps with the orthographic projections of the P-type gate electrode of the eighth P-type transistor and the N-type gate electrode of the eighth N-type transistor on the silicon substrate, and the orthographic projection of the fourth connecting line on the silicon substrate at least partially overlaps with the orthographic projections of the P-type gate electrode of the ninth P-type transistor and the N-type gate electrode of the ninth N-type transistor on the silicon substrate.

28. The gate driving circuit according to claim 2, wherein: The third inverter includes at least a fourth N-type transistor and a fifth N-type transistor, and the second NAND gate includes at least a sixth N-type transistor; the fourth N-type transistor includes at least a fourth N-type gate electrode, the fifth N-type transistor includes at least a fifth N-type gate electrode, and the sixth N-type transistor includes at least a sixth N-type active area and a sixth N-type source electrode, and the sixth N-type source electrode is connected to the first area of ​​the sixth N-type active area through a via; the shift register circuit also includes a seventh connecting line, the seventh connecting line is in the shape of a strip extending along the first direction, a first end of the seventh connecting line is connected to the fourth N-type gate electrode, and a second end of the seventh connecting line is connected to the sixth N-type source electrode; the seventh connecting line is arranged on a side of the fifth N-type active area away from the gap area.

29. The gate driving circuit according to claim 28, wherein: An orthographic projection of the seventh connecting line on the silicon substrate does not overlap with an orthographic projection of the fifth N-type gate electrode on the silicon substrate.

30. The gate driving circuit according to claim 2, wherein: The transistor group in the third inverter includes a first gate connection electrode, the first gate connection electrode is connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through a first gate via, and the first gate via is provided in the gap region; An orthographic projection of the first gate via on the silicon substrate at least partially overlaps with an orthographic projection of the gap center line on the silicon substrate.

31. The gate driving circuit according to claim 30, wherein: At least one transistor group in the first inverter, the second inverter, and the fourth inverter includes a second gate connection electrode, the second gate connection electrode is connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through a second gate via, and the second gate via is arranged in the gap area; in the second direction, the second gate via is closer to the N-type active area of ​​the N-type transistor than the first gate via.

32. The gate driving circuit according to claim 30, wherein: At least one transistor group in the first NAND gate and the second NAND gate includes a third gate connection electrode, the third gate connection electrode is connected to the P-type gate electrode of the P-type transistor and the N-type gate electrode of the N-type transistor through a third gate via, and the third gate via is provided in the gap region; In the second direction, the third gate via is closer to the P-type active region of the P-type transistor than to the first gate via.

33. The gate driving circuit according to claim 30, wherein: At least one transistor group among the first transmission gate, the second transmission gate and the third transmission gate includes a fourth P-type gate connection electrode and a fourth N-type gate connection electrode, the fourth P-type gate connection electrode is connected to the P-type gate electrode of the P-type transistor through a fourth P-type gate via, the fourth N-type gate connection electrode is connected to the N-type gate electrode of the N-type transistor through a fourth N-type gate via, and the fourth P-type gate via and the fourth N-type gate via are arranged in the gap area; in the second direction Y, relative to the first gate via, the fourth P-type gate via is closer to the P-type active area of ​​the P-type transistor, and the fourth N-type gate via is closer to the N-type active area of ​​the N-type transistor.

34. The gate driving circuit according to claim 2, wherein: The first transmission gate includes a first P-type transistor and a first N-type transistor, and the second inverter includes an eleventh P-type transistor and an eleventh N-type transistor; the shift register circuit also includes a first connecting electrode, a second connecting electrode, a fifteenth connecting electrode, a first signal transfer line, and a second signal transfer line; the first connecting electrode is connected to the P-type gate electrode of the first P-type transistor, the second connecting electrode is connected to the N-type gate electrode of the first N-type transistor, the fifteenth connecting electrode is connected to the P-type gate electrode of the eleventh P-type transistor and the N-type gate electrode of the eleventh N-type transistor, a first end of the first signal transfer line is connected to the first connecting electrode through a first transfer via, and a second end of the first signal transfer line is connected to the second electrode of the eleventh P-type transistor and the second electrode of the eleventh N-type transistor through a second transfer via; a first end of the second signal transfer line is connected to the second connecting electrode through a third transfer via, and a second end of the second signal transfer line is connected to the fifteenth connecting electrode through a fourth transfer via; There is a first signal transmission length between the geometric center of the first transfer via and the geometric center of the second transfer via, there is a second signal transmission length between the geometric center of the third transfer via and the geometric center of the fourth transfer via, the second signal transmission length is greater than the first signal transmission length, and the first signal transmission length and the second signal transmission length are the dimensions in the first direction.

35. The gate driving circuit according to claim 34, wherein: A difference between the second signal transmission length and the first signal transmission length is greater than or equal to 0.8 μm.

36. The gate driving circuit according to claim 34, wherein: At least one of the first signal patch line and the second signal patch line is disposed in the gap region.

37. The gate driving circuit according to claim 2, wherein: The shift register circuit also includes a third signal switching line, a first end of the third signal switching line is connected to the P-type gate electrode of the third P-type transistor in the first NAND gate, and a second end of the third signal switching line is connected to the P-type gate electrode of the eighth P-type transistor in the second NAND gate; the orthographic projection of the third signal switching line on the silicon substrate at least partially overlaps with the orthographic projection of the P-type gate electrodes in the third inverter, the second transmission gate, and the third transmission gate on the silicon substrate.

38. The gate driving circuit according to claim 2, wherein: The shift register circuit also includes a fourth signal transfer line, a first end of the fourth signal transfer line is connected to the P-type drain electrode of the first P-type transistor in the first transmission gate, and a second end of the fourth signal transfer line is connected to the P-type drain electrode of the fifth P-type transistor in the third inverter; the orthographic projection of the fourth signal transfer line on the silicon substrate at least partially overlaps with the orthographic projection of the P-type gate electrodes in the first NAND gate and the third inverter on the silicon substrate.

39. The gate driving circuit according to claim 2, wherein: The shift register circuit also includes a fifth signal switching line, a first end of the fifth signal switching line is connected to the second transmission gate and the third transmission gate, and a second end of the fifth signal switching line is connected to the fourth inverter; the orthographic projection of the fifth signal switching line on the silicon substrate does not overlap with the orthographic projection of the P-type active area in the third transmission gate and the second NAND gate on the silicon substrate, and the orthographic projection of the fifth signal switching line on the silicon substrate does not overlap with the orthographic projection of the N-type active area in the third transmission gate and the second NAND gate on the silicon substrate.

40. The gate drive circuit according to claims 1 to 39, wherein: The gate drive circuit also includes a logic operation circuit, a level converter and a row drive enhancer arranged on a silicon substrate. The shift register circuit is configured to generate a row-by-row shift timing according to a timing signal, the logic operation circuit is configured to generate a target timing through a logic operation, the level converter is configured to perform voltage domain conversion on the target timing, and the row drive enhancer is configured to enhance the converted signal and output it to the scan signal line of the display area.

41. A display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit comprises the gate driving circuit as described in any one of claims 1 to 40.

42. A display device comprising the display substrate according to claim 41.

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