Display panel and display apparatus

Abstract

A display panel. The display panel comprises a barrier (20). A plurality of blocking units (21) are arranged in a first sub-non-display region (2001) and / or a second sub-non-display region (2002) on two sides of the barrier (20). The plurality of blocking units (21) are located between the barrier (20) and a base substrate (11), the plurality of blocking units (21) are arranged at intervals around the periphery of a display region (100), and a first separation groove (22) is formed between every two adjacent blocking units (21). Before moisture passes over the barrier (20) and / or after moisture has passed over the barrier (20), surfaces of the plurality of first separation grooves (22) formed between the plurality of blocking units (21) can extend an ingress path of the moisture. The reduction in the number of barriers (20) can reduce the width of a non-display region (200), thereby enabling the display panel to have a smaller bezel while ensuring the moisture blocking effect of the display panel. The present disclosure further provides a display apparatus comprising the display panel.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous upgrading of display devices, users have put forward extremely narrow demands for the borders of display devices, and the narrow borders have also put forward higher requirements for design.

[0003] In order to prevent water vapor from entering the display panel, multiple cofferdams are usually set in the non-display area of ​​the display panel. The more cofferdams there are, the wider the border of the display panel. However, reducing the number of cofferdams will weaken the water vapor blocking ability, making the display panel less reliable.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0005] Public content

[0006] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a display panel and a display device.

[0007] According to one aspect of the present disclosure, a display panel is provided, which has a display area and a non-display area located outside the display area. The display panel also includes a base substrate, a dam and a driving circuit layer. The dam is provided on one side of the base substrate and is located in the non-display area. The first sub-non-display area is between the dam and the edge of the display panel, and the second sub-non-display area is between the dam and the display area. The driving circuit layer is provided between the dam and the base substrate, and a plurality of first partition grooves are provided at intervals on the driving circuit layer. A blocking unit is formed between two adjacent first partition grooves. The plurality of blocking units are located in the first sub-non-display area and / or the second sub-non-display area. The plurality of blocking units are arranged at intervals around the display area.

[0008] In one embodiment of the present disclosure, the multiple blocking units include a plurality of first blocking units, the multiple first blocking units are arranged in the first sub-non-display area, the multiple first blocking units include at least two first sub-blocking units and at least two second sub-blocking units, the second sub-blocking units are located on a side of the first sub-blocking unit away from the cofferdam, and the distance between the second sub-blocking units is greater than the distance between the first sub-blocking units.

[0009] In one embodiment of the present disclosure, the blocking unit also includes a plurality of second blocking units, and the plurality of second blocking units are arranged in the second sub-non-display area, the non-display area includes a first area and a second area, the first area is used to set the wiring, and the second area is used to bind the wiring, the first area and the second area are both provided with a first blocking unit, and the number of the second blocking units located in the first area is greater than or equal to the number of the first blocking units.

[0010] In one embodiment of the present disclosure, the blocking unit also includes a plurality of second blocking units, and the plurality of second blocking units are arranged in the second sub-non-display area. The non-display area includes a first area and a second area. The second area is provided with a first blocking unit, and the first area is provided with a first blocking unit and a second blocking unit.

[0011] In one embodiment of the present disclosure, the driving circuit layer includes a first source-drain metal layer, a first protective layer, a first planarization layer, a second source-drain metal layer and a second planarization layer, the first source-drain metal layer is arranged on one side of the base substrate, the first protective layer is arranged on the side of the first source-drain metal layer away from the base substrate, and the first protective layer is an inorganic material; the first planarization layer is arranged on the side of the first protective layer away from the base substrate; the first source-drain metal layer is arranged on the side of the first planarization layer away from the base substrate; the second planarization layer is arranged on the side of the first source-drain metal layer away from the base substrate; the first blocking unit is arranged on the side of the first protective layer away from the base substrate, and the second blocking unit is arranged on the side of the first protective layer away from the base substrate or the side of the first planarization layer away from the base substrate.

[0012] In one embodiment of the present disclosure, the blocking unit further includes a mask layer, which is disposed on a side of the blocking unit away from the base substrate. The mask layer is provided with a mask opening, and a mask unit is formed between two adjacent mask openings. The orthographic projection of the mask unit on the base substrate overlaps with the orthographic projection of the blocking unit on the base substrate.

[0013] In one embodiment of the present disclosure, when the second blocking unit is provided on a side of the first protection layer away from the base substrate, the mask layer and the second source / drain metal layer are provided in the same layer and with the same material.

[0014] In one embodiment of the present disclosure, the display panel also includes a pixel electrode layer, which is arranged on the side of the second planarization layer away from the base substrate. When the second blocking unit is arranged on the side of the first planarization layer away from the base substrate, the mask layer and the pixel electrode layer are arranged in the same layer and material.

[0015] In one embodiment of the present disclosure, the display panel further includes a second protective layer, which is disposed between the second planarization layer and the pixel electrode layer, and the mask layer and the second protective layer are disposed in the same layer and with the same material.

[0016] In one embodiment of the present disclosure, second partition grooves are respectively provided at positions adjacent to the second sub-non-display area, the display area, and the cofferdam, and the second partition grooves penetrate the first planarization layer and the second planarization layer.

[0017] In one embodiment of the present disclosure, the display panel further includes a blocking portion, which is provided in the same layer and material as the mask layer. The blocking portion is provided in the second partition groove and extends to a side of the second planarization layer away from the base substrate.

[0018] In one embodiment of the present disclosure, the first partition groove includes a first groove segment and a second groove segment that are sequentially away from the substrate base plate, the orthographic projection of the second groove segment on the substrate base plate is located within the orthographic projection of the first groove segment on the substrate base plate, and the area of ​​the orthographic projection of the second groove segment on the substrate base plate is smaller than the area of ​​the orthographic projection of the first groove segment on the substrate base plate.

[0019] In one embodiment of the present disclosure, the width of the first slot segment gradually increases along a side away from the substrate.

[0020] In one embodiment of the present disclosure, the width of the second slot segment gradually decreases in a direction away from the substrate.

[0021] In one embodiment of the present disclosure, the bottom surface of the first groove segment includes a first bottom surface and a second bottom surface located at both ends of the first bottom surface, the second bottom surface is connected to the side surface of the first groove segment, and the second bottom surface is inclined toward the side close to the substrate.

[0022] In one embodiment of the present disclosure, the first slot segment is configured as an inwardly concave arc surface, and the width of the first slot segment gradually increases and then gradually decreases in a direction away from the substrate.

[0023] In one embodiment of the present disclosure, the side surfaces of the first groove segment include a first side surface and a second side surface sequentially arranged in a direction away from the substrate, the first side surface is connected to the second bottom surface, and the width between the first side surfaces gradually decreases in a direction away from the substrate.

[0024] In one embodiment of the present disclosure, the second side surfaces are concave arc surfaces, and the distance between the second side surfaces first gradually increases and then gradually decreases in a direction away from the base substrate.

[0025] In one embodiment of the present disclosure, the display panel further includes a common electrode layer and an encapsulation layer. The common electrode layer is disposed on a side of the mask layer away from the base substrate, and the encapsulation layer is disposed on a side of the common electrode layer away from the base substrate.

[0026] According to another aspect of the present disclosure, a display device is provided, including the display panel provided in one aspect of the present disclosure.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0029] FIG1 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure, when a first barrier unit and a second barrier unit are both provided in the same layer and with the same material as a first planarization layer.

[0030] 2 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when the first barrier unit and the second barrier unit are both provided in the same layer and made of the same material as the second planarization layer, and the mask layer and the pixel electrode are provided in the same layer and made of the same material.

[0031] 3 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure when the first barrier unit and the second barrier unit are both provided in the same layer and made of the same material as the second planarization layer, and the mask layer and the second protective layer are provided in the same layer and made of the same material.

[0032] FIG4 is a partial schematic diagram of a portion of a display panel A when the width of the first groove segment gradually increases along a side away from the base substrate in an embodiment of the present disclosure.

[0033] FIG5 is a partial schematic diagram of a portion of a display panel B when the width of the first groove segment gradually increases along a side away from the base substrate in an embodiment of the present disclosure.

[0034] FIG6 is a partial schematic diagram of a portion A of the display panel when the width of the first groove segment gradually increases along the side away from the base substrate and the width of the second groove segment gradually decreases along the direction away from the base substrate in an embodiment of the present disclosure.

[0035] FIG7 is a partial schematic diagram of a portion A of the display panel when the width of the first groove segment gradually increases and then gradually decreases in a direction away from the base substrate in an embodiment of the present disclosure.

[0036] FIG8 is a partial schematic diagram of a portion of the display panel A when the second bottom surface is tilted toward the side close to the base substrate in the embodiment of the present disclosure.

[0037] FIG9 is a partial schematic diagram of a portion of a display panel A when the first bottom surface is a curved surface recessed toward the base substrate.

[0038] FIG10 is a partial schematic diagram of a portion of the display panel A when the second bottom surface is tilted toward the side close to the base substrate and the distance between the second side surfaces gradually increases and then decreases in a direction away from the base substrate in the embodiment of the present disclosure.

[0039] Figure 11 is a planar schematic diagram of the display panel involved in the embodiment of the present disclosure when the first blocking units and the second blocking units are provided on the upper frame, the lower frame, the left frame and the right frame, and the number of the first blocking units is greater than the number of the second blocking units.

[0040] 12 is a planar schematic diagram of the display panel according to an embodiment of the present disclosure, in which first and second blocking units are provided on the upper frame, the lower frame, the left frame, and the right frame, and the number of the first blocking units is equal to the number of the second blocking units.

[0041] FIG13 is a schematic plan view of a display panel according to an embodiment of the present disclosure when only the number of first barrier units in the second region of the lower frame is reduced.

[0042] FIG14 is a schematic plan view of the display panel according to an embodiment of the present disclosure when only the second blocking unit is provided on the lower frame.

[0043] Figure 15 is another planar schematic diagram of the display panel involved in the embodiment of the present disclosure when the first blocking units and the second blocking units are set on the upper frame, the lower frame, the left frame and the right frame, and the number of the first blocking units is greater than the number of the second blocking units.

[0044] FIG16 is a partial enlarged view of portion C in FIG15 .

[0045] FIG17 is a plan view of symmetrical and / or asymmetrical remaining first barrier units remaining after the display panel is cut in an embodiment of the present disclosure.

[0046] FIG18 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0048] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0049] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0050] After a long period of reliable high temperature and high humidity process, water vapor can easily invade from the edge of the display panel to the inside of the display panel. As the water vapor continues to diffuse, peeling occurs between the insulating layer group and the first planarization layer, resulting in poor display. In order to prevent water vapor from entering the interior of the display panel, multiple cofferdams are usually set in the non-display area of ​​the display panel. The more cofferdams there are, the better the water vapor blocking effect. With the continuous upgrading of display devices, users have put forward extremely narrow demands on the borders of display devices, and the narrowing of the borders also puts higher demands on the design. Therefore, it is necessary to reduce the number of cofferdams to reduce the border of the display panel, but this will weaken the water vapor blocking ability, making the display panel less reliable.

[0051] Based on this, embodiments of the present disclosure provide a display panel. As shown in Figures 1 to 16, the display panel comprises a display area 100 and a non-display area 200 located outside the display area 100. The display panel further comprises a base substrate 11, a dam 20, and a driving circuit layer 13. The dam 20 is provided on one side of the base substrate 11 and located in the non-display area 200. A first sub-non-display area 2001 is defined between the dam 20 and the edge of the display panel, and a second sub-non-display area 2002 is defined between the dam 20 and the display area 100. The driving circuit layer 13 is provided between the dam 20 and the base substrate 11. A plurality of first partitioning grooves 22 are provided in the driving circuit layer 13, with blocking units 21 formed between adjacent first partitioning grooves 22. The plurality of blocking units 21 are located in the first sub-non-display area 2001 and / or the second sub-non-display area 2002, and the plurality of blocking units 21 are spaced around the display area 100.

[0052] The first sub-non-display area 2001 and / or the second sub-non-display area 2002 on either side of the cofferdam 20 are provided with a plurality of blocking units 21. The plurality of blocking units 21 are located between the cofferdam 20 and the base substrate 11. The plurality of blocking units 21 are spaced apart around the display area 100, and a first partition groove 22 is formed between two adjacent blocking units 21. Before and / or after water vapor passes through the cofferdam 20, the surface of the plurality of first partition grooves 22 formed between the plurality of blocking units 21 can extend the entry path of water vapor. Since the first sub-non-display area 2001 and the second sub-non-display area 2002 on either side of the cofferdam 20 are typically used for peripheral wiring and are indispensable, and reducing the number of cofferdams 20 can reduce the width of the non-display area 200, the display panel can reduce the bezel of the display panel while maintaining the water vapor blocking effect.

[0053] The plurality of barrier units 21 may be disposed only in the first sub-non-display area 2001, or may be disposed in both the first sub-non-display area 2001 and the second sub-non-display area 2002. When the plurality of barrier units 21 are disposed only in the first sub-non-display area 2001, the plurality of first partition grooves 22 may extend the entry path of water vapor before it passes through the cofferdam 20, thereby reducing the amount of water vapor entering the surface of the cofferdam 20 and ensuring a water vapor blocking effect.

[0054] The plurality of barrier units 21 may also be provided only in the second sub-non-display area 2002 at intervals. When the plurality of barrier units 21 are provided only in the second sub-non-display area 2002, water vapor first passes through the surface of the cofferdam 20, is blocked by the cofferdam 20, and then enters the plurality of first partition grooves 22. After the cofferdam 20 extends the entry path to initially reduce the amount of water vapor, the entry path of the remaining water vapor is further extended, thereby also ensuring the water vapor blocking effect.

[0055] In order to better block water vapor, multiple blocking units 21 can be set simultaneously in the first sub-non-display area 2001 and the second sub-non-display area 2002. When multiple blocking units 21 are set simultaneously in the first sub-non-display area 2001 and the second sub-non-display area 2002, the surfaces of the multiple first partition grooves 22 can extend the entry path of water vapor before and after the water vapor passes through the cofferdam 20, thereby enhancing the blocking effect on water vapor.

[0056] The display panel involved in the embodiments of the present disclosure will be described in detail below with reference to specific examples.

[0057] As shown in FIG2 , a display panel generally includes a base substrate 11, a drive circuit layer 13, a planarization layer group 14, and a light-emitting layer 16. The drive circuit layer 13 is disposed on one side of the base substrate 11, the planarization layer group 14 is disposed on a side of the drive circuit layer 13 away from the base substrate 11, and the light-emitting layer 16 is disposed on a side of the planarization layer group 14 away from the base substrate 11. Furthermore, the display panel may further include a buffer layer 12 disposed between the base substrate 11 and the drive circuit layer 13.

[0058] The base substrate 11 may be an inorganic material or an organic material. For example, in one embodiment of the present disclosure, the base substrate 11 may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass, or may be made of a metal material such as stainless steel, aluminum, or nickel.

[0059] In another embodiment of the present disclosure, the substrate 11 may be a flexible substrate 11. For example, the substrate 11 may be made of polyimide (PI). The substrate 11 may also be a composite of multiple layers. For example, in one embodiment of the present disclosure, the substrate 11 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0060] In the display area 100, the driving circuit layer 13 is provided with a driving circuit for driving the light-emitting unit. The driving circuit is located in the display area 100. Any driving circuit may include a transistor, which may be a thin film transistor. The thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor. Taking a top-gate thin film transistor as an example, the driving circuit layer may include an active layer 131, a first gate electrode 1331, a second gate electrode 1332, a first gate insulating layer 1321, a second gate insulating layer 1322, an interlayer dielectric layer 134, a first source and drain metal layer, a second source and drain metal layer, a first planarization layer 141, and a second planarization layer 142, wherein:

[0061] Active layer 131 is provided on one side of base substrate 11. The material of active layer 131 can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, or other types of semiconductor materials. Therefore, the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor. Active layer 131 can include a channel region and two doped regions of different doping types located on either side of the channel region.

[0062] The first gate insulating layer 1321 is disposed on a side of the active layer 131 away from the substrate 11. The first gate insulating layer 1321 may cover the active layer 131 and the substrate 11. The first gate electrode 1331 is disposed on a side of the first gate insulating layer 1321 away from the substrate 11 and directly faces the active layer 131. That is, the projection of the first gate electrode 1331 on the substrate 11 is located within the projection of the active layer 131 on the substrate 11. For example, the projection of the first gate electrode 1331 on the substrate 11 coincides with the projection of the channel region of the active layer 131 on the substrate 11. The second gate insulating layer 1322 is disposed on a side of the first gate electrode 1331 away from the substrate 11. The second gate insulating layer 1322 may cover the first gate electrode 1331 and the first gate insulating layer 1321. The second gate electrode 1332 is disposed on a side of the second gate insulating layer 1322 away from the substrate 11 and directly faces the active layer 131. The first gate insulating layer 1321 and the second gate insulating layer 1322 are both made of insulating materials such as silicon oxide.

[0063] An interlayer dielectric layer 134 is disposed on a side of the second gate 1332 away from the base substrate 11. The interlayer dielectric layer 134 may cover the second gate 1332 and the second gate insulation layer 1322. The interlayer dielectric layer 134 is composed of an insulating material. A first source-drain metal layer is disposed on a surface of the interlayer dielectric layer 134 away from the base substrate 11. The first source-drain metal layer includes a first source electrode 135 and a drain electrode 136. The first source electrode 135 and the drain electrode 136 are connected to the active layer 131. For example, the first source electrode 135 and the drain electrode 136 are respectively connected to the two corresponding doped regions of the active layer 131 through vias, forming a top-gate thin film transistor.

[0064] A first planarization layer 141 is provided on the side of the first source / drain metal layer away from the base substrate 11, and the surface of the first planarization layer 141 away from the base substrate 11 is flat. The second source / drain metal layer may include a second source electrode 138, which is connected to the first source electrode 135. A second planarization layer 142 is provided on the side of the second source electrode 138 away from the base substrate 11, and the second planarization layer 142 covers the second source electrode 138 and the first planarization layer 141. A first protective layer 137 may also be provided on the side of the first source electrode 135 away from the base substrate 11, and the first protective layer 137 covers the first source electrode 135 and the drain electrode 136. The first planarization layer 141 covers the first protective layer 137. It should be noted that the first source electrode 135 and the drain electrode 136 are located in the first source / drain metal layer of the driving circuit layer 13, and the second source electrode 138 is located in the second source / drain metal layer of the driving circuit layer 13.

[0065] The display panel also includes a pixel definition layer and a light-emitting layer. The light-emitting layer may include a pixel electrode layer, a light-emitting element layer, and a common electrode layer. The pixel definition layer 15 is disposed on the side of the first planarization layer 141 or the second planarization layer 142 away from the array substrate. The pixel definition layer 15 has a plurality of pixel openings 151. The light-emitting layer 16 may include a plurality of light-emitting units, each disposed within a different pixel opening 151. Each light-emitting unit may include a pixel electrode 161, a light-emitting element 162, and a common electrode 163. The pixel electrode layer includes a plurality of pixel electrodes 161, which are located on a surface of the first planarization layer 141 or the second planarization layer 142 away from the base substrate 11. The light-emitting element layer includes a plurality of light-emitting elements 162, which are disposed on a surface of the pixel electrodes 161 away from the base substrate 11. The common electrode layer includes a common electrode 163, which is disposed on a surface of the light-emitting elements 162 away from the base substrate 11. The pixel electrodes 161 and the common electrode 163 can be used to drive the light-emitting elements 162 to emit light, thereby displaying an image.

[0066] The pixel electrode 161 is connected to the first source electrode 135 or the second source electrode 138. A pixel defining layer 15 is provided on the side of the pixel electrode 161 away from the base substrate 11. When the thin film transistor includes only the first source electrode 135, the pixel electrode 161 is connected to the first source electrode 135, and the pixel defining layer 15 covers the pixel electrode 161 and the first planarization layer 141. When the thin film transistor also includes the second source electrode 138, the pixel electrode 161 is connected to the second source electrode 138, and the pixel defining layer 15 covers the pixel electrode 161 and the second planarization layer 142. It should be noted that the source and drain of the thin film transistor are opposite to each other, so it can also be considered that the pixel electrode 161 is connected to the first drain or the second drain.

[0067] The common electrode 163 can serve as a cathode, and the pixel electrode 161 can serve as an anode. The light-emitting element 162 can be driven to emit light by applying a signal to the pixel electrode 161. The specific light-emitting principle will not be described in detail here. The light-emitting element 162 may include an electro-induced organic light-emitting material and may be formed by a process such as evaporation. For example, the light-emitting element 162 may include a hole injection layer, a hole transport layer, a light generating layer, an electron transport layer, and an electron injection layer sequentially stacked on the pixel electrode 161 layer. It should be noted that the light-emitting element 162 may include a red light-emitting element 162, a green light-emitting element 162, and a blue light-emitting element 162, depending on the color of the light emitted.

[0068] In order to facilitate the evaporation of the light-emitting element 162 , a support column 26 may be further provided on the side of the pixel defining layer 15 away from the base substrate 11 , and the support column 26 is used to support the evaporation mask corresponding to the light-emitting element 162 .

[0069] In addition, the display panel of the present disclosure may further include an encapsulation layer 17. Encapsulation layer 17 is disposed on the side of light-emitting layer 16 away from substrate 11, thereby encapsulating light-emitting layer 16 and preventing corrosion by water and oxygen. Encapsulation layer 17 may have a single-layer or multi-layer structure, and the material of encapsulation layer 17 may include organic or inorganic materials, without particular limitation herein.

[0070] In this embodiment, the encapsulation layer 17 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172, and a second inorganic encapsulation layer 173. The first inorganic encapsulation layer 171 is provided on a side of the light-emitting layer 16 away from the base substrate 11, the organic encapsulation layer 172 is provided on a side of the first inorganic encapsulation layer 171 away from the base substrate 11, and the second inorganic encapsulation layer 173 is provided on a side of the organic encapsulation layer 172 away from the base substrate 11. The inorganic encapsulation layer 17 and the second inorganic encapsulation layer 173 may be formed by vapor deposition, and the organic encapsulation layer 172 may be formed by inkjet printing and leveling.

[0071] Because the liquid organic encapsulating material flows, it is prone to overflow. To prevent this, a dam 20 has been installed in the non-display area 200, away from the display area 100, to prevent it from overflowing. The cross-sectional shape of the dam 20 can be rectangular as shown in the figure, or it can be trapezoidal. The dam 20 has at least one inclined side near the display area 100, which is not limited here.

[0072] In addition, the cofferdam 20 can also prevent water and oxygen from entering the interior of the display panel from the edge of the display panel. To achieve the effect of a narrow bezel, the present disclosure only provides one cofferdam 20. This can easily weaken the water vapor barrier capability of the display panel, making the display panel less reliable. It should be noted that the cofferdam 20 includes a first insulating layer 201 and a second insulating layer 202. The first insulating layer 201 is provided in the same layer and material as the pixel defining layer 15, and the second insulating layer 202 is provided in the same layer and material as the support pillars 26.

[0073] As shown in FIG1 , the area between the dam 20 and the edge of the display panel is defined as a first sub-non-display area 2001, and the area between the dam 20 and the display area 100 is defined as a second sub-non-display area 2002. A plurality of barrier units 21 are provided in the first sub-non-display area 2001, spaced apart around the display area 100. The plurality of barrier units 21 include a plurality of first barrier units 211, which are provided in the first sub-non-display area 2001. The plurality of barrier units 21 may also include a plurality of second barrier units 212, which are provided in the second sub-non-display area 2002.

[0074] As shown in FIG1 , the first and second barrier units 211 and 212 are provided in the same layer and made of the same material as the first planarization layer 141. The second planarization layer 142 does not cover the first and second sub-non-display areas 2001 and 2002, so the first planarization layer 141 is exposed in the first and second sub-non-display areas 2001 and 2002. The first and second barrier units 211 and 212 are provided on a side of the first protective layer 137 away from the base substrate 11, and the first protective layer 137 is exposed.

[0075] As shown in FIG2 , the first barrier unit 211 and the second barrier unit 212 are provided in the same layer and made of the same material as the second planarization layer 142. The first planarization layer 141 is not provided in the first sub-non-display area 2001, and the second planarization layer 142 directly covers the first protective layer 137. The first barrier unit 211 is provided on the side of the first protective layer 137 away from the base substrate 11, and is exposed from the first protective layer 137. The second barrier unit 212 is provided on the side of the first planarization layer 141 away from the base substrate 11, and is exposed from the first planarization layer 141.

[0076] In the first sub-non-display area 2001, a first inorganic encapsulation layer 171 is provided across the entire surface. The side of the first inorganic encapsulation layer 171, corresponding to the first blocking unit 211, facing away from the base substrate 11 is an organic encapsulation layer 172. This organic encapsulation layer 172 is formed by inkjet printing and leveling. It is blocked by the dam 20 on the side closest to the display area. A second inorganic encapsulation layer is provided on the side of the organic encapsulation layer 172 facing away from the base substrate 11. Furthermore, the side of the second inorganic encapsulation layer 173, corresponding to the first blocking unit 211, facing away from the base substrate 11 is coated with encapsulation adhesive 18.

[0077] As shown in Figures 2 and 3, because the material of the first planarization layer 141 and the second planarization layer 142 is usually an organic material, and the material of the first gate insulation layer 1321, the second gate insulation layer 1322, the interlayer dielectric layer and the first protective layer 137 included in the insulation layer group is usually an inorganic material, organic materials are more likely to absorb water than inorganic materials. The water vapor absorbed by the first planarization layer 141 will remain inside the display panel and enter the display area 100 of the display panel when heated, affecting the display effect.

[0078] Therefore, when multiple second blocking units 212 are arranged on the side of the first planarization layer 141 away from the base substrate 11, while ensuring the wiring width, the width of the first sub-non-display area 2001 is usually set to be larger, and the width of the second sub-non-display area 2002 is set to be smaller, so that more first blocking units 211 are set in the first sub-non-display area 2001. Usually, the number of first blocking units 211 is greater than or equal to the number of second blocking units 212, so that water vapor is blocked as much as possible in the first sub-non-display area 2001 outside the cofferdam 20, so as to avoid water vapor from entering the second sub-non-display area 2002 from the cofferdam 20 or reduce the amount of water vapor entering the second sub-non-display area 2002 from the cofferdam 20 as much as possible, so as to enhance the water vapor blocking effect.

[0079] As shown in Figures 1 to 3, the non-display area 200 is further provided with a mask layer 23. The mask layer 23 is disposed on the side of the barrier unit 21 away from the base substrate 11. The mask layer 23 is provided with mask openings 232. A mask unit 231 is formed between two adjacent mask openings 232. The orthographic projection of the mask unit 231 on the base substrate 11 overlaps with the orthographic projection of the barrier unit 21 on the base substrate 11. When forming the barrier unit 21, the mask layer 23 within the display panel can be used to directly pattern the first planarization layer 141 or the second planarization layer 142.

[0080] As shown in FIG3 , the display panel may further include a second protective layer 19, which is disposed between the second planarization layer 142 and the pixel electrode 161. A mask layer 23 is formed from the same material as the second protective layer 19, and the mask layer 23 can pattern the second planarization layer 142. However, forming the second protective layer 19 requires an additional masking process, and then patterning the second planarization layer 142 using the mask layer 23, which is equivalent to performing two masking processes.

[0081] To save process costs, it is considered to pattern the first planarization layer 141 or the second planarization layer 142 using the existing film layers of the display panel. As shown in Figure 2, when the first barrier unit 211 and the second barrier unit 212 are located on the side of the insulating layer group away from the base substrate 11, the mask layer 23 is provided in the same layer and material as the second source / drain metal layer. This mask layer 23 can be used to pattern the first planarization layer 141. To facilitate the arrangement of different thin-film transistors in the pixel circuit, the driver circuit layer 13 may also include a third source / drain metal layer. When the driver circuit layer 13 also includes a third source / drain metal layer, the mask layer 23 can also be provided in the same layer and material as the third source / drain metal layer.

[0082] As shown in FIG3 , when the first barrier unit 211 is disposed on the side of the insulating layer group away from the base substrate 11, and the second barrier unit 212 is disposed on the side of the first planarization layer 141 away from the base substrate 11, the mask layer 23 is formed of the same layer and material as the pixel electrode 161, and the mask layer 23 can pattern the second planarization layer 142. Obviously, in both of the above-mentioned cases, only one masking process is required to pattern the first planarization layer 141 or the second planarization layer 142, resulting in lower costs.

[0083] A first partitioning groove 22 is formed between two adjacent blocking units 21. As shown in FIG4 , the first partitioning groove 22 formed by the two first blocking units 211 is located on the side of the first protective layer 137 away from the base substrate 11. As shown in FIG5 , the first partitioning groove 22 formed by the two second blocking units 212 is located on the side of the first planarization layer 141 away from the base substrate 11.

[0084] As shown in Figures 4 to 9, the first partitioning groove 22 includes a first groove segment 221 and a second groove segment 222, which are sequentially spaced away from the base substrate 11. The orthographic projection of the second groove segment 222 on the base substrate 11 is located within the orthographic projection of the first groove segment 221 on the base substrate 11. The orthographic projection area of ​​the second groove segment 222 on the base substrate 11 is smaller than the orthographic projection area of ​​the first groove segment 221 on the base substrate 11. Therefore, the width d2 of the second groove segment 222 is smaller than the width d1 of the first groove segment 221. The distance between two adjacent blocking units, that is, the width of the partitioning groove (the width d2 of the second groove segment 222), is typically between 5 and 15 microns, and the sum s of the width of the partitioning groove and the distance between the blocking units 21 is typically between 10 and 30 microns.

[0085] As shown in Figures 4 and 5, the width of the first slot segment 221 gradually increases along the side away from the base substrate 11, so that the difference in width between the second slot segment 222 and the first slot segment 221 at the end away from the base substrate 11 is larger. This increases the surface area of ​​the first partition slot 22 and prolongs the path for water vapor to enter the display area 100. As shown in Figure 6, the second slot segment 222 can also adopt a structure similar to that of the first slot segment 221, that is, the width of the second slot segment 222 gradually decreases along the direction away from the base substrate 11, and the increase in the width of the second slot segment 222 gradually decreases along the direction away from the base substrate 11, further extending the water vapor blocking path.

[0086] As shown in FIG7 , the width of the first groove section 221 can be configured to gradually increase and then gradually decrease in a direction away from the base substrate 11. This can form a curved surface in the first groove section 221. Obviously, a curved surface has a larger surface area than a straight surface, thereby further extending the path for blocking water vapor. The side surface 2214 of the first groove section 221 is configured as a concave curved surface. The side surface 2214 of the first groove section 221 can form a water vapor holding space with the bottom surface 2211 of the first groove section 221 and the side of the second groove section 222 closer to the base substrate 11, retaining some water vapor in this holding space and reducing the amount of water vapor flowing toward the display area 100.

[0087] As shown in FIG8 , the bottom surface 2211 of the first groove segment 221 includes a first bottom surface 2212 and second bottom surfaces 2213 located at both ends of the first bottom surface 2212. The second bottom surface 2213 is connected to the side surface 2214 of the first groove segment 221. The second bottom surface 2213 is inclined toward the side closer to the base substrate 11, which effectively increases the area of ​​the bottom surface 2211 of the first groove segment 221, thereby extending the water vapor entry path and increasing the volume of the retention space, further reducing the water vapor flowing toward the display area 100. As shown in FIG9 , the first bottom surface 2212 can also be an arcuate surface that is concave toward the base substrate 11, which further enhances the effect of the first partition groove 22 on extending the water vapor path.

[0088] As shown in FIG10 , the side surfaces 2214 of the first slot segment 221 include a first side surface 2215 and a second side surface 2216, which are sequentially arranged in a direction away from the base substrate 11. The first side surface 2215 is connected to the second bottom surface 2213. The width between the first side surfaces 2215 gradually decreases in the direction away from the base substrate 11. The second side surfaces 2216 are concave arc surfaces, and the distance between the second side surfaces 2216 gradually increases and then gradually decreases in the direction away from the base substrate 11. This increases the area of ​​the side surfaces 2214 of the first slot segment 221, further extending the path for water vapor to enter. Furthermore, a gap is formed between the first side surface 2215 and the second bottom surface 2213 relative to the front accommodation space. This gap has a stronger locking effect on water vapor than the front accommodation space, further reducing the amount of water vapor flowing toward the display area 100.

[0089] As shown in Figures 1 to 3, second partitioning grooves 24 are provided in the second sub-non-display area 2002 adjacent to the display area 100 and the cofferdam 20. These second partitioning grooves 24 penetrate the first planarization layer 141 and the second planarization layer 142. They are deeper than the first partitioning grooves 22, thus extending the entry path for water vapor. The second partitioning grooves 24 adjacent to the cofferdam 20 can block any remaining water vapor after the cofferdam 20 blocks it. The second partitioning grooves 24 adjacent to the display area 100 can block any remaining water vapor after the second barrier units 212 block it, forming the final barrier before the display area 100. It should be noted that the second partitioning grooves 24 are located outside the plurality of second barrier units 212, leaving slotted areas between the plurality of second barrier units 212 and the display area 100, and between the plurality of second barrier units 212 and the cofferdam 20.

[0090] The non-display area 200 includes a first area 2003 and a second area 2007. The first area 2003 is used to set up wiring, and the second area 2007 is typically located at the bottom frame of the display panel. The second area 2007 is used to bind the wiring. As shown in Figures 10 to 15, the first area 2003 typically includes a first sub-area 2004 located at the top frame of the display panel, a second sub-area 2005 located at the left frame, and a third sub-area 2006 located at the right frame. First blocking units 211 and second blocking units 212 can be provided on the top, bottom, left, and right frames. As shown in Figure 11, the number of first blocking units 211 mentioned above is typically greater than the number of second blocking units 212.

[0091] As shown in FIG12 , because the second region 2007 of the lower frame is used to bind the wiring, the lower frame of the display panel is typically compressed. To ensure the consistency of the widths of the upper frame, the lower frame, the left frame, and the right frame as much as possible, the number of first blocking units 211 in the lower frame can be reduced. For example, the number of second blocking units 212 in the first region 2003 can be equal to the number of first blocking units 211. As shown in FIG13 , the number of first blocking units 211 in only the second region 2007 of the lower frame can also be reduced, so that the number of first blocking units 211 in the second region 2007 of the lower frame is less than the number of first blocking units 211 in the first sub-region 2004 of the upper frame, the second sub-region 2005 of the left frame, and the third sub-region 2006 of the right frame.

[0092] Because the first sub-non-display area 2001 has a better barrier effect, the first barrier unit 211 can also be set in the top, bottom, left, and right frames, or only in a portion of the top, bottom, left, and right frames. As shown in Figure 14, because the second area 2007 generally requires the installation of external structures such as binding pins, the second barrier unit 212 can be set only in the bottom frame to further enhance the moisture barrier effect of the bottom frame. Since there is sufficient space in the top, left, and right frames, the first barrier unit 211 and the second barrier unit 212 can be set in the top, left, and right frames at the same time.

[0093] During the formation of the display panel, multiple groups of stacked driving circuit layers 13, planarization layer groups 14 and light-emitting layers 16 are usually formed simultaneously on a larger whole substrate to form multiple array-distributed display panels. The multiple display panels are then cut. Cutting stress is generated during the cutting process, which may damage the display panel and cause separation between the layers of the display panel. Therefore, the distance between the first blocking units 211 near the edge of the display panel can be increased.

[0094] As shown in Figures 15 and 16, the plurality of barrier elements 21 include a plurality of first barrier elements 211. The plurality of first barrier elements 211 are disposed in the first sub-non-display area 2001. The plurality of first barrier elements 211 include at least two first sub-barrier elements 2111 and at least two second sub-barrier elements 2112. The second sub-barrier elements 2112 are located on a side of the first sub-barrier elements 2111 away from the cofferdam 20. The width of the second sub-barrier elements 2112 is greater than the width of the first sub-barrier elements 2111, and the distance between the second sub-barrier elements 2112 is greater than the distance between the first sub-barrier elements 2111. The first partition grooves 22 formed between the second sub-barrier elements 2112 can buffer the cutting stress generated during the cutting process. As shown in Figure 17, after the cutting is completed, the display panel may have symmetrical and / or asymmetrical first barrier elements 211 remaining from the cutting (due to process fluctuations).

[0095] The present disclosure also provides a method for manufacturing a display panel as provided in any of the above embodiments. As shown in Figures 1 to 18, the method includes:

[0096] Step S10: providing a base substrate 11.

[0097] In step S20 , a driving circuit layer 13 is formed on one side of the base substrate 11 , and a plurality of blocking units 21 are formed in the first sub-non-display area 2001 and the second sub-non-display area 2002 of the driving circuit layer 13 . The plurality of blocking units 21 are arranged at intervals around the display area 100 .

[0098] In step S30 , a dam 20 is formed on a side of the driving circuit layer 13 away from the base substrate 11 . The dam 20 is located between the first sub-non-display area 2001 and the second sub-non-display area 2002 .

[0099] The structure and beneficial effects involved in the manufacturing method can be referred to the display panel mentioned above, and will not be described in detail here.

[0100] When the mask layer 23 and the second source / drain metal layer are provided in the same layer and with the same material, a plurality of barrier units 21 are formed in the first sub-non-display area 2001 and the second sub-non-display area 2002 of the driving circuit layer 13, including:

[0101] An insulating layer group is formed on one side of the base substrate 11, and the insulating layer group includes a first protective layer 137;

[0102] forming a first planarization layer 141 on a side of the first protection layer 137 away from the base substrate 11;

[0103] A second source / drain metal layer and a mask layer 23 are formed on a side of the first planarization layer 141 away from the substrate 11 ;

[0104] A second planarization layer 142 is formed on a side of the second source / drain metal layer and the mask layer 23 away from the base substrate 11;

[0105] forming a pixel electrode 161 layer on a side of the second planarization layer 142 away from the base substrate 11 and performing a patterning process on the pixel electrode 161 layer;

[0106] The second planarization layer 142 in the first sub-non-display area 2001 and the second sub-non-display area 2002 is removed to expose the first planarization layer 141 ;

[0107] The first planarization layer 141 of the first sub-non-display area 2001 and the second sub-non-display area 2002 is patterned using the plurality of mask openings of the mask layer 23 to form a plurality of barrier units 21 .

[0108] The mask layer 23 is formed at the same time as the second source / drain metal layer is formed. There is no need to set up a separate mask process for forming the mask layer 23 , which saves the manufacturing cost of the display panel.

[0109] When the mask layer 23 and the pixel electrode 161 are provided in the same layer and the same material, a plurality of barrier units 21 are formed in the first sub-non-display area 2001 and the second sub-non-display area 2002 of the driving circuit layer 13, including:

[0110] An insulating layer group is formed on one side of the base substrate 11, and the insulating layer group includes a first protective layer 137;

[0111] forming a first planarization layer 141 on a side of the first protection layer 137 away from the base substrate 11;

[0112] forming a second source-drain metal layer on a side of the first planarization layer 141 away from the base substrate 11;

[0113] A second planarization layer 142 is formed on a side of the second source / drain metal layer away from the base substrate 11 , and the second planarization layer does not cover the first sub-non-display area 2001 ;

[0114] A pixel electrode 161 layer and a mask layer 23 are formed on a side of the second planarization layer 142 away from the base substrate 11;

[0115] The first planarization layer 141 of the first sub-display area 100 and the second planarization layer 142 of the second sub-display area 100 are patterned simultaneously through the multiple mask openings of the mask layer 23 to form a plurality of barrier units 21 .

[0116] The mask layer 23 is formed at the same time as the pixel electrode 161 is formed. There is no need to set up a separate mask process for forming the mask layer 23 , which saves the manufacturing cost of the display panel.

[0117] The present disclosure also provides a display device. The display device may include any of the display panels described above. The specific structure and beneficial effects of the display panel have been described in detail above and will not be repeated here.

[0118] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0119] The display device can also be an emerging wearable device, such as a virtual reality device and an augmented reality device, or a traditional electronic device, such as a mobile phone, a computer, a television, and a camcorder. These are not listed here one by one.

[0120] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel having a display area and a non-display area located around the display area, wherein, The display panel further includes: a substrate; a dam, disposed on one side of the substrate and located in the non-display area. A first sub-non-display area is formed between the dam and the edge of the display panel, and a second sub-non-display area is formed between the dam and the display area; a driving circuit layer, disposed between the dam and the substrate. The driving circuit layer is provided with a plurality of first partition grooves at intervals, and a plurality of blocking units are formed between two adjacent first partition grooves. The plurality of blocking units are located in the first sub-non-display area and / or the second sub-non-display area, and the plurality of blocking units are arranged at intervals around the periphery of the display area.

2. The display panel according to claim 1, wherein, The plurality of blocking units include a plurality of first blocking units, and the plurality of first blocking units are disposed in the first sub-non-display area. The plurality of first blocking units include at least two first sub-blocking units and at least two second sub-blocking units. The second sub-blocking units are located on the side of the first sub-blocking units away from the dam, and the distance between the second sub-blocking units is greater than the distance between the first sub-blocking units.

3. The display panel according to claim 2, wherein, The blocking unit further includes a plurality of second blocking units, and the plurality of second blocking units are disposed in the second sub-non-display area. The non-display area includes a first area and a second area. The first area is used for arranging traces, and the second area is used for binding the traces. The first area and the second area are both provided with first blocking units, and the number of the second blocking units in the first area is greater than or equal to the number of the first blocking units.

4. The display panel according to claim 1, wherein, The blocking unit further includes a plurality of second blocking units, and the plurality of second blocking units are disposed in the second sub-non-display area. The non-display area includes a first area and a second area. The second area is provided with first blocking units, and the first area is provided with the first blocking units and the second blocking units.

5. The display panel according to claim 3, wherein The driving circuit layer includes: a first source-drain metal layer, disposed on one side of the substrate; a first protective layer, disposed on the side of the first source-drain metal layer away from the substrate, wherein the first protective layer is an inorganic material; a first planarization layer, disposed on the side of the first protective layer away from the substrate; a second source-drain metal layer, disposed on the side of the first planarization layer away from the substrate; a second planarization layer, disposed on the side of the second source-drain metal layer away from the substrate; The first blocking unit is disposed on the side of the first protective layer away from the substrate, and the second blocking unit is disposed on the side of the first protective layer away from the substrate or on the side of the first planarization layer away from the substrate.

6. The display panel according to claim 5, wherein, The blocking unit further includes a mask layer, and the mask layer is disposed on the side of the blocking unit away from the substrate. The mask layer is provided with mask openings, and mask units are formed between two adjacent mask openings. The orthographic projection of the mask units on the substrate overlaps with the orthographic projection of the blocking units on the substrate.

7. The display panel according to claim 6, wherein, When the second blocking unit is disposed on the side of the first protective layer away from the substrate, the mask layer is provided with the same layer and the same material as the second source-drain metal layer.

8. The display panel according to claim 6, wherein, The display panel also includes a pixel electrode layer, which is arranged on a side of the second planarization layer away from the base substrate. When the second blocking unit is arranged on a side of the first planarization layer away from the base substrate, the mask layer and the pixel electrode layer are arranged in the same layer and with the same material.

9. The display panel according to claim 6, wherein, The display panel further includes a second protective layer, which is disposed between the second planarization layer and the pixel electrode layer. The mask layer and the second protective layer are disposed in the same layer and with the same material.

10. The display panel according to any one of claims 6 to 9, wherein, Second partition grooves are respectively disposed at positions of the second non-display sub-area adjacent to the display area and the cofferdam, and the second partition grooves penetrate through the first planarization layer and the second planarization layer.

11. The display panel according to claim 10, wherein, The display panel further includes a blocking portion, which is provided in the same layer and made of the same material as the mask layer. The blocking portion is provided in the second partition groove and extends to a side of the second planarization layer away from the base substrate.

12. The display panel according to claim 1, wherein, The first partition groove includes a first groove segment and a second groove segment which are sequentially away from the substrate, the orthographic projection of the second groove segment on the substrate is located within the orthographic projection of the first groove segment on the substrate, and the area of the orthographic projection of the second groove segment on the substrate is smaller than the area of the orthographic projection of the first groove segment on the substrate.

13. The display panel according to claim 12, wherein, The width of the first groove segment gradually increases along a side away from the substrate base.

14. The display panel according to claim 13, wherein, The width of the second groove segment gradually decreases in a direction away from the substrate.

15. The display panel according to claim 13, wherein, The bottom surface of the first groove segment includes a first bottom surface and second bottom surfaces located at two ends of the first bottom surface, the second bottom surface is connected to the side surface of the first groove segment, and the second bottom surface is inclined toward a side close to the substrate.

16. The display panel according to claim 15, wherein, The first groove section is configured as an inwardly concave arc surface, and the width of the first groove section gradually increases and then gradually decreases in a direction away from the substrate.

17. The display panel according to claim 15, wherein, The side surfaces of the first groove segment include a first side surface and a second side surface sequentially arranged in a direction away from the substrate, the first side surface is connected to the second bottom surface, and the width between the first side surfaces gradually decreases in a direction away from the substrate.

18. The display panel according to claim 17, wherein, The second side surfaces are concave arc surfaces, and the distance between the second side surfaces gradually increases and then gradually decreases in a direction away from the base substrate.

19. The display panel according to claim 6, wherein, The display panel further comprises a common electrode layer and a packaging layer. The common electrode layer is arranged on a side of the mask layer away from the base substrate, and the packaging layer is arranged on a side of the common electrode layer away from the base substrate.

20. A display device, wherein, A display panel comprising any one of claims 1 to 19.

Images