Pixel driving circuit and operating method therefor, display substrate, and display device

Abstract

A pixel driving circuit and an operating method therefor, a display substrate, and a display device. The gate driving circuit comprises multiple stages of shift register circuits (100) and row control circuits (01). The multiple stages of shift register circuits (100) comprise multiple stages of intermediate shift register circuits and (2S+1)-stage first-type offset shift register circuits (P100-1) and (2S+1)-stage second-type offset shift register circuits (P100-2) located on two sides of the multiple stages of intermediate shift register circuits; the row control circuits (01) are configured to receive initial row control signals (Zn, Z_n), and under the control of the initial row control signals (Zn, Z_n), select a stage from the (2S+1)-stage first-type offset shift register circuits (P100-1) as a first-type initial shift register circuit (P100-1), and selects a stage from the (2S+1)-stage second-type offset shift register circuits (P100-2) as a second-type initial shift register circuit; and the first-type initial shift register circuit and the second-type initial shift register circuit have the same offset direction relative to the multiple stages of intermediate shift register circuits, and the number of offset stages relative to the multiple stages of intermediate shift register circuits is N, N being less than or equal to S.

Description

Gate drive circuit and operating method thereof, display substrate, and display device

[0001] This application claims priority to PCT international applications No. PCT / CN2024 / 071143, No. PCT / CN2024 / 071152, and No. PCT / CN2024 / 071147, filed on January 8, 2024, and priority to Chinese patent applications No. 202410129327.2, No. 202410130614.5, and No. 202410130058.1, filed on January 30, 2024. The contents of the above-mentioned PCT international applications and Chinese patent applications should be understood as being incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and specifically to a gate driving circuit and a working method thereof, a display substrate, and a display device. Background Art

[0003] Micro-OLEDs (Micro Organic Light-Emitting Diodes) are a type of microdisplay that has been developed in recent years, with silicon-based OLEDs being one of them. Silicon-based OLEDs are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using wafers as substrates to manufacture OLED devices. By combining the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLEDs not only offer a high pixel density (PPI), but also high brightness, low power consumption, fast response time, a wide color gamut, and excellent thermal stability.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In a first aspect, an embodiment of the present disclosure provides a gate drive circuit, comprising a multi-stage shift register circuit and a row control circuit, wherein the multi-stage shift register circuit is connected in cascade, and the multi-stage shift register circuit includes a multi-stage intermediate shift register circuit and a 4S+2-stage offset shift register circuit;

[0007] In the direction of cascading the multi-stage shift register circuits, the 4S+2-stage offset shift register circuit includes a 2S+1-stage first-type offset shift register circuit located on one side of the multi-stage intermediate shift register circuit, and a 2S+1-stage second-type offset shift register circuit located on the other side of the multi-stage intermediate shift register circuit;

[0008] The row control circuit is configured to receive an initial row control signal, and under the control of the initial row control signal, select one stage from the 2S+1 stages of the first-type offset shift register circuits as the first-type initial shift register circuit, and select one stage from the 2S+1 stages of the second-type offset shift register circuits as the second-type initial shift register circuit;

[0009] In the direction of the cascade of the multi-stage shift register circuits, the first type of initial shift register circuit and the second type of initial shift register circuit have the same offset direction relative to the multi-stage intermediate shift register circuit, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is an integer, and N is less than or equal to S.

[0010] In an exemplary embodiment, the gate shift register circuit further includes an initial signal terminal and a row control terminal; in the row control circuit, an input terminal is connected to the initial signal terminal, a control terminal is connected to the row control terminal, and an output terminal is connected to the input terminal of the multi-stage offset shift register circuit;

[0011] The row control circuit is configured to receive a forward and reverse scan control signal from the row control end, and to receive an initial signal from the initial signal end. Under the control of the forward and reverse scan control signal, one of the first type of initial shift register circuit and the second type of initial shift register circuit is used as a starting row of the shift register circuit, and the other is used as an ending row of the shift register circuit, and the initial signal is provided to the starting row of the shift register circuit.

[0012] In an exemplary embodiment, the gate drive circuit further includes a reset control circuit and a reset control terminal; the multi-stage offset shift register circuit includes a first offset shift register circuit, the first offset shift register circuit including an offset shift register circuit located on a side of a start row of the shift register circuit that is away from an end row of the shift register circuit, and an offset shift register circuit located on a side of an end row of the shift register circuit that is away from a start row of the shift register circuit;

[0013] The input end of the reset control circuit is connected to the reset control end, and the output end is connected to the enable signal end of the multi-stage offset shift register circuit. It is configured to receive a reset control signal from the reset control end, and under the control of the reset control signal, the first offset shift register circuit is set to a high-impedance state.

[0014] In an exemplary embodiment, the gate driving circuit further includes a plurality of row driving enhancement circuits respectively connected to the multi-stage shift register circuits;

[0015] The plurality of row drive enhancement circuits include a plurality of offset row drive enhancement circuits, wherein the input terminals of the plurality of offset row drive enhancement circuits are respectively connected to the output terminals of the multi-stage offset shift register circuit, and the enable signal terminals are connected to the reset control circuit;

[0016] The plurality of offset row driving enhancement circuits include a first offset row driving enhancement circuit, the first offset row driving enhancement circuit including an offset row driving enhancement circuit located on a side of the start row of the shift register circuit away from an end row of the shift register circuit, and an offset row driving enhancement circuit located on a side of the end row of the shift register circuit away from a start row of the shift register circuit;

[0017] The reset control circuit is configured to set the first offset row drive enhancement circuit to a high impedance state under the control of the reset control signal.

[0018] In an exemplary embodiment, the gate driving circuit further includes a plurality of offset transmission control circuits, wherein two adjacent stages of offset shift register circuits are cascade-connected via one of the offset transmission control circuits; a control terminal in the offset transmission control circuit is connected to the row control terminal;

[0019] In the two adjacent stages of the offset shift register circuits, the input end of the offset transmission control circuit is connected to the output end of one of the stages of the offset shift register circuit, and the output end of the offset transmission control circuit is connected to the input end of the other stage of the offset shift register circuit;

[0020] The offset transmission control circuit is configured to receive the initial row control signal from the row control terminal and be turned on or off under the control of the initial row control signal.

[0021] In an exemplary embodiment, the plurality of offset transmission control circuits include a first offset transmission control circuit and a second offset transmission control circuit, the first offset control circuit including an offset transmission control circuit located on a side of a start row of the shift register circuit that is farther from an end row of the shift register circuit, and an offset transmission control circuit located on a side of an end row of the shift register circuit that is farther from the start row of the shift register circuit; the second offset transmission control circuit including an offset transmission control circuit located on a side of a start row of the shift register circuit that is closer to the end row of the shift register circuit, and an offset transmission control circuit located on a side of an end row of the shift register circuit that is closer to the start row of the shift register circuit;

[0022] The first offset transmission control circuit is configured to be turned off under the control of the initial row control signal, and the second offset transmission control circuit is configured to be turned on under the control of the initial row control signal.

[0023] In an exemplary embodiment, the multi-stage shift register circuit further includes a multi-stage intermediate shift register circuit, the multi-stage offset shift register circuit includes at least one first-type offset shift register circuit and at least one second-type offset shift register circuit, the at least first-type offset shift register circuit is located on a first side of the multi-stage intermediate shift register circuit, and the second-type offset shift register circuit is located on a second side of the multi-stage intermediate shift register circuit;

[0024] One of the start row of the shift register circuits and the end row of the shift register circuits is the first type of offset shift register circuit, and the other is the second type of offset shift register circuit.

[0025] In an exemplary embodiment, the gate driving circuit further includes a shift control circuit, the shift control circuit includes a scan control circuit and an input control terminal; the row control circuit includes an initial row control circuit, and the row control terminal includes an initial row control terminal;

[0026] The initial row control circuit has an input terminal connected to the initial signal terminal, and a control terminal connected to the initial row control terminal, and is configured to receive an initial signal from the initial signal terminal and the initial row control signal from the initial row control terminal. Under the control of the initial control signal, one stage from the 2S+1 stages of the first-type offset shift register circuits is selected as the first-type initial shift register circuit, and one stage from the 2S+1 stages of the second-type offset shift register circuits is selected as the second-type initial shift register circuit.

[0027] The input end of the scanning control circuit is connected to the input control end, and the output end is connected to the initial row control end. The scanning control circuit is configured to receive an input control signal from the input control end, generate the initial row control signal under the control of the input control signal, and provide the initial row control signal to the initial row control end.

[0028] In an exemplary embodiment, the shift control circuit further includes a cutoff row control circuit, and the gate drive circuit further includes a reset control circuit and a reset control terminal;

[0029] The cutoff row control circuit has an input terminal connected to the input control terminal, an output terminal connected to the reset control terminal, and is configured to receive an input control signal from the input control terminal, generate a reset control signal under the control of the input control signal, and provide the reset control signal to the reset control terminal circuit;

[0030] The reset control circuit is configured to receive the reset control signal through the reset control terminal, and under the control of the reset control signal, sets the multi-stage offset shift register circuit to a high-impedance state or a working state.

[0031] In an exemplary embodiment, the number of the scan control circuits is 2S+1, the multi-stage offset shift register circuit includes 2S+1 stages of first-type offset shift register circuits and 2S+1 stages of second-type offset shift register circuits, the initial row control circuit includes 2S+1 first-type initial row control circuits and 2S+1 second-type initial row control circuits, the initial signal terminal includes 2S+1 first-type initial signal terminals and 2S+1 second-type initial signal terminals, and the initial row control terminal includes 2S+1 first initial row control terminals and 2S+1 second initial row control terminals, where S is an integer greater than or equal to 0;

[0032] The 2S+1 first-type initial row control circuits have input terminals connected to the 2S+1 first-type initial signal terminals, output terminals connected to the input terminals of the 2S+1-stage first-type offset shift register circuits, first control terminals connected to the 2S+1 first initial row control terminals, and second control terminals connected to the 2S+1 second initial row control terminals.

[0033] The 2S+1 second-type initial row control circuits have input terminals connected to the 2S+1 second-type initial signal terminals, output terminals connected to the input terminals of the 2S+1-stage second-type offset shift register circuits, first control terminals connected to the 2S+1 first initial row control terminals, and second control terminals connected to the 2S+1 second initial row control terminals.

[0034] In the 2S+1 scan control circuits, the input end is connected to the input control end, the first output end is connected to the 2S+1 first initial row control ends, and the second output end is connected to the 2S+1 second initial row control ends.

[0035] In an exemplary embodiment, the shift control circuit further includes m scan input inversion circuits, and the number of the input control terminals is m;

[0036] The m scan input inversion circuits have input terminals connected to the m input control terminals respectively, and are configured to invert the input control signals of the m input control terminals respectively to obtain inverted signals of the input control signals, and output the inverted signals of the input control signals through the output terminals;

[0037] An input terminal of the scan control circuit is connected to at least part of the m input control terminals and output terminals of the m scan input inverting circuits.

[0038] In an exemplary embodiment, the m input control terminals include first to fifth input control terminals, the m scan input inversion circuits include first to fifth scan input inversion circuits, and at least one of the scan control circuits includes an eighth NAND gate, a ninth NAND gate, a sixth NOR gate, and a nineteenth inverter.

[0039] The eighth NAND gate has a first input terminal connected to the first input control terminal or the output terminal of the first scan input inverting circuit, a second input terminal connected to the second input control terminal or the output terminal of the second scan input inverting circuit, a third input terminal connected to the third input control terminal or the output terminal of the third scan input inverting circuit, and an output terminal connected to the second input terminal of the sixth NOR gate;

[0040] The ninth NAND gate has a first input terminal connected to the fourth input control terminal or the output terminal of the fourth scan input inverting circuit, a second input terminal connected to the fifth input control terminal or the output terminal of the fifth scan input inverting circuit, and an output terminal connected to the first input terminal of the sixth NOR gate;

[0041] The output end of the sixth NOR gate is connected to the input end of the nineteenth inverter and the corresponding first initial row control end, and the output end of the nineteenth inverter is connected to the corresponding second initial row control end.

[0042] In an exemplary embodiment, at least one of the initial row control circuits includes a fifth transmission gate, an input terminal of the fifth transmission gate is connected to the corresponding initial signal terminal, an output terminal is connected to the input terminal of the corresponding offset shift register circuit, a first control terminal is connected to the corresponding first initial row control terminal, and a second control terminal is connected to the corresponding second initial row control terminal.

[0043] In an exemplary embodiment, the number of the cutoff row control circuits is 2S, the reset control circuit includes 2S first-type reset control circuits and 2S second-type reset control circuits, and the reset control terminal includes 2S first reset control terminals and 2S second reset control terminals;

[0044] The 2S first-type reset control circuits have input terminals connected to the 2S first reset control terminals, and output terminals connected to 2S stages of first-type offset shift register circuits, respectively. In the direction from the first-type offset shift register circuit to the second-type offset shift register circuit, the 2S stages of first-type offset shift register circuits are the first stage to the 2S stages of the 2S+1-stage first-type offset shift register circuit.

[0045] The 2S second-type reset control circuits have input terminals connected to the 2S second reset control terminals, and output terminals connected to 2S stages of second-type offset shift register circuits, respectively. In the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, the 2S stages of second-type offset shift register circuits are the first to the secondS stages of the 2S+1-stage second-type offset shift register circuits.

[0046] In the 2S cut-off row control circuits, the input end is connected to the input control end, the first output end is connected to the 2S first reset control ends respectively, and the second output end is connected to the 2S second reset control ends respectively.

[0047] In an exemplary embodiment, at least one of the reset control circuits includes a tenth NAND gate and a twentieth inverter;

[0048] In the first type reset control circuit, the input terminal of the tenth NAND gate is connected to the corresponding first reset control terminal, the output terminal is connected to the twelfth inverter, and the output terminal of the twelfth inverter is connected to the corresponding first type offset shift register circuit;

[0049] In the second type reset control circuit, the input end of the tenth NAND gate is connected to the corresponding second reset control end, the output end is connected to the twelfth inverter, and the output end of the twelfth inverter is connected to the corresponding second type offset shift register circuit.

[0050] In an exemplary embodiment, the shift control circuit further includes m reset input inversion circuits, and the number of the input control terminals is m;

[0051] The m reset input inverting circuits have input terminals connected to the m input control terminals respectively, and are configured to invert the input control signals of the m input control terminals respectively to obtain inverted signals of the input control signals, and output the inverted signals of the input control signals through the output terminals;

[0052] An input terminal of the cutoff row control circuit is connected to at least part of the m input control terminals and output terminals of the m reset input inverter circuits.

[0053] In an exemplary embodiment, the m input control terminals include first to fifth input control terminals, the m reset input inverting circuits include first to fifth reset input inverting circuits, the shift control circuit further includes first to S-th input subcircuits; the 2S cutoff row control circuits include S-1 first cutoff row subcircuits and S+1 second cutoff row subcircuits;

[0054] In the S-1 first cut-off row sub-circuits, the first input terminals are connected to the output terminals of the first input sub-circuit to the S-1th input sub-circuit, respectively; the second input terminals are connected to the output terminal of the Sth input sub-circuit, the first output terminals are connected to the first to S-1th first reset control terminals, respectively; and the second output terminals are connected to the first to S-1th second reset control terminals, respectively.

[0055] In the S+1 second cut-off row sub-circuits, the input end of the first second cut-off row sub-circuit is connected to the fifth input control end; the first input ends of the second to S-th second cut-off row sub-circuits are connected to the output end of the fifth reset input inverting circuit, and the second input ends are respectively connected to the output ends of the first input sub-circuit to the S-1-th input sub-circuit; in the S+1-th second cut-off row sub-circuit, the first input end is connected to the output end of the fifth reset input inverting circuit, and the second input end is connected to the four input control ends; in the S+1 second cut-off row sub-circuit, the first output end is respectively connected to the S-th to 2S+1 first reset control ends, and the second output end is respectively connected to the S-th to 2S+1 second reset control ends.

[0056] In an exemplary embodiment, the first input sub-circuit includes an eleventh NAND gate, wherein a first input terminal of the eleventh NAND gate is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, an output terminal is connected to the first input terminal and the first input terminal of the S-1th first cut-off row sub-circuit, and an output terminal is connected to the S-1th first cut-off row sub-circuit and the second second cut-off row sub-circuit, and the output terminal of the eleventh NAND gate serves as the output terminal of the first input sub-circuit;

[0057] The second input sub-circuit includes a twelfth NAND gate, wherein a first input terminal of the twelfth NAND gate is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the S-2th first cut-off row sub-circuit and the third second cut-off row sub-circuit, and the output terminal of the twelfth NAND gate serves as the output terminal of the second input sub-circuit;

[0058] The third input sub-circuit includes a thirteenth NAND gate, a seventh NOR gate, and a twenty-first inverter; the seventh NOR gate has a first end connected to the output of the first reset input inverter circuit, a second end connected to the output of the second reset input inverter circuit, and an output connected to the input of the twenty-first inverter; the output of the twenty-first inverter is connected to the second input of the thirteenth NAND gate, the first input of the thirteenth NAND gate is connected to the output of the third reset input inverter circuit, the output of the thirteenth NAND gate is connected to the S-3rd first cut-off row sub-circuit and the fourth second cut-off row sub-circuit, and the output of the thirteenth NAND gate serves as the output of the third input sub-circuit;

[0059] The fourth input sub-circuit includes a twenty-second inverter, the input end of the twenty-second inverter is connected to the output end of the third reset input inverter circuit, the output end of the twenty-second inverter is connected to the S-4th first cut-off row sub-circuit and the fifth second cut-off row sub-circuit, and the output end of the twenty-second inverter serves as the output end of the fourth input sub-circuit;

[0060] The fifth input sub-circuit includes a fourteenth NAND gate, an eighth NOR gate, and a twenty-third inverter; the fourteenth NAND gate has a first terminal connected to the output terminal of the first reset input inverter circuit, a second terminal connected to the output terminal of the second reset input inverter circuit, and an output terminal connected to the input terminal of the twenty-third inverter; the output terminal of the twenty-third inverter is connected to the second input terminal of the eighth NOR gate, the first input terminal of the eighth NOR gate is connected to the output terminal of the third reset input inverter circuit, the output terminal of the eighth NOR gate is connected to the (S-5)th first cut-off row sub-circuit and the sixth second cut-off row sub-circuit, and the output terminal of the eighth NOR gate serves as the output terminal of the fifth input sub-circuit;

[0061] The sixth input sub-circuit includes a ninth NOR gate, wherein a first input terminal of the ninth NOR gate is connected to the output terminal of the second reset input inverting circuit, a second input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the (S-6)th first cut-off row sub-circuit and the seventh second cut-off row sub-circuit, and the output terminal of the ninth NOR gate serves as the output terminal of the sixth input sub-circuit;

[0062] The seventh input sub-circuit includes a tenth NOR gate, wherein a first input terminal of the tenth NOR gate is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the (S-7)th first cut-off row sub-circuit and the eighth second cut-off row sub-circuit, and the output terminal of the tenth NOR gate serves as the output terminal of the seventh input sub-circuit;

[0063] The eighth input sub-circuit includes an eleventh NOR gate, a twenty-fourth inverter and a twenty-fifth inverter. The input end of the twenty-fourth inverter is connected to the third input control end, and the output end is connected to the first input end of the eleventh NOR gate. The second input end of the eleventh NOR gate is connected to the output end of the fifth reset input inverter circuit, and the output end is connected to the input end of the twenty-fifth inverter. The output end of the twenty-fifth inverter is connected to the S-1 first cut-off row sub-circuits, and the output end of the twenty-fifth inverter serves as the output end of the eighth input sub-circuit.

[0064] In an exemplary embodiment, the first cutoff row sub-circuit includes a twelfth NOR gate and a twenty-sixth inverter. The twelfth NOR gate has a first input terminal connected to a corresponding input sub-circuit among the first to S-1th input sub-circuits, a second input terminal connected to the Sth input sub-circuit, an output terminal connected to the twenty-sixth inverter and a corresponding first reset control terminal, and an output terminal of the twenty-sixth inverter is connected to the corresponding second reset control terminal; the output terminal of the twenty-sixth inverter serves as the second output terminal, and the output terminal of the twelfth NOR gate serves as the first output terminal.

[0065] In an exemplary embodiment, the first second cutoff row sub-circuit includes a twenty-seventh inverter, wherein the input terminal of the twenty-seventh inverter is connected to the fifth input control terminal, and the output terminal is connected to the first second reset control terminal;

[0066] The second to Sth second-blocking row sub-circuits include a fifteenth NAND gate, a twenty-eighth inverter, a thirteenth NOR gate, and a twenty-eighth inverter; the fifteenth NAND gate has a first input connected to the output of the fifth reset input inverter circuit, a second input connected to the corresponding input sub-circuit, and an output connected to the input of the twenty-eighth inverter; the output of the twenty-eighth inverter is connected to the first input of the thirteenth NOR gate, the second input of the thirteenth NOR gate is connected to the fifth input control terminal, and the output of the thirteenth NOR gate is connected to the input of the twenty-ninth inverter and the corresponding second reset control terminal; the output of the twenty-ninth inverter is connected to the corresponding first reset control terminal; the output of the thirteenth NOR gate serves as the second output of the corresponding second-blocking row sub-circuit, and the output of the twenty-ninth inverter serves as the first output of the corresponding second-blocking row sub-circuit;

[0067] The (S+1)th second cutoff row circuit includes a sixteenth NAND gate, a fourteenth NOR gate, and a thirtieth inverter. In the sixteenth NAND gate, a first input terminal is connected to the output terminal of the fifth reset input inverter circuit, a second input terminal is connected to the fourth input control terminal, and an output terminal is connected to the first input terminal of the fourteenth NOR gate; in the fourteenth NOR gate, a second input terminal is connected to the output terminal of the first input sub-circuit, an output terminal is connected to the input terminal of the thirtieth inverter and the (2S+1)th first reset control terminal, and the output terminal of the thirtieth inverter is connected to the (2S+1)th second reset control terminal.

[0068] In an exemplary embodiment, the gate drive circuit further includes 2S first-type offset transmission control circuits and 2S second-type offset transmission control circuits; two adjacent stages of the first-type offset shift register circuits are cascade-connected via one of the first-type offset transmission control circuits, and two adjacent stages of the second-type offset shift register circuits are cascade-connected via one of the second-type offset transmission control circuits;

[0069] In the 2S first-type offset transmission control circuits, the first control terminals are respectively connected to the 2S second initial row control terminals, and the second control terminals are respectively connected to the 2S first initial row control terminals; in the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, the 2S first initial row control terminals are the first to 2S of the 2S+1 first initial row control terminals, and the 2S second initial row control terminals are the first to 2S of the 2S+1 second initial row control terminals;

[0070] In the 2S second-type offset transmission control circuits, the first control terminals are respectively connected to the 2S second initial row control terminals, and the second control terminals are respectively connected to the 2S first initial row control terminals.

[0071] In an exemplary embodiment, in a direction from the first-type offset shift register circuit to the second-type offset shift register circuit, in two adjacent stages of the first-type offset shift register circuit, the input terminal of the first-type offset transmission control circuit is connected to the output terminal of the first-type offset shift register circuit of the previous stage, and the output terminal of the offset transmission control circuit is connected to the input terminal of the offset shift register circuit of the next stage;

[0072] In the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, in the two adjacent stages of the second-type offset shift register circuit, the input end of the second-type offset transmission control circuit is connected to the output end of the first-type offset shift register circuit of the previous stage, and the output end of the offset transmission control circuit is connected to the input end of the offset shift register circuit of the next stage.

[0073] In an exemplary embodiment, the row control circuit further includes 2S+1 first-type forward and reverse scan control circuits and 2S+1 second-type forward and reverse scan control circuits, and the row control terminal further includes a first forward and reverse scan control terminal and a second forward and reverse scan control terminal;

[0074] The output ends of the 2S+1 first-type initial row control circuits are connected to the input ends of the 2S+1-stage first-type offset shift register circuits through the 2S+1 first-type forward and reverse scan control circuits; the output ends of the 2S+1 second-type initial row control circuits are connected to the input ends of the 2S+1-stage second-type offset shift register circuits through the 2S+1 second-type forward and reverse scan control circuits;

[0075] The 2S+1 first-type forward and reverse scan control circuits have input terminals connected to the output terminals of the 2S+1 first-type initial row control circuits, output terminals connected to the input terminals of the 2S+1-stage first-type offset shift register circuits, a first control terminal connected to the first forward and reverse scan control terminal, and a second terminal connected to the second forward and reverse scan control terminal;

[0076] In the 2S+1 second-type forward and reverse scan control circuits, the input ends are respectively connected to the output ends of the 2S+1 second-type initial row control circuits, the output ends are respectively connected to the input ends of the 2S+1-level second-type offset shift register circuits, the first control end is connected to the second forward and reverse scan control end, and the second end is connected to the first forward and reverse scan control end.

[0077] In an exemplary embodiment, the scan control circuit includes at least two 3-line-8-line decoders, 2S+1 expansion circuits, 2S+1 output terminals and at least one expansion input control terminal. The input control terminal of the scan control circuit includes three input terminals of the 3-line-8-line decoder and the at least one expansion input terminal. The input terminals of the 2S+1 expansion circuits are connected to 2S+1 output terminals of the at least two 3-line-8-line decoders, and the output terminals of the 2S+1 expansion circuits serve as 2S+1 output terminals of the scan control circuit respectively.

[0078] In an exemplary embodiment, the input control terminals of the scan control circuit include first to fifth input control terminals, the at least two 3-line-8-line decoders include a first 3-line-8-line decoder and a second 3-line-8-line decoder, the three input terminals of the first 3-line-8-line decoder serve as the first to third input control terminals of the scan control circuit, and the inverted signal terminals of the first to third input control terminals serve as the input terminals of the second 3-line-8-line decoder.

[0079] In an exemplary embodiment, the 2S+1 expansion circuits include 2S first expansion circuits and 1 second expansion circuit; the first expansion circuit and the second expansion circuit each include a ninth NAND gate, a sixth NOR gate, and a nineteenth inverter; the second expansion circuit further includes an eighth NAND gate;

[0080] In the ninth NAND gate, a first input terminal is connected to the fourth input control terminal or the inverted signal terminal of the fourth input control terminal, a second input terminal is connected to the fifth input control terminal or the inverted signal terminal of the fifth input control terminal, and an output terminal is connected to the first input terminal of the sixth NOR gate;

[0081] The output end of the sixth NOR gate is connected to the input end of the nineteenth inverter, the output end of the sixth NOR gate serves as an output end of the scan control circuit, and the output end of the nineteenth inverter serves as an inverted signal end of an output end of the scan control circuit;

[0082] In the first expansion circuit, the second input terminal of the sixth NOR gate is connected to one output terminal of the 3-line to 8-line decoder, and in the second expansion circuit, the second input terminal of the sixth NOR gate is connected to the output terminal of the eighth NAND gate;

[0083] In the eighth NAND gate, three input terminals are connected to the first input control terminal to the third input control terminal respectively, and an output terminal is connected to the second input terminal of the sixth NOR gate.

[0084] In a second aspect, an embodiment of the present disclosure provides a working method of a gate drive circuit, which is applied to the gate drive circuit described in any of the above embodiments, wherein the gate drive circuit includes a multi-stage shift register circuit and a row control circuit, the multi-stage shift register circuits being cascaded, and the multi-stage shift register circuits including a multi-stage intermediate shift register circuit and a 4S+2-stage offset shift register circuit; in the direction of the cascade connection of the multi-stage shift register circuits, the 4S+2-stage offset shift register circuit includes a 2S+1-stage first-type offset shift register circuit located on one side of the multi-stage intermediate shift register circuit, and a 2S+1-stage second-type offset shift register circuit located on the other side of the multi-stage intermediate shift register circuit; the working method includes:

[0085] The row control circuit receives an initial row control signal, and under the control of the initial row control signal, selects one level from the 2S+1 levels of the first-type offset shift register circuits as the first-type initial shift register circuit, and selects one level from the 2S+1 levels of the second-type offset shift register circuits as the second-type initial shift register circuit; in the direction of the cascade of the multi-stage shift register circuits, the offset direction of the first-type initial shift register circuit and the second-type initial shift register circuit relative to the multi-stage intermediate shift register circuit are consistent, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is a positive integer, and N is less than or equal to S.

[0086] In a third aspect, an embodiment of the present disclosure provides a display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit comprises the gate driving circuit described in any of the above embodiments.

[0087] In a fourth aspect, an embodiment of the present disclosure provides a display device comprising the display substrate described in any of the above embodiments.

[0088] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] The accompanying drawings are intended to facilitate understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of each component in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0090] FIG1 is a schematic structural diagram of a silicon-based OLED display device;

[0091] FIG2 is a schematic diagram of a planar structure of a display area in a silicon-based OLED display device;

[0092] FIG3 is a schematic diagram of the cross-sectional structure of a display area in a silicon-based OLED display device;

[0093] FIG4 a is an equivalent circuit diagram of a pixel driving circuit;

[0094] FIG4 b is an equivalent circuit diagram of a pixel driving circuit;

[0095] FIG5a is a driving timing diagram of the pixel driving circuit shown in FIG4b;

[0096] FIG5b is a driving timing diagram of the pixel driving circuit shown in FIG4b;

[0097] FIG6 a is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0098] FIG6 b is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0099] FIG6 c is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0100] FIG6 d is a schematic structural diagram of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0101] FIG7 is a working principle diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0102] FIG8 is an equivalent circuit diagram of a first operation circuit according to an exemplary embodiment of the present disclosure;

[0103] FIG9 a is a working principle diagram of a second operation circuit according to an exemplary embodiment of the present disclosure;

[0104] FIG9b is a working principle diagram of the latch in FIG9a provided by an exemplary embodiment of the present disclosure;

[0105] FIG9c is a timing diagram of an operation of a latch provided by an exemplary embodiment of the present disclosure;

[0106] FIG10 is an equivalent circuit diagram of a second operation circuit according to an exemplary embodiment of the present disclosure;

[0107] FIG11 is a working principle diagram of a third operation circuit according to an exemplary embodiment of the present disclosure;

[0108] FIG12 is an equivalent circuit diagram of a third operation circuit according to an exemplary embodiment of the present disclosure;

[0109] FIG13 is a working principle diagram of a level converter according to an exemplary embodiment of the present disclosure;

[0110] FIG14 is a working principle diagram of a row drive enhancer according to an exemplary embodiment of the present disclosure;

[0111] FIG15 is an equivalent circuit diagram of a level converter according to an exemplary embodiment of the present disclosure;

[0112] FIG16 is an equivalent circuit diagram of a row driver booster according to an exemplary embodiment of the present disclosure;

[0113] FIG17 is an equivalent circuit diagram of an output circuit according to an exemplary embodiment of the present disclosure;

[0114] FIG18 is a schematic structural diagram of a shift register circuit according to an exemplary embodiment of the present disclosure;

[0115] FIG19 is a diagram showing the working principle of a trigger according to an exemplary embodiment of the present disclosure;

[0116] FIG20 is a timing diagram of an operation of a trigger according to an exemplary embodiment of the present disclosure;

[0117] FIG21 is an equivalent circuit diagram of a trigger according to an exemplary embodiment of the present disclosure;

[0118] FIG22 is a working principle diagram of a first test circuit according to an exemplary embodiment of the present disclosure;

[0119] FIG23 is a working principle diagram of a second test circuit according to an exemplary embodiment of the present disclosure;

[0120] FIG24 is a working principle diagram of a third test circuit according to an exemplary embodiment of the present disclosure;

[0121] FIG25 a is a schematic diagram showing an example of image shift according to an exemplary embodiment of the present disclosure;

[0122] FIG25 b is a schematic diagram showing an example of image shift according to an exemplary embodiment of the present disclosure;

[0123] FIG25c is a schematic diagram showing an example of image shift according to an exemplary embodiment of the present disclosure;

[0124] FIG25 d is a schematic diagram showing an example of image shift according to an exemplary embodiment of the present disclosure;

[0125] FIG25e is a schematic diagram showing an example of image shift according to an exemplary embodiment of the present disclosure;

[0126] FIG25f is a schematic diagram showing an example of image shift according to an exemplary embodiment of the present disclosure;

[0127] FIG25g is a schematic diagram showing image flipping according to an exemplary embodiment of the present disclosure;

[0128] FIG25h is a schematic diagram showing image flipping according to an exemplary embodiment of the present disclosure;

[0129] FIG26 a is a schematic diagram of an exemplary embodiment of the present disclosure showing an image display;

[0130] FIG26 b is a schematic diagram showing a flipped image according to an exemplary embodiment of the present disclosure;

[0131] FIG27 is a schematic diagram of the architecture of a gate driving circuit according to an exemplary embodiment of the present disclosure;

[0132] FIG28 a is a circuit schematic diagram of a gate driving circuit of a first type of control row according to an exemplary embodiment of the present disclosure;

[0133] FIG28 b is a circuit schematic diagram of a gate driving circuit of a second type of control row according to an exemplary embodiment of the present disclosure;

[0134] FIG29 is a schematic diagram of a shift control module according to an exemplary embodiment of the present disclosure;

[0135] 30a and 30b are working principle diagrams of a first decoding circuit according to an exemplary embodiment of the present disclosure;

[0136] FIG30c is a working principle diagram of a scan control circuit according to an exemplary embodiment of the present disclosure;

[0137] FIG31 is a working principle diagram of a second decoding circuit according to an exemplary embodiment of the present disclosure;

[0138] FIG32 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0139] FIG33 is a schematic structural diagram of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0140] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0141] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0142] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0143] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of components with reference to the accompanying drawings. This is merely to facilitate the description of this specification and simplify the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of the components may be appropriately changed depending on the direction in which each component is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced as appropriate.

[0144] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0145] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0146] In this specification, in order to distinguish the two electrodes of a transistor other than the gate electrode, one of the electrodes is directly described as the first electrode and the other as the second electrode. The first electrode can be the drain electrode and the second electrode can be the source electrode, or the first electrode can be the source electrode and the second electrode can be the drain electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchangeable. Therefore, in this specification, the terms "source electrode" and "drain electrode" can be interchanged.

[0147] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0148] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0149] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0150] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0151] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0152] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0153] FIG1 is a schematic diagram of the structure of a silicon-based OLED display device. As shown in FIG1 , the silicon-based OLED display device may include a display area and a non-display area. The display area may include multiple scan signal lines, multiple data signal lines, and multiple sub-pixels Pxij forming multiple pixel rows and multiple pixel columns. The multiple scan signal lines are respectively arranged in the multiple pixel rows, and the multiple data signal lines are respectively arranged in the multiple pixel columns. Each sub-pixel Pxij may include at least a pixel driving circuit and a light-emitting device. The pixel driving circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel driving circuit of each sub-pixel Pxij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel Pxij may refer to the sub-pixel in the i-th pixel row and the j-th pixel column. The pixel driving circuit of the sub-pixel Pxij is respectively connected to the i-th scan signal line and the j-th data signal line, where i and j may be natural numbers. The non-display area may include a display driver integrated circuit (DDIC), a gate driver (GD), and a data driver (SD). The display driver circuit may include at least a timing controller (TCON). The timing controller is configured to generate timing signals required by the gate driver, such as a start signal (STV) and a clock signal (CKV), and send the timing signals to the gate driver. The gate driver is respectively connected to a plurality of scan signal lines in the display area. The gate driver is configured to provide the required timing signals (timing) to the connected pixel driver circuit to implement a display progressive scan function. The data driver is respectively connected to a plurality of data signal lines in the display area. The data driver is configured to provide the required data signals (data) to the connected pixel driver circuit to implement switching and control of the display screen. In an exemplary embodiment, the gate driver may include a gate driver circuit, and the data driver may include a data driver circuit.

[0154] In one exemplary embodiment, a silicon-based OLED display device may utilize a single-chip display architecture ("One Chip"), integrating a gate driver, data driver, clock control unit, image processing unit, and storage unit on a single chip. A chip with a One Chip architecture includes both digital and analog components, making it a mixed-signal chip.

[0155] In another exemplary embodiment, the silicon-based OLED display device can be a dual-chip display architecture (Two Chip), in which the gate driving device and the data driving device are integrated in the display substrate, and the clock control unit, the image processing unit, the mobile industry processor interface (MIPI) and the storage unit are integrated in one chip, which is bonded to the display substrate through the COC process.

[0156] Figure 2 is a schematic diagram of the planar structure of a display area in a silicon-based OLED display device. As shown in Figure 2, the display area may include multiple pixel units P arranged in a matrix on a plane parallel to the display device. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 that emits a third color light. Each of the three sub-pixels may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the sub-pixel is respectively connected to a scan signal line and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the display light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0157] In an exemplary embodiment, the first subpixel P1 may be a red (R) subpixel emitting red light, the second subpixel P2 may be a blue (B) subpixel emitting blue light, and the third subpixel P3 may be a green (G) subpixel emitting green light.

[0158] In an exemplary embodiment, the shape of the sub-pixels can be any one or more of a triangle, square, rectangle, rhombus, trapezoid, parallelogram, pentagon, hexagon, and other polygons. The three sub-pixels can be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a herringbone arrangement, etc., which is not limited in this disclosure. In other possible embodiments, the pixel unit can include four sub-pixels, which is not limited in this disclosure.

[0159] FIG3 is a schematic diagram of the cross-sectional structure of the display area in a silicon-based OLED display device, illustrating a structure that uses white light + color filter to achieve full color. As shown in FIG3 , in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on the side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on the side of the color filter structure layer 105 away from the silicon substrate 101, and a cover layer 107 disposed on the side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementations, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0160] In an exemplary embodiment, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be prepared on the silicon substrate 101 by a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units. The circuit units may include at least a pixel driving circuit. The pixel driving circuit is connected to a scanning signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistors and a storage capacitor. FIG3 shows only one transistor as an example. The transistor may include a gate electrode G, a first electrode S, and a second electrode D. The gate electrode G, the first electrode S, and the second electrode D may be connected to corresponding connection electrodes through tungsten metal-filled vias (i.e., tungsten vias, W-vias), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0161] In an exemplary embodiment, the light-emitting structure layer 103 may include a plurality of light-emitting devices, each of which may include at least an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second pole D of the transistor via a connecting electrode, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the cathode is connected to the second power line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML for short), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, for a light-emitting device that emits white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0162] In an exemplary embodiment, the first encapsulation layer 104 and the second encapsulation layer 106 can be encapsulated using a thin film encapsulation (TFE) method to ensure that external moisture cannot enter the light-emitting structure layer. The color filter structure layer 105 can include at least a red filter unit, a blue filter unit, and a green filter unit. The red filter unit is set in the red sub-pixel to filter the white light emitted by the light-emitting device into red light. The blue filter unit is set in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light. The green filter unit is set in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic material such as colorless polyimide.

[0163] Figure 4a is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4a, the pixel driving circuit has a 4T2C structure, which can include four transistors (a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (a first capacitor C1 and a second capacitor C2). The pixel driving circuit is connected to six signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DATA, a first power line VDD, and a second power line VSS).

[0164] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the first electrode of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2, respectively. The third node N3 is connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, respectively.

[0165] In an exemplary embodiment, the first transistor T1 can be referred to as a write switch transistor, a gate electrode of the first transistor T1 is connected to the first scan signal line S1, a first electrode of the first transistor T1 is connected to the data signal line DATA, and a second electrode of the first transistor T1 is connected to the first node N1.

[0166] In an exemplary embodiment, the second transistor T2 is called a display switch transistor, a gate electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the first power line VDD, and a second electrode of the second transistor T2 is connected to the second node N2.

[0167] In an exemplary embodiment, the third transistor T3 may be referred to as a driver transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0168] In an exemplary embodiment, the fourth transistor T4 can be called an auto zero transistor, a gate electrode of the fourth transistor T4 is connected to the third scan signal line S3, a first electrode of the fourth transistor T4 is connected to the second power line VSS, and a second electrode of the fourth transistor T4 is connected to the third node N3.

[0169] In an exemplary embodiment, a first end of the first capacitor C1 is connected to the first node N1, a second end of the first capacitor C1 is connected to the second node N2, a first end of the second capacitor C2 is connected to the second node N2, and a second end of the second capacitor C2 is connected to the first power line VDD.

[0170] In an exemplary embodiment, the light emitting device EL may be an organic electroluminescent diode (OLED) including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device XL is connected to the third node N3, and the second electrode of the light emitting device EL is connected to the common voltage line VCOM.

[0171] In an exemplary embodiment, the signal of the first power line VDD may be a continuously provided high level signal, and the signals of the second power line VSS and the common voltage line VCOM may be continuously provided low level signals.

[0172] In an exemplary embodiment, the first to fourth transistors T1 to T4 may be P-type transistors (PMOS) or N-type transistors (NMOS). For example, the first to fourth transistors T1 to T4 are all P-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the difficulty of manufacturing the display substrate, and improve the product yield.

[0173] In an exemplary embodiment, the first to fourth transistors T1 to T4 may include P-type transistors and N-type transistors. For example, the first to third transistors T1 to T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as shown in FIG4a. In an exemplary embodiment, the first to fourth transistors T1 to T4 are all P-type transistors. For example, the first to fourth transistors T1 to T4 may all be P-type transistors, as shown in FIG4b.

[0174] FIG5a is a driving timing diagram of the pixel driving circuit shown in FIG4a. As shown in FIG5a, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0175] The first phase A1 (from the first moment t1 to the second moment t2) can be called the initialization phase. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, so that the first transistor T1, the second transistor T2 and the fourth transistor T4 are turned on. The first transistor T1 is turned on so that the bias voltage Vofs output by the data signal line DATA is written into the first capacitor C1, and the potential Vs of the first node N1 (i.e., the gate electrode of the third transistor T3) is Vofs. The second transistor T2 is turned on so that the first power supply voltage ELVDD output by the first power line VDD is written into the second node N2, and the potential Vg of the second node N2 (i.e., the first electrode of the third transistor T3) is ELVDD. At this time, the gate-source voltage Vgs of the third transistor T3 is ELVDD-Vofs, and the storage voltage V of the first capacitor C1 is V cs =ELVDD-Vofs, the potential Vd of the third node N3 (ie, the second electrode of the third transistor T3) = Vg+Vth, preparing for the next stage of discharge. ofs >|Vth|, where Vth is the threshold voltage of the third transistor T3.

[0176] The second stage A2 (from the second moment t2 to the third moment t3) can be called the self-discharge stage. The signal of the third scanning signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scanning signal line S1 changes from a low-level signal to a high-level signal, causing the first transistor T1 to be disconnected first, and the first node N1 to float. Subsequently, the signal of the second scanning signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to be disconnected, and the second node N2 forms a loop through the turned-on third transistor T3, the third node N3 and the turned-on fourth transistor T4, and begins to discharge, and the potential of the second node N2 drops. Because the first node N1 is floating, the voltage difference across the first capacitor C1 remains unchanged, and thus the potential of the first node N1 drops as the potential of the second node N2 drops. Due to the back gate effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, and thus the equivalent threshold voltage |V th_EF |As the potential of the second node N2 decreases, the equivalent threshold voltage of the third transistor T3 gradually increases. th_EF |=α(ELVDD-Vs)+|Vth|, α is the back gate coefficient. When the equivalent threshold voltage of the third transistor T3 |V th_EF When Vgs increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 is turned off and the second node N2 stops discharging.

[0177] The third stage A3 (from the third moment t3 to the fourth moment t4) can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 is continuously disconnected. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 is continuously turned on. The signal of the first scan signal line S1 changes from a high-level signal to a low-level signal, turning on the first transistor T1. The first transistor T1 is turned on so that the data voltage Vdata output by the data signal line DATA is written to the first node N1, and the potential of the first node N1 changes from Vofs to Vdata. Since the second node N2 is floating, threshold compensation can be achieved in this stage.

[0178] The fourth phase A4 (after the fifth moment t5) can be called the light-emitting phase. The signals on the second scan signal line S2 and the third scan signal line S3 are low-level signals, and the signal on the first scan signal line S1 is high-level signal, turning on the second transistor T2 and turning off the first transistor T1 and the fourth transistor T4. Turning on the second transistor T2 causes the power supply voltage output from the first power line VDD to provide a driving voltage to the first electrode of the light-emitting device EL through the turned-on second transistor T2 and third transistor T3, driving the light-emitting device EL to emit light.

[0179] The fourth moment t4 is the moment when the signal of the first scanning signal line S1 changes from a low level to a high level, that is, the end time of the second valid signal in the signal of the first scanning signal line S1.

[0180] In the light-emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0181] FIG5 b is a driving timing diagram of the pixel driving circuit shown in FIG4 b . As shown in FIG5 b , the operation process of the pixel driving circuit in FIG4 b may include a first stage A1 to a fourth stage A4. FIG5 b differs from FIG5 a in that the timing of the third scanning signal line S3 is different. In FIG4 a and FIG5 a , the fourth transistor T4 is an N-type transistor (high level turns on, low level turns off), while in FIG4 b and FIG5 b , the fourth transistor T4 is a P-type transistor (high level turns off, low level turns on).

[0182] The signals of the first scanning signal line S1, the second scanning signal line S2 and the third scanning signal line S3 in Figures 5a and 5b are usually provided by the gate driving circuit. The gate driving circuit is usually in a cascade connection relationship. Technical problems such as signal input errors or initial signal input errors in the gate driving circuit often occur between two adjacent levels of gate driving circuits, resulting in the pixel driving circuit not being able to work normally. Under normal circumstances, the displayed image will be displayed in the center. In practice, there is a technical problem of incomplete image display due to occlusion (such as mechanical occlusion).

[0183] An embodiment of the present disclosure provides a gate driving circuit, which may include a multi-stage shift register circuit and a row control circuit. The multi-stage shift register circuit is cascade-connected, and the multi-stage shift register circuit includes a multi-stage intermediate shift register circuit and a 4S+2-stage offset shift register circuit.

[0184] In the direction of cascading the multi-stage shift register circuits, the 4S+2-stage offset shift register circuit includes a 2S+1-stage first-type offset shift register circuit located on one side of the multi-stage intermediate shift register circuit, and a 2S+1-stage second-type offset shift register circuit located on the other side of the multi-stage intermediate shift register circuit;

[0185] The row control circuit is configured to receive an initial row control signal, and under the control of the initial row control signal, select one stage from the 2S+1 stages of the first-type offset shift register circuits as the first-type initial shift register circuit, and select one stage from the 2S+1 stages of the second-type offset shift register circuits as the second-type initial shift register circuit;

[0186] In the direction of the cascade of the multi-stage shift register circuits, the first type of initial shift register circuit and the second type of initial shift register circuit have the same offset direction relative to the multi-stage intermediate shift register circuit, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is an integer, and N is less than or equal to S.

[0187] The gate drive circuit provided by the embodiments of the present disclosure includes a multi-stage shift register circuit and a row control circuit. Under the control of an initial row control signal, the row control circuit selects one stage from a 2S+1-stage first-type offset shift register circuit as a first-type initial shift register circuit, and selects one stage from a 2S+1-stage second-type offset shift register circuit as a second-type initial shift register circuit. The first-type initial shift register circuit and the second-type initial shift register circuit are offset in the same direction relative to the multi-stage intermediate shift register circuit, and the number of offset stages relative to the multi-stage intermediate shift register circuit is N, where N is an integer and S is an integer, and N is less than or equal to S. The technical solution provided by the embodiments of the present disclosure can shift the first-type initial shift register circuit and the second-type initial shift register circuit, thereby achieving pixel-level alignment or preventing incomplete displayed images due to occlusion.

[0188] As shown in FIG6a and FIG6b, the gate driving circuit provided by the embodiment of the present disclosure may include a multi-stage shift register circuit 100 and a row control circuit 01. The multi-stage shift register circuit 100 is cascade-connected, and the multi-stage shift register circuit 100 includes a multi-stage intermediate shift register circuit and a 4S+2-stage offset shift register circuit P100.

[0189] In the direction of cascading the multi-stage shift register circuits, the 4S+2-stage offset shift register circuit P100 may include a 2S+1-stage first-type offset shift register circuit P100-1 located on one side of the multi-stage intermediate shift register circuit, and a 2S+1-stage second-type offset shift register circuit P100-2 located on the other side of the multi-stage intermediate shift register circuit.

[0190] The row control circuit is configured to receive an initial row control signal, and under the control of the initial row control signal, select one stage from the 2S+1 stages of the first-type offset shift register circuits as the first-type initial shift register circuit, and select one stage from the 2S+1 stages of the second-type offset shift register circuits as the second-type initial shift register circuit;

[0191] In the direction of the cascade of the multi-stage shift register circuits, the first type of initial shift register circuit and the second type of initial shift register circuit have the same offset direction relative to the multi-stage intermediate shift register circuit, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is a positive integer, and N is less than or equal to S.

[0192] In an exemplary embodiment, the movement directions of the first type initial shift register circuit and the second type initial shift register circuit can be controlled by a row control circuit, which can solve the technical problem of being unable to display a complete image due to occlusion, or can be applicable to pixel-level alignment.

[0193] In an exemplary embodiment, the gate driving circuit may further include an initial signal terminal and a row control terminal; in the row control circuit, the input terminal is connected to the initial signal terminal, the control terminal is connected to the row control terminal, and the output terminal is connected to the input terminal of the multi-stage offset shift register circuit;

[0194] The row control circuit is configured to receive a forward and reverse scan control signal from a row control terminal, and an initial signal from an initial signal terminal. Under the control of the forward and reverse scan control signal, one of the first type of initial shift register circuit and the second type of initial shift register circuit is used as a starting row of the shift register circuit, and the other is used as an ending row of the shift register circuit, and the initial signal is provided to the starting row of the shift register circuit.

[0195] As shown in FIG6a and FIG6b, a structural diagram of a gate drive circuit provided in an embodiment of the present disclosure is shown. The gate drive circuit may include a multi-stage shift register circuit 100, a row control circuit 01, an initial signal terminal IN_STV, and a row control terminal (for example, IN_Z8, GSD_BW, and GSD_FW). The multi-stage shift register circuits 100 are cascade-connected, and the multi-stage shift register circuit 100 includes a multi-stage offset shift register circuit P100. In the row control circuit 01, the input terminal is connected to the initial signal terminal IN_STV, the control terminal is connected to the row control terminal (for example, IN_Z8, GSD_BW, and GSD_FW), and the output terminal is connected to the input terminal of the multi-stage offset shift register circuit P100.

[0196] The row control circuit 01 is configured to receive the initial row control signal (Zn, Z_n, Zn_, Z_n_, n is an integer, and the value of n can be 0 to S) and the forward and reverse scan control signal (GSD_BW, GSD_FW) from the row control end, and receive the initial signal STV from the initial signal end IN_STV. Under the control of the initial row control signal, two are selected from the multi-stage offset shift register circuit P100 as the initial shift register circuits. Under the control of the forward and reverse scan control signal, one of the two initial shift register circuits is used as the starting row of the shift register circuit, and the other is used as the end row of the shift register circuit, and the initial signal STV is provided to the starting row of the shift register circuit.

[0197] In an exemplary embodiment, under the control of the initial row control signal, the row control circuit 01 selects two from the multi-stage offset shift register circuit P100 as the initial shift register circuits, and can determine the two initial shift register circuits. Under the control of the forward and reverse scan control signal, one of the two initial shift register circuits is used as the starting row of the shift register circuit, and the other is used as the end row of the shift register circuit. The initial signal STV is provided to the starting row of the shift register circuit, and the end row of the shift register circuit cannot receive the initial signal STV. The initial signal STV is input by the starting row of the shift register circuit and transmitted to the end row of the shift register circuit through the multi-stage cascaded shift register circuit 100.

[0198] In an exemplary embodiment, as shown in FIG6a and FIG6b, the gate driving circuit may further include a reset control circuit 10-3 and a reset control terminal (Tn, where n is an integer and the value of n may be 0 to S); the multi-stage offset shift register circuit P100 includes a first offset shift register circuit, the first offset shift register circuit including an offset shift register circuit located on a side of a start row of the shift register circuit that is away from an end row of the shift register circuit, and an offset shift register circuit located on a side of an end row of the shift register circuit that is away from a start row of the shift register circuit;

[0199] The input end of the reset control circuit 10-3 is connected to the reset control end IN_Tn, and the output end is connected to the enable signal end of the multi-stage offset shift register circuit P100. It is configured to receive the reset control signal Tn from the reset control end IN_Tn. Under the control of the reset control signal Tn, the first offset shift register circuit is set to a high-impedance state.

[0200] In an exemplary embodiment, as shown in FIG6 a and FIG6 b , the gate driving circuit may further include a plurality of row driving enhancement circuits 400 respectively connected to the multi-stage shift register circuits;

[0201] The multiple row driver enhancement circuits 400 include multiple offset row driver enhancement circuits P400. In the multiple offset row driver enhancement circuits P400, the input terminals are respectively connected to the output terminals of the multi-stage offset shift register circuit P100, and the enable signal terminals are connected to the reset control circuit 10-3.

[0202] The plurality of offset row driving enhancement circuits P400 include a first offset row driving enhancement circuit, the first offset row driving enhancement circuit including an offset row driving enhancement circuit located on a side of the shift register circuit that is away from the end row of the shift register circuit, and an offset row driving enhancement circuit located on a side of the end row of the shift register circuit that is away from the start row of the shift register circuit;

[0203] The reset control circuit is configured to set the first offset row drive enhancement circuit to a high impedance state under the control of a reset control signal.

[0204] In an exemplary embodiment, as shown in FIG6 a and FIG6 b , the gate driving circuit may further include a plurality of offset transmission control circuits P10 - 1 , wherein two adjacent stages of offset shift register circuits P100 are cascade-connected via one of the offset transmission control circuits P10 - 1 ; a control terminal in the offset transmission control circuit P10 - 1 is connected to a row control terminal;

[0205] In two adjacent stages of offset shift register circuits P100, the input terminal of the offset transmission control circuit P10-1 is connected to the output terminal of one stage of the offset shift register circuit P100, and the output terminal of the offset transmission control circuit P10-1 is connected to the input terminal of the other stage of the offset shift register circuit P100;

[0206] The offset transmission control circuit P10 - 1 is configured to receive an initial row control signal (Zn, Z_n, Zn_, Z_n_) from the row control terminal 01 and is turned on or off under the control of the initial row control signal.

[0207] In an exemplary embodiment, the plurality of offset transmission control circuits Zn, Z_n may include a first offset transmission control circuit and a second offset transmission control circuit, the first offset control circuit including an offset transmission control circuit located on a side of a start row of a shift register circuit that is farther from an end row of the shift register circuit, and an offset transmission control circuit located on a side of an end row of the shift register circuit that is farther from the start row of the shift register circuit; the second offset transmission control circuit including an offset transmission control circuit located on a side of a start row of the shift register circuit that is closer to the end row of the shift register circuit, and an offset transmission control circuit located on a side of an end row of the shift register circuit that is closer to the start row of the shift register circuit;

[0208] The first offset transmission control circuit is configured to be turned off under the control of the initial row control signal, and the second offset transmission control circuit is configured to be turned on under the control of the initial row control signal.

[0209] In an exemplary embodiment, as shown in FIG6a and FIG6b, the multi-stage shift register circuit 100 may further include a multi-stage intermediate shift register circuit 100, the multi-stage offset shift register circuit including at least one first-type offset shift register circuit (such as P100 in FIG6a) and at least one second-type offset shift register circuit (such as P100 in FIG6b), at least the first-type offset shift register circuit is located on a first side of the multi-stage intermediate shift register circuit, and the second-type offset shift register circuit is located on a second side of the multi-stage intermediate shift register circuit;

[0210] One of the start row of the shift register circuit and the end row of the shift register circuit is a first type offset shift register circuit, and the other is a second type offset shift register circuit.

[0211] The first type of offset shift register circuit P100 is indicated by the OrbitS row to the Orbit-S row in FIG6a , and the second type of offset shift register circuit P100 is indicated by the OrbitS row to the Orbit-S row in FIG6b . The multi-stage intermediate shift register circuit 100 is located between the Orbit-S row in FIG6a and the OrbitS row in FIG6b . Of the starting row and the ending row of the shift register circuit, one is a first type of offset shift register circuit, and the other is a second type of offset shift register circuit. The displayed image can be offset in a first or second direction. In the event of mechanical obstruction or pixel-level alignment during assembly, the displayed image can be shifted to avoid incomplete display, which is suitable for pixel-level alignment.

[0212] The technical solution of the gate driving circuit disclosed in the present invention is described below through exemplary embodiments.

[0213] As shown in FIG6c, it is a schematic diagram of the structure of a multi-stage cascade gate drive circuit (including a multi-stage intermediate stage shift register circuit). Each gate drive circuit may include a logic control circuit 10 and a target signal generating circuit 20. The logic control circuit 10 may include a logic control unit (for example, it may include at least one of a transmission gate, a logic control transistor, a NAND gate, and an inverter), which is mainly used for addressing, forward and reverse scanning control, etc. (10-3 is a reset control subcircuit, which is configured to reset the row drive enhancer 400). Among them, Z0 to Zn+1 and Z0_ to Zn+1_ The target signal generating circuit 20 may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level conversion circuit (Level shifter) 300 and a line driver enhancement circuit (Line Driver) 400, which are mainly used to generate the line drive timing signal as shown in Figure 5a or Figure 5b. In an exemplary embodiment, the gate driver circuit can be arranged in the non-display area of ​​the display substrate, can be located on one side of the pixel row direction of the display area in the display substrate, or can be located on both sides of the pixel row direction of the display area in the display substrate. The gate drive device may include multiple cascaded gate drive circuits, at least one of which is connected to a scan signal line in a pixel row in the display area, providing a scan signal to the connected scan signal line. When the gate drive device is positioned on both sides of the pixel row in the display area, the scan signal lines in the pixel row are driven by two gate drive circuits, forming a bilateral drive structure. This ensures high pixel density drive capability and prevents drive signal distortion.

[0214] Figure 6d is a schematic diagram of the structure of a target signal generating circuit 20 in a gate driver circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 6d, the target signal generating circuit in the gate driver circuit may include a shift register circuit 100, a logical operation circuit (Logical Transition Unit) 200, a level shifter circuit (Level Shifter) 300, and a line driver enhancement circuit (Line Driver) 400.

[0215] In an exemplary embodiment, the shift register circuit 100 may be a shift register circuit composed of a D flip-flop (D Flip Flop, abbreviated as DFF). The shift register circuit 100 is connected to the display driver circuit and receives a timing signal generated by the display driver circuit. The timing signal may include a start signal STV and a clock signal CKV. The D flip-flop is configured to shift and register the received timing signal to initially generate a timing sequence that can be shifted row by row. The logic operation circuit 200 is connected to the shift register circuit 100 and is configured to perform a logic operation on the shifted signal to generate a plurality of target timing sequences with different waveforms. The level conversion circuit 300 is connected to the logic operation circuit 200 and is configured to perform voltage domain conversion on the target timing sequence. The row drive enhancement circuit 400 is connected to the level conversion circuit 300 and is configured to enhance the converted signal, thereby enhancing the output capability and outputting the scan signal to the display area.

[0216] In an exemplary embodiment, the pixel driving circuit in the display area includes a first scan signal line S1, a second scan signal line S2, and a third scan signal line S3. The level conversion circuit 300 and the row drive enhancement circuit 400 constitute an output circuit. The output circuit may include three output sub-circuits. Each sub-output circuit may include a level converter and a row drive enhancer. One output sub-circuit is connected to the first scan signal line S1 of a pixel row in the display area and is configured to output a first scan signal to the display area. Another output sub-circuit is connected to the second scan signal line S2 of a pixel row in the display area and is configured to output a second scan signal to the display area. Still another output sub-circuit is connected to the third scan signal line S3 of a pixel row in the display area and is configured to output a third scan signal to the display area.

[0217] In an exemplary embodiment, the first scan signal may be referred to as a write switch (WS) signal, configured to control the on / off switching of a first transistor T1 in a pixel driving circuit. The second scan signal may be referred to as a display switch (DS) signal, configured to control the on / off switching of a second transistor T2 in the pixel driving circuit. The third scan signal may be referred to as a display reset signal (Auto Zero, AZ) signal, configured to control the on / off switching of a fourth transistor T4 in the pixel driving circuit.

[0218] In an exemplary embodiment, since signals such as the start signal and the clock signal are output by the display driver circuit, their voltage domains are inconsistent with the voltage domain of the pixel driver circuit. By converting the level converter in the level conversion circuit 300, the required voltage (0V to -2V & -5V) is introduced, thereby ensuring that the voltage of the output gate drive signal matches that of the pixel driver circuit.

[0219] In an exemplary embodiment, the start signal STV may be referred to as a frame start signal, with a period of one frame, and the clock signal CKV may be referred to as a row driving clock signal, with a period of one row.

[0220] In an exemplary embodiment, the logic operation circuit 200 may include at least a first operation circuit, a second operation circuit, and a third operation circuit, the first operation circuit being configured to generate a write switch signal WS, the second operation circuit being configured to generate a display switch signal DS, and the third operation circuit being configured to generate a display reset signal AZ.

[0221] FIG7 is a diagram illustrating the working principle of a first arithmetic circuit according to an exemplary embodiment of the present disclosure. The first arithmetic circuit may include nine components, namely four inverters (INVX), three NOR gates (NOR), one NAND gate (NAND), and one two-way selector (MUX2). As shown in FIG7 , the first arithmetic circuit may include a first NAND gate 301, a first inverter 401, a second inverter 402, a third inverter 403, a fourth inverter 404, a first NOR gate 501, a second NOR gate 502, a third NOR gate 503, and a two-way selector 510.

[0222] In an exemplary embodiment, a first input terminal of the first NAND gate 301 is connected to the second input terminal B_Qn of the logic operation circuit, a second input terminal of the first NAND gate 30 is connected to the third input terminal C_Qn of the logic operation circuit, an output terminal of the first NAND gate 301 is connected to the input terminal of the first inverter 401, an output terminal of the first inverter 401 is connected to the first input terminal of the first NOR gate 501, a second input terminal of the first NOR gate 501 is connected to the first input terminal IN_A_Qn_ of the logic operation circuit, an output terminal of the first NOR gate 501 is connected to the input terminal of the second inverter 402, an output terminal of the second inverter 402 is connected to the first input terminal of the second NOR gate 502, a second input terminal of the second NOR gate 502 is connected to the clock signal terminal CKV4 of the logic operation circuit, an output terminal of the second NOR gate 502 is connected to the input terminal of the fourth inverter 404, and an output terminal of the fourth inverter 404 is connected to the second input terminal of the two-way selector 510. The input of the third inverter 403 is connected to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The output of the third inverter 403 is connected to the second input terminal of the third NOR gate 503. The first input of the third NOR gate 503 is connected to the first reset terminal IN_LF_pulse1 of the logic operation circuit. The output of the third NOR gate 503 is connected to the control terminal of the two-way selector 510. The first input of the two-way selector 510 is connected to the input terminal IN_A_Qn of the inverted first input signal of the logic operation circuit. The output of the two-way selector 510 serves as the output terminal of the first operation circuit (which can serve as the write switch signal terminal WSn of the logic operation circuit) and is connected to the input terminal of a level shifter (e.g., the first level shifter) to output the write switch signal WSn to the level shifter.

[0223] In an exemplary embodiment, the first operation circuit operates as follows: the first NAND gate 301 and the first inverter 401 perform an AND operation on the second input signal B_Qn at the second input terminal IN_B_Qn and the third input signal C_Qn at the third input terminal IN_C_Qn. The first NOR gate 501 and the second inverter 402 perform an OR operation on the AND operation result and the first input signal A_Qn_ at the first input terminal IN_A_Qn_. The second NOR gate 502 and the fourth inverter 404 perform an OR operation on the OR operation result and the fourth clock signal CKV4 at the fourth clock signal terminal IN_CKV4, i.e., F1 = B_Qn & C_Qn + A_Qn_ + CKV4. The third inverter 403 inverts the second reset signal at the second reset terminal LF_pulse2. The third NOR gate 503 performs a NOR operation on the inverted result and the first reset signal at the first reset terminal LF_pulse1, i.e., F2 serves as a control signal of the two-way selector 510. When F2=1, the output end of the two-way selector 510 outputs A_Qn (ie, the inverted signal of the first input signal A_Qn_); when F2=0, the output end of the two-way selector 510 outputs F1.

[0224] FIG8 is an equivalent circuit diagram of a first operation circuit of an exemplary embodiment of the present disclosure. As shown in FIG8 , in the gate drive circuit of the embodiment of the present disclosure, the first operation circuit of the logic operation circuit may include 30 transistors. Among them, the first inverter 401, the second inverter 402, the third inverter 403, and the fourth inverter 404 each include 1 P-type transistor and 1 N-type transistor, the first NAND gate 301, the first NOR gate 501, the second NOR gate 502, and the third NOR gate 503 each include 2 P-type transistors and 2 N-type transistors, and the two-way selector 510 includes 3 P-type transistors and 3 N-type transistors.

[0225] In an exemplary embodiment, the first NAND gate 301, the first inverter 401, the first NOR gate 501, the second inverter 402, the second NOR gate 502, the fourth inverter 404, the third inverter 403, the third NOR gate 503 and the two-way selector 510 can be arranged in sequence along the first direction X (the direction close to the display area).

[0226] In an exemplary embodiment, a first P-type transistor P1, a first N-type transistor N1, a second P-type transistor P2, and a second N-type transistor N2 form a first NAND gate 301. The gate electrode of the first P-type transistor P1 and the gate electrode of the first N-type transistor N1 are connected to each other and to the third input terminal IN_C_Qn of the logic operation circuit. The gate electrode of the second P-type transistor P2 and the gate electrode of the second N-type transistor N2 are connected to each other and to the second input terminal IN_B_Qn of the logic operation circuit. The first electrode of the first P-type transistor P1 and the first electrode of the second P-type transistor P2 are both connected to the first power supply line VDD. The second electrode of the first P-type transistor P1 and the second electrode of the second P-type transistor P2 are connected to each other and to the second electrode of the second N-type transistor N2, the gate electrode of the third P-type transistor P3, and the gate electrode of the third N-type transistor N3, respectively. The first electrode of the first N-type transistor N1 is connected to the ground line GND, and the second electrode of the first N-type transistor N1 is connected to the first electrode of the second N-type transistor N2.

[0227] In the exemplary embodiment, a third P-type transistor P3 and a third N-type transistor N3 form a first inverter 401. The gate electrode of the third P-type transistor P3 and the gate electrode of the third N-type transistor N3 are connected to each other and are connected to the second electrode of the first P-type transistor P1, the second electrode of the second P-type transistor P2, and the second electrode of the second N-type transistor N2, respectively. A first electrode of the third P-type transistor P3 is connected to the first power supply line VDD, a first electrode of the third N-type transistor N3 is connected to the ground line GND, and a second electrode of the third P-type transistor P3 and the second electrode of the third N-type transistor N3 are connected to each other and are connected to the gate electrode of the fifth P-type transistor P5 and the gate electrode of the fifth N-type transistor N5, respectively.

[0228] In an exemplary embodiment, a fourth P-type transistor P4, a fourth N-type transistor N4, a fifth P-type transistor P5, and a fifth N-type transistor N5 form a first NOR gate 501. The gate electrode of the fourth P-type transistor P4 and the gate electrode of the fourth N-type transistor N4 are connected to each other and to the first input terminal IN_A_Qn of the logic operation circuit. The gate electrode of the fifth P-type transistor P5 and the gate electrode of the fifth N-type transistor N5 are connected to each other and to the second electrode of the third P-type transistor P3 and the second electrode of the third N-type transistor N3, respectively. A first electrode of the fourth P-type transistor P4 is connected to the first power supply line VDD. A second electrode of the fourth P-type transistor P4 is connected to the first electrode of the fifth P-type transistor P5. A first electrode of the fourth N-type transistor N4 and a first electrode of the fifth N-type transistor N5 are both connected to the ground line GND. A second electrode of the fourth N-type transistor N4 and a second electrode of the fifth N-type transistor N5 are connected to each other and to the second electrode of the fifth P-type transistor P5, the gate electrode of the sixth P-type transistor P6, and the gate electrode of the sixth N-type transistor N6, respectively.

[0229] In an exemplary embodiment, the sixth P-type transistor P6 and the sixth N-type transistor N6 constitute the second inverter 402. The gate electrode of the sixth P-type transistor P6 and the gate electrode of the sixth N-type transistor N6 are connected to each other and are respectively connected to the second electrode of the fifth P-type transistor P5, the second electrode of the fourth N-type transistor N4, and the second electrode of the fifth N-type transistor N5. A first electrode of the sixth P-type transistor P6 is connected to the first power supply line VDD, a first electrode of the sixth N-type transistor N6 is connected to the ground line GND, and a second electrode of the sixth P-type transistor P6 and the second electrode of the sixth N-type transistor N6 are connected to each other and are respectively connected to the gate electrode of the eighth P-type transistor P8 and the gate electrode of the eighth N-type transistor N8.

[0230] In an exemplary embodiment, a seventh P-type transistor P7, a seventh N-type transistor N7, an eighth P-type transistor P8, and an eighth N-type transistor N8 form a second NOR gate 502. The gate electrode of the seventh P-type transistor P7 and the gate electrode of the seventh N-type transistor N7 are connected to each other and to the clock signal terminal CKV4 of the logic operation circuit. The gate electrode of the eighth P-type transistor P8 and the gate electrode of the eighth N-type transistor N8 are connected to each other and to the second electrode of the sixth P-type transistor P6 and the second electrode of the sixth N-type transistor N6, respectively. A first electrode of the seventh P-type transistor P7 is connected to the first power supply line VDD. A second electrode of the seventh P-type transistor P7 is connected to the first electrode of the eighth P-type transistor P8. A first electrode of the seventh N-type transistor N7 and a first electrode of the eighth N-type transistor N8 are both connected to the ground line GND. A second electrode of the seventh N-type transistor N7 and a second electrode of the eighth N-type transistor N8 are connected to each other and to the second electrode of the eighth P-type transistor P8, the gate electrode of the ninth P-type transistor P9, and the gate electrode of the ninth N-type transistor N9, respectively.

[0231] In an exemplary embodiment, a ninth P-type transistor P9 and a ninth N-type transistor N9 form a fourth inverter 404. The gate electrode of the ninth P-type transistor P9 and the gate electrode of the ninth N-type transistor N9 are connected to each other and are connected to the second electrode of the seventh N-type transistor N7, the second electrode of the eighth N-type transistor N8, and the second electrode of the eighth P-type transistor P8, respectively. A first electrode of the ninth P-type transistor P9 is connected to the first power supply line VDD, a first electrode of the ninth N-type transistor N9 is connected to the ground line GND, and a second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9 are connected to each other and are connected to the first electrode of the fifteenth P-type transistor P15 and the first electrode of the fifteenth N-type transistor N15, respectively.

[0232] In an exemplary embodiment, the tenth P-type transistor P10 and the tenth N-type transistor N10 form a third inverter 403. The gate electrode of the tenth P-type transistor P10 and the gate electrode of the tenth N-type transistor N10 are connected to each other and to the second reset terminal IN_LF_pulse2 of the logic operation circuit. The first electrode of the tenth P-type transistor P10 is connected to the first power supply line VDD, the first electrode of the tenth N-type transistor N10 is connected to the ground line GND, and the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10 are connected to each other and to the gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11, respectively.

[0233] In an exemplary embodiment, the eleventh P-type transistor P11, the eleventh N-type transistor N11, the twelfth P-type transistor P12, and the twelfth N-type transistor N12 constitute a third NOR gate 503. The gate electrode of the eleventh P-type transistor P11 and the gate electrode of the eleventh N-type transistor N11 are connected to each other and to the second electrode of the tenth P-type transistor P10 and the second electrode of the tenth N-type transistor N10, respectively. The gate electrode of the twelfth P-type transistor P12 and the gate electrode of the twelfth N-type transistor N12 are connected to each other and to the first reset terminal IN_LF_pulse1 of the logic operation circuit. The first electrode of the eleventh P-type transistor P11 is connected to the first power line VDD, and the second electrode of the eleventh P-type transistor P11 is connected to the first reset terminal IN_LF_pulse1 of the logic operation circuit. The first electrode of the twelfth P-type transistor P12 is connected, the first electrode of the eleventh N-type transistor N11 and the first electrode of the twelfth N-type transistor N12 are both connected to the ground line GND, the second electrode of the eleventh N-type transistor N11 and the second electrode of the twelfth N-type transistor N12 are connected to each other, and are respectively connected to the second electrode of the twelfth P-type transistor P12, the gate electrode of the thirteenth P-type transistor P13, the gate electrode of the thirteenth N-type transistor N13, the gate electrode of the fourteenth N-type transistor N14 and the gate electrode of the fifteenth P-type transistor P15.

[0234] In an exemplary embodiment, the thirteenth P-type transistor P13, the thirteenth N-type transistor N13, the fourteenth P-type transistor P14, the fourteenth N-type transistor N14, the fifteenth P-type transistor P15, and the fifteenth N-type transistor N15 constitute a two-way selector 510. The gate electrode of the thirteenth P-type transistor P13 and the gate electrode of the thirteenth N-type transistor N13 are connected to each other, and are respectively connected to the second electrode of the eleventh N-type transistor N11, the second electrode of the twelfth N-type transistor N12, the second electrode of the twelfth P-type transistor P12, the gate electrode of the fourteenth N-type transistor N14, and the gate electrode of the fifteenth P-type transistor P15. A first electrode of the thirteenth P-type transistor P13 is connected to the first power supply line VDD, a first electrode of the thirteenth N-type transistor N13 is connected to the ground line GND, a second electrode of the thirteenth P-type transistor P13 and the second electrode of the thirteenth N-type transistor N13 are connected to each other, and are respectively connected to the gate electrode of the fourteenth P-type transistor P14 and the gate electrode of the fifteenth N-type transistor N15. The first electrode of the fourth N-type transistor N14 is connected to the first electrode of the fourth N-type transistor N14, and is connected to the first input terminal A_Qn of the logic operation circuit. The first electrode of the fifteenth P-type transistor P15 and the first electrode of the fifteenth N-type transistor N15 are connected to each other, and are respectively connected to the second electrode of the ninth P-type transistor P9 and the second electrode of the ninth N-type transistor N9. The second electrode of the fourteenth P-type transistor P14, the second electrode of the fourteenth N-type transistor N14, the second electrode of the fifteenth P-type transistor P15, and the second electrode of the fifteenth P-type transistor P15 are connected to each other and serve as the output terminal OUT_WS of the first operation circuit (that is, the output terminal of the output write switch signal OUT_WSn in Figure 7, which can be used as the write switch signal terminal OUT_WSn of the logic operation circuit).

[0235] Figure 9a is a schematic diagram of the working principle of a second arithmetic circuit according to an exemplary embodiment of the present disclosure. The second arithmetic circuit may include nine parts, namely six inverters, one NOR gate, one NAND gate, and one latch (D-Latch). As shown in Figure 9, the second arithmetic circuit may include a second NAND gate 302, a fifth inverter 405, a sixth inverter 406, a seventh inverter 407, an eighth inverter 408, a ninth inverter 409, a tenth inverter 410, a fourth NOR gate 504, and a latch 520.

[0236] In an exemplary embodiment, an input terminal of the fifth inverter 405 is connected to a write switch signal terminal WSn of the logic operation circuit, an output terminal of the fifth inverter 405 is connected to an input terminal of the sixth inverter 406, an output terminal of the sixth inverter 406 is connected to an input terminal of the seventh inverter 407, an output terminal of the seventh inverter 407 is connected to an input terminal of the eighth inverter 408, an output terminal of the eighth inverter 408 is connected to an input terminal of the ninth inverter 409, an output terminal of the ninth inverter 409 is connected to an input terminal of the tenth inverter 410, an output terminal of the tenth inverter 410 is connected to an enable signal terminal EN of a latch 520, and an input terminal of the latch 520 is connected to a second input terminal IN_B_Q of the logic operation circuit. n, the output of the latch 520 is connected to the second input of the fourth NOR gate 504, the first input of the fourth NOR gate 504 is connected to the duty control terminal IN_D_Qn of the logic operation circuit, the output of the fourth NOR gate 504 is connected to the first input of the second NAND gate 302, the second input of the second NAND gate 302 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, and the output of the second NAND gate 302 serves as the output terminal OUT_DS of the second operation circuit and the display switch signal terminal OUT_DSn, and is connected to the display switch control terminal DS of the at least one pixel driving circuit, outputting the display switch signal to the display switch control terminal DS of the at least one pixel driving circuit. In an exemplary embodiment, the output of the second NAND gate 302 can be connected to the input of another level shifter (e.g., a second level shifter), outputting the display switch signal DSn to the level shifter. The level shifter performs level shifting on the display switch signal DSn and outputs it to the corresponding row driver booster (e.g., the second row driver booster). After the row driver booster performs signal amplification, the signal is output to the display switch control terminal of the corresponding pixel driving circuit.

[0237] In an exemplary embodiment, the operating principle of the second operation circuit is as follows: the fifth inverter 405 to the tenth inverter 410 delay the signal written to the switch signal terminal OUT_WSn and then input it to the enable signal terminal EN of the latch 520, which serves as the enable signal of the latch 520. The second input signal of the second input terminal IN_B_Qn of the logic operation circuit serves as the input signal of the latch 520. When the enable signal at the enable signal terminal EN is low, the output of the latch 520 remains unchanged. When the enable signal at the enable signal terminal EN is high, the output of the latch 520 changes with the second input signal. Subsequently, the fourth NOR gate 504 performs a NOR operation on the duty control signal D_Qn at the duty control terminal IN_D_Qn and the signal at the first output terminal OUT_Q of the latch 520. The second NAND gate 302 performs a NAND operation on the NOR operation result and the second reset signal at the second reset terminal LF_pulse2. The logical expression is: Where Q is the output signal of latch 520 (when the enable signal EN input to the enable signal terminal of latch 520 is high, Q = B_Qn; when the enable signal EN input to the enable signal terminal of latch 520 is low, the signal output from output terminal Q remains the original output signal; under normal operation, the enable signal EN input to the enable signal terminal of latch 520 is high, Q = B_Qn). LF_pulse2 is the reset signal. Under normal operation, LF_pulse2 = 1, and DSn = D_Qn + Q. When a global reset is required, LF_pulse2 = 0, and the output signal DSn of the second arithmetic circuit is high (i.e., DSn = 1). D_Qn is the emission duty control signal. When the emission duty is 100%, D_Qn remains low, and DSn = Q. To adjust the emission duty, the duty cycle of D_Qn can be adjusted.

[0238] As shown in FIG9b, a working principle diagram of a latch 520 according to an exemplary embodiment of the present disclosure is shown. The latch 520 includes one inverter and four NAND gates. As shown in FIG9b, the latch 520 includes a twenty-first NAND gate 521, a twenty-second NAND gate 522, a twenty-third NAND gate 523, a twenty-fourth NAND gate 524, and a twenty-fifth inverter 525. The first input terminal of the twenty-first NAND gate 521 is connected to the second input terminal B_Qn of the logic operation circuit, the second input terminal of the twenty-first NAND gate 521 is connected to the enable signal terminal EN, the output terminal of the twenty-first NAND gate 521 is connected to the first input terminal of the twenty-second NAND gate 522, and the second input terminal of the twenty-second NAND gate 522 is connected to the second input terminal of the latch 520. The output terminal OUT_Q_ is connected, and the output terminal of the twenty-second NAND gate 522 serves as the first output terminal Q of the latch 520; the input terminal of the twenty-fifth inverter 525 is connected to the second input terminal IN_B_Qn of the logic operation circuit, the output terminal of the twenty-fifth inverter 525 is connected to the first input terminal of the twenty-third NAND gate 523, the second input terminal of the twenty-third NAND gate 523 is connected to the enable signal terminal EN, the output terminal of the twenty-third NAND gate 523 is connected to the second input terminal of the twenty-fourth NAND gate 524, the first input terminal of the twenty-fourth NAND gate 524 is connected to the first output terminal OUT_Q of the latch 520, and the output terminal of the twenty-fourth NAND gate 524 serves as the second output terminal OUT_Q_ of the latch 520. As shown in Figure 9c, it is a working timing diagram of the latch provided in an embodiment of the present disclosure (the horizontal axis in Figure 9c is time, the unit is microseconds; the vertical axis is voltage, the unit is volt V); in Figure 9b, the signal of the first node B1 is the result of the NAND operation obtained by performing a NAND operation on the second input signal B_Qn and the enable signal EN, the signal of the second node B2 is the result of the NAND operation obtained by performing a NAND operation on the second input signal B_Qn after being inverted by the inverter and the enable signal EN, the output signal Q is the result of the NAND operation obtained by performing a NAND operation on the signal of the first node B1 and the signal of the output terminal OUT_Q_, and the output signal Q_ is the result of the NAND operation obtained by performing a NAND operation on the signal of the second node B2 and the signal of the output terminal Q.

[0239] As shown in FIG9c , in the first stage t1, the enable signal EN is a high-level signal and the second input signal B_Qn is a low-level signal. The signal of the first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a high-level signal. The signal of the second node B2 obtained by performing a NAND operation on the second input signal B_Qn after inverting the second input signal B_Qn and performing a NAND operation on the enable signal EN is a low-level signal. The signal of the second node B2 and the signal of the first output terminal OUT_Q obtained by performing a NAND operation on the second output terminal OUT_Q is a high-level signal. Since the signals of the first node B1 and the second output terminal OUT_Q_ are both high-level, the signal of the first output terminal OUT_Q obtained by performing a NAND operation on the signal of the first node B1 and the signal of the second output terminal OUT_Q_ is a low-level signal. In the second stage t2, the enable signal EN is a low-level signal and the second input signal B_Qn changes from a low-level signal to a high-level signal. Since the enable signal EN is a low-level signal, the first node B1 and the second node B2 are both high-level signals. The first output terminal OUT_Q maintains the low level of the previous stage, and the second output terminal OUT_Q_ maintains the high level signal of the previous stage; in the third stage t3, the enable signal EN and the second input signal B_Qn are both high level signals, the first node B1 obtained by performing a NAND operation on the enable signal EN and the second input signal B_Qn is a low level signal, the signal of the first node B1 and the signal of the second output terminal OUT_Q_ are performed a NAND operation to obtain the first output terminal OUT_Q is a high level signal, the second input signal B_Qn is inverted and performed a NAND operation on the enable signal EN to obtain the second node B2 is a high level signal, the second section The second output terminal OUT_Q_ obtained by performing a NAND operation on the signal at point B2 and the signal at the first output terminal OUT_Q is a low-level signal; the timing of the fourth stage t4 and the sixth stage t6 is the same as that of the second stage t2, the timing of the fifth stage t5 and the seventh stage t7 is the same as that of the third stage t3, and the timing of the eighth stage t8 and the tenth stage t10 is the same as that of the first stage t1; in the ninth stage t9 and the eleventh stage t11, the second input signal B_Qn changes from a high-level signal to a low-level signal, and the timing of other signals is the same as that of the second stage t2.

[0240] As can be seen from FIG9b and FIG9c, the latch 520 has the following three states in total. The first state: the enable signal EN is at a high level (1), the second input signal B_Qn is a low level signal (0), the signal of the first node B1 is at a high level, the signal of the second node B2 is at a low level, the signal of the second output terminal Q_ is a high level signal, and the signal of the first output terminal OUT_Q is a low level signal (called a latch set 0 operation); the second state: the enable signal EN is at a low level (0), the second input signal B_Qn is any signal (high level or low level), the first node B 1 and the signals of the second node B2 are both high level, the second output terminal OUT_Q_ and the first output terminal Q maintain the original output signal and do not change with the change of the second input signal B_Qn (called the holding stage, the stage of latching 1-bit binary number); the third state: the enable signal EN is high level (1), the second input signal B_Qn is a high level signal (1), the signal of the first node B1 is low level, the signal of the second node B2 is high level, the signal of the first output terminal Q is a high level signal (latch set 1 stage), and the signal of the second output terminal OUT_Q_ is a low level signal.

[0241] The D latch 520 in FIG9a primarily functions to prevent the high level of the display switch signal DSn from enclosing the first low level of the write switch signal WSn (i.e., the first low level of the write switch signal WSn at least partially overlaps with the high level of the display switch signal DSn). If the high level of the display switch signal DSn shifts forward to enclose the first low level of the write switch signal WSn, the time for writing the first power supply voltage at the second node N2 of the pixel driver circuit and the time for writing the bias voltage Vofs at the first node N1 of the pixel driver circuit will be shortened, resulting in incomplete initialization. If the first low level of the write switch signal WSn shifts backward to enclose the high level of the display switch signal DSn, the self-discharge time of the pixel driver circuit will be shortened, resulting in inaccurate threshold voltage readings. The D latch 520 operates normally only when the enable signal EN input to the enable signal terminal EN of the latch 520 is at a high level (i.e., EN=1). If the enable signal at the enable signal terminal EN is not at a high level (e.g., EN=0), the latch state is indeterminate, and the signal output from the first output terminal Q of the latch 520 is indeterminate.

[0242] FIG10 is an equivalent circuit diagram of a second operation circuit of an exemplary embodiment of the present disclosure. As shown in FIG10 , in the gate drive circuit of the embodiment of the present disclosure, the second operation circuit of the logic operation circuit may include 38 transistors. Among them, the second NAND gate 302 includes 2 P-type transistors and 2 N-type transistors, the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, and the tenth inverter 410 each include 1 P-type transistor and 1 N-type transistor, the fourth NOR gate 504 includes 2 P-type transistors and 2 N-type transistors, and the latch 520 includes 9 P-type transistors and 9 N-type transistors.

[0243] In an exemplary embodiment, the fifth inverter 405, the sixth inverter 406, the seventh inverter 407, the eighth inverter 408, the ninth inverter 409, the tenth inverter 410, the latch 520, the fourth NOR gate 504 and the second NAND gate 302 can be arranged in sequence along the first direction X (the direction close to the display area in the display substrate).

[0244] In the exemplary embodiment, the twenty-first P-type transistor P21 and the twenty-first N-type transistor N21 constitute a fifth inverter 405. The gate electrode of the twenty-first P-type transistor P21 and the gate electrode of the twenty-first N-type transistor N21 are connected to each other and to the write switch signal terminal OUT_WSn of the logic operation circuit. A first electrode of the twenty-first P-type transistor P21 is connected to the first power supply line VDD, a first electrode of the twenty-first N-type transistor N21 is connected to the ground line GND, and a second electrode of the twenty-first P-type transistor P21 and the second electrode of the twenty-first N-type transistor N21 are connected to each other and to the gate electrode of the twenty-second P-type transistor P22 and the gate electrode of the twenty-second N-type transistor N22, respectively.

[0245] In the exemplary embodiment, the twenty-second P-type transistor P22 and the twenty-second N-type transistor N22 constitute the sixth inverter 406. The gate electrode of the twenty-second P-type transistor P22 and the gate electrode of the twenty-second N-type transistor N22 are connected to each other and to the second electrode of the twenty-first P-type transistor P21 and the second electrode of the twenty-first N-type transistor N21, respectively. The first electrode of the twenty-second P-type transistor P22 is connected to the first power supply line VDD, the first electrode of the twenty-second N-type transistor N22 is connected to the ground line GND, the second electrode of the twenty-second P-type transistor P22 and the second electrode of the twenty-second N-type transistor N22 are connected to each other and to the gate electrode of the twenty-third P-type transistor P23 and the gate electrode of the twenty-third N-type transistor N23, respectively.

[0246] In the exemplary embodiment, the twenty-third P-type transistor P23 and the twenty-third N-type transistor N23 constitute the seventh inverter 407. The gate electrode of the twenty-third P-type transistor P23 and the gate electrode of the twenty-third N-type transistor N23 are connected to each other and to the second electrode of the twenty-second P-type transistor P22 and the second electrode of the twenty-second N-type transistor N22, respectively. A first electrode of the twenty-third P-type transistor P23 is connected to the first power supply line VDD, a first electrode of the twenty-third N-type transistor N23 is connected to the ground line GND, and a second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23 are connected to each other and to the gate electrode of the twenty-fourth P-type transistor P24 and the gate electrode of the twenty-fourth N-type transistor N24, respectively.

[0247] In the exemplary embodiment, the twenty-fourth P-type transistor P24 and the twenty-fourth N-type transistor N24 constitute the eighth inverter 408. The gate electrode of the twenty-fourth P-type transistor P24 and the gate electrode of the twenty-fourth N-type transistor N24 are connected to each other and to the second electrode of the twenty-third P-type transistor P23 and the second electrode of the twenty-third N-type transistor N23, respectively. The first electrode of the twenty-fourth P-type transistor P24 is connected to the first power supply line VDD, the first electrode of the twenty-fourth N-type transistor N24 is connected to the ground line GND, the second electrode of the twenty-fourth P-type transistor P24 and the second electrode of the twenty-fourth N-type transistor N24 are connected to each other and to the gate electrode of the twenty-fifth P-type transistor P25 and the gate electrode of the twenty-fifth N-type transistor N25, respectively.

[0248] In the exemplary embodiment, the twenty-fifth P-type transistor P25 and the twenty-fifth N-type transistor N25 constitute a ninth inverter 409. The gate electrode of the twenty-fifth P-type transistor P25 and the gate electrode of the twenty-fifth N-type transistor N25 are connected to each other and to the second electrode of the twenty-fourth P-type transistor P24 and the second electrode of the twenty-fourth N-type transistor N24, respectively. A first electrode of the twenty-fifth P-type transistor P25 is connected to the first power supply line VDD, a first electrode of the twenty-fifth N-type transistor N25 is connected to the ground line GND, and a second electrode of the twenty-fifth P-type transistor P25 and the second electrode of the twenty-fifth N-type transistor N25 are connected to each other and to the gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26, respectively.

[0249] In the exemplary embodiment, the twenty-sixth P-type transistor P26 and the twenty-sixth N-type transistor N26 constitute the tenth inverter 410. The gate electrode of the twenty-sixth P-type transistor P26 and the gate electrode of the twenty-sixth N-type transistor N26 are connected to each other and to the second electrode of the twenty-fifth P-type transistor P25 and the second electrode of the twenty-fifth N-type transistor N25, respectively. A first electrode of the twenty-sixth P-type transistor P26 is connected to the first power supply line VDD, a first electrode of the twenty-sixth N-type transistor N26 is connected to the ground line GND, and a second electrode of the twenty-sixth P-type transistor P26 and the second electrode of the twenty-sixth N-type transistor N26 are connected to each other and to the gate electrode of the twenty-ninth P-type transistor P29, the gate electrode of the twenty-ninth N-type transistor N29, the gate electrode of the thirty-second P-type transistor P32, and the gate electrode of the thirty-second N-type transistor N32, respectively.

[0250] In an exemplary embodiment, the twenty-seventh to thirty-fifth P-type transistors P27 to P35 and the twenty-seventh to thirty-fifth N-type transistors N27 to N35 constitute the latch 520 .

[0251] In an exemplary embodiment, the gate electrode of the twenty-seventh P-type transistor P27 and the gate electrode of the twenty-seventh N-type transistor N27 are interconnected and respectively connected to the second input terminal B_Qn of the logic operation circuit, the gate electrode of the thirty-third P-type transistor P33 and the gate electrode of the thirty-third N-type transistor N33, the first electrode of the twenty-seventh P-type transistor P27 is connected to the first power supply line VDD, the first electrode of the twenty-seventh N-type transistor N27 is connected to the ground line GND, the second electrode of the twenty-seventh P-type transistor P27 and the second electrode of the twenty-seventh N-type transistor N27 are interconnected and respectively connected to the gate electrode of the twenty-eighth P-type transistor P28 and the gate electrode of the twenty-eighth N-type transistor N28.

[0252] In the exemplary embodiment, the gate electrode of the twenty-eighth P-type transistor P28 and the gate electrode of the twenty-eighth N-type transistor N28 are connected to each other and are respectively connected to the second electrode of the twenty-seventh P-type transistor P27 and the second electrode of the twenty-seventh N-type transistor N27. The gate electrode of the twenty-ninth P-type transistor P29 and the gate electrode of the twenty-ninth N-type transistor N29 are connected to each other and are respectively connected to the second electrode of the twenty-sixth P-type transistor P26, the second electrode of the twenty-sixth N-type transistor N26, the gate electrode 232P of the thirty-second P-type transistor P32, and the gate electrode of the thirty-second N-type transistor N32. In addition, the first electrode of the twenty-eighth P-type transistor P28 and the first electrode of the twenty-ninth P-type transistor P29 are both connected to the first power supply line VDD, the second electrode of the twenty-eighth P-type transistor P28 and the second electrode of the twenty-ninth P-type transistor P29 are connected to each other, and are respectively connected to the second electrode of the twenty-eighth N-type transistor N28, the gate electrode of the thirtieth P-type transistor P30 and the gate electrode of the thirtieth N-type transistor N30, the first electrode of the twenty-ninth N-type transistor N29 is connected to the ground line GND, and the second electrode of the twenty-ninth N-type transistor N29 is connected to the first electrode of the twenty-eighth N-type transistor N28.

[0253] In the exemplary embodiment, the gate electrode of the 30th P-type transistor P30 and the gate electrode of the 30th N-type transistor N30 are connected to each other and are respectively connected to the second electrode of the 28th P-type transistor P28, the second electrode of the 28th N-type transistor N28, and the second electrode of the 29th P-type transistor P29. The gate electrode of the 31st P-type transistor P31 and the gate electrode of the 31st N-type transistor N31 are connected to each other and are respectively connected to the second electrode of the 34th P-type transistor P34, the second electrode of the 34th N-type transistor N34, the second electrode of the 35th P-type transistor P35, the gate electrode of the 36th P-type transistor P36, and the gate electrode of the 37th P-type transistor P37. The gate electrode of the sixteenth N-type transistor N36 is connected, the first electrode of the thirtieth P-type transistor P30 and the first electrode of the thirty-first P-type transistor P31 are both connected to the first power supply line VDD, the second electrode of the thirtieth P-type transistor P30 and the second electrode of the thirty-first P-type transistor P31 are connected to each other, and are respectively connected to the second electrode of the thirty-first N-type transistor N31, the gate electrode of the thirty-fifth P-type transistor P35 and the gate electrode of the thirty-fifth N-type transistor N35, the first electrode of the thirtieth N-type transistor N30 is connected to the ground line GND, and the second electrode of the thirtieth N-type transistor N30 is connected to the first electrode of the thirty-first N-type transistor N30.

[0254] In an exemplary embodiment, the gate electrode of the thirty-second P-type transistor P32 and the gate electrode of the thirty-second N-type transistor N32 are connected to each other and are respectively connected to the second electrode of the twenty-sixth P-type transistor P26, the second electrode of the twenty-sixth N-type transistor N26, the gate electrode of the twenty-ninth P-type transistor P29 and the gate electrode of the twenty-ninth N-type transistor N29, the gate electrode of the thirty-third P-type transistor P33 and the gate electrode of the thirty-third N-type transistor N33 are connected to each other and are respectively connected to the second input terminal NI_B_Qn of the logic operation circuit, the gate electrode of the twenty-seventh P-type transistor P27 and the gate electrode of the twenty-seventh N-type transistor N27. The first electrode of the thirty-second P-type transistor P32 and the first electrode of the thirty-third P-type transistor P33 are both connected to the first power supply line VDD, the second electrode of the thirty-second P-type transistor P32 and the second electrode of the thirty-third P-type transistor P33 are connected to each other, and are respectively connected to the second electrode of the thirty-third N-type transistor N33, the gate electrode of the thirty-fourth P-type transistor P34 and the gate electrode of the thirty-fourth N-type transistor N34, the first electrode of the thirty-second N-type transistor N32 is connected to the ground line GND, and the second electrode of the thirty-second N-type transistor N32 is connected to the first electrode of the thirty-third N-type transistor N33.

[0255] In the exemplary embodiment, the gate electrode of the thirty-fourth P-type transistor P34 and the gate electrode of the thirty-fourth N-type transistor N34 are connected to each other and are respectively connected to the second electrode of the thirty-second P-type transistor P32, the second electrode of the thirty-third P-type transistor P33, and the second electrode of the thirty-third N-type transistor N33; the gate electrode of the thirty-fifth P-type transistor P35 and the gate electrode of the thirty-fifth N-type transistor N35 are connected to each other and are respectively connected to the second electrode of the thirtieth P-type transistor P30, the second electrode of the thirty-first P-type transistor P31, and the second electrode of the thirty-first N-type transistor N31; the first electrode of the thirty-fourth P-type transistor P34 and the second electrode of the thirty-second P-type transistor P32 are respectively connected to the second electrode of the thirty-second P-type transistor P32, the second electrode of the thirty-third P-type transistor P33, and the second electrode of the thirty-third N-type transistor N33; The first electrodes of the fifteen P-type transistors P35 are all connected to the first power supply line VDD, the second electrode of the thirty-fourth P-type transistor P34 and the second electrode of the thirty-fifth P-type transistor P35 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth N-type transistor N34, the gate electrode of the thirty-first P-type transistor P31, the gate electrode of the thirty-first N-type transistor N31, the gate electrode of the thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36, the first electrode of the thirty-fifth N-type transistor N35 is connected to the ground line GND, and the second electrode of the thirty-fifth N-type transistor N35 is connected to the first electrode of the thirty-fourth N-type transistor N34.

[0256] In the exemplary embodiment, the thirty-sixth P-type transistor P36, the thirty-sixth N-type transistor N36, the thirty-seventh P-type transistor P37, and the thirty-seventh N-type transistor N37 constitute a fourth NOR gate 504. The gate electrode of the thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth P-type transistor P34, the second electrode of the thirty-fourth N-type transistor N34, the second electrode of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-first P-type transistor P31, and the gate electrode of the thirty-first N-type transistor N31. The gate electrode of the thirty-seventh P-type transistor P37 and the gate electrode of the thirty-seventh N-type transistor N37 are connected to each other and are connected to the ratio control terminal D_Qn of the logic operation circuit. The thirty-sixth P-type transistor P36 and the gate electrode of the thirty-sixth N-type transistor N36 are connected to each other, and are respectively connected to the second electrode of the thirty-fourth P-type transistor P34, the second electrode of the thirty-fourth N-type transistor N34, the second electrode of the thirty-fifth P-type transistor P35, the gate electrode of the thirty-first P-type transistor P31, and the gate electrode of the thirty-first N-type transistor N31. The gate electrode of the thirty-seventh P-type transistor P37 and the gate electrode of the thirty-seventh N-type transistor N37 are connected to each other, and are connected to the ratio control terminal D_Qn of the logic operation circuit. The first electrode of the thirty-sixth P-type transistor P36 is connected to the first power supply line VDD, the second electrode of the thirty-sixth P-type transistor P36 is connected to the first electrode of the thirty-seventh P-type transistor P37, the first electrode of the thirty-sixth N-type transistor N36 and the first electrode of the thirty-seventh N-type transistor N37 are both connected to the ground line GND, the second electrode of the thirty-sixth N-type transistor N36 and the second electrode of the thirty-seventh N-type transistor N37 are connected to each other, and are respectively connected to the second electrode of the thirty-seventh P-type transistor P37, the gate electrode of the thirty-ninth P-type transistor P39 and the gate electrode of the thirty-ninth N-type transistor N39.

[0257] In an exemplary embodiment, the thirty-eighth P-type transistor P38 , the thirty-eighth N-type transistor N38 , the thirty-ninth P-type transistor P39 , and the thirty-ninth N-type transistor N39 constitute the second NAND gate 302 . The gate electrode of the thirty-eighth P-type transistor P38 and the gate electrode of the thirty-eighth N-type transistor N38 are connected to each other and to the second reset terminal LF_pulse2 of the logic operation circuit. The gate electrode of the thirty-ninth P-type transistor P39 and the gate electrode of the thirty-ninth N-type transistor N39 are connected to each other and to the second electrode of the thirty-sixth N-type transistor N36, the second electrode of the thirty-seventh P-type transistor P37, and the second electrode of the thirty-seventh N-type transistor N37, respectively. The first electrode of the thirty-eighth P-type transistor P38 and the first electrode of the thirty-ninth P-type transistor P39 are both connected to the first power supply line VDD, the first electrode of the thirty-ninth N-type transistor N39 is connected to the ground line GND, the second electrode of the thirty-ninth N-type transistor N39 is connected to the first electrode of the thirty-eighth N-type transistor N38, the second electrode of the thirty-eighth P-type transistor P38, the second electrode of the thirty-eighth N-type transistor N38, and the second electrode of the thirty-ninth P-type transistor P39 are connected to each other and serve as the output terminal OUT_DS of the second operation circuit (i.e., the output terminal of the output display switch signal DSn in Figure 9, which can serve as the display switch signal terminal DSn of the logic operation circuit).

[0258] Figure 11 is a schematic diagram illustrating the operation of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. The third arithmetic circuit may include two components: a NOR gate and a NAND gate. As shown in Figure 9 , the third arithmetic circuit may include a fifth NOR gate 505 and a third NAND gate 303.

[0259] In an exemplary embodiment, a first input terminal of the fifth NOR gate 505 is connected to the third input terminal C_Qn of the logic operation circuit, a second input terminal of the fifth NOR gate 505 is connected to the second input terminal B_Qn of the logic operation circuit, a third input terminal of the fifth NOR gate 505 is connected to the duty control terminal D_Qn of the logic operation circuit, an output terminal of the fifth NOR gate 505 is connected to the first input terminal of the third NAND gate 303, a second input terminal of the third NAND gate 303 is connected to the second reset terminal LF_pulse2 of the logic operation circuit, and an output terminal of the third NAND gate 303 serves as the output terminal OUT_AZ of the third operation circuit and as the display reset signal terminal AZn of the logic operation circuit, and is connected to the display reset control terminal AZ in at least one pixel driving circuit, and outputs a display reset signal to the display reset control terminal AZ in the at least one pixel driving circuit. In an exemplary embodiment, the output end of the third NAND gate 303 can be connected to the input end of another level converter (e.g., a third level converter), and a display reset signal is output to the level converter. The level converter converts the display reset signal into a voltage domain and outputs the signal to a corresponding row driver enhancer (e.g., a third row driver enhancer). The row driver enhancer enhances the converted signal and outputs the signal to a display reset control terminal AZ in a corresponding pixel driver circuit.

[0260] In an exemplary embodiment, the operating principle of the third operation circuit is as follows: the fifth NOR gate 505 performs a NOR operation on the third input signal of the third input terminal IN_C_Qn, the second input signal of the second input terminal IN_B_Qn, and the duty control signal of the duty control terminal IN_D_Qn, and the third NAND gate 303 performs a NAND operation on the NOR operation result and the second reset signal of the second reset terminal IN_LF_pulse2. The logical expression thereof is: Among them, LF_pulse2 is the initialization signal, which maintains a high level under normal working conditions (i.e., LF_pulse2=1), then AZn=B_Qn+C_Qn+D_Qn. When LF_pulse2 is a low level (i.e., LF_pulse2=0), then AZn=1, and AZn outputs a high level. When the luminous time accounts for 100%, D_Qn remains at a low level, then AZn=B_Qn+C_Qn. When it is necessary to adjust the luminous time proportion, it can be done by adjusting the duty cycle of D_Qn. That is, the duty cycle control signal of the duty cycle control terminal D_Qn can simultaneously affect the write switch signal DSn and the display reset signal AZn, and the write switch signal DSn and the display reset signal AZn can be simultaneously controlled by the duty cycle control signal of the duty cycle control terminal D_Qn, thereby adjusting and controlling the luminous time proportion of the luminous stage.

[0261] Figure 12 is an equivalent circuit diagram of a third arithmetic circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 12, the third arithmetic circuit of the logic arithmetic circuit of the gate driver circuit in the display substrate of the present embodiment may include 10 transistors. The fifth NOR gate 505 includes three P-type transistors and three N-type transistors, and the third NAND gate 303 includes two P-type transistors and two N-type transistors.

[0262] In an exemplary embodiment, the fifth NOR gate 505 and the third NAND gate 303 may be sequentially disposed along the first direction X (a direction approaching the display area).

[0263] In an exemplary embodiment, the forty-first P-type transistor P41 , the forty-first N-type transistor N41 , the forty-second P-type transistor P42 , the forty-second N-type transistor N42 , the forty-third P-type transistor P43 , and the forty-third N-type transistor N43 constitute a fifth NOR gate 505 . The gate electrode of the forty-first P-type transistor P41 and the gate electrode of the forty-first N-type transistor N41 are connected to each other and to the proportion control terminal IN_D_Qn of the logic operation circuit. The gate electrode of the forty-second P-type transistor P42 and the gate electrode of the forty-second N-type transistor N42 are connected to each other and to the second input terminal B_Qn of the logic operation circuit. The gate electrode of the forty-third P-type transistor P43 and the gate electrode of the forty-third N-type transistor N43 are connected to each other and to the third input terminal IN_C_Qn of the logic operation circuit. The first electrode of the forty-first P-type transistor P41 is connected to the first power line VDD. The second electrode of the forty-first P-type transistor P41 is connected to the first electrode of the forty-second P-type transistor P42. The second electrode of the forty-second P-type transistor P42 is connected to the forty-third P-type transistor P43. The first electrode of the forty-first N-type transistor N41, the first electrode of the forty-second N-type transistor N42 and the first electrode of the forty-third N-type transistor N43 are all connected to the ground line GND, the second electrode of the forty-first N-type transistor N41, the second electrode of the forty-second N-type transistor N42 and the second electrode of the forty-third N-type transistor N43 are connected to each other and are respectively connected to the second electrode of the forty-third P-type transistor P43, the gate electrode of the forty-fifth P-type transistor P45 and the gate electrode of the forty-fifth N-type transistor N45.

[0264] In the exemplary embodiment, the forty-fourth P-type transistor P44, the forty-fourth N-type transistor N44, the forty-fifth P-type transistor P45, and the forty-fifth N-type transistor N45 constitute a third NAND gate 303. The gate electrode of the forty-fourth P-type transistor P44 and the gate electrode of the forty-fourth N-type transistor N44 are connected to each other and to the second reset terminal LF_pulse2 of the logic operation circuit. The gate electrode of the forty-fifth P-type transistor P45 and the gate electrode of the forty-fifth N-type transistor N45 are connected to each other and to the second electrode of the forty-first N-type transistor N41, the second electrode of the forty-second N-type transistor N42, the second electrode of the forty-third N-type transistor N43, and the second electrode of the forty-third P-type transistor P43, respectively. The first electrode of the forty-fourth P-type transistor P44 and the forty-fifth P-type transistor P45 are connected to the second electrode of the forty-first N-type transistor N41, the second electrode of the forty-second N-type transistor N42, the second electrode of the forty-third N-type transistor N43, and the second electrode of the forty-third P-type transistor P43, respectively. The first electrode of the forty-fourth N-type transistor N45 is connected to the first power supply line VDD, the first electrode of the forty-fourth N-type transistor N44 is connected to the ground line GND, the second electrode of the forty-fourth N-type transistor N44 is connected to the first electrode of the forty-fifth N-type transistor N45, the second electrode of the forty-fourth P-type transistor P44, the second electrode of the forty-fifth P-type transistor P45 and the second electrode of the forty-fifth N-type transistor N45 are connected to each other and serve as the output terminal OUT_AZ of the third operation circuit (that is, the output terminal of the output display reset signal AZn in Figure 11, which can be used as the display reset signal terminal OUT_AZn of the logic operation circuit).

[0265] FIG13 is a diagram illustrating the working principle of a level converter according to an exemplary embodiment of the present disclosure. As shown in FIG13 , the level converter may include an eleventh inverter 411 , a first P-type field effect transistor 501P, a second P-type field effect transistor 502P, a first N-type field effect transistor 501N, and a second N-type field effect transistor 502N.

[0266] In an exemplary embodiment, the input terminal IN_shifter of the level converter is respectively connected to the input terminal of the eleventh inverter 411 and the gate electrode of the first P-type field effect transistor 501P (wherein, the input terminal of the second level converter is electrically connected to the display switch signal terminal OUT_DSn in the logic operation circuit, and the input terminal of the third level converter is electrically connected to the display reset signal terminal AZ in the path operation circuit), the output terminal of the eleventh inverter 411 is connected to the gate electrode of the second P-type field effect transistor 502P, and the first electrode and the second P-type field effect transistor 501P are connected. The first electrodes of the field effect transistors 502P are connected to the first power supply line VDD. The second electrode of the first P-type field effect transistor 501P is respectively connected to the second electrode of the first N-type field effect transistor 501N, the gate electrode of the second N-type field effect transistor 502N, and the second output terminal OUT_B_shifter of the level shifter. The second electrode of the second P-type field effect transistor 502P is respectively connected to the gate electrode of the first N-type field effect transistor 501N, the second electrode of the second N-type field effect transistor 502N, and the first output terminal OUT_shifter of the level shifter. The first electrodes of the first N-type field effect transistor 501N and the first electrodes of the second N-type field effect transistor 502N are both connected to the second power supply line VSS. The first output terminal of the second level shifter is electrically connected to the first input terminal of the second row driver booster; the second output terminal of the second level shifter is electrically connected to the second input terminal of the second row driver booster; the first output terminal of the third level shifter is electrically connected to the first input terminal of the third row driver booster; and the second output terminal of the third level shifter is electrically connected to the second input terminal of the third row driver booster.

[0267] In an exemplary embodiment, the operating principle of the level shifter is as follows: when the input signal at the input terminal IN_shifter of the level shifter is at a low level, the first P-type field-effect transistor 501P is turned on, the second P-type field-effect transistor 502P is turned off, the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the first power line VDD, the second N-type field-effect transistor 502N is turned on, the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the second power line VSS, and the first N-type field-effect transistor 501N is turned off. When the input signal at the input terminal IN_shifter of the level shifter is at a high level, the first P-type field-effect transistor 501P is turned off, the second P-type field-effect transistor 502P is turned on, the output signal at the first output terminal OUT_shifter of the level shifter is the signal of the first power line VDD, the first N-type field-effect transistor 501N is turned on, the output signal at the second output terminal OUT_B_shifter of the level shifter is the signal of the second power line VSS, and the second N-type field-effect transistor 502N is turned off.

[0268] FIG14 is a schematic diagram illustrating the operating principle of a row driver enhancer according to an exemplary embodiment of the present disclosure. As shown in FIG14 , the row driver enhancer may include a fourth NAND gate 304, a fifth NAND gate 305, a first transmission gate 201, a twelfth inverter 412, a third P-type field effect transistor 503P, and a third N-type field effect transistor 503N. The third P-type field effect transistor 503P and the third N-type field effect transistor 503N have a relatively large width-to-length ratio to improve driving capability. The row driver enhancer can enhance the driving capability of a signal. The signal enhanced by the row driver enhancer can enhance the driving capability and can be suitable for driving an entire row of pixel driver circuits. In an exemplary embodiment, the enable signal input terminal IN_EN in FIG14 can be electrically connected to the reset control subcircuit 10-3 in FIG6 d and configured to receive the reset control signal from the reset control subcircuit 10-3. The reset control subcircuit 10-3 may include a NAND gate and an inverter, wherein the two input terminals of the NAND gate are respectively connected to the reset control terminal and the reset terminal, the output terminal of the NAND gate is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the enable signal input terminal IN_EN in the row driver enhancer.

[0269] In an exemplary embodiment, a first input terminal IN_driver of the row driver booster is connected to a first input terminal of a fourth NAND gate 304, an enable signal terminal EN of the row driver booster is connected to a second input terminal of the fourth NAND gate 304, an output terminal of the fourth NAND gate 304 is connected to an input terminal of the first transmission gate 201, an output terminal of the first transmission gate 201 is connected to a gate electrode of a third P-type field effect transistor 503P, and a first electrode of the third P-type field effect transistor 503P is connected to a first power supply line VDD. A second input terminal IN_B_driver of the row driver booster is connected to a first input terminal of a fifth NAND gate 305, an enable signal EN of the row driver booster is connected to a second input terminal of the fifth NAND gate 305, an output terminal of the fifth NAND gate 305 is connected to an input terminal of a twelfth inverter 412, an output terminal of the twelfth inverter 412 is connected to a gate electrode of a third N-type field effect transistor 503N, and a first electrode of the third N-type field effect transistor 503N is connected to a second power supply line VSS. The second electrode of the third P-type field-effect transistor 503P and the second electrode of the third N-type field-effect transistor 503N are connected to the output terminal OUT_driver of the row driver booster. The first transmission gate 201 and the twelfth inverter 412 have active-high enable terminals connected to the first power line VDD, and active-low enable terminals connected to the second power line VSS. The fourth NAND gate 304 and the fifth NAND gate 305 have active-high enable terminals connected to the first power line VDD, and active-low enable terminals connected to the ground line GND. In an exemplary embodiment, the output terminal of the second row driver booster is electrically connected to the display switch control terminal DS of the corresponding pixel driver circuit, and the output terminal of the third row driver booster is electrically connected to the display reset control terminal AZ of the corresponding pixel driver circuit.

[0270] In an exemplary embodiment, when the enable signal input to the enable signal terminal IN_EN of the row driver booster is a first level signal, the row driver booster is in a high-impedance state. This satisfies the requirement that, when the gate driver circuit is bilaterally driven (i.e., the gate driver circuit is located on both sides of the display area of ​​the display substrate), the enable signal input to the enable signal terminal of the row driver booster located on one side of the display area is set to the first level, so that the modified row driver booster is in a high-impedance state, thereby achieving unilateral driving of the gate driver circuit. That is, when gate driver circuits are provided on both sides of the display area, the high-impedance state of the row driver booster can achieve unilateral driving of the gate driver circuit (the row driver booster on one side of the display area is in a high-impedance state) or bilateral driving (the row driver boosters on both sides of the display area are not in a high-impedance state).

[0271] In an exemplary embodiment, the first level of the enable signal input to the enable signal terminal EN of the row driver booster may be a low level, that is, the enable signal is a low level. The embodiments of the present disclosure are not limited thereto. The row driver booster can be configured according to the circuit structure of the row driver booster so that the row driver booster is in a high-impedance state when the enable signal is at the first level.

[0272] In an exemplary embodiment, the row driver booster operates as follows:

[0273] When the enable signal at the enable signal terminal EN is 0, the fourth NAND gate 304 and the fifth NAND gate 305 output 1 (high level). The output of the fourth NAND gate 304 outputs 1 (high level) after passing through the first transmission gate 201, the third P-type field effect transistor 503P is turned off, and the output of the fifth NAND gate 305 outputs 0 (low level) after passing through the twelfth inverter 412, the third N-type field effect transistor 503N is turned off, and the entire circuit is in a high-impedance state.

[0274] When the enable signal at the enable signal terminal EN is 1, the circuit output is determined by the input signals at the first input terminal IN_driver and the second input terminal IN_B_driver of the row driver enhancer. The input signal at the first input terminal IN_driver and the input signal at the second input terminal IN_B_driver of the row driver enhancer are opposite direction signals. The opposite direction signals mean that the input signal at the first input terminal IN_driver is a high level signal 1, and the input signal at the second input terminal IN_B_driver is a low level signal 0; the input signal at the first input terminal IN_driver is a low level signal 0, and the input signal at the second input terminal IN_B_driver is a high level signal 1.

[0275] When the input signal at the first input terminal IN_driver of the row driver booster is 1 and the input signal at the second input terminal IN_B_driver is 0, the fourth NAND gate 304 outputs 0. The output of the fourth NAND gate 304 is output as 0 after passing through the first transmission gate 201, and the third P-type field effect transistor 503P is turned on. The fifth NAND gate 305 outputs 1. The output of the fifth NAND gate 305 is output as 0 after passing through the twelfth inverter 412, and the third N-type field effect transistor 503N is turned off. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the first power line VDD (high level).

[0276] When the input signal at the first input terminal IN_driver of the row driver booster is 0 and the input signal at the second input terminal IN_B_driver is 1, the fourth NAND gate 304 outputs 1. The output of the fourth NAND gate 304 outputs 1 after passing through the first transmission gate 201, and the third P-type field effect transistor 503P is turned off. The fifth NAND gate 305 outputs 0. The output of the fifth NAND gate 305 outputs 1 after passing through the twelfth inverter 412, and the third N-type field effect transistor 503N is turned on. The output signal at the output terminal OUT_driver of the row driver booster is the signal of the second power line VSS (low level).

[0277] In an exemplary embodiment, when the enable signal at the enable signal terminal EN is 0, the circuit output is in a high-impedance state. When the enable signal at the enable signal terminal EN is 1, the circuit output does not change the logical relationship between the high and low inputs and outputs; the enable signal at the enable signal terminal EN is a high-configuration control signal. In principle, the row driver booster is a buffer with a large width-to-length ratio, resulting in high output current and high drive capability. Furthermore, the row driver booster has low output impedance and strong drive capability.

[0278] In an exemplary embodiment, the input terminal IN_shifter of the level converter can be connected to the output terminal of the logic operation circuit 200, the first output terminal OUT_shifter of the level converter can be connected to the first input terminal IN_driver of the row driver enhancer, the second output terminal OUT_B_shifter of the level converter can be connected to the second input terminal IN_B_driver of the row driver enhancer, and the output terminal OUT_driver of the row driver enhancer can be connected to the scan signal line of the display area.

[0279] Figure 15 is an equivalent circuit diagram of a level shifter according to an exemplary embodiment of the present disclosure. As shown in Figure 15 , the level shifter of the gate drive circuit in the display substrate according to the present embodiment may include 16 transistors. The eleventh inverter 411 includes one P-type transistor and one N-type transistor, the first P-type field-effect transistor 501P includes six P-type transistors, the second P-type field-effect transistor 502P includes six P-type transistors, the first N-type field-effect transistor 501N includes one N-type transistor, and the second N-type field-effect transistor 502N includes one N-type transistor.

[0280] In the exemplary embodiment, a fifty-first P-type transistor P1 and a fifty-first N-type transistor N1 form an eleventh inverter 411. A gate electrode of the fifty-first P-type transistor P1 and a gate electrode of the fifty-first N-type transistor N1 are both connected to the converter input terminal IN_shifter. A first electrode of the fifty-first P-type transistor P1 is connected to the first power supply line VDD. A first electrode of the fifty-first N-type transistor N1 is connected to the ground line GND. A second electrode of the fifty-first P-type transistor P1 is connected to the second electrode of the fifty-first N-type transistor N1 and to the gate electrodes of the six P-type transistors in the second P-type field-effect transistor 502P.

[0281] In an exemplary embodiment, the fifty-second P-type transistor P52, the fifty-third P-type transistor P53, the fifty-fourth P-type transistor P54, the fifty-fifth P-type transistor P55, the fifty-sixth P-type transistor P56 and the fifty-seventh P-type transistor P57 connected in parallel constitute a first P-type field effect transistor 501P, the gate electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are all connected to the converter input terminal IN_shifter, the first electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are all connected to the first power line VDD, and the second electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57 are respectively connected to the gate electrode of the fifty-third N-type transistor N53, the second electrode of the fifty-second N-type transistor N52 and the second output terminal OUT_B_shifter of the converter.

[0282] In an exemplary embodiment, the fifty-eighth P-type transistor P58, the fifty-ninth P-type transistor P59, the sixtieth P-type transistor P60, the sixty-first P-type transistor P61, the sixty-second P-type transistor P62 and the sixty-third P-type transistor P63 connected in parallel constitute a second P-type field effect transistor 502P, the gate electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are all connected to the second electrode of the fifty-first P-type transistor P51 and the second electrode of the fifty-first N-type transistor N51, the first electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are all connected to the first power line VDD, and the second electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63 are respectively connected to the gate electrode of the fifty-second N-type transistor N52, the second electrode of the fifty-third N-type transistor N53 and the first output terminal OUT_shifter of the converter.

[0283] In the exemplary embodiment, a fifty-second N-type transistor N52 serves as the first N-type field-effect transistor 501N. A gate electrode of the fifty-second N-type transistor N52 is connected to the first output terminal OUT_shifter of the converter and second electrodes of the fifty-eighth through sixty-third P-type transistors P58 through P63, respectively. A first electrode of the fifty-second N-type transistor N52 is connected to the second power supply line VSS, and a second electrode of the fifty-second N-type transistor N52 is connected to the second output terminal OUT_B_shifter of the converter and second electrodes of the fifty-second through fifty-seventh P-type transistors P52 through P57, respectively.

[0284] In an exemplary embodiment, the fifty-third N-type transistor N53 serves as the second N-type field-effect transistor 502N, the gate electrode of the fifty-third N-type transistor N53 is respectively connected to the second output terminal OUT_B_shifter of the converter and the second electrodes of the fifty-second P-type transistor P52 to the fifty-seventh P-type transistor P57, the first electrode of the fifty-third N-type transistor N53 is connected to the second power line VSS, and the second electrode of the fifty-third N-type transistor N53 is respectively connected to the first output terminal OUT_shifter of the converter and the second electrodes of the fifty-eighth P-type transistor P58 to the sixty-third P-type transistor P63.

[0285] Figure 16 is an equivalent circuit diagram of a row driver booster according to an exemplary embodiment of the present disclosure. As shown in Figure 16, the row driver booster of the gate driver circuit in the display substrate according to the embodiment of the present disclosure may include 20 transistors. Among them, the fourth NAND gate 304 includes two P-type transistors and two N-type transistors, the fifth NAND gate 305 includes two P-type transistors and two N-type transistors, the first transmission gate 201 includes one P-type transistor and one N-type transistor, the twelfth inverter 412 includes one P-type transistor and one N-type transistor, the third P-type field-effect transistor 503P includes four P-type transistors, and the third N-type field-effect transistor 503N includes four N-type transistors.

[0286] In an exemplary embodiment, the fourth NAND gate 304, the first transmission gate 201, the fifth NAND gate 305 and the twelfth inverter 412 can be arranged in sequence along the first direction X (the direction close to the display area), the third P-type field effect transistor 503P and the third N-type field effect transistor 503N can be arranged on one side of the twelfth inverter 412 in the first direction X, and the third N-type field effect transistor 503N can be arranged on one side of the third P-type field effect transistor 503P in the second direction Y.

[0287] In an exemplary embodiment, the seventy-first P-type transistor P71 , the seventy-second P-type transistor P72 , the seventy-first N-type transistor N71 , and the seventy-second N-type transistor N72 constitute a fourth NAND gate 304 . The gate electrode of the seventy-first P-type transistor P71 and the gate electrode of the seventy-first N-type transistor N71 are connected to each other and to the first input terminal IN_driver of the enhancer, the gate electrode of the seventy-second P-type transistor P72 and the gate electrode of the seventy-second N-type transistor N72 are connected to each other and to the enable signal terminal EN, the first electrode of the seventy-first P-type transistor P71 and the first electrode of the seventy-second P-type transistor P72 are both connected to the first power line VDD, the first electrode of the seventy-second N-type transistor N72 is connected to the second power line VSS, the second electrode of the seventy-second N-type transistor N72 is connected to the first electrode of the seventy-first N-type transistor N71, the second electrode of the seventy-first P-type transistor P71 and the second electrode of the seventy-second P-type transistor P72 are connected to each other and are respectively connected to the second electrode of the seventy-first N-type transistor N71, the first electrode of the seventy-third P-type transistor P73 and the first electrode of the seventy-third N-type transistor N73.

[0288] In the exemplary embodiment, the seventy-third P-type transistor P73 and the seventy-third N-type transistor N73 constitute the first transmission gate 201. The gate electrode of the seventy-third P-type transistor P73 is connected to the second power supply line VSS, the gate electrode of the seventy-third N-type transistor N73 is connected to the first power supply line VDD, the first electrode of the seventy-third P-type transistor P73 and the first electrode of the seventy-third N-type transistor N73 are connected to each other and are respectively connected to the second electrode of the seventy-first P-type transistor P71, the second electrode of the seventy-first N-type transistor N71, and the second electrode of the seventy-second P-type transistor P72, the second electrode of the seventy-third P-type transistor P73 and the second electrode of the seventy-third N-type transistor N73 are connected to each other and are respectively connected to the gate electrodes of the seventy-seventh P-type transistor P77 to the eightieth P-type transistor P80.

[0289] In an exemplary embodiment, the seventy-fourth P-type transistor P74 , the seventy-fifth P-type transistor P75 , the seventy-fourth N-type transistor N74 , and the seventy-fifth N-type transistor N75 constitute a fifth NAND gate 305 . The gate electrode of the seventy-fourth P-type transistor P74 and the gate electrode of the seventy-twenty-fourth N-type transistor N74 are connected to each other and to the second input terminal IN_B_driver of the enhancer, the gate electrode of the seventy-fifth P-type transistor P75 and the gate electrode of the seventy-fifth N-type transistor N75 are connected to each other and to the enable signal terminal EN, the first electrode of the seventy-fourth P-type transistor P74 and the first electrode of the seventy-fifth P-type transistor P75 are both connected to the first power line VDD, the first electrode of the seventy-fifth N-type transistor N75 is connected to the second power line VSS, the second electrode of the seventy-fifth N-type transistor N75 is connected to the first electrode of the seventy-fourth N-type transistor N74, the second electrode of the seventy-fourth P-type transistor P74 and the second electrode of the seventy-fifth P-type transistor P75 are connected to each other and are respectively connected to the second electrode of the seventy-fourth N-type transistor N74, the gate electrode of the seventy-sixth P-type transistor P76 and the gate electrode of the seventy-sixth N-type transistor N76.

[0290] In the exemplary embodiment, the seventy-sixth P-type transistor P76 and the seventy-sixth N-type transistor N76 constitute the twelfth inverter 412. The gate electrode of the seventy-sixth P-type transistor P76 and the gate electrode of the seventy-sixth N-type transistor N76 are connected to each other and are respectively connected to the second electrode of the seventy-fourth P-type transistor P74, the second electrode of the seventy-fourth N-type transistor N74, and the second electrode of the seventy-fifth P-type transistor P75. A first electrode of the seventy-sixth P-type transistor P76 is connected to the first power supply line VDD, a first electrode of the seventy-sixth N-type transistor N76 is connected to the second power supply line VSS, a second electrode of the seventy-sixth P-type transistor P76 and the second electrode of the seventy-sixth N-type transistor N27 are connected to each other and are respectively connected to the gate electrodes of the seventy-seventh N-type transistor N77 to the eightieth N-type transistor N80.

[0291] In the exemplary embodiment, a seventy-seventh P-type transistor P77, a seventy-eighth P-type transistor P78, a seventy-ninth P-type transistor P79, and an eightieth P-type transistor P80 connected in parallel form a third P-type field effect transistor 503P. Gate electrodes of the seventy-seventh P-type transistor P77 through the eightieth P-type transistor P80 are connected to one another and to the second electrode of the seventy-third P-type transistor P73 and the second electrode of the seventy-third N-type transistor N73, respectively. First electrodes of the seventy-seventh P-type transistor P77 through the eightieth P-type transistor P80 are all connected to the first power supply line VDD, and second electrodes of the seventy-seventh P-type transistor P77 through the eightieth P-type transistor P80 are all connected to the booster output terminal OUT_driver.

[0292] In the exemplary embodiment, a seventy-seventh N-type transistor N77, a seventy-eighth N-type transistor N78, a seventy-ninth N-type transistor N79, and an eightieth N-type transistor N80, which are connected in parallel, form a third N-type field effect transistor 503N. Gate electrodes of the seventy-seventh N-type transistor N77 through the eightieth N-type transistor N80 are connected to each other and to the second electrode of the seventy-sixth P-type transistor P76 and the second electrode of the seventy-sixth N-type transistor N76, respectively. First electrodes of the seventy-seventh N-type transistor N77 through the eightieth N-type transistor N80 are all connected to the second power supply line VSS, and second electrodes of the seventy-seventh N-type transistor N77 through the eightieth N-type transistor N80 are all connected to the booster output terminal OUT_driver.

[0293] Figure 17 is an equivalent circuit diagram of an output circuit (including a level shifter and a row driver booster) according to an exemplary embodiment of the present disclosure. As shown in Figures 15, 16, and 17, the output circuit includes the level shifter shown in Figure 15 and the row driver booster shown in Figure 16. The first output terminal OUT_shifter of the shifter is connected to the first input terminal IN_driver of the booster, and the second output terminal OUT_B_shifter of the shifter is connected to the second input terminal IN_B_driver of the booster.

[0294] In an exemplary embodiment, as shown in Figure 18, which is a circuit schematic diagram of a shift register circuit provided in an exemplary embodiment of the present disclosure, each gate drive circuit may include four triggers (DFF1 to DFF4), and the shift registers in multiple rows of gate drive circuits are cascaded. For example, the first output terminal OUT_A_Qn (which can be used as the output terminal of the inverted signal of the first shift signal, wherein the second output terminal OUT_A_Qn_ can be used as the output terminal of the first shift signal) of the n-th row gate drive circuit is connected to the input terminal IN_A_Dn+1 of the first trigger DFF1 of the n+1-th row gate drive circuit; the first output terminal OUT_A_Qn+1 of the first trigger DFF1 of the n+1-th row gate drive circuit is connected to the input terminal IN_A_Dn of the first trigger DFF1 of the n-th row gate drive circuit. Similarly, the first output terminal OUT_B_Qn (which can serve as the second shift signal output terminal) of the second flip-flop DFF2 of the gate driver circuit in the nth row is connected to the input terminal IN_B_Dn+1 (which can serve as the second signal input terminal) of the second flip-flop DFF2 of the gate driver circuit in the n+1th row; the first output terminal OUT_B_Qn+1 of the second flip-flop DFF2 of the gate driver circuit in the n+1th row is connected to the input terminal IN_B_Dn of the second flip-flop DFF2 of the gate driver circuit in the nth row. The first output terminal OUT_C_Qn (which can serve as the third shift signal output terminal) of the third flip-flop DFF3 of the gate driver circuit in the nth row is connected to the input terminal IN_C_Dn+1 (which can serve as the third signal input terminal) of the third flip-flop DFF3 of the gate driver circuit in the n+1th row; and the first output terminal OUT_C_Qn+1 of the third flip-flop DFF3 of the gate driver circuit in the n+1th row is connected to the input C_Dn of the third flip-flop DFF3 of the gate driver circuit in the nth row. The first output terminal OUT_D_Qn of the fourth trigger DFF4 of the gate driving circuit of the nth row is connected to the input terminal IN_D_Dn+1 of the fourth trigger DFF4 of the gate driving circuit of the n+1th row; the first output terminal OUT_D_Qn+1_ of the fourth trigger DFF4 of the gate driving circuit of the n+1th row is connected to the input terminal IN_D_Dn of the fourth trigger DFF4 of the gate driving circuit of the nth row.

[0295] In an exemplary embodiment, as shown in Figure 18, the logic control circuit 10 in the gate drive circuit may include a forward and reverse scan control circuit, and the forward and reverse scan control circuit may include a forward scan control circuit 10-1 and a reverse scan control circuit 10-2. Each forward and reverse scan control circuit may include a first forward and reverse scan control terminal GSD_FW and a second forward and reverse scan control terminal GSD_BW. The two cascaded triggers can be connected through the forward and reverse scan control circuit. Taking the first trigger as an example: the first output terminal OUT_A_Qn of the first trigger DFF1 of the n-th stage gate drive circuit is connected to the input terminal IN_A_Dn+1 of the first trigger DFF1 of the n+1-th stage gate drive circuit through the forward scan control circuit 10-1; the first output terminal OUT_A_Qn+1 of the first trigger DFF1 of the n+1-th stage gate drive circuit is connected to the input terminal IN_A_Dn (which can be used as the above-mentioned first signal input terminal) of the first trigger DFF1 of the n-th stage gate drive circuit through the reverse scan control circuit 10-2. In the case of forward scanning, the forward scanning control circuit 10-1 is turned on and scans in the direction from the nth row to the n+1th row (i.e., the forward scanning control circuit 10-1 is turned on and the reverse scanning control circuit 10-2 is turned off by the signal input to the first forward and reverse scanning control terminal GSD_FW and the second forward and reverse scanning control terminal GSD_BW). In the case of reverse scanning, the reverse scanning control circuit 10-2 is turned on and scans in the direction from the n+1th row to the nth row (i.e., the forward scanning control circuit 10-1 is turned off and the reverse scanning control circuit 10-2 is turned on by the signal input to the first forward and reverse scanning control terminal GSD_FW and the second forward and reverse scanning control terminal GSD_BW). In an exemplary embodiment, the forward and reverse scanning control circuits may be transmission gates.

[0296] In an exemplary embodiment, FIG18 is a diagram illustrating the operating principle of a shift register circuit according to an exemplary embodiment of the present disclosure. The shift register circuit may be composed of a flip-flop (D Flip Flop) as shown in FIG19 . The flip-flop (which may be a D flip-flop) may include nine parts, namely three transmission gates (TG), four inverters (INVX), and two NAND gates (NAND). The inverters may also be referred to as NOT gates. As shown in FIG19 , the flip-flop may include a second transmission gate 202, a third transmission gate 203, a fourth transmission gate 204, a sixth NAND gate 306, a seventh NAND gate 307, a twelfth inverter 412, a thirteenth inverter 413, a fourteenth inverter 414, and a fifteenth inverter 415.

[0297] In an exemplary embodiment, an input terminal of the twelfth inverter 412 is connected to the clock signal terminal IN_CK of the shift register circuit, and an output terminal of the twelfth inverter 412 is connected to the first node CK_. An input terminal of the thirteenth inverter 413 is connected to the first node CK_, and an output terminal of the thirteenth inverter 413 is connected to the second node CK'. A first terminal of the second transmission gate 202 is connected to the input terminal IN_D of the shift register circuit, a second terminal of the second transmission gate 202 is connected to the output terminal of the fourteenth inverter 414 and the first input terminal of the sixth NAND gate 306, respectively, a high-level active enable terminal of the second transmission gate 202 is connected to the first node CK_, and a low-level active enable terminal of the second transmission gate 202 is connected to the second node CK'. A second input terminal of the sixth NAND gate 306 is connected to the reset terminal RN of the shift register circuit. An output terminal of the sixth NAND gate 306 is connected to the input terminal of the fourteenth inverter 414 and the first terminal of the third transmission gate 203, respectively. An active-high enable terminal of the fourteenth inverter 414 is connected to the second node CK′, and an active-low enable terminal of the fourteenth inverter 414 is connected to the first node CK_. A second terminal of the third transmission gate 203 is connected to the input terminal of the fifteenth inverter 415 and the first terminal of the fourth transmission gate 204, respectively. An active-high enable terminal of the third transmission gate 203 is connected to the second node CK′, and an active-low enable terminal of the third transmission gate 203 is connected to the first node CK_. The output end of the fifteenth inverter 415 is connected to the first input end of the seventh NAND gate 307 and the first output end OUT_Q of the shift register circuit, the second end of the fourth transmission gate 204 is respectively connected to the output end of the seventh NAND gate 307 and the second output end OUT_Q_ of the shift register circuit, the high-level effective enable end of the fourth transmission gate 204 is connected to the first node CK_, the low-level effective enable end of the fourth transmission gate 204 is connected to the second node CK', and the second input end of the seventh NAND gate 307 is connected to the reset end RN of the trigger.

[0298] In an exemplary embodiment, the trigger is active on a rising edge. With each rising edge, the output maintains the state of the previous stage input to the input terminal IN_D. RN is the reset signal terminal (or initialization signal terminal). When it is high, the shift register circuit is active. FIG20 shows an operational timing diagram of the trigger shown in FIG19 . In FIG20 , the horizontal axis represents time in microseconds, and the vertical axis represents voltage in volts (V). The operation of the trigger may include the first stage p1 to the sixth stage p6 (the signal input to the initialization signal terminal RN is high during the first stage p1 to the ninth stage p9):

[0299] Phase 1 p1: The input signal at the clock signal terminal CK of the flip-flop is low, the input signal D at the input terminal IN_D of the flip-flop is low, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the low-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A (which can be called the third node of the flip-flop) is low, and node D_ (which can be called the fourth node of the flip-flop) is high. Since the third transmission gate 203 is turned off, the node D_' (which can be called the fifth node of the flip-flop) remains high. The output signal Q at the first output terminal OUT_Q of the flip-flop is low. Since the fourth transmission gate 204 is turned on, the high level of node D_' is transmitted to the second output terminal OUT_Q_ of the flip-flop via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the flip-flop is high. In the second stage p2, the input signal of the clock signal terminal CK of the trigger is high, the input signal of the input terminal IN_D of the trigger is low, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the low-level signal of the input terminal D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the low level of the previous stage, and node D_ maintains the high level of the previous stage. Since the third transmission gate 203 is turned on, node The high-level signal of D is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a high level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a low level. Since the fourth transmission gate 204 is disconnected, the high level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The low level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are NANDed by the seventh NAND gate 307 to obtain a high level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a high level.

[0300] The third stage p3: The working sequence is the same as the first stage p1 and will not be repeated here.

[0301] Phase 4 p4: The input signals at the clock signal terminal CK and the input terminal IN_D of the flip-flop are both high, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the high-level signal D at the input terminal IN_D cannot be transmitted to the node A via the second transmission gate 202. Node A maintains the low level of the previous phase, and node D_ maintains the high level of the previous phase. Since the third transmission gate 203 is turned on, the high-level signal at node D is transmitted to the node D_' via the third transmission gate 203. Node D_' is high, and the output signal Q at the first output terminal OUT_Q of the flip-flop is low. Since the fourth transmission gate 204 is disconnected, the high level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger through the fourth transmission gate 204. The low level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are NANDed by the seventh NAND gate 307 to obtain a high level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is high.

[0302] Fifth stage p5: The input signal at the clock signal terminal CK of the trigger is low, the input signal at the input terminal IN_D of the trigger is high, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the high-level signal D at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is high, and node D_ becomes low. Since the third transmission gate 203 is turned off, node D_' remains high. The output signal Q at the first output terminal OUT_Q of the trigger is low. Since the fourth transmission gate 204 is turned on, the high level of node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the trigger is high.

[0303] Phase 6 p6: The input signal of the clock signal terminal CK of the flip-flop and the input signal D of the input terminal OUT_D are both high, the first node CK_ is low, the second node CK' is high, the second transmission gate 202 and the fourth transmission gate 204 are disconnected, and the third transmission gate 203 is turned on. Since the second transmission gate 202 is disconnected, the high-level signal of the input terminal IN_D cannot be transmitted to the node A through the second transmission gate 202. Node A maintains the high level of the previous phase, and node D_ maintains the low level of the previous phase. Since the third transmission gate 203 is turned on, node D_ The low-level signal of the trigger is transmitted to the node D_' via the third transmission gate 203. The node D_' is at a low level, and the output signal Q of the first output terminal OUT_Q of the trigger is at a high level. Since the fourth transmission gate 204 is disconnected, the low level of the node D_' cannot be transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The high level of the first output terminal OUT_Q of the trigger and the high level of the initial signal terminal RN are obtained by the NAND operation of the seventh NAND gate 307 to obtain a low level. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is at a low level.

[0304] Seventh stage p7: the input signal at the clock signal terminal CK of the trigger is low, the input signal D at the input terminal IN_D of the trigger is high, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the high-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is high, and node D_ is low. Since the third transmission gate 203 is turned off, node D_' remains at its original low level. The output signal Q at the first output terminal OUT_Q of the trigger is high. Since the fourth transmission gate 204 is turned on, the low level at the node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ at the second output terminal OUT_Q_ of the trigger is low.

[0305] The eighth stage p8: The working sequence is the same as that of the sixth stage p6, and will not be repeated here.

[0306] Ninth stage p9: the input signal of the clock signal terminal CK of the trigger is low, the input signal D of the input terminal IN_D of the trigger is low, the first node CK_ is high, the second node CK' is low, the second transmission gate 202 and the fourth transmission gate 204 are turned on, and the third transmission gate 203 is turned off. Since the second transmission gate 202 is turned on, the low-level signal at the input terminal IN_D is transmitted to the node A via the second transmission gate 202. Node A is low, and node D_ is high. Since the third transmission gate 203 is turned off, the node D_' maintains its original low level. The output signal Q of the first output terminal OUT_Q of the trigger is high. Since the fourth transmission gate 204 is turned on, the low level of the node D_' is transmitted to the second output terminal OUT_Q_ of the trigger via the fourth transmission gate 204. The output signal Q_ of the second output terminal OUT_Q_ of the trigger is low.

[0307] Combining the first stage p1 to the ninth stage p9, the working principle of the trigger is:

[0308] (1) When the input signal of the clock signal terminal CK of the trigger is at a low level and the input signal D of the input terminal IN_D of the trigger is at a low level, the second transmission gate 202 is turned on, the third transmission gate 203 is turned off, and the fourth transmission gate 204 is turned on. The node A is a low level signal, the node D_ is a high level signal, the output signal Q of the first output terminal OUT_Q of the trigger maintains the original level signal (for example, a low level), and the output signal Q_ of the second output terminal OIT_Q_ of the trigger maintains the original level signal (for example, a high level).

[0309] (2) When the input signal of the clock signal terminal CK of the trigger is at a high level and the input signal D of the input terminal IN_D of the trigger is at a low level, the second transmission gate 202 is disconnected, the third transmission gate 203 is turned on, and the fourth transmission gate 204 is disconnected. Node A and node D_ maintain their original potentials. When node A is originally a low-level signal and node D_ is originally a high-level signal, the output of the first output terminal OUT_Q of the trigger is low-level, and the output of the second output terminal OUT_Q_ of the trigger is high-level; when node A is originally a high-level signal and node D_ is originally a low-level signal, the output signal Q of the first output terminal OUT_Q of the trigger is high-level, and the output signal Q_ of the second output terminal OUT_Q_ of the trigger is low-level.

[0310] (3) When the input signal of the clock signal terminal CK of the trigger is at a low level and the input signal of the input terminal IN_D of the trigger is at a high level, the second transmission gate 202 is turned on, the third transmission gate 203 is turned off, and the fourth transmission gate 204 is turned on. Node A is a high-level signal, and node D_ is a low-level signal. The signal after the third transmission gate 203 is latched (i.e., the signal from node D_' to the first output terminal OUT_Q and the second output terminal OUT_Q_ is latched), and the output is maintained (i.e., the output signal Q of the first output terminal OUT_Q of the trigger and the output signal Q_ of the second output terminal OUT_Q_ of the trigger maintain their original levels);

[0311] (4) When the input signal of the clock signal terminal CK of the trigger is at a high level and the input signal of the input terminal IN_D of the trigger is at a high level, the second transmission gate 202 is disconnected, the third transmission gate 203 is turned on, and the fourth transmission gate 204 is disconnected. Node A and node D_ maintain their original potentials. When node A is originally a low-level signal and node D_ is originally a high-level signal, the output of the first output terminal OUT_Q of the trigger is low-level, and the output of the second output terminal OUT_Q_ of the trigger is high-level; when node A is originally a high-level signal and node D_ is originally a low-level signal, the output signal Q of the first output terminal OUT_Q of the trigger is high-level, and the output signal Q_ of the second output terminal OUT_Q_ of the trigger is low-level.

[0312] FIG21 is an equivalent circuit diagram of a trigger according to an exemplary embodiment of the present disclosure. As shown in FIG8 , the trigger of the gate drive circuit in the display substrate of the present embodiment can include 24 transistors. The second transmission gate 202, the third transmission gate 203, the fourth transmission gate 204, the twelfth inverter 412, the thirteenth inverter 413, and the fifteenth inverter 415 each include one P-type transistor and one N-type transistor, and the sixth NAND gate 306, the seventh NAND gate 307, and the fourteenth inverter 414 each include two P-type transistors and two N-type transistors.

[0313] In an exemplary embodiment, the second transmission gate 202, the sixth NAND gate 306, the fourteenth inverter 414, the third transmission gate 203, the fourth transmission gate 204, the seventh NAND gate 307, the fifteenth inverter 415, the thirteenth inverter 413 and the twelfth inverter 412 can be arranged in sequence along the first direction X (the direction close to the display area).

[0314] In the exemplary embodiment, the eighty-first P-type transistor P81 and the eighty-first N-type transistor N81 constitute the second transmission gate 202. The gate electrode of the eighty-first P-type transistor P81 is respectively connected to the gate electrode of the eighty-fifth N-type transistor N85, the gate electrode of the eighty-sixth N-type transistor N86, the gate electrode of the eighty-seventh P-type transistor P87, the second electrode of the ninety-first P-type transistor P91, and the second electrode of the ninety-first N-type transistor N91, and the gate electrode of the eighty-first N-type transistor N81 is respectively connected to the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91. The gate electrode of the ninety-second P-type transistor P82, the gate electrode of the eighty-second N-type transistor N82, the second electrode of the eighty-fifth P-type transistor P85 and the second electrode of the eighty-fifth N-type transistor N85 are connected respectively.

[0315] In the exemplary embodiment, the eighty-second P-type transistor P82, the eighty-third P-type transistor P83, the eighty-second N-type transistor N82, and the eighty-third N-type transistor N83 constitute a sixth NAND gate 306. The gate electrode of the eighty-second P-type transistor P82 and the gate electrode of the eighty-second N-type transistor N82 are connected to each other, and are respectively connected to the second electrode of the eighty-first P-type transistor P81, the second electrode of the eighty-first N-type transistor N81, the second electrode of the eighty-fifth P-type transistor P85, and the second electrode of the eighty-fifth N-type transistor N85. The gate electrode of the eighty-third P-type transistor P83 and the gate electrode of the eighty-third N-type transistor N83 are connected to each other and to the reset terminal RN. The first electrode of the eighty-second P-type transistor P82 and the first electrode of the eighty-third P-type transistor P83 are both connected to the first electrode. The source line VDD is connected, the second electrode of the eighty-second P-type transistor P82 and the second electrode of the eighty-third P-type transistor P83 are connected to each other, and are respectively connected to the second electrode of the eighty-second N-type transistor N82, the gate electrode of the eighty-fourth P-type transistor P84, the gate electrode of the eighty-fourth N-type transistor N84, the first electrode of the eighty-sixth P-type transistor P86 and the first electrode of the eighty-sixth N-type transistor N86, the first electrode of the eighty-third N-type transistor N83 is connected to the ground line GND, and the second electrode of the eighty-third N-type transistor N83 is connected to the first electrode of the eighty-second N-type transistor N82.

[0316] In an exemplary embodiment, the eighty-fourth P-type transistor P84 , the eighty-fifth P-type transistor P85 , the eighty-fourth N-type transistor N84 , and the eighty-fifth N-type transistor N85 constitute the fourteenth inverter 414 . The gate electrode of the eighty-fourth P-type transistor P84 and the gate electrode of the eighty-fourth N-type transistor N84 are connected to each other, and are respectively connected to the second electrode of the eighty-second P-type transistor P82, the second electrode of the eighty-second N-type transistor N82, the second electrode of the eighty-third P-type transistor P83, the first electrode of the eighty-sixth P-type transistor P86, and the first electrode of the eighty-sixth N-type transistor N86. The gate electrode of the eighty-fifth P-type transistor P85 is respectively connected to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91, the second electrode of the ninety-second P-type transistor P92, and the second electrode of the ninety-second N-type transistor N92. The gate electrode of the eighty-fifth N-type transistor N85 is respectively connected to the gate electrode of the eighty-first P-type transistor P81, The gate electrode of the eighty-sixth N-type transistor N86, the gate electrode of the eighty-seventh P-type transistor P87, the second electrode of the ninety-first P-type transistor P91 and the second electrode of the ninety-first N-type transistor N91 are connected, the first electrode of the eighty-fourth P-type transistor P84 is connected to the first power supply line VDD, the second electrode of the eighty-fourth P-type transistor P84 is connected to the first electrode of the eighty-fifth P-type transistor P85, the first electrode of the eighty-fourth N-type transistor N84 is connected to the ground line GND, the second electrode of the eighty-fourth N-type transistor N84 is connected to the first electrode of the eighty-fifth N-type transistor N85, the second electrode of the eighty-fifth P-type transistor P85 and the second electrode of the eighty-fifth N-type transistor N85 are connected to each other, and are respectively connected to the second electrode of the eighty-first P-type transistor P81, the second electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-second P-type transistor P82 and the gate electrode of the eighty-second N-type transistor N82.

[0317] In the exemplary embodiment, the eighty-sixth P-type transistor P86 and the eighty-sixth N-type transistor N86 constitute the third transmission gate 203. The gate electrode of the eighty-sixth P-type transistor P86 is respectively connected to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91, the second electrode of the ninety-second P-type transistor P92, and the second electrode of the ninety-second N-type transistor N92, and the gate electrode of the eighty-sixth N-type transistor N86 is respectively connected to the gate electrode of the eighty-first P-type transistor P81, the gate electrode of the eighty-fifth N-type transistor N85, the gate electrode of the eighty-seventh P-type transistor P87, the second electrode of the ninety-first P-type transistor P91, and the second electrode of the ninety-first N-type transistor N91. The two electrodes are connected, the first electrode of the eighty-sixth P-type transistor P86 and the first electrode of the eighty-sixth N-type transistor N86 are connected to each other, and are respectively connected to the second electrode of the eighty-second P-type transistor P82, the second electrode of the eighty-third P-type transistor P83, the second electrode of the eighty-second N-type transistor N82, the gate electrode of the eighty-fourth P-type transistor P84 and the gate electrode of the eighty-fourth N-type transistor N84, the second electrode of the eighty-sixth P-type transistor P86 and the second electrode of the eighty-sixth N-type transistor N86 are connected to each other, and are respectively connected to the first electrode of the eighty-seventh P-type transistor P87, the first electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninetieth P-type transistor P90 and the gate electrode of the ninetieth N-type transistor N90.

[0318] In the exemplary embodiment, the eighty-seventh P-type transistor P87 and the eighty-seventh N-type transistor N87 constitute the fourth transmission gate 204. The gate electrode of the eighty-seventh P-type transistor P87 is respectively connected to the gate electrode of the eighty-first P-type transistor P81, the gate electrode of the eighty-fifth N-type transistor N85, the gate electrode of the eighty-sixth N-type transistor N86, the second electrode of the ninety-first P-type transistor P91, and the second electrode of the ninety-first N-type transistor N91, and the gate electrode of the eighty-seventh N-type transistor N87 is respectively connected to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the ninety-first P-type transistor P91, the gate electrode of the ninety-first N-type transistor N91, the gate electrode of the ninety-second P-type transistor P92. The second electrode of the eighty-seventh P-type transistor P87 and the second electrode of the ninety-second N-type transistor N92 are connected, the first electrode of the eighty-seventh P-type transistor P87 and the first electrode of the eighty-seventh N-type transistor N87 are connected to each other, and are respectively connected to the second electrode of the eighty-sixth P-type transistor P86, the second electrode of the eighty-sixth N-type transistor N86, the gate electrode of the ninetieth P-type transistor P90 and the gate electrode of the ninetieth N-type transistor N90, the second electrode of the eighty-seventh P-type transistor P87 and the second electrode of the eighty-seventh N-type transistor N87 are connected to each other, and are respectively connected to the second electrode of the eighty-eighth P-type transistor P88, the second electrode of the eighty-ninth P-type transistor P89 and the second electrode of the eighty-ninth N-type transistor N89.

[0319] In an exemplary embodiment, the eighty-eighth P-type transistor P88 , the eighty-ninth P-type transistor P89 , the eighty-eighth N-type transistor N88 , and the eighty-ninth N-type transistor N89 constitute the seventh NAND gate 307 . The gate electrode of the eighty-eighth P-type transistor P88 and the gate electrode of the eighty-eighth N-type transistor N88 are connected to each other and to the reset terminal RN of the shift register circuit. The gate electrode of the eighty-ninth P-type transistor P89 and the gate electrode of the eighty-ninth N-type transistor N89 are connected to each other and to the second electrode of the ninetieth P-type transistor P90 and the second electrode of the ninetieth N-type transistor N90, respectively. The first electrode of the eighty-eighth P-type transistor P88 and the first electrode of the eighty-ninth P-type transistor P89 are both connected to the first power supply line VDD. The second electrode of the eighty-eighth P-type transistor P88 and the second electrode of the eighty-ninth P-type transistor P89 are connected to each other and to the second electrode of the eighty-ninth N-type transistor N89, the second electrode of the eighty-seventh P-type transistor P87 and the second electrode of the eighty-seventh N-type transistor N87, respectively. The first electrode of the eighty-eighth N-type transistor N88 is connected to the ground line GND, and the second electrode of the eighty-eighth N-type transistor N88 is connected to the first electrode of the eighty-ninth N-type transistor N89.

[0320] In the exemplary embodiment, the 90th P-type transistor P90 and the 90th N-type transistor N90 form the 15th inverter 415. The gate electrode of the 90th P-type transistor P90 and the gate electrode of the 90th N-type transistor N90 are connected to each other and are respectively connected to the second electrode of the 86th P-type transistor P86, the second electrode of the 86th N-type transistor N86, the first electrode of the 87th P-type transistor P87, and the first electrode of the 87th N-type transistor N87. The first electrode of the 90th P-type transistor P90 is connected to the first power supply line VDD, the first electrode of the 90th N-type transistor N90 is connected to the ground line GND, and the second electrode of the 90th P-type transistor P90 and the second electrode of the 90th N-type transistor N90 are connected to each other and are respectively connected to the gate electrode of the 89th P-type transistor P89 and the gate electrode of the 89th N-type transistor N89.

[0321] In the exemplary embodiment, the ninety-first P-type transistor P91 and the ninety-first N-type transistor N91 constitute the thirteenth inverter 413. The gate electrodes of the ninety-first P-type transistor P91 and the ninety-first N-type transistor N91 are connected to each other and to the gate electrodes of the eighty-first N-type transistor N81, the eighty-fifth P-type transistor P85, the eighty-sixth P-type transistor P86, the eighty-seventh N-type transistor N87, the second electrode of the ninety-second P-type transistor P92, and the second electrode of the ninety-second N-type transistor N92, respectively. A first electrode of the ninety-first P-type transistor P91 is connected to the first power supply line VDD, a first electrode of the ninety-first N-type transistor N91 is connected to the ground line GND, and a second electrode of the ninety-first P-type transistor P91 and the second electrode of the ninety-first N-type transistor N91 are connected to each other and to the gate electrodes of the eighty-first P-type transistor P81, the eighty-fifth N-type transistor N85, the eighty-sixth N-type transistor N86, and the eighty-seventh P-type transistor P87, respectively.

[0322] In the exemplary embodiment, the ninety-second P-type transistor P92 and the ninety-second N-type transistor N92 form the twelfth inverter 412. The gate electrode of the ninety-second P-type transistor P92 and the gate electrode of the ninety-second N-type transistor N92 are connected to each other and to the clock signal terminal CK of the shift register circuit. A first electrode of the ninety-second P-type transistor P92 is connected to the first power supply line VDD, a first electrode of the ninety-second N-type transistor N92 is connected to the ground line GND, and a second electrode of the ninety-second P-type transistor P92 and the second electrode of the ninety-second N-type transistor N92 are connected to each other and to the gate electrode of the eighty-first N-type transistor N81, the gate electrode of the eighty-fifth P-type transistor P85, the gate electrode of the eighty-sixth P-type transistor P86, the gate electrode of the eighty-seventh N-type transistor N87, the gate electrode of the ninety-first P-type transistor P91, and the gate electrode of the ninety-first N-type transistor N91, respectively.

[0323] In an exemplary embodiment, the function of the first flip-flop DFF1 is to shift the first signal A_Dn input to the first signal input terminal IN_A_Dn (the shift clock signal is CKV1), the function of the second flip-flop DFF2 is to shift the second signal B_Dn input to the second signal input terminal IN_B_Dn (the shift clock signal is CKV2), the function of the third flip-flop DFF3 is to shift the third signal C_Dn input to the third signal input terminal IN_C_Dn (the shift clock signal is CKV3), and the function of the fourth flip-flop DFF4 is to shift the fourth signal D_Dn input to the fourth signal input terminal IN_D_Dn (the shift clock signal is CKV5), thereby providing an initial signal for the logic operation circuit 200.

[0324] In an exemplary embodiment, as shown in FIG22 , the gate drive circuit may further include a first test circuit, which may be configured to test the write switch signal output by the first logic circuit. The operating principle diagram of the first test circuit is shown in FIG22 . The first test circuit may include two inverters, and the input of the first test circuit may be electrically connected to the output OUT_WS of the first operation circuit (i.e., the write switch signal terminal OUT_WSn of the logic operation circuit). As shown in FIG22 , the first test circuit may include a thirteenth inverter 413 and a fourteenth inverter 414. The input of the thirteenth inverter 413 is connected to the output OUT_DS of the second operation circuit, and the output of the thirteenth inverter 413 is connected to the input of the fourteenth inverter 414. The output of the fourteenth inverter 414 may serve as the output Test_WS of the first test circuit (i.e., the test terminal for the write switch signal DSn of the gate drive circuit).

[0325] In an exemplary embodiment, a first test circuit can detect whether a write switch signal DSn outputted from an output terminal OUT_WS of the first arithmetic circuit is consistent with a target timing. If the write switch signal WSn detected at the output terminal Test_WS of the first test circuit is inconsistent with the target timing, it indicates that an abnormality has occurred in the write switch signal WSn before the write switch signal WSn enters the level shifter 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that an operational abnormality of the first arithmetic circuit has caused the write switch signal WSn to be inconsistent with the target timing. If the write switch signal WSn detected at the output terminal Test_WS of the first test circuit is consistent with the target timing, it indicates that an abnormality has occurred in the write switch signal WSn after the write switch signal WSn enters the level shifter 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the first arithmetic circuit is operating normally. Therefore, the write switch signal WSn outputted by the first arithmetic circuit can be tested at the output terminal Test_WS of the first test circuit to determine whether the first arithmetic circuit is operating normally. In an exemplary embodiment, the output terminal Test_WS of the first test circuit can be brought out through a pad around the display area. During testing, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_WS of the first test circuit. The waveform output by the output terminal Test_WS of the first test circuit is obtained through the oscilloscope, and the waveform output by the output terminal Test_WS of the first test circuit is compared with the waveform of the target timing to see whether they are consistent. If they are consistent, it indicates that the first operation circuit is working normally, and if they are inconsistent, it indicates that the first operation circuit is working abnormally.

[0326] In an exemplary embodiment, as shown in FIG23 , the gate drive circuit may further include a second test circuit, which may be configured to test the display switch signal output by the second logic circuit. The operating principle diagram of the second test circuit is shown in FIG23 . The second test circuit may include two inverters, and the input of the second test circuit may be electrically connected to the output OUT_DS of the second operation circuit (i.e., the display switch signal terminal OUT_DSn of the logic operation circuit). As shown in FIG23 , the second test circuit may include a fifteenth inverter 415 and a sixteenth inverter 416. The input of the fifteenth inverter 415 is connected to the output OUT_DS of the second operation circuit, and the output of the fifteenth inverter 415 is connected to the input of the sixteenth inverter 416. The output of the sixteenth inverter 416 may serve as the output Test_DS of the second test circuit (i.e., the test terminal for the display switch signal DSn of the gate drive circuit).

[0327] In an exemplary embodiment, a second test circuit can detect whether the display switching signal DSn outputted from the output terminal OUT_DS of the second arithmetic circuit is consistent with a target timing. If the display switching signal DSn detected at the output terminal Test_DS of the second test circuit is inconsistent with the target timing, it indicates that the display switching signal DSn has already experienced an abnormality before entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the abnormal operation of the second arithmetic circuit has caused the display switching signal DSn to be inconsistent with the target timing. If the display switching signal DSn detected at the output terminal Test_DS of the second test circuit is consistent with the target timing, it indicates that the display switching signal DSn has experienced an abnormality after entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the second arithmetic circuit is operating normally. Therefore, the display switching signal DSn outputted by the second arithmetic circuit can be tested at the output terminal Test_DS of the second test circuit to determine whether the second arithmetic circuit is operating normally. In an exemplary embodiment, the output terminal Test_DS of the first test circuit can be brought out through a pad around the display area. During testing, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_DS of the second test circuit. The waveform output by the output terminal Test_DS of the second test circuit is obtained through the oscilloscope, and the waveform output by the output terminal Test_DS of the second test circuit is compared with the waveform of the target timing to see whether they are consistent. If they are consistent, it indicates that the second operation circuit is working normally, and if they are inconsistent, it indicates that the second operation circuit is working abnormally.

[0328] In an exemplary embodiment, as shown in FIG24 , the gate drive circuit may further include a third test circuit, which may be configured to test the display reset signal output by the third logic circuit. The operating principle diagram of the third test circuit is shown in FIG24 . The third test circuit may include two inverters, and the input of the third test circuit may be electrically connected to the output OUT_AZ of the third operation circuit (i.e., the display reset signal terminal OUT_AZn of the logic operation circuit). As shown in FIG24 , the third test circuit may include a seventeenth inverter 417 and an eighteenth inverter 418. The input of the seventeenth inverter 417 is connected to the output OUT_AZ of the third operation circuit, and the output of the seventeenth inverter 417 is connected to the input of the eighteenth inverter 418. The output of the eighteenth inverter 418 may serve as the output Test_AZ of the third test circuit (i.e., the test terminal for the display reset signal AZn of the gate drive circuit).

[0329] In an exemplary embodiment, a third test circuit can detect whether the display reset signal AZn outputted from the output terminal OUT_AZ of the third arithmetic circuit is consistent with a target timing. If the display reset signal AZn detected at the output terminal Test_AZ of the third test circuit is inconsistent with the target timing, it indicates that the display reset signal AZn has already experienced an abnormality before entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the abnormal operation of the third arithmetic circuit has caused the display reset signal AZn to be inconsistent with the target timing. If the display reset signal AZn detected at the output terminal Test_AZ of the third test circuit is consistent with the target timing, it indicates that the display reset signal AZn has experienced an abnormality after entering the level shifter circuit 300 and the line driver enhancement circuit 400. Therefore, it can be inferred that the third arithmetic circuit is operating normally. Therefore, the display reset signal AZn outputted by the third arithmetic circuit can be tested at the output terminal Test_AZ of the third test circuit to determine whether the third arithmetic circuit is operating normally. In an exemplary embodiment, the output terminal Test_AZ of the third test circuit can be brought out through a pad around the display area. During testing, the signal input terminal of the oscilloscope can be electrically connected to the pad of the output terminal Test_AZ of the third test circuit. The waveform output by the output terminal Test_AZ of the third test circuit is obtained through the oscilloscope, and the waveform output by the output terminal Test_AZ of the third test circuit is compared with the waveform of the target timing to see whether they are consistent. If they are consistent, it indicates that the third operation circuit is working normally, and if they are inconsistent, it indicates that the third operation circuit is working abnormally.

[0330] In an exemplary embodiment, under normal circumstances, the display image is displayed in a display area located in the center of the display substrate. The position of the display area (i.e., the position of the displayed image) is generally fixed. In actual products, the image may be mechanically blocked due to alignment issues, or pixel-level alignment may be required during assembly, requiring the displayed image to be moved. While maintaining the resolution of the displayed image, at least one of the rows and columns may need to be added. Combined with the configuration of the shift register circuit 100, the function of moving the displayed image position can be referred to as the Orbit function. The vertical Orbit function (moving the displayed image in the column direction Y) can be implemented through the addressing configuration of the gate driver circuit, and the horizontal Orbit function (moving the displayed image in the row direction X) can be implemented through the configuration of the data driver circuit.

[0331] As shown in Figures 25a to 25c, a resolution of 3840x3552 and ±8 Orbit Pixel (i.e., 8 rows of pixels offset to the upper or lower side, and 8 columns of pixels offset to the left or right) is used as an example for explanation. Under normal circumstances, as shown in Figure 25a, the displayed image is displayed in the center; in the case of mechanical occlusion in the lower left corner, the displayed image can be moved to the upper right side (+8, +8) by setting the gate drive circuit and the data drive circuit, as shown in Figure 25b, that is, the displayed image is moved 8 columns of pixels to the right and 8 rows of pixels upward; in the case of mechanical occlusion in the upper left corner, the displayed image can be moved to the lower right side (-8, +8) by setting the gate drive circuit and the data drive circuit, as shown in Figure 25c, that is, the displayed image is moved 8 rows of pixels downward and 8 columns of pixels to the right; in the case of mechanical occlusion in the upper right corner, the displayed image can be moved to the lower left side (-8, +8) by setting the gate drive circuit and the data drive circuit, as shown in Figure 25d. , -8), that is, the displayed image is moved downward by 8 rows of pixels and to the left by 8 columns of pixels; in the case of mechanical occlusion on the right side, the displayed image can be moved to the left side (0, -8) by setting the data driving circuit as shown in FIG25e, that is, the displayed image is moved to the left by 8 columns of pixels; in the case of mechanical occlusion on the left side, the displayed image can be moved to the right side (0, +8) by setting the data driving circuit as shown in FIG25f, that is, the displayed image is moved to the right by 8 columns of pixels; in the case of mechanical occlusion on the upper side, the displayed image can be moved to the lower side (-8, 0) by setting the gate driving circuit as shown in FIG25g, that is, the displayed image is moved downward by 8 rows of pixels; in the case of mechanical occlusion on the lower side, the displayed image can be moved to the upper side (+8, 0) by setting the gate driving circuit as shown in FIG25h, that is, the displayed image is moved upward by 8 rows of pixels.

[0332] In an exemplary embodiment, the order of row-by-row scanning can be adjusted by configuring a gate drive circuit. The scanning order can include forward scanning and reverse scanning. Forward scanning can be performed from top to bottom (i.e., scanning in the opposite direction of the column direction Y), and reverse scanning can be performed from bottom to top (i.e., scanning in the column direction Y). The gate drive circuit can be configured to convert forward scanning to reverse scanning, or vice versa. Under these two scanning orders, the displayed image can be flipped along the first centerline (the first centerline can be the centerline of the displayed image extending along the pixel row direction). This can be applied to VR binocular display systems. Figure 26a shows image "F" displayed after forward scanning, and Figure 26b shows image "F" displayed after reverse scanning.

[0333] In an exemplary embodiment, the architecture of the gate drive circuit for realizing the forward and reverse scanning functions and the Orbit function is shown in FIG27. In a display substrate with a resolution of 3840x3552 and capable of realizing ±8 Orbit Pixel (i.e., 8 rows of pixels offset upward or downward), a total of 3856 rows are required for 3840 resolution and ±8 Orbit Pixel. That is, on the basis of 3840 rows of pixels, 8 rows of pixels on the first side (i.e., the top 8 rows, which can be called Top 8 Orbit Line) and 8 rows of pixels on the second side (i.e., the bottom 8 rows, which can be called Bottom 8 Orbit Line) are added; in order to realize ±8 The function of Orbit shift requires start and end control of ±17 lines (that is, start and end control of 17 lines in the first type of control lines and 17 lines in the second type of control lines). Taking the display of 8 lines shifted up as an example, the control logic for determining the start and end lines of scanning and the forward and reverse scanning is explained: When the displayed image is shifted up by 8 lines of pixels, the initial trigger signal (that is, STV signal) needs to be given to "Orbit8" in the "first side 8 lines" and "Orbit8" in the "second side 8 lines" in Figure 27, that is, "Orbit8" in the "first side 8 lines" and "Orbit8" in the "second side 8 lines". The row is set as the scan start row, and the initial input signals (i.e., STV signals) of the remaining 16 rows in the first category of control rows and the 16 rows in the second category of control rows are cut off. In this way, the "Orbit8" row in the "first side 8 rows" and the "Orbit8" row in the "second side 8 rows" receive the STV trigger signal, and then the forward scan or reverse scan is determined by setting the transmission gate in the gate drive circuit. In the case of reverse scanning, the STV signal can continue to be transmitted to the upper level through the "Orbit8" row in the "second side 8 rows" (i.e., transmitted in the direction of the "Orbit8" row in the first side 8 rows). In the case of forward scanning, the STV signal can be transmitted to the lower level through the "Orbit8" row in the "first side 8 rows" (i.e., transmitted in the direction of the "Orbit8" row in the second side 8 rows). Through the enable signal input to the trigger (e.g., a D trigger) in the gate drive circuit, the "Orbit-8" to "Orbit7" rows in the second category of control rows are reset, and the trigger is set to a high-impedance state. The logic table for scanning the start row can be shown in Table 1, that is, the register value for setting the scan start row (the logic value in Table 1 is the input code of the shift register):

[0334] Table 1: Logic table for scanning starting row

[0335] In Table 1, the logical value may be the logical value of the scan start row, and the scan start row represents the start row in the "8 rows on the first side" and the "8 rows on the second side". For example, the scan start row +8 in Table 1 represents that "Orbit8" in the "8 rows on the first side" and "Orbit8" in the "8 rows on the second side" are used as the start rows; the scan start row -8 in Table 1 represents that "Orbit-8" in the "8 rows on the first side" and "Orbit-8" in the "8 rows on the second side" are used as the start rows.

[0336] In an exemplary embodiment, Table 2 shows a start row strobe truth table, Table 3 shows a reset (off) row strobe truth table for the first type of control row, and Table 4 shows a reset (off) row strobe truth table for the second type of control row:

[0337] Table 2: Start Row Strobe Truth Table

[0338] In Table 2, Z1 to Z8 are the output scan start row control signals of Orbit1 to Orbit8 in the first and second control rows respectively, Z_1 to Z_8 are the output scan start row control signals of Orbit-1 to Orbit-8 in the first and second control rows respectively, and Z0 is the output scan start row control signal of the 3840th row as the starting row.

[0339] Table 3: Reset (cutoff) row strobe truth table for the first type of control row

[0340] Table 4: Reset (cutoff) row strobe truth table for the second type of control row

[0341] In Tables 2 to 4, A0 to A4 are input control signals of the input control terminals.

[0342] In an exemplary embodiment, Figure 28a shows a circuit schematic diagram of a gate drive circuit that implements the first type of control row in Figure 27; Figure 28b shows a circuit schematic diagram of a gate drive circuit that implements the second type of control row in Figure 27, and Figure 29 shows a schematic diagram of a shift control module. The shift control module can be a functional module in the gate drive circuit that can implement the first type of control row and the second type of control row in Figure 27.

[0343] Taking Orbit8 (i.e., shifting the displayed image up by 8 lines) as an example, the working principle of the shift control module shown in FIG29 is illustrated: as shown in FIG29, the values ​​of the input control signals from the first input terminal A0 to the fifth input control terminal A4 are set to 01000, and the shift control module (which can be called the Orbit Controller circuit module) outputs a scan start line control signal [Z_8: Z_1, Z0: Z8] with a value of 000000000000000001. The Orbit8 row scan start control transmission gate in the first type of control line (which can be called the T-Start / End Control Line, which can include the first type of offset shift register circuit P100) and the second type of control line (which can be called the B-Start / End Control Line, which can include the second type of offset shift register circuit P100) is turned on, and the initial STV inputted by the initial signal input terminal IN_STV is inputted into the D flip-flop in the shift register circuit 100; the remaining 32 row scan start control transmission gates (including 16 row scan start control transmission gates and the B-Start / End Control Line in the T-Start / End Control Line) are turned on. The 16-row scan start control transmission gate in Line is turned off, and the initial signal STV is cut off. The forward and reverse scan control signals are GSD_FW and GSD_BW, where GSD_FW and GSD_BW are mutually inverse signals (for example, mutually inverse signals can be: when the GSD_FW signal is 1, the GSD_BW signal is 0; when the GSD_FW signal is 0, the GSD_BW signal is 1). When GSD_FW=1 and GSD_BW=0, the transmission gate controlled by the forward and reverse scan signals in the Orbit8 row of the first type of control row (which can be called Top Orbit8) is opened, and the Orbit8 row of the second type of control row (which can be called Bottom Orbit8) is opened. The transmission gate controlled by the forward and reverse scan signals in the shift register circuit in row Orbit8 (i.e., the forward and reverse scan control circuit) is turned off, realizing the forward scan function, and vice versa, realizing the reverse scan function; the output reset control signal [T_7:T_1,T0:T8] has a value of 111111111111111111, and the value of [T_7_:T_1_,T0_:T8_] is 00000000000000000. After passing through the NAND gate and NOT gate in the reset control circuit 10-3, the reset signal input to the row driver enhancer (Driver) is 0. All B-Start / End Control Line rows except Bottom Orbit8 are reset to a high-impedance state, and no gate driver timing signal is output.

[0344] As shown in Figures 28a and 28b, a transmission gate is incorporated into the gate drive register circuit to prevent erroneous signal input into the shift register circuit. This prevents noise signals from causing abnormal output from the row drive boost circuit (gate drive), reduces the risk of display anomalies, and improves product yield. The operating principle diagram is shown in Figure 27. During forward scanning, the two transmission gate control signals between the B-Start / End Control Line shift registers are inverse signals (Z* and Z*_), preventing the initial signal STV from transmitting in the reverse direction. Similarly, during reverse scanning, the same function can be achieved.

[0345] The shift control module (Orbit Controller) shown in Figure 29 can be a decoder that can implement the logical truth tables shown in Tables 2 to 4. Figures 30a and 30b show the operating principle diagrams of the first decoding circuit in the shift control module (Orbit Controller) in Figure 29, and Figure 31 shows the operating principle diagram of the second decoding circuit in the shift control module (Orbit Controller) in Figure 29. The first decoding circuit can be a 3-wire to 8-wire decoder, and the second decoder circuit can be a temperature decoder circuit. The 3-wire to 8-wire decoder circuit shown in Figures 30a and 30b can implement the logical truth table functions shown in Table 2; the thermometer code decoder circuit shown in Figures 31a and 31b can implement the logical truth table functions shown in Tables 3 and 4.

[0346] In an exemplary embodiment, the gate drive circuit may further include a shift control circuit (i.e., a shift control module as shown in FIG. 29 ). As shown in FIG. 30 a and FIG. 30 b , the shift control circuit may include a scan control circuit (SZ0 to SZ8, SZ_1 to SZ_8) and input control terminals (IN_A0 to IN_A4). As shown in FIG. 28 a and FIG. 28 b , the row control circuit 01 may include an initial row control circuit 01 - 1, and the row control terminals may include initial row control terminals (IN_Z8 to IN_Z0, IN_Z_1 to IN_Z_8).

[0347] The initial row control circuit 01-1 has an input terminal connected to the initial signal terminal IN_STV and a control terminal connected to the initial row control terminal. The circuit is configured to receive an initial signal from the initial signal terminal and an initial row control signal from the initial row control terminal. Under control of the initial control signals (Z8 to Z0, Z_1 to Z_8), the circuit selects one stage from the 2S+1 first-type offset shift register circuits as the first-type initial shift register circuit and selects one stage from the 2S+1 second-type offset shift register circuits as the second-type initial shift register circuit.

[0348] The input end of the scanning control circuit is connected to the input control end, and the output end is connected to the initial row control end. It is configured to receive an input control signal from the input control end, generate an initial row control signal under the control of the input control signal, and provide the initial row control signal to the initial row control end.

[0349] In an exemplary embodiment, as shown in FIG31 , the shift control circuit may further include a cutoff row control circuit (second cutoff row control sub-circuits KT_1 to KT_7, first cutoff row control sub-circuits KT1 to KT7). As shown in FIG28 a and FIG28 b , the gate drive circuit may further include a reset control circuit 10 - 3 and reset control terminals (IN_T0 to IN_T8, IN_T_1 to IN_T_8).

[0350] The input terminal of the cutoff line control circuit is connected to the input control terminal, and the output terminal is connected to the reset control terminal. The circuit is configured to receive an input control signal from the input control terminal, generate a reset control signal under the control of the input control signal, and provide the reset control signal to the reset control terminal circuit.

[0351] The reset control circuit is configured to receive a reset control signal through a reset control terminal, and under the control of the reset control signal, the multi-stage offset shift register circuit is set to a high impedance state or a working state.

[0352] In an exemplary embodiment, as shown in FIG6a to FIG6b, FIG28a to FIG28b, and FIG30a to FIG30b, the number of scan control circuits (KT_n, KTn) may be 2S+1, the multi-stage offset shift register circuit includes 2S+1 stages of first-type offset shift register circuits P100 (as shown in FIG6a and FIG28a) and 2S+1 stages of second-type offset shift register circuits P100 (as shown in FIG6b and FIG28b), the initial row control circuit 01-1 may include 2S+1 first-type initial row control circuits 01-11 and 2S+1 second-type initial row control circuits 01-12, the initial signal terminal may include 2S+1 first-type initial signal terminals and 2S+1 second-type initial signal terminals, the initial row control terminal includes 2S+1 first initial row control terminals and 2S+1 second initial row control terminals, and S is an integer greater than or equal to 0;

[0353] The 2S+1 first-type initial row control circuits have input terminals connected to the 2S+1 first-type initial signal terminals, output terminals connected to the input terminals of the 2S+1-stage first-type offset shift register circuits, first control terminals connected to the 2S+1 first initial row control terminals, and second control terminals connected to the 2S+1 second initial row control terminals.

[0354] The 2S+1 second-type initial row control circuits have input terminals connected to the 2S+1 second-type initial signal terminals, output terminals connected to the input terminals of the 2S+1-stage second-type offset shift register circuits, first control terminals connected to the 2S+1 first initial row control terminals, and second control terminals connected to the 2S+1 second initial row control terminals.

[0355] In the 2S+1 scanning control circuits, the input end is connected to the input control end, the first output end is connected to 2S+1 first initial row control ends respectively, and the second output end is connected to 2S+1 second initial row control ends respectively.

[0356] In an exemplary embodiment, as shown in FIG30a and FIG30b, the shift control circuit may further include m scan input inverting circuits (SR1 to SR5), and the number of input control terminals is m, as shown in FIG30a and FIG30b, where m is an integer, for example, m may be 1 to 5;

[0357] The m scan input inversion circuits have input terminals connected to the m input control terminals respectively, and are configured to invert the input control signals of the m input control terminals respectively to obtain inverted signals of the input control signals, and output the inverted signals of the input control signals through the output terminals;

[0358] An input terminal of the scan control circuit is connected to at least part of the m input control terminals and the output terminals of the m scan input inverter circuits.

[0359] In an exemplary embodiment, each scan input inversion circuit may include an inverter, an input terminal of the inverter is connected to the corresponding input control terminal, and an output terminal may serve as an inverting signal terminal of the corresponding input control terminal.

[0360] In an exemplary embodiment, as shown in FIG30 a to FIG30 c , the m input control terminals may include first to fifth input control terminals IN_A0 to IN_A4, the m scan input inverting circuits may include first to fifth scan input inverting circuits RS1 to RS5, and at least one scan control circuit may include an eighth NAND gate 308, a ninth NAND gate 309, a sixth NOR gate 506, and a nineteenth inverter 419;

[0361] In the eighth NAND gate 308, the first input terminal is connected to the first input control terminal or the output terminal of the first scan input inverting circuit, the second input terminal is connected to the second input control terminal or the output terminal of the second scan input inverting circuit, the third input terminal is connected to the third input control terminal or the output terminal of the third scan input inverting circuit, and the output terminal is connected to the second input terminal of the sixth NOR gate 506;

[0362] In the ninth NAND gate 309, a first input terminal is connected to the fourth input control terminal or the output terminal of the fourth scan input inverting circuit, a second input terminal is connected to the fifth input control terminal or the output terminal of the fifth scan input inverting circuit, and an output terminal is connected to the first input terminal of the sixth NOR gate 506;

[0363] The output terminal of the sixth NOR gate 506 is connected to the input terminal of the nineteenth inverter 419 and the corresponding first initial row control terminal, and the output terminal of the nineteenth inverter 419 is connected to the corresponding second initial row control terminal.

[0364] In an exemplary embodiment, as shown in Figures 28a and 28b, at least one initial row control circuit may include a fifth transmission gate 205, the input terminal of the fifth transmission gate is connected to the corresponding initial signal terminal, the output terminal is connected to the input terminal of the corresponding offset shift register circuit, the first control terminal is connected to the corresponding first initial row control terminal, and the second control terminal is connected to the corresponding second initial row control terminal.

[0365] In an exemplary embodiment, as shown in FIG31 , the number of cutoff row control circuits (KT_n, KTn) may be 2S. As shown in FIG6 a and FIG6 b , the reset control circuit 10-3 may include 2S first-type reset control circuits (as shown in FIG6 a ) and 2S second-type reset control circuits (as shown in FIG6 b ), and the reset control terminal may include 2S first reset control terminals and 2S second reset control terminals.

[0366] In the 2S first-type reset control circuits, the input terminals are respectively connected to the 2S first reset control terminals (OUT_Tn, OUT_T_n), and the output terminals are respectively connected to the 2S-stage first-type offset shift register circuits. In the direction from the first-type offset shift register circuit to the second-type offset shift register circuit, the 2S-stage first-type offset shift register circuit is the first stage to the 2S-stage in the 2S+1-stage first-type offset shift register circuit.

[0367] In the 2S second-type reset control circuits, the input terminals are respectively connected to the 2S second reset control terminals, and the output terminals are respectively connected to the 2S-stage second-type offset shift register circuits. In the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, the 2S-stage second-type offset shift register circuit is the first stage to the 2S-stage second-type offset shift register circuit in the 2S+1-stage second-type offset shift register circuit.

[0368] In the 2S cut-off row control circuits, the input end is connected to the input control end, the first output end is connected to the 2S first reset control ends respectively, and the second output end is connected to the 2S second reset control ends respectively.

[0369] In an exemplary embodiment, as shown in FIG28 a , at least one reset control circuit 10 - 3 includes a tenth NAND gate 310 and a twentieth inverter 420 ;

[0370] In the first type reset control circuit, the input terminal of the tenth NAND gate is connected to the corresponding first reset control terminal, the output terminal is connected to the twelfth inverter, and the output terminal of the twelfth inverter is connected to the corresponding first type offset shift register circuit;

[0371] In the second type reset control circuit, the input terminal of the tenth NAND gate is connected to the corresponding second reset control terminal, the output terminal is connected to the twelfth inverter, and the output terminal of the twelfth inverter is connected to the corresponding second type offset shift register circuit.

[0372] In an exemplary embodiment, as shown in FIG31 , the shift control circuit may further include m reset input inverting circuits FRn, and the number of input control terminals IN_An is m;

[0373] The m reset input inverting circuits have input terminals connected to the m input control terminals respectively, and are configured to invert the input control signals of the m input control terminals respectively to obtain inverted signals of the input control signals, and output the inverted signals of the input control signals through the output terminals;

[0374] An input terminal of the cutoff row control circuit is connected to at least part of the m input control terminals and the output terminals of the m reset input inverter circuits.

[0375] In an exemplary embodiment, as shown in FIG31 , the m input control terminals may include a first input control terminal IN_A0 to a fifth input control terminal IN_A5, the m reset input inverting circuits may include a first reset input inverting circuit to a fifth reset input inverting circuit, and the shift control circuit may further include a first input sub-circuit KR1 to an S-th input sub-circuit KR5; the 2S cut-off row control circuits may include S-1 first cut-off row sub-circuits (KT_1 to KT_7) and S+1 second cut-off row sub-circuits (KT0 to KT8);

[0376] In the S-1 first cutoff row sub-circuits, the first input terminals are connected to the output terminals of the first input sub-circuit to the S-1th input sub-circuit, respectively; the second input terminals are connected to the output terminal of the S-th input sub-circuit; the first output terminals are connected to the first to S-1th first reset control terminals (OUT_T_1 to OUT_T_7), respectively; and the second output terminals are connected to the first to S-1th second reset control terminals (OUT_T_1 to OUT_T_7), respectively.

[0377] In the S+1 second cut-off row sub-circuits, the input end of the first second cut-off row sub-circuit is connected to the fifth input control end; the first input ends of the second to S-th second cut-off row sub-circuits are connected to the output ends of the fifth reset input inverting circuit, and the second input ends are respectively connected to the output ends of the first input sub-circuit to the S-1-th input sub-circuit; in the S+1-th second cut-off row sub-circuit, the first input end is connected to the output end of the fifth reset input inverting circuit, and the second input end is connected to the four-input control end; in the S+1 second cut-off row sub-circuit, the first output end is respectively connected to the S-th to 2S+1 first reset control ends, and the second output end is respectively connected to the S-th to 2S+1 second reset control ends.

[0378] In an exemplary embodiment, as shown in Figures 30a to 31, the value of S may be 8. In an exemplary embodiment, as shown in Figure 31, the reset input inversion circuit may include an inverter, the input terminal of the inverter may be connected to the corresponding input control terminal, and the output terminal may serve as an inverting signal terminal of the corresponding input control terminal.

[0379] In an exemplary embodiment, as shown in FIG31 , the first input sub-circuit KR1 may include an eleventh NAND gate 311. In the eleventh NAND gate, a first input terminal is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, an output terminal is connected to the first input terminal and the first input terminal of the S-1th first cut-off row sub-circuit, an output terminal is connected to the S-1th first cut-off row sub-circuit and the second second cut-off row sub-circuit, and the output terminal of the eleventh NAND gate serves as the output terminal of the first input sub-circuit.

[0380] The second input sub-circuit KR2 may include a twelfth NAND gate 312. In the twelfth NAND gate, a first input terminal is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the S-2 th first cut-off row sub-circuit and the third second cut-off row sub-circuit. The output terminal of the twelfth NAND gate serves as the output terminal of the second input sub-circuit.

[0381] The third input sub-circuit KR3 may include a thirteenth NAND gate 313, a seventh NOR gate 507, and a twenty-first inverter 421. The seventh NOR gate 507 has a first terminal connected to the output terminal of the first reset input inverter circuit, a second terminal connected to the output terminal of the second reset input inverter circuit, and an output terminal connected to the input terminal of the twenty-first inverter 421. The output terminal of the twenty-first inverter 421 is connected to the second input terminal of the thirteenth NAND gate 313, the first input terminal of the thirteenth NAND gate 313 is connected to the output terminal of the third reset input inverter circuit, the output terminal of the thirteenth NAND gate is connected to the S-3rd first cut-off row sub-circuit and the fourth second cut-off row sub-circuit, and the output terminal of the thirteenth NAND gate serves as the output terminal of the third input sub-circuit.

[0382] The fourth input sub-circuit KR4 may include a twenty-second inverter 422, the input end of the twenty-second inverter being connected to the output end of the third reset input inverter circuit, the output end of the twenty-second inverter being connected to the S-4th first cut-off row sub-circuit and the fifth second cut-off row sub-circuit, and the output end of the twenty-second inverter 422 serving as the output end of the fourth input sub-circuit;

[0383] The fifth input sub-circuit KR5 may include a fourteenth NAND gate 314, an eighth NOR gate 508, and a twenty-third inverter 423. The fourteenth NAND gate 314 has a first terminal connected to the output of the first reset input inverter circuit, a second terminal connected to the output of the second reset input inverter circuit, and an output terminal connected to the input of the twenty-third inverter 423. The output of the twenty-third inverter 423 is connected to the second input of the eighth NOR gate 508, the first input of the eighth NOR gate 508 is connected to the output of the third reset input inverter circuit, the output of the eighth NOR gate 508 is connected to the (S-5)th first cut-off row sub-circuit and the sixth second cut-off row sub-circuit, and the output of the eighth NOR gate 508 serves as the output of the fifth input sub-circuit.

[0384] The sixth input sub-circuit KR6 may include a ninth NOR gate 509. In the ninth NOR gate 509, a first input terminal is connected to the output terminal of the second reset input inverting circuit, a second input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the (S-6)th first cut-off row sub-circuit and the seventh second cut-off row sub-circuit. The output terminal of the ninth NOR gate 509 serves as the output terminal of the sixth input sub-circuit.

[0385] The seventh input sub-circuit KR7 may include a tenth NOR gate 510. In the tenth NOR gate 510, a first input terminal is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the S-7th first cut-off row sub-circuit and the eighth second cut-off row sub-circuit. The output terminal of the tenth NOR gate 510 serves as the output terminal of the seventh input sub-circuit.

[0386] The eighth input sub-circuit KR7 may include an eleventh NOR gate 511, a twenty-fourth inverter 424 and a twenty-fifth inverter 425. In the twenty-fourth inverter 424, the input terminal is connected to the third input control terminal, and the output terminal is connected to the first input terminal of the eleventh NOR gate 511; in the eleventh NOR gate 511, the second input terminal is connected to the output terminal of the fifth reset input inverter circuit, and the output terminal is connected to the input terminal of the twenty-fifth inverter 425. The output terminal of the twenty-fifth inverter 425 is connected to the S-1 first cut-off row sub-circuits, and the output terminal of the twenty-fifth inverter 425 serves as the output terminal of the eighth input sub-circuit.

[0387] In an exemplary embodiment, as shown in FIG31 , the first cutoff row sub-circuit (KT_n) may include a twelfth NOR gate 512 and a twenty-sixth inverter 426. In the twelfth NOR gate 512, a first input terminal is connected to a corresponding input sub-circuit among the first to S-1th input sub-circuits, a second input terminal is connected to the Sth input sub-circuit, an output terminal is connected to the twenty-sixth inverter 426 and a corresponding first reset control terminal, and an output terminal of the twenty-sixth inverter 426 is connected to a corresponding second reset control terminal; the output terminal of the twenty-sixth inverter 426 serves as the second output terminal, and the output terminal of the twelfth NOR gate 512 serves as the first output terminal.

[0388] In an exemplary embodiment, as shown in FIG31 , the first second cutoff row sub-circuit KT0 includes a twenty-seventh inverter 427 , wherein the input terminal of the twenty-seventh inverter 427 is connected to the fifth input control terminal, and the output terminal is connected to the first second reset control terminal OUT_T0_;

[0389] The second to Sth second-cutoff row sub-circuits (KT1 to KT7) include a fifteenth NAND gate 315, a twenty-eighth inverter 428, a thirteenth NOR gate 513, and a twenty-eighth inverter 429. The fifteenth NAND gate 315 has a first input connected to the output of the fifth reset input inverter circuit, a second input connected to the corresponding input sub-circuit, and an output connected to the input of the twenty-eighth inverter 428. The output of the twenty-eighth inverter 428 is connected to the first input of the thirteenth NOR gate 513, the second input of the thirteenth NOR gate 513 is connected to the fifth input control terminal, and the output of the thirteenth NOR gate 513 is connected to the input of the twenty-ninth inverter 429 and the corresponding second reset control terminal. The output of the twenty-ninth inverter 429 is connected to the corresponding first reset control terminal. The output of the thirteenth NOR gate 513 serves as the second output of the corresponding second-cutoff row sub-circuit, and the output of the twenty-ninth inverter 429 serves as the first output of the corresponding second-cutoff row sub-circuit.

[0390] The (S+1)th second cutoff row circuit KT8 includes a sixteenth NAND gate 316, a fourteenth NOR gate 514 and a thirtieth inverter 430. In the sixteenth NAND gate 316, the first input terminal is connected to the output terminal of the fifth reset input inverter circuit, the second input terminal is connected to the fourth input control terminal, and the output terminal is connected to the first input terminal of the fourteenth NOR gate 514; in the fourteenth NOR gate 514, the second input terminal is connected to the output terminal of the first input sub-circuit, the output terminal is connected to the input terminal of the thirtieth inverter 430 and the (2S+1)th first reset control terminal, and the output terminal of the thirtieth inverter 430 is connected to the (2S+1) second reset control terminal.

[0391] In an exemplary embodiment, as shown in FIG28 a and FIG28 b , the gate driving circuit may further include 2S first-type offset transmission control circuits P10-11 (as shown in FIG28 a ) and 2S second-type offset transmission control circuits P10-12 (as shown in FIG28 b ); two adjacent stages of the first-type offset shift register circuits are cascade-connected via one of the first-type offset transmission control circuits, and two adjacent stages of the second-type offset shift register circuits are cascade-connected via one of the second-type offset transmission control circuits;

[0392] In the 2S first-type offset transmission control circuits, the first control terminals are respectively connected to the 2S second initial row control terminals, and the second control terminals are respectively connected to the 2S first initial row control terminals; in the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, the 2S first initial row control terminals are the first to the 2Sth of the 2S+1 first initial row control terminals, and the 2S second initial row control terminals are the first to the 2Sth of the 2S+1 second initial row control terminals;

[0393] In the 2S second-type offset transmission control circuits, the first control terminals are respectively connected to the 2S second initial row control terminals, and the second control terminals are respectively connected to the 2S first initial row control terminals.

[0394] In an exemplary embodiment, as shown in FIG28 a and FIG28 b , in a direction from a first-type offset shift register circuit to a second-type offset shift register circuit, in two adjacent stages of first-type offset shift register circuits, the input terminal of the first-type offset transmission control circuit is connected to the output terminal of the first-type offset shift register circuit of the previous stage, and the output terminal of the offset transmission control circuit is connected to the input terminal of the offset shift register circuit of the next stage;

[0395] In the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, in two adjacent stages of the second-type offset shift register circuit, the input end of the second-type offset transmission control circuit is connected to the output end of the first-type offset shift register circuit of the previous stage, and the output end of the offset transmission control circuit is connected to the input end of the offset shift register circuit of the next stage.

[0396] In an exemplary embodiment, as shown in FIG28a and FIG28b, the row control circuit may further include 2S+1 first-type forward and reverse scan control circuits 01-21 and 2S+1 second-type forward and reverse scan control circuits 01-22, and the row control terminal may further include a first forward and reverse scan control terminal GSD_FW and a second forward and reverse scan control terminal GSD_BW;

[0397] The output ends of the 2S+1 first-type initial row control circuits are connected to the input ends of the 2S+1-stage first-type offset shift register circuit through the 2S+1 first-type forward and reverse scan control circuits; the output ends of the 2S+1 second-type initial row control circuits are connected to the input ends of the 2S+1-stage second-type offset shift register circuit through the 2S+1 second-type forward and reverse scan control circuits;

[0398] The 2S+1 first-type forward and reverse scan control circuits have input terminals connected to the output terminals of the 2S+1 first-type initial row control circuits, output terminals connected to the input terminals of the 2S+1-stage first-type offset shift register circuits, a first control terminal connected to the first forward and reverse scan control terminal, and a second terminal connected to the second forward and reverse scan control terminal.

[0399] In the 2S+1 second-type forward and reverse scan control circuits, the input ends are respectively connected to the output ends of the 2S+1 second-type initial row control circuits, the output ends are respectively connected to the input ends of the 2S+1-level second-type offset shift register circuits, the first control end is connected to the second forward and reverse scan control end, and the second end is connected to the first forward and reverse scan control end.

[0400] In an exemplary embodiment, a scan control circuit may include at least two 3-line to 8-line decoders, 2S+1 expansion circuits, 2S+1 output terminals, and at least one expanded input control terminal. The input control terminals of the scan control circuit include three input terminals of the 3-line to 8-line decoder and at least one expanded input terminal. The input terminals of the 2S+1 expansion circuits are connected to the 2S+1 output terminals of the at least two 3-line to 8-line decoders, and the output terminals of the 2S+1 expansion circuits serve as the 2S+1 output terminals of the scan control circuit. In an exemplary embodiment, the scan control circuit adds input terminals and expansion circuits to the 3-line to 8-line decoder, which can fully utilize the output states of the decoder and reduce costs. A standard 3-line to 8-line decoder is generally more expensive than a standard 5-line to 32-line decoder. By expanding the output states of the 3-line to 8-line decoder, costs can be effectively reduced.

[0401] In an exemplary embodiment, as shown in Figures 29, 30a, and 30b, the input control terminals of the scan control circuit include a first input control terminal IN_A0 to a fifth input control terminal IN_A4, and at least two 3-line-8-line decoders include a first 3-line-8-line decoder as shown in Figure 30a and a second 3-line-8-line decoder as shown in Figure 30b. The three input terminals (IN_A0 to IN_A2) of the first 3-line-8-line decoder serve as the first input control terminal to the third input control terminal of the scan control circuit, and the inverted signal terminals (A0_ to A2_) of the first input control terminal to the third input control terminal serve as the input terminals of the second 3-line-8-line decoder.

[0402] In an exemplary embodiment, as shown in FIG30 a and FIG30 b , the 2S+1 expansion circuits include 2S first expansion circuits and one second expansion circuit; the first expansion circuit and the second expansion circuit both include a ninth NAND gate, a sixth NOR gate, and a nineteenth inverter (i.e., the eighth NAND gate 308 is removed from SZ0 to SZ7 in FIG30 a and FIG30 b ); the second expansion circuit further includes an eighth NAND gate (SZ8 in FIG30 a );

[0403] In the ninth NAND gate, the first input terminal is connected to the fourth input control terminal or the inverted signal terminal of the fourth input control terminal, the second input terminal is connected to the fifth input control terminal or the inverted signal terminal of the fifth input control terminal, and the output terminal is connected to the first input terminal of the sixth NOR gate;

[0404] The output end of the sixth NOR gate is connected to the input end of the nineteenth inverter, the output end of the sixth NOR gate serves as an output end of the scan control circuit, and the output end of the nineteenth inverter serves as an inverted signal end of an output end of the scan control circuit;

[0405] In the first expansion circuit, the second input terminal of the sixth NOR gate is connected to one output terminal of the 3-line to 8-line decoder, and in the second expansion circuit, the second input terminal of the sixth NOR gate is connected to the output terminal of the eighth NAND gate;

[0406] In the eighth NAND gate, the three input terminals are connected to the first input control terminal to the third input control terminal respectively, and the output terminal is connected to the second input terminal of the sixth NOR gate.

[0407] As shown in FIG29 , the shift control module may include multiple input control terminals and multiple output terminals. The multiple input control terminals may include a first input control terminal IN_A 0, a second input control terminal IN_A 1, a third input control terminal IN_A 2, a fourth input control terminal IN_A 3, and a fifth input control terminal IN_A 4. The multiple output terminals may include: 8 scan start row control terminals and corresponding inverted signal terminals, 9 multiplexed scan start row control terminals and corresponding inverted signal terminals, 8 reset control terminals of the first type of control rows, 8 multiplexed reset control terminals of the first type of control rows, 8 reset control terminals of the second type of control rows, and 8 multiplexed reset control terminals of the second type of control rows. The 8 scan start row control terminals may include a first scan start row control terminal OUT_Z1 to an eighth scan start row control terminal OUT_Z8, and the inverted signal terminals of the 8 scan start row control terminals. The inverted signal terminals OUT_Z1_ of the first scan start row control terminal OUT_Z1 to the inverted signal terminal OUT_Z8_ of the eighth scan start row control terminal OUT_Z8; the nine multiplexed scan start row control terminals may include the first multiplexed scan start row control terminal OUT_Z0, the second multiplexed scan start row control terminal OUT_Z_1 to the ninth multiplexed scan start row control terminal OUT_Z_8, and the inverted signal terminals of the nine multiplexed scan start row control terminals may include the inverted signal terminal of the first multiplexed scan start row control terminal OUT_Z0 OUT_Z0_, the inverted signal terminal OUT_Z8_ of the second multiplexed scan start row control terminal OUT_Z_1 to the ninth multiplexed scan start row control terminal OUT_Z_8; the reset control terminals of the eight first-class control rows may include the first reset control terminal OUT_T1 of the first-class control row to the eighth reset control terminal OUT_T8 of the first-class control row; the multiplexed reset control terminals of the eight first-class control rows may include the first multiplexed reset control terminal OUT_T0 of the first-class control row, the second multiplexed reset control terminal OUT_T _1 to the eighth multiplexed reset control terminal OUT_T_7 of the first type of multiplexed control row; the reset control terminals of the 8 second type control rows can include the first reset control terminal OUT_T1_ of the second type control row to the eighth reset control terminal OUT_T8_ of the second type control row; the multiplexed reset control terminals of the 8 second type control rows can include the first multiplexed reset control terminal OUT_T0_ of the second type control row, the second multiplexed reset control terminal OUT_T_1_ of the second type control row to the eighth multiplexed reset control terminal OUT_T_7_ of the second type control row.

[0408] In an exemplary embodiment, in the shift control module, the first reset control terminal OUT_T1_ of the second-type control row through the eighth reset control terminal OUT_T8_ of the second-type control row can be respectively the inverted signal terminals of the first reset control terminal OUT_T1 through the eighth reset control terminal OUT_T8 of the first-type control row; and the first multiplexed reset control terminal OUT_T0_ of the second-type control row through the eighth multiplexed reset control terminal OUT_T_7_ of the second-type control row can be respectively the inverted signal terminals of the first multiplexed reset control terminal OUT_T0 through the eighth multiplexed reset control terminal OUT_T_7 of the first-type control row. By configuring the inverted signal terminals, the circuit structure can be effectively reduced and circuit utilization can be improved.

[0409] As shown in Figures 30a and 30b, the first decoder circuit (which can be a 3-line-8-line decoder circuit) may include 8 scan start row control circuits, 9 multiplexed scan start row control circuits, and 5 scan reverse circuits. The 8 scan start row control circuits may include the first scan start row control circuit SZ1 to the eighth scan start control circuit SZ8; the 9 multiplexed scan start row control circuits may include the first multiplexed scan start row control circuit SZ0, the second multiplexed scan start row control circuit SZ_1 to the ninth multiplexed scan start row control circuit SZ_8; the 5 scan reverse circuits may include the first scan reverse circuit SR1 to the fifth scan reverse circuit SR5.

[0410] As shown in Figures 30a and 30b, the first scanning inverter circuit SR1 to the fifth scanning inverter circuit SR5 can each include an inverter, wherein the input end of the inverter in the first scanning inverter circuit SR1 is connected to the first input control terminal IN_A0; the input end of the inverter in the second scanning inverter circuit SR2 is connected to the second input control terminal IN_A1; the input end of the inverter in the third scanning inverter circuit SR3 is connected to the third input control terminal IN_A2; the input end of the inverter in the fourth scanning inverter circuit SR4 is connected to the fourth input control terminal IN_A3; and the input end of the inverter in the fifth scanning inverter circuit SR5 is connected to the fifth input control terminal IN_A4.

[0411] As shown in Figure 30c, each scan start control circuit and each multiplexed scan start row control circuit (i.e., scan control circuit) may include an eighth NAND gate 308, a ninth NAND gate 309, a sixth NOR gate 506, and a nineteenth inverter 419, wherein the first input terminal of the eighth NAND gate 308 is connected to the first input control terminal IN_A0 of the shift control module or to the output terminal of the first scan inverting circuit SR1, the second input terminal of the eighth NAND gate 308 is connected to the second input control terminal IN_A1 of the shift control module or to the output terminal of the second scan inverting circuit SR2, the third input terminal of the eighth NAND gate 308 is connected to the third input control terminal IN_A2 of the shift control module or to the output terminal of the third scan inverting circuit SR3, and the output terminal of the eighth NAND gate 308 is connected to the first input terminal of the sixth NOR gate 506. A first input terminal of the ninth NAND gate 309 is connected to the fourth input control terminal IN_A3 of the shift control module or to the output terminal of the fourth scan inverting circuit SR4. A second input terminal of the ninth NAND gate 309 is connected to the fifth input control terminal IN_A4 of the shift control module or to the output terminal of the fifth scan inverting circuit SR5. The output terminal of the ninth NAND gate 309 is connected to the second input terminal of the sixth NOR gate 506. The output terminal of the sixth NOR gate 506 is connected to the input terminal of the nineteenth inverter 419. The output terminal of the sixth NOR gate 506 may also be connected to one of the scan start row control terminals OUT_Zm, the output terminal of the nineteenth inverter 419 may be connected to the negated signal terminal OUT_Zm of one of the scan start row control terminals OUT_Zm, or the output terminal of the sixth NOR gate 506 may be connected to one of the multiplexed scan start row control terminals OUT_Z_m, and the output terminal of the nineteenth inverter 419 may be connected to the negated signal terminal OUT_Z_m of one of the multiplexed scan start row control terminals OUT_Z_m.

[0412] As shown in Figure 31, the second decoder circuit may include multiple reset control circuits, and the multiple reset control circuits may include 8 reset control circuits KTm, 8 multiplexed reset control circuits KT_m, 9 input sub-circuits, and 4 inverting sub-circuits; the 8 reset control circuits KTm may include a first reset control circuit KT1 to an eighth reset control circuit KT8; the 8 multiplexed reset control circuits KT_m may include a first multiplexed reset control circuit KT0, a second multiplexed reset control circuit KT_1 to an eighth multiplexed reset control circuit KT_7; the 9 input sub-circuits may include a first input sub-circuit KR1 to an eighth input sub-circuit KR8, and the 4 inverting sub-circuits may include a first inverting sub-circuit FR1 to a fourth inverting sub-circuit FR4.

[0413] The first reset inverting sub-circuit FR1 to the fourth reset inverting sub-circuit FR4 may each include an inverter, wherein the input end of the inverter in the first reset inverting sub-circuit FR1 is connected to the first input control terminal IN_A0, the input end of the inverter in the second reset inverting sub-circuit FR2 is connected to the second input control terminal IN_A1, the input end of the inverter in the third reset inverting sub-circuit FR3 is connected to the third input control terminal IN_A3, and the input end of the inverter in the fourth reset inverting sub-circuit FR4 is connected to the fourth input control terminal IN_A4.

[0414] Taking T1 and T_7 as examples to illustrate the working principle of the temperature decoder in Figure 31, the input values ​​of the shift register circuit are set as follows: From the logic truth table 3, we can see that Expand the logical truth table related to T1 in Table 3 to the logical truth table shown in Figure 5. Item A3 can be eliminated in the logical expression, and the logical expression of T1 is simplified to According to the simplified expression of T1, its logic circuit consists of a NOT gate, a NAND gate, and a NOR gate, as shown in the first reset control circuit KT1 and the first input sub-circuit KR1 in Figure 31. It can be seen from the logic truth table 3 that According to the simplified logic expression of T1, its logic circuit is shown as the eighth multiplexing reset control circuit KT_7 and the first input sub-circuit KR1 in Figure 31.

[0415] Table 5: Extended truth table

[0416] An exemplary embodiment of the present disclosure further provides an operating method of a gate drive circuit, which is applied to the gate drive circuit described in any of the above embodiments, wherein the gate drive circuit includes a multi-stage shift register circuit and a row control circuit, wherein the multi-stage shift register circuit is cascade-connected, and the multi-stage shift register circuit includes a multi-stage intermediate shift register circuit and a 4S+2-stage offset shift register circuit; in the direction of the cascade connection of the multi-stage shift register circuit, the 4S+2-stage offset shift register circuit includes a 2S+1-stage first-type offset shift register circuit located on one side of the multi-stage intermediate shift register circuit, and a 2S+1-stage second-type offset shift register circuit located on the other side of the multi-stage intermediate shift register circuit; the operating method includes:

[0417] The row control circuit receives an initial row control signal, and under the control of the initial row control signal, selects one level from the 2S+1 levels of the first-type offset shift register circuits as the first-type initial shift register circuit, and selects one level from the 2S+1 levels of the second-type offset shift register circuits as the second-type initial shift register circuit; in the direction of the cascade of the multi-stage shift register circuits, the offset direction of the first-type initial shift register circuit and the second-type initial shift register circuit relative to the multi-stage intermediate shift register circuit are consistent, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is a positive integer, and N is less than or equal to S.

[0418] An exemplary embodiment of the present disclosure also provides a display substrate, as shown in Figure 32, the display substrate may include a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel driving circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit may include the gate driving circuit described in any of the above embodiments.

[0419] In an exemplary embodiment, the display substrate provided by the present disclosure can generate the target timing required by the pixel driving circuit using standard signals through the reasonable layout of the first operation circuit, the second operation circuit and the third operation circuit in the logic operation circuit, and can drive a display panel with a pixel density of 4K or above, and can be applied to silicon-based OLED display devices with a pixel density of 4K or above.

[0420] The exemplary embodiments of the present disclosure further provide a display device, as shown in FIG33 , which may include the aforementioned display substrate. The display device of the present disclosure may be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights and rangefinders, computers, mobile phones, wearable devices, and the like.

[0421] The present disclosure provides a gate drive circuit and operating method thereof, a display substrate, and a display device. The gate drive circuit includes a multi-stage shift register circuit and a row control circuit. Under the control of an initial row control signal, the row control circuit selects one stage from a 2S+1-stage first-type offset shift register circuit as a first-type initial shift register circuit, and selects one stage from a 2S+1-stage second-type offset shift register circuit as a second-type initial shift register circuit. The first-type initial shift register circuit and the second-type initial shift register circuit have the same offset direction relative to the multi-stage intermediate shift register circuit, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer and S is an integer, and N is less than or equal to S. The technical solutions provided in the embodiments of the present disclosure can shift the first-type initial shift register circuit and the second-type initial shift register circuit, thereby achieving pixel-level alignment or preventing incomplete displayed images due to occlusion.

[0422] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A gate drive circuit comprising a multi-stage shift register circuit and a row control circuit, wherein the multi-stage shift register circuit is cascade-connected and includes a multi-stage intermediate shift register circuit and a 4S+2-stage offset shift register circuit; In the direction of cascading the multi-stage shift register circuits, the 4S+2-stage offset shift register circuit includes a 2S+1-stage first-type offset shift register circuit located on one side of the multi-stage intermediate shift register circuit, and a 2S+1-stage second-type offset shift register circuit located on the other side of the multi-stage intermediate shift register circuit; The row control circuit is configured to receive an initial row control signal, and under the control of the initial row control signal, select one stage from the 2S+1 stages of the first-type offset shift register circuits as the first-type initial shift register circuit, and select one stage from the 2S+1 stages of the second-type offset shift register circuits as the second-type initial shift register circuit; In the direction of the cascade of the multi-stage shift register circuits, the first type of initial shift register circuit and the second type of initial shift register circuit have the same offset direction relative to the multi-stage intermediate shift register circuit, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is a positive integer, and N is less than or equal to S.

2. The gate drive circuit according to claim 1, further comprising an initial signal terminal and a row control terminal; in the row control circuit, an input terminal is connected to the initial signal terminal, a control terminal is connected to the row control terminal, and an output terminal is connected to the input terminal of the multi-stage offset shift register circuit; The row control circuit is configured to receive a forward and reverse scan control signal from the row control end, and to receive an initial signal from the initial signal end. Under the control of the forward and reverse scan control signal, one of the first type of initial shift register circuit and the second type of initial shift register circuit is used as a starting row of the shift register circuit, and the other is used as an ending row of the shift register circuit, and the initial signal is provided to the starting row of the shift register circuit.

3. The gate drive circuit according to claim 2, further comprising a reset control circuit and a reset control terminal; the multi-stage offset shift register circuit comprises a first offset shift register circuit, the first offset shift register circuit comprising an offset shift register circuit located on a side of a start row of the shift register circuit that is away from an end row of the shift register circuit, and an offset shift register circuit located on a side of an end row of the shift register circuit that is away from a start row of the shift register circuit; The input end of the reset control circuit is connected to the reset control end, and the output end is connected to the enable signal end of the multi-stage offset shift register circuit. It is configured to receive a reset control signal from the reset control end, and under the control of the reset control signal, the first offset shift register circuit is set to a high-impedance state.

4. The gate driving circuit according to claim 3, further comprising a plurality of row driving enhancement circuits respectively connected to the multi-stage shift register circuits; The plurality of row drive enhancement circuits include a plurality of offset row drive enhancement circuits, wherein the input terminals of the plurality of offset row drive enhancement circuits are respectively connected to the output terminals of the multi-stage offset shift register circuit, and the enable signal terminals are connected to the reset control circuit; The plurality of offset row driving enhancement circuits include a first offset row driving enhancement circuit, the first offset row driving enhancement circuit including an offset row driving enhancement circuit located on a side of the start row of the shift register circuit away from an end row of the shift register circuit, and an offset row driving enhancement circuit located on a side of the end row of the shift register circuit away from a start row of the shift register circuit; The reset control circuit is configured to set the first offset row drive enhancement circuit to a high impedance state under the control of the reset control signal.

5. The gate driving circuit according to claim 2, further comprising a plurality of offset transmission control circuits, wherein two adjacent stages of offset shift register circuits are cascade-connected via one of the offset transmission control circuits; a control terminal in the offset transmission control circuit is connected to the row control terminal; In the two adjacent stages of the offset shift register circuits, the input end of the offset transmission control circuit is connected to the output end of one of the stages of the offset shift register circuit, and the output end of the offset transmission control circuit is connected to the input end of the other stage of the offset shift register circuit; The offset transmission control circuit is configured to receive the initial row control signal from the row control terminal and be turned on or off under the control of the initial row control signal.

6. The gate driving circuit according to claim 5, wherein: The plurality of offset transmission control circuits include a first offset transmission control circuit and a second offset transmission control circuit, the first offset control circuit including an offset transmission control circuit located on a side of a start row of the shift register circuit that is away from an end row of the shift register circuit, and an offset transmission control circuit located on a side of an end row of the shift register circuit that is away from the start row of the shift register circuit; the second offset transmission control circuit including an offset transmission control circuit located on a side of a start row of the shift register circuit that is closer to the end row of the shift register circuit, and an offset transmission control circuit located on a side of an end row of the shift register circuit that is closer to the start row of the shift register circuit; The first offset transmission control circuit is configured to be turned off under the control of the initial row control signal, and the second offset transmission control circuit is configured to be turned on under the control of the initial row control signal.

7. The gate driving circuit according to any one of claims 2 to 6, further comprising a shift control circuit, wherein the shift control circuit comprises a scan control circuit and an input control terminal; the row control circuit comprises an initial row control circuit, and the row control terminal comprises an initial row control terminal; The initial row control circuit has an input terminal connected to the initial signal terminal, and a control terminal connected to the initial row control terminal, and is configured to receive an initial signal from the initial signal terminal and the initial row control signal from the initial row control terminal. Under the control of the initial control signal, one stage from the 2S+1 stages of the first-type offset shift register circuits is selected as the first-type initial shift register circuit, and one stage from the 2S+1 stages of the second-type offset shift register circuits is selected as the second-type initial shift register circuit. The input end of the scanning control circuit is connected to the input control end, and the output end is connected to the initial row control end. The scanning control circuit is configured to receive an input control signal from the input control end, generate the initial row control signal under the control of the input control signal, and provide the initial row control signal to the initial row control end.

8. The gate driving circuit according to claim 7, wherein: The shift control circuit further includes a cutoff row control circuit, and the gate drive circuit further includes a reset control circuit and a reset control terminal; The cutoff row control circuit has an input terminal connected to the input control terminal, an output terminal connected to the reset control terminal, and is configured to receive an input control signal from the input control terminal, generate a reset control signal under the control of the input control signal, and provide the reset control signal to the reset control terminal circuit; The reset control circuit is configured to receive the reset control signal through the reset control terminal, and under the control of the reset control signal, sets the multi-stage offset shift register circuit to a high-impedance state or a working state.

9. The gate driving circuit according to claim 8, wherein: The number of the scan control circuits is 2S+1, the initial row control circuits include 2S+1 first-type initial row control circuits and 2S+1 second-type initial row control circuits, the initial signal terminals include 2S+1 first-type initial signal terminals and 2S+1 second-type initial signal terminals, and the initial row control terminals include 2S+1 first initial row control terminals and 2S+1 second initial row control terminals, where S is an integer greater than or equal to 0; The 2S+1 first-type initial row control circuits have input terminals connected to the 2S+1 first-type initial signal terminals, output terminals connected to the input terminals of the 2S+1-stage first-type offset shift register circuits, first control terminals connected to the 2S+1 first initial row control terminals, and second control terminals connected to the 2S+1 second initial row control terminals. The input terminals of the 2S+1 second type initial row control circuits are respectively connected to the 2S+1 second type initial signal terminals. The output terminals are connected to the input terminals of the 2S+1-stage second-type offset shift register circuits, the first control terminals are connected to the 2S+1 first initial row control terminals, and the second control terminals are connected to the 2S+1 second initial row control terminals; In the 2S+1 scan control circuits, the input end is connected to the input control end, the first output end is connected to the 2S+1 first initial row control ends, and the second output end is connected to the 2S+1 second initial row control ends.

10. The gate driving circuit according to claim 9, wherein: The shift control circuit further includes m scan input inversion circuits, and the number of the input control terminals is m; The m scan input inversion circuits have input terminals connected to the m input control terminals respectively, and are configured to invert the input control signals of the m input control terminals respectively to obtain inverted signals of the input control signals, and output the inverted signals of the input control signals through the output terminals; An input terminal of the scan control circuit is connected to at least part of the m input control terminals and output terminals of the m scan input inverting circuits.

11. The gate driving circuit according to claim 10, wherein: The m input control terminals include first to fifth input control terminals, the m scan input inverting circuits include first to fifth scan input inverting circuits, and at least one of the scan control circuits includes an eighth NAND gate, a ninth NAND gate, a sixth NOR gate, and a nineteenth inverter; The eighth NAND gate has a first input terminal connected to the first input control terminal or the output terminal of the first scan input inverting circuit, a second input terminal connected to the second input control terminal or the output terminal of the second scan input inverting circuit, a third input terminal connected to the third input control terminal or the output terminal of the third scan input inverting circuit, and an output terminal connected to the second input terminal of the sixth NOR gate; The ninth NAND gate has a first input terminal connected to the fourth input control terminal or the output terminal of the fourth scan input inverting circuit, a second input terminal connected to the fifth input control terminal or the output terminal of the fifth scan input inverting circuit, and an output terminal connected to the first input terminal of the sixth NOR gate; The output end of the sixth NOR gate is connected to the input end of the nineteenth inverter and the corresponding first initial row control end, and the output end of the nineteenth inverter is connected to the corresponding second initial row control end.

12. The gate driving circuit according to claim 9, wherein: At least one of the initial row control circuits includes a fifth transmission gate, the input end of the fifth transmission gate is connected to the corresponding initial signal end, the output end is connected to the input end of the corresponding offset shift register circuit, the first control end is connected to the corresponding first initial row control end, and the second control end is connected to the corresponding second initial row control end.

13. The gate driving circuit according to claim 9, wherein: The number of the cutoff row control circuits is 2S, the reset control circuit includes 2S first-type reset control circuits and 2S second-type reset control circuits, and the reset control terminals include 2S first reset control terminals and 2S second reset control terminals; The 2S first-type reset control circuits have input terminals connected to the 2S first reset control terminals, and output terminals connected to 2S stages of first-type offset shift register circuits, respectively. In the direction from the first-type offset shift register circuit to the second-type offset shift register circuit, the 2S stages of first-type offset shift register circuits are the first stage to the 2S stages of the 2S+1-stage first-type offset shift register circuit. The 2S second-type reset control circuits have input terminals connected to the 2S second reset control terminals, and output terminals connected to 2S stages of second-type offset shift register circuits, respectively. In the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, the 2S stages of second-type offset shift register circuits are the first to the secondS stages of the 2S+1-stage second-type offset shift register circuits. In the 2S cut-off row control circuits, the input end is connected to the input control end, the first output end is connected to the 2S first reset control ends respectively, and the second output end is connected to the 2S second reset control ends respectively.

14. The gate driving circuit according to claim 13, wherein: At least one of the reset control circuits includes a tenth NAND gate and a twentieth inverter; In the first type reset control circuit, the input terminal of the tenth NAND gate is connected to the corresponding first reset control terminal, the output terminal is connected to the twelfth inverter, and the output terminal of the twelfth inverter is connected to the corresponding first type offset shift register circuit; In the second type reset control circuit, the input end of the tenth NAND gate is connected to the corresponding second reset control end, the output end is connected to the twelfth inverter, and the output end of the twelfth inverter is connected to the corresponding second type offset shift register circuit.

15. The gate driving circuit according to claim 13, wherein: The shift control circuit further includes m reset input inversion circuits, and the number of the input control terminals is m; The m reset input inverting circuits have input terminals connected to the m input control terminals respectively, and are configured to invert the input control signals of the m input control terminals respectively to obtain inverted signals of the input control signals, and output the inverted signals of the input control signals through the output terminals; The input terminal of the cut-off row control circuit is connected to the m input control terminals and the m reset input inverting circuits. At least some of the output terminals are connected.

16. The gate driving circuit according to claim 13, wherein: The m input control terminals include a first input control terminal to a fifth input control terminal, the m reset input inverting circuits include a first reset input inverting circuit to a fifth reset input inverting circuit, and the shift control circuit further includes a first input subcircuit to an Sth input subcircuit; the 2S cutoff row control circuits include S-1 first cutoff row subcircuits and S+1 second cutoff row subcircuits; In the S-1 first cut-off row sub-circuits, the first input terminals are connected to the output terminals of the first input sub-circuit to the S-1th input sub-circuit, respectively; the second input terminals are connected to the output terminal of the Sth input sub-circuit, the first output terminals are connected to the first to S-1th first reset control terminals, respectively; and the second output terminals are connected to the first to S-1th second reset control terminals, respectively. In the S+1 second cut-off row sub-circuits, the input end of the first second cut-off row sub-circuit is connected to the fifth input control end; the first input ends of the second to S-th second cut-off row sub-circuits are connected to the output end of the fifth reset input inverting circuit, and the second input ends are respectively connected to the output ends of the first input sub-circuit to the S-1-th input sub-circuit; in the S+1-th second cut-off row sub-circuit, the first input end is connected to the output end of the fifth reset input inverting circuit, and the second input end is connected to the four input control ends; in the S+1 second cut-off row sub-circuit, the first output end is respectively connected to the S-th to 2S+1 first reset control ends, and the second output end is respectively connected to the S-th to 2S+1 second reset control ends.

17. The gate driving circuit according to claim 16, wherein: The first input sub-circuit includes an eleventh NAND gate, wherein a first input terminal of the eleventh NAND gate is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, an output terminal is connected to the first input terminal and the first input terminal of the S-1th first cut-off row sub-circuit, an output terminal is connected to the S-1th first cut-off row sub-circuit and the second second cut-off row sub-circuit, and the output terminal of the eleventh NAND gate serves as the output terminal of the first input sub-circuit; The second input sub-circuit includes a twelfth NAND gate, wherein a first input terminal of the twelfth NAND gate is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the S-2th first cut-off row sub-circuit and the third second cut-off row sub-circuit, and the output terminal of the twelfth NAND gate serves as the output terminal of the second input sub-circuit; The third input sub-circuit includes a thirteenth NAND gate, a seventh NOR gate, and a twenty-first inverter; the first end of the seventh NOR gate is connected to the output end of the first reset input inverter circuit, and the second end is connected to the second reset input The output end of the inverter circuit is connected to the input end of the twenty-first inverter; the output end of the twenty-first inverter is connected to the second input end of the thirteenth NAND gate, the first input end of the thirteenth NAND gate is connected to the output end of the third reset input inverter circuit, the output end of the thirteenth NAND gate is connected to the S-3th first cut-off row sub-circuit and the fourth second cut-off row sub-circuit, and the output end of the thirteenth NAND gate serves as the output end of the third input sub-circuit; The fourth input sub-circuit includes a twenty-second inverter, the input end of the twenty-second inverter is connected to the output end of the third reset input inverter circuit, the output end of the twenty-second inverter is connected to the S-4th first cut-off row sub-circuit and the fifth second cut-off row sub-circuit, and the output end of the twenty-second inverter serves as the output end of the fourth input sub-circuit; The fifth input sub-circuit includes a fourteenth NAND gate, an eighth NOR gate, and a twenty-third inverter; the fourteenth NAND gate has a first terminal connected to the output terminal of the first reset input inverter circuit, a second terminal connected to the output terminal of the second reset input inverter circuit, and an output terminal connected to the input terminal of the twenty-third inverter; the output terminal of the twenty-third inverter is connected to the second input terminal of the eighth NOR gate, the first input terminal of the eighth NOR gate is connected to the output terminal of the third reset input inverter circuit, the output terminal of the eighth NOR gate is connected to the (S-5)th first cut-off row sub-circuit and the sixth second cut-off row sub-circuit, and the output terminal of the eighth NOR gate serves as the output terminal of the fifth input sub-circuit; The sixth input sub-circuit includes a ninth NOR gate, wherein a first input terminal of the ninth NOR gate is connected to the output terminal of the second reset input inverting circuit, a second input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the (S-6)th first cut-off row sub-circuit and the seventh second cut-off row sub-circuit, and the output terminal of the ninth NOR gate serves as the output terminal of the sixth input sub-circuit; The seventh input sub-circuit includes a tenth NOR gate, wherein a first input terminal of the tenth NOR gate is connected to the output terminal of the first reset input inverting circuit, a second input terminal is connected to the output terminal of the second reset input inverting circuit, a third input terminal is connected to the output terminal of the third reset input inverting circuit, and an output terminal is connected to the (S-7)th first cut-off row sub-circuit and the eighth second cut-off row sub-circuit, and the output terminal of the tenth NOR gate serves as the output terminal of the seventh input sub-circuit; The eighth input sub-circuit includes an eleventh NOR gate, a twenty-fourth inverter, and a twenty-fifth inverter. The twenty-fourth inverter has an input terminal connected to the third input control terminal, and an output terminal connected to the first input terminal of the eleventh NOR gate. The eleventh NOR gate has a second input terminal connected to the output terminal of the fifth reset input inverter circuit, and an output terminal connected to the input terminal of the twenty-fifth inverter. The output terminal of the twenty-fifth inverter is connected to the S-1 first cut-off row sub-circuits are connected, and the output end of the twenty-fifth inverter serves as the output end of the eighth input sub-circuit.

18. The gate driving circuit according to claim 16, wherein: The first cutoff row sub-circuit includes a twelfth NOR gate and a twenty-sixth inverter. In the twelfth NOR gate, a first input terminal is connected to the corresponding input sub-circuit among the first to S-1th input sub-circuits, a second input terminal is connected to the Sth input sub-circuit, an output terminal is connected to the twenty-sixth inverter and the corresponding first reset control terminal, and the output terminal of the twenty-sixth inverter is connected to the corresponding second reset control terminal; the output terminal of the twenty-sixth inverter serves as the second output terminal, and the output terminal of the twelfth NOR gate serves as the first output terminal.

19. The gate driving circuit according to claim 16, wherein: The first second cutoff row sub-circuit includes a twenty-seventh inverter, wherein the input end of the twenty-seventh inverter is connected to the fifth input control end, and the output end is connected to the first second reset control end; The second to Sth second-blocking row sub-circuits include a fifteenth NAND gate, a twenty-eighth inverter, a thirteenth NOR gate, and a twenty-eighth inverter; the fifteenth NAND gate has a first input connected to the output of the fifth reset input inverter circuit, a second input connected to the corresponding input sub-circuit, and an output connected to the input of the twenty-eighth inverter; the output of the twenty-eighth inverter is connected to the first input of the thirteenth NOR gate, the second input of the thirteenth NOR gate is connected to the fifth input control terminal, and the output of the thirteenth NOR gate is connected to the input of the twenty-ninth inverter and the corresponding second reset control terminal; the output of the twenty-ninth inverter is connected to the corresponding first reset control terminal; the output of the thirteenth NOR gate serves as the second output of the corresponding second-blocking row sub-circuit, and the output of the twenty-ninth inverter serves as the first output of the corresponding second-blocking row sub-circuit; The (S+1)th second cutoff row circuit includes a sixteenth NAND gate, a fourteenth NOR gate, and a thirtieth inverter. In the sixteenth NAND gate, a first input terminal is connected to the output terminal of the fifth reset input inverter circuit, a second input terminal is connected to the fourth input control terminal, and an output terminal is connected to the first input terminal of the fourteenth NOR gate; in the fourteenth NOR gate, a second input terminal is connected to the output terminal of the first input sub-circuit, an output terminal is connected to the input terminal of the thirtieth inverter and the (2S+1)th first reset control terminal, and the output terminal of the thirtieth inverter is connected to the (2S+1)th second reset control terminal.

20. The gate driving circuit according to claim 9, further comprising 2S first-type offset transmission control circuits and 2S second-type offset transmission control circuits; two adjacent stages of the first-type offset shift register circuits are cascade-connected via one of the first-type offset transmission control circuits, and two adjacent stages of the second-type offset shift register circuits are cascade-connected via one of the second-type offset transmission control circuits; In the 2S first-type offset transmission control circuits, the first control terminals are respectively connected to the 2S second initial row control terminals, and the second control terminals are respectively connected to the 2S first initial row control terminals; in the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, the 2S first initial row control terminals are the first to 2S of the 2S+1 first initial row control terminals, and the 2S second initial row control terminals are the first to 2S of the 2S+1 second initial row control terminals; In the 2S second-type offset transmission control circuits, the first control terminals are respectively connected to the 2S second initial row control terminals, and the second control terminals are respectively connected to the 2S first initial row control terminals.

21. The gate driving circuit according to claim 20, wherein in the direction from the first type of offset shift register circuit to the second type of offset shift register circuit, in the two adjacent stages of the first type of offset shift register circuit, the input end of the first type of offset transmission control circuit is connected to the output end of the first type of offset shift register circuit of the previous stage, and the output end of the offset transmission control circuit is connected to the input end of the offset shift register circuit of the next stage; In the direction from the second-type offset shift register circuit to the first-type offset shift register circuit, in the two adjacent stages of the second-type offset shift register circuit, the input end of the second-type offset transmission control circuit is connected to the output end of the first-type offset shift register circuit of the previous stage, and the output end of the offset transmission control circuit is connected to the input end of the offset shift register circuit of the next stage.

22. The gate driving circuit according to claim 9, wherein: The row control circuit further includes 2S+1 first-type forward and reverse scan control circuits and 2S+1 second-type forward and reverse scan control circuits, and the row control terminal further includes a first forward and reverse scan control terminal and a second forward and reverse scan control terminal; The output ends of the 2S+1 first-type initial row control circuits are connected to the input ends of the 2S+1-stage first-type offset shift register circuits through the 2S+1 first-type forward and reverse scan control circuits; the output ends of the 2S+1 second-type initial row control circuits are connected to the input ends of the 2S+1-stage second-type offset shift register circuits through the 2S+1 second-type forward and reverse scan control circuits; The 2S+1 first-type forward and reverse scan control circuits have input terminals connected to the output terminals of the 2S+1 first-type initial row control circuits, output terminals connected to the input terminals of the 2S+1-stage first-type offset shift register circuits, a first control terminal connected to the first forward and reverse scan control terminal, and a second terminal connected to the second forward and reverse scan control terminal; In the 2S+1 second-type forward and reverse scan control circuits, the input ends are respectively connected to the output ends of the 2S+1 second-type initial row control circuits, the output ends are respectively connected to the input ends of the 2S+1-level second-type offset shift register circuits, the first control end is connected to the second forward and reverse scan control end, and the second end is connected to the first forward and reverse scan control end.

23. The gate driving circuit according to claim 7, wherein: The scan control circuit includes at least two 3-line-8-line decoders, 2S+1 expansion circuits, 2S+1 output terminals and at least one expanded input control terminal. The input control terminal of the scan control circuit includes the three input terminals of the 3-line-8-line decoder and the at least one expanded input terminal. The input terminals of the 2S+1 expansion circuits are connected to the 2S+1 output terminals of the at least two 3-line-8-line decoders. The output terminals of the 2S+1 expansion circuits serve as the 2S+1 output terminals of the scan control circuit respectively.

24. The gate driving circuit according to claim 23, wherein: The input control terminals of the scan control circuit include first to fifth input control terminals, and the at least two 3-line-8-line decoders include a first 3-line-8-line decoder and a second 3-line-8-line decoder. The three input terminals of the first 3-line-8-line decoder serve as the first to third input control terminals of the scan control circuit, and the inverted signal terminals from the first to third input control terminals serve as the input terminals of the second 3-line-8-line decoder.

25. The gate driving circuit according to claim 24, wherein: The 2S+1 expansion circuits include 2S first expansion circuits and 1 second expansion circuit; the first expansion circuit and the second expansion circuit each include a ninth NAND gate, a sixth NOR gate, and a nineteenth inverter; the second expansion circuit also includes an eighth NAND gate; In the ninth NAND gate, a first input terminal is connected to the fourth input control terminal or the inverted signal terminal of the fourth input control terminal, a second input terminal is connected to the fifth input control terminal or the inverted signal terminal of the fifth input control terminal, and an output terminal is connected to the first input terminal of the sixth NOR gate; The output end of the sixth NOR gate is connected to the input end of the nineteenth inverter, the output end of the sixth NOR gate serves as an output end of the scan control circuit, and the output end of the nineteenth inverter serves as an inverted signal end of an output end of the scan control circuit; In the first expansion circuit, the second input terminal of the sixth NOR gate is connected to one output terminal of the 3-line to 8-line decoder, and in the second expansion circuit, the second input terminal of the sixth NOR gate is connected to the output terminal of the eighth NAND gate; In the eighth NAND gate, three input terminals are connected to the first input control terminal to the third input control terminal respectively, and an output terminal is connected to the second input terminal of the sixth NOR gate.

26. A gate drive circuit operating method, applied to the gate drive circuit according to any one of claims 1 to 25, the gate drive circuit comprising a multi-stage shift register circuit and a row control circuit, the multi-stage shift register circuits being cascade-connected, the multi-stage shift register circuit comprising a multi-stage intermediate shift register circuit and a 4S+2-stage offset shift register circuit; in the direction of the cascade connection of the multi-stage shift register circuits, the 4S+2-stage offset shift register circuit comprises a 2S+1-stage first-type offset shift register circuit located on one side of the multi-stage intermediate shift register circuit, and a 2S+1-stage second-type offset shift register circuit located on the other side of the multi-stage intermediate shift register circuit; the operating method comprising: The row control circuit receives an initial row control signal, and under the control of the initial row control signal, selects one level from the 2S+1 levels of the first-type offset shift register circuits as the first-type initial shift register circuit, and selects one level from the 2S+1 levels of the second-type offset shift register circuits as the second-type initial shift register circuit; in the direction of the cascade of the multi-stage shift register circuits, the offset direction of the first-type initial shift register circuit and the second-type initial shift register circuit relative to the multi-stage intermediate shift register circuit are consistent, and the number of offset levels relative to the multi-stage intermediate shift register circuit is N, where N is an integer, S is a positive integer, and N is less than or equal to S.

27. A display substrate comprising a display area and a non-display area; the display area comprises a plurality of sub-pixels, at least one sub-pixel comprises a pixel driving circuit and at least one scanning signal line, the scanning signal line is configured to provide a scanning signal to the connected pixel driving circuit; the non-display area comprises a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit comprises the gate driving circuit as described in any one of claims 1 to 25.

28. A display device comprising the display substrate according to claim 27.

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