Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a base substrate (100), which comprises a non-display area (BB), wherein the non-display area (BB) comprises a shift register area and a bonding area. The shift register area comprises a plurality of gate drive circuits (10), wherein each gate drive circuit (10) comprises a plurality of cascaded shift register units (SR); and each gate drive circuit (10) is electrically connected to a plurality of voltage signal lines (V1), and the plurality of voltage signal lines (V1) are electrically connected to a voltage signal transfer line (Z1). The bonding area comprises a signal input terminal (OT) and signal input lines (S1), wherein the signal input terminal (OT) transmits voltage signals to the voltage signal transfer lines (Z1) by means of the signal input lines (S1), and the voltage signal transfer lines (Z1) transmit the voltage signals to the voltage signal lines (V1). Each voltage signal transfer line (Z1) is adjacent to the tail end of the last-stage shift register unit (SR) among the plurality of cascaded shift register units (SR).

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on January 11, 2024, with application number 202410044296.0 and application name “Display Panel and Display Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] Organic Light Emitting Diode (OLED) display panels have been widely used in the display field due to their advantages such as high brightness, full viewing angle, fast response speed, and flexible display. With the development of OLED display panels, the bottom bezel of display panels with rounded corners has tended to increase, making it difficult to achieve a narrow-bezel display.

[0005] With the rapid development of display technology, display panels are showing a trend toward high integration and low cost. Among these technologies, Gate Driver on Array (GOA) integrates gate driver circuitry onto the array substrate of a display panel to provide scan drive for the display panel. Currently, gate driver circuitry typically consists of multiple cascaded shift register units.

[0006] Summary of the Invention

[0007] The display panel provided by the embodiment of the present disclosure includes: a base substrate including a non-display area;

[0008] The non-display area includes: a shift register area and a bonding area;

[0009] The shift register area includes: a plurality of gate drive circuits; each of the gate drive circuits includes a plurality of cascaded shift register units; wherein each of the gate drive circuits is electrically connected to a plurality of voltage signal lines;

[0010] The plurality of voltage signal lines are electrically connected to the voltage signal adapter line;

[0011] The bonding area includes: a signal input terminal and a signal input line; the signal input terminal transmits a voltage signal to the voltage signal adapter line through the signal input line;

[0012] The voltage signal adapter wire transmits the voltage signal to the voltage signal wire;

[0013] The voltage signal transfer line is adjacent to an end of a last stage of the shift register unit in the plurality of cascaded shift register units.

[0014] In some possible implementations, the voltage signal adapter wire and the voltage signal wire are located in different film layers.

[0015] In some possible implementations, the last stage shift register unit in the plurality of cascaded shift register units and the voltage signal transfer line are located in a corner area of ​​the non-display area;

[0016] The orthographic projection of the voltage signal transfer line on the base substrate does not overlap with the orthographic projection of the shift register unit on the base substrate.

[0017] In some possible implementations, the voltage signal adapter is arranged in parallel with the last stage shift register unit.

[0018] In some possible implementations, the orthographic projection of the voltage signal line on the base substrate partially overlaps with the orthographic projection of the voltage signal adapter line on the base substrate.

[0019] In some possible implementations, the plurality of voltage signal lines include: a plurality of first voltage signal lines, a plurality of second voltage signal lines;

[0020] The voltage signal adapter wire includes: a first voltage signal adapter wire and a second voltage signal adapter wire;

[0021] The plurality of first voltage signal lines are electrically connected to the first voltage signal adapter line;

[0022] The plurality of second voltage signal lines are electrically connected to the second voltage signal adapter line.

[0023] In some possible implementations, the orthographic projection of the first voltage signal patch cord on the base substrate is adjacent to the orthographic projection of the second voltage signal patch cord on the base substrate.

[0024] In some possible implementations, the plurality of voltage signal lines further include: a plurality of third voltage signal lines, a plurality of fourth voltage signal lines;

[0025] The voltage signal adapter cable further includes: a third voltage signal adapter cable;

[0026] The plurality of third voltage signal lines are electrically connected to the third voltage signal adapter line;

[0027] The plurality of fourth voltage signal lines are electrically connected to each other through the transfer portion.

[0028] In some possible implementations, the plurality of fourth voltage signal lines are disposed adjacent to each other.

[0029] In some possible implementations, the further comprising: a first conductive layer, a second conductive layer, and a third conductive layer; wherein the second conductive layer is located between the first conductive layer and the third conductive layer;

[0030] The first conductive layer includes the first voltage signal adapter wire and the third voltage signal adapter wire;

[0031] The second conductive layer includes the second voltage signal adapter wire;

[0032] The third conductive layer includes the voltage signal line.

[0033] The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1a is a schematic diagram of some structures of a display panel according to an embodiment of the present disclosure;

[0035] FIG1b is a schematic diagram of another structure of a display panel in an embodiment of the present disclosure;

[0036] FIG1c is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0037] FIG2 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0038] FIG3 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0039] FIG4 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0040] FIG5 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0041] FIG6 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0042] FIG7 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0043] FIG8 is a schematic diagram of some structures of a shift register unit in an embodiment of the present disclosure;

[0044] FIG9 is another schematic diagram of the structure of the shift register unit in the embodiment of the present disclosure;

[0045] FIG10 is a schematic diagram of some further structures of the shift register unit in the embodiment of the present disclosure;

[0046] FIG11 is a schematic diagram of some further structures of the shift register unit in the embodiment of the present disclosure;

[0047] FIG12 is a schematic diagram of some further structures of the shift register unit in the embodiment of the present disclosure;

[0048] FIG13 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0049] FIG14 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0050] FIG15 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0051] FIG16 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0052] FIG17 is a schematic diagram of some further structures of a display panel in an embodiment of the present disclosure;

[0053] FIG18 is a schematic diagram of some further structures of the display panel in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0055] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0056] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0057] For example, as shown in FIG1a, FIG1b, and FIG1c, the left side of the display panel Lt in the prior art includes a plurality of gate drive circuits (such as Reset_P, NGOA, and PGOA in FIG1a); the right side of the display panel Rt includes a plurality of gate drive circuits (such as PGOA, Reset_H, and EOA in FIG1b); wherein the gate drive circuit Reset_P can be symmetrically arranged with the gate drive circuit EOA with respect to the display area; the gate drive circuit NGOA can be symmetrically arranged with the gate drive circuit Reset_H with respect to the display area; the gate drive circuit PGOA of the left side of the display panel Lt can be symmetrically arranged with respect to the display area. The gate drive circuit PGOA on the right side of the display panel (Rt) is symmetrically arranged with respect to the display area. The gate drive circuits PGOA and EOA are electrically connected to the VGL and VGH signal lines. The gate drive circuits Reset_P, Reset_H, and NGOA are electrically connected to the VGL_N and VGH_N signal lines. The gate drive circuits Reset_H, EOA, Reset_P, and NGOA all utilize unilateral drive (i.e., the gate drive circuit is located only on the left or right side of the display panel). Only the gate drive circuit PGOA utilizes bilateral drive (i.e., the gate drive circuit is located on both the left and right sides of the display panel). Figure 1c shows that the wiring of the VGL, VGH, VGL_N, and VGH_N signal lines in the display panel occupies a relatively large amount of space, which is not conducive to achieving a narrow bezel. On this basis, if the gate drive circuits Reset_H, EOA, Reset_P, NGOA, and PGOA are all set to adopt bilateral drive, the number of VGL signal lines, VGH signal lines, VGL_N signal lines, and VGH_N signal lines will increase, and the space occupied by the wiring will also increase, which will be more unfavorable for achieving a narrow frame.

[0058] In view of the above problems, the display panel provided by the embodiment of the present disclosure, as shown in FIG2 , includes: a base substrate 100 including a non-display area BB;

[0059] The non-display area BB includes: a shift register area and a bonding area;

[0060] The shift register area includes: a plurality of gate drive circuits 10; each gate drive circuit 10 includes a plurality of cascaded shift register units SR; wherein each gate drive circuit 10 is electrically connected to a plurality of voltage signal lines V1;

[0061] The plurality of voltage signal lines V1 are electrically connected to the voltage signal adapter line Z1;

[0062] The bonding area includes: a signal input terminal OT and a signal input line S1; the signal input terminal OT transmits a voltage signal to the voltage signal adapter line Z1 via the signal input line S1;

[0063] The voltage signal adapter cable Z1 transmits the voltage signal to the voltage signal cable V1;

[0064] The voltage signal transfer line Z1 is adjacent to an end of the last stage shift register unit SRn among the plurality of cascaded shift register units.

[0065] The embodiment of the present disclosure transmits the voltage signal to the voltage signal line by setting a voltage signal adapter line, and makes the voltage signal adapter line adjacent to the end of the last stage shift register unit in multiple cascaded shift register units; wherein, the signal input terminal transmits the voltage signal to the voltage signal adapter line through the signal input line; that is, the present disclosure electrically connects multiple voltage signal lines to the same voltage signal adapter line, and leads a line from the voltage signal adapter line to be electrically connected to the signal input line; it can save the wiring space of directly electrically connecting multiple voltage signal lines to the signal input line, thereby improving space utilization and facilitating the realization of a narrow frame design.

[0066] It should be noted that the voltage signal transfer line is adjacent to the end of the last shift register unit in the multiple cascaded shift register units, wherein the proximity may include: the voltage signal transfer line is adjacent to the end of the last shift register unit in the multiple cascaded shift register units, that is, there is no gap between the voltage signal transfer line and the last shift register unit in the multiple cascaded shift register units; as shown in Figure 2, the voltage signal transfer line Z1 is closely adjacent to the end of the last shift register unit SRn, with no gap in between, but the voltage signal transfer line Z1 overlaps with the end of the last shift register unit SRn; or, there is a small gap between the voltage signal transfer line and the end of the last shift register unit in the multiple cascaded shift register units, at which point wiring can be performed or possible transfer holes can be avoided according to specific needs. For example, as shown in Figure 3, there is a small gap between the voltage signal transfer line Z1 and the end of the last shift register unit SRn, at which point a signal line x1 can be set according to specific needs.

[0067] For example, as shown in FIG2 , the substrate 100 may further include a display area AA, wherein the display area AA may include a plurality of pixel units. Each pixel unit may include a plurality of sub-pixels. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0068] Exemplarily, as shown in FIG2 , the display area AA may further include a plurality of gate lines and a plurality of data lines. Each sub-pixel may include a transistor and a pixel electrode. Among them, a row of sub-pixels corresponds to a gate line, and a column of sub-pixels corresponds to a data line. The gate of the transistor is coupled to the corresponding gate line, the source of the transistor is coupled to the corresponding data line, and the drain of the transistor is coupled to the pixel electrode. It should be noted that the pixel array structure disclosed in the present invention may also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of pixels. This arrangement can reduce half of the data lines, that is, some data lines are included between two adjacent columns of pixels, and some data lines are not included between two adjacent columns of pixels. The specific pixel arrangement structure and data lines, and the arrangement of the gate lines are not limited.

[0069] Exemplarily, the display panel may be an electroluminescent display panel. The sub-pixel may include a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The light-emitting element includes a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting element may include at least one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), and a micro light-emitting diode (MicroLED).

[0070] In some embodiments of the present disclosure, the voltage signal adapter line Z1 and the voltage signal line V1 are located in different film layers.

[0071] In some embodiments of the present disclosure, as shown in Figure 2, the last-stage shift register unit SRn and the voltage signal transfer line Z1 in the multiple cascaded shift register units are located in the corner area of ​​the non-display area BB; the orthographic projection of the voltage signal transfer line Z1 on the base substrate 100 does not overlap with the orthographic projection of the shift register unit SR on the base substrate 100.

[0072] In some embodiments of the present disclosure, as shown in FIG. 2 , the voltage signal adapter line Z1 is arranged in parallel with the last stage shift register unit SRn.

[0073] In some embodiments of the present disclosure, as shown in FIG. 2 , the orthographic projection of the voltage signal line V1 on the base substrate 100 partially overlaps with the orthographic projection of the voltage signal transfer line Z1 on the base substrate 100 .

[0074] In some embodiments of the present disclosure, as shown in FIG. 4 to FIG. 7 , the plurality of voltage signal lines V1 include: a plurality of first voltage signal lines VGL, a plurality of second voltage signal lines VGH;

[0075] The voltage signal adapter cable Z1 includes: a first voltage signal adapter cable ZV1 and a second voltage signal adapter cable ZV2;

[0076] A plurality of first voltage signal lines VGL are electrically connected to the first voltage signal adapter line ZV1;

[0077] The plurality of second voltage signal lines VGH are electrically connected to the second voltage signal adapter line ZV2.

[0078] Exemplarily, the first voltage signal transfer line ZV1 may be electrically connected to the first voltage signal transfer line ZV2 through a via; and the second voltage signal line VGH may be electrically connected to the second voltage signal transfer line ZV2 through a via.

[0079] In some embodiments of the present disclosure, as shown in FIG. 4 to FIG. 7 , the orthographic projection of the first voltage signal transfer line ZV1 on the base substrate 100 is adjacent to the orthographic projection of the second voltage signal transfer line ZV2 on the base substrate 100 .

[0080] For example, as shown in Figures 6 and 7, a plurality of first voltage signal lines VGL are electrically connected to a first voltage signal adapter line ZV1, and the first voltage signal adapter line ZV1 is electrically connected to the signal input line S1 through a lead line Y1, and the voltage value of the voltage signal transmitted on the signal input line S1 is vgl; a plurality of second voltage signal lines VGH are electrically connected to a second voltage signal adapter line ZV2, and the second voltage signal adapter line ZV2 is electrically connected to the signal input line S1 through a lead line Y2, and the voltage value of the voltage signal transmitted on the signal input line S1 is is vgh; wherein, the orthographic projection of the first voltage signal transfer line ZV1 on the base substrate 100 and the orthographic projection of the second voltage signal transfer line ZV2 on the base substrate 100 are parallel to each other; the orthographic projection of the second voltage signal transfer line ZV2 on the base substrate 100 is closer to the orthographic projection of the last-stage shift register unit SRn on the base substrate 100; the orthographic projections of the first voltage signal transfer line ZV1 and the second voltage signal transfer line ZV2 on the base substrate 100 are both parallel to the orthographic projection of the last-stage shift register unit SRn on the base substrate 100.

[0081] In some embodiments of the present disclosure, as shown in FIG. 4 to FIG. 7 , the plurality of voltage signal lines further include: a plurality of third voltage signal lines VGL_N, a plurality of fourth voltage signal lines VGH_N;

[0082] The voltage signal adapter cable Z1 further includes: a third voltage signal adapter cable ZV3;

[0083] A plurality of third voltage signal lines VGL_N are electrically connected to the third voltage signal adapter line ZV3;

[0084] The plurality of fourth voltage signal lines VGH_N are electrically connected to each other through the transfer portion L.

[0085] Exemplarily, the third voltage signal line VGL_N may be electrically connected to the third voltage signal transfer line ZV3 through a via.

[0086] In some embodiments of the present disclosure, as shown in FIG. 4 to FIG. 7 , a plurality of fourth voltage signal lines VGH_N are disposed adjacent to each other.

[0087] For example, as shown in Figures 6 and 7, multiple third voltage signal lines VGL_N are electrically connected to a third voltage signal adapter line ZV3, and the third voltage signal adapter line ZV3 is electrically connected to the signal input line S1 through a lead Y3, and the voltage value of the voltage signal transmitted on the signal input line S1 is vgl_n; multiple fourth voltage signal lines VGH_N are electrically connected through the adapter L, and then the multiple fourth voltage signal lines VGH_N are equivalent to a fourth voltage signal line VGH_N, and the fourth voltage signal line VGH_N is electrically connected to the signal input line S1, and the voltage value of the voltage signal transmitted on the signal input line S1 is vgh_n; wherein, the orthographic projection of the first voltage signal adapter line ZV1 on the substrate 100 and the orthographic projection of the third voltage signal adapter line ZV3 are on the same straight line; the orthographic projection of the third voltage signal adapter line ZV3 on the substrate 100 is parallel to the orthographic projection of the last-stage shift register unit SRn on the substrate 100. For example, as shown in FIG. 7 , the orthographic projection of the transition portion L on the base substrate 100 is in an “L” shape.

[0088] For example, as shown in FIG4 to FIG7 , the gate driving circuits EOA, Reset_H, Reset_P, NGOA, and PGOA in the display panel are all driven on both sides, that is, the gate driving circuits Reset_H, EOA, Reset_P, NGOA, and PGOA are provided on both sides of the display panel.

[0089] Exemplarily, as shown in FIG4 and FIG8 , the gate driving circuit EOA is electrically connected to the first voltage signal line VGL, the second voltage signal line VGH, the first clock signal line ECK, the second clock signal line ECB, and the third clock signal line ECX.

[0090] For example, as shown in Figures 4 and 9, the gate drive circuit Reset_H is electrically connected to the first voltage signal line VGL, the second voltage signal line VGH, the fourth clock signal line HCK, the fifth clock signal line HCB, the sixth clock signal line HCX, the first frame start signal line HSTV1, the second frame start signal line HSTV2, and the third frame start signal line ESTV2.

[0091] For example, as shown in Figures 4 and 10, the gate drive circuit Reset_P is electrically connected to the first voltage signal line VGL, the second voltage signal line VGH, the seventh clock signal line PCK, the eighth clock signal line PCB, the ninth clock signal line PCX, the fourth frame start signal line PSTV1, the fifth frame start signal line PSTV2, and the sixth frame start signal line ESTV1.

[0092] 4 and 11 , the gate drive circuit NGOA is electrically connected to the third voltage signal line VGL_N, the fourth voltage signal line VGH_N, the tenth clock signal line NCK, the eleventh clock signal line NCB, the twelfth clock signal line NCX, the seventh frame start signal line NSTV1, and the eighth frame start signal line NSTV2.

[0093] For example, as shown in Figures 4 and 12, the gate drive circuit PGOA is electrically connected to the first voltage signal line VGL, the second voltage signal line VGH, the first clock control signal line CLK1, the second clock control signal line CLK2, the third clock control signal line CLK3, the fourth clock control signal line CLK4, the ninth frame start signal line GSTV1, the tenth frame start signal line GSTV2, the first initialization signal line Vinit1, the second initialization signal line Vinit2, and the third initialization signal line Vinit3.

[0094] In some embodiments of the present disclosure, as shown in Figures 13 to 16, it also includes: a first conductive layer Gate1, a second conductive layer Gate2 and a third conductive layer SD2; wherein the second conductive layer Gate2 is located between the first conductive layer Gate1 and the third conductive layer SD2; the first conductive layer Gate1 includes a first voltage signal adapter line ZV1 and a third voltage signal adapter line ZV3; the second conductive layer Gate2 includes a second voltage signal adapter line ZV2; and the third conductive layer SD2 includes a voltage signal line V1.

[0095] For example, as shown in Figures 4 and 14, the third conductive layer SD2 also includes: a first clock signal line ECK, a second clock signal line ECB, a third clock signal line ECX, a fourth clock signal line HCK, a fifth clock signal line HCB, a sixth clock signal line HCX, a first frame start signal line HSTV1, a second frame start signal line HSTV2, a third frame start signal line ESTV2, a seventh clock signal line PCK, an eighth clock signal line PCB, a ninth clock signal line PCX, a fourth frame start signal line PSTV1, a fifth frame start signal line PSTV2, a sixth frame start signal line ESTV1, a tenth clock signal line NCK, an eleventh clock signal line NCB, a twelfth clock signal line NCX, a seventh frame start signal line NSTV1, an eighth frame start signal line NSTV2, a ninth frame start signal line GSTV1, a tenth frame start signal line GSTV2, a first initialization signal line Vinit1, a second initialization signal line Vinit2, and a third initialization signal line Vinit3.

[0096] For example, as shown in FIG13 and FIG14, the display panel includes: a semiconductor layer located on a substrate; a first gate insulating layer located on a side of the semiconductor layer facing away from the substrate; a first conductive layer Gate1 located on a side of the first gate insulating layer facing away from the substrate; a second gate insulating layer located on a side of the first conductive layer Gate1 facing away from the substrate; a second conductive layer Gate2 located on a side of the second gate insulating layer facing away from the substrate; a first interlayer insulating layer located on a side of the second conductive layer Gate2 facing away from the substrate; a buffer layer located on a side of the first interlayer insulating layer facing away from the substrate; an active layer located on a side of the buffer layer facing away from the substrate layer; a third gate insulating layer located on the side of the active layer facing away from the substrate; a fourth conductive layer located on the side of the third gate insulating layer facing away from the substrate; a second interlayer insulating layer located on the side of the fourth conductive layer facing away from the substrate; a fifth conductive layer located on the side of the second interlayer insulating layer facing away from the substrate; a first insulating layer located on the side of the fifth conductive layer facing away from the substrate; a first flattening layer located on the side of the first flattening layer facing away from the substrate; a second insulating layer located on the side of the third conductive layer SD2 facing away from the substrate; and a sixth conductive layer located on the side of the second insulating layer facing away from the substrate.

[0097] For example, FIG15 is a schematic diagram showing the first conductive layer Gate1 and the second conductive layer Gate2 being superimposed together.

[0098] 4 and 17 , the fifth conductive layer SD1 includes a first voltage signal line VGL and a second voltage signal line VGH electrically connected to the gate drive circuit EOA. The sixth conductive layer includes a first clock control signal line CLK1, a second clock control signal line CLK2, a third clock control signal line CLK3, and a fourth clock control signal line CLK4.

[0099] Exemplarily, FIG18 is a schematic diagram showing the fifth conductive layer SD1 and the third conductive layer SD2 stacked together.

[0100] For example, the semiconductor layer and the active layer can be patterned using semiconductor materials; the semiconductor layer and the active layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. The source region and the drain region can be conductive regions formed by doping with n-type impurities or p-type impurities.

[0101] For example, the materials of the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be conductive materials. For example, the conductive material can include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of the present disclosure do not limit the materials of the functional layers.

[0102] Illustratively, the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the buffer layer, the third gate insulating layer, the second interlayer insulating layer, the first insulating layer, the first flat layer, the second insulating layer, etc. are all formed of insulating materials. As needed, organic insulating materials such as polyimide, resin materials, etc. can be selected, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. can be selected. The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0103] For example, a patterning process can be used to form various structures in the first to fifth conductive layers, and an etching process can be used to form vias. It should be noted that the patterning process may include only photolithography, or may include both photolithography and etching steps, and may also include other processes such as printing and inkjet printing to form a predetermined pattern. Photolithography refers to a process that uses photoresist, a mask, an exposure machine, and the like to form a pattern, including film formation, exposure, and development processes. In specific implementations, the corresponding patterning process can be selected based on the structure formed in this disclosure.

[0104] Based on the same inventive concept, the present disclosure also provides a display device comprising the display panel described above. The principles of this display device are similar to those of the aforementioned display panel, so the implementation of this display device can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated here.

[0105] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0106] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0107] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, characterized in that: include: a base substrate, comprising a non-display area; The non-display area includes: a shift register area and a bonding area; The shift register area includes: a plurality of gate drive circuits; each of the gate drive circuits includes a plurality of cascaded shift register units; wherein each of the gate drive circuits is electrically connected to a plurality of voltage signal lines; The plurality of voltage signal lines are electrically connected to the voltage signal adapter line; The bonding area includes: a signal input terminal and a signal input line; the signal input terminal transmits a voltage signal to the voltage signal adapter line through the signal input line; The voltage signal adapter wire transmits the voltage signal to the voltage signal wire; The voltage signal transfer line is adjacent to an end of a last stage of the shift register unit in the plurality of cascaded shift register units.

2. The display panel according to claim 1, wherein The voltage signal transfer line and the voltage signal line are located in different film layers.

3. The display panel according to claim 1, wherein The last stage shift register unit of the plurality of cascaded shift register units and the voltage signal transfer line are located in a corner area of ​​the non-display area; The orthographic projection of the voltage signal transfer line on the base substrate does not overlap with the orthographic projection of the shift register unit on the base substrate.

4. The display panel according to claim 3, wherein: The voltage signal adapter is arranged in parallel with the last stage shift register unit.

5. The display panel according to any one of claims 1 to 4, wherein: The orthographic projection of the voltage signal line on the base substrate partially overlaps with the orthographic projection of the voltage signal switching line on the base substrate.

6. The display panel according to claim 5, wherein: The plurality of voltage signal lines include: a plurality of first voltage signal lines and a plurality of second voltage signal lines; The voltage signal adapter wire includes: a first voltage signal adapter wire and a second voltage signal adapter wire; The plurality of first voltage signal lines are electrically connected to the first voltage signal adapter line; The plurality of second voltage signal lines are electrically connected to the second voltage signal adapter line.

7. The display panel according to claim 6, wherein: The orthographic projection of the first voltage signal switching line on the base substrate is adjacent to the orthographic projection of the second voltage signal switching line on the base substrate.

8. The display panel according to claim 5, wherein: The plurality of voltage signal lines further include: a plurality of third voltage signal lines and a plurality of fourth voltage signal lines; The voltage signal adapter cable further includes: a third voltage signal adapter cable; The plurality of third voltage signal lines are electrically connected to the third voltage signal adapter line; The plurality of fourth voltage signal lines are electrically connected to each other through the transfer portion.

9. The display panel according to claim 8, wherein: The plurality of fourth voltage signal lines are disposed adjacent to each other.

10. The display panel according to any one of claims 6 to 9, wherein: Also includes: A first conductive layer, a second conductive layer and a third conductive layer; wherein the second conductive layer is located between the first conductive layer and the third conductive layer; The first conductive layer includes the first voltage signal adapter wire and the third voltage signal adapter wire; The second conductive layer includes the second voltage signal adapter wire; The third conductive layer includes the voltage signal line.

11. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 10.

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