Imaging device and imaging method

Abstract

[Problem] To provide an imaging device and an imaging method capable of suppressing potential variation in accordance with the elapsed time from pixel initialization. [Solution] The present disclosure provides an imaging device comprising: a pixel array unit in which a plurality of first pixels each outputting a luminance signal corresponding to a light amount are configured in a matrix; a detection circuit unit that outputs a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels exceeds a predetermined threshold; and a drive unit having a first drive for resetting the accumulated charge of the first pixels in a partial region within the plurality of first pixels.

Description

Imaging device and imaging method

[0001] The present disclosure relates to an imaging device and an imaging method.

[0002] In an image sensor having a pixel array in which pixels each having a photoelectric conversion unit that performs photoelectric conversion of incident light are arranged in a two-dimensional matrix, an image sensor is used that selects only pixels that detect a predetermined change in luminance and reads out a signal representing that change in luminance. Such changes in luminance are caused by the movement of the object, and by selecting and reading out only pixels that detect the change in luminance, it is possible to detect a moving subject at a high frame rate. Such an image sensor is called an EVS (Event-based Vision Sensor).

[0003] Japanese Patent Application Laid-Open No. 2021-048554

[0004] On the other hand, there are cases where only pixels in which a change in luminance is detected are initialized, and as time passes from the initialization, the potential corresponding to the accumulated charge of the pixel may fluctuate.

[0005] Therefore, the present disclosure provides an imaging device and an imaging method that can suppress potential fluctuations that occur over time after pixel initialization.

[0006] In order to solve the above problem, according to the present disclosure, there is provided an imaging device including: a pixel array section in which a plurality of first pixels that output luminance signals according to the amount of light are arranged in a matrix; a detection circuit section that outputs a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels exceeds a predetermined threshold; and a drive section having a first drive that resets the accumulated charges of the first pixels in a partial region within the plurality of first pixels.

[0007] The first driving may be performed row by row.

[0008] The first driving may be performed for each of a plurality of rows.

[0009] The device may further include a signal processing unit that determines a range in which the first driving is to be performed based on the number of times the detection signal is generated within a predetermined time, and the driving unit may perform the first driving in accordance with the determination of the signal processing unit.

[0010] The pixel array unit may perform imaging in units of different frames, and the signal processing unit may determine a range in which the first driving is performed based on the number of occurrences of the detection signal in a single frame.

[0011] The pixel array unit may perform imaging in units of different frames, and the signal processing unit may determine a range in which the first driving is performed based on the number of occurrences of the detection signal in a plurality of frames.

[0012] The drive section may cause the first pixels that output the detection signals to output luminance signals corresponding to the light amounts on a row-by-row basis.

[0013] The image sensor may further include an arbiter unit that arbitrates the detection signals and causes the first pixel to output a luminance signal corresponding to the amount of light to the drive unit.

[0014] The image display device may further include an output section that generates a signal of a data type including information indicating the first pixel that has undergone the first driving.

[0015] The output unit may generate a signal including information indicating the first pixel in at least one of a line header and embedded data of a packet.

[0016] The drive section may further include a second drive that resets all of the plurality of first pixels.

[0017] The driving section may perform the first driving for each randomly selected row.

[0018] The pixel array section may further include a plurality of second pixels for gradation arranged in a matrix, and may be capable of generating a gradation image based on output signals of the plurality of second pixels.

[0019] The drive section may perform the first driving based on a control signal received when the drive section controls the second pixel.

[0020] The drive section may perform the first driving based on a control signal when initialization or reading out of the second pixel is performed.

[0021] The drive section may perform the first driving on the first pixels in a row in which the second pixels are initialized or in which readout is performed.

[0022] The driving unit may perform the first driving on the first pixels in at least one of the row in which the second pixels are initialized and the row in which the readout is performed, and another row different from the row in which the second pixels are initialized and the row in which the readout is performed.

[0023] The image sensor may further include a second drive unit that drives the second pixels, and accumulated charges of the second pixels may be read out for each row.

[0024] The image sensor may further include a second drive section that drives the second pixels, and accumulated charges of the second pixels may be read out for every row.

[0025] In order to solve the above problem, according to the present disclosure, there is provided an imaging method including: a detection step of outputting a detection signal indicating the occurrence of an address event when each luminance signal of a plurality of first pixels that output a luminance signal according to the amount of light exceeds a predetermined threshold; and a drive circuit step of executing a first drive that resets the accumulated charges of the first pixels in a partial region within the plurality of first pixels.

[0026] 15 is a block diagram showing an example of the configuration of an imaging system to which the technology according to the present disclosure is applied. FIG. 16 is a block diagram showing an example of the configuration of a scan-type imaging device. FIG. 17 is a block diagram showing an example of the configuration of a pixel array unit. FIG. 18 is a block diagram showing an example of the configuration of a column processing unit. FIG. 19 is a circuit diagram showing an example of the circuit configuration of a pixel. FIG. 19 is a block diagram showing an example of the configuration of an address event detection unit. FIG. 19 is a diagram showing voltage fluctuations based on accumulated charge in a light receiving element. FIG. 20 is a diagram showing an example of a row that rarely becomes an active pixel. FIG. 21 is a diagram showing an example of a circuit configuration. FIG. 22 is a diagram showing a first control example according to the present embodiment. FIG. 23 is a diagram showing a second control example according to the present embodiment. FIG. 24 is a diagram showing a third control example according to the present embodiment. FIG. 25 is a diagram showing a fourth control example according to the present embodiment. FIG. 26 is a diagram showing an example of a data structure according to the present embodiment. FIG. 27 is a diagram showing one row of data in the example data format shown in FIG. 24. FIG. 28 is a diagram showing an example of processing in a subsequent image processing device. FIG. 29 is a diagram showing an example of the configuration of an imaging device according to the second embodiment. FIG. 29 is a diagram showing an example of a control example according to the second embodiment. FIG. 29 is a block diagram showing an example of the configuration of an imaging device according to the third embodiment. FIG. 29 is a diagram showing a schematic configuration of a pixel block. FIG. 29 is a diagram showing a schematic flow of signals between a first access control circuit, a second access control circuit, and a second signal processing unit. FIG. 29 is a diagram showing a fifth control example according to the third embodiment. 10A to 10C are diagrams showing a sixth control example according to the third embodiment, a seventh control example according to the third embodiment, an eighth control example according to the third embodiment, and a ninth control example according to the third embodiment.

[0027] Hereinafter, embodiments of an imaging device and an imaging method will be described with reference to the drawings. The following description will focus on the main components of the imaging device, but the imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0028] First Embodiment FIG. 1 is a block diagram showing an example of the system configuration of an imaging system to which the technology according to the present disclosure is applied.

[0029] 1, an imaging system 10 to which the technology according to the present disclosure is applied includes an imaging lens 11, an imaging device 20, a recording unit 12, and a control unit 13. The imaging system 10 is an example of an electronic device according to the present disclosure, and examples of such electronic devices include a camera system mounted on an industrial robot and an in-vehicle camera system.

[0030] In the imaging system 10 configured as described above, the imaging lens 11 captures incident light from a subject and forms an image on the imaging surface of the imaging device 20. The imaging device 20 obtains imaging data by photoelectrically converting the incident light captured by the imaging lens 11 on a pixel-by-pixel basis. An imaging device according to the present disclosure, which will be described later, is used as this imaging device 20.

[0031] The imaging device 20 performs predetermined signal processing such as image recognition processing on the captured image data, and outputs data indicating the processing result and an address event detection signal (hereinafter simply referred to as a "detection signal") to the recording unit 12. A method for generating the address event detection signal will be described later. The recording unit 12 stores the data supplied from the imaging device 20 via a signal line 14. The control unit 13 is, for example, configured by a microcomputer, and controls the imaging operation of the imaging device 20.

[0032] [Imaging Device According to First Configuration Example (Scanning Method)] The imaging device according to the first configuration example is an imaging device to which a synchronous readout method is applied. This imaging device is a scanning method imaging device, the same as a normal imaging device that captures images at a predetermined frame rate.

[0033] FIG. 2 is a block diagram showing an example of the configuration of an imaging device according to a first configuration example, that is, a scanning type imaging device, which is used as the imaging device 20 in the imaging system 10 to which the technology according to the present disclosure is applied.

[0034] As shown in FIG. 2, an imaging device 20 according to a first configuration example of an imaging device of the present disclosure includes a pixel array section 21, a driving section 22, a column processing section 24, a signal processing section 25, and a readout area selection section 27.

[0035] The pixel array unit 21 includes a plurality of pixels 30. The plurality of pixels 30 output an output signal in response to a selection signal from the readout region selection unit 27. Each of the plurality of pixels 30 may be configured to have a quantizer within the pixel, as shown in FIG. 3, for example. The plurality of pixels 30 output an output signal corresponding to the amount of change in light intensity. The plurality of pixels 30 may be arranged two-dimensionally in a matrix, as shown in FIG. 2.

[0036] [Configuration Example of Pixel Array Unit] FIG. 3 is a block diagram showing an example of the configuration of the pixel array unit 21. As shown in FIG.

[0037] In the pixel array section 21, which is made up of a plurality of pixels 30 arranged two-dimensionally in a matrix, each of the plurality of pixels 30 has a light receiving section 31, a pixel signal generating section 32, and an address event detecting section 33.

[0038] In the pixel 30 having the above configuration, the light receiving unit 31 performs photoelectric conversion on incident light to generate a photocurrent. Then, under the control of the drive unit 22 (see FIG. 2 ), the light receiving unit 31 supplies the photocurrent generated by photoelectric conversion to either the pixel signal generation unit 32 or the address event detection unit 33.

[0039] The pixel signal generation unit 32 generates a pixel signal SIG, which is a voltage signal corresponding to the photocurrent supplied from the light receiving unit 31, and supplies this generated pixel signal SIG to the column processing unit 24 (see Figure 2) via the vertical signal line VSL.

[0040] The address event detector 33 detects the presence or absence of an address event based on whether the change in photocurrent from each light-receiving unit 31 exceeds a predetermined threshold. The address event may be, for example, an ON event indicating that the change in photocurrent exceeds an upper threshold, or an OFF event indicating that the change in photocurrent falls below a lower threshold. The address event detector 33 according to this embodiment can generate, for example, a 1-bit ON detection signal indicating whether an ON event has occurred, a 1-bit OFF detection signal indicating whether an OFF event has occurred, and a 1-bit detection signal indicating whether either an ON event or an OFF event has occurred. For example, the ON detection signal, the OFF detection signal, and the detection signal each indicate a true value (e.g., 1) or a false value (e.g., 0). For example, the ON detection signal indicates a true value when an ON event has occurred and a false value when an ON event has not occurred. Similarly, the OFF detection signal indicates a true value when an OFF event has occurred and a false value when an OFF event has not occurred. Similarly, the detection signal indicates a true value when at least one of an ON event and an OFF event has occurred and a false value when neither an ON event nor an OFF event has occurred.

[0041] When an address event occurs, the address event detection unit 33 supplies an address event detection signal to the drive unit 22 and the signal processing unit 25. The address event detection unit 33 according to this embodiment corresponds to a detection circuit unit. Furthermore, multiple address event detection units 33 can be configured as a single circuit outside the pixel 30.

[0042] 2 again, the driver 22 drives the pixel array unit 21 for each frame in accordance with a control signal from the controller 13 (see FIG. 1). The driver 22 outputs pixel signals generated by the pixels 30 for each row selected by a readout region selector 27 (described later) to the column processor 24. At this time, the driver 22 outputs pixel signals generated by the pixels 30 to the column processor 24 in accordance with detection signals output by the address event detector 33 for each selected row.

[0043] Furthermore, the driving unit 22 performs a first driving operation to reset the accumulated charges in a partial region of the plurality of pixels 30 in accordance with the determination of the signal processing unit 25. Furthermore, the driving unit 22 can perform a second driving operation to reset the accumulated charges in the entire region of the plurality of pixels 30 at a predetermined cycle.

[0044] [Configuration Example of Column Processing Unit] Fig. 4 is a block diagram showing an example of the configuration of the column processing unit 24 of the imaging device 20 according to Configuration Example 1. As shown in Fig. 4, the column processing unit 24 according to this example has a configuration including a plurality of analog-to-digital converters (ADCs) 241 arranged for each pixel column of the pixel array unit 21.

[0045] Although the configuration example in which the analog-to-digital converters 241 are arranged in a one-to-one correspondence with the pixel columns of the pixel array unit 21 has been exemplified here, the present invention is not limited to this configuration example. For example, a configuration in which the analog-to-digital converters 241 are arranged for each of a plurality of pixel columns, and the analog-to-digital converters 241 perform processing among the plurality of pixel columns by time division, may also be adopted.

[0046] The analog-to-digital converter 241 converts the analog pixel signal SIG supplied via the vertical signal line VSL into a digital signal with a larger number of bits than the address event detection signal described above. For example, if the address event detection signal is 2 bits, the pixel signal is converted into a digital signal with 3 or more bits (e.g., 16 bits). The analog-to-digital converter 241 supplies the digital signal generated by the analog-to-digital conversion to the signal processing unit 25. Note that the column processing unit 24 may be configured to include, for example, a column selection circuit that arbitrates signals entering the column processing unit 24. Furthermore, the column processing unit 24 may be configured to output not only information about active pixels that have detected an event, but also information about inactive pixels that have not detected an event. Note that the column processing unit 24 according to this embodiment corresponds to the detection unit.

[0047] 2 again, the signal processing unit 25 performs predetermined signal processing such as CDS (Correlated Double Sampling) processing and image recognition processing on the digital signal supplied from the column processing unit 24. Then, the signal processing unit 25 supplies a signal including data indicating the processing result and information related to the detection signal supplied from the address event detection unit 33 (described later) to the recording unit 12 (see FIG. 1) via the signal line 14.

[0048] Furthermore, the signal processing unit 25 determines the range in which the above-described first driving is performed based on the number of occurrences of detection signals within a predetermined time period that are supplied from the address event detection unit 33. In this case, the signal processing unit 25 causes the driving unit 22 to perform the first driving for each row, for example. Alternatively, the signal processing unit 25 causes the driving unit 22 to perform the first driving for each of a plurality of rows, for example.

[0049] The signal processing unit 25 can be configured to output not only information about active pixels that have detected an event, but also information about inactive pixels that have not detected an event. Address information and timestamp information (e.g., (X, Y, T)) of the active pixels that have detected an event are output from the signal processing unit 25 via the output line 14. However, the data output from the column processing unit 24 may be not only address information and timestamp information, but also frame-format information (e.g., (0, 0, 1, 0, ...)). Details of the signal processing unit 25 will be described later.

[0050] The readout region selection unit 27 selects a portion of the plurality of pixels 30 included in the pixel array unit 21. For example, the readout region selection unit 27 selects one or more rows from among the rows included in the two-dimensional matrix structure corresponding to the pixel array unit 21. The readout region selection unit 27 sequentially selects one or more rows according to a preset cycle. The readout region selection unit 27 may also determine the selection region in response to a request from each pixel 30 in the pixel array unit 21.

[0051] 5 is a circuit diagram showing an example of the circuit configuration of the pixel 30. As described above, each of the plurality of pixels 30 includes a light receiving unit 31, a pixel signal generating unit 32, and an address event detecting unit 33.

[0052] In the pixel 30 having the above configuration, the light receiving unit 31 includes a light receiving element (photoelectric conversion element) 311, a transistor 312, and a transistor 313. For example, an N-type MOS (Metal Oxide Semiconductor) transistor is used as the transistor 312 and the transistor 313. The transistor 312 and the transistor 313 are connected in series to each other.

[0053] The light receiving element 311 is connected to a common connection node N １ and ground, and performs photoelectric conversion on incident light to generate charges in an amount corresponding to the amount of incident light.

[0054] 2 is supplied to the gate electrode of the transistor 312. In response to the transfer signal TRG, the transistor 312 supplies the charge photoelectrically converted by the light receiving element 311 to the pixel signal generation unit 32.

[0055] A control signal OFG is supplied from the driving unit 22 to the gate electrode of the transistor 313. In response to the control signal OFG, the transistor 313 supplies the electrical signal generated by the light receiving element 311 to the address event detection unit 33. The electrical signal supplied to the address event detection unit 33 is a photocurrent made up of electric charges.

[0056] The pixel signal generation unit 32 includes a reset transistor 321, an amplification transistor 322, a selection transistor 323, and a floating diffusion layer 324. The reset transistor 321, the amplification transistor 322, and the selection transistor 323 are, for example, N-type MOS transistors.

[0057] The pixel signal generation unit 32 receives charges photoelectrically converted by the light receiving element 311 from the light receiving unit 31 via the transistor 312. The charges supplied from the light receiving unit 31 are accumulated in the floating diffusion layer 324. The floating diffusion layer 324 generates a voltage signal having a voltage value corresponding to the amount of accumulated charge. In other words, the floating diffusion layer 324 converts the charges into a voltage.

[0058] The reset transistor 321 is connected to the power supply voltage V ＤＤ and the floating diffusion layer 324. The reset transistor 321 initializes (resets) the amount of charge in the floating diffusion layer 324 in response to a reset signal RST.

[0059] Furthermore, the drive unit 22 supplies a reset signal RST to the pixels 30 in a specific region in accordance with a control signal from the signal processing unit 25. As a result, the pixel array unit 21 has a first drive in which the reset signal RST is supplied to the pixels 30 in a specific region in accordance with the control of the signal processing unit 25, and a second drive in which initialization (resetting) of all the pixels 30 is periodically executed.

[0060] The amplifier transistor 322 receives the power supply voltage V ＤＤ The amplifier transistor 322 is connected in series with the selection transistor 323 between the power supply line and the vertical signal line VSL. The amplifier transistor 322 amplifies the voltage signal converted from charge to voltage by the floating diffusion layer 324.

[0061] A selection signal SEL is supplied to the gate electrode of the selection transistor 323 from the drive unit 22. In response to the selection signal SEL, the selection transistor 323 outputs the voltage signal amplified by the amplification transistor 322 as a pixel signal SIG to the column processing unit 24 (see FIG. 2) via the vertical signal line VSL.

[0062] The driver 22 supplies a reset signal RST to the pixel signal generator 32 after a predetermined time has passed since the driver 22 supplied the selection signal SEL to the pixel signal generator 32. This resets the pixel 30 to its initial state, thereby preventing the pixel 30 from being selected again once.

[0063] In an imaging device 20 having a pixel array section 21 in which pixels 30 having the above-described configuration are arranged two-dimensionally, when the control section 13 shown in FIG. 1 instructs the drive section 22 to start detecting an address event, the drive section 22 supplies a control signal OFG to the transistor 313 of the light receiving section 31 to drive the transistor 313 and supply a photocurrent to the address event detection section 33.

[0064] Furthermore, when an address event is detected in a certain pixel 30, the driving unit 22 turns off the transistor 313 of that pixel 30 to stop the supply of photocurrent to the address event detection unit 33. Next, the driving unit 22 drives the transistor 312 by supplying a transfer signal TRG to the transistor 312, causing the transistor 312 to transfer the charge photoelectrically converted by the light receiving element 311 to the floating diffusion layer 324.

[0065] In this way, the imaging device 20 having the pixel array unit 21 in which the pixels 30 having the above configuration are arranged two-dimensionally outputs only pixel signals of the pixels 30 in which an address event is detected to the column processing unit 24. This makes it possible to reduce the power consumption of the imaging device 20 and the amount of image processing compared to when pixel signals of all pixels are output regardless of whether an address event occurs.

[0066] Note that the configuration of the pixel 30 illustrated here is merely an example, and is not limited to this configuration example. For example, a pixel configuration without the pixel signal generation unit 32 is also possible. In this pixel configuration, the transistor 313 is omitted from the light receiving unit 31, and the function of the transistor 313 is given to the transistor 312.

[0067] [Configuration Example of Address Event Detector] Fig. 6 is a block diagram showing a configuration example of the address event detector 33. As shown in Fig. 6, the address event detector 33 according to this configuration example includes a current-voltage converter 331, a buffer 332, a subtractor 333, a quantizer 334, an arithmetic circuit 335, a signal holding circuit 336, a transfer unit 337, and a control circuit 338.

[0068] The current-voltage converter 331 converts the photocurrent from the light receiving unit 31 of the pixel 30 into a logarithmic voltage signal. The current-voltage converter 331 supplies the converted voltage signal to the buffer 332. The buffer 332 buffers the voltage signal supplied from the current-voltage converter 331 and supplies it to the subtractor 333.

[0069] The subtractor 333 receives a row drive signal from the driver 22. The subtractor 333 reduces the level of the voltage signal supplied from the buffer 332 in accordance with the row drive signal. The subtractor 333 then supplies the voltage signal after the reduction in level to the quantizer 334. The quantizer 334 quantizes the voltage signal supplied from the subtractor 333 into a digital signal and outputs it to the arithmetic circuit 335 as an address event detection signal. For example, the quantizer 334 sequentially supplies an ON detection signal and an OFF detection signal to the arithmetic circuit 335.

[0070] The arithmetic circuit 335 performs a logical operation based on the on detection signal and the off detection signal supplied in order from the quantizer 334, and generates a detection signal. For example, the arithmetic circuit 335 supplies the value of the first supplied signal of the on detection signal and the off detection signal to the signal holding circuit 336. Next, if one of the value of the next supplied signal of the on detection signal and the off detection signal and the value of the first supplied signal held by the signal holding circuit 336 is a true value, the arithmetic circuit 335 supplies a signal indicating the true value to the signal holding circuit 336, and if both are false values, the arithmetic circuit 335 supplies a signal indicating a false value to the signal holding circuit 336. In this way, if at least one of the on detection signal and the off detection signal is a true value, the arithmetic circuit 335 outputs a detection signal indicating a true value, and if both are false values, the arithmetic circuit 335 outputs a detection signal indicating a false value.

[0071] The signal hold circuit 336 is provided between the arithmetic circuit 335 and the transfer unit 337, and accumulates the calculation results of the arithmetic circuit 335 based on the sample signal supplied from the control circuit 338. The signal hold circuit 336 may be a sampling circuit such as a switch, plastic, or capacitor, or may be a digital memory circuit such as a latch or flip-flop. The signal hold circuit 336 according to this embodiment has a so-called one-latch (Latch) configuration, in which one circuit is configured for the on detection signal and one for the off detection signal. This allows the area of ​​the signal hold circuit 336 to be smaller than that of a so-called two-latch (Latch) configuration, in which one signal hold circuit 336 is configured for each of the on detection signal and the off detection signal.

[0072] The transfer unit 337 transfers the address event detection signal supplied from the quantizer 334 to the arbiter unit 23 etc. When an address event is detected, the transfer unit 337 supplies a request for transmission of the address event detection signal to the arbiter unit 23. Then, when the transfer unit 337 receives a response to the request from the arbiter unit 23, it supplies the address event detection signal to the drive unit 22 and the signal processing unit 25.

[0073] The control circuit 338 supplies a predetermined threshold voltage V to the inverting (−) input terminal of the comparator 3341. ｔｈ The control circuit 338 supplies a threshold voltage V ｔｈ is a voltage value that varies in a time division manner. For example, the control circuit 338 may set a threshold voltage V ｔｈ１ , and a threshold voltage V corresponding to an OFF event indicating that the amount of change falls below the lower limit threshold. ｔｈ２ This allows a single comparator 3341 to generate an ON detection signal and an OFF detection signal.

[0074] 7 is a diagram showing voltage fluctuations based on accumulated charge in the light-receiving element 311. The horizontal axis represents time, and the vertical axis represents voltage. Line L112 represents the lower threshold of the address event detection unit 33, and line L114 represents voltage fluctuations based on accumulated charge after reset. Line L116 represents the auto-zero potential of the ADC 241 when there is no fluctuation in accumulated charge. Line L118 represents the upper threshold of the address event detection unit 33.

[0075] As shown in Figure 7, the accumulated charge in the light-receiving element 311 after reset decreases over time. As a result, the difference between the upper threshold L116 and the potential L114 after reset increases from d10 to d12 over time. This causes fluctuations in the amount of light received by the light-receiving element 311, and the amount of light received by the light-receiving element 311 may not exceed the upper threshold even if it would normally exceed it. Alternatively, even if charge exceeding the lower threshold is accumulated in the light-receiving element 311, the amount of light received by the light-receiving element 311 may not exceed the lower threshold.

[0076] 8 shows an example of a row that is rarely activated. If the second driving mode, which resets all pixels, is not executed for a period of several frames, even if such a row is selected, the accumulated charge will not be read out.

[0077] 9 is a diagram showing an example of a circuit configuration according to this embodiment. An OR circuit O22 is provided between the drive unit 22 and the signal processing unit 25. As described above, the signal processing unit 25 counts the detection signal for each pixel 30 and can determine the row in which a pixel 30 that does not output a detection signal is located. Therefore, in this embodiment, the accumulated charge of the light receiving element 311 is reset in response to a control signal from the signal processing unit 25 in addition to a control signal from the control unit 13 (see FIG. 1).

[0078] FIG. 10 is a diagram showing a first control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame. The EVS control state represents the control state according to the control signal from the control unit 13 (see FIG. 1). The accessed row represents the access state to the pixels 30. "All rows" means all the pixels 30, and "some" means some of the pixels among all the pixels 30.

[0079] The detection period S12 is a period during which accumulation is performed in the light receiving elements 311. During this period, accumulation is performed in all rows of the pixels 30. The reset period S14 is a period during which the charges in the floating diffusion layers 324 (see FIG. 5) are initialized. During this period, accumulation is performed in all rows of the pixels 30.

[0080] The data read period S16 is a period during which luminance signals are read out from the pixels 30 that output the detection signals. Line RD is the readout start period for each row. As described above, the luminance signals for each row are read out at the timing indicated by line RD, and the luminance signals of the pixels 30 that output the detection signals are read out and initialized.

[0081] On the other hand, the reset period S18 is a period for resetting rows in which there are pixels 30 that have a low frequency of outputting detection signals, as determined by the signal processing unit 25. The reset period S18 may be for a single row or multiple rows.

[0082] The signal processing unit 25 counts the frequency of detection signal output for each frame and initializes rows with low detection frequency to the reset period S18. By initializing rows with low detection frequency to the reset period S18 in this way, it is possible to suppress the occurrence of pixels 30 with a decrease in accumulated charge.

[0083] FIG. 11 is a diagram showing a second control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame. The EVS control state represents the control state according to the control signal from the control unit 13 (see FIG. 1). The accessed row represents the access state to the pixels 30. "All rows" means all the pixels 30, and "some" means some of the pixels among all the pixels 30.

[0084] 11 differs from the first control example in that the period S14 in which all pixels 30 are reset is periodically repeated. By periodically repeating the period S14 in which all pixels 30 are reset in this manner, it is possible to further suppress the occurrence of pixels 30 in which the accumulated charge decreases.

[0085] FIG. 12 is a diagram showing a third control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame. The EVS control state represents the control state according to the control signal from the control unit 13 (see FIG. 1). The accessed row represents the access state to the pixels 30. "All rows" refers to all the pixels 30, and "some" refers to some of the pixels among all the pixels 30. The data readout period S16 is not shown in the figure.

[0086] 12, the second and third control examples differ from the first control example in that the reset period S20 changes the row to be reset in each frame in sequence. The reset period S20 may be for a single row or multiple rows.

[0087] In this way, by cyclically setting the set period S20 for resetting the pixels 30 and sequentially changing the reset rows, it is possible to uniformly suppress the occurrence of pixels 30 in which the accumulated charge decreases.

[0088] FIG. 13 is a diagram showing a fourth control example according to this embodiment. The horizontal axis represents time. The EVS synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame. The EVS control state represents the control state according to the control signal from the control unit 13 (see FIG. 1). The accessed row represents the access state to the pixels 30. "All rows" refers to all the pixels 30, and "some" refers to some of the pixels among all the pixels 30. The data readout period S16 is not shown in the figure.

[0089] 13 , the fourth control example differs from the third control example in that the reset period S22 randomly changes the order of rows to be reset in each frame. The reset period S22 may be for a single row or multiple rows. By periodically setting the set period S22 for resetting the pixels 30 and randomly changing the reset row in this manner, it is possible to uniformly suppress the occurrence of pixels 30 with a decrease in accumulated charge and to prevent the reset stripes from becoming periodic in each row.

[0090] FIG. 14 is a diagram showing an example of a data structure according to this embodiment. As shown in FIG. 14, the signal processing unit 25 (see FIG. 2) is a diagram showing an example of the frame structure of one frame of event data transmitted to the recording unit 12. In this way, one frame of event data is stored in multiple long packets arranged in a line between a frame start FS, which is a short packet indicating the start of the frame, and a frame end FE, which is a short packet indicating the end of the frame. In the example shown in FIG. 14, a long packet storing embedded data is arranged at the beginning of the long packet storing the event data. The signal processing unit 25 according to this embodiment corresponds to the output unit.

[0091] A long packet has a packet header PH and a packet footer PF. The packet header PH contains a data type DT indicating the type of data stored in the long packet, and the data type DT can be used to distinguish whether embedded data EBD, spare data LH, or pixel data DATA is stored. The data type DT may be placed in the packet header PH or at the beginning of the area in the long packet where data is stored. As shown in FIG. 14, data indicating the position of the reset row is stored in the embedded data EBD.

[0092] Fig. 15 is a diagram showing one row of data in the example of the data format shown in Fig. 14. As shown in Fig. 15, data indicating the position of the reset row may be stored in the spare data LH.

[0093] 16A and 16B are diagrams schematically illustrating an example of processing in a subsequent image processing device. (a) is a diagram schematically illustrating a row in which data has been lost due to initialization. As described above, initialization may result in less information in the captured image than in other rows. (b) is a diagram illustrating an example in which interpolation processing is performed using a data signal for a reset row included in the data structure. As shown in (b), the data structure makes it possible to determine whether the data information in the reset row has been lost due to initialization or was not originally present. As a result, in cases in which data has been lost due to initialization, the data structure can be used to determine this, allowing interpolation.

[0094] As described above, according to this embodiment, in addition to the second drive in which the drive unit 22 periodically initializes all of the light receiving units 31, the drive unit 22 also has the first drive in which the accumulated charge in a partial region of all of the light receiving units 31 is reset. This makes it possible to suppress a drop in potential due to the accumulated charge from the timing of resetting in the second drive.

[0095] Second Embodiment The imaging device 20 according to the first embodiment is a scanning type, whereas the imaging device 20 according to the second embodiment is an arbiter type. The differences from the imaging device 20 according to the first embodiment will be described below.

[0096] Fig. 17 is a diagram showing a configuration example of an imaging device 20 according to the second embodiment. As shown in Fig. 17 , the imaging device 20 according to the second configuration example as an imaging device of the present disclosure is an asynchronous imaging device called EVS, and is configured to include a pixel array unit 21, a drive unit 22, an arbiter unit (arbitration unit) 23, a column processing unit 24, and a signal processing unit 25.

[0097] In the imaging device 20 having the above configuration, a plurality of pixels 30 are two-dimensionally arranged in a matrix (array) in the pixel array section 21. Vertical signal lines VSL (Vertical Signal Lin) are wired for each pixel column in this matrix-like pixel arrangement.

[0098] Each of the plurality of pixels 30 generates a pixel signal, which is an analog signal of a voltage corresponding to the photocurrent. Each of the plurality of pixels 30 detects the presence or absence of an address event based on whether or not the amount of change in the photocurrent exceeds a predetermined threshold. When an address event occurs, the pixel 30 outputs a request to the arbiter unit 23.

[0099] The driving section 22 drives each of the plurality of pixels 30 to output a pixel signal generated in each pixel 30 to the column processing section 24 .

[0100] The arbiter unit 23 arbitrates requests from each of the multiple pixels 30 and transmits a response based on the arbitration result to the pixel 30. Upon receiving the response from the arbiter unit 23, the pixel 30 supplies a detection signal indicating the detection result (address event detection signal) to the drive unit 22 and the signal processing unit 25. The detection signal from the pixel 30 can also be read out from multiple rows.

[0101] The column processing unit 24 is composed of, for example, an analog-to-digital converter, and performs processing to convert, into digital signals, analog pixel signals output from the pixels 30 in each pixel column of the pixel array unit 21. Then, the column processing unit 24 supplies the digital signals after analog-to-digital conversion to the signal processing unit 25.

[0102] The signal processing unit 25 performs predetermined signal processing such as CDS (Correlated Double Sampling) processing and image recognition processing on the digital signal supplied from the column processing unit 24. Then, the signal processing unit 25 supplies data indicating the processing result and the detection signal supplied from the arbiter unit 23 to the recording unit 12 (see FIG. 1 ) via the signal line 14.

[0103] The signal processing unit 25 counts the detection signals of each pixel 30, and outputs a control signal to the driving unit 22 to reset the pixels 30 that have output a detection signal less frequently. In response to this, the driving unit 22 resets the pixels 30 that have output a detection signal less frequently.

[0104] FIG. 18 is a diagram showing an example of control according to the second embodiment. The horizontal axis represents time. The EVS reset synchronization signal tr on the other vertical axis is a synchronization control signal from the control unit 13 (see FIG. 1). In accordance with this EVS reset synchronization signal tr, the signal processing unit 25 outputs a reset control signal sr to the drive unit 22. The reset control signal sr includes a reset address, which is the address of the pixel 30 to be reset. This enables the drive unit 22 to perform a first drive that resets pixels 30 that have output a detection signal less frequently.

[0105] The data readout is a period during which the photo-pixel signals are read out through arbitration by the arbiter unit 23, separate from the reset by the reset control signal sr. The second drive, which is a reset of all the pixels 30, is executed at the start of the drive.

[0106] As described above, according to this embodiment, the driving unit 22 has a first drive that resets pixels 30 that have output a detection signal less frequently, in addition to the second drive that periodically initializes all of the light receiving units 31. This makes it possible to suppress a drop in potential due to accumulated charge from the timing of resetting in the second drive.

[0107] Third Embodiment An imaging device 20 according to a third embodiment differs from the imaging device 20 according to the first embodiment in that a pixel block 30 a includes a plurality of gradation pixels 308 a and EVS pixels 308 b. The differences from the imaging device 20 according to the first embodiment will be described below.

[0108] 19 is a block diagram showing an example configuration of an imaging device 20 according to a third embodiment. As shown in FIG. 19 , the imaging device 20 according to the present disclosure is an apparatus capable of performing asynchronous imaging called EVS and synchronous imaging for gradation images in parallel. The imaging device 20 includes a pixel array unit 21, a first access control circuit 211 a, a second access control circuit 211 b, an AD converter 212 a, an EVS readout circuit 212 b, a first signal processing unit 213, a second signal processing unit 214, a timestamp generation circuit 215, a timing control circuit 216, and output interfaces 217 and 218.

[0109] The gradation pixel 308a has, for example, a light receiving element (photoelectric conversion element) 311 and a pixel signal generation unit 32 of the pixel 30 shown in Fig. 5. For example, the light receiving element (photoelectric conversion element) 311 is directly connected to the floating diffusion layer 324. The EVS pixel 308b has, for example, the same configuration as the pixel 30 shown in Fig. 5.

[0110] The configuration of the pixel block 30a will now be described with reference to FIG. 20 . FIG. 20 is a diagram schematically illustrating the configuration of the pixel block 30a. As shown in FIG. 20 , the pixel block 30a includes a plurality of gradation pixels 308a, EVS pixels 308b, and an EVS AFE (Analog Front End) 314. In this pixel block 30a, a plurality of gradation pixels 308a and EVS pixels 308b are arranged in a matrix. A first vertical signal line is wired to this pixel arrangement for each pixel column of the gradation pixels 308a. In addition, a second vertical signal line, independent of the first vertical signal line, is wired for each pixel column of the EVS pixels 308b. Each of the plurality of gradation pixels 308a generates an analog signal having a voltage corresponding to a photocurrent as a gradation luminance signal, and outputs the analog signal to the AD converter 212a (see FIG. 19 ).

[0111] On the other hand, the EVS pixel 308b outputs an analog signal of a voltage corresponding to the photocurrent to the EVS AFE 314. The EVS pixel 308b also generates an analog signal of a voltage corresponding to the photocurrent as an EVS luminance signal, and outputs the signal to the EVS readout circuit 212b (see FIG. 19 ) when an address event occurs.

[0112] The EVS AFE (Analog Front End) 314 generates a detection signal from a voltage signal based on the output of the EVS pixel 308b and outputs the detection signal to the second signal processing unit 214 (see FIG. 19 ). More specifically, the EVS AFE 314 detects the presence or absence of an address event based on whether the amount of change in photocurrent in the EVS pixel 308b exceeds a predetermined threshold. The EVS AFE 314 then outputs the detection signal to the second signal processing unit 214. For example, the EVS AFE 314 outputs address information (X, Y), timestamp information T, and address event information VCH and VCL of the detected active pixel to the second signal processing unit 214 as, for example, event information (X, Y, T, VCH, VCL). These multiple gradation pixels 308a, the EVS pixels 308b, and the EVS AFE 314 can operate in parallel by independent control systems.

[0113] 19 , the first access control circuit 211a controls the plurality of gradation pixels 308a. That is, the first access control circuit 211a controls the generation of gradation luminance signals according to the amount of accumulated photoelectric conversion current, the output of gradation luminance signals, etc. For example, the first access control circuit 211a outputs the photoelectric conversion current accumulated in each of the plurality of gradation pixels 308a to the AD converter 212a as gradation luminance signals in sequence for each row.

[0114] The second access control circuit 211b controls the multiple EVS AFEs 314. The second access control circuit 211b according to this embodiment causes the multiple EVS AFEs 314 to detect address events row by row in sequence and output detection signals to the second signal processing unit 214 row by row in sequence. The second access control circuit 211b also causes the luminance signals of the EVS pixels 308b in which address events have been detected to be output to the EVS readout circuit 212b row by row in sequence. The second access control circuit 211b also performs a first drive that refreshes a portion of all EVS pixels 308b or a second drive that refreshes all EVS pixels 308b in accordance with the second signal processing unit 214. Note that the second access control circuit 211b according to this embodiment corresponds to a drive unit.

[0115] The AD converter 212a includes an ADC for each column of the gradation pixels 308a arranged in each pixel block 30a, 30b. The ADC converts the analog gradation luminance signals supplied via the first vertical signal lines into digital signals. The ADC of the AD converter 212a supplies the generated digital signals to the first signal processing unit 213.

[0116] The EVS readout circuit 212b includes an ADC for each column of the EVS pixels 308b arranged in each pixel block 30a, 30b. The ADC converts the analog EVS luminance signal supplied via the vertical signal line VSL2 into a digital signal. The ADC of the EVS readout circuit 212b supplies the generated digital signal to the second signal processing unit 214.

[0117] 19 again, the first signal processing unit 213 performs predetermined signal processing such as CDS (Correlated Double Sampling) processing and image recognition processing on the digital signal from the AD converter 212a. The signal processing unit 212 supplies data indicating the processing results and a detection signal to the recording unit 12 (see FIG. 1) via a signal line 209.

[0118] The second signal processing unit 214 performs predetermined signal processing on the detection signals from the multiple EVS AFEs 314. For example, the second signal processing unit 214 arranges the detection signals as pixel signals in a two-dimensional grid to generate an EVS image. The second signal processing unit 214 also causes the second access control circuit 211b to initialize (refresh) predetermined EVS pixels 308b in synchronization with a control signal from the first access control circuit 211a.

[0119] The timestamp generation circuit 215 generates timestamp information T and supplies it to each component of the solid-state imaging device 200. For example, the timestamp generation circuit 215 supplies the timestamp information T to a plurality of AFEs 314 for EVS.

[0120] The timing control circuit 216 controls the timing of each component of the solid-state imaging device 200. For example, the timing control circuit 216 controls the timing of the first access control circuit 211a and the second access control circuit 211b.

[0121] The output interface 217 outputs the image data and the like supplied from the first signal processing unit 213 to the recording unit 12. Similarly, the output interface 218 outputs the image data and the like supplied from the second signal processing unit 214 to the recording unit 12.

[0122] 21 is a diagram schematically showing the flow of signals between the first access control circuit 211a, the second access control circuit 211b, and the second signal processing unit 214. An OR circuit O22 is connected between the second signal processing unit 214 and the second access control circuit 211b. As a result, the second access control circuit 211b executes a second drive that refreshes all of the EVS pixels 308b based on a control signal from the control unit 13, and a first drive that refreshes a portion of all of the EVS pixels 308b based on a control signal from the second signal processing unit 214.

[0123] The row selection signals SEL_SH / RD are signals for selecting the gradation pixels 308a for each row, the transfer signals TRG_SH / RD are signals for transferring signals from the light receiving portions of the gradation pixels 308a to the floating diffusion layers, and the reset signals RST_SH / RD are signals for resetting the floating diffusion layers of the gradation pixels 308a. Each signal includes address information for the row or the gradation pixels 308a.

[0124] The second signal processing unit 214 references the row selection signals SEL_SH / RD, the transfer signals TRG_SH / RD, and the reset signals RST_SH / RD, and outputs a control signal including information about the row of the EVS pixels 308b to be reset to the second access control circuit 211b. As a result, as described above, the second access control circuit 211b executes the first drive that refreshes a portion of all the EVS pixels 308b.

[0125] FIG. 22 is a diagram showing a fifth control example according to the third embodiment. The horizontal axis represents time. The EVS frame synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the EVS pixel 308b. The EVS control state represents the control state according to the control signal from the control unit 13 (see FIG. 1). The gradation frame synchronization signal S30 is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the gradation pixel 308a. The access row address represents the row of the pixel array unit 21.

[0126] The detection period S12 is a period during which the EVS pixels 308b accumulate charges. During this period, the EVS pixels 308b in all rows perform accumulation. The reset period S14 is a period during which the charges of the EVS pixels 308b are initialized. During this period, the EVS pixels 308b in each row of the pixel array portion 21 are initialized in order.

[0127] The data read period S16 is a period during which luminance signals are read out from the pixels 30 that output the detection signals. Line RD is the readout start period for each row. As described above, the luminance signals for each row are read out at the timing indicated by line RD, and the luminance signals of the pixels 30 that output the detection signals are read out and initialized.

[0128] The line SH indicates the timing at which the gradation pixels 308a are initialized, and the line RD indicates the timing at which the light detection signals are read out from the gradation pixels 308a. That is, the gradation pixels 308a are initialized and the light detection signals are read out for each row.

[0129] In this way, the signal processing unit 25 initializes the EVS pixels 308b of each row S26 of the pixel array unit 21 in synchronization with the timing of the line SH. By initializing the EVS pixels 308b of each row S26 of the pixel array unit 21 in this way in synchronization with the timing of the line SH, it is possible to suppress the occurrence of EVS pixels 308b with a decrease in accumulated charge.

[0130] FIG. 23 is a diagram showing a sixth control example according to the third embodiment. The horizontal axis represents time. The EVS frame synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the EVS pixel 308b. The gradation frame synchronization signal S34 is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the gradation pixel 308a. The access row address indicates a row in the pixel array unit 21 (see FIG. 19).

[0131] In synchronization with the timing of the lines SH and RD, the signal processing unit 25 initializes the EVS pixels 308b in each row S26 of the pixel array unit 21. By initializing the EVS pixels 308b in each row S26 of the pixel array unit 21 in this way in synchronization with the timing of the lines SH and RD, it is possible to further suppress the occurrence of EVS pixels 308b whose accumulated charge decreases.

[0132] FIG. 24 is a diagram showing a seventh control example according to the third embodiment. The horizontal axis represents time. The EVS frame synchronization signal S10 on the vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the EVS pixel 308b. The gradation frame synchronization signal S34 is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the gradation pixel 308a. The access row address indicates a row in the pixel array unit 21 (see FIG. 19).

[0133] The signal processing unit 25 initializes the EVS pixels 308b in each row S26 of the pixel array unit 21 in synchronization with the timing of the line RD. In this way, by initializing the EVS pixels 308b in each row S26 of the pixel array unit 21 in synchronization with the timing of the line RD, it is possible to suppress the occurrence of EVS pixels 308b with a decrease in accumulated charge.

[0134] FIG. 25 is a diagram showing an eighth control example according to the third embodiment. The horizontal axis represents time. The EVS frame synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the EVS pixels 308b. The EVS control state represents the control state according to the control signal from the control unit 13 (see FIG. 1). The gradation pixels 308a are controlled by a so-called global shutter method. That is, this example differs from the seventh control example according to the third embodiment in that the luminance signals of all pixels are transferred by line transfer and the luminance signals of all pixels are reset by line SH.

[0135] In this way, even in the global shutter method, by initializing the EVS pixels 308b of each row S26 of the pixel array section 21 in synchronization with the timing of line RD, it is possible to suppress the occurrence of EVS pixels 308b with a decrease in accumulated charge.

[0136] FIG. 26 is a diagram illustrating a ninth control example according to the third embodiment. The horizontal axis represents time. The EVS frame synchronization signal S10 on the other vertical axis is a control signal from the control unit 13 (see FIG. 1) and serves as the start signal for each frame in the EVS pixels 308b. The EVS control state represents the control state according to the control signal from the control unit 13 (see FIG. 1). In this manner, the EVS pixels 308b in each row S36 of the pixel array unit 21 are initialized in synchronization with the timing of the lines SH and RD. Furthermore, the EVS pixels 308b in multiple rows are initialized in sequence for each frame. During period S38, the EVS pixels 308b in all pixels are initialized. This further reduces the occurrence of EVS pixels 308b with a decrease in accumulated charge.

[0137] The present technology can be configured as follows:

[0138] (1) An imaging device comprising: a pixel array section in which a plurality of first pixels are arranged in a matrix and output a luminance signal according to the amount of light; a detection circuit section that outputs a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels exceeds a predetermined threshold; and a drive section having a first drive that resets the accumulated charge of the first pixels in a partial region within the plurality of first pixels.

[0139] (2) The imaging device according to (1), wherein the first driving is performed for each row.

[0140] (3) The imaging device according to (1), wherein the first driving is performed for each of a plurality of rows.

[0141] (4) The imaging device according to (1), further comprising a signal processing unit that determines a range in which the first drive is to be performed based on the number of occurrences of the detection signal within a predetermined time, and the drive unit performs the first drive in accordance with the determination of the signal processing unit.

[0142] (5) The imaging device according to (4), wherein the pixel array unit performs imaging in units of different frames, and the signal processing unit determines a range in which the first driving is performed based on the number of occurrences of the detection signals in a single frame.

[0143] (6) The imaging device according to (4), wherein the pixel array unit performs imaging in units of different frames, and the signal processing unit determines a range in which the first driving is performed based on the number of occurrences of the detection signals in a plurality of frames.

[0144] (7) The imaging device according to (1), wherein the drive section causes the first pixels that output the detection signals to output luminance signals corresponding to the light amounts on a row-by-row basis.

[0145] (8) The imaging device according to (1), further including an arbiter unit that arbitrates the detection signals and causes the first pixels to output luminance signals according to the amount of light to the drive unit.

[0146] (9) The imaging device according to (1), further comprising: an output unit that generates a signal of a data type including information indicating the first pixel that has undergone the first driving.

[0147] (10) The imaging device according to (9), wherein the output unit generates a signal including information indicating the first pixel in at least one of a line header of a packet and embedded data.

[0148] (11) The imaging device according to (1), wherein the drive section further includes a second drive that resets all of the plurality of first pixels.

[0149] (12) The imaging device according to (2), wherein the driving section performs the first driving for each randomly selected row.

[0150] (13) The imaging device according to (1), wherein the pixel array unit further includes a plurality of second pixels for gradation arranged in a matrix, and a gradation image can be generated based on output signals of the plurality of second pixels.

[0151] (14) The imaging device according to (13), wherein the drive section performs the first driving based on a control signal when control is performed on the second pixel.

[0152] (15) The imaging device according to (13), wherein the drive unit performs the first driving based on a control signal when initialization or readout is performed on the second pixel.

[0153] (16) The imaging device according to (13), wherein the drive section performs the first driving on the first pixels in a row in which the second pixels are initialized or in which readout is performed.

[0154] (17) The imaging device according to (13), wherein the drive unit performs the first driving on the first pixels in at least one of a row in which the second pixels are initialized and a row in which a readout is performed, and a row other than the row in which the second pixels are initialized and the row in which a readout is performed.

[0155] (18) The imaging device according to (17), further comprising: a second drive unit that drives the second pixels; and the accumulated charges of the second pixels are read out for each row.

[0156] (19) The imaging device according to (17), further comprising: a second drive unit that drives the second pixels; and the accumulated charges of the second pixels are read out for every row.

[0157] (20) An imaging method comprising: a detection step of outputting a detection signal indicating the occurrence of an address event when each luminance signal of a plurality of first pixels that output a luminance signal according to the amount of light exceeds a predetermined threshold; and a drive circuit step of executing a first drive that resets the accumulated charges of the first pixels in a partial region within the plurality of first pixels.

[0158] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0159] 20: imaging device, 21: pixel array unit, 22: drive unit, 23: arbiter unit, 24: column processing unit, 25: signal processing unit, 33: address event detection unit, 311: light receiving element, 211a: first access control circuit, 211b: second access control circuit, 214: second signal processing unit.

Claims

1. An imaging device comprising: a pixel array unit in which a plurality of first pixels that output luminance signals according to the amount of light are arranged in a matrix; a detection circuit unit that outputs a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels exceeds a predetermined threshold value; and a drive unit having a first drive for resetting the charge accumulated in the first pixels in a partial region within the plurality of first pixels.

2. The imaging device according to claim 1, wherein the first drive is executed every time the first drive is performed.

3. The imaging device according to claim 1, wherein the first drive is executed for every plurality of rows.

4. Further comprising a signal processing unit that determines a range in which the first drive is to be executed based on the number of occurrences of the detection signal within a predetermined time, and wherein the drive unit executes the first drive according to the determination of the signal processing unit. The imaging device according to claim 1.

5. The imaging device according to claim 4, wherein the pixel array unit performs imaging in different frame units, and the signal processing unit determines a range in which the first drive is to be executed based on the number of occurrences of the detection signal in a single frame.

6. The imaging device according to claim 4, wherein the pixel array unit performs imaging in different frame units, and the signal processing unit determines a range in which the first drive is to be executed based on the number of occurrences of the detection signal in a plurality of frames.

7. The imaging device according to claim 1, wherein the drive unit causes the first pixels that output the detection signal to output luminance signals according to the amount of light in units of rows.

8. The imaging device according to claim 1, further comprising an arbiter unit that arbitrates the detection signal and causes the first pixels to output luminance signals according to the amount of light to the drive unit.

9. The imaging device according to claim 1, further comprising an output unit that generates a signal of a data type including information indicating the first pixels for which the first drive has been executed.

10. The imaging device according to claim 9, wherein the output unit generates a signal including information indicating the first pixels in at least one of a packet line header and embedded data.

11. The imaging device according to claim 1, wherein the drive unit further has a second drive for resetting all of the plurality of first pixels.

12. The imaging device according to claim 2, wherein the drive unit executes the first drive for each randomly selected row.

13. The imaging device according to claim 1, wherein the pixel array unit further includes a plurality of second pixels for gradation arranged in a matrix, and a gradation image can be generated based on output signals of the plurality of second pixels.

14. The imaging device according to claim 13, wherein the driving unit executes the first driving based on a control signal when executing control for the second pixel.

15. The imaging device according to claim 13, wherein the driving unit executes the first driving based on a control signal when executing initialization or reading for the second pixel.

16. The imaging device according to claim 13, wherein the driving unit executes the first driving for the first pixel in a row where the second pixel is initialized or a row where reading is executed.

17. The imaging device according to claim 13, wherein the driving unit executes the first driving for the first pixel in at least one of a row where the second pixel is initialized and a row where reading is executed and another row different from the row where the second pixel is initialized and the row where reading is executed.

18. The imaging device according to claim 17, further comprising a second driving unit that drives the plurality of second pixels, wherein the plurality of second pixels have stored charges read out row by row.

19. The imaging device according to claim 17, further comprising a second driving unit that drives the plurality of second pixels, wherein the plurality of second pixels have stored charges read out for each entire row.

20. An imaging method, comprising: a detection step of outputting a detection signal indicating the occurrence of an address event when the luminance signal of each of the plurality of first pixels that output luminance signals corresponding to the amount of light exceeds a predetermined threshold; and a driving circuit step of executing a first driving for resetting the stored charges of the first pixels in a partial area within the plurality of first pixels.

Images