Light detection device and electronic apparatus

Abstract

This disclosure relates to a light detection device and an electronic apparatus with which transfer efficiency can be optimised. This disclosure involves: a photoelectric conversion part for converting light formed in a semiconductor substrate into electric charges; a storage part for temporarily storing the electric charges; and a transfer part configured to transfer the electric charges to the storage part. The transfer part includes a transfer gate at least a part of which is provided in the semiconductor substrate. An extension line in a movement direction of the electric charges at a point where the potential becomes highest within the part of the semiconductor substrate where the potential is modulated by the transfer part intersects with the storage part in a plan view. This disclosure can be applied to, for example, a light detection device that detects a phase difference.

Description

Photodetectors, electronic devices

[0001] The present technology relates to a photodetector device and an electronic device, and more particularly to a photodetector device and an electronic device that are capable of optimizing the transfer efficiency of charges accumulated in a photodiode, for example.

[0002] In general, photodetection devices such as CMOS (Complementary Metal Oxide Semiconductor) image sensors and CCD (Charge Coupled Device) sensors are widely used in digital still cameras, digital video cameras, and the like. For example, incident light entering a CMOS image sensor is photoelectrically converted in a PD (Photodiode) included in each pixel. Then, the charge generated in the PD is transferred to a FD (Floating Diffusion) via a transfer transistor, where it is converted into a pixel signal at a level corresponding to the amount of received light, and then read out.

[0003] Patent Document 1 proposes providing two photodiodes in one pixel and using the two photodiodes as a pair of phase difference detection pixels to detect the phase difference and achieve autofocus.

[0004] International Publication No. 2021 / 193915

[0005] It is desirable to optimize the transfer of charge from the photodiode and improve the transfer efficiency.

[0006] The present technology has been made in view of such circumstances, and makes it possible to optimize transfer efficiency.

[0007] A first photodetector according to one aspect of the present technology is a photodetector comprising: a photoelectric conversion unit formed within a semiconductor substrate that converts light into electric charges; a storage unit that temporarily stores the electric charges; and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit comprises a transfer gate at least a portion of which is provided within the semiconductor substrate; and an extension line of the direction of movement of the electric charges at a point of the semiconductor substrate where the electric potential is modulated by the transfer unit and where the electric potential is highest intersects with the storage unit in a planar view.

[0008] A first electronic device according to one aspect of the present technology is an electronic device comprising: a photoelectric conversion unit formed in a semiconductor substrate that converts light into electric charges; a storage unit that temporarily stores the electric charges; and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit has a transfer gate at least a portion of which is provided in the semiconductor substrate; an extension line of the direction in which the electric charges move at a point of the semiconductor substrate where the electric potential is modulated by the transfer unit and where the electric potential is highest intersects with the storage unit in a planar view; and a processing unit that processes signals from the photodetection device.

[0009] A second photodetector according to one aspect of the present technology is a photodetector including a photoelectric conversion unit formed in a semiconductor substrate that converts light into electric charges, a storage unit that temporarily stores the electric charges, and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit includes a transfer gate at least a portion of which is provided in the semiconductor substrate, and a first line passing through one surface of the transfer gate intersects with the storage unit in a planar view.

[0010] A second electronic device according to one aspect of the present technology is an electronic device including: a photoelectric conversion unit formed in a semiconductor substrate that converts light into electric charges; a storage unit that temporarily stores the electric charges; and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit includes a transfer gate at least a portion of which is provided in the semiconductor substrate, and a first line passing through one surface of the transfer gate intersects with the storage unit in a planar view; a photodetector; and a processing unit that processes signals from the photodetector.

[0011] A third photodetector according to one aspect of the present technology is a photodetector including: a photoelectric conversion unit formed in a semiconductor substrate that converts light into electric charges; an accumulation unit that temporarily accumulates the electric charges; and a transfer unit configured to transfer the electric charges to the accumulation unit, wherein the transfer unit includes two transfer gates, at least a portion of which is provided in the semiconductor substrate; and a first line that passes through the center between the two transfer gates and is perpendicular to the arrangement direction of the two transfer gates intersects with the accumulation unit in a planar view.

[0012] A third electronic device according to one aspect of the present technology is an electronic device including: a photoelectric conversion unit formed in a semiconductor substrate that converts light into electric charges; a storage unit that temporarily stores the electric charges; and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit includes two transfer gates, at least a portion of which is provided in the semiconductor substrate, and a line that passes through the center between the two transfer gates and is perpendicular to the arrangement direction of the two transfer gates intersects with the storage unit in a planar view; a photodetector; and a processing unit that processes signals from the photodetector.

[0013] A first photodetector according to one aspect of the present technology includes a photoelectric conversion unit formed within a semiconductor substrate that converts light into electric charges, a storage unit that temporarily stores the electric charges, and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit includes a transfer gate at least a portion of which is provided within the semiconductor substrate, and an extension line of the direction of movement of the electric charges at a point of the semiconductor substrate where the electric potential is modulated by the transfer unit and where the electric potential is highest intersects with the storage unit in a planar view.

[0014] A first electronic device according to an aspect of the present technology includes the first photodetector.

[0015] A second photodetector according to one aspect of the present technology includes a photoelectric conversion unit formed within a semiconductor substrate that converts light into electric charges, a storage unit that temporarily stores the electric charges, and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit includes a transfer gate at least a portion of which is provided within the semiconductor substrate, and a first line passing through one surface of the transfer gate intersects with the storage unit in a planar view.

[0016] A second electronic device according to an aspect of the present technology includes the second photodetector.

[0017] A third photodetector according to one aspect of the present technology includes a photoelectric conversion unit formed within a semiconductor substrate that converts light into electric charges, a storage unit that temporarily stores the electric charges, and a transfer unit configured to transfer the electric charges to the storage unit, and the transfer unit includes two transfer gates, at least a portion of which is provided within the semiconductor substrate, and a first line that passes through the center between the two transfer gates and is perpendicular to the arrangement direction of the two transfer gates intersects with the storage unit in a planar view.

[0018] A third electronic device according to an aspect of the present technology includes the third photodetector.

[0019] The electronic device may be an independent device or an internal block that constitutes a single device.

[0020] 1 is a diagram illustrating a configuration of an embodiment of a photodetector to which the present technology is applied. FIG. 2 is a diagram for explaining a stacked structure of a photodetector. FIG. 3 is a diagram for explaining an example of a circuit configuration of a pixel. FIG. 4 is a diagram for explaining another example of a circuit configuration of a pixel. FIG. 5 is a diagram for explaining another example of a circuit configuration of a pixel. FIG. 6 is a diagram for explaining a cross-sectional configuration of a pixel. FIG. 7 is a diagram for explaining a planar configuration of a pixel in a 1-1th embodiment. FIG. 8 is a diagram for explaining a planar configuration of a pixel in a 1-1th embodiment. FIG. 9 is a diagram for explaining a planar configuration of a pixel in a 1-2th embodiment. FIG. 10 is a diagram for explaining a planar configuration of a pixel in a 1-3th embodiment. FIG. 11 is a diagram for explaining a planar configuration of a pixel in a 2-1th embodiment. FIG. 12 is a diagram for explaining a cross-sectional configuration of a pixel in a 2-2th embodiment. FIG. 13 is a diagram for explaining a planar configuration of a pixel in a 2-3th embodiment. FIG. 3 is a diagram showing an example of a planar configuration of a pixel in embodiment 3-1. FIG. 4 is a diagram showing an example of a cross-sectional configuration of a pixel in embodiment 3-1. FIG. 5 is a diagram showing an example of a planar configuration of a pixel in embodiment 3-2. FIG. 6 is a diagram showing an example of a planar configuration of a pixel in embodiment 3-3. FIG. 7 is a diagram showing an example of a planar configuration of a pixel in embodiment 4-1. FIG. 8 is a diagram showing an example of a cross-sectional configuration of a pixel in embodiment 4-1. FIG. 9 is a diagram showing an example of a planar configuration of a pixel in embodiment 4-2. FIG. 10 is a diagram showing an example of a planar configuration of a pixel in embodiment 4-3. FIG. 11 is a diagram showing an example of a planar configuration of a pixel in embodiment 5-1. FIG. 12 is a diagram showing an example of a cross-sectional configuration of a pixel in embodiment 5-1. FIG. 13 is a diagram showing an example of a planar configuration of a pixel in embodiment 5-2. FIG. 14 is a diagram showing an example of a planar configuration of a pixel in embodiment 5-3. FIG. 15 is a diagram showing an example of a planar configuration of a pixel in embodiment 6-1. FIG. 16 is a diagram showing an example of a planar configuration of a pixel in embodiment 6-2. FIG. 17 is a diagram showing an example of a planar configuration of a pixel in embodiment 7.FIG. 13 is a diagram showing an example of a cross-sectional configuration of a pixel in a seventh embodiment. FIG. 14 is a diagram showing an example of a planar configuration of a pixel in an eighth embodiment. FIG. 15 is a diagram showing an example of a planar configuration of another pixel in the eighth embodiment. FIG. 16 is a block diagram showing an example of the configuration of an electronic device. FIG. 17 is a block diagram showing an example of a schematic configuration of an endoscopic surgery system. FIG. 18 is a block diagram showing an example of the functional configuration of a camera head and a CCU. FIG. 19 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of the installation positions of an outside vehicle information detection unit and an imaging unit.

[0021] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described.

[0022] <Schematic Configuration Example of Photodetector> Fig. 1 shows a configuration example of an embodiment of a photodetector to which the present technology is applied. The photodetector 1 in Fig. 1 is configured to have a pixel array section 20 in which a plurality of pixels 100 are arranged in a two-dimensional array on a semiconductor substrate 10 made of, for example, silicon, and a peripheral circuit section surrounding the pixel array section. The peripheral circuit section includes a vertical drive circuit section 21, a column signal processing circuit section 22, a horizontal drive circuit section 23, an output circuit section 24, a control circuit section 25, etc.

[0023] The pixel 100 includes a photodiode as a photoelectric conversion element and a plurality of pixel transistors, such as a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, and is configured as a MOS transistor.

[0024] The control circuit unit 25 receives an input clock and data instructing the operation mode and the like, and outputs data such as internal information of the photodetector 1. That is, the control circuit unit 25 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit unit 21, the column signal processing circuit unit 22, the horizontal drive circuit unit 23, etc., based on a vertical synchronization signal, a horizontal synchronization signal, and a master clock. The control circuit unit 25 outputs the generated clock signals and control signals to the vertical drive circuit unit 21, the column signal processing circuit unit 22, the horizontal drive circuit unit 23, etc.

[0025] The vertical drive circuit unit 21 is configured with, for example, a shift register, selects a predetermined pixel drive line 26, supplies a pulse for driving the pixels 100 to the selected pixel drive line 26, and drives the pixels 100 row by row. That is, the vertical drive circuit unit 21 selects and scans each pixel 100 in the pixel array unit 20 row by row in the vertical direction, and supplies a pixel signal based on a signal charge generated in the photoelectric conversion unit of each pixel 100 according to the amount of received light to the column signal processing circuit unit 22 through the vertical signal line 27.

[0026] The column signal processing circuit unit 22 is arranged for each column of pixels 100, and performs signal processing such as noise removal for each pixel column on signals output from one row of pixels 100. For example, the column signal processing circuit unit 22 performs signal processing such as CDS (Correlated Double Sampling) or DDS (Double Data Sampling) for removing fixed pattern noise specific to the pixel, and AD conversion.

[0027] The horizontal drive circuit unit 23 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, selects each of the column signal processing circuit units 22 in turn and causes each of the column signal processing circuit units 22 to output a pixel signal to the horizontal signal line 28.

[0028] The output circuit unit 24 processes and outputs signals sequentially supplied from each of the column signal processing circuits 22 via the horizontal signal line 28. The output circuit unit 24 may perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 29 exchanges signals with the outside.

[0029] The photodetector 1 configured as above is a CMOS image sensor called a column AD type in which the column signal processing circuit unit 22 that performs CDS processing or DDS processing and AD conversion processing is arranged for each pixel column.

[0030] <Layered Structure> The photodetector 1 can have a layered structure as shown in Fig. 2. The photodetector 1 includes three substrates: a first substrate 50, a second substrate 60, and a third substrate 70. The photodetector 1 can have a three-dimensional structure formed by bonding together the three substrates: the first substrate 50, the second substrate 60, and the third substrate 70. The first substrate 50, the second substrate 60, and the third substrate 70 are layered in this order.

[0031] The first substrate 50 has, on a semiconductor substrate 51, a plurality of pixels 100 that perform photoelectric conversion. The plurality of pixels 100 are arranged in a matrix within a pixel array section 20 on the first substrate 50. The second substrate 60 has, on the semiconductor substrate 61, readout circuit sections 62 that output pixel signals based on electric charges output from the pixels 100, one for every four pixels 100. Note that, although the description will be continued using an example in which one readout circuit section 62 is provided for every four pixels 100, a configuration in which one readout circuit section 62 is provided for every two pixels 100 may also be used. The second substrate 60 has a plurality of pixel drive lines 26 extending in the row direction and a plurality of vertical signal lines 27 extending in the column direction.

[0032] The third substrate 70 has a logic circuit 72 that processes pixel signals on a semiconductor substrate 71. The logic circuit 72 has, for example, a vertical drive circuit unit 21, a column signal processing circuit unit 22, a horizontal drive circuit unit 23, and a control circuit unit 25. The logic circuit 72 (specifically, the horizontal drive circuit unit 23) outputs an output signal Dout converted into a digital signal for each pixel 100 to the outside. In the logic circuit 72, for example, low-resistance regions made of silicide formed using a salicide (self-aligned silicide) process such as CoSi2 or NiSi may be formed on the surfaces of impurity diffusion regions in contact with the source electrode and the drain electrode.

[0033] The vertical drive circuit unit 21, for example, sequentially selects a plurality of pixels 100 row by row. The column signal processing circuit unit 22, for example, performs correlated double sampling on pixel signals output from each pixel 100 in the row selected by the vertical drive circuit unit 21. The column signal processing circuit unit 22 extracts the signal level of the pixel signal by, for example, performing CDS processing, and holds pixel data corresponding to the amount of light received by each pixel 100. The horizontal drive circuit unit 23, for example, sequentially outputs the pixel data held in the column signal processing circuit unit 22 to the outside. The control circuit unit 25, for example, controls the driving of each block (the vertical drive circuit unit 21, the column signal processing circuit unit 22, and the horizontal drive circuit unit 23) in the logic circuit 72.

[0034] 3 shows an example of a pixel 100 and a readout circuit unit 62. In FIG. 3, a case will be described in which four pixels 100 share one readout circuit unit 62. Here, "shared" means that the outputs of the four pixels 100 are input to a common readout circuit unit 62.

[0035] Each pixel 100 has common components. In Fig. 3, in order to distinguish the components of each pixel 100 from one another, an identification number (1, 2, 3, 4) is added to the end of the reference numeral of the component of each pixel 100. Hereinafter, when it is necessary to distinguish the components of each pixel 100 from one another, an identification number is added to the end of the reference numeral of the component of each pixel 100, but when it is not necessary to distinguish the components of each pixel 100 from one another, the identification number at the end of the reference numeral of the component of each pixel 100 will be omitted.

[0036] Each pixel 100 includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate charge according to the amount of light received. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a pixel drive line 26. The transfer transistor TR is, for example, a complementary metal oxide semiconductor (CMOS) transistor.

[0037] The floating diffusions FD of the pixels 100 that share one readout circuit unit 62 are electrically connected to each other and to the input terminal of the common readout circuit unit 62. The readout circuit unit 62 includes, for example, a reset transistor RST, a selection transistor SEL, and an amplification transistor AMP. Note that the selection transistor SEL may be omitted as necessary. The source of the reset transistor RST (the input terminal of the readout circuit unit 62) is electrically connected to the floating diffusion FD, and the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the amplification transistor AMP.

[0038] The gate of the reset transistor RST is electrically connected to the vertical signal line 27. The source of the amplification transistor AMP is electrically connected to the drain of the selection transistor SEL, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. The source of the selection transistor SEL (the output terminal of the readout circuit unit 62) is electrically connected to the vertical signal line 27, and the gate of the selection transistor SEL is electrically connected to the pixel drive line 26.

[0039] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR extends from the surface of the semiconductor substrate 51 through the well layer 42 to a depth reaching the PD 41, as shown in FIG. 12 (described later), for example. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD.

[0040] The selection transistor SEL controls the output timing of the pixel signal from the readout circuit unit 62. The amplification transistor AMP generates a pixel signal with a voltage corresponding to the level of charge held in the floating diffusion FD. The amplification transistor AMP forms a source follower amplifier and outputs a pixel signal with a voltage corresponding to the level of charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 27. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0041] 4 is a diagram showing another circuit configuration of the photodetector 1. The photodetector 1 shown in FIG. 4 shows a circuit configuration in which two subpixels are arranged in parallel within one pixel 100. A pixel having two subpixels arranged in parallel within one pixel 100 is used, for example, when performing autofocus (AF) operation. When operating in autofocus mode, a color filter of the same color and one on-chip lens are provided on a photodiode (one pixel) made up of two divided photodiodes, and each of the divided photodiodes receives light that has passed through a part of the imaging optical system.

[0042] When performing autofocus operation, the photodetector 1 detects image shifts of the divided photodiodes to measure the distance to the subject, and focuses the image by signal processing using the distance measurement information.

[0043] In a photodetector 1 having a similar configuration, different exposure time control is performed between sub-pixels, signals with different exposure times are synthesized by signal processing to construct an image over a wide exposure area, and an HDR (High Dynamic Range) operation that expands the dynamic range can also be configured.

[0044] In the circuit configuration example of the photodetector 1 shown in FIG. 4 , the pixel circuit has a photodiode PD_L and a photodiode PD_R. In this case, a unit pixel is composed of one pixel 100 (two sub-pixels). The photodiodes PD_L and PD_R may have the same characteristics, or may have different characteristics. For example, one of the photodiodes PD_L and PD_R may perform photoelectric conversion on incident light in a wavelength band different from that of the other.

[0045] In Fig. 4, the unit pixel has a transfer gate TG_L and a transfer gate TG_R. The pixel circuit shown in Fig. 4 controls the readout of photocharges from the photodiodes PD_L and PD_R, ​​respectively, based on the transfer gates TG_L and TG_R. The capacitance Cfd is the capacitance of the floating diffusion.

[0046] Components such as a floating diffusion (FD), reset transistor RST, amplifier transistor AMP, and select transistor SEL are shared within a unit pixel, and pixel signals from each pixel (photodiode PD_L and photodiode PD_R) are transmitted via the same vertical signal line.

[0047] FIG. 5 shows another example circuit configuration of the photodetector 1. In the example circuit configuration of the photodetector 1 shown in FIG. 5, the pixel circuit includes photodiodes PD1_L, PD1_R, PD2_L, and PD2_R. In this case, the unit pixel is composed of two pixels 100 (four sub-pixels). The photodiodes PD1_L, PD1_R, PD2_L, and PD2_R may have the same characteristics or different characteristics. For example, some or all of the photodiodes PD1_L, PD1_R, PD2_L, and PD2_R may photoelectrically convert incident light in a different wavelength band from the others.

[0048] In FIG. 5, the unit pixel has a transfer gate TG1_L, a transfer gate TG1_R, a transfer gate TG2_L and a transfer gate TG2_R.

[0049] 5 controls the readout of photocharges from the photodiodes PD1_L, PD1_R, PD2_L, and PD2_R based on the transfer gates TG1_L, TG1_R, TG2_L, and TG2_R. The capacitance Cfd is the capacitance of the floating diffusion.

[0050] Components such as a floating diffusion (FD), reset transistor, amplification transistor, and selection transistor are shared within a unit pixel, and pixel signals from each pixel (photodiode PD1_L, photodiode PD1_R, photodiode PD2_L, and photodiode PD2_R) are transmitted to each other via the same vertical signal line.

[0051] Fig. 6 shows another example of the circuit configuration of the photodetector 1. In the example of the circuit configuration of the photodetector 1 shown in Fig. 6, the pixel circuit has photodiodes PD1_L, PD1_R, PD2_L, PD2_R, PD3_L, PD3_R, PD4_L, and PD4_R. In this case, the unit pixel is made up of four pixels 100 (eight sub-pixels).

[0052] The photodiodes PD1_L, PD1_R, PD2_L, PD2_R, PD3_L, PD3_R, PD4_L, and PD4_R may have the same characteristics as one another, or may have different characteristics from one another. For example, some or all of the photodiodes PD1_L, PD1_R, PD2_L, PD2_R, PD3_L, PD3_R, PD4_L, and PD4_R may perform photoelectric conversion on incident light in a wavelength band different from that of the others.

[0053] In FIG. 6, the unit pixel has transfer gates TG1_L, TG1_R, TG2_L, TG2_R, TG3_L, TG3_R, TG4_L, and TG4_R.

[0054] 6 controls readout of photocharges from photodiodes PD1_L, PD1_R, PD2_L, PD2_R, PD3_L, PD3_R, PD4_L, and PD4_R based on transfer gates TG1_L, TG1_R, TG2_L, TG2_R, TG3_L, TG3_R, TG4_L, and TG4_R. Capacitance Cfd is the capacitance of the floating diffusion.

[0055] Components such as a floating diffusion (FD), reset transistor, amplification transistor, and selection transistor are shared within a unit pixel, and pixel signals from each pixel (photodiode PD1_L, photodiode PD1_R, photodiode PD2_L, photodiode PD2_R, photodiode PD3_L, photodiode PD3_R, photodiode PD4_L, and photodiode PD4_R) are transmitted to each other via the same vertical signal line.

[0056] In the embodiment described below, the explanation will be continued using as an example a pixel 100 having a structure in which two sub-pixels are arranged in parallel within one pixel 100 as shown in FIG. 4 , but the present technology can be appropriately applied to any of the circuit configurations described above, as well as to circuit configurations not described here.

[0057] <Example of a Cross-Sectional Configuration of a Photodetector> Fig. 7 shows an example of a cross-sectional configuration taken along line B-B' of the example of the planar configuration of pixel 100 shown in Fig. 10, and Fig. 8 is a diagram showing an example of a cross-sectional configuration taken along line C-C', and more specifically, corresponds to a cross section of pixel 100 cut along the thickness direction of semiconductor substrate 51. The example of the cross-sectional configuration of pixel 100 will also be explained as appropriate in each of the embodiments described below.

[0058] 7 and 8 , the pixel 100 includes an on-chip lens 200, a color filter 202, a light-shielding portion (light-shielding film) 204, a semiconductor substrate 51, and transfer gates 400 a and 400 b. The semiconductor substrate 51 includes a pair of photodiodes 300 a and 300 b, each of which includes a photodiode 300. The semiconductor substrate 51 also includes a protrusion 304 that separates the pair of photodiodes 300 a and 300 b, an inter-pixel isolation portion 310 that surrounds the photodiodes 300 a and 300 b, and a diffusion region 306 provided around the protrusion 304 and the inter-pixel isolation portion 310.

[0059] In the following description, the description will proceed from the top (light-receiving surface 11a side) to the bottom in FIG. 7 . As shown in FIGS. 7 and 8 , the pixel 100 has one on-chip lens 200 that is provided above the light-receiving surface 11a of the semiconductor substrate 51 and focuses incident light onto the photodiode 300. The pixel 100 has a structure in which a pair of photodiodes 300a, 300b is provided for one on-chip lens 200. In other words, the on-chip lens 200 is shared by the two photodiodes 300a, 300b. The on-chip lens 200 can be formed, for example, from a silicon nitride film (SiN) or a resin material such as a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer resin, or a siloxane-based resin.

[0060] The incident light collected by the on-chip lens 200 is irradiated onto each of the pair of photodiodes 300 a and 300 b via a color filter 202 provided below the on-chip lens 200. The color filter 202 can be any of a color filter that transmits red wavelength components, a color filter that transmits green wavelength components, and a color filter that transmits blue wavelength components. It may also be a filter that transmits infrared light, a transparent (white) filter, or a yellow, magenta, cyan, or other color filter. The color filter 202 can be formed from a material in which a pigment or dye is dispersed in a transparent binder such as silicon.

[0061] A light-shielding portion 204 is provided on the light-receiving surface 11a of the semiconductor substrate 51 so as to surround the color filter 202. The light-shielding portion 204 is provided between adjacent pixels 100, thereby suppressing crosstalk between the adjacent pixels 100 and providing light shielding between the pixels 100 in order to further improve the accuracy of phase difference detection and improve image quality. The light-shielding portion 204 can be formed from a metal material containing, for example, tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), nickel (Ni), or the like.

[0062] The photodiode 300 is, for example, a region having impurities of a first conductivity type (e.g., N type) in a semiconductor substrate 51 of a second conductivity type (e.g., P type). As described above, the photodiode 300 absorbs light incident through the color filter 202 and generates electric charges.

[0063] The photodiodes 300a and 300b are physically separated by a protrusion 304. The protrusion 304 is made of a groove (trench) (not shown) that penetrates or does not penetrate the semiconductor substrate 51 along the thickness direction of the semiconductor substrate 51, and a material filled in the trench, such as an oxide film or a metal film, such as silicon oxide (SiO), silicon nitride, amorphous silicon, polycrystalline silicon, titanium oxide (TiO), aluminum, or tungsten. Providing the protrusion 304 effectively physically separates the photodiodes 300a and 300b, thereby suppressing color mixing.

[0064] When the pixel 100 is viewed from the light-receiving surface 11a side, a slit 312 ( FIG. 9 ) corresponding to the space between the two protrusions 304 is provided near the center of the pixel 100. As shown in FIGS. 7 and 8 , in the region of the slit 312 in the semiconductor substrate 51 (an example of a region positioned around the protrusion 304 and extending in the thickness direction of the semiconductor substrate 51), for example, a P-type impurity is diffused via the protrusion 304 by conformal doping, thereby forming a diffusion region 306.

[0065] The diffusion region 306 electrically isolates the pair of photodiodes 300a, 300b and prevents color mixing. Because the protrusion 304 penetrates the semiconductor substrate 51, the diffusion region 306 can be formed deep within the semiconductor substrate 51 (here, "depth" refers to the distance from the light-receiving surface 11a and the surface 11b of the semiconductor substrate 51 along the thickness direction of the semiconductor substrate 51) by conformal doping via the protrusion 304. This can suppress color mixing and further improve the accuracy of phase difference detection. Also, as shown in FIG. 8 , a diffusion region 313 containing a lower P-type impurity concentration than the diffusion region 306 is formed in the region sandwiched between the diffusion regions 306 and the slits 312, and a diffusion region 315 containing an N-type impurity (N- in the figure) is formed in a portion of the diffusion region 313.

[0066] An inter-pixel isolation portion 310 is provided in the semiconductor substrate 51, surrounding the photodiodes 300a and 300b and physically isolating adjacent pixels 100. The inter-pixel isolation portion 310 is made of a groove (trench) (not shown) that penetrates the semiconductor substrate 51 in the thickness direction of the semiconductor substrate 51, and a material filled in the trench, such as an oxide film or a metal film, such as a silicon oxide film, a silicon nitride film, amorphous silicon, polycrystalline silicon, titanium oxide film, aluminum, or tungsten. In other words, the protrusion 304 and the inter-pixel isolation portion 310 may be formed from the same material. Note that, since the inter-pixel isolation portion 310 and the protrusion 304 have similar configurations, they can have an integrated form and can be formed simultaneously.

[0067] The charges generated in the photodiodes 300a and 300b are transferred via transfer gates 400a and 400b of transfer transistors provided on the surface 11b of the semiconductor substrate 51, which is located on the opposite side from the light-receiving surface 11a. The transfer gates 400a and 400b can be formed, for example, from a metal film. The transfer gates 400a and 400b shown in FIG. 7 are formed from a metal film on the surface 11b, but as will be described with reference to FIG. 12, they can also have a structure having vertical electrodes provided vertically within the semiconductor substrate 51.

[0068] The charges stored in the photodiodes 300a and 300b may be stored, for example, in a floating diffusion portion (charge storage portion) (not shown) provided in a semiconductor region having a first conductivity type (e.g., N type) provided in the semiconductor substrate 51.

[0069] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 1-1> Fig. 9 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 1-1. The plane configuration example shown in Fig. 9 is a diagram of the pixel 100 viewed from the front surface 11b side. Fig. 12 is a diagram showing a cross-sectional configuration example of the pixel 100 taken along line A-A' in Fig. 9. In Fig. 12, the upper direction in the figure is the front surface 11b side, and the lower direction in the figure is the light-receiving surface 11a side.

[0070] 9, the pixel 100 includes a sub-pixel 100a and a sub-pixel 100b that are adjacent to each other. The sub-pixel 100a includes a photodiode 300a, and the sub-pixel 100b includes a photodiode 300b.

[0071] The photodiode 300a and the photodiode 300b are separated by a protrusion 304 formed integrally with the inter-pixel separation section 310. In detail, when viewed from the front surface 11b, the inter-pixel separation section 310 has two protrusions 304 that protrude along the column direction toward the center of the pixel 100 and face each other. Here, when the pixel 100 is viewed from the front surface 11b side, the region between the two protrusions 304 that is located near the center of the pixel 100 is referred to as a slit 312.

[0072] When the pixel 100 is viewed from above the surface 11b, the two protrusions 304 are provided at the center of the pixel 100 in the row direction, and their protruding lengths (lengths in the column direction) are approximately the same. The width of the protrusions 304 is not particularly limited as long as it can separate the pair of photodiodes 300a, 300b.

[0073] The presence of the slit 312 near the center of the pixel 100 suppresses scattering of light by the protrusion 304. Therefore, light incident on the center of the pixel 100 can be incident on the photodiodes 300a and 300b without being scattered. As a result, the pixel 100 can more reliably capture light incident on the center of the pixel 100, thereby preventing degradation of the imaging pixel.

[0074] A conductor portion made of, for example, polysilicon is formed in the inter-pixel isolation portion 310. An N+ conductor portion 351 made of N-type doped polysilicon is formed at the portion where the protrusion portion 304 and the inter-pixel isolation portion 310 intersect, on the upper side in the figure. Referring to the cross-sectional configuration example in FIG. 12 , the N+ conductor portion 351 is formed on the surface 11b side of the semiconductor substrate 51, above the inter-pixel isolation portion 310 in the figure, and is configured to contact the FD 251a. The FD is configured to include the FD 251a and the N+ conductor portion 351. A wiring 355 ( FIG. 12 ) is connected to the N+ conductor portion 351, and a signal from the FD 251a is supplied to the logic circuit 72 on the third substrate 70 ( FIG. 2 ) via the pixel circuit on the second substrate 60 ( FIG. 2 ).

[0075] In the planar configuration example shown in Fig. 9, the FD 251a is formed on the lower left side of the N+ conductor portion 351. In the cross-sectional configuration example shown in Fig. 12, the FD 251a is formed on the right side adjacent to the N+ conductor portion 351. Charges accumulated in the photodiode 300a are transferred to the FD 251a. The FD 251a can be formed, for example, by thermal diffusion of donors from the N+ conductor portion 351 when the N+ conductor portion 351 is formed. The FD 251a is formed in a triangular shape.

[0076] Note that the present embodiment also includes cases where the side corresponding to the base of the triangular FD 251a is not linear. For example, a shape with a curved or partially curved base is also included in the triangular shape in the following description. The longest line connecting the portions that can be determined to be the area of ​​the FD 251a and that can be determined to be the vertices of the FD 251a is defined as the base (end) of the FD 251a. Furthermore, if the FD 251a has a shape that includes a curve, or other sides that include shapes other than straight lines, when the shape of the FD 251a is made to resemble a triangle, the side that is the base or a tangent line that passes through part of the curve can be defined as the end.

[0077] 10, an FD 251 having a shape in which the vertices at both ends of the triangle are removed and the central portion is recessed is also included in the triangular shape. In the case of the shape of the FD 251 shown in FIG. 10, for example, when the FD 251 is shaped like a triangle, the end portion is the portion that becomes the base when the FD 251 is shaped like a triangle, or the line connecting the points (vertices) on the side closest to the transfer gate 400 is the end portion.

[0078] For example, as shown in FIG. 11, when an end portion has an arc shape, the end portion is defined as a tangent line passing through a point of the arc closest to the transfer gate 400, or as a line connecting the end points of the arc.

[0079] The transfer gate 400a-1 and the transfer gate 400a-2 of the transfer transistor are formed on the lower left side of the FD 251a in FIG. 9 and on the right side in FIG. 12. The transfer gate of the transfer transistor has two gate electrodes and has a gate electrode structure called a twin gate. As shown in FIG. 12, the transfer gate 400a-1 is configured with a vertical electrode that combines an electrode provided in a planar manner on the surface 11b of the semiconductor substrate 51 with an electrode provided vertically within the semiconductor substrate 51. In the first embodiment, the transfer gate 400 of one transfer transistor will be described as an example, where the transfer gate 400 is a twin gate configured with two vertical electrodes.

[0080] A portion of the transfer gate 400a-1 of the transfer transistor is covered with an insulating film 401a-1. In the planar configuration example shown in Fig. 9, when viewed from the surface 11b, for example, the lower right side of the transfer gate 400a-1 in the figure is covered with the insulating film 401a-1. In the cross-sectional configuration example shown in Fig. 12, the vertical electrode of the transfer gate 400a-1 is formed obliquely, and the side surface of the vertical electrode on the right side in the figure is covered with the insulating film 401a-1.

[0081] 12, an insulating film 402 is formed on the surface 11b of the semiconductor substrate 51. The insulating film 402 and the insulating film 401a-1 are given different reference numerals and are shown separately for the sake of explanation, but they can be formed integrally from the same material. The insulating film 401a-1 is a region that does not appear to overlap with the planar electrode formed in the planar direction of the transfer gate 400a-1 in a plan view as shown in FIG. 9, and is an insulating film that is formed within the semiconductor substrate 51 in a cross-sectional view as shown in FIG. 12 and is formed around (part of) the vertical electrode.

[0082] The transfer gate 400a-2 has a configuration similar to that of the transfer gate 400a-1, and includes a vertical electrode, at least a portion of the sidewall of which is covered with an insulating film 401b-1. The positional relationship between the N+ conductor portion 351, the FD 251a, and the transfer gate 400a will be described later with reference to Figures 13 and 14, but they are each arranged in a positional relationship that improves transfer efficiency.

[0083] 9, an FD 251b is formed on the lower right side of the N+ conductor portion 351. Charges accumulated in the photodiode 300b are transferred to the FD 251b. Transfer gates 400b-1 and 400b-2 of the transfer transistors are formed on the lower right side of the FD 251b in FIG.

[0084] The FD 251b, transfer gate 400b-1, and transfer gate 400b-2 included in the sub-pixel 100b have the same configurations as the FD 251a, transfer gate 400a-1, and transfer gate 400a-2 included in the sub-pixel 100a, respectively, and their positional relationships are also basically the same as those of the FD 251a, transfer gate 400a-1, and transfer gate 400a-2, so in the following explanation, the FD 251a, transfer gate 400a-1, and transfer gate 400a-2 included in the sub-pixel 100a will be used as an example. In other words, since the configurations of the sub-pixels 100a and 100b are similar, the explanation will continue here using the sub-pixel 100a as an example.

[0085] The inter-pixel isolation section 310 surrounds the photodiode 300a and is located on the lower left side in the figure, and a P+ conductor section 352 made of P-type doped polysilicon is formed at the intersection of the inter-pixel isolation section 310. Referring to the cross-sectional configuration example in Figure 12, the P+ conductor section 352 is on the front surface 11b side of the semiconductor substrate 51 and is formed above the inter-pixel isolation section 310 in the figure.

[0086] A P+ region 252a is provided on the upper right side of the P+ conductor portion 352 in the drawing. In the cross-sectional configuration example shown in Fig. 12, the P+ region 252a is formed on the left side adjacent to the P+ conductor portion 352. A wiring 356 (Fig. 12) is connected to the P+ region 252a. The P+ region 252a is a region provided for applying a reference potential, and the wiring 356 is connected to, for example, ground (GND).

[0087] The P+ region 252a can be formed, for example, by thermal diffusion of donors from the P+ conductor 352 when the P+ conductor 352 is formed. The P+ region 252a is formed in a triangular shape. Note that this embodiment also includes cases where the side corresponding to the base of the triangular P+ region 252a is not linear. For example, a shape with a curved base will be considered to be included in the triangular shape in the following description.

[0088] The inter-pixel isolation section 310 surrounding the photodiode 300b is located on the lower right side of the drawing, and a P+ conductor section 353 made of P-type doped polysilicon is formed at the intersection of the inter-pixel isolation sections 310. A P+ region 252b is provided on the upper left side of the P+ conductor section 353 in the drawing. A wiring (not shown) connected to ground is connected to the P+ region 252b.

[0089] 12, the inter-pixel isolation portion 310 is composed of a trench formed in the semiconductor substrate 51, a P-type region 321 doped with, for example, a P-type impurity formed on the side surface of the trench, and a filler 322 made of, for example, polysilicon inside the P-type region 321. In addition, an oxide region 323 made of oxide is formed at the top of the inter-pixel isolation portion 310 in the drawing, for example, on the N+ conductor portion 351 side.

[0090] <Position of Transfer Gate> FIG. 13 is a diagram illustrating the positional relationship between the N+ conductor portion 351, the FD 251, the transfer gate 400, and the insulating film 401. As described above, the transfer gate 400 is formed in a shape having a vertical electrode. The transfer gate 400 may be made of, for example, polysilicon (poly-Si), and an insulating film 401 made of, for example, a silicon oxide film or a silicon nitride film is formed on the side of the vertical electrode of the transfer gate 400. By surrounding the side of the transfer gate 400 with the insulating film 401, the FD 251, to which a high voltage is applied, and the transfer gate (portion of the vertical electrode) are not brought into close proximity, thereby suppressing the generation of a high electric field near the portion of the vertical electrode.

[0091] 13, in a plan view, the parallel arrangement direction of the transfer gates 400a-1 and 400a-2 is inclined obliquely with respect to the lattice of the inter-pixel isolation portion 310. If the line connecting the center P1 of the transfer gate 400a-1 and the center P2 of the transfer gate 400a-2 is taken as line L1, then line L1 is inclined obliquely with respect to the inter-pixel isolation portion 310. The angle formed by line L1 and the inter-pixel isolation portion 310 is, for example, approximately 45 degrees.

[0092] The N+ conductor portion 351, which is in contact with the FD 251a and located above the inter-pixel separation portion 310, is formed in a cross shape with two orthogonal crosses. The length between the horizontal and vertical ends of this cross-shaped N+ conductor portion 31 is approximately equal, and the line connecting the two ends forms an angle of approximately 45 degrees. If the center of the horizontal end of the cross-shaped N+ conductor portion 351 is taken as center P3, the center of the vertical end is taken as center P4, and the line connecting center P3 and center P4 is taken as line L2, then line L2 forms an angle of approximately 45 degrees with respect to the inter-pixel separation portion 310.

[0093] The line L2 connects the center of one side of the cross-shaped N+ conductor portion 351 to the center of the other side that is perpendicular to the first side. The line L2 forms an angle of approximately 45 degrees with respect to the inter-pixel separation portion 310.

[0094] The lines L1 and L2 are parallel to each other. The FD 251a is formed by doping through thermal diffusion from the N+ conductor portion 351, and has a triangular shape as shown in FIG. 13, with the base (end) of the triangle at an angle of approximately 45 degrees to the inter-pixel separation portion 310. Therefore, the lines L1, L2, and the bases of the FD 251a are parallel to each other.

[0095] Note that the present embodiment also includes cases where the side corresponding to the base of the triangular FD 251a is not linear. For example, a shape with a curved or partially curved base is also included in the triangular shape in the following description. As will be described later, the FD 251a may be formed in a shape other than a triangle. For example, in a rectangular shape, the FD 251a can be determined to be the region of the FD 251a, and the longest line connecting the vertices of the FD 251a is defined as the base (end) of the FD 251a. The base (end) of the FD 251a is the side closest to the transfer gate 400a, the side farther from the N+ conductor 351, or the side farther from the inter-pixel isolation 310.

[0096] By making the ends of the line L1 and the FD 251a parallel, it is possible to make the distance L3 (not shown) between the transfer gate 400a-1 and the FD 251a equal to the distance L4 (not shown) between the transfer gate 400a-2 and the FD 251a. By making the distance L3 equal to the distance L4, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0097] Let us assume that the distances L3 and L4 are different, for example, the distance L3 is shorter than the distance L4. In this case, the transfer gate 400a-1 is closer to the FD 251a than the transfer gate 400a-2. The difference in distance between the transfer gate 400a and the FD 251a appears as a difference in transfer efficiency. In this case, a difference in transfer efficiency occurs between the transfer gate 400a-1 and the transfer gate 400a-2.

[0098] In the transfer gate 400a-1 located closer to the FD 251a, the electric field is increased due to the voltage difference between the voltage applied when the transfer gate 400a-1 is in the off state and the voltage of the FD 251a, which may generate dark electrons and generate noise.In the transfer gate 400a-2 located farther from the FD 251a, the potential gradient required for transferring signal charges is reduced, which may cause transfer failure.

[0099] If the distances between the two transfer gates 400a-1 and 400a-2 and the FD 251a are different in this way, the characteristics cannot be optimized, and it becomes difficult to fully avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects.

[0100] As described with reference to FIG. 13, according to this embodiment, the distance L3 between the transfer gate 400a-1 and the FD 251a and the distance L4 between the transfer gate 400a-2 and the FD 251a can be made approximately equal, so that a configuration can be achieved that can sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects.

[0101] The positional relationship between the transfer gate 400b-1, transfer gate 400b-2, FD251b, and N+ conductor portion 351 of subpixel 100b is the same as the positional relationship between the transfer gate 400a-1, transfer gate 400a-2, FD251a, and N+ conductor portion 351 of subpixel 100a, and the subpixel 100b is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects.

[0102] 13, the line L1 has been described as a line passing through the center P1 of the transfer gate 400a-1 and the center P2 of the transfer gate 400a-2, but the line L1 may be defined as a line passing through another position of the transfer gate 400. For example, even when the line L1 is a straight line connecting the side of the transfer gate 400a-1 located closer to the FD 251a and the side of the transfer gate 400a-2 located closer to the FD 251a, or when the line L1 is a straight line connecting the side of the transfer gate 400a-1 located farther from the FD 251a and the side of the transfer gate 400a-2 located farther from the FD 251a, the transfer gate 400 is arranged so as to satisfy the above-described positional relationship.

[0103] The relationship between the transfer gate 400 and the FD 251 will be described with reference to Fig. 14, focusing on the charge transfer direction. Like Fig. 13, Fig. 14 is an enlarged view of the transfer gate 400a-1, transfer gate 400a-2, FD 251a, and N+ conductor portion 351. The line L2 connecting the horizontal end and vertical end of the N+ conductor portion 351 is the same as in Fig. 13.

[0104] In FIG. 14, the direction in which the charge read from the photodiode 300a by the transfer transistor is transferred to the FD 251a is represented by lines L5 and L6. Line L5 is a line passing through and following the end of the insulating film 401a-1. Referring again to the cross-sectional configuration example of the pixel 100 shown in FIG. 12, the end of the insulating film 401a-1 can be, for example, the center of the side corresponding to the bottom of the insulating film 401a-1. Alternatively, line L5 may be a portion of the side where the transfer gate 400a-1 and the insulating film 401a-1 contact each other, in other words, a portion of the side surface of the transfer gate 400a-1, for example, the center line of the side surface. Note that if the end of the insulating film 401a-1 has a curved shape, line L5 corresponds to a line that contacts at least a portion of the end and points toward the FD 251a.

[0105] On the line L5, the side closer to the center of the photodiode 300a is designated as position P5, and the side closer to the FD 251a is designated as position P6. The position P5 side is the region corresponding to the source of the transfer transistor, and the position P6 side is the region corresponding to the drain. The charge read out from the photodiode 300a is transferred from position P5 (source) of the transfer gate 400a-1 via the transfer gate 400a-1 to position P6 (drain) of the transfer gate 400a-1, and is supplied to the FD 251a.

[0106] Therefore, line L5 connecting position P5 and position P6 represents the transfer direction. Line L5 and line L2 are in a perpendicular positional relationship. Line L2 and the base of FD 251a are parallel to each other, so line L5 and the base of FD 251a are in a perpendicular positional relationship. Note that if the base of FD 251a is curved, the line that is tangent to at least a portion of the base and points toward FD 251a corresponds to line L5.

[0107] The transfer direction of the transfer gate 400a-1 and the bottom side (end) of the FD 251a are orthogonal to each other. Also, the transfer direction of the transfer gate 400a-1 and the line L2 connecting the centers of the horizontal and vertical ends of the N+ conductor portion 351 are orthogonal to each other.

[0108] The line L6 shown on the transfer gate 400a-2 side is a line that passes through the end of the insulating film 401a-2. Like the line L5, the line L6 is also positioned perpendicular to the line L3 of the N+ conductor portion 351 and perpendicular to the bottom side (end) of the FD 251a.

[0109] A line Lc is set that passes through the center between the lines L5 and L6. The line Lc passes through the center between the transfer gate 400a-1 and the transfer gate 400a-2. The line Lc is also perpendicular to the line L1 (FIG. 13) that runs in the direction in which the transfer gates 400a-1 and 400a-2 are aligned. Therefore, like the lines L5 and L6, the line Lc is also positioned so as to intersect with the line L3 of the N+ conductor portion 351 and with the bottom side (end) of the FD 251a.

[0110] A line Lc that passes through the center between the two transfer gates 400 and is perpendicular to the arrangement direction of the two transfer gates 400 intersects with the FD 251 in a plan view.

[0111] In this way, even when the transfer direction of the transfer gate 400 and the bottom side of the FD 251a are perpendicular to each other, the configuration can sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects, as in the case described with reference to Fig. 13. Furthermore, there is no need to lower the depletion potential of the photodiode in order to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0112] <Regarding the Charge Movement Direction> In the explanation with reference to Figure 14, the charge transfer direction (movement direction) was represented by, for example, a straight line L5, which was explained as a line passing through the end of the insulating film 401a-1. The charge movement direction will be further explained with reference to Figures 15 and 16. Figure 15 is a diagram for explaining the movement direction in the case where the transfer gate 400 has gates formed not only on the surface but also inside the semiconductor substrate 51 as explained with reference to Figure 12 etc., and an insulating film 401 is formed around the transfer gate 400 in the semiconductor substrate 10.

[0113] The transfer gate 400 shown in FIGS. 15A to 15E is formed in a hexagonal shape. The insulating film 401 shown in FIG. 15A is formed in an octagonal shape. If the transfer gate 400 shown in FIG. 15A represents a gate shape formed on the semiconductor substrate 51, the line L5 representing the movement direction can be set to a direction along one side of the transfer gate 400. If the transfer gate 400 shown in FIG. 15A represents a gate shape formed within the semiconductor substrate 51, the line L5 representing the movement direction can also be set to a direction along one side where the transfer gate 400 and the insulating film 401 are in contact, or a direction along the surface where the transfer gate 400 and the insulating film 401 are in contact. In either case, the side opposite to the side where the inter-pixel isolation portion 310 is located is the movement direction.

[0114] The insulating film 401 shown in B of Fig. 15 is fan-shaped. In the case of the insulating film 401 shown in B of Fig. 15, as in A of Fig. 15, the straight line L5 representing the movement direction can be set to a direction along a side (the right side in the figure) opposite to the side (the left side in the figure) on which the inter-pixel isolation portion 310 of the transfer gate 400 is located, and the line can be set to a direction along a side (a plane including this side) where the transfer gate 400 and the insulating film 401 are in contact.

[0115] The shape of the insulating film 401 may be a shape in which a portion of a circular arc of a sector is missing, as shown in Fig. 15C, or may be an octagonal shape, as shown in Fig. 15D, which is larger than the insulating film 401 shown in Fig. 15A and is elongated in the diagonal direction in the figure. In such a case, as in Fig. 15A, the straight line L5 representing the movement direction can be set to a direction along one side of the transfer gate 400 (a plane including this side), and this line can be set to a direction along one side where the transfer gate 400 and the insulating film 401 are in contact.

[0116] The insulating film 401 may have a circular shape as shown in Fig. 15D. In this case, as in Fig. 15A, the straight line L5 representing the movement direction may be set to a direction along one side (plane) of the transfer gate 400. Furthermore, the straight line L5 may be set to a direction along one side where the transfer gate 400 and the insulating film 401 are in contact.

[0117] In this way, regardless of the shape of the insulating film 401, one side of the transfer gate 400 or one side where the transfer gate 400 and the insulating film 401 are in contact can be defined as the movement direction. This movement direction is a direction including the part with the highest potential among the parts whose potential is modulated by the transfer transistor including the transfer gate 400.

[0118] As described with reference to Fig. 14, this movement direction is a direction that intersects with the FD 251 that accumulates the charge. That is, an extension of the movement direction of the charge, for example, the straight line L5 shown in Fig. 14, is in a positional relationship where it intersects with the FD 251a that accumulates the charge. The angle of intersection is approximately right angles.

[0119] Although the transfer gate 400 described with reference to FIG. 15 has been described as having a hexagonal shape, other shapes may be used. Also, a configuration may be adopted in which the insulating film 401 formed around the transfer gate 400 in the semiconductor substrate 50 is not formed. The shape and transfer direction of the transfer gate 400 without the insulating film 401 will be described with reference to FIG. 16. The configuration in which the insulating film 401 is not formed can be appropriately applied to the embodiments described above and below.

[0120] The portion of the transfer gate 400 shown in A of Fig. 16 that is located within the semiconductor substrate 51 has a fan-like shape in plan view. In the case of the transfer gate 400 shown in A of Fig. 16, the direction of charge movement can be defined by the arc portion of the fan shape. This movement direction is the direction in which the potential becomes highest in the portion whose potential is modulated by the transfer transistor including the transfer gate 400.

[0121] The portion of the transfer gate 400 shown in Fig. 16B that is located within the semiconductor substrate 51 is shaped so that a portion of a sectorial arc is missing in plan view. In the case of the transfer gate 400 shown in Fig. 16B, the direction of charge movement can be defined as the direction connecting both ends of the recessed portion that is shaped like a missing arc. This movement direction is the direction in which the potential becomes highest in the portion whose potential is modulated by the transfer transistor that includes the transfer gate 400.

[0122] The portion of the transfer gate 400 shown in FIG. 16C that is located within the semiconductor substrate 51 has an octagonal shape in plan view, with the diagonal length in the figure being longer. In the case of the transfer gate 400 shown in FIG. 16C, the direction of charge movement can be defined as the direction in which one side of the octagon is located. In the example shown in FIG. 16C, the direction along one of the longest sides of the octagon is defined as the movement direction. This movement direction is the direction in which the potential becomes highest in the portion whose potential is modulated by the transfer transistor including the transfer gate 400.

[0123] The portion of the transfer gate 400 shown in Fig. 16D that is located within the semiconductor substrate 51 is formed in a circular shape in a plan view. In the case of the transfer gate 400 shown in Fig. 16D, the tangent to the circle can be defined as the direction of charge movement. Of the portion whose potential is modulated by the transfer transistor including the transfer gate 400, the tangent to the circle in the direction in which the potential becomes highest can be defined as the movement direction.

[0124] As described with reference to Fig. 14, this movement direction is a direction that intersects with the FD 251 that accumulates the charge. That is, an extension of the movement direction of the charge, for example, the straight line L5 shown in Fig. 14, is in a positional relationship where it intersects with the FD 251a that accumulates the charge. The angle of intersection is approximately right angles.

[0125] In the following explanation of each embodiment, we will continue to use the line L1 connecting the transfer gates as an example, as explained with reference to Figure 13, but the relationship with the lines L5 and L6, which represent the direction in which the charges move (the transfer direction in which the charges are transferred), also holds true in each embodiment described below.

[0126] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 1-2> Fig. 17 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 1-2. In the plane configuration example shown in Fig. 17, parts that are the same as those in the pixel 100 in Embodiment 1-1 shown in Fig. 9 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0127] The pixel 100 in the embodiment 1-2 shown in Figure 17 is different from the pixel 100 in the embodiment 1-1 shown in Figure 9 in that the N+ conductor portion 352 is formed larger than the N+ conductor portion 351 (Figure 9), and therefore the inclination of the transfer gate 400 is gentler, but is otherwise basically the same.

[0128] Because the region of the N+ conductor portion 361 formed in the horizontal direction in the figure is larger (longer), the length between the horizontal ends of the N+ conductor portion 361 is different from the length between the vertical ends, and the line L11 connecting the two ends has a gentler slope than the line L2 shown in Fig. 9. The angle formed by the line L11 and the inter-pixel separation portion 310 is, for example, about 30 degrees.

[0129] The transfer gates 400a-1 and 400a-2 are arranged so that the line L11 is parallel to the line L12 connecting the transfer gates 400a-1 and 400a-2. The lines L11 and L12 are parallel to each other. When the FD 261a is formed by doping through thermal diffusion from the N+ conductor portion 351, it has a triangular shape as shown in FIG. 17, and the base (end) of the triangle is at an angle of approximately 30 degrees to the inter-pixel isolation portion 310. Therefore, the lines L11, L12, and the bases of the FD 261a are parallel to each other.

[0130] By making the ends of the line L12 and the FD 261a parallel, it is possible to make the distance L13 (not shown) between the transfer gate 400a-1 and the FD 261a equal to the distance L14 (not shown) between the transfer gate 400a-2 and the FD 261a. By making the distance L13 and the distance L14 equal, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0131] 14, the transfer direction (not shown) of the transfer gate 400a-1 is in a positional relationship that is perpendicular to the line L11 of the N+ conductor portion 361 and also perpendicular to the bottom side (end) of the FD 261a. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0132] In the first and second embodiments, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0133] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 1-3> Fig. 18 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 1-3. In the plane configuration example shown in Fig. 18, parts that are the same as those of the pixel 100 in Embodiment 1-1 shown in Fig. 9 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0134] The pixel 100 according to the embodiment 1-3 shown in Fig. 18 differs from the pixel 100 according to the embodiment 1-1 shown in Fig. 9 in that the N+ conductor portion 351 (Fig. 9) is divided into an N+ conductor portion 371a and an N+ conductor portion 371b, which are provided in the sub-pixel 100a and the sub-pixel 100b, respectively. In addition, the pixel 100 according to the embodiment 1-3 shown in Fig. 18 is different from the pixel 100 according to the embodiment 1-1 shown in Fig. 9 in that the N+ conductor portion 351 (Fig. 9) is divided into an N+ conductor portion 371a and an N+ conductor portion 371b, which are provided in the sub-pixel 100a and the sub-pixel 100b, respectively. In addition, the pixel 100 according to the embodiment 1-3 is basically the same in other respects.

[0135] An N+ conductor portion 371a is provided on the upper side of the sub-pixel 100a in the drawing, and an N+ conductor portion 371b is provided on the upper side of the sub-pixel 100b in the drawing. The N+ conductor portion 371a and the N+ conductor portion 371b are each configured in a rectangular shape and are formed so as to straddle the inter-pixel separation portion 310.

[0136] A line L21 connecting the centers of two sides of the N+ conductor portion 371a on the inter-pixel separation portion 310 is parallel to the inter-pixel separation portion 310 that the N+ conductor portion 371a straddles, and the angle therebetween is approximately 0 degrees. A line L21 connecting the centers of two sides of the N+ conductor portion 371b on the inter-pixel separation portion 310 is parallel to the inter-pixel separation portion 310 that the N+ conductor portion 371b straddles, and the angle therebetween is approximately 0 degrees. A line connecting the centers of the N+ conductor portion 371a and the N+ conductor portion 371b is line L21, and line L21 is parallel to the lattice of the inter-pixel separation portion 310.

[0137] The transfer gates 400a-1 and 400a-2 are arranged so that the line L21 and the line L22 connecting the transfer gates 400a-1 and 400a-2 are parallel to each other. The transfer gates 400b-1 and 400b-2 are arranged so that the line L21 and the line L22 connecting the transfer gates 400b-1 and 400b-2 are parallel to each other. In other words, the line L22 is a line that passes through the centers of the transfer gates 400a-1, 400a-2, 400b-1, and 400b-2.

[0138] The lines L21 and L22 are parallel to each other. When the FD 271a is formed by doping through thermal diffusion from the N+ conductor portion 351, it becomes polygonal as shown in FIG. 18. FIG. 21 shows an example in which the FD 271a is formed in a rectangular shape. One side of the FD 271a contacts the N+ conductor portion 371a, and the side opposite that side (the side corresponding to the base or end) is at approximately 0 degrees with respect to the inter-pixel separation portion 310. Therefore, the lines L21, L22, and the end of the FD 271a are parallel to each other.

[0139] By making the ends of the line L22 and the FD 271a parallel, it is possible to make the distance L23 (not shown) between the transfer gate 400a-1 and the FD 271a equal to the distance L24 (not shown) between the transfer gate 400a-2 and the FD 271a. By making the distance L23 equal to the distance L24, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0140] The transfer direction (not shown) of the transfer gate 400a-1 is in a positional relationship that is perpendicular to the line L21 of the N+ conductor portion 371a and also perpendicular to the bottom side (end) of the FD 271a, as in the case described with reference to Figure 14. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0141] In the first to third embodiments, the pixel 100 is configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0142] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 2-1> Fig. 19 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 2-1. Fig. 20 is a diagram showing a cross-sectional configuration example of the pixel 100 taken along line A-A' in Fig. 19. In the plan configuration example shown in Fig. 19 and the cross-sectional configuration example shown in Fig. 20, parts that are the same as those of the pixel 100 in Embodiment 1-1 shown in Figs. 9 and 12 are designated by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0143] The pixel 100 in the embodiment 2-1 shown in FIG. 19 is basically the same as the pixel 100 in the embodiment 1-1 shown in FIG. 9 except for the shape of the transfer gate 410 and the shape of the insulating film 411 formed around the transfer gate 410.

[0144] In the cross-sectional view shown in FIG. 20, the transfer gate 410a-1 in the second embodiment is composed of a rectangular electrode that reaches a part of the inside of the photodiode 300a and a vertical electrode formed in the vertical direction. The transfer gate 410a-1 is formed to have a larger bottom area than the transfer gate 400a-1 shown in FIG. 12, for example. The transfer gate 410a-1 is entirely formed within the semiconductor substrate 51. The transfer gate 410a-1 is connected to a wiring 357 to which a drive signal is supplied.

[0145] An insulating film 411a-1 is formed on the side surface of the vertical electrode portion of the transfer gate 410a-1, in other words, on the upper side surface of the transfer gate 410a-1, so as to cover the side surface.

[0146] The transfer gates 410a-2, 410b-1, and 410b-2 each have the same configuration as the transfer gate 410a-1. The insulating films 411a-2, 411b-1, and 411b-2 each have the same configuration as the insulating film 411a-1.

[0147] With this configuration, even if the position of the end of FD251a changes slightly due to, for example, variations in the processed shape, misalignment during pattern formation of the FD251a layer and the oxide region 323 layer, or changes in the thermal process, it is possible to stably prevent FD251a and the transfer gate 410a from coming close to each other, thereby suppressing the generation of a high electric field near the transfer gate 410a.

[0148] 19, in a plan view, the parallel arrangement direction of the transfer gates 410a-1 and 410a-2 is inclined obliquely with respect to the lattice of the inter-pixel isolation portion 310. If the line connecting the center of the transfer gate 410a-1 and the center of the transfer gate 410a-2 is taken as line L1, then line L1 is inclined obliquely with respect to the inter-pixel isolation portion 310. The angle formed by line L1 and the inter-pixel isolation portion 310 is, for example, approximately 45 degrees.

[0149] The N+ conductor portion 351, which is in contact with the FD 251a and located above the inter-pixel separation portion 310, is formed in a cross shape with two orthogonal crosses. The length between the horizontal and vertical ends of this cross-shaped N+ conductor portion 31 is approximately equal, and the line connecting the two ends forms an angle of approximately 45 degrees. If the center of the horizontal end of the cross-shaped N+ conductor portion 31 is taken as center P3, the center of the vertical end is taken as center P4, and the line connecting center P3 and center P4 is taken as line L2, then line L2 forms an angle of approximately 45 degrees with respect to the inter-pixel separation portion 310.

[0150] The lines L1 and L2 are parallel to each other. The FD 251a is formed, for example, by doping using thermal diffusion from the N+ conductor portion 351, and is formed in a triangular shape as shown in FIG. 19. The base (end) of the triangle of the FD 251a is at an angle of approximately 45 degrees to the inter-pixel separation portion 310. Therefore, the lines L1, L2, and the ends of the FD 251a are parallel to each other.

[0151] By making the ends of the line L1 and the FD 251a parallel, it is possible to make the distance L3 (not shown) between the transfer gate 410a-1 and the FD 251a equal to the distance L4 (not shown) between the transfer gate 410a-2 and the FD 251a. By making the distance L3 equal to the distance L4, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0152] 14, the transfer direction (not shown) of the transfer gate 400a-1 is in a positional relationship that is perpendicular to the line L1 of the N+ conductor portion 351 and also perpendicular to the bottom side (end) of the FD 251a. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0153] In the second embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer failures. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer failures, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0154] <Example of Planar Configuration and Example of Cross-Sectional Configuration of Pixel in Embodiment 2-2> Fig. 21 is a diagram showing an example of a planar configuration of a pixel 100 in Embodiment 2-2. In the example of the planar configuration shown in Fig. 21, parts that are the same as those of the pixel 100 in Embodiment 2-1 shown in Fig. 19 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0155] The pixel 100 in the embodiment 2-2 shown in Figure 21 is different from the pixel 100 in the embodiment 2-1 shown in Figure 19 in that the N+ conductor portion 352 is formed larger than the N+ conductor portion 351 (Figure 19), and therefore the inclination of the transfer gate 410 is gentler, but is otherwise basically the same.

[0156] Because the region of the N+ conductor portion 361 formed in the horizontal direction in the figure is larger (longer), the length between the horizontal ends of the N+ conductor portion 361 is different from the length between the vertical ends, and the line L11 connecting the two ends has a gentler slope than the line L2 shown in Fig. 19. The angle formed by the line L11 and the inter-pixel separation portion 310 is, for example, about 30 degrees.

[0157] The transfer gates 410a-1 and 410a-2 are arranged so that the line L11 of the N+ conductor portion 361 and the line L12 connecting the transfer gates 410a-1 and 410a-2 are parallel to each other. The lines L11 and L12 are parallel to each other. The FD 261a is formed, for example, by doping through thermal diffusion from the N+ conductor portion 351, and is formed in a triangular shape as shown in FIG. 21. The base (end) of the triangle of the FD 261a is at an angle of approximately 30 degrees to the inter-pixel isolation portion 310. Therefore, the lines L11, L12, and the bases of the FD 261a are parallel to each other.

[0158] By making the ends of the line L12 and the FD 261a parallel, it is possible to make the distance L13 (not shown) between the transfer gate 410a-1 and the FD 261a equal to the distance L14 (not shown) between the transfer gate 410a-2 and the FD 261a. By making the distance L13 equal to the distance L14, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0159] 14, the transfer direction (not shown) of the transfer gate 400a-1 is in a positional relationship that is perpendicular to the line L11 of the N+ conductor portion 361 and also perpendicular to the bottom side (end) of the FD 261a. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0160] In the second embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0161] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 2-3> Fig. 22 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 2-3. In the plane configuration example shown in Fig. 22, parts that are the same as those of the pixel 100 in Embodiment 2-1 shown in Fig. 19 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0162] The pixel 100 in the embodiment 2-3 shown in Figure 22 differs from the pixel 100 in the embodiment 2-1 shown in Figure 19 in that the N+ conductor portion 351 (Figure 19) is divided into an N+ conductor portion 371a and an N+ conductor portion 371b, which are provided in the sub-pixel 100a and the sub-pixel 100b, respectively, and accordingly the inclination of the transfer gate 410 is 0 degrees, but other points are basically the same.

[0163] An N+ conductor portion 371a is provided on the upper side of the sub-pixel 100a in the drawing, and an N+ conductor portion 371b is provided on the upper side of the sub-pixel 100b in the drawing. The N+ conductor portion 371a and the N+ conductor portion 371b are each configured in a rectangular shape and are formed so as to straddle the inter-pixel separation portion 310.

[0164] A line L21 connecting the centers of the N+ conductor portion 371a and the N+ conductor portion 371b is parallel to the inter-pixel isolation portion 310, and the angle therebetween is approximately 0 degrees. The line L21 is parallel to the lattice of the inter-pixel isolation portion 310.

[0165] The transfer gates 410a-1 and 410a-2 are arranged so that a line L21 passing through the N+ conductor portions 371a and 371b is parallel to a line L22 connecting the transfer gates 410a-1 and 410a-2. The transfer gates 410b-1 and 410b-2 are arranged so that the line L21 is parallel to a line L22 connecting the transfer gates 410b-1 and 410b-2. The line L22 passes through the centers of the transfer gates 410a-1, 410a-2, 410b-1, and 410b-2.

[0166] The lines L21 and L22 are parallel to each other. The FD 271a is formed, for example, by doping using thermal diffusion from the N+ conductor portion 351, and is formed in a rectangular shape as shown in FIG. 22. One side of the FD 271a is in contact with the N+ conductor portion 371a, and the side opposite that side (referred to as the end) is at an angle of approximately 0 degrees with respect to the inter-pixel separation portion 310. Therefore, the lines L21, L22, and the end of the FD 271a are parallel to each other.

[0167] By making the line L22 passing through the transfer gates 410a-1 and 410a-2 parallel to the end of the FD 271a, it is possible to make the distance L23 (not shown) between the transfer gate 410a-1 and the FD 271a equal to the distance L24 (not shown) between the transfer gate 410a-2 and the FD 271a. Making the distance L23 equal to the distance L24 improves transfer efficiency and suppresses the occurrence of white spots and the like.

[0168] 14, the transfer direction (not shown) of the transfer gate 410 is in a positional relationship that is perpendicular to the line L21 of the N+ conductor portion 371 and also perpendicular to the bottom side (end) of the FD 271a. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0169] In the second and third embodiments, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0170] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 3-1> Fig. 23 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 3-1. Fig. 24 is a diagram showing a cross-sectional configuration example of the pixel 100 taken along line A-A' in Fig. 23. In the planar configuration example shown in Fig. 23 and the cross-sectional configuration example shown in Fig. 24, parts that are the same as those of the pixel 100 in Embodiment 1-1 shown in Figs. 9 and 12 are designated by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0171] The pixel 100 in the embodiment 3-1 shown in Figure 23 is different from the pixel 100 in the embodiment 1-1 shown in Figure 9 in that the N+ conductor portion 351, the P+ conductor portion 352, and the P+ conductor portion 353 have been removed, but is otherwise basically the same.

[0172] 23, the N+ conductor portion 351, the P+ conductor portion 352, and the P+ conductor portion 353 are not formed in the intersecting region of the inter-pixel isolation portion 310. The N+ regions of the FDs 251a and 251b and the P+ regions 252a and 251b for supplying the reference potential are formed by, for example, ion implantation.

[0173] In the pixel 100 in the cross-sectional configuration example shown in Fig. 24, the N+ conductor portion 351 provided in the inter-pixel isolation portion 310 in the embodiment 1-1 shown in Fig. 12 is absent, and an oxide region 323 is formed in that region. Similarly, in the pixel 100 in the cross-sectional configuration example shown in Fig. 24, the P+ conductor portion 352 provided in the inter-pixel isolation portion 310 in the embodiment 1-1 shown in Fig. 12 is absent, and an oxide region 323 is formed in that region. The wiring 355 is connected to the FD 251a, and the wiring 356 is connected to the P+ region 252a.

[0174] 23, the parallel arrangement direction of the transfer gates 400a-1 and 400a-2 is inclined obliquely with respect to the lattice of the inter-pixel isolation portion 310. If the line connecting the center of the transfer gate 400a-1 and the center of the transfer gate 400a-2 is taken as line L1, then line L1 is inclined obliquely with respect to the inter-pixel isolation portion 310. The angle formed by line L1 and the inter-pixel isolation portion 310 is, for example, approximately 45 degrees.

[0175] 23, the FD 251a is formed in a triangular shape at the upper right corner of the sub-pixel 100a. If the base (end) of the triangle is line L31, the angle between line L31 and the inter-pixel isolation portion 310 is approximately 45 degrees. The line L1 of the transfer gate 400 and the line L31 of the FD 251 are parallel to each other.

[0176] By making the line L1 and the line L31 parallel, it is possible to make the distance L3 (not shown) between the transfer gate 400a-1 and the FD 251a equal to the distance L4 (not shown) between the transfer gate 400a-2 and the FD 251a. By making the distance L3 equal to the distance L4, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0177] 14, the transfer direction (not shown) of the transfer gate 400 is positioned perpendicular to the bottom side (end) of the FD 251. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0178] In the third embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0179] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 3-2> Fig. 25 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 3-2. In the plane configuration example shown in Fig. 25, parts that are the same as those of the pixel 100 in Embodiment 3-1 shown in Fig. 23 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0180] The pixel 100 in the embodiment 3-2 shown in FIG. 25 is basically the same as the pixel 100 in the embodiment 3-1 shown in FIG. 23 except that the FD 261 is formed to be larger than the FD 251 (FIG. 23), has a polygonal shape, and the transfer gate 410 has a gentler slope.

[0181] If the line passing through the side of the FD 261a on the transfer gate 400a side, in other words, the line passing through the longest side of the sides forming the FD 261a, is taken as line L41, the inclination of line L41 is gentler than the inclination of line L31 passing through the FD 251a shown in Fig. 23. The angle formed between line L41 and the inter-pixel isolation portion 310 is, for example, about 30 degrees.

[0182] The transfer gates 400a-1 and 400a-2 are arranged so that the line L41 is parallel to a line L12 connecting the centers of the transfer gates 400a-1 and 400a-2. The lines L41 and L12 are parallel to each other. By making the lines L12 and L41 (ends of the FD 261a) parallel to each other, the distance L13 (not shown) between the transfer gates 400a-1 and FD 261a and the distance L14 (not shown) between the transfer gates 400a-2 and FD 261a can be made equal. By making the distances L13 and L14 equal, the transfer efficiency can be improved and the occurrence of white spots and the like can be suppressed.

[0183] 14, the transfer direction (not shown) of the transfer gate 400 is positioned perpendicular to the bottom side (end) of the FD 261. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0184] In the third embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0185] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 3-3> Fig. 26 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 3-3. In the plane configuration example shown in Fig. 26, parts that are the same as those of the pixel 100 in Embodiment 3-1 shown in Fig. 23 are assigned the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0186] The pixel 100 in the embodiment 3-2 shown in FIG. 26 is basically the same as the pixel 100 in the embodiment 3-1 shown in FIG. 23 except that the FD271 is formed larger than the FD251 (FIG. 23), has a polygonal shape, and the inclination of the transfer gate 400 is approximately 0 degrees.

[0187] If the line passing through the side of the FD 271a on the transfer gate 400a side, in other words, the line passing through the longest side of the sides forming the FD 271a, is taken as line L51, the inclination of line L51 is gentler than the inclination of line L31 shown in Fig. 23. The angle formed by line L51 and the inter-pixel isolation portion 310 is, for example, about 0 degrees, that is, line L51 and inter-pixel isolation portion 310 are in a positional relationship in which they are parallel.

[0188] The transfer gates 400a-1 and 400a-2 are arranged so that the line L51 and the line L22 connecting the transfer gates 400a-1 and 400a-2 are parallel to each other. The transfer gates 400b-1 and 400b-2 are arranged so that the line L51 and the line L22 connecting the transfer gates 400b-1 and 400b-2 are parallel to each other. In other words, the line L22 passes through the centers of the transfer gates 400a-1, 400a-2, 400b-1, and 400b-2, and the transfer gates 400 are arranged so that the line L22 is parallel to the line L51.

[0189] By making the line L22 and the end (line L51) of the FD 271a parallel to each other, it is possible to make the distance L23 (not shown) between the transfer gate 400a-1 and the FD 271a equal to the distance L24 (not shown) between the transfer gate 400a-2 and the FD 271a. By making the distance L23 and the distance L24 equal to each other, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0190] 14, the transfer direction (not shown) of the transfer gate 400 is positioned perpendicular to the bottom side (end) of the FD 271. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0191] In the third embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0192] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 4-1> Fig. 27 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 4-1. Fig. 28 is a diagram showing a cross-sectional configuration example of the pixel 100 taken along line A-A' in Fig. 27. In the planar configuration example shown in Fig. 27 and the cross-sectional configuration example shown in Fig. 28, parts that are the same as those of the pixel 100 in Embodiment 3-1 shown in Figs. 23 and 24 are designated by the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0193] The pixel 100 in the embodiment 4-1 shown in FIG. 27 is basically the same as the pixel 100 in the embodiment 3-1 shown in FIG. 23 except for the shape of the transfer gate 410 and the shape of the insulating film 411 formed around the transfer gate 410.

[0194] 28, the transfer gate 410a-1 in the embodiment 4-1 has a rectangular electrode that reaches a part of the inside of the photodiode 300a, and a vertical electrode formed in the vertical direction is connected to the rectangular electrode. The bottom of the transfer gate 410a-1 is formed larger than the top.

[0195] The insulating film 411a-1 is formed so as to cover the side surface of the vertical electrode portion of the transfer gate 410a-1, in other words, the upper side surface of the transfer gate 410a-1.

[0196] The transfer gates 410a-2, 410b-1, and 410b-2 each have the same configuration as the transfer gate 410a-1. The insulating films 411a-2, 411b-1, and 411b-2 each have the same configuration as the insulating film 411a-1.

[0197] With this configuration, even if the position of the end of FD251a changes slightly due to, for example, variations in the processed shape, misalignment during pattern formation of the FD251a layer and the oxide region 323 layer, changes in the thermal process, etc., it is possible to stably prevent FD251a and the transfer gate 410a from coming close to each other, and it is possible to suppress the generation of a high electric field near the transfer gate 410a.

[0198] 27, in a plan view, the parallel arrangement direction of the transfer gates 410a-1 and 410a-2 is inclined obliquely with respect to the lattice of the inter-pixel isolation portion 310. If the line connecting the center of the transfer gate 410a-1 and the center of the transfer gate 410a-2 is taken as line L1, then line L1 is inclined obliquely with respect to the inter-pixel isolation portion 310. The angle formed by line L1 and the inter-pixel isolation portion 310 is, for example, approximately 45 degrees.

[0199] 27, the FD 251a is formed in a triangular shape at the upper right corner of the sub-pixel 100a. If the base (end) of the triangle is line L31, the angle between line L31 and the inter-pixel separation portion 310 is approximately 45 degrees. Therefore, line L1 and line L31 are in a parallel positional relationship.

[0200] By making the line L1 and the line L31 parallel, it is possible to make the distance L3 (not shown) between the transfer gate 410a-1 and the FD 251a equal to the distance L4 (not shown) between the transfer gate 410a-2 and the FD 251a. By making the distance L3 equal to the distance L4, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0201] 14, the transfer direction (not shown) of the transfer gate 410 is in a positional relationship that is perpendicular to the bottom side (end) of the FD 251. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0202] In the embodiment 4-1, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. Furthermore, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0203] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 4-2> Fig. 29 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 4-2. In the plane configuration example shown in Fig. 29, parts that are the same as those of the pixel 100 in Embodiment 4-1 shown in Fig. 27 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0204] The pixel 100 in the embodiment 4-2 shown in FIG. 29 is basically the same as the pixel 100 in the embodiment 4-1 shown in FIG. 27 except that the FD 261 is formed to be larger than the FD 251 (FIG. 27), has a polygonal shape, and the transfer gate 410 has a gentler slope.

[0205] If the line passing through the side of the FD 261a on the transfer gate 410a side, in other words, the line passing through the longest side of the sides forming the FD 261a, is taken as line L41, the inclination of line L41 is gentler than the inclination of line L31 shown in Fig. 27. The angle formed between line L41 and the inter-pixel isolation portion 310 is, for example, about 30 degrees.

[0206] The transfer gates 410a-1 and 410a-2 are arranged so that this line L41 is parallel to the line L12 connecting the transfer gates 410a-1 and 410a-2. The lines L41 and L12 are parallel to each other. By making the line L12 of the transfer gate 410 parallel to the line L41 at the end of the FD 261a, it is possible to make the distance L13 (not shown) between the transfer gate 410a-1 and the FD 261a equal to the distance L14 (not shown) between the transfer gate 410a-2 and the FD 261a. By making the distance L13 equal to the distance L14, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0207] 14, the transfer direction (not shown) of the transfer gate 410 is in a positional relationship that is perpendicular to the bottom side (end) of the FD 261. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0208] In the embodiment 4-2, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0209] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 4-3> Fig. 30 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 4-3. In the plane configuration example shown in Fig. 30, parts that are the same as those of the pixel 100 in Embodiment 4-1 shown in Fig. 27 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0210] The pixel 100 in the embodiment 3-2 shown in FIG. 30 is basically the same as the pixel 100 in the embodiment 3-1 shown in FIG. 27 except that the FD271 is formed larger than the FD251 (FIG. 27), has a polygonal shape, and the inclination of the transfer gate 410 is approximately 0 degrees.

[0211] If the line passing through the side of the FD 271a on the transfer gate 410a side, in other words, the line passing through the longest side of the sides forming the FD 271a, is taken as line L51, the inclination of line L51 is gentler than the inclination of line L31 shown in Fig. 27. The angle formed by line L51 and the inter-pixel isolation portion 310 is, for example, about 0 degrees, that is, line L51 and inter-pixel isolation portion 310 are in a positional relationship in which they are parallel.

[0212] The transfer gates 410a-1 and 410a-2 are arranged so that the line L51 and the line L22 connecting the transfer gates 410a-1 and 410a-2 are parallel to each other. The transfer gates 410b-1 and 410b-2 are arranged so that the line L51 and the line L22 connecting the transfer gates 410b-1 and 410b-2 are parallel to each other. In other words, the line L22 is a line that passes through the centers of the transfer gates 410a-1, 410a-2, 410b-1, and 410b-2, and the line L22 is parallel to the line L51.

[0213] By making the line L22 passing through the transfer gates 410a-1 and 410a-2 parallel to the end (line L51) of the FD 271a, it is possible to make the distance L23 (not shown) between the transfer gate 410a-1 and the FD 271a equal to the distance L24 (not shown) between the transfer gate 410a-2 and the FD 271a. Making the distance L23 equal to the distance L24 improves transfer efficiency and suppresses the occurrence of white spots and the like.

[0214] 14, the transfer direction (not shown) of the transfer gate 410 is in a positional relationship that is perpendicular to the bottom side (end) of the FD 271. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0215] In the embodiment 4-3, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. Furthermore, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0216] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 5-1> Fig. 31 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 5-1. Fig. 32 is a diagram showing a cross-sectional configuration example of the pixel 100 taken along line A-A' in Fig. 31. In the planar configuration example shown in Fig. 31 and the cross-sectional configuration example shown in Fig. 32, parts that are the same as those of the pixel 100 in Embodiment 1-1 shown in Figs. 9 and 12 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0217] The pixel 100 in the 5-1 embodiment is basically the same as the pixel 100 in the 1-1 embodiment, except that an N-type layer 501 and a P-type layer 502 are added, and the end of the N-type layer 501 is formed parallel to the line L1 and the line L2.

[0218] Referring to the cross-sectional configuration example of the pixel 100 shown in FIG. 32, an N-type layer 501 doped with N-type impurities is provided on the upper side of the photodiode 300a in the figure, between the transfer gate 400a-1 and the P+ region 252a, and a P-type layer 502 doped with P-type impurities is provided above the N-type layer 501.

[0219] The N-type layer 501 functions as a signal storage layer, and is formed so that a portion of it is in contact with the vertical electrode of the transfer gate 400a-1. The P-type layer 502 functions as a layer that suppresses the generation of dark current, and is formed so that it does not come into contact with the transfer gate 400a-1.

[0220] 31 shows the area where the N-type layer 501 is located and the area where the P-type layer 502 is located when viewed from the front surface 11b. The N-type layer 501 is formed so that it has areas that partially overlap with the transfer gates 400a-1 and 400a-2. The P-type layer 502 is formed so that it does not have areas that overlap with the transfer gates 400a-1 and 400a-2, and so that it does not have areas that overlap with the insulating films 401a-1 and 401a-2.

[0221] The depletion potential of the N-type layer 501 is set to be the same as or slightly higher than the depletion potential of the N-type layer that constitutes the photodiode 300a.

[0222] It is also possible to adopt a configuration in which the P-type layer 502 is not provided.

[0223] 31 , in a plan view, the parallel arrangement direction of the transfer gates 400a-1 and 400a-2 is inclined obliquely with respect to the lattice of the inter-pixel isolation portion 310. If the line connecting the center of the transfer gate 400a-1 and the center of the transfer gate 400a-2 is taken as line L1, then line L1 is inclined obliquely with respect to the inter-pixel isolation portion 310. The angle formed by line L1 and the inter-pixel isolation portion 310 is, for example, approximately 45 degrees.

[0224] If the line connecting the center of the horizontal end of the cross-shaped N+ conductor portion 31 and the center of the vertical end is defined as line L2, line L2 forms an angle of approximately 45 degrees with respect to the inter-pixel isolation portion 310. Lines L1 and L2 are parallel to each other. FD 251a is formed in a triangular shape, and the base (end) of the triangle forms an angle of approximately 45 degrees with respect to the inter-pixel isolation portion 310. Therefore, lines L1, L2, and the bases of FD 251a are parallel to each other.

[0225] By making the line L1 passing through the transfer gate 400a parallel to the end of the FD 251a, it is possible to make the distance L3 (not shown) between the transfer gate 410a-1 and the FD 251a equal to the distance L4 (not shown) between the transfer gate 410a-2 and the FD 251a. By making the distance L3 equal to the distance L4, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0226] 14, the transfer direction (not shown) of the transfer gate 400 is in a positional relationship that is perpendicular to the line L2 of the N+ conductor portion 351 and also perpendicular to the bottom side (end) of the FD 251a. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0227] In the fifth embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer failures. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer failures, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0228] In the fifth embodiment, by providing the N-type layer 501, the short channel effect does not deteriorate and transfer efficiency can be sufficiently ensured even if, for example, the pixel size is reduced and the vertical electrode of the transfer gate 400 becomes shallower. Therefore, the depletion potential of the signal accumulation layer can be increased, and the number of saturated electrons can be increased.

[0229] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 5-2> Fig. 33 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 5-2. In the plane configuration example shown in Fig. 33, parts that are the same as those of the pixel 100 in Embodiment 5-1 shown in Fig. 31 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0230] The pixel 100 according to the embodiment 5-2 shown in Fig. 33 is basically the same as the pixel 100 according to the embodiment 5-1 shown in Fig. 31 except that the N+ conductor portion 361 is formed larger than the N+ conductor portion 351 (Fig. 31) and accordingly the inclination of the transfer gate 400 is gentler. The end of the N-type layer 501 is formed parallel to the line L11 and the line L12.

[0231] Because the region of the N+ conductor portion 361 formed in the horizontal direction in the figure is larger (longer), the length between the horizontal ends of the N+ conductor portion 361 is different from the length between the vertical ends, and the line L11 connecting the two ends has a gentler slope than the line L2 shown in Fig. 31. The angle formed by the line L11 and the inter-pixel separation portion 310 is, for example, about 30 degrees.

[0232] The transfer gates 400a-1 and 400a-2 are arranged so that the line L11 is parallel to the line L12 connecting the transfer gates 400a-1 and 400a-2. The lines L11 and L12 are parallel to each other. When the FD 261a is formed by doping through thermal diffusion from the N+ conductor portion 351, it takes on a polygonal shape as shown in FIG. 33, with the longest side (end) of the polygon at an angle of approximately 30 degrees relative to the inter-pixel isolation portion 310. Therefore, the lines L11, L12, and the bases of the FD 261a are parallel to each other.

[0233] By making the ends of the line L12 and the FD 261a parallel, it is possible to make the distance L13 (not shown) between the transfer gate 400a-1 and the FD 261a equal to the distance L14 (not shown) between the transfer gate 400a-2 and the FD 261a. By making the distance L13 and the distance L14 equal, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0234] 14, the transfer direction (not shown) of the transfer gate 400 is in a positional relationship that is perpendicular to the line L11 of the N+ conductor portion 361 and also perpendicular to the bottom side (end) of the FD 261. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0235] As in the embodiment 5-1 (FIG. 31), the N-type layer 501 is formed so as to have a region that partially overlaps with the transfer gate 400a-1 and the transfer gate 400a-2. The P-type layer 502 is formed so as not to have a region that overlaps with the transfer gate 400a-1 and the transfer gate 400a-2, and so as not to have a region that overlaps with the insulating film 401a-1 and the insulating film 401a-2. In the embodiment 5-2, the N-type layer 501 is also provided, thereby ensuring sufficient transfer efficiency, increasing the depletion potential of the signal storage layer, and increasing the number of saturated electrons.

[0236] In the fifth embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0237] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 5-3> Fig. 34 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 5-3. In the plane configuration example shown in Fig. 34, parts that are the same as those of the pixel 100 in Embodiment 5-1 shown in Fig. 31 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0238] The pixel 100 in the embodiment 5-3 shown in Figure 34 differs from the pixel 100 in the embodiment 5-1 shown in Figure 31 in that the N+ conductor portion 351 (Figure 31) is divided into an N+ conductor portion 371a and an N+ conductor portion 371b, which are provided in the sub-pixel 100a and the sub-pixel 100b, respectively, and accordingly the inclination of the transfer gate 400 is 0 degrees, but other points are basically the same.

[0239] An N+ conductor portion 371a is provided on the upper side of the sub-pixel 100a in the drawing, and an N+ conductor portion 371b is provided on the upper side of the sub-pixel 100b in the drawing. The N+ conductor portion 371a and the N+ conductor portion 371b are each configured in a rectangular shape and are formed so as to straddle the inter-pixel separation portion 310.

[0240] The line connecting the centers of the N+ conductor portion 371a and the N+ conductor portion 371b is line L21, and line L21 is parallel to the lattice of the inter-pixel isolation portion 310. Line L21 is parallel to the inter-pixel isolation portion 310, and the angle therebetween is approximately 0 degrees.

[0241] The transfer gates 400a-1 and 400a-2 are arranged so that the line L21 and the line L22 connecting the transfer gates 400a-1 and 400a-2 are parallel to each other. The transfer gates 400b-1 and 400b-2 are arranged so that the line L21 and the line L22 connecting the transfer gates 400b-1 and 400b-2 are parallel to each other. In other words, the line L22 passes through the centers of the transfer gates 400a-1, 400a-2, 400b-1, and 400b-2, and this line L22 is parallel to the line L21 passing through the N+ conductor portion 371.

[0242] The lines L21 and L22 are parallel to each other. The FD 271a is formed, for example, by doping using thermal diffusion from the N+ conductor portion 351, and is formed in a polygonal shape as shown in FIG. 34. One side of the FD 271a is in contact with the N+ conductor portion 371a, and the side opposite that side (referred to as the end) is at an angle of approximately 0 degrees with respect to the inter-pixel separation portion 310. Therefore, the lines L21, L22, and the end of the FD 271a are parallel to each other.

[0243] By making the line L22 passing through the transfer gate 400 and the end of the FD 271a parallel, it is possible to make the distance L23 (not shown) between the transfer gate 400a-1 and the FD 271a equal to the distance L24 (not shown) between the transfer gate 400a-2 and the FD 271a. By making the distance L23 equal to the distance L24, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0244] 14, the transfer direction (not shown) of the transfer gate 400 is in a positional relationship that is perpendicular to the line L21 of the N+ conductor portion 371 and also perpendicular to the bottom side (end) of the FD 271. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0245] As in the embodiment 5-1 (FIG. 31), the N-type layer 501 is formed so as to have a region that partially overlaps with the transfer gate 400a-1 and the transfer gate 400a-2. The P-type layer 502 is formed so as not to have a region that overlaps with the transfer gate 400a-1 and the transfer gate 400a-2, and so as not to have a region that overlaps with the insulating film 401a-1 and the insulating film 401a-2. In the embodiment 5-2, the N-type layer 501 is also provided, thereby ensuring sufficient transfer efficiency, increasing the depletion potential of the signal storage layer, and increasing the number of saturated electrons.

[0246] In the fifth embodiment, the pixel 100 is also configured to be able to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. In addition, there is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0247] Here, the fifth embodiment has been described as being applied to the first embodiment as an example, but the fifth embodiment can also be applied in combination with any of the second to fourth embodiments.

[0248] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 6-1> Fig. 35 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 6-1. In the plane configuration example shown in Fig. 35, parts that are the same as those of the pixel 100 in Embodiment 5-1 shown in Fig. 31 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0249] In the first to fifth embodiments described above, one sub-pixel 100 is configured to have two transfer gates, 400-1 and 400-2, but in the sixth embodiment, one sub-pixel 100 is configured to have one transfer gate 600, which is different from the other embodiments.

[0250] The sub-pixel 100a includes a transfer gate 600a, and an insulating film 601a is provided on the side of the transfer gate 600a. The sub-pixel 100b includes a transfer gate 600b, and an insulating film 601b is provided on the side of the transfer gate 600b. The following description will continue using the sub-pixel 100a as an example.

[0251] The sub-pixel 100a is configured to include an N-type layer 501 and a P-type layer 502, similar to the embodiment 5-1. The N-type layer 501 is formed so as to have a region that partially overlaps with the transfer gate 600a. The P-type layer 502 is formed so as not to have a region that overlaps with the transfer gate 600a or the insulating film 601a.

[0252] If the line connecting the center of the horizontal end of the cross-shaped N+ conductor portion 31 and the center of the vertical end is taken as line L2, line L2 forms an angle of approximately 45 degrees with respect to the inter-pixel separation portion 310.

[0253] 35, the direction in which the charge read from the photodiode 300a by the transfer transistor is transferred to the FD 251a is represented by line L5. Line L5 is a line passing through an end of the insulating film 601a. ​​The end of the insulating film 601a is the same as that described with reference to FIG. 14, and may be, for example, the center of the side corresponding to the bottom of the insulating film 601a, a part of the side where the transfer gate 600a and the insulating film 601a meet, or a part of the side surface of the transfer gate 600a, and the line passing through such an end is line L5.

[0254] On the line L5, the side closer to the center of the photodiode 300a is designated as position P5, and the side closer to the FD 251a is designated as position P6. The position P5 side is the region corresponding to the source of the transfer transistor, and the position P6 side is the region corresponding to the drain. The charge read from the photodiode 300a is transferred from position P5 (source) of the transfer gate 600a through the transfer gate 600a to position P6 (drain) of the transfer gate 600a and supplied to the FD 251a.

[0255] Line L5 connecting position P5 and position P6 represents the transfer direction. Line L5 representing the transfer direction and line L2 connecting the centers of the ends of the N+ conductor portion 351 are orthogonal to each other. Line L2 and the base (end) of FD 251a are parallel to each other. Therefore, line L5, which is the transfer direction of the transfer gate 600a, and the end of FD 251a are orthogonal to each other.

[0256] In this way, when the transfer direction of the transfer gate 600 and the bottom side of the FD 251a are perpendicular to each other, it is possible to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer failures. There is no need to lower the depletion potential of the photodiode to avoid transfer failures, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0257] In the sixth embodiment, by providing the N-type layer 501, it is possible to ensure sufficient transfer efficiency, increase the depletion potential of the signal accumulation layer, and increase the number of saturated electrons.

[0258] <Plane Configuration Example and Cross-Sectional Configuration Example of Pixel in Embodiment 6-2> Fig. 36 is a diagram showing a plane configuration example of a pixel 100 in Embodiment 6-2. In the plane configuration example shown in Fig. 36, parts that are the same as those of the pixel 100 in Embodiment 6-1 shown in Fig. 35 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0259] In the pixel 100 of the embodiment 6-2 shown in FIG. 36, the N+ conductor portion 361 is formed larger than the N+ conductor portion 351 (FIG. 35), and accordingly the transfer direction of the transfer gate 600 is different, but other points are basically the same as the pixel 100 of the embodiment 6-1 shown in FIG.

[0260] Because the region of the N+ conductor portion 361 formed in the horizontal direction in the figure is larger (longer), the length between the horizontal ends of the N+ conductor portion 361 is different from the length between the vertical ends, and the line L11 connecting the two ends has a gentler slope than the line L2 shown in Fig. 35. The angle formed by the line L11 and the inter-pixel separation portion 310 is, for example, about 30 degrees.

[0261] The transfer gate 600 is disposed so that this line L11 and a line L7 representing the transfer direction of the transfer gate 600 are orthogonal to each other. The lines L11 and L7 are in an orthogonal positional relationship. The side (end) of the FD 261a on the transfer gate 600a side is at an angle of, for example, about 30 degrees with respect to the inter-pixel isolation portion 310. Therefore, the line L7 representing the transfer direction of the transfer gate 600a and the end of the FD 261a are in an orthogonal positional relationship.

[0262] In this way, when the transfer direction of the transfer gate 600 and the end of the FD 261a are perpendicular to each other, it is possible to achieve a configuration that can sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. There is no need to lower the depletion potential of the photodiode to avoid transfer defects, and a sufficient number of saturated electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0263] In the sixth embodiment, by providing the N-type layer 501, it is possible to ensure sufficient transfer efficiency, increase the depletion potential of the signal accumulation layer, and increase the number of saturated electrons.

[0264] The sixth embodiment is a case where the sixth embodiment is applied to the fifth embodiment, and the sixth embodiment is a case where the sixth embodiment is applied to the fifth embodiment. Although not shown here, the sixth embodiment can also be configured to be applied to the fifth embodiment. The sixth embodiment can also be applied in combination with any of the first to fourth embodiments. That is, although the first to fifth embodiments have shown configurations having two transfer gates 400, the present technology can also be applied to cases where each of the first to fifth embodiments has a configuration having one transfer gate.

[0265] <Example of Planar Configuration and Example of Cross-Sectional Configuration of Pixel in Seventh Embodiment> Fig. 37 is a diagram showing an example of a planar configuration of a pixel 100 in the seventh embodiment. Fig. 38 is a diagram showing an example of a cross-sectional configuration of the pixel 100 taken along line A-A' in Fig. 37.

[0266] The pixel 100 in the first to sixth embodiments has been described as an example of a pixel included in the photodetector 1 having a stacked structure, which has been described with reference to Fig. 2. The description does not indicate that the present technology can be applied only to the photodetector 1 having a stacked structure, but can also be applied to a configuration in which a transistor is disposed on the surface 11b of the semiconductor substrate 51 on which the pixel 100 is formed, as will be described as the seventh embodiment.

[0267] The pixel 100 according to the seventh embodiment shown in Figures 37 and 38 shows a configuration in which the seventh embodiment is applied to the pixel 100 according to the embodiment 3-1 shown in Figure 23. The pixel 100 according to the seventh embodiment shown in Figures 37 and 38 has a configuration in which the N+ conductor portion 351, the P+ conductor portion 352, and the P+ conductor portion 353 are not formed in the inter-pixel isolation portion 310.

[0268] An FD 251a, a transfer gate 400a-1, and a transfer gate 400a-2 are formed in the upper part of the sub-pixel 100a in the drawing. A gate electrode 701a of a transistor is formed in the lower part of the sub-pixel 100a in the drawing, and an N+ region 702a serving as a source or drain and an N+ region 703a serving as a drain or source are formed in the semiconductor substrate 51. The transistors can be transistors for the readout circuit unit 62 (FIG. 2).

[0269] STI (Shallow Trench Isolation) 705 is provided in the slit 312 between the subpixels 100a and 100b, and between the transistor 701a and the active region in which the transfer gate 400a is formed. In the cross-sectional configuration example of Figure 38, the STI 705 is formed on the right side of the transfer gate 400a-1 in the figure. An N+ region 702a that constitutes the transistor is formed on the right side of the STI 705 in the figure.

[0270] A gate electrode 701a of the transistor is formed on the surface 11b of the semiconductor substrate 51, to the right of the N+ region 702a in the drawing. An N+ region 703b that constitutes the transistor is formed in the semiconductor substrate 51, to the right of the gate electrode 701a in the drawing.

[0271] If the line passing through the side of FD261a on the transfer gate 400a side, in other words, the line passing through the longest side of the sides forming FD261a, is taken as line L41, the angle formed by line L41 and the inter-pixel separation section 310 is, for example, approximately 30 degrees.

[0272] The transfer gates 400a-1 and 400a-2 are arranged so that the line L41 is parallel to the line L12 connecting the transfer gates 400a-1 and 400a-2. The lines L11 and L12 are parallel to each other. By making the line L12 passing through the transfer gate 400 parallel to the line L41 passing through the end of the FD 261a, it is possible to make the distance L13 (not shown) between the transfer gate 410a-1 and the FD 261a equal to the distance L14 (not shown) between the transfer gate 410a-2 and the FD 261a. By making the distance L13 equal to the distance L14, it is possible to improve transfer efficiency and suppress the occurrence of white spots and the like.

[0273] 14, the transfer direction (not shown) of the transfer gate 400 is positioned perpendicular to the bottom side (end) of the FD 251. Therefore, the transfer path can be made the shortest, and transfer efficiency can be improved.

[0274] Even in the seventh embodiment, that is, even if the transistor is disposed on the semiconductor substrate 51, the pixel 100 can be configured to be capable of sufficiently avoiding both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects. Furthermore, there is no need to lower the depletion potential of the photodiode in order to avoid transfer defects, and a sufficient number of saturation electrons can be obtained, making it possible to obtain a low-noise image in the reproduced image and an image with a wide dynamic range.

[0275] The seventh embodiment can be applied in combination with any of the first to sixth embodiments.

[0276] <Plane Configuration Example of Pixel in Eighth Embodiment> The first to seventh embodiments have been described using an example in which the pixel 100 has a structure including two photodiodes (photoelectric conversion units) within one pixel. The present technology can also be applied to pixels 100 other than those including two photodiodes within one pixel, and can also be applied to, for example, the photodetector 1 having the circuit configuration shown in Fig. 3. Fig. 39 is a diagram showing an example of the planar configuration of the photodetector 1 corresponding to the circuit configuration shown in Fig. 3.

[0277] The photodetector 1 shown in Fig. 3 has a configuration in which four pixels 100 share the FD and below. In the planar configuration example of the photodetector 1 shown in Fig. 39, pixel 100-1 is located in the upper left of the figure, pixel 100-2 is located in the upper right of the figure, pixel 100-3 is located in the lower left of the figure, and pixel 100-4 is located in the lower right of the figure. An N+ conductor portion 351 is formed in the center of pixels 100-1 to 100-4.

[0278] A P+ conductor 352-1 is formed on the upper left side of pixel 100-1, and a P+ region 252-1 is formed by doping from the P+ conductor 352-1 through thermal diffusion. A P+ conductor 352-2 is formed on the upper right side of pixel 100-2, and a P+ region 252-2 is formed by doping from the P+ conductor 352-2 through thermal diffusion. A P+ conductor 352-3 is formed on the lower left side of pixel 100-3, and a P+ region 252-3 is formed by doping from the P+ conductor 352-3 through thermal diffusion. A P+ conductor 352-4 is formed on the lower right side of pixel 100-2, and a P+ region 252-4 is formed by doping from the P+ conductor 352-4 through thermal diffusion.

[0279] Within each pixel 100, FDs 251-1 to 251-4 are formed adjacent to the N+ conductor portion 351. The FDs 251-1 to 251-4 are formed by doping through thermal diffusion from the N+ conductor portion 351 when the N+ conductor portion 351 is formed. Because the FDs 251-1 to 251-4 are connected to the N+ conductor portion 351, they can function as a single FD 251, and a configuration can be adopted in which the FDs are shared by four pixels 100.

[0280] Since the pixels 100-1 to 100-4 each have the same configuration, the following description will be given taking pixel 100-1 as an example. Pixel 100-1 is provided with a transfer gate 400-1 and a transfer gate 400-2, with an insulating film 401-1 provided on the vertical electrode portion (not shown) of transfer gate 400-1, and an insulating film 401-2 provided on the vertical electrode portion (not shown) of transfer gate 400-2.

[0281] The ends of the N+ conductor portion 351, the transfer gates 400-1 and 400-2, and the FD 251-1 have the positional relationship described with reference to Figures 13 and 14. Therefore, similar to the above-described embodiment, this configuration can sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects, can obtain a sufficient number of saturated electrons, can obtain a low-noise image on the reproduced image, and can obtain an image with a high dynamic range.

[0282] As shown in Fig. 40, a configuration may also be adopted in which a transistor 711 is formed on the surface 11b of a semiconductor substrate 51. Although the seventh embodiment in which a transistor is formed on the surface 11b of a semiconductor substrate 51 has been described with reference to Figs. 37 and 38, the seventh embodiment may also be implemented in combination with the eighth embodiment.

[0283] In the example shown in FIG. 40, a transistor 711-1 is formed in the pixel 100-1, a transistor 711-2 is formed in the pixel 100-2, a transistor 711-3 is formed in the pixel 100-3, and a transistor 711-4 is formed in the pixel 100-4.

[0284] 40, the ends of the N+ conductor portion 351, transfer gates 400-1 and 400-2, and FD 251-1 have the positional relationship described with reference to Figures 13 and 14. Therefore, similar to the above-described embodiment, the configuration is such that it is possible to sufficiently avoid both an increase in dark noise due to the generation of dark electrons and an increase in dark noise due to transfer defects, it is possible to obtain a sufficient number of saturated electrons, it is possible to obtain a low-noise image on the reproduced image, and it is possible to obtain an image with a high dynamic range.

[0285] The eighth embodiment can be applied in combination with any of the first to seventh embodiments.

[0286] <Configuration Example of Electronic Device> The photodetector 1 as described above can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0287] FIG. 41 is a block diagram showing an example of the configuration of an electronic device.

[0288] As shown in Figure 41, electronic device 1001 is equipped with an optical system 1002, a photodetector 1003, and a DSP (Digital Signal Processor) 1004, and is configured by connecting DSP 1004, a display device 1005, an operation system 1006, a memory 1008, a recording device 1009, and a power supply system 1010 via a bus 1007, and is capable of capturing still images and moving images.

[0289] The optical system 1002 is configured to have one or more lenses, and guides image light (incident light) from a subject to the photodetector 1003 , forming an image on the light receiving surface (sensor portion) of the photodetector 1003 .

[0290] The photodetector 1003 is a photodetector 1 including the pixel 100 of any of the configuration examples described above. Electrons are accumulated in the photodetector 1003 for a certain period of time in accordance with an image formed on the light-receiving surface via the optical system 1002. A signal corresponding to the electrons accumulated in the photodetector 1003 is then supplied to the DSP 1004.

[0291] The DSP 1004 performs various signal processing on the signal from the photodetector 1003 to acquire an image, and temporarily stores the image data in a memory 1008. The image data stored in the memory 1008 is recorded in a recording device 1009 or supplied to a display device 1005 to display the image. In addition, an operation system 1006 accepts various operations by a user and supplies operation signals to each block of the electronic device 1001, and a power supply system 1010 supplies power necessary to drive each block of the electronic device 1001.

[0292] <Application Example to Endoscopic Surgery System> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be applied to an endoscopic surgery system.

[0293] FIG. 42 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0294] 42 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical tools 11110 such as an insufflation tube 11111 and an energy treatment tool 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0295] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0296] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens toward an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0297] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0298] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102 and performs various types of image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0299] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0300] The light source device 11203 is composed of a light source such as an LED (light emitting diode), and supplies irradiation light to the endoscope 11100 when photographing the surgical area, etc.

[0301] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiated light, magnification, focal length, etc.) of the endoscope 11100.

[0302] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0303] The light source device 11203, which supplies illumination light to the endoscope 11100 when photographing the surgical site, can be configured from a white light source, such as an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, allowing the light source device 11203 to adjust the white balance of the captured image. In this case, it is also possible to time-share images corresponding to each RGB by irradiating the object of observation with laser light from each RGB laser light source and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, color images can be obtained without providing a color filter to the image sensor.

[0304] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free from so-called blocked-up shadows and blown-out highlights.

[0305] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may involve fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation may involve irradiating excitation light onto body tissues and observing the fluorescence from the tissue (autofluorescence observation), or by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0306] FIG. 43 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0307] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so that they can communicate with each other.

[0308] The lens unit 11401 is an optical system provided at the connection portion with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0309] The imaging unit 11402 may include one imaging element (a so-called single-chip type) or multiple imaging elements (a so-called multi-chip type). When the imaging unit 11402 is configured as a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured to have a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to a 3D (dimensional) display. The 3D display allows the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured as a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0310] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0311] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0312] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0313] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0314] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with a so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0315] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0316] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0317] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0318] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data transmitted from the camera head 11102 .

[0319] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0320] Furthermore, the control unit 11413 displays the captured image showing the surgical site, etc., on the display device 11202 based on the image signal subjected to image processing by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0321] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable of these.

[0322] In the illustrated example, communication is performed wired using a transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0323] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0324] FIG. 44 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0325] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 44, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0326] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0327] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0328] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0329] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0330] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0331] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0332] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0333] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0334] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 44, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0335] FIG. 45 is a diagram showing an example of the installation position of the imaging unit 12031.

[0336] In FIG. 45, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0337] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0338] 45 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0339] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0340] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0341] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0342] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0343] In this specification, a system refers to an entire device made up of multiple devices.

[0344] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0345] It should be noted that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible within the scope of the present technology.

[0346] The present technology may also be configured as follows. (1) A photodetector including: a photoelectric conversion unit formed in a semiconductor substrate for converting light into electric charges; an accumulation unit for temporarily accumulating the electric charges; and a transfer unit configured to transfer the electric charges to the accumulation unit, wherein the transfer unit includes a transfer gate at least a portion of which is provided in the semiconductor substrate, and an extension line of the direction of movement of the electric charges at a point of the semiconductor substrate where the electric potential is modulated by the transfer unit intersects with the accumulation unit in a planar view. (2) The photodetector according to (1), wherein the extension line and a side of the accumulation unit facing the transfer unit are substantially perpendicular to each other. (3) The photodetector according to (1) or (2), wherein the extension line is a direction that follows at least a part of an end of an insulating film provided on a side wall of the transfer gate of the transfer unit. (4) The photodetector according to any of (1) to (3), wherein the extension line is a direction that follows at least a position of one side of the transfer gate of the transfer unit. (5) The photodetector according to any one of (1) to (4), wherein the transfer section includes two transfer gates, and the movement directions of the two transfer gates intersect with the storage section. (6) The photodetector according to any one of (1) to (5), further including an inter-pixel isolation section that isolates pixels, and a conductor section that is on the inter-pixel isolation section and in contact with the storage section, and wherein the extension line intersects with a line that passes through the center of one side of the conductor section and passes through the center of another side perpendicular to the one side. (7) The photodetector according to (6), wherein the line that passes through the conductor section is parallel to a side of the storage section. (8) An electronic device comprising: a photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate for converting light into electric charges; a storage unit for temporarily storing the electric charges; and a transfer unit configured to transfer the electric charges to the storage unit, wherein the transfer unit has a transfer gate at least a portion of which is provided in the semiconductor substrate, and an extension line of the direction of movement of the electric charges at a point of the semiconductor substrate where the electric potential is highest, among the portion of the semiconductor substrate where the electric potential is modulated by the transfer unit, intersects with the storage unit in a planar view; and a processing unit that processes signals from the photodetector.(9) A photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate that converts light into charges, a storage unit that temporarily stores the charges, and a transfer unit configured to transfer the charges to the storage unit, wherein the transfer unit comprises a transfer gate at least a portion of which is provided in the semiconductor substrate, and a first line passing through one surface of the transfer gate intersects with the storage unit in a planar view. (10) An electronic device comprising: a photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate that converts light into charges, a storage unit that temporarily stores the charges, and a transfer unit configured to transfer the charges to the storage unit, wherein the transfer unit comprises a transfer gate at least a portion of which is provided in the semiconductor substrate, and a first line passing through one surface of the transfer gate intersects with the storage unit in a planar view; and a processing unit that processes signals from the photodetector. (11) A photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate that converts light into electric charges, an accumulation unit that temporarily accumulates the electric charges, and a transfer unit configured to transfer the electric charges to the accumulation unit, wherein the transfer unit comprises two transfer gates, at least a portion of which is provided in the semiconductor substrate, and a first line that passes through a center between the two transfer gates and is perpendicular to an arrangement direction of the two transfer gates intersects with the accumulation unit in a planar view. (12) The photodetector according to (11), further comprising: an inter-pixel isolation unit that isolates pixels, and a conductor unit of the same conductivity type as the accumulation unit, that contacts the accumulation unit in a region where the inter-pixel isolation unit intersects, wherein the first line that passes through the two transfer gates and a second line that passes through a center of one side of the conductor unit and passes through a center of another side perpendicular to the one side are parallel to each other. (13) The photodetector according to (11) or (12), wherein the transfer unit includes a first transfer gate and a second transfer gate, and the line orthogonal to the first line is a line passing through a center of the first transfer gate and a center of the second transfer gate. (14) The photodetector according to any one of (11) to (13), wherein the transfer gate includes a vertical electrode formed in the semiconductor substrate, and at least a portion of the vertical electrode is covered with an insulating film.(15) The photodetector according to (12), wherein the conductor portion is formed in a cross shape, and the second line is a line passing through the center of a vertical side and the center of a horizontal side of the cross-shaped conductor portion. (16) The photodetector according to (12), wherein the conductor portion is formed in a quadrangular shape, and the second line is a line passing through the center of each of two sides of the quadrangular conductor portion that straddles the inter-pixel separation portion. (17) The photodetector according to (12), wherein the angle formed by the first line and one side of the inter-pixel separation portion is approximately 45 degrees, approximately 30 degrees, or approximately 0 degrees. (18) The photodetector according to any of (11) to (16), further comprising: a first conductor layer stacked on the photoelectric conversion portion and having the same conductivity type as the photoelectric conversion portion, and the transfer gate is provided up to a position where it contacts the first conductor layer. (19) The photodetector according to (18), wherein a second conductor layer having a conductivity type different from that of the first conductor layer is stacked on the first conductor layer. (20) An electronic device comprising: a photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate for converting light into charges, an accumulation unit for temporarily accumulating the charges, and a transfer unit configured to transfer the charges to the accumulation unit, wherein the transfer unit comprises two transfer gates, at least a portion of which is provided in the semiconductor substrate, and a line passing through the center between the two transfer gates and perpendicular to the arrangement direction of the two transfer gates intersects with the accumulation unit in a plan view; and a processing unit for processing signals from the photodetector.

[0347] REFERENCE SIGNS LIST 1 Photodetector, 10 Semiconductor substrate, 20 Pixel array section, 21 Vertical drive circuit section, 22 Column signal processing circuit section, 23 Horizontal drive circuit section, 24 Output circuit section, 25 Control circuit section, 26 Element drive line, 27 Vertical signal line, 28 Horizontal signal line, 29 Input / output terminal, 31 Conductor section, 34 Column signal processing circuit, 42 Well layer, 50 First substrate, 51 Semiconductor substrate, 60 Second substrate, 61 Semiconductor substrate, 62 Readout circuit section, 70 Third substrate, 71 Semiconductor substrate, 72 Logic circuit, 100 Pixel, 200 On-chip lens, 202 Color filter, 204 Light-shielding section, 251 Region, 300 Photodiode, 304 Protrusion, 306 Diffusion region, 310 Inter-pixel isolation portion, 312 slit, 321 P-type region, 322 filling material, 323 oxide film, 351 conductor portion, 352 conductor portion, 353 conductor portion, 355 wiring, 356 wiring, 361 conductor portion, 371 conductor portion, 400 transfer gate, 401 insulating film, 402 insulating film, 410 transfer gate, 411 insulating film, 501 N-type layer, 502 P-type layer, 600 transfer gate, 601 insulating film, 701 gate electrode, 711 transistor

Claims

1. A photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate for converting light into charges; a storage unit for temporarily storing the charges; and a transfer unit configured to transfer the charges to the storage unit, wherein the transfer unit includes a transfer gate at least partially provided in the semiconductor substrate, and an extension line of the moving direction of the charges at the point where the potential is highest among the portions of the semiconductor substrate whose potential is modulated by the transfer unit intersects the storage unit in a plan view.

2. The photodetector according to claim 1, wherein the extension line and a side of the storage unit on the transfer unit side are substantially orthogonal.

3. The photodetector according to claim 1, wherein the extension line is at least along a part of an end of an insulating film provided on a side wall of the transfer gate of the transfer unit.

4. The photodetector according to claim 1, wherein the extension line is at least along a position of one side of the transfer gate of the transfer unit.

5. The photodetector according to claim 1, wherein the transfer unit includes two transfer gates, and the moving directions of the two transfer gates each intersect the storage unit.

6. The photodetector according to claim 1, further comprising: an inter-pixel separation unit for separating between pixels; and a conductor unit provided on the inter-pixel separation unit and in contact with the storage unit, wherein the extension line intersects a line passing through the center of one side of the conductor unit and the center of the other side orthogonal to the one side.

7. The photodetector according to claim 6, wherein the line passing through the conductor unit is parallel to a side of the storage unit.

8. An electronic device comprising: a photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate for converting light into charges; a storage unit for temporarily storing the charges; and a transfer unit configured to transfer the charges to the storage unit, wherein the transfer unit includes a transfer gate at least partially provided in the semiconductor substrate, and an extension line of the moving direction of the charges at the point where the potential is highest among the portions of the semiconductor substrate whose potential is modulated by the transfer unit intersects the storage unit in a plan view; and a processing unit for processing a signal from the photodetector.

9. A photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate for converting light into charges; a storage unit for temporarily storing the charges; and a transfer unit configured to transfer the charges to the storage unit, wherein the transfer unit includes a transfer gate at least partially provided in the semiconductor substrate, and a first line passing through one surface of the transfer gate intersects the storage unit in a plan view.

10. An electronic device comprising: a photodetector including: a photoelectric conversion unit formed in a semiconductor substrate for converting light into charges; a storage unit for temporarily storing the charges; and a transfer unit configured to transfer the charges to the storage unit, wherein the transfer unit includes a transfer gate at least partially provided in the semiconductor substrate, and a first line passing through one surface of the transfer gate intersects the storage unit in a plan view; and a processing unit for processing a signal from the photodetector.

11. A photodetector comprising: a photoelectric conversion unit formed in a semiconductor substrate for converting light into charges; a storage unit for temporarily storing the charges; and a transfer unit configured to transfer the charges to the storage unit, wherein the transfer unit includes two transfer gates each at least partially provided in the semiconductor substrate, and a first line passing through the center between the two transfer gates and orthogonal to the arrangement direction of the two transfer gates intersects the storage unit in a plan view.

12. The photodetector according to claim 11, further comprising: a pixel isolation unit for separating pixels; and a conductor unit in contact with the storage unit in a region where the pixel isolation unit intersects, and having the same conductivity type as the storage unit, wherein a second line passing through the center of one side of the conductor unit and orthogonal to the one side and passing through the center of the other side is parallel to the first line passing through the two transfer gates.

13. The photodetector according to claim 11, wherein the transfer unit includes a first transfer gate and a second transfer gate, and a line orthogonal to the first line passes through the centers of the first transfer gate and the second transfer gate.

14. The photodetector according to claim 11, wherein the transfer gate includes a vertical electrode formed in the semiconductor substrate, and at least a part of the vertical electrode is covered with an insulating film.

15. The conductor portion is formed in a cross shape, and the second line is a line passing through the centers of the longitudinal sides and the lateral sides of the cross-shaped conductor portion. The photodetection device according to claim 12.

16. The conductor portion is formed in a rectangular shape, and the second line is a line passing through the centers of the two sides straddling the pixel separation portion of the rectangular conductor portion. The photodetection device according to claim 12.

17. The angle formed by the first line and one side of the pixel separation portion is approximately 45 degrees, approximately 30 degrees, or approximately 0 degrees. The photodetection device according to claim 12.

18. A first conductor layer having the same conductivity type as the photoelectric conversion portion and laminated on the photoelectric conversion portion, and the transfer gate is provided up to a position in contact with the first conductor layer. The photodetection device according to claim 11.

19. A second conductor layer having a conductivity type different from that of the first conductor layer is laminated on the first conductor layer. The photodetection device according to claim 18.

20. An electronic device comprising: a photoelectric conversion portion formed in a semiconductor substrate for converting light into charges; a storage portion for temporarily storing the charges; and a transfer portion configured to transfer the charges to the storage portion, the transfer portion including two transfer gates at least a part of each of which is provided in the semiconductor substrate, and a line passing through the center between the two transfer gates and orthogonal to the arrangement direction of the two transfer gates intersects the storage portion in a plan view, a photodetection device, and a processing portion for processing a signal from the photodetection device.

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