Solar cell and photovoltaic module

Abstract

Disclosed in the present application are a solar cell and a photovoltaic module. The solar cell comprises: a silicon substrate, which has an illuminated face and a non-illuminated face opposite each other, and a side face disposed between the illuminated face and the non-illuminated face, wherein a protective layer is disposed on the side face, and the protective layer comprises a first conductive layer, an insulating layer and a second conductive layer, which are sequentially disposed on the side face, the conductivity type of the first conductive layer being opposite to the conductivity type of the second conductive layer. The insulating layer is used to perform insulated isolation between the first conductive layer and the second conductive layer, such that during the preparation of the cell, it is unnecessary to specifically remove a conductive layer formed on the side face of the silicon substrate by means of wrap-around plating, thereby facilitating the simplification of the production process for the cell. Moreover, using the protective layer to form shielding protection on the side face of the silicon substrate can prevent the side face of the silicon substrate from the risks of damage and electric leakage caused by direct exposure thereof, and can also reduce carrier recombination on the side face of the silicon substrate, thereby improving the conversion efficiency of the cell.

Description

A solar cell and a photovoltaic module Cross-reference to related applications This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on January 16, 2024, with the application number 202410065730.3 and the title "A solar cell and a photovoltaic module", and a Chinese patent application filed with the Chinese Patent Office on September 14, 2024, with the application number 202411295529.0 and the title "A back-contact cell and a photovoltaic module", the entire content of which is incorporated herein by reference. Technical field This application belongs to the field of photovoltaic technology, and specifically relates to a solar cell and a photovoltaic module. Background art A solar cell is a device that can convert the light energy of the sun into electrical energy. Specifically, when the solar cell is in a working state, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After connecting the circuit, an electric current can be generated. Among them, a solar cell with both the positive electrode and the negative electrode on the back of the cell is a back-contact cell. Compared with a double-sided contact solar cell, the front side of the back-contact cell has no metal electrode shielding, so that the light-receiving side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, which is one of the technical directions for realizing high-efficiency crystalline silicon cells at present. However, in existing back-contact cells, both the front and back sides of the silicon substrate are passivated, while the side of the silicon substrate is directly exposed, resulting in serious side recombination and an increased risk of damage, thereby reducing the efficiency of the back-contact cell. Summary of the invention The purpose of this application is to provide a solar cell and a photovoltaic module, which protect the side of the silicon substrate through a film layer provided on the side of the silicon substrate. While reducing the risk of side damage, it can also passivate the side of the silicon substrate, reduce the carrier recombination on the side of the silicon substrate, and improve the conversion efficiency of the back-contact cell. In order to solve the above technical problems, this application is implemented as follows: In a first aspect, this application provides a solar cell, including: a silicon substrate; the silicon substrate has an opposite light-receiving surface and a backlight surface, and a side surface disposed between the light-receiving surface and the backlight surface; A protective layer is provided on the side surface. Along the direction away from the silicon substrate, the protective layer includes a first conductive layer, an insulating layer, and a second conductive layer sequentially disposed on the side surface; the first conductive layer and the second conductive layer have opposite conduction types. In this application, by providing a protective layer on the side surface of the silicon substrate, the protective layer includes a first conductive layer, an insulating layer, and a second conductive layer provided on the side surface of the silicon substrate. The insulating layer is used to insulate and isolate between the first conductive layer and the second conductive layer, so that there is no need to specifically remove the conductive layer formed by overplating on the side surface of the silicon substrate during the battery preparation process, which helps to simplify the battery production process. Moreover, the protective layer can play a passivation and protection role for the side surface of the silicon substrate, which can not only avoid the risks of damage and leakage due to the direct exposure of the side surface of the silicon substrate, but also reduce the carrier recombination on the side surface of the silicon substrate and improve the conversion efficiency of the battery. Optionally, along the direction parallel to the backlight surface, the backlight surface has alternately arranged first regions and second regions; the first conductive layer is formed in the first regions, and the second conductive layer is formed in the second regions. Optionally, the protective layer further includes a first passivation layer located between the side surface and the first conductive layer and a second passivation layer located between the insulating layer and the second conductive layer; Along the direction parallel to the backlight surface, the backlight surface has alternately arranged first regions and second regions; along the direction away from the silicon substrate, the first passivation layer and the first conductive layer are sequentially formed in the first regions, and the second passivation layer and the second conductive layer are sequentially formed in the second regions; an insulating layer is provided between the first regions and the second regions. Optionally, the junction of the side surface and the backlight surface is the first position, and the junction of the side surface and the light-receiving surface is the second position. The thickness of the protective layer at the first position is greater than the thickness of the protective layer at the second position. Optionally, the thickness of the protective layer at the first position is D1, and the thickness of the protective layer at the second position is D2, satisfying: 1 < D1 / D2 ≤ 10. Optionally, the total thickness of the first passivation layer and the first conductive layer on the backlight surface is H1, the total thickness of the first passivation layer and the first conductive layer at the first position is H11, and the total thickness of the first passivation layer and the first conductive layer at the second position is H12, satisfying: H12 < H11 ≤ H1. Optionally, the total thickness H11 of the first passivation layer and the first conductive layer on the side surface at the first position and the total thickness H12 of the first passivation layer and the first conductive layer on the side surface at the second position satisfy: 0.2 ≤ H12 / H11 < 1. Optionally, the total thickness H1 of the first passivation layer and the first conductive layer on the backlight surface and the total thickness H11 of the first passivation layer and the first conductive layer at the first position satisfy: 0.5 ≤ H11 / H1 ≤ 1. Optionally, the total thickness H1 of the first passivation layer and the first conductive layer on the backlight surface and the total thickness H12 of the first passivation layer and the first conductive layer at the second position satisfy: 0.2 ≤ H12 / H1 ≤ 0.6. Optionally, the thickness of the insulating layer on the backlight surface is H2, the thickness of the insulating layer at the first position is H21, and the thickness of the insulating layer at the second position is H22, satisfying: H22 < H21 ≤ H2. Optionally, the thickness H21 of the insulating layer at the first position on the side surface and the thickness H22 of the insulating layer at the second position on the side surface satisfy: 0.2 ≤ H22 / H21 < 1. Optionally, the thickness H2 of the insulating layer on the backlight surface and the thickness H21 of the insulating layer at the first position satisfy: 0.5 ≤ H21 / H2 ≤ 1. Optionally, the thickness H2 of the insulating layer on the backlight surface and the total thickness H22 of the insulating layer at the second position satisfy: 0.2 ≤ H22 / H2 ≤ 0.6. Optionally, the total thickness of the second passivation layer and the second conductive layer on the backlight surface is H3, the total thickness of the second passivation layer and the second conductive layer at the first position is H31, and the total thickness of the second passivation layer and the second conductive layer at the second position is H32, satisfying: H32 < H31 ≤ H3. Optionally, the total thickness H31 of the second passivation layer and the second conductive layer at the first position on the side surface and the total thickness H32 of the second passivation layer and the second conductive layer at the second position on the side surface satisfy: 0.2 ≤ H32 / H31 < 1. Optionally, the total thickness H3 of the second passivation layer and the second conductive layer on the backlight surface and the total thickness H31 of the second passivation layer and the second conductive layer at the first position satisfy: 0.5 ≤ H31 / H3 ≤ 1. Optionally, the total thickness H3 of the second passivation layer and the second conductive layer on the backlight surface and the total thickness H32 of the second passivation layer and the second conductive layer at the second position satisfy: 0.2 ≤ H32 / H3 ≤ 0.6. Optionally, the protective layer further includes a third passivation layer and an antireflection layer. The third passivation layer is provided on the side of the second conductive layer away from the side surface, and the antireflection layer is provided on the side of the third passivation layer away from the second conductive layer; In the direction away from the silicon substrate, a third passivation layer and an antireflection layer are sequentially formed on the light-receiving surface. Optionally, the total thickness of the third passivation layer and the antireflection layer on the light-receiving surface is H4, the total thickness of the third passivation layer and the antireflection layer at the first position is H41, and the total thickness of the third passivation layer and the antireflection layer at the second position is H42, satisfying: H41 < H42 ≤ H4. Optionally, the total thickness H41 of the third passivation layer and the antireflection layer at the first position on the side surface and the total thickness H42 of the third passivation layer and the antireflection layer at the second position on the side surface satisfy: 0.1 ≤ H42 / H41 < 1. Optionally, the total thickness H4 of the third passivation layer and the antireflection layer on the light-receiving surface and the total thickness H41 of the third passivation layer and the antireflection layer at the first position satisfy: 0.1 ≤ H41 / H4 ≤ 0.4. Optionally, the total thickness H4 of the third passivation layer and the antireflection layer on the light-receiving surface and the total thickness H42 of the third passivation layer and the antireflection layer at the second position satisfy: 0.5 ≤ H42 / H4 ≤ 0.8. Optionally, the protective layer further includes: a transparent conductive layer disposed on the side of the antireflection layer away from the side surface; At least one of the first region and the second region is provided with a transparent conductive layer, and the transparent conductive layer is disposed on the side of the first conductive layer and / or the second conductive layer away from the backlight surface. Optionally, the thickness of the transparent conductive layer on the backlight surface is H5, the thickness of the transparent conductive layer at the first position is H51, and the thickness of the transparent conductive layer at the second position is H52, satisfying: H52 < H51 ≤ H5. Optionally, the thickness H51 of the transparent conductive layer at the first position on the side surface and the thickness H52 of the transparent conductive layer at the second position on the side surface satisfy: 0.3 ≤ H52 / H51 < 1. Optionally, the thickness H5 of the transparent conductive layer on the backlight surface and the thickness H51 of the transparent conductive layer at the first position satisfy: 0.5 ≤ H51 / H5 ≤ 1. Optionally, the thickness H5 of the transparent conductive layer on the backlight surface and the thickness H52 of the transparent conductive layer at the second position satisfy: 0.2 ≤ H52 / H5 ≤ 0.5. In the first set of possible implementation solutions of the first aspect, further, the solar cell is a back-contact cell; The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes a surface passivation layer and an antireflection layer; Wherein, the back-contact cell includes: along the direction away from the silicon substrate, a first interface passivation layer, a first doped silicon layer, a surface passivation layer, an antireflection layer, an intrinsic silicon layer, a second doped silicon layer, and a transparent conductive layer are sequentially disposed on the side surface; Wherein, along the thickness direction of the silicon substrate, the surface passivation layer and the antireflection layer are also sequentially disposed on the light-receiving surface, and the surface passivation layer and the antireflection layer extend from the light-receiving surface to the side surface. In this application, in the case of adopting the above technical solution, on the side surface of the silicon substrate and in the direction away from the side surface, a first interface passivation layer, a first doped silicon layer, a surface passivation layer, an antireflection layer, an intrinsic silicon layer, a second doped silicon layer, and a transparent conductive layer are sequentially arranged. The presence of the above-mentioned film layers can isolate the side surface of the silicon substrate from the external environment, reducing the risk of damage such as scratches on the side surface of the silicon substrate due to factors such as extrusion and collision during transportation or packaging. At the same time, it can also reduce the risk of water vapor and the like entering the battery from the side of the battery and causing battery failure, improving the service life of the back-contact battery. In addition, the surface passivation layer and the antireflection layer are not only located on the light-receiving surface of the silicon substrate but also extend to the side surface of the silicon substrate. At this time, on the side surface of the silicon substrate, the first doped silicon layer and the second doped silicon layer with opposite conduction types can be isolated by the surface passivation layer and the antireflection layer, preventing the two from conducting and leaking electricity, so that the back-contact battery has a high conversion efficiency. In addition, the part of the surface passivation layer and the antireflection layer arranged on the light-receiving surface can reduce carrier recombination and surface reflectivity. When the two are extended to the side surface of the silicon substrate, they can also be used to isolate the first doped silicon layer and the second doped silicon layer. There is no need to additionally form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer and the second doped silicon layer, which can simplify the manufacturing process of the back-contact battery. At the same time, there is no need to consider the compatibility between the film layer for isolating the first doped silicon layer and the second doped silicon layer and other structures in the back-contact battery, ensuring a high yield of the back-contact battery. At the same time, not only the first interface passivation layer and the first doped silicon layer arranged on the side surface of the silicon substrate have a passivation effect on the silicon substrate, but the above-mentioned surface passivation layer that realizes the insulation isolation of the first doped silicon layer and the second doped silicon layer on the side surface can also passivate the side surface of the silicon substrate, further reducing the carrier recombination rate on the side surface of the silicon substrate and improving the conversion efficiency of the back-contact battery. In addition, in the actual manufacturing process, the formation sequence of the corresponding film layers arranged on the backlight surface and the light-receiving surface of the silicon substrate affects the formation sequence of the corresponding film layers on the side surface of the silicon substrate. Since the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate is closely related to processes, battery structures, equipment, etc., the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate cannot be adjusted arbitrarily. That is to say, the formation sequence of the film layers formed on the side surface of the silicon substrate cannot be adjusted arbitrarily and needs to be comprehensively considered according to the formation sequence requirements of the film layers on the side surface of the silicon substrate, the technical problems to be solved, as well as the formation sequence requirements and the solved technical problems of the front and back film layers. Optionally, the backlight surface includes a first region and a second region; the first interface passivation layer and the first doped silicon layer are located in the first region; the intrinsic silicon layer and the second doped silicon layer are located in the second region, extend from the second region to the first region, and cover a part of the first interface passivation layer and the first doped silicon layer; the insulating layer further includes an insulating mask layer; the insulating mask layer is disposed between the first doped silicon layer on the side and the surface passivation layer, and the insulating mask layer is also disposed along the thickness direction of the silicon substrate between the intrinsic silicon layer and the first doped silicon layer on the backlight surface. In the case of adopting the above technical solution, on the backlight surface of the silicon substrate, the intrinsic silicon layer and the second doped silicon layer are not only stacked in sequence along the thickness direction of the silicon substrate in the second region, but also cover a part of the first interface passivation layer and the first doped silicon layer. At this time, the formation range of the intrinsic silicon layer and the second doped silicon layer on one side of the backlight surface of the silicon substrate is relatively large, which is beneficial to reducing the etching range of the integral intrinsic silicon layer and the second doped silicon layer during the manufacturing process and improving the etching productivity. Moreover, the part of the intrinsic silicon layer and the second doped silicon layer covering the first doped silicon layer can protect the edge of the first doped silicon layer and prevent the etchant from affecting the edge of the first doped silicon layer, ensuring that the edge of the first doped silicon layer has a high carrier collection efficiency. The insulating mask layer can, together with the surface passivation layer and the antireflection layer, separate the first doped silicon layer and the second doped silicon layer on the side, further suppressing side leakage. At the same time, it can also passivate the side of the silicon substrate, further reducing the number of defects on the side of the silicon substrate. In addition, forming an insulating mask layer on the side is also beneficial to reducing the thickness requirement for the intrinsic silicon layer. While ensuring a low forward leakage between the first doped silicon layer and the second doped silicon layer, the intrinsic silicon layer has a low tunneling resistance, which is beneficial to improving the carrier collection efficiency of the second doped silicon layer on the backlight surface side. Optionally, on the side of the silicon substrate, the thickness of the insulating mask layer gradually increases in the direction from the light-receiving surface to the backlight surface. Optionally, the insulating mask layer disposed on the side is located on a partial area of the side; along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the insulating mask layer on the side to the thickness of the silicon substrate is less than or equal to 80%. In the case of adopting the above technical solution, it can be understood that the greater the extension length of the insulating mask layer on the side, the more the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be isolated by forming a larger insulating mask layer, the lower the forward leakage of the back contact battery, and the stronger the protection effect of the insulating mask layer on the side of the silicon substrate. And the smaller the extension length of the insulating mask layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the hot spot risk of the back contact battery. Based on this, when the ratio of the maximum extension length of the insulating mask layer on the side to the thickness of the silicon substrate is less than or equal to 80%, the forward leakage, hot spot risk and side protection of the back contact battery can be regulated by adjusting the maximum extension length of the insulating mask layer on the side according to the actual application scenario requirements of the back contact battery, which is beneficial to achieving the balance among the forward leakage, hot spot risk and side protection of the back contact battery. Optionally, the first interface passivation layer and the first doped silicon layer disposed on the side are only located on a partial area of the side and are close to the backlight surface; wherein, along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side to the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is a matte surface, and the ratio of the maximum extension length of the matte surface on the side to the thickness of the silicon substrate is less than or equal to 30%; and / or, in the side, the surface reflectivity of the area that is not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area that is covered by the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is a matte surface; and / or, the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer is a polished surface. In the case of adopting the above technical solution, as described above, the first interface passivation layer and the first doped silicon layer have a passivation effect on the side of the silicon substrate. Therefore, when the ratio of the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side to the thickness of the silicon substrate is greater than or equal to 70%, it is ensured that the first interface passivation layer and the first doped silicon layer have a larger formation range on the side of the silicon substrate, so that the surface of more areas on the side has a lower carrier recombination rate, further improving the conversion efficiency of the back contact battery. And, most areas on the side of the silicon substrate are covered with the first interface passivation layer and the first doped silicon layer. At this time, the first interface passivation layer and the first doped silicon layer have a protective effect on most areas on the side of the silicon substrate. When preventing the intrusion of water vapor and the like, it is ensured that the side of the silicon substrate has a relatively thick laminated protection, further improving the protection effect of the side of the silicon substrate. The application principle of the beneficial effect that the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is a matte surface, and the ratio of the maximum extension length of the matte surface on the side to the thickness of the silicon substrate is less than or equal to 30% can refer to the above, and will not be elaborated here. In addition, compared with the area on the side of the silicon substrate that is covered by the first interface passivation layer and the first doped silicon layer, the surface reflectivity of the area on the side of the silicon substrate that is not covered by the first interface passivation layer and the first doped silicon layer is smaller. At this time, although the passivation effect of the surface of the area on the side of the silicon substrate that is not covered by the first interface passivation layer and the first doped silicon layer is relatively low, this area surface has a relatively high light trapping effect, which is beneficial to making more light refract into the silicon substrate from the side of the silicon substrate close to the light-receiving surface, which is beneficial to improving the conversion efficiency of the back contact battery. In addition, it is not necessary to strictly control the manufacturing conditions in order to retain all the first interface passivation layer and the first doped silicon layer on the side during the process of removing the first interface passivation layer and the first doped silicon layer plated around the light-receiving surface, reducing the manufacturing difficulty of the back contact battery.Furthermore, when the surface of the region covering the first interface passivation layer and the first doped silicon layer on the side is a polished surface, the surface of the region covering the first interface passivation layer and the first doped silicon layer on the side is relatively flat, which is conducive to forming a thicker first interface passivation layer and first doped silicon layer on this region, enhancing the passivation effect of the first interface passivation layer and the first doped silicon layer on the corresponding region of the side, and further improving the conversion efficiency of the back contact battery. Optionally, the thickness of each part of the first interface passivation layer and / or the first doped silicon layer is the same. In this case, it is conducive to making each part of the first interface passivation layer and / or the first doped silicon layer have a high passivation effect, so that each region in the silicon substrate corresponding to the first interface passivation layer and / or the first doped silicon layer in the silicon substrate has a relatively low carrier recombination rate, and further improving the conversion efficiency of the back contact battery. Optionally, on the side of the silicon substrate, the thickness of the surface passivation layer is equal, or the thickness of the surface passivation layer gradually increases in the direction from the backlight surface to the light-receiving surface. In the case of adopting the above technical solution, within a certain range, the thickness of the surface passivation layer is proportional to its own passivation effect and insulation isolation effect. Based on this, when the thickness of the surface passivation layer on the side of the silicon substrate is equal, each part of the surface passivation layer has a high passivation effect and high insulation isolation characteristics, which is conducive to making each region covered with the surface passivation layer on the side of the silicon substrate have a low number of surface defects, and is also conducive to better realizing the electrical isolation effect between the first doped silicon layer and the second doped silicon layer through the surface passivation layer with uniform thickness, and reducing forward leakage. When the thickness of the surface passivation layer gradually increases in the direction from the backlight surface to the light-receiving surface, the part of the surface passivation layer on the side close to the light-receiving surface has a high passivation effect and better insulation isolation characteristics. While further reducing the number of surface defects in the region close to the light-receiving surface on the side of the silicon substrate, it further reduces the leakage risk between the first doped silicon layer and the second doped silicon layer, which is conducive to increasing the open circuit voltage and fill factor of the back contact battery. Optionally, on the side of the silicon substrate, the thickness of the antireflection layer gradually increases in the direction from the backlight surface to the light-receiving surface. In this case, the part of the surface passivation layer on the side close to the light-receiving surface has better insulation isolation characteristics, further reducing the leakage risk between the first doped silicon layer and the second doped silicon layer, and is conducive to increasing the open circuit voltage and fill factor of the back contact battery. Optionally, on the side of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer, and the transparent conductive layer gradually increases in the direction from the light-receiving surface to the backlight surface. In the case of adopting the above technical solution, on the side of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer, and the transparent conductive layer is larger near the backlight surface, which is conducive to improving the protection effect of this film layer on the region near the backlight surface on the side of the silicon substrate, and can further improve the structural reliability of the side in the back contact battery. Optionally, the surface passivation layer and the antireflection layer provided on the side are located on a partial area of the side and close to the light-receiving surface; along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the surface passivation layer and the antireflection layer on the side to the thickness of the silicon substrate is less than or equal to 80%. In the case of adopting the above technical solution, when forming the surface passivation layer and the antireflection layer on the light-receiving surface and the side of the silicon substrate, the surface passivation layer and the antireflection layer may also be formed on the backlight side due to overplating. To eliminate the influence of the surface passivation layer and the antireflection layer on the backlight side on the carrier collection efficiency of the second interface passivation layer and the second doped silicon layer, it is necessary to remove the part of them overplated to the backlight side. Based on this, when the surface passivation layer and the antireflection layer provided on the side can be located on a partial area of the side, the difficulty of removing the part of the surface passivation layer and the antireflection layer overplated to the backlight side can be reduced, and the manufacturing precision requirements can be lowered. In addition, at the area of the side of the silicon substrate where the surface passivation layer and the antireflection layer are not covered, the first doped silicon layer can be electrically contacted with the second interface passivation layer and the second doped silicon layer with the opposite conductivity type to itself, so as to form a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, which is beneficial to reducing the hot spot risk of the back contact battery and improving the anti-burning ability of the back contact battery. Or, the surface passivation layer provided on the side is located on a partial area of the side and close to the light-receiving surface; along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the surface passivation layer on the side to the thickness of the silicon substrate is less than or equal to 80%. The beneficial effects corresponding to this feature will not be elaborated here. Optionally, the material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. In the case of adopting the above technical solution, hydrogen is contained in aluminum oxide and intrinsic amorphous silicon. When the material of the surface passivation layer includes aluminum oxide and / or intrinsic amorphous silicon, hydrogen passivation can be performed on the silicon substrate and the first doped silicon layer to further improve the passivation effect of the surface passivation layer. And the doped silicon glass is doped with impurities of the corresponding conductivity type, and field passivation can also be performed on the silicon substrate and the first doped silicon layer, which can also further improve the passivation effect of the surface passivation layer. Secondly, the manufacturing process of the surface passivation layer made of doped silicon glass is also relatively simple, which is beneficial to reducing the manufacturing difficulty of the back contact battery. Optionally, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm. In the case of adopting the above technical solution, the presence of the transparent conductive layer can improve the carrier collection efficiency and leave a margin for thinning the first doped silicon layer. In other words, on the premise of not reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is beneficial to reducing its own parasitic absorption and further improving the working efficiency of the back contact battery. And it can also reduce the deposition time of the first doped silicon layer and improve the manufacturing efficiency of the first doped silicon layer. Optionally, the thickness of the intrinsic silicon layer is greater than or equal to 8 nm and less than or equal to 14 nm. In this case, the relatively large thickness of the intrinsic silicon layer is conducive to enhancing the isolation effect between the first doped silicon layer and the second doped silicon layer, and reducing the risk of forward leakage. Optionally, in the side surface of the silicon substrate, the region where the first interface passivation layer and the first doped silicon layer are provided has a tower base-like texture structure; wherein, the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower base-like texture structure. In the case of adopting the above technical solution, it can be understood that the bottom surface and the side wall of the above tower base-like texture structure have different crystal orientations. Specifically, the bottom surface of the tower base-like texture structure is

[0110] the

[0110] crystal orientation, and the number of dangling bonds on the surface with the

[0110] crystal orientation is relatively small; while the side wall of the tower base-like texture structure is

[0111] the

[0111] crystal orientation, and the number of dangling bonds on the

[0111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure, it is conducive to making the part of the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure have a relatively high passivation effect, meeting the requirement of the side wall of the tower base-like texture structure for a high passivation effect, reducing the carrier recombination rate of the side wall of the tower base-like texture structure, and further improving the working efficiency of the back contact battery. Optionally, the side surface of the silicon substrate has a tower base-like texture structure; wherein, the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower base-like texture structure; the thickness of the intrinsic silicon layer located at the bottom surface of the tower base-like texture structure is greater than the thickness of the intrinsic silicon layer located at the side wall of the tower base-like texture structure; and / or, the thickness of the second doped silicon layer located at the bottom surface of the tower base-like texture structure is greater than the thickness of the second doped silicon layer located at the side wall of the tower base-like texture structure. In the case of adopting the above technical solution, the relationship between the thicknesses of the first interface passivation layer at the bottom surface and the side wall of the tower base-like texture structure is opposite to the relationship between the thicknesses of the intrinsic silicon layer and / or the second doped silicon layer at the bottom surface and the side wall of the tower base-like texture structure. At this time, the thickness of the first interface passivation layer located at the side wall of the tower base-like texture structure is relatively large, which can make up for the relatively weak passivation effect and protection function of the intrinsic silicon layer and / or the second doped silicon layer due to their relatively small thicknesses at the side wall of the tower base-like texture structure; and, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower base-like texture structure is relatively large, which can make up for the relatively weak passivation effect and protection function of the first interface passivation layer due to its relatively small thickness at the bottom surface of the tower base-like texture structure, ensuring that under the combined passivation and protection effects of the first interface passivation layer, the intrinsic silicon layer, and / or the second doped silicon layer, both the bottom surface and the side surface of the silicon substrate corresponding to the tower base-like texture structure have relatively high passivation effects and protection strengths. Optionally, on the side surface of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower base-like texture structure. Moreover, the thickness of the first interface passivation layer located on the bottom surface of the tower base-like texture structure is greater than the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure. Optionally, a doped layer is formed in the side surface of the silicon substrate; the dopant in the doped layer includes the dopant in the first doped silicon layer. In the case of adopting the above technical solution, a high-low junction can be formed between the doped layer and the first doped silicon layer, so that the energy band between the first doped silicon layer and the side surface of the silicon substrate is more matched, the passivation effect of the first doped silicon layer on the side surface of the silicon substrate is improved, and the open-circuit voltage of the back contact battery is increased. In the second group of possible implementation solutions of the first aspect, further, the solar cell is a back contact battery; The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes an insulating mask layer; wherein, the back contact battery includes: along the direction away from the silicon substrate, a first interface passivation layer, a first doped silicon layer, an insulating mask layer, an intrinsic silicon layer, a second doped silicon layer, and a transparent conductive layer are sequentially arranged on the side surface; wherein, the back contact battery includes a surface passivation layer arranged on the light-receiving surface, and the surface passivation layer extends from the light-receiving surface to the side surface; the back contact battery further includes a second interface passivation layer arranged on the backlight surface and located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the backlight surface to the side surface; on the side surface, the intrinsic silicon layer includes a surface passivation layer and a second interface passivation layer stacked in a direction away from the side surface. In the present application, in the case of adopting the above technical solution, in addition to the intrinsic silicon layer being disposed between the first doped silicon layer and the second doped silicon layer, an insulating mask layer is also provided. While ensuring a reduction in forward leakage loss, the thickness requirement for the intrinsic silicon layer can also be reduced, the tunneling resistance of the intrinsic silicon layer can be reduced, which is beneficial to improving the carrier collection efficiency of the second doped silicon layer disposed on the backlight side of the silicon substrate, and further improving the conversion efficiency of the back contact battery. Moreover, the presence of the insulating mask layer can also enhance the protection effect on the side surface of the silicon substrate, and further improve the side surface structure reliability of the back contact battery. In addition, during the actual manufacturing process, the formation sequence of the corresponding film layers disposed on the backlight surface and the light-receiving surface of the silicon substrate affects the formation sequence of the corresponding film layers on the side surface of the silicon substrate. Since the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate is closely related to processes, battery structures, equipment, etc., the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate cannot be arbitrarily adjusted. That is to say, the formation sequence of the film layers formed on the side surface of the silicon substrate cannot be arbitrarily adjusted, and it needs to be comprehensively considered according to the formation sequence requirements of the film layers on the side surface of the silicon substrate, the technical problems to be solved, as well as the formation sequence requirements and the technical problems solved by the front and back film layers. Optionally, the back contact battery further includes an anti-reflection layer disposed on the light-receiving surface, and the anti-reflection layer extends from the light-receiving surface to the side surface; on the side surface, the anti-reflection layer is disposed between the second doped silicon layer and the transparent conductive layer in a direction away from the side surface. In the case of adopting the above technical solution, an additional anti-reflection layer is added to the film layers on the side surface of the silicon substrate, which can further improve the protection effect on the side surface of the silicon substrate, reduce the risk of damage to the side surface of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate. Due to the difference between the materials of the surface passivation layer and the second doped silicon layer, and the anti-reflection layer is more likely to be deposited on the surface passivation layer. Based on this, compared with the anti-reflection layer being directly formed on the surface passivation layer, when the anti-reflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate, the plating-around range of the anti-reflection layer on the backlight side can be reduced, thereby reducing the etching amount when removing the plating-around of the anti-reflection layer on the backlight side and improving the manufacturing efficiency. Optionally, the first interface passivation layer and the first doped silicon layer disposed on the side surface are only located on a partial area of the side surface and close to the backlight surface; wherein, along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side surface to the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side surface that is not covered by the first interface passivation layer and the first doped silicon layer is a matte surface, and the ratio of the maximum extension length of the matte surface on the side surface to the thickness of the silicon substrate is less than or equal to 30%; and / or, in the side surface, the surface reflectivity of the area not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area covered by the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side surface that is not covered by the first interface passivation layer and the first doped silicon layer is a matte surface; and / or, the surface of the area on the side surface that is covered by the first interface passivation layer and the first doped silicon layer is a polished surface. Optionally, each part of the first interface passivation layer and / or the first doped silicon layer has the same thickness. Optionally, on the side surface of the silicon substrate, the thickness of the surface passivation layer is equal, or the thickness of the surface passivation layer gradually increases in a direction from the backlight surface to the light-receiving surface. Optionally, on the side surface of the silicon substrate, the thickness of the anti-reflection layer gradually increases in a direction from the backlight surface to the light-receiving surface. Optionally, on the side surface of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer, and the transparent conductive layer gradually increases in a direction from the light-receiving surface to the backlight surface. Optionally, the surface passivation layer and the anti-reflection layer disposed on the side surface are located on a partial area of the side surface and close to the light-receiving surface; along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the surface passivation layer and the anti-reflection layer on the side surface to the thickness of the silicon substrate is less than or equal to 80%. Optionally, the material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Optionally, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm. Optionally, the thickness of the intrinsic silicon layer is greater than or equal to 8 nm and less than or equal to 14 nm. Optionally, in the side surface of the silicon substrate, the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-base-like texture structure; wherein, the thickness of the first interface passivation layer located at the bottom surface of the tower-base-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower-base-like texture structure. Optionally, in the side surface of the silicon substrate, the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower-base-like texture structure. Moreover, the thickness of the first interface passivation layer located at the bottom surface of the tower-base-like texture structure is greater than the thickness of the first interface passivation layer located on the side wall of the tower-base-like texture structure. Optionally, the side surface of the silicon substrate has a tower-base-like texture structure; wherein, the thickness of the first interface passivation layer located at the bottom surface of the tower-base-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower-base-like texture structure; the thickness of the intrinsic silicon layer located at the bottom surface of the tower-base-like texture structure is greater than the thickness of the intrinsic silicon layer located at the side wall of the tower-base-like texture structure; and / or, the thickness of the second doped silicon layer located at the bottom surface of the tower-base-like texture structure is greater than the thickness of the second doped silicon layer located at the side wall of the tower-base-like texture structure. Optionally, a doped layer is formed in the side surface of the silicon substrate; the dopant in the doped layer includes the dopant in the first doped silicon layer. It should be understood that in the second group and the first group of the first aspect, the same or similar alternative solutions have the same or similar technical effects, which will not be elaborated here. In the second aspect, the present application proposes a solar cell, and the solar cell is a back contact cell, wherein the back contact cell includes: A silicon substrate, the silicon substrate includes a backlight surface and a light-receiving surface arranged oppositely, and a side surface connecting the backlight surface and the light-receiving surface; And, in the direction away from the side surface, a first interface passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer, and a transparent conductive layer are sequentially arranged on the side surface; on the side surface of the silicon substrate, the first doped silicon layer and the intrinsic silicon layer are in direct contact; wherein, the conductive types of the first doped silicon layer and the second doped silicon layer are opposite. In this application, in the case of adopting the above technical solution, on the side of the silicon substrate, the first doped silicon layer can be electrically connected through the intrinsic silicon layer and the second doped silicon layer with the opposite conductivity type to itself, so as to form a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, reducing the hot spot risk of the back contact battery. At the same time, the first doped silicon layer, the intrinsic silicon layer, and the second doped silicon layer provided on the side of the silicon substrate can also passivate the side of the silicon substrate, reduce the carrier recombination rate on the side of the silicon substrate, and improve the conversion efficiency of the back contact battery. Secondly, the first doped silicon layer, the intrinsic silicon layer, and the second doped silicon layer provided on the side of the silicon substrate can also protect the side of the silicon substrate, reduce the risk of damage and leakage easily occurring due to the direct exposure of the side of the silicon substrate, and improve the structural reliability of the back contact battery. In addition, during the actual manufacturing process, the formation sequence of the corresponding film layers provided on the backlight surface and the light-receiving surface of the silicon substrate affects the formation sequence of the corresponding film layers on the side of the silicon substrate. Since the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate is closely related to processes, battery structures, equipment, etc., the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate cannot be adjusted arbitrarily. That is to say, the formation sequence of the film layers formed on the side of the silicon substrate cannot be adjusted arbitrarily, and it needs to be comprehensively considered according to the formation sequence requirements of the film layers on the side of the silicon substrate, the technical problems to be solved, as well as the formation sequence requirements and the solved technical problems of the front and back film layers. Optionally, the back contact battery includes a surface passivation layer provided on the light-receiving surface, and the surface passivation layer extends from the light-receiving surface to the side. And, the back contact battery further includes a second interface passivation layer provided on the backlight surface and located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the backlight surface to the side. Based on this, on the side, the intrinsic silicon layer includes the surface passivation layer and the second interface passivation layer stacked in a direction away from the side. In the case of adopting the above technical solution, on the side of the silicon substrate, there are two film layers, namely the surface passivation layer and the second interface passivation layer, between the first doped silicon layer and the second doped silicon layer. At this time, the intrinsic silicon layer has a certain transmission resistance, which is beneficial to reducing the forward leakage of the back contact battery and balancing the conversion efficiency and hot spot risk of the back contact battery. In addition, while obtaining a lower forward leakage, there is no need to form a thicker intrinsic silicon layer, resulting in a larger thickness of a single second interface passivation layer or surface passivation layer, ensuring that the second interface passivation layer has a lower tunneling resistance and the surface passivation layer has a lower hindrance to light transmission, and ensuring that the back contact battery has a higher conversion efficiency. Optionally, on the side of the silicon substrate, the thicknesses of all parts of the intrinsic silicon layer are the same. In this case, all parts of the intrinsic silicon layer provided on the side of the silicon substrate have higher passivation performance and protection effects, which can further reduce the carrier recombination rate on the side of the silicon substrate and improve the structural reliability of the back contact battery. Optionally, on the side surface of the silicon substrate, the thickness of the intrinsic silicon layer is greater than or equal to 5 nm and less than or equal to 30 nm. In the case of adopting the above technical solution, on the side surface of the silicon substrate, the thickness of the intrinsic silicon layer is within the above range, which is beneficial to preventing the poor passivation performance and protection effect caused by the small thickness of the intrinsic silicon layer, ensuring a low carrier recombination rate and high structural reliability on the side surface, and at the same time is also beneficial to reducing the forward leakage loss of the back contact battery. It can also prevent the thickness of the second interface passivation layer (or the second interface passivation layer and the surface passivation layer) from being too large due to the large thickness of the intrinsic silicon layer, ensuring that the second interface passivation layer has a low tunneling resistance and the surface passivation layer has a low hindrance to light transmission, and ensuring that the back contact battery has a high conversion efficiency. Optionally, the back contact battery further includes an antireflection layer. On the light-receiving surface, the antireflection layer is disposed on the side of the surface passivation layer away from the silicon substrate. The antireflection layer extends from the light-receiving surface to the side surface, and on the side surface, the antireflection layer is disposed between the second doped silicon layer and the transparent conductive layer. In the case of adopting the above technical solution, an additional antireflection layer is added to the film layer on the side surface of the silicon substrate, which can further improve the protection effect on the side surface of the silicon substrate, reduce the risk of damage to the side surface of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the antireflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate. Since there are differences between the materials of the surface passivation layer and the second doped silicon layer, and the antireflection layer is more likely to be deposited on the surface passivation layer. Based on this, compared with the antireflection layer being directly formed on the surface passivation layer, when the antireflection layer is directly formed on the side of the second doped silicon layer away from the silicon substrate, the plating range of the antireflection layer on the backlight side can be reduced, thereby reducing the etching amount when removing the plating of the antireflection layer on the backlight side and improving the manufacturing efficiency. Optionally, the back contact battery further includes a surface passivation layer and an antireflection layer sequentially disposed on the light-receiving surface along the thickness direction of the silicon substrate, and the surface passivation layer and the antireflection layer extend from the light-receiving surface to the side surface. And on the side surface, and along the direction away from the side surface, the surface passivation layer and the antireflection layer are sequentially stacked between the second doped silicon layer and the transparent conductive layer. In this case, the presence of the surface passivation layer and the antireflection layer can further improve the protection effect on the side surface of the silicon substrate and reduce the risk of damage to the side surface of the silicon substrate. Optionally, a doped layer is formed in the side surface of the silicon substrate. The dopant in the doped layer includes the dopant in the first doped silicon layer. Optionally, the first interface passivation layer and the first doped silicon layer disposed on the side are only located on a partial area of the side and close to the backlight surface. Wherein, along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side to the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is a matte surface, and the ratio of the maximum extension length of the matte surface on the side to the thickness of the silicon substrate is less than or equal to 30%; and / or, the surface reflectivity of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the area covered by the first interface passivation layer and the first doped silicon layer; and / or, the surface of the area on the side that is not covered by the first interface passivation layer and the first doped silicon layer is a matte surface; and / or, the surface of the area on the side that is covered by the first interface passivation layer and the first doped silicon layer is a polished surface. Optionally, each part of the first interface passivation layer and / or the first doped silicon layer has the same thickness. Optionally, on the side of the silicon substrate, the thickness of the surface passivation layer is equal, or the thickness of the surface passivation layer gradually increases in the direction from the backlight surface to the light-receiving surface. Optionally, on the side of the silicon substrate, the thickness of the antireflection layer gradually increases in the direction from the backlight surface to the light-receiving surface. Optionally, on the side of the silicon substrate, the thickness of the second doped silicon layer and / or the transparent conductive layer gradually increases in the direction from the light-receiving surface to the backlight surface. Optionally, the surface passivation layer and the antireflection layer disposed on the side are located on a partial area of the side and close to the light-receiving surface; along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the surface passivation layer and the antireflection layer on the side to the thickness of the silicon substrate is less than or equal to 80%. Optionally, the material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Optionally, the thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm. Optionally, on the side of the silicon substrate, the surface of the area provided with the first interface passivation layer and the first doped silicon layer has a tower-base texture structure. And, the thickness of the first interface passivation layer located on the bottom surface of the tower-base texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower-base texture structure. Optionally, on the side of the silicon substrate, the surface of the area provided with the first interface passivation layer and the first doped silicon layer has a tower-base texture structure. And, the thickness of the first interface passivation layer located on the bottom surface of the tower-base texture structure is greater than the thickness of the first interface passivation layer located on the side wall of the tower-base texture structure. Optionally, the side surface of the silicon substrate has a tower base-like texture structure; wherein, the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower base-like texture structure; the thickness of the intrinsic silicon layer located at the bottom surface of the tower base-like texture structure is greater than the thickness of the intrinsic silicon layer located at the side wall of the tower base-like texture structure; and / or, the thickness of the second doped silicon layer located at the bottom surface of the tower base-like texture structure is greater than the thickness of the second doped silicon layer located at the side wall of the tower base-like texture structure. It should be understood that in the second aspect and the first aspect, the same or similar alternative solutions have the same or similar technical effects, which will not be elaborated here. In a third aspect, the present application provides a photovoltaic module, including the solar cell according to any one of the above. The additional aspects and advantages of the present application will be partly given in the following description, partly will become obvious from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, wherein: FIG. 1 is a schematic diagram of a solar cell according to an embodiment of the present application; FIG. 2 is a schematic diagram of a silicon substrate according to an embodiment of the present application; FIG. 3 is a schematic diagram of the structure at the edge of a solar cell according to an embodiment of the present application; FIG. 4 is a schematic diagram of the structure at the edge of another solar cell according to an embodiment of the present application; FIG. 5 is a schematic diagram of the structure at the edge of yet another solar cell according to an embodiment of the present application; FIG. 6 is a schematic diagram of the structure at the edge of yet another solar cell according to an embodiment of the present application; FIG. 7 is a partial side sectional view of a solar cell according to an embodiment of the present application; FIG. 8 is a schematic longitudinal sectional view of the structure of a back contact cell provided by an embodiment of the present application; FIG. 9 is a schematic longitudinal sectional view of the structure of a back contact cell provided by an embodiment of the present application; FIG. 10 is a schematic longitudinal sectional view of the structure of a back contact cell provided by an embodiment of the present application; FIG. 11 is a schematic longitudinal sectional view of the structure of a back contact cell provided by an embodiment of the present application; FIG. 12 is a schematic longitudinal sectional view of the structure of a back contact cell provided by an embodiment of the present application; FIG. 13 is a schematic longitudinal sectional view of the structure of a back contact cell provided by an embodiment of the present application; FIG. 14 is a schematic longitudinal sectional view of the structure of a back contact cell provided by an embodiment of the present application; FIG. 15 is the eighth longitudinal sectional view of the structure of the back-contact battery provided by the embodiment of the present application; FIG. 16 is the ninth longitudinal sectional view of the structure of the back-contact battery provided by the embodiment of the present application; FIG. 17 is the tenth longitudinal sectional view of the structure of the back-contact battery provided by the embodiment of the present application; FIG. 18 is the eleventh longitudinal sectional view of the structure of the back-contact battery provided by the embodiment of the present application. Reference numerals: 100 - silicon substrate; 110 - light-receiving surface; 120 - backlight surface; 120a - first region; 120b - second region; 130 - side surface; 130a - first position; 130b - second position; 200 - protective layer; 201 - first passivation layer; 202 - first conductive layer; 203 - insulating layer; 204 - second passivation layer; 205 - second conductive layer; 206 - third passivation layer; 207 - antireflection layer; 208 - transparent conductive layer; 12 - first doped silicon layer; 13 - surface passivation layer; 15 - intrinsic silicon layer; 16 - second doped silicon layer; 20 - first interface passivation layer; 21 - insulating mask layer; 22 - second interface passivation layer. Detailed implementation manners The following The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation to the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application. The terms "first" and "second" in the description and claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally means an "or" relationship between the associated objects before and after. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "mounted", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. Next, with reference to the accompanying drawings, the solar cell and photovoltaic module provided by the embodiments of the present application will be described in detail through specific embodiments and their application scenarios. In a first aspect, as shown in FIG. 1, FIG. 1 shows a schematic diagram of a solar cell according to an embodiment of the present application. The solar cell according to some embodiments of the present application includes: a silicon substrate 100; the silicon substrate 100 has opposite light-receiving surfaces 110 and backlight surfaces 120, and side surfaces 130 provided between the light-receiving surfaces 110 and the backlight surfaces 120; a protective layer 200 is provided on the side surfaces 130. As shown in FIG. 3, the protective layer 200 includes a first conductive layer 202, an insulating layer 203, and a second conductive layer 205 sequentially provided on the side surfaces 130; the conductive types of the first conductive layer 202 and the second conductive layer 205 are opposite. In the embodiment of the present application, by providing a protective layer 200 on the side surface 130 of the silicon substrate 100, the protective layer 200 includes a first conductive layer 202, an insulating layer 203, and a second conductive layer 205, and the insulating layer 203 is used to insulate and isolate between the first conductive layer 202 and the second conductive layer 205, so that there is no need to specifically remove the conductive layer formed by overplating on the side surface 130 of the silicon substrate 100 during the battery preparation process, which helps to simplify the production process of the battery. Moreover, the protective layer 200 can play a passivation protection role for the side surface 130 of the silicon substrate 100, which can not only avoid the risks of damage and leakage caused by the direct exposure of the side surface 130 of the silicon substrate 100, but also reduce the carrier recombination on the side surface 130 of the silicon substrate 100 and improve the conversion efficiency of the battery. Next, with reference to FIGS. 1 to 7, the structure and the like of the solar cell according to some embodiments of the present application will be described in detail. Specifically, as shown in FIG2 , FIG2 shows a schematic diagram of a silicon substrate of an embodiment of the present application. The silicon substrate 100 in the solar cell has a light-receiving surface 110 and a backlight surface 120 relative to each other, and a side surface 130 arranged around the silicon substrate 100. Among them, the light-receiving surface 110 is a side of the silicon substrate 100 that receives incident light, the backlight surface 120 is a side of the silicon substrate 100 that is away from the light-receiving surface 110, and the side surface 130 connects the light-receiving surface 110 and the backlight surface 120. Furthermore, a protective layer 200 is provided on the side surfaces 130 around the silicon substrate 100, so as to use the protective layer 200 to form shielding protection for the side surfaces 130 around the silicon substrate 100. It is understandable that in the solar cell manufacturing process, it is usually necessary to process and form a first conductive layer 202 and a second conductive layer 205 of different conductive types on the light-receiving surface 110 and / or the backlight surface 120 of the silicon substrate 100. In this process, a winding plating layer is inevitably formed on the side 130 of the silicon substrate 100. In order to avoid the leakage problem caused by the direct contact and conduction of the first conductive layer 202 and the second conductive layer 205 formed by the winding plating on the side 130, in the embodiment of the present application, an insulating layer 203 is provided between the first conductive layer 202 and the second conductive layer 205 on the side 130 to insulate and isolate the first conductive layer 202 and the second conductive layer 205. In this way, in the battery manufacturing process, there is no need to specifically remove the first conductive layer 202 and the second conductive layer 205 wound on the side 130, which can not only solve the leakage problem of the side 130 caused by the winding plating, but also simplify the processing technology. Furthermore, the protection layer 200 formed by the insulating layer 203 and the first conductive layer 202 and the second conductive layer 205 can also play a role in passivation protection of the side surface 130 , which helps to improve the battery performance. It should be noted that the insulating layer 203 disposed on the side surface 130 of the silicon substrate 100 in the embodiment of the present application can be prepared separately in the battery manufacturing process. It can also be based on the existing battery manufacturing process, in the process of preparing the film layer structure on the backlight surface 120 and / or the light-receiving surface 110 of the silicon substrate 100, the corresponding insulating layer 203 is formed on the surrounding side surfaces 130 of the silicon substrate 100 at the same time, and can be flexibly arranged according to actual conditions, and the embodiment of the present application is not limited to this. In some embodiments, the electrical properties of the first conductive layer 202 and the second conductive layer 205 are opposite. Among them, one of the first conductive layer 202 and the second conductive layer 205 can be set as: N-type amorphous silicon layer, N-type microcrystalline silicon layer, a mixed layer of N-type amorphous silicon and microcrystalline silicon, N-type transition metal compound layer, N-type polycrystalline silicon layer, etc. The other of the first conductive layer 202 and the second conductive layer 205 can be set as: P-type amorphous silicon, P-type microcrystalline silicon, a mixed layer of P-type amorphous silicon and microcrystalline silicon, P-type transition metal compound layer or P-type polycrystalline silicon layer, etc. In some embodiments, the insulating layer 203 can be made of materials such as silicon nitride, silicon oxide, silicon oxynitride, silicon carbide layer, etc. Of course, the insulating layer 203 can also be prepared from other materials, and the embodiments of the present application do not limit this. Optionally, as shown in FIG. 7, along the direction parallel to the backlight surface 120, the backlight surface 120 has alternately arranged first regions 120a and second regions 120b; a first conductive layer 202 is formed in the first region 120a, and a second conductive layer 205 is formed in the second region 120b. It can be understood that the solar cell structure in the embodiments of the present application can be applied to back-contact cells. For example, it can be applied to HBC cells. In a back-contact cell, both the PN junction and the metal grid lines are disposed on the backlight surface 120 of the cell. During the preparation process of the back-contact cell, it is necessary to deposit and form a first conductive layer 202 in the first region 120a of the backlight surface 120 of the silicon substrate 100, and deposit and form a second conductive layer 205 in the second region 120b. During this process, the side surface 130 of the silicon substrate 100 will be simultaneously plated with the first conductive layer 202 and the second conductive layer 205. By providing an insulating layer 203 between the first conductive layer 202 and the second conductive layer 205 on the side surface 130, it is possible to avoid the direct contact and conduction between the first conductive layer 202 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100, resulting in a leakage problem. At the same time, the protective layer 200 can also play a passivation and protection role for the side surface 130. In a specific application, the insulating layer 203 can be provided only on the side surface 130 of the silicon substrate 100; or the insulating layer 203 can be provided on both the side surface 130 and the backlight surface 120 of the silicon substrate 100. For example, an insulating layer 203 can also be provided between the first region 120a and the second region 120b, which can be flexibly set according to actual situations, and the present application does not limit this. Optionally, as shown in FIG. 3, the protective layer 200 further includes a first passivation layer 201 located between the side surface 130 of the silicon substrate 100 and the first conductive layer 202, and a second passivation layer 204 located between the insulating layer 203 and the second conductive layer 205; as shown in FIG. 7, along the direction parallel to the backlight surface 120, the backlight surface 120 has alternately arranged first regions 120a and second regions 120b; along the direction away from the silicon substrate 100, the first region 120a is sequentially formed with a first passivation layer 201 and a first conductive layer 202, and the second region 120b is sequentially formed with a second passivation layer 204 and a second conductive layer 205; an insulating layer 203 is provided between the first region 120a and the second region 120b. In an embodiment of the present application, by disposing a first passivation layer 201 between the silicon substrate 100 and the first conductive layer 202, and disposing a second passivation layer 204 between the insulating layer 203 and the second conductive layer 205, while forming an occlusion protection for the side surface 130 of the silicon substrate 100, the passivation effect of the entire protection layer 200 on the side surface 130 of the silicon substrate 100 can be further improved, thereby improving the conversion efficiency of the battery. Moreover, by making the film layer structure of the side surface 130 of the silicon substrate 100 adapt to the film layer structure of the backlight surface 120 of the silicon substrate 100, when forming the film layer structure on the backlight surface 120 of the silicon substrate 100 during the battery processing technology, a corresponding protection layer 200 can be simultaneously formed on the side surface 130 of the silicon substrate 100. In this way, the processing flow can be simplified and the processing efficiency can be improved. It can be understood that in the film layer structures of the backlight surface 120 and the side surface 130 of the silicon substrate 100, the same type of film layer structure can be formed by corresponding processes at one time. For example, the first passivation layer 201 can be simultaneously deposited on the backlight surface 120 and the side surface 130 of the silicon substrate 100 by using the PECVD process. Correspondingly, the first conductive layer 202 can also be further deposited on the surface of the first passivation layer 201 by using the PECVD process. In this way, the first passivation layer 201 and the first conductive layer 202 can be simultaneously processed on the backlight surface 120 and the side surface 130 of the silicon substrate 100. As shown in FIG. 7, FIG. 7 shows a partial side sectional view of the solar cell according to an embodiment of the present application; the backlight surface 120 of the silicon substrate 100 has alternating first regions 120a and second regions 120b. On the backlight surface of the silicon substrate 100 in the first region 120a, a first passivation layer 201 and a first conductive layer 202 are sequentially provided. On the backlight surface of the silicon substrate 100 in the second region 120b, a second passivation layer 204 and a second conductive layer 205 are sequentially provided, and an insulating layer 203 is disposed between the first region 120a and the second region 120b to perform insulation isolation on the first region 120a and the second region 120b. In a specific application, processing techniques such as PECVD process can be adopted to successively form a first passivation layer 201, a first conductive layer 202, and an insulating layer 203 on the backlight surface 120 and the peripheral side surfaces 130 of the silicon substrate 100. Further, a mask layer is provided on the surface of the insulating layer 203 of the backlight surface 120 of the silicon substrate 100. Through processes such as photolithography, laser, and etching, the film layer structure of the backlight surface 120 of the silicon substrate 100 is patterned to form a first region 120a and a second region 120b on the backlight surface 120, and the first passivation layer 201 and the first conductive layer 202 in the second region 120b are removed. Then, processing techniques such as PECVD process are adopted to form a second passivation layer 204 and a second conductive layer 205 in the second region 120b. At the same time, the second passivation layer 204 and the second conductive layer 205 are also formed on the peripheral side surfaces 130 of the silicon substrate 100. In this way, the protective layer 200 formed on the peripheral side surfaces 130 of the silicon substrate 100 can be adapted to the film layer structure of the backlight surface 120 of the silicon substrate 100, so as to realize the processing of the protective layer 200 on the side surfaces 130 of the silicon substrate 100 without increasing the processing procedures. Thus, it not only helps to simplify the processing flow of the battery but also can realize the shielding protection of the side surfaces 130 of the silicon substrate 100. It should be noted that the specific film layer structure on the backlight surface 120 of the silicon substrate 100 can be set according to actual needs, and the embodiments of the present application do not limit this here. In some other embodiments, the first passivation layer 201 and the second passivation layer 204 can be set as at least one of an amorphous silicon layer, a hydrogenated amorphous silicon layer, a carbon-doped amorphous silicon layer, and an intrinsic amorphous silicon layer. Of course, the specific structures and preparation materials of the first conductive layer 202, the second conductive layer 205, the first passivation layer 201, and the second passivation layer 204 can be flexibly selected according to the structural design of the solar cell, and the embodiments of the present application do not limit this. Optionally, as shown in FIG. 1, the junction of the side surface 130 and the backlight surface 120 is the first position 130a, and the junction of the side surface 130 and the light-receiving surface 110 is the second position 130b. The thickness of the protective layer 200 at the first position 130a is greater than the thickness of the protective layer 200 at the second position 130b. In the embodiments of the present application, by setting the thickness of the protective layer 200 on the side close to the backlight surface 120 of the silicon substrate 100 to be greater than the thickness on the side close to the light-receiving surface 110 of the silicon substrate 100, the protective effect on the side of the side surface 130 of the silicon substrate 100 close to the backlight surface 120 is strengthened. Generally, in a back contact cell, the P+ and N+ emitters, the back field, and the positive and negative electrodes are all arranged on the backlight surface 120 of the silicon substrate 100. Therefore, the surrounding side surfaces 130 of the silicon substrate 100 are at a greater risk of leakage on the side close to the backlight surface 120. Therefore, in the embodiment of the present application, the protective layer 200 of the side surface 130 of the silicon substrate 100 is arranged to have a thickness greater on the side close to the backlight surface 120 than on the side close to the light receiving surface 110, so as to increase the protective effect of the protective layer 200 on the side of the silicon substrate 100 close to the backlight surface 120. Optionally, as shown in FIG. 1 , the thickness of the protective layer 200 at the first position 130 a is D1 , and the thickness of the protective layer 200 at the second position 130 b is D2 , satisfying: 1<D1 / D2≤10; optionally, 2.5≤D1 / D2≤10. In the embodiment of the present application, a reasonable value range of the ratio D1 / D2 between the thickness D1 of the protective layer 200 at the first position 130a and the thickness D2 of the protective layer 200 at the second position 130b of the side surface 130 of the silicon substrate 100 is set, so that the thickness of the protective layer 200 at different positions of the side surface 130 of the silicon substrate 100 is different. In this way, effective shielding protection can be formed for the entire side surface 130 of the silicon substrate 100, and the material consumption required for preparing the protective layer 200 can be appropriately reduced. Exemplarily, the ratio D1 / D2 of the total thickness D1 of the protective layer 200 at the first position 130a to the total thickness D2 of the protective layer 200 at the second position 130b can be set to any value such as 1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 8, 9, 10, or a range between any two values. The thickness of the protective layer 200 on the side 130 of the silicon substrate 100 refers to the straight-line distance between the side of the protective layer 200 facing the silicon substrate 100 and the side of the protective layer 200 facing away from the silicon substrate 100 along a direction perpendicular to the side 130 of the silicon substrate 100 . Optionally, as shown in Figure 3, the total thickness of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 is H1, the total thickness of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side 130 is H11, and the total thickness of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side 130 is H12, satisfying: H12<H11≤H1. In the embodiment of the present application, by setting the total thickness of the first passivation layer 201 and the first conductive layer 202 on the side surface 130 of the silicon substrate 100 to be less than or equal to the total thickness of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, while satisfying the formation of an occlusion protection for the side surface 130 of the silicon substrate 100, the material loss required for preparing the first passivation layer 201 and the first conductive layer 202 can be reduced. Moreover, by setting the first passivation layer 201 and the first conductive layer 202 on the side surface 130 of the silicon substrate 100, the total thickness H11 at the first position 130a is greater than the total thickness H12 at the second position 130b, thereby strengthening the protection effect on the side of the side surface 130 of the silicon substrate 100 close to the backlight surface 120. It can be understood that the first passivation layer 201 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 in the embodiment of the present application can be processed by a one-step forming process. For example, a PECVD process can be used to simultaneously deposit and form the first passivation layer 201 on the backlight surface 120 and the side surface 130 of the silicon substrate 100. Similarly, a one-step forming process can also be used to process the first conductive layer 202 on the surface of the first passivation layer 201 on the backlight surface 120 and the side surface 130 of the silicon substrate 100, so that the first conductive layer 202 covers the surface of the first passivation layer 201. It should be noted that the preparation method of the first passivation layer 201 and the first conductive layer 202 can adopt a PECVD process or other preparation processes, and the embodiment of the present application does not limit this. Optionally, the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 and the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 satisfy: 0.2 ≤ H12 / H11 < 1. By setting a reasonable value range of H12 / H11, the side surface of the silicon substrate 100 can be occluded and protected by the first passivation layer 201 and the first conductive layer 202, and at the same time, the protection effect on the side of the side surface 130 of the silicon substrate 100 close to the backlight surface 120 can be strengthened. Specifically, the ratio H12 / H11 of the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 to the total thickness H11 at the first position 130a can be set to any number such as 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or the range between any two values. Optionally, as shown in FIG. 3, the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 and the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 satisfy: 0.5 ≤ H11 / H1 ≤ 1. In the embodiment of the present application, by setting the reasonable value range of the ratio H11 / H1 of the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 of the silicon substrate 100 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, the structure of the first passivation layer 201 and the first conductive layer 202 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, thereby realizing the passivation protection effect on the side surface 130 of the silicon substrate 100, reducing the carrier recombination on the side surface 130, and also being able to reduce the material loss of preparing the first passivation layer 201 and the first conductive layer 202, and reducing the production cost. Exemplarily, the ratio H11 / H1 of the total thickness H11 of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1 or the range between any two numerical values. Optionally, as shown in FIG. 3, the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 and the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 satisfy: 0.2 ≤ H12 / H1 ≤ 0.6. In the embodiment of the present application, by setting the reasonable value range of the ratio H12 / H1 of the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 of the silicon substrate 100 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, the structure of the first passivation layer 201 and the first conductive layer 202 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100, thereby realizing the passivation protection effect on the side surface 130 of the silicon substrate 100, and also being able to reduce the material loss of preparing the first passivation layer 201 and the first conductive layer 202, and reducing the production cost. Exemplarily, the ratio H12 / H1 of the total thickness H12 of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 to the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6 or a range between any two numerical values. It should be noted that the total thickness H1 of the first passivation layer 201 and the first conductive layer 202 on the backlight surface 120 of the silicon substrate 100 refers to the total thickness dimension of the first passivation layer 201 and the first conductive layer 202 located on the backlight surface 120 of the silicon substrate 100 along the direction perpendicular to the backlight surface 120. The total thickness of the first passivation layer 201 and the first conductive layer 202 on the side surface 130 of the silicon substrate 100 refers to the total thickness dimension of the first passivation layer 201 and the first conductive layer 202 located on the side surface 130 of the silicon substrate 100 along the direction perpendicular to the side surface 130. Optionally, as shown in FIG. 3, the thickness of the insulating layer 203 on the backlight surface 120 is H2, the thickness of the insulating layer 203 at the first position 130a on the side surface 130 is H21, and the thickness of the insulating layer 203 at the second position 130b on the side surface 130 is H22, satisfying: H22 < H21 ≤ H2. In the embodiment of the present application, by setting the thickness of the insulating layer 203 on the side surface 130 of the silicon substrate 100 to be less than or equal to the thickness of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, while forming an occlusion protection for the side surface 130 of the silicon substrate 100 by using the insulating layer 203, the material loss for preparing the insulating layer 203 is reduced. Moreover, by setting the insulating layer 203 on the side surface 130 of the silicon substrate 100, the thickness H21 at the first position 130a is greater than the thickness H22 at the second position 130b, thereby strengthening the protection effect on the side surface 130 of the silicon substrate 100 near the backlight surface 120 side. It can be understood that the insulating layer 203 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 in the embodiment of the present application can be processed by a one-step forming process. For example, a PECVD process can be used to deposit and form the insulating layer 203 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 simultaneously. It should be noted that the specific preparation method of the insulating layer 203 can be flexibly set according to the actual situation, and the embodiment of the present application does not limit this. Optionally, the thickness H21 of the insulating layer 203 at the first position 130a on the side surface 130 and the thickness H22 of the insulating layer 203 at the second position 130b on the side surface 130 satisfy: 0.2 ≤ H22 / H21 < 1. In an embodiment of the present application, by setting a reasonable value range of H22 / H21, the insulating layer 203 is utilized to play an insulating and isolating role between the first conductive layer 202 and the second conductive layer 205 on the side surface 130. Furthermore, the insulating layer 203, the first conductive layer 202, and the second conductive layer 205 form a protective layer to form an occlusion protection for the side surface 130 of the silicon substrate 100. At the same time, the protection effect on the side surface 130 of the silicon substrate 100 close to the backlight surface 120 can also be enhanced. Specifically, for the insulating layer 203 on the side surface 130, the ratio H22 / H21 of the thickness H22 at the second position 130b to the thickness H21 at the first position 130a can be set to any number such as 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or the range between any two values. Optionally, as shown in Figure 3, the thickness H2 of the insulating layer 203 on the backlight surface 120 and the thickness H21 of the insulating layer 203 on the side surface 130 at the first position 130a satisfy: 0.5 ≤ H21 / H2 ≤ 1. In an embodiment of the present application, by setting a reasonable value range of the ratio H21 / H2 of the thickness H21 of the insulating layer 203 at the first position 130a on the side surface 130 of the silicon substrate 100 to the thickness H2 of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, the structure of the insulating layer 203 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, thereby facilitating actual processing and forming. At the same time, the insulating layer 203, the first conductive layer 202, and the second conductive layer 205 form a protective layer 200 to form an occlusion protection for the side surface 130 of the silicon substrate 100, and the material loss required for preparing the insulating layer 203 can also be reduced, thus lowering the production cost. Exemplarily, the ratio H21 / H2 of the thickness H21 of the insulating layer 203 at the first position 130a on the side surface 130 to the thickness H2 of the insulating layer 203 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1 or the range between any two values. Optionally, as shown in Figure 3, the thickness H2 of the insulating layer 203 on the backlight surface 120 and the total thickness H22 of the insulating layer 203 on the side surface 130 at the second position 130b satisfy: 0.2 ≤ H22 / H2 ≤ 0.6. In an embodiment of the present application, by setting a reasonable value range for the ratio H22 / H2 of the thickness H22 of the insulating layer 203 on the side surface 130 of the silicon substrate 100 at the second position 130b to the thickness H2 of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, the structure of the insulating layer 203 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100, thereby facilitating actual processing and forming. At the same time, the insulating layer 203, the first conductive layer 202, and the second conductive layer 205 are used to form a protective layer 200 to form an occlusion protection effect on the side surface 130 of the silicon substrate 100, and can also reduce the material loss required for preparing the insulating layer 203 and lower the production cost. Exemplarily, the ratio H22 / H2 of the total thickness H22 of the insulating layer 203 on the side surface 130 at the second position 130b to the thickness H2 of the insulating layer 203 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6 or a range between any two values. It should be noted that the thickness H2 of the insulating layer 203 on the backlight surface 120 of the silicon substrate 100 refers to the thickness dimension of the insulating layer 203 on the backlight surface 120 along the direction perpendicular to the backlight surface 120. The thickness of the insulating layer 203 on the side surface 130 of the silicon substrate 100 refers to the thickness dimension of the insulating layer 203 on the side surface 130 along the direction perpendicular to the side surface 130. Optionally, as shown in FIG. 3, the total thickness of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 is H3, the total thickness of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 at the first position 130a is H31, and the total thickness of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 at the second position 130b is H32, satisfying: H32 < H31 ≤ H3. In an embodiment of the present application, by setting the total thickness of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100 to be less than or equal to the total thickness of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100, while satisfying the occlusion protection of the side surface 130 of the silicon substrate 100, the material loss for preparing the second passivation layer 204 and the second conductive layer 205 is reduced. And, by setting the second passivation layer 204 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100, the total thickness H31 at the first position 130a is greater than the total thickness H32 at the second position 130b, thereby strengthening the protection effect on the side of the side surface 130 of the silicon substrate 100 close to the backlight surface 120. It can be understood that the second passivation layer 204 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 in the embodiments of the present application can be processed by a one-step forming process. For example, the PECVD process can be first used to simultaneously deposit the second passivation layer 204 on the backlight surface 120 and the side surface 130 of the silicon substrate 100. Similarly, the second conductive layer 205 can also be further processed on the surface of the second passivation layer 204 by a one-step forming process, so that the second conductive layer 205 covers the surface of the second passivation layer 204. It should be noted that the preparation methods of the second passivation layer 204 and the second conductive layer 205 can adopt the PECVD process or other preparation processes. The embodiments of the present application do not limit this. Optionally, the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side surface 130 and the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side surface 130 satisfy: 0.2 ≤ H32 / H31 < 1. By setting a reasonable value range of H32 / H31, while using the second passivation layer 204 and the second conductive layer 205 to form passivation protection on the side surface 130 of the silicon substrate 100, the protection effect on the side surface 130 of the silicon substrate 100 near the backlight surface 120 can be strengthened. Specifically, the ratio H32 / H31 of the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b to the total thickness H31 at the first position 130a on the side surface 130 can be set to any number such as 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or the range between any two values. Optionally, as shown in Figure 3, the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 and the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side surface 130 satisfy: 0.5 ≤ H31 / H3 ≤ 1. In the embodiments of the present application, by setting a reasonable value range of the ratio H31 / H3 of the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side surface 130 of the silicon substrate 100 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120, the structure of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100, so as to play a passivation protection role on the side surface 130 of the silicon substrate 100, and can also reduce the material loss of preparing the second passivation layer 204 and the second conductive layer 205 and reduce the production cost. Exemplarily, the ratio H31 / H3 of the total thickness H31 of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side surface 130 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1 or a range between any two values. Optionally, as shown in FIG. 3, the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 and the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side surface 130 satisfy: 0.2 ≤ H32 / H3 ≤ 0.6. In the embodiment of the present application, by setting a reasonable value range of the ratio H32 / H3 of the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side surface 130 of the silicon substrate 100 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100, the structure of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100. To play a passivation protection role on the side surface 130 of the silicon substrate 100, and can also reduce the material loss of preparing the second passivation layer 204 and the second conductive layer 205, and reduce the production cost. Exemplarily, the ratio of the total thickness H32 of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side surface 130 to the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6 or a range between any two values. It should be noted that the total thickness H3 of the second passivation layer 204 and the second conductive layer 205 on the backlight surface 120 of the silicon substrate 100 refers to the total thickness dimension of the second passivation layer 204 and the second conductive layer 205 located on the backlight surface 120 along the direction perpendicular to the backlight surface 120. The total thickness of the second passivation layer 204 and the second conductive layer 205 on the side surface 130 of the silicon substrate 100 refers to the total thickness dimension of the second passivation layer 204 and the second conductive layer 205 located on the side surface 130 along the direction perpendicular to the side surface 130. Optionally, as shown in FIG. 4, FIG. 4 shows another schematic diagram of the edge of the solar cell according to an embodiment of the present application; the protective layer 200 further includes a third passivation layer 206 and an antireflection layer 207. The third passivation layer 206 is disposed on a side of the second conductive layer 205 away from the side surface 130, and the antireflection layer 207 is disposed on a side of the third passivation layer 206 away from the second conductive layer 205; along the direction away from the silicon substrate 100, the third passivation layer 206 and the antireflection layer 207 are sequentially formed on the light-receiving surface 110. In the embodiment of the present application, by providing that the third passivation layer 206 and the antireflection layer 207 are both formed on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100, while meeting the structural design requirements of the light-receiving surface 110 of the silicon substrate 100, the third passivation layer 206 and the antireflection layer 207 are correspondingly formed on the side surface 130 of the silicon substrate 100, thereby enhancing the shielding and protection effect on the side surface 130 of the silicon substrate 100. It can be understood that the third passivation layer 206 on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100 can be processed by a one-step forming process. For example, the PECVD process can be used to simultaneously deposit and form the third passivation layer 206 on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100. Similarly, a one-step forming process can also be used to process the antireflection layer 207 on the surface of the third passivation layer 206 on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100, so that the antireflection layer 207 covers the surface of the third passivation layer 206. In some embodiments, the third passivation layer 206 can be set as at least one of an amorphous silicon layer, a hydrogenated amorphous silicon layer, a carbon-doped amorphous silicon layer, and an intrinsic amorphous silicon layer. The antireflection layer 207 can be made of one or more of silicon oxide, titanium oxide, silicon nitride, and silicon carbide. It should be noted that the materials and specific preparation processes of the third passivation layer 206 and the antireflection layer 207 can be flexibly set according to actual needs, and the embodiments of the present application do not limit this. Optionally, as shown in FIG. 4, the total thickness of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 is H4, the total thickness of the third passivation layer 206 and the antireflection layer 207 at the first position 130a on the side surface 130 is H41, and the total thickness of the third passivation layer 206 and the antireflection layer 207 at the second position 130b on the side surface 130 is H42, satisfying: H41 < H42 ≤ H4. In an embodiment of the present application, by setting the total thickness of the third passivation layer 206 and the antireflection layer 207 on the side surface 130 of the silicon substrate 100 to be less than or equal to the total thickness of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 of the silicon substrate 100, while not affecting the battery conversion efficiency, the side surface 130 of the silicon substrate 100 can be shielded and protected by the third passivation layer 206 and the antireflection layer 207. Moreover, by setting the total thickness H42 of the third passivation layer 206 and the antireflection layer 207 on the second position 130b of the side surface 130 of the silicon substrate 100 to be greater than the total thickness H41 on the first position 130a, a smooth transition in size can be formed at the junction area between the edge of the light-receiving surface 110 and the side surface 130 of the silicon substrate 100 by the third passivation layer 206 and the antireflection layer 207, so as to enhance the protection effect on the edge of the silicon substrate 100. Optionally, the total thickness H41 of the third passivation layer 206 and the antireflection layer 207 on the first position 130a of the side surface 130 and the total thickness H42 of the third passivation layer 206 and the antireflection layer 207 on the second position 130b of the side surface 130 satisfy: 0.1 ≤ H42 / H41 < 1. By setting a reasonable value range of H42 / H41, the side surface 130 of the silicon substrate 100 can be shielded and protected by the third passivation layer 206 and the antireflection layer 207, and meanwhile, it is convenient for actual processing and shaping. Specifically, the ratio H42 / H41 of the total thickness H42 of the third passivation layer 206 and the antireflection layer 207 on the second position 130b to the total thickness H41 of the third passivation layer 206 and the antireflection layer 207 on the first position 130a of the side surface 130 can be set to any number such as 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or a range between any two numerical values. Optionally, as shown in FIG. 4, the total thickness H4 of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 and the total thickness H41 of the third passivation layer 206 and the antireflection layer 207 on the first position 130a of the side surface 130 satisfy: 0.1 ≤ H41 / H4 ≤ 0.4. In an embodiment of the present application, by setting a reasonable value range of the ratio H41 / H4 of the total thickness H41 of the third passivation layer 206 and the antireflection layer 207 at the first position 130a on the side surface 130 of the silicon substrate 100 to the total thickness H4 of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 of the silicon substrate 100, the structure of the third passivation layer 206 and the antireflection layer 207 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 of the silicon substrate 100. Furthermore, the third passivation layer 206 and the antireflection layer 207 form a further shielding and protective effect on the side surface 130 of the silicon substrate 100, and can also reduce the material loss in preparing the third passivation layer 206 and the antireflection layer 207, thereby reducing the production cost. Exemplarily, the ratio of the total thickness H41 of the third passivation layer 206 and the antireflection layer 207 at the first position 130a on the side surface 130 to the total thickness H4 of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 can be set to any number such as 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4 or a range between any two values. Optionally, as shown in FIG. 4, the total thickness H4 of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 and the total thickness H42 of the third passivation layer 206 and the antireflection layer 207 at the second position 130b on the side surface 130 satisfy: 0.5 ≤ H42 / H4 ≤ 0.8. In an embodiment of the present application, by setting a reasonable value range of the ratio H42 / H4 of the total thickness H42 of the third passivation layer 206 and the antireflection layer 207 at the second position 130b on the side surface 130 of the silicon substrate 100 to the total thickness H4 of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 of the silicon substrate 100, the structure of the third passivation layer 206 and the antireflection layer 207 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 of the silicon substrate 100. Furthermore, the third passivation layer 206 and the antireflection layer 207 form a further shielding and protective effect on the side surface 130 of the silicon substrate 100, and can also reduce the material loss in preparing the third passivation layer 206 and the antireflection layer 207, thereby reducing the production cost. Exemplarily, the ratio H42 / H4 of the total thickness H42 of the third passivation layer 206 and the antireflection layer 207 at the second position 130b on the side surface 130 to the total thickness H4 of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8 or a range between any two values. It should be noted that the total thickness H4 of the third passivation layer 206 and the antireflection layer 207 on the light-receiving surface 110 of the silicon substrate 100 refers to the total thickness dimension of the third passivation layer 206 and the antireflection layer 207 located on the light-receiving surface 110 along the direction perpendicular to the light-receiving surface 110. The total thickness of the third passivation layer 206 and the antireflection layer 207 on the side surface 130 of the silicon substrate 100 refers to the total thickness dimension of the third passivation layer 206 and the antireflection layer 207 on the side surface 130 along the direction perpendicular to the side surface 130. Optionally, as shown in FIGS. 7 and 8, FIGS. 7 and 8 show a schematic structural diagram of the edge of another solar cell. The protective layer 200 further includes: a transparent conductive layer 208, which is disposed on the side of the antireflection layer 207 away from the side surface 130; the transparent conductive layer 208 is disposed in at least one of the first region 120a and the second region 120b, and the transparent conductive layer 208 is disposed on the side of the first conductive layer 202 and / or the second conductive layer 205 away from the backlight surface 120. In the embodiment of the present application, by disposing the transparent conductive layer 208 on both the backlight surface 120 and the side surface 130 of the silicon substrate 100, while meeting the structural design requirements of the backlight surface 120 of the silicon substrate 100, a transparent conductive layer 208 is correspondingly formed on the side surface 130 of the silicon substrate 100, thereby further enhancing the shielding and protection effect on the side surface 130 of the silicon substrate 100. Among them, the transparent conductive layer 208 on the backlight surface 120 and the side surface 130 of the silicon substrate 100 can be prepared by the same process. For example, the transparent conductive layer 208 can be deposited on the backlight surface 120 and the side surface 130 of the silicon substrate 100 simultaneously by using the PECVD process. Of course, the transparent conductive layer 208 can also be prepared by other processing techniques, and the embodiments of the present application do not limit this. Exemplarily, the transparent conductive layer 208 can be made of materials such as indium tin oxide, conductive polymer, fluorine-doped tin dioxide, aluminum-doped zinc oxide, etc., or can be made of other types of transparent conductive materials, and can be flexibly selected according to actual needs. The embodiments of the present application do not limit this. Optionally, as shown in FIG. 6, the thickness of the transparent conductive layer 208 located on the backlight surface 120 is H5, the thickness of the transparent conductive layer 208 located at the first position 130a on the side surface 130 is H51, and the thickness of the transparent conductive layer 208 located at the second position 130b on the side surface 130 is H52, satisfying: H52 < H51 ≤ H5. In an embodiment of the present application, by setting the thickness of the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 to be less than or equal to the thickness of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100, while not affecting the battery conversion efficiency, the side surface 130 of the silicon substrate 100 can be shielded and protected by the transparent conductive layer 208. Moreover, by setting the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 to have a thickness H51 at the first position 130a greater than the thickness H52 at the second position 130b, the protection effect on the side surface 130 of the silicon substrate 100 near the backlight surface 120 is strengthened. At the same time, the transparent conductive layer 208 is made to form a smooth transition in size at the junction region between the edge of the backlight surface 120 and the side surface 130, so as to enhance the protection effect on the edge of the silicon substrate 100. Optionally, the thickness H51 of the transparent conductive layer 208 on the side surface 130 at the first position 130a and the thickness H52 of the transparent conductive layer 208 on the side surface 130 at the second position 130b satisfy: 0.3 ≤ H52 / H51 < 1. By setting the ratio of H52 / H51, the side surface 130 of the silicon substrate 100 can be shielded and protected by the transparent conductive layer 208, and at the same time, it is convenient for actual processing and forming. Specifically, the ratio H52 / H51 of the thickness H52 of the transparent conductive layer 208 on the side surface 130 at the second position 130b to the thickness H51 at the first position 130a can be set to any number such as 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 0.95 or the range between any two numerical values. Optionally, as shown in FIG. 6, the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 and the thickness H51 of the transparent conductive layer 208 on the side surface 130 at the first position 130a satisfy: 0.5 ≤ H51 / H5 ≤ 1. In an embodiment of the present application, by setting a reasonable value range of the ratio H51 / H5 of the thickness H51 of the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 at the first position 130a to the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100, the structure of the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100. Furthermore, not only can the side surface 130 of the silicon substrate 100 be further shielded and protected by the transparent conductive layer 208, but also the material loss of preparing the transparent conductive layer 208 can be reduced, and the production cost can be lowered. Exemplarily, the ratio H51 / H5 of the thickness H51 of the transparent conductive layer 208 at the first position 130a on the side surface 130 to the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 can be set to any number such as 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1 or a range between any two values. Optionally, as shown in FIG. 6, the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 and the thickness H52 of the transparent conductive layer 208 at the second position 130b on the side surface 130 satisfy: 0.2 ≤ H52 / H5 ≤ 0.5. In the embodiment of the present application, by setting a reasonable value range of the ratio H52 / H5 of the thickness H52 of the transparent conductive layer 208 at the second position 130b on the side surface 130 of the silicon substrate 100 to the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100, the structure of the transparent conductive layer 208 on the side surface 130 of the silicon substrate 100 can be reasonably set according to the structure of the transparent conductive layer 208 on the backlight surface 120 of the silicon substrate 100. Furthermore, the side surface 130 of the silicon substrate 100 can be shielded and protected by the transparent conductive layer 208, and the material loss of preparing the transparent conductive layer 208 can be reduced, and the production cost can be lowered. Exemplarily, the ratio H52 / H5 of the thickness H52 of the transparent conductive layer 208 at the second position 130b on the side surface 130 to the thickness H5 of the transparent conductive layer 208 on the backlight surface 120 can be set to any number such as 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5 or a range between any two values. In some embodiments, electrodes are further provided in the first region and the second region on the backlight surface 120 of the silicon substrate 100 respectively. For the specific structure of the electrodes, reference can be made to the related art, and the embodiments of the present application will not elaborate herein. In some embodiments, the preparation process of the solar cell in the embodiment of the present application includes: Step 1: Polish and clean the silicon substrate 100. The silicon substrate 100 includes a light-receiving surface 110, a backlight surface 120, and a side surface 130 provided between the light-receiving surface 110 and the backlight surface 120. Among them, the backlight surface 120 has an alternately arranged first region 120a and second region 120b. Step 2: Deposit a first passivation layer 201, a first conductive layer 202, and an insulating layer 203 in sequence on the entire backlight surface 120 and the side surface 130 of the silicon substrate 100. Among them, the thickness range of the first passivation layer 201 is 4 - 200 nm, the thickness range of the first conductive layer 202 is 4 - 300 nm, and the thickness range of the insulating layer 203 is 30 - 300 nm. The deposition method can adopt processes such as PECVD and LPCVD, which are not limited herein. Step 3: Use a laser to remove the insulating layer 203 in the second region 120b on the backlight surface 120 of the silicon substrate 100 to form an opening. The laser wavelength used can be 355 nm, 532 nm, 1064 nm, etc. Step 4: Use an alkaline solution for etching to remove the first passivation layer 201 and the first conductive layer 202 at the opening, exposing the silicon substrate 100 in the second region 120b; at the same time, texture and clean the silicon substrate 100 at the opening and the light-receiving surface 110 of the silicon substrate 100. Among them, the alkaline etching solution used can be an alkaline solution such as NaOH and KOH. Step 5: Deposit a second passivation layer 204 and a second conductive layer 205 in sequence on the entire backlight surface 120 and the side surface 130 of the silicon substrate 100. Among them, the thickness range of the second passivation layer 204 is 4 - 200 nm, and the thickness range of the second conductive layer 205 is 5 - 300 nm. The deposition method can adopt processes such as PECVD and LPCVD, which are not limited herein. Step 6: Use a laser to remove the second passivation layer 204 and the second conductive layer 205 covering the first region 120a. The laser wavelength used can be 355 nm, 532 nm, 1064 nm, etc. Step 7: Use a wet process to etch the insulating layer 203 in the first region 120a. Step 8: Deposit a third passivation layer 206 and an antireflection layer 207 in sequence on the light-receiving surface 110 and the side surface 130 of the silicon substrate 100. Among them, the thickness range of the third passivation layer 206 is 4 - 200 nm, and the thickness of the antireflection layer 207 is 5 - 300 nm. The deposition method can adopt processes such as PECVD and LPCVD, which are not limited herein. Step 9: Deposit a transparent conductive layer in the first region 120a and the second region 120b on the backlight surface 120 of the silicon substrate 100. Among them, the thickness range of the transparent conductive layer is 10 - 300 nm, and the deposition method can adopt processes such as PVD and RPD processes. Step 10: Use a screen printing process to prepare metal electrodes in the first region 120a and the second region 120b. In some other instances, referring to the above preparation process, by adjusting the process parameters during the preparation, the thickness of the film layer structure deposited on the side surface 130 of the silicon substrate 100 is controlled, and then solar cells with different structures are prepared, and performance tests such as open-circuit voltage, short-circuit current, and conversion efficiency are carried out on the corresponding solar cells. Among them, in Comparative Example 1, a film layer structure is only deposited on the backlight surface 120 and the light-receiving surface 110 of the silicon substrate 100, and the bypass plating layer existing on the side surface 130 of the silicon substrate 100 is removed during the preparation process to expose the side surface 130 of the silicon substrate 100. In Examples 1 to 3, and Comparative Examples 2 to 4, while forming a film layer on the backlight surface 120 and the light-receiving surface 110 of the silicon substrate 100, a corresponding film layer structure is formed on the side surface 130 of the silicon substrate 100, and the difference lies in the different total thicknesses of the film layer structures formed on the side surface 130 of the silicon substrate 100. In addition, for the convenience of comparative analysis, based on the performance data results of Comparative Example 1, proportional conversion is performed on the test data of other groups, and the specific test results are shown in Table 1 below: Table 1 It can be seen from the test data in Table 1 that compared with directly exposing the side surface 130 of the silicon substrate 100, by forming a corresponding film layer structure on the side surface 130 of the silicon substrate 100, a shielding and protection effect can be formed on the side surface 130 of the silicon substrate 100, thereby avoiding the risks of damage and leakage on the side surface 130 of the silicon substrate 100. And when forming a film layer structure on the side surface 130, by reasonably setting the thickness of the film layer structure on the side surface 130 of the silicon substrate 100, the passivation effect on the side surface 130 of the silicon substrate 100 can be realized, and then the recombination of carriers on the side surface 130 can be reduced, improving the performance of the solar cell. Furthermore, by controlling the thickness D1 of the film layer structure on the side surface 130 of the silicon substrate 100 at the first position 130a (i.e., the side closer to the backlight surface 120) and the thickness D2 at the second position 130b (i.e., the side closer to the light-receiving surface 110) within a certain range, passivation protection is carried out on the side surface 130 of the silicon substrate 100, and then the recombination of carriers on the side surface 130 is reduced. Since the thickness of the protective layer 200 on the side surface 130 generally does not exceed the sum of the thicknesses of the film layers on the backlight surface 120 and the light-receiving surface 110, that is, the thickness of the protective layer 200 on the side surface 130 is within a relatively fixed range. If the ratio of D1 / D2 is too large, the value of D1 is too small, it is difficult to form reliable shielding protection for the part of the side surface 130 of the silicon substrate 100 close to the light-receiving surface 110, and the passivation effect of the part of the side surface 130 close to the light-receiving surface 110 is poor, reducing the overall performance of the solar cell. To this end, in the embodiments of the present application, by setting the ratio range of the thickness D1 of the protective layer 200 on the side surface 130 at the first position 130a to the thickness D2 at the second position 130b to be: 1 < D1 / D2 ≤ 10, in this way, not only can the protection effect on the side surface 130 of the silicon substrate 100 be improved, but also the performance of the solar cell can be appropriately improved. Next, with reference to FIGS. 8 to 14, the structure and the like of the solar cell according to some other embodiments of the first aspect of the present application will be described in detail. In the solar cell shown in FIGS. 8 to 14, the solar cell is a back-contact cell; the first conductive layer 202 is the first doped silicon layer 12, the second conductive layer 205 is the second doped silicon layer 16, and the insulating layer 203 includes a surface passivation layer 13 and an antireflection layer 207. As shown in FIG. 8, the back-contact cell provided by the embodiment of the present application includes: a silicon substrate 100, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an antireflection layer 207, an intrinsic silicon layer 15, a second doped silicon layer 16, and a transparent conductive layer 208. The silicon substrate 100 includes a backlight surface and a light-receiving surface arranged oppositely, and a side surface connecting the backlight surface and the light-receiving surface. Along the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the surface passivation layer 13, the antireflection layer 207, the intrinsic silicon layer 15, the second doped silicon layer 16, and the transparent conductive layer 208 are sequentially arranged on the side surface. The conduction types of the first doped silicon layer 12 and the second doped silicon layer 16 are opposite. Among them, along the thickness direction of the silicon substrate 100, the surface passivation layer 13 and the antireflection layer 207 are also sequentially arranged on the light-receiving surface, and the surface passivation layer 13 and the antireflection layer 207 extend from the light-receiving surface to the side surface. It can be understood that in this part, the first interface passivation layer 20 can also be referred to as the aforementioned first passivation layer 201, the intrinsic silicon layer 15 can also be referred to as the aforementioned second passivation layer 204, and "along the direction away from the side surface" is also "along the direction away from the silicon substrate". In the case of adopting the above technical solution, as shown in FIG. 8, on the side surface of the silicon substrate 100 and in the direction away from the side surface, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an antireflection layer 207, an intrinsic silicon layer 15, a second doped silicon layer 16, and a transparent conductive layer 208 are sequentially arranged. The existence of each film layer can isolate the side surface of the silicon substrate 100 from the external environment, reducing the risk of damage such as scratches on the side surface of the silicon substrate 100 due to factors such as extrusion and collision during transportation or packaging. At the same time, it can also reduce the risk of water vapor and the like entering the battery from the side of the battery and causing battery failure, improving the service life of the back contact battery. In addition, the surface passivation layer 13 and the antireflection layer 207 are not only located on the light-receiving surface of the silicon substrate 100 but also extend to the side surface of the silicon substrate 100. At this time, on the side surface of the silicon substrate 100, the first doped silicon layer 12 and the second doped silicon layer 16 with opposite conduction types can be isolated by the surface passivation layer 13 and the antireflection layer 207, preventing the two from conducting and leaking electricity, reducing the forward leakage loss, and enabling the back contact battery to have a high conversion efficiency. In addition, the part of the surface passivation layer 13 and the antireflection layer 207 arranged on the light-receiving surface can reduce the carrier recombination and the surface reflectivity. Extending the two to the side surface of the silicon substrate 100 can also be used to isolate the first doped silicon layer 12 and the second doped silicon layer 16, and there is no need to additionally form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer 12 and the second doped silicon layer 16, which can simplify the manufacturing process of the back contact battery. At the same time, there is no need to consider the compatibility between the film layer for isolating the first doped silicon layer 12 and the second doped silicon layer 16 and other structures in the back contact battery, ensuring that the back contact battery has a high yield. At the same time, not only the first interface passivation layer 20 and the first doped silicon layer 12 arranged on the side surface of the silicon substrate 100 have a passivation effect on the silicon substrate 100, but the surface passivation layer 13 that realizes the insulation and isolation of the first doped silicon layer 12 and the second doped silicon layer 16 on the side surface can also passivate the side surface of the silicon substrate 100, further reducing the carrier recombination rate on the side surface of the silicon substrate 100 and improving the conversion efficiency of the back contact battery. In addition, it is worth noting that in the actual manufacturing process, the formation sequence of the corresponding film layers arranged on the backlight surface and the light-receiving surface of the silicon substrate affects the formation sequence of the corresponding film layers on the side surface of the silicon substrate. Since the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate is closely related to processes, battery structures, equipment, etc., the formation sequence of the film layers on the backlight surface and the light-receiving surface of the silicon substrate cannot be arbitrarily adjusted. That is to say, the formation sequence of the film layers formed on the side surface of the silicon substrate cannot be arbitrarily adjusted, and it needs to be comprehensively considered according to the formation sequence requirements of the film layers on the side surface of the silicon substrate, the technical problems to be solved, as well as the formation sequence requirements and the solved technical problems of the front and back film layers. In the actual application process, the conductive type of the silicon substrate in the embodiments of the present application is not specifically limited. The conductive type of the silicon substrate can be N-type, P-type, or intrinsic type. In the above case, as shown in FIG. 8, the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15, the second doped silicon layer 16, and the transparent conductive layer 208 included in the back contact battery are not only provided on the side surface of the silicon substrate 100, but also provided on the backlight surface of the silicon substrate 100. Specifically, on one side of the backlight surface of the silicon substrate 100, the transparent conductive layer 208 covers the sides of the first doped silicon layer 12 and the second doped silicon layer 16 facing away from the silicon substrate 100, and through isolation grooves are provided in the transparent conductive layer 208 to disconnect the portion of the transparent conductive layer 208 corresponding to the first doped silicon layer 12 from the portion of the transparent conductive layer 208 corresponding to the second doped silicon layer 16 to prevent short circuit. As for the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15, and the second doped silicon layer 16 on one side of the backlight surface of the silicon substrate 100, it can be set according to actual needs and is not specifically limited here. Exemplarily, the backlight surface may include a first region and a second region that do not overlap with each other. The first interface passivation layer and the first doped silicon layer are provided on the first region, and the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region in a direction away from the silicon substrate. In this case, the distribution ranges of the first region and the second region on the backlight surface can be determined respectively according to the distribution of the first doped silicon layer and the second doped silicon layer on the backlight surface in the actual application scenario. Exemplarily, the backlight surface may include a first region and a second region that are spaced apart, and a third region located between the first region and the second region. The first interface passivation layer and the first doped silicon layer are provided on the first region, and the intrinsic silicon layer and the second doped silicon layer are sequentially stacked on the second region in a direction away from the silicon substrate. In this case, the distribution ranges of the first region and the second region on the backlight surface can be determined respectively according to the distribution of the first doped silicon layer and the second doped silicon layer on the backlight surface in the actual application scenario. The third region is the region on the backlight surface where the first doped silicon layer and the second doped silicon layer are not provided. Exemplarily, as shown in FIG. 8, the backlight surface includes a first region 120a and a second region 120b which are distributed at intervals. The first interface passivation layer 20 and the first doped silicon layer 12 are disposed on the first region 120a. The intrinsic silicon layer 15 and the second doped silicon layer 16 are disposed on the second region 120b, extend from the second region 120b to the first region 120a, and cover a part of the first interface passivation layer 20 and the first doped silicon layer 12. In this case, on the backlight surface of the silicon substrate 100, the intrinsic silicon layer 15 and the second doped silicon layer 16 are not only stacked in sequence along the thickness direction of the silicon substrate 100 on the second region 120b, but also cover a part of the first interface passivation layer 20 and the first doped silicon layer 12. At this time, the formation range of the intrinsic silicon layer 15 and the second doped silicon layer 16 on one side of the backlight surface of the silicon substrate 100 is relatively large, which is beneficial to reducing the etching range of the intrinsic silicon layer 15 and the second doped silicon layer 16 arranged in a whole layer during the manufacturing process, and is beneficial to improving the etching productivity. Moreover, the part of the intrinsic silicon layer 15 and the second doped silicon layer 16 covering the first doped silicon layer 12 can protect the edge of the first doped silicon layer 12, prevent the etchant from affecting the edge of the first doped silicon layer 12, and ensure that the edge of the first doped silicon layer 12 has a high carrier collection efficiency. In addition, no isolation groove is provided between the first interface passivation layer 20, the first doped silicon layer and the second interface passivation layer, the second doped silicon layer. Therefore, the contact area between the first interface passivation layer, the first doped silicon layer 12 and the silicon substrate 100, and the contact area between the intrinsic silicon layer 15, the second doped silicon layer 16 and the silicon substrate 100 can be maximized, thereby improving the utilization rate of the silicon substrate 100, and further improving the photoelectric conversion efficiency. Specifically, in this case, the distribution range of the first region 120a on the backlight surface can be determined according to the distribution of the first doped silicon layer 12 on the backlight surface in the actual application scenario. The distribution range of the second region 120b on the backlight surface can be determined according to the distribution of the part of the second doped silicon layer 16 that does not overlap with the first doped silicon layer 12 in the actual application scenario. Regarding the surface topography of the silicon substrate, the light-receiving surface of the silicon substrate can be a polished surface or a textured surface. Among them, when the light-receiving surface of the silicon substrate is a textured surface, the light-trapping effect of itself can be improved, and the conversion efficiency of the back-contact battery can be further improved. Secondly, the backlight surface of the silicon substrate can all be polished surfaces; or, in the backlight surface of the silicon substrate, the surface of the region corresponding to the first interface passivation layer and the first doped silicon layer can be a polished surface, and the surface in contact with the intrinsic silicon layer and the second doped silicon layer can be a textured surface. At this time, after at least removing the part of the first interface passivation layer and the first doped silicon layer covering the region corresponding to the intrinsic silicon layer and the second doped silicon layer on the backlight surface, while performing the texturing treatment on the light-receiving surface, the surface of the region corresponding to the intrinsic silicon layer and the second doped silicon layer on the backlight surface is also textured to increase the contact area between the second doped silicon layer and the transparent conductive layer and reduce the contact loss therebetween. In addition, the lateral morphology of the silicon substrate can be determined according to the formation ranges of the first interface passivation layer and the first doped silicon layer on the side of the silicon substrate and the actual manufacturing process, and no specific limitation is made here. In the actual application process, as shown in FIG. 8, the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side cover all regions on the side. Alternatively, as shown in FIG. 9, the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side may be located in a partial region on the side and close to the backlight surface; in this case, it can be understood that during the actual manufacturing process, when the first doped silicon layer 12 is formed on the backlight surface and the side of the silicon substrate 100, the first doped silicon layer 12 may be deposited by plating around on the light-receiving surface. The first doped silicon layer 12 located on the light-receiving surface has parasitic absorption and needs to be removed to improve the light utilization rate of the silicon substrate. Based on this, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side are located in a partial region on the side, there is no need to strictly control the manufacturing conditions to completely retain the first doped silicon layer 12 formed on the side during the process of removing the first interface passivation layer 20 and the first doped silicon layer 12 plated around to the light-receiving surface, thereby reducing the manufacturing difficulty of the back-contact battery. Among them, as shown in FIG. 8, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side cover all regions on the side, the surface reflectivity and / or surface morphology of each partial region on the side of the silicon substrate 100 can be substantially the same. At this time, the surface of each region on the side of the silicon substrate 100 can be a polished surface, or can be a texture surface such as a matte surface. Exemplarily, as shown in FIG. 10, when the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side are located in a partial region on the side and close to the backlight surface, the surface reflectivity of the region on the side that is not covered by the first doped silicon layer 12 can be less than the surface reflectivity of the region on the side that is covered with the first interface passivation layer 20 and the first doped silicon layer 12. At this time, although the passivation effect of the surface of the region on the side of the silicon substrate 100 that is not covered by the first interface passivation layer 20 and the first doped silicon layer 12 is relatively low, the surface of this region has a relatively high light-trapping effect, which is beneficial to refracting more light from the side of the silicon substrate 100 close to the light-receiving surface into the silicon substrate 100, and is beneficial to improving the conversion efficiency of the back-contact battery. Among them, when the surface reflectivity of the region on the side that is not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the region on the side that is covered with the first interface passivation layer and the first doped silicon layer, the surface morphology of the region on the side that is not covered by the first interface passivation layer and the first doped silicon layer can be the same as the surface morphology of the region on the side that is covered with the first interface passivation layer and the first doped silicon layer, while the size of the texture structure on the surface of the region on the side that is not covered by the first interface passivation layer and the first doped silicon layer is different from the size of the texture structure on the surface of the region on the side that is covered with the first interface passivation layer and the first doped silicon layer. For example, the surfaces of the regions in the side that are not covered by the first interface passivation layer and the first doped silicon layer and the surfaces of the regions in the side that are covered by the first interface passivation layer and the first doped silicon layer may both have a tower base-like texture structure, and the side length of the tower base-like texture structure of the surface of the region in the side that is not covered by the first interface passivation layer and the first doped silicon layer is smaller than the side length of the tower base-like texture structure of the surface of the region in the side that is covered by the first interface passivation layer and the first doped silicon layer, and / or, the height of the tower base-like texture structure of the surface of the region in the side that is not covered by the first interface passivation layer and the first doped silicon layer is greater than the height of the tower base-like texture structure of the surface of the region in the side that is covered by the first interface passivation layer and the first doped silicon layer. Another example: the surfaces of the regions in the side that are not covered by the first interface passivation layer and the first doped silicon layer and the surfaces of the regions in the side that are covered by the first interface passivation layer and the first doped silicon layer may both have a pyramid-like texture structure, and the side length (or diagonal, height) of the bottom of the pyramid-like texture structure of the surface of the region in the side that is not covered by the first interface passivation layer and the first doped silicon layer is greater than the side length (or diagonal, height) of the pyramid-like texture structure of the surface of the region in the side that is covered by the first interface passivation layer and the first doped silicon layer. Alternatively, when the surface reflectivity of the region in the side that is not covered by the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the region in the side that is covered by the first interface passivation layer and the first doped silicon layer, the surface morphology of the region in the side that is not covered by the first interface passivation layer and the first doped silicon layer may also be different from the surface morphology of the region in the side that is covered by the first interface passivation layer and the first doped silicon layer. At this time, the surface morphologies of these two regions in the side can be determined according to the relationship of the reflectivity magnitudes and the actual manufacturing process, and no specific limitation is made here. Exemplarily, as shown in FIG. 10, the surface of the region in the side that is not covered by the first interface passivation layer 20 and the first doped silicon layer 12 may be a matte surface. In this case, the surface of the region in the side that is not covered by the first interface passivation layer 20 and the first doped silicon layer 12 has a relatively high light trapping effect, which is beneficial for refracting more light from the side of the silicon substrate 100 close to the light receiving surface into the silicon substrate 100, and is beneficial for improving the conversion efficiency of the back contact battery. Exemplarily, as shown in FIG. 10, the surface of the region in the side that is covered by the first interface passivation layer 20 and the first doped silicon layer 12 is a polished surface. In this case, the surface of the region in the side that is covered by the first interface passivation layer 20 and the first doped silicon layer 12 is relatively flat, which is beneficial for forming a thicker first interface passivation layer 20 and first doped silicon layer 12 on this region, enhancing the passivation effect of the first interface passivation layer 20 and the first doped silicon layer 12 on the corresponding region of the side, and further improving the conversion efficiency of the back contact battery. For the first doped silicon layer, in terms of the arrangement form of substances, the crystal phase of the first doped silicon layer can be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline, etc. The specific crystal phase of the first doped silicon layer can be determined according to the type of the first interface passivation layer. Among them, the first interface passivation layer can be a tunneling passivation layer such as a tunneling oxide layer. At this time, the first doped silicon layer is a doped crystalline silicon layer, and the material of the doped crystalline silicon layer can include polysilicon and / or single crystal silicon. Or, the first interface passivation layer can also be an intrinsic silicon passivation layer such as intrinsic amorphous silicon. At this time, the materials of the first interface passivation layer and the first doped silicon layer can include at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon. It should be noted that when the first interface passivation layer is a tunneling passivation layer and the first doped silicon layer is a doped crystalline silicon layer, the first interface passivation layer has higher film density, which further improves its passivation effect on the silicon substrate, thereby further reducing the surface defects of the silicon substrate and improving the conversion efficiency of the back contact battery. In terms of thickness, as shown in FIG. 8, the thicknesses of the respective parts of the first doped silicon layer 12 can be the same; as shown in FIG. 9, or alternatively, the thickness of the first doped silicon layer 12 provided on the backlight side can be greater than the thickness of the first doped silicon layer 12 provided on the side. Among them, when the thicknesses of the respective parts of the first doped silicon layer 12 are the same, it is beneficial to make each part of the first doped silicon layer 12 have a high passivation effect, so that each region corresponding to the first doped silicon layer 12 in the silicon substrate 100 has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery. As for the specific thickness of the first doped silicon layer, it can be determined according to actual needs and the material of the first doped silicon layer, and no specific limitation is made here. Exemplarily, the thickness of the first doped silicon layer can be greater than or equal to 30 nm and less than or equal to 140 nm. For example: the thickness of the first doped silicon layer can be 30 nm, 40 nm, 50 nm, 60 nm, 80 nm, 100 nm, 120 nm, 130 nm or 140 nm, etc. With such a setting, the presence of the transparent conductive layer can improve the carrier collection efficiency and leave a margin for thinning the first doped silicon layer. In other words, on the premise of not reducing the carrier collection efficiency, the thickness of the first doped silicon layer can be appropriately reduced due to the presence of the transparent conductive layer. Based on this, when the thickness of the first doped silicon layer is within the above range, the thickness of the first doped silicon layer is small, which is beneficial to reducing its parasitic absorption and further improving the working efficiency of the back contact battery; and, it can also reduce the deposition time of the first doped silicon layer and improve the manufacturing efficiency of the first doped silicon layer. In addition, the thickness of the first doped silicon layer cannot be too small to avoid affecting the carrier collection. For the first interface passivation layer, as shown in FIG. 8, the thicknesses of the respective parts of the first interface passivation layer 20 can be the same; or, the thickness of the first interface passivation layer disposed on the backlight side can be greater than the thickness of the first interface passivation layer disposed on the side surface. Among them, when the thicknesses of the respective parts of the first interface passivation layer are the same, it is beneficial to make each part of the first interface passivation layer 20 have a relatively high passivation effect, so that each region in the silicon substrate 100 corresponding to the first interface passivation layer 20 has a relatively low carrier recombination rate, further improving the conversion efficiency of the back contact battery. As for the specific thickness of the first interface passivation layer, it can be determined according to actual requirements and the material of the first interface passivation layer, and no specific limitation is made here. In addition, in the side surface of the silicon substrate, when the surface of the region where the first interface passivation layer and the first doped silicon layer are provided has a tower base-like texture structure, the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure can be equal to the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure. At this time, the first interface passivation layer has a relatively high passivation effect on both the bottom surface and the side wall of the tower base-like texture structure. Or, the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure can also be less than the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure. In this case, it can be understood that the bottom surface of the tower base-like texture structure and the side surface of the tower base-like texture structure have different crystal orientations. Specifically, the bottom surface of the tower base-like texture structure is the

[0110] crystal orientation, and the number of dangling bonds on the surface of this

[0110] crystal orientation is relatively small; while the side surface of the tower base-like texture structure is the

[0111] crystal orientation, and the number of dangling bonds on this

[0111] crystal orientation is relatively large. Based on this, when the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure, it is beneficial to make the part of the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure have a relatively high passivation effect, meet the requirement of the side surface of the tower base-like texture structure for a high passivation effect, reduce the carrier recombination rate of the side surface of the tower base-like texture structure, and further improve the working efficiency of the back contact battery. As for the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure and the thickness of the first interface passivation layer located on the side wall of the tower base-like texture structure, they can be determined according to the requirements for the passivation effect of different regions of the tower base-like texture structure and the actual manufacturing process, and no specific limitation is made here. Exemplarily, the thickness of the first interface passivation layer located at the bottom surface of the tower-based texture structure can be greater than or equal to 0.5 nm and less than or equal to 1.5 nm. For example: the thickness of the first interface passivation layer located at the bottom surface of the tower-based texture structure can be 0.5 nm, 0.6 nm, 0.8 nm, 1 nm, 1.2 nm, 1.3 nm, 1.5 nm, etc. In this case, the thickness of the first interface passivation layer located at the bottom surface of the tower-based texture structure is within the above range, which is beneficial to preventing the passivation effect of this part on the silicon substrate from being low due to the small thickness of the first interface passivation layer located at the bottom surface of the tower-based texture structure, while reducing the carrier recombination rate on the side of the tower-based texture structure. Exemplarily, the thickness of the first interface passivation layer located on the sidewall of the tower-based texture structure can be greater than or equal to 0.5 nm and less than or equal to 2 nm. For example: the thickness of the first interface passivation layer located on the sidewall of the tower-based texture structure can be 0.5 nm, 0.8 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, 2 nm, etc. In this case, the thickness of the first interface passivation layer located on the sidewall of the tower-based texture structure is within the above range, which is beneficial to preventing the passivation effect of itself from being low due to the small thickness of this part, and reducing the carrier recombination rate on the side of the tower-based texture structure. Regarding the formation range of the first interface passivation layer and the first doped silicon layer on the side of the silicon substrate, as described above, the first interface passivation layer and the first doped silicon layer provided on the side can cover the entire area on the side. Or, the first interface passivation layer and the first doped silicon layer provided on the side can also be only located in a local area on the side and close to the backlight surface; in this case, the extension range of the first interface passivation layer and the first doped silicon layer on the side can be set according to the actual manufacturing process and actual requirements, and no specific limitation is made here. Exemplarily, as shown in FIG. 10, along the thickness direction of the silicon substrate 100, the ratio of the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side surface to the thickness of the silicon substrate 100 can be greater than or equal to 70%. For example: the ratio of the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side surface to the thickness of the silicon substrate 100 can be 70%, 75%, 80%, 85%, 90%, 95% or 98%, etc. In this case, as described above, the first interface passivation layer 20 and the first doped silicon layer 12 passivate the side surface of the silicon substrate 100. Therefore, when the ratio of the maximum extension length of the first interface passivation layer 20 and the first doped silicon layer 12 on the side surface to the thickness of the silicon substrate 100 is greater than or equal to 70%, it is ensured that the first interface passivation layer 20 and the first doped silicon layer 12 have a larger formation range on the side surface of the silicon substrate 100, so that the surface of more regions in the side surface has a lower carrier recombination rate, further improving the conversion efficiency of the back contact battery. And, most regions in the side surface of the silicon substrate 100 are covered with the first interface passivation layer 20 and the first doped silicon layer 12. At this time, the first interface passivation layer 20 and the first doped silicon layer 12 protect most regions in the side surface of the silicon substrate 100, and when preventing the intrusion of water vapor and the like, it is ensured that the side surface of the silicon substrate 100 has a relatively thick laminated protection, further improving the protection effect of the side surface of the silicon substrate 100. Exemplarily, when the first interface passivation layer and the first doped silicon layer provided on the side surface are only located on a partial region of the side surface and are close to the backlight surface, the surface of the region in the side surface that is not covered with the first interface passivation layer and the first doped silicon layer is a matte surface, and the ratio of the maximum extension length of the matte surface on the side surface to the thickness of the silicon substrate can be less than or equal to 30%. For example: the ratio of the maximum extension length of the matte surface on the side surface to the thickness of the silicon substrate can be 1%, 5%, 10%, 15%, 20%, 25% or 30%, etc. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects when the ratio of the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side surface to the thickness of the silicon substrate is greater than or equal to 70% described above, and will not be elaborated here. For the surface passivation layer and the antireflection layer, the embodiments of the present application do not specifically limit the materials of the surface passivation layer and the antireflection layer, as long as they can be applied to the back contact battery provided by the embodiments of the present application. Exemplarily, the material of the surface passivation layer may include at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Among them, the conductivity type of the doped silicon glass is the same as or opposite to that of the first doped silicon layer. Specifically, the material of the surface passivation layer may only include aluminum oxide, intrinsic amorphous silicon, or doped silicon glass. Or, the material of the surface passivation layer may include any two of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass. Or, the material of the surface passivation layer may also include aluminum oxide, intrinsic amorphous silicon, and doped silicon glass at the same time. Specifically, when the material of the surface passivation layer includes at least two types, the distribution between different materials may be determined according to actual requirements and the actual manufacturing process, and no specific limitation is made here. In this case, hydrogen is contained in aluminum oxide and intrinsic amorphous silicon. When the material of the surface passivation layer includes aluminum oxide and / or intrinsic amorphous silicon, hydrogen passivation can be performed on the silicon substrate and the first doped silicon layer to further improve the passivation effect of the surface passivation layer. The doped silicon glass is doped with impurities of the corresponding conductivity type, and field passivation can also be performed on the silicon substrate and the first doped silicon layer, which can also further improve the passivation effect of the surface passivation layer. Secondly, the manufacturing process of the surface passivation layer with the material of doped silicon glass is relatively simple, which is beneficial to reducing the manufacturing difficulty of the back contact battery. Exemplarily, the material of the antireflection layer may include silicon nitride and / or silicon oxynitride, etc. Regarding the formation range of the surface passivation layer and the antireflection layer on the side surface of the silicon substrate, as shown in FIGS. 8 to 10, along the thickness direction of the silicon substrate 100, the surface passivation layer 13 and the antireflection layer 207 may cover all regions on the side surface of the silicon substrate 100, that is, cover the entire side surface. Or, as shown in FIG. 11, the surface passivation layer 13 and the antireflection layer 207 provided on the side surface may also be located on a partial region of the side surface and close to the light-receiving surface. In this case, it can be understood that during the actual manufacturing process, when forming the surface passivation layer 13 and the antireflection layer 207 on the light-receiving surface and the side surface of the silicon substrate 100, in order to ensure that the surface passivation layer 13 and the antireflection layer 207 with a larger coverage range are formed on the side surface, the surface passivation layer 13 and the antireflection layer 207 may be plated around on the backlight side. The surface passivation layer 13 and the antireflection layer 207 on the backlight side will affect the carrier collection effect of the subsequently formed intrinsic silicon layer 15 and the second doped silicon layer 16, so it is necessary to remove the surface passivation layer 13 and the antireflection layer 207 on the backlight side. Based on this, when the surface passivation layer 13 and the antireflection layer 207 provided on the side surface are located on a partial region of the side surface, there is no need to strictly control the manufacturing conditions to retain all the surface passivation layer 13 and the antireflection layer 207 on the side surface during the process of removing the surface passivation layer 13 and the antireflection layer 207 plated around on the backlight side, reducing the manufacturing difficulty of the back contact battery. Specifically, it can be understood that the greater the extension length of the surface passivation layer and the anti-reflection layer on the side, the more the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be isolated by forming a larger range of the surface passivation layer and the anti-reflection layer, the lower the forward leakage current of the back contact battery, and at the same time, the maximum protection range of the surface passivation layer and the anti-reflection layer for the side of the silicon substrate. And the smaller the extension length of the surface passivation layer and the anti-reflection layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the hot spot risk of the back contact battery. Based on this, the extension range of the surface passivation layer and the anti-reflection layer on the side can be determined according to the forward leakage loss, side protection, hot spot risk of the back contact battery in the actual application scenario, and the actual manufacturing process, and no specific limitation is made here. Exemplarily, along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the surface passivation layer and the anti-reflection layer on the side to the thickness of the silicon substrate can be less than or equal to 80%. For example: the ratio of the maximum extension length of the surface passivation layer and the anti-reflection layer on the side to the thickness of the silicon substrate can be 5%, 10%, 15%, 20%, 30%, 40%, 50%, 60%, 70% or 80%, etc. In this case, the difficulty of removing the part of the surface passivation layer and the anti-reflection layer that is plated around to the backlight surface can be reduced, and the manufacturing precision requirement can be lowered. In addition, at the area of the side of the silicon substrate where the surface passivation layer and the anti-reflection layer are not covered, the first doped silicon layer can be electrically contacted with the second doped silicon layer with the opposite conductivity type through the intrinsic silicon layer, so as to form a diode structure with a lower reverse breakdown voltage on the side of the silicon substrate, which is beneficial to reducing the hot spot risk of the back contact battery and improving the anti-burning ability of the back contact battery. In addition, according to the requirements of the actual application scenario of the back contact battery, the forward leakage current, hot spot risk and side protection of the back contact battery can be regulated by adjusting the maximum extension length of the surface passivation layer and the anti-reflection layer on the side, which is beneficial to achieving the balance among the forward leakage current, hot spot risk and side protection of the back contact battery. As for the thickness of the surface passivation layer and the anti-reflection layer, among them, the thickness of the surface passivation layer and / or the anti-reflection layer on the light-receiving side of the silicon substrate can be substantially the same, so that each area on the light-receiving side of the silicon substrate corresponds to a relatively high passivation effect, and it is beneficial to make each area on the light-receiving side of the back contact battery have a relatively low reflectivity, further improving the conversion efficiency of the back contact battery. Regarding the thickness of the surface passivation layer and the antireflection layer on the side surface of the silicon substrate, the thickness of each part of the surface passivation layer and / or the antireflection layer on the side surface of the silicon substrate can be the same. In this case, within a certain range, the thickness of the surface passivation layer is proportional to its own passivation effect and insulation isolation effect. Based on this, when the thickness of the surface passivation layer is equal on the side surface of the silicon substrate, each part of the surface passivation layer has a high passivation effect and high insulation isolation characteristics, which is conducive to making each area covered with the surface passivation layer on the side surface of the silicon substrate have a low number of surface defects. It is also conducive to better achieving the electrical isolation effect between the first doped silicon layer and the second doped silicon layer through the surface passivation layer with uniform thickness, and reducing the forward leakage current. Secondly, when the thickness of each part of the antireflection layer on the side surface of the silicon substrate is the same, it is conducive to making each part of the antireflection layer on the side surface have high insulation characteristics and a protective effect, and is conducive to better achieving the electrical isolation effect between the first doped silicon layer and the second doped silicon layer through the antireflection layer with uniform thickness, reducing the forward leakage current, and improving the structural reliability of the side surface of the back contact battery. Alternatively, as shown in FIG. 11, on the side surface of the silicon substrate 100, the thickness of the surface passivation layer 13 and / or the antireflection layer 207 can gradually increase in the direction from the backlight surface to the light-receiving surface. In this case, it can be understood that when the thickness of the surface passivation layer 13 gradually increases in the direction from the backlight surface to the light-receiving surface, the part of the surface passivation layer 13 on the side surface close to the light-receiving surface has a high passivation effect and better insulation isolation characteristics. While further reducing the number of surface defects in the area on the side surface of the silicon substrate 100 close to the light-receiving surface, it further reduces the leakage risk between the first doped silicon layer 12 and the second doped silicon layer 16, which is conducive to increasing the open-circuit voltage and fill factor of the back contact battery. When the thickness of the antireflection layer 207 gradually increases in the direction from the backlight surface to the light-receiving surface, the part of the surface passivation layer 13 on the side surface close to the light-receiving surface has better insulation isolation characteristics, further reducing the leakage risk between the first doped silicon layer 12 and the second doped silicon layer 16, which is conducive to increasing the open-circuit voltage and fill factor of the back contact battery. Among them, on the side surface of the silicon substrate, the increasing amplitude of the thickness of the surface passivation layer and / or the antireflection layer in the direction from the backlight surface to the light-receiving surface, and the thickness of the part of the surface passivation layer and / or the antireflection layer close to the backlight surface or the light-receiving surface can be set according to actual needs, and no specific limitation is made here. For the intrinsic silicon layer and the second doped silicon layer, in terms of materials, the materials of the intrinsic silicon layer and / or the second doped silicon layer may include at least one of amorphous silicon, microcrystalline silicon, and nanocrystalline silicon. Secondly, the conduction types of the second doped silicon layer and the first doped silicon layer can be determined according to the material of the first doped silicon layer and the actual application scenario, as long as the conduction types of the first doped silicon layer and the second doped silicon layer are opposite. Specifically, the conduction type of the first doped silicon layer can be N-type, and in this case, the conduction type of the second doped silicon layer is P-type. Or, the conduction type of the first doped silicon layer can also be P-type, and in this case, the conduction type of the second doped silicon layer is N-type. Optionally, when the material of the first doped silicon layer includes polysilicon, the conduction type of the first doped silicon layer can be N-type, and the conduction type of the second doped silicon layer is P-type. In this case, compared with P-type doped amorphous silicon, P-type doped microcrystalline silicon, and P-type doped nanocrystalline silicon materials, the contact resistance between the P-type doped polysilicon material and the electrode is relatively high, and the field passivation effect is relatively poor. Therefore, when the conduction type of the first doped silicon layer is set to N-type and the conduction type of the second doped silicon layer is set to P-type, the field passivation effect of the first doped silicon layer can be further improved, and at the same time, the contact resistance between the first doped silicon layer and the electrode can be reduced, which is beneficial to improving the electrical performance of the back contact battery. Regarding the formation range of the intrinsic silicon layer and the second doped silicon layer on the side surface of the silicon substrate, as shown in FIGS. 8 to 10, along the thickness direction of the silicon substrate 100, the intrinsic silicon layer 15 and the second doped silicon layer 16 can cover all regions on the side surface of the silicon substrate 100, that is, the entire side surface. Or, as shown in FIG. 12, the intrinsic silicon layer 15 and the second doped silicon layer 16 provided on the side surface can also be located on a partial region of the side surface and close to the backlight surface. In this case, it can be understood that during the actual manufacturing process, when forming the intrinsic silicon layer 15 and the second doped silicon layer 16 on the backlight surface and the side surface of the silicon substrate 100, in order to ensure that the intrinsic silicon layer 15 and the second doped silicon layer 16 with a larger coverage range are formed on the side surface, the intrinsic silicon layer 15 and the second doped silicon layer 16 may be plated around on the light-receiving surface side. However, the intrinsic silicon layer 15 and the second doped silicon layer 16 on the light-receiving surface have parasitic absorption, so it is necessary to remove the intrinsic silicon layer 15 and the second doped silicon layer 16 on the light-receiving surface. Based on this, when the intrinsic silicon layer 15 and the second doped silicon layer 16 provided on the side surface are located on a partial region of the side surface, there is no need to strictly control the manufacturing conditions to retain all the intrinsic silicon layer 15 and the second doped silicon layer 16 on the side surface during the process of removing the intrinsic silicon layer 15 and the second doped silicon layer 16 plated around on the light-receiving surface, thereby reducing the manufacturing difficulty of the back contact battery. Specifically, in this case, the extension range of the intrinsic silicon layer 15 and the second doped silicon layer 16 on the side surface can be determined according to the passivation and protection requirements for the side surface of the silicon substrate 100 in the actual application scenario, the anti-leakage requirements between the first doped silicon layer 12 and the second doped silicon layer 16 provided on the side surface of the silicon substrate 100, and the actual manufacturing process, and no specific limitation is made here. Regarding the thicknesses of the intrinsic silicon layer and the second doped silicon layer on the side of the silicon substrate, the thicknesses of the two on the side of the silicon substrate can be substantially the same along the direction from the backlight surface to the light-receiving surface. Alternatively, as shown in FIG. 12, on the side of the silicon substrate 100, the thicknesses of the intrinsic silicon layer 15 and / or the second doped silicon layer 16 gradually increase along the direction from the light-receiving surface to the backlight surface. In this case, it is beneficial to improve the protection effect of the intrinsic silicon layer 15 and / or the second doped silicon layer 16 on the area near the backlight surface in the side of the silicon substrate 100, and the structural reliability of the side in the back contact battery can be further improved. Exemplarily, the thickness of the intrinsic silicon layer can be greater than or equal to 8 nm and less than or equal to 14 nm. For example, the thickness of the intrinsic silicon layer can be 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, or 14 nm, etc. In this case, the thickness of the intrinsic silicon layer is relatively large, which is beneficial to enhancing the isolation effect between the first doped silicon layer and the second doped silicon layer and reducing the risk of forward leakage. In addition, in the side of the silicon substrate, when the surface of the area covered with the intrinsic silicon layer and / or the second doped silicon layer has a tower-base-like texture structure, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower-base-like texture structure can be equal to the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the sidewall of the tower-base-like texture structure; or, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower-base-like texture structure can also be greater than the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the sidewall of the tower-base-like texture structure. It can be understood that the part of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower-base-like texture structure accounts for a relatively large proportion in the side. Therefore, when the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower-base-like texture structure is relatively large, a relatively large part of the intrinsic silicon layer and / or the second doped silicon layer can have a high passivation and protection effect, which can further reduce the number of defects on the side of the back contact battery and improve the protection effect on the side of the silicon substrate. Of course, it can also be that the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower-base-like texture structure is less than the thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the sidewall of the tower-base-like texture structure, so as to improve the applicability of the back contact battery provided by the embodiments of the present application in different application scenarios. In this article, the "thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the bottom surface of the tower-base-like texture structure" can refer to the thickness of the intrinsic silicon layer located at the bottom surface of the tower-base-like texture structure, or can refer to the thickness of the second doped silicon layer located at the bottom surface of the tower-base-like texture structure; of course, it can also refer to the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer located at the bottom surface of the tower-base-like texture structure. In this article, the "thickness of the intrinsic silicon layer and / or the second doped silicon layer located at the sidewall of the tower-base-like texture structure" is similar to the foregoing explanation and will not be elaborated here. In addition, when comparing the thickness of the bottom surface of the tower-base-shaped texture structure with the thickness of the side wall of the tower-base-shaped texture structure, the comparison should be made for the same film layer. For example, the intrinsic silicon layer, or the second doped silicon layer, or the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer. As a possible implementation, when the side surface of the silicon substrate has a tower-base-shaped texture structure, the thickness of the first interface passivation layer on the bottom surface of the tower-base-shaped texture structure can be less than the thickness of the first interface passivation layer on the side wall of the tower-base-shaped texture structure. Moreover, the thickness of the intrinsic silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the thickness of the intrinsic silicon layer on the side wall of the tower-base-shaped texture structure; and / or, the thickness of the second doped silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the thickness of the second doped silicon layer on the side wall of the tower-base-shaped texture structure. "The thickness of the intrinsic silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the thickness of the intrinsic silicon layer on the side wall of the tower-base-shaped texture structure; and the thickness of the second doped silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the thickness of the second doped silicon layer on the side wall of the tower-base-shaped texture structure." means that the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the sum of the thicknesses of the intrinsic silicon layer and the second doped silicon layer on the side wall of the tower-base-shaped texture structure. Specifically, in the intrinsic silicon layer and the second doped silicon layer, it can be that only the thickness of the intrinsic silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the thickness of the intrinsic silicon layer on the side wall of the tower-base-shaped texture structure, while the thickness of the second doped silicon layer on the bottom surface of the tower-base-shaped texture structure is less than or equal to the thickness of the second doped silicon layer on the side wall of the tower-base-shaped texture structure; or it can be that in the intrinsic silicon layer and the second doped silicon layer, the thickness of the intrinsic silicon layer on the bottom surface of the tower-base-shaped texture structure is less than or equal to the thickness of the intrinsic silicon layer on the side wall of the tower-base-shaped texture structure, while the thickness of the second doped silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the thickness of the second doped silicon layer on the side wall of the tower-base-shaped texture structure. It can also be that in the intrinsic silicon layer and the second doped silicon layer, the thickness of the intrinsic silicon layer on the bottom surface of the tower-base-shaped texture structure is greater than the thickness of the intrinsic silicon layer on the side wall of the tower-base-shaped texture structure, and the thickness of the second doped silicon layer on the bottom surface of the tower-base-shaped texture structure is also greater than the thickness of the second doped silicon layer on the side wall of the tower-base-shaped texture structure. In the case of adopting the above technical solution, the thickness relationship between the first interface passivation layer on the bottom surface and the side wall of the tower-shaped texture structure is opposite to the thickness relationship between the intrinsic silicon layer and / or the second doped silicon layer on the bottom surface and the side wall of the tower-shaped texture structure. At this time, the thickness of the first interface passivation layer located on the side wall of the tower-shaped texture structure is larger, which can make up for the weak passivation effect and protection function of the intrinsic silicon layer and / or the second doped silicon layer due to their smaller thickness on the side wall of the tower-shaped texture structure. Moreover, the thickness of the intrinsic silicon layer and / or the second doped silicon layer located on the bottom surface of the tower-shaped texture structure is larger, which can make up for the weak passivation effect and protection function of the first interface passivation layer due to its smaller thickness on the bottom surface of the tower-shaped texture structure, ensuring that under the combined passivation and protection effects of the first interface passivation layer, the intrinsic silicon layer and / or the second doped silicon layer, both the bottom surface and the side surface of the silicon substrate corresponding to the tower-shaped texture structure have high passivation effects and protection strengths. For the transparent conductive layer, as shown in FIG. 8, along the thickness direction of the silicon substrate 100, the transparent conductive layer 208 can cover various regions on the side surface of the silicon substrate 100. Alternatively, as shown in FIG. 12, the transparent conductive layer 208 provided on the side surface can also be located on a partial region of the side surface and close to the backlight surface. In this case, there is no need to strictly control the manufacturing conditions to completely retain the transparent conductive layer 208 on the side surface during the process of removing the transparent conductive layer 208 plated around to the light-receiving surface, reducing the manufacturing difficulty of the back-contact battery. Specifically, in this case, the extension range of the transparent conductive layer 208 on the side surface can be determined according to the protection requirements for the side surface of the silicon substrate 100 in the actual application scenario, the anti-leakage requirements between the first doped silicon layer 12 and the second doped silicon layer 16 provided on the side surface of the silicon substrate 100, and the actual manufacturing process, and no specific limitation is made here. As for the thickness of the transparent conductive layer on the side surface of the silicon substrate, its thickness on the side surface of the silicon substrate can be substantially the same along the direction from the backlight surface to the light-receiving surface. Alternatively, as shown in FIG. 12, on the side surface of the silicon substrate 100, the thickness of the transparent conductive layer 208 gradually increases along the direction from the light-receiving surface to the backlight surface. In this case, it is beneficial to improve the protection effect of the transparent conductive layer 208 on the region near the backlight surface in the side surface of the silicon substrate 100, and can further improve the structural reliability of the side surface in the back-contact battery. In addition, the material of the transparent conductive layer can include indium tin oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, antimony-doped tin oxide, etc. As a possible implementation, as shown in FIG. 13, the back contact battery may further include an insulating mask layer 21. The insulating mask layer 21 is disposed between the first doped silicon layer 12 on the side and the surface passivation layer 13, and the insulating mask layer 21 is also disposed between the intrinsic silicon layer 15 on the backlight side and the first doped silicon layer 12 in the thickness direction of the silicon substrate 100. In this case, the insulating mask layer 21, together with the surface passivation layer 13 and the antireflection layer 207, can separate the first doped silicon layer 12 on the side from the second doped silicon layer 16, further suppressing side leakage. At the same time, it can also passivate the side of the silicon substrate 100, further reducing the number of defects on the side of the silicon substrate 100. In addition, forming the insulating mask layer 21 on the side is also beneficial to reducing the thickness requirement for the intrinsic silicon layer 15. While ensuring a low forward leakage between the first doped silicon layer 12 and the second doped silicon layer 16, the thickness of the intrinsic silicon layer 15 is made smaller to have a low tunneling resistance, which is beneficial to improving the carrier collection efficiency of the second doped silicon layer 16 on the backlight side. In terms of materials, the material of the insulating mask layer may include any insulating material with a masking and protecting effect, and no specific limitation is made here. For example: the insulating mask layer may include at least one of a doped silicon glass layer, an alumina layer, and a silicon nitride layer. Among them, the conduction type of the doped silicon glass layer is opposite to that of the first doped silicon layer. In terms of the coverage range on the side, as shown in FIG. 13, in the thickness direction of the silicon substrate 100, the insulating mask layer 21 can cover all regions on the side of the silicon substrate 100. Or, as shown in FIG. 14, the insulating mask layer 21 disposed on the side may also be located on a local area of the side. The application principle of the beneficial effects in this case can refer to the application principle of the beneficial effects when the transparent conductive layer 208 is located on a local area of the side and close to the backlight side, which will not be elaborated here. Among them, when the insulating mask layer 21 disposed on the side is located on a local area of the side, the insulating mask layer 21 disposed on the side may be close to the backlight side, may be close to the light-receiving side, or may be located in the middle area on the side. Specifically, when forming the insulating mask layer on the backlight side and the side of the silicon substrate, the insulating mask layer may also be deposited around the light-receiving surface. At this time, when removing the insulating mask layer deposited around the light-receiving surface, if the part of the insulating mask layer located on the side and close to the light-receiving surface is also removed, and when removing the surface passivation layer and the anti-reflection layer deposited around the backlight surface, and the etchant has little or no effect on the insulating mask layer, the insulating mask layer on the side of the back-contact battery is closer to the backlight side. Or, when removing the insulating mask layer deposited around the light-receiving surface, it has no effect on the insulating mask layer on the side; and when removing the surface passivation layer and the anti-reflection layer deposited around the backlight surface, and the etchant removes the part of the insulating mask layer on the side close to the backlight surface, the insulating mask layer on the side of the back-contact battery is closer to the light-receiving side. Or, when removing the insulating mask layer deposited around the light-receiving surface, the corresponding etchant removes the part of the insulating mask layer located on the side and close to the light-receiving surface; and when removing the surface passivation layer and the anti-reflection layer deposited around the backlight surface, and the etchant removes the part of the insulating mask layer on the side close to the backlight surface, the insulating mask layer on the side of the back-contact battery may be located in the middle area of the side. In addition, in this case, the extension range of the insulating mask layer on the side can be determined according to the passivation and protection requirements for the side of the silicon substrate in the actual application scenario, the anti-leakage requirements between the first doped silicon layer and the second doped silicon layer provided on the side of the silicon substrate, and the actual manufacturing process, and no specific limitation is made here. Exemplarily, the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate can be less than or equal to 80%. For example: the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate can be 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70% or 80%, etc. In this case, it can be understood that the greater the extension length of the insulating mask layer on the side, the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate can be isolated by forming a larger insulating mask layer, the forward leakage of the back-contact battery is lower, and the protective effect of the insulating mask layer on the side of the silicon substrate is stronger. And the smaller the extension length of the insulating mask layer on the side, the larger the range of the reverse leakage area formed between the first doped silicon layer and the second doped silicon layer in the side of the silicon substrate, and the lower the hot spot risk of the back-contact battery. Based on this, when the ratio between the maximum extension length of the insulating mask layer on the side and the thickness of the silicon substrate is less than or equal to 80%, the forward leakage, hot spot risk and side protection of the back-contact battery can be regulated by adjusting the maximum extension length of the insulating mask layer on the side according to the actual application scenario requirements of the back-contact battery, which is conducive to achieving the balance between the forward leakage, hot spot risk and side protection of the back-contact battery. As for the thickness of the insulating mask layer on the side of the silicon substrate, its thickness on the side of the silicon substrate may be substantially the same along the direction from the backlight surface to the light-receiving surface. Alternatively, as shown in FIG. 14, on the side of the silicon substrate 100, the thickness of the insulating mask layer 21 gradually increases along the direction from the light-receiving surface to the backlight surface. The application principle of the beneficial effect in this case is similar to the application principle of the beneficial effect that the thickness of the surface passivation layer 13 on the side of the silicon substrate 100 gradually increases along the direction from the backlight surface to the light-receiving surface as described above, and will not be elaborated here. As a possible implementation, a doped layer may also be formed in the side of the silicon substrate. The dopant in the doped layer includes the dopant in the first doped silicon layer. In this case, when the first doped silicon layer is formed, by controlling the manufacturing process, the concentration of the dopant in the first doped silicon layer, the thickness of the first doped silicon layer, and the thickness and compactness of the first interface passivation layer, etc., part of the dopant in the first doped silicon layer passes through the first interface passivation layer and enters the side region of the silicon substrate to form the doped layer; or the doped layer and the first doped silicon layer may be formed separately. Based on this, a high-low junction may be formed between the doped layer and the first doped silicon layer, so that the energy band between the first doped silicon layer and the side of the silicon substrate is more matched, the passivation effect of the first doped silicon layer on the side of the silicon substrate is improved, and the open-circuit voltage of the back-contact battery is increased. Specifically, the formation range of the doped layer, the doping concentration of the dopant in the doped layer, etc. may be determined according to the formation range of the first interface passivation layer and the first doped silicon layer on the side, the thickness and compactness of the first interface passivation layer, and the doping concentration of the first doped silicon layer, or according to actual requirements, and no specific limitation is made here. Next, with reference to FIG. 15, the structure of the solar cell of some other embodiments of the first aspect of the present application will be described in detail. Referring to FIG. 15, FIG. 15 shows a schematic diagram of a back-contact battery according to an embodiment of the present application. The solar cell is a back-contact battery; the first conductive layer 202 is the first doped silicon layer 12, the second conductive layer 205 is the second doped silicon layer 16, and the insulating layer 203 includes the insulating mask layer 21. Specifically, as shown in FIG. 15, the back-contact battery includes: a silicon substrate, a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16, and a transparent conductive layer 208. The silicon substrate includes a backlight surface and a light-receiving surface disposed opposite to each other, and a side surface connecting the backlight surface and the light-receiving surface. Along the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15, the second doped silicon layer 16, and the transparent conductive layer 208 are sequentially disposed on the side surface. The conduction types of the first doped silicon layer 12 and the second doped silicon layer 16 are opposite. Among them, the back-contact battery includes a surface passivation layer 13 disposed on the light-receiving surface, and the surface passivation layer 13 extends from the light-receiving surface to the side surface; the back-contact battery further includes a second interface passivation layer 22 disposed on the backlight surface and located between the silicon substrate and the second doped silicon layer 16, and the second interface passivation layer 22 extends from the backlight surface to the side surface; on the side surface, the intrinsic silicon layer 15 includes the surface passivation layer 13 and the second interface passivation layer 22 stacked along the direction away from the side surface. It can be understood that in this part, the first interface passivation layer 20 can also be referred to as the aforementioned first passivation layer 201, the intrinsic silicon layer 15 can also be referred to as the aforementioned second passivation layer 204, and "along the direction away from the side surface" is also "along the direction away from the silicon substrate". In the case of adopting the above technical solution, in addition to the intrinsic silicon layer disposed between the first doped silicon layer and the second doped silicon layer, an insulating mask layer is also provided, which can not only ensure the reduction of the forward leakage loss, but also reduce the thickness requirement of the intrinsic silicon layer, reduce the tunneling resistance of the intrinsic silicon layer, facilitate improving the carrier collection efficiency of the second doped silicon layer disposed on one side of the backlight surface of the silicon substrate, and further improve the conversion efficiency of the back-contact battery. Moreover, the presence of the insulating mask layer can also enhance the protection effect on the side surface of the silicon substrate and further improve the side structure reliability of the back-contact battery. In the above case, as shown in FIG. 15, the back contact battery includes a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16, and a transparent conductive layer 208, which are disposed not only on the side surface of the silicon substrate 100 but also on the backlight surface of the silicon substrate 100. Specifically, on one side of the backlight surface of the silicon substrate 100, the transparent conductive layer 208 covers the sides of the first doped silicon layer 12 and the second doped silicon layer 16 facing away from the silicon substrate 100, and through isolation grooves are provided in the transparent conductive layer 208 to disconnect the portion of the transparent conductive layer 208 corresponding to the first doped silicon layer 12 from the portion of the transparent conductive layer 208 corresponding to the second doped silicon layer 16, preventing short circuits. As for the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15, and the second doped silicon layer 16 on one side of the backlight surface of the silicon substrate 100, reference may be made to the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15, and the second doped silicon layer 16 on one side of the backlight surface of the silicon substrate 100 described in the previous description of FIGS. 8 - 14, and no specific limitation is made here. In addition, among the side surfaces of the back contact battery, the second doped silicon layer can be in direct contact with the transparent conductive layer. Alternatively, as shown in FIG. 15, the back contact battery may further include an antireflection layer 207 disposed on the light-receiving surface, and the antireflection layer 207 extends from the light-receiving surface to the side surface. On the side surface, the antireflection layer 207 is disposed between the second doped silicon layer 16 and the transparent conductive layer 208 in a direction away from the side surface. In this case, an additional antireflection layer is added to the film layers disposed on the side surface of the silicon substrate, which can further improve the protection of the side surface of the silicon substrate, reduce the risk of damage to the side surface of the silicon substrate, and reduce the forward leakage loss. In addition, in this case, the antireflection layer is directly formed on the side of the second doped silicon layer facing away from the silicon substrate. Due to the difference between the materials of the surface passivation layer and the second doped silicon layer, and the antireflection layer is more likely to be deposited on the surface passivation layer. Based on this, compared with the antireflection layer being directly formed on the surface passivation layer, when the antireflection layer is directly formed on the side of the second doped silicon layer facing away from the silicon substrate, the plating-around range of the antireflection layer on the backlight surface side can be reduced, thereby reducing the etching amount when removing the plating-around of the antireflection layer on the backlight surface and improving the manufacturing efficiency. The insulating mask layer can cover all regions on the side surface. Alternatively, as shown in FIG. 15, the insulating mask layer 21 can also be disposed on a partial region of the side surface and on the side close to the backlight surface. The coverage range of the insulating mask layer 21 on the side surface can refer to the corresponding description in the previous text, and will not be elaborated here. It should be understood that in the first aspect, the various features in different embodiments can be applied separately or combined as needed. Next, with reference to FIGS. 3 and 8, the structure and the like of the solar cell in some further embodiments of the first aspect of the present application will be described in detail. In some embodiments, the solar cell is a back-contact cell, comprising: a silicon substrate 100, a first interface passivation layer 20, a first doped silicon layer 12, a surface passivation layer 13, an antireflection layer 207, an intrinsic silicon layer 15, a second doped silicon layer 16, and a transparent conductive layer 208. The silicon substrate 100 includes a backlight surface and a light-receiving surface which are oppositely arranged, and a side surface connecting the backlight surface and the light-receiving surface. Along the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the surface passivation layer 13, the antireflection layer 207, the intrinsic silicon layer 15, the second doped silicon layer 16, and the transparent conductive layer 208 are sequentially arranged on the side surface. The conduction types of the first doped silicon layer 12 and the second doped silicon layer 16 are opposite. Wherein, along the thickness direction of the silicon substrate 100, the surface passivation layer 13 and the antireflection layer 207 are also sequentially arranged on the light-receiving surface, and the surface passivation layer 13 and the antireflection layer 207 extend from the light-receiving surface to the side surface. Wherein, the protective layer 200 includes the first doped silicon layer 12, the surface passivation layer 13, the antireflection layer 207, and the second doped silicon layer 16, and wherein, the insulating layer 203 includes the surface passivation layer 13 and the antireflection layer 207. The junction of the side surface 130 and the backlight surface 120 is the first position 130a, and the junction of the side surface 130 and the light-receiving surface 110 is the second position 130b. The thickness of the protective layer 200 at the first position 130a is D1, and the thickness of the protective layer 200 at the second position 130b is D2, satisfying: 1 < D1 / D2 ≤ 10; preferably, 2.5 ≤ D1 / D2 ≤ 10. In addition, the surface passivation layer 13 and the antireflection layer 207 are not only located on the light-receiving surface of the silicon substrate 100, but also extend to the side surface of the silicon substrate 100. At this time, on the side surface of the silicon substrate 100, the first doped silicon layer 12 and the second doped silicon layer 16 with opposite conduction types can be isolated by the surface passivation layer 13 and the antireflection layer 207, preventing the two from conducting and leaking electricity, reducing the forward leakage loss, and enabling the back-contact battery to have a high conversion efficiency. In addition, the part of the surface passivation layer 13 and the antireflection layer 207 disposed on the light-receiving surface can reduce the carrier recombination and the surface reflectivity. When they are extended to the side surface of the silicon substrate 100, they can also be used to isolate the first doped silicon layer 12 and the second doped silicon layer 16. There is no need to additionally form other insulating layers through other deposition steps to prevent leakage between the first doped silicon layer 12 and the second doped silicon layer 16, which can simplify the manufacturing process of the back-contact battery. At the same time, there is no need to consider the compatibility between the film layer for isolating the first doped silicon layer 12 and the second doped silicon layer 16 and other structures in the back-contact battery, ensuring that the back-contact battery has a high yield. At the same time, not only the first interface passivation layer 20 and the first doped silicon layer 12 disposed on the side surface of the silicon substrate 100 have a passivation effect on the silicon substrate 100, but also the surface passivation layer 13 that realizes the insulation isolation between the first doped silicon layer 12 and the second doped silicon layer 16 on the side surface can passivate the side surface of the silicon substrate 100, further reducing the carrier recombination rate on the side surface of the silicon substrate 100 and improving the conversion efficiency of the back-contact battery. And, by setting a reasonable value range of the ratio D1 / D2 between the thickness D1 of the protective layer 200 at the first position 130a and the thickness D2 of the protective layer 200 at the second position 130b on the side surface 130 of the silicon substrate 100, so that the thickness of the protective layer 200 on the side surface 130 of the silicon substrate 100 is different at different positions. In this way, it can not only effectively shield and protect the entire side surface 130 of the silicon substrate 100, but also appropriately reduce the material consumption required for preparing the protective layer 200. Furthermore, the thickness of the insulating layer 203 (i.e., the surface passivation layer 13 and the antireflection layer 207) on the backlight surface 120 is H2, the thickness of the insulating layer 203 at the first position 130a on the side surface 130 is H21, and the thickness of the insulating layer 203 at the second position 130b on the side surface 130 is H22, satisfying: H22 < H21 ≤ H2. For the technical effects of H22 < H21 ≤ H2, reference can be made to the previous text and will not be elaborated here. Further, the total thickness of the first passivation layer 201 (i.e., the first interface passivation layer 20) and the first conductive layer 202 (i.e., the first doped silicon layer 12) on the backlight surface 120 is H1, the total thickness of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 is H11, and the total thickness of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 is H12, satisfying: H12 < H11 ≤ H1. For the technical effects of H12 < H11 ≤ H1, reference can be made to the foregoing, and details will not be elaborated here. Further, the total thickness of the second passivation layer 204 (i.e., the intrinsic silicon layer 15) and the second conductive layer 205 (i.e., the second doped silicon layer 16) on the backlight surface 120 is H3, the total thickness of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side surface 130 is H31, and the total thickness of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side surface 130 is H32, satisfying: H32 < H31 ≤ H3. For the technical effects of H32 < H31 ≤ H3, reference can be made to the foregoing, and details will not be elaborated here. Next, with reference to FIG. 3 and FIG. 15, the structure and the like of the solar cell according to some other embodiments of the first aspect of the present application will be described in detail. In some other embodiments, the solar cell is a back-contact cell, including: a silicon substrate, a first interface passivation layer 20, a first doped silicon layer 12, an insulating mask layer 21, an intrinsic silicon layer 15, a second doped silicon layer 16, and a transparent conductive layer 208. The silicon substrate includes a backlight surface and a light-receiving surface disposed opposite to each other, and a side surface connecting the backlight surface and the light-receiving surface. Along the direction away from the side surface, the first interface passivation layer 20, the first doped silicon layer 12, the insulating mask layer 21, the intrinsic silicon layer 15, the second doped silicon layer 16, and the transparent conductive layer 208 are sequentially disposed on the side surface. The conductive types of the first doped silicon layer 12 and the second doped silicon layer 16 are opposite. Among them, the back-contact cell includes a surface passivation layer 13 disposed on the light-receiving surface, and the surface passivation layer 13 extends from the light-receiving surface to the side surface; the back-contact cell further includes a second interface passivation layer 22 disposed on the backlight surface and located between the silicon substrate and the second doped silicon layer 16, and the second interface passivation layer 22 extends from the backlight surface to the side surface; on the side surface, the intrinsic silicon layer 15 includes the surface passivation layer 13 and the second interface passivation layer 22 stacked along the direction away from the side surface. Among them, the protective layer 200 includes the first doped silicon layer 12, the insulating mask layer 21, and the second doped silicon layer 16, and among them, the insulating layer 203 includes the insulating mask layer 21. The junction of the side surface 130 and the backlight surface 120 is the first position 130a, and the junction of the side surface 130 and the light-receiving surface 110 is the second position 130b. The thickness of the protective layer 200 at the first position 130a is D1, and the thickness of the protective layer 200 at the second position 130b is D2, satisfying: 1 < D1 / D2 ≤ 10; preferably, 2.5 ≤ D1 / D2 ≤ 10. In addition to the intrinsic silicon layer disposed between the first doped silicon layer and the second doped silicon layer, an insulating mask layer is also provided. While ensuring a reduction in forward leakage loss, it can also reduce the thickness requirement for the intrinsic silicon layer, reduce the tunneling resistance of the intrinsic silicon layer, facilitate improving the carrier collection efficiency of the second doped silicon layer disposed on the backlight side of the silicon substrate, and further improve the conversion efficiency of the back contact battery. Moreover, the presence of the insulating mask layer can also enhance the protection of the side surface of the silicon substrate, further improving the side structure reliability of the back contact battery. And by setting a reasonable value range for the ratio D1 / D2 between the thickness D1 of the protective layer 200 at the first position 130a and the thickness D2 of the protective layer 200 at the second position 130b on the side surface 130 of the silicon substrate 100, so that the thickness of the protective layer 200 on the side surface 130 of the silicon substrate 100 is different at different positions. In this way, it can not only effectively shield and protect the entire side surface 130 of the silicon substrate 100, but also appropriately reduce the material consumption required for preparing the protective layer 200. Further, the thickness of the insulating layer 203 (i.e., the insulating mask layer 21) on the backlight surface 120 is H2, the thickness of the insulating layer 203 at the first position 130a on the side surface 130 is H21, and the thickness of the insulating layer 203 at the second position 130b on the side surface 130 is H22, satisfying: H22 < H21 ≤ H2. For the technical effects of H22 < H21 ≤ H2, reference can be made to the foregoing, and details are not described herein again. Further, the total thickness of the first passivation layer 201 (i.e., the first interface passivation layer 20) and the first conductive layer 202 (i.e., the first doped silicon layer 12) on the backlight surface 120 is H1, the total thickness of the first passivation layer 201 and the first conductive layer 202 at the first position 130a on the side surface 130 is H11, and the total thickness of the first passivation layer 201 and the first conductive layer 202 at the second position 130b on the side surface 130 is H12, satisfying: H12 < H11 ≤ H1. For the technical effects of H12 < H11 ≤ H1, reference can be made to the foregoing, and details are not described herein again. Further, the total thickness of the second passivation layer 204 (i.e., the intrinsic silicon layer 15) and the second conductive layer 205 (i.e., the second doped silicon layer 16) on the backlight surface 120 is H3, the total thickness of the second passivation layer 204 and the second conductive layer 205 at the first position 130a on the side surface 130 is H31, and the total thickness of the second passivation layer 204 and the second conductive layer 205 at the second position 130b on the side surface 130 is H32, satisfying: H32 < H31 ≤ H3. For the technical effects of H32 < H31 ≤ H3, reference can be made to the foregoing, and details are not described herein again. In a second aspect, as shown in FIGS. 16-18, a schematic diagram of another solar cell according to an embodiment of the present application is shown. As shown in FIG. 16, the back-contact battery includes: a silicon substrate 100, a first interface passivation layer 20, a first doped silicon layer 12, an intrinsic silicon layer 15, a second doped silicon layer 16, and a transparent conductive layer 208. The silicon substrate 100 includes a backlight surface and a light-receiving surface that are oppositely disposed, and a side surface connecting the backlight surface and the light-receiving surface. Along the direction away from the side surface, the first doped silicon layer 12, the intrinsic silicon layer 15, the second doped silicon layer 16, and the transparent conductive layer 208 are sequentially disposed on the side surface. On the side surface of the silicon substrate 100, the first doped silicon layer 12 and the intrinsic silicon layer 15 are in direct contact. Among them, the first doped silicon layer 12 and the second doped silicon layer 16 have opposite conduction types. In the case of adopting the above technical solution, as shown in FIG. 16, on the side surface of the silicon substrate 100, the first doped silicon layer 12 can be electrically connected to the second doped silicon layer 16 with the opposite conduction type through the intrinsic silicon layer 15, so as to form a diode structure with a lower reverse breakdown voltage on the side surface of the silicon substrate 100, reducing the hot spot risk of the back-contact battery. At the same time, the first doped silicon layer 12, the intrinsic silicon layer 15, and the second doped silicon layer 16 disposed on the side surface of the silicon substrate 100 can also passivate the side surface of the silicon substrate 100, reducing the carrier recombination rate on the side surface of the silicon substrate 100 and improving the conversion efficiency of the back-contact battery. Secondly, the first doped silicon layer 12, the intrinsic silicon layer 15, and the second doped silicon layer 16 disposed on the side surface of the silicon substrate 100 can also protect the side surface of the silicon substrate 100, reducing the risk of damage and leakage that are likely to occur due to the direct exposure of the side surface of the silicon substrate 100, and improving the structural reliability of the back-contact battery. In the above case, as shown in FIG. 16, the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15, the second doped silicon layer 16, and the transparent conductive layer 208 included in the back-contact battery are not only disposed on the side surface of the silicon substrate 100, but also disposed on the backlight surface of the silicon substrate 100. Specifically, on one side of the backlight surface of the silicon substrate 100, the transparent conductive layer 208 covers the sides of the first doped silicon layer 12 and the second doped silicon layer 16 away from the silicon substrate 100, and through isolation grooves are provided in the transparent conductive layer 208 to disconnect the portion of the transparent conductive layer 208 corresponding to the first doped silicon layer 12 from the portion of the transparent conductive layer 208 corresponding to the second doped silicon layer 16 to prevent short circuit. As for the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15, and the second doped silicon layer 16 on one side of the backlight surface of the silicon substrate 100, reference can be made to the distribution of the first interface passivation layer 20, the first doped silicon layer 12, the intrinsic silicon layer 15, and the second doped silicon layer 16 on one side of the backlight surface of the silicon substrate 100 in the first aspect described above, and no specific limitation is made here. It should be noted that the following is only used to illustrate the differences between the back-contact battery provided in the second aspect and the contact battery provided in the first aspect in the embodiments of the present application. The similarities between the back-contact battery provided in the second aspect and the contact battery provided in the first aspect, such as the conductivity type of the silicon substrate, the formation range and thickness of the first doped silicon layer on the side, and the formation range and thickness of the intrinsic silicon layer and the second doped silicon layer on the side, etc., can refer to the corresponding descriptions in the first aspect and will not be elaborated here. For the intrinsic silicon layer, the intrinsic silicon layer can be a single-layer structure. At this time, each part of the intrinsic silicon layer can form a selective contact structure with the second doped silicon layer to achieve selective absorption of carriers and can passivate the surface in contact with the silicon substrate. Alternatively, as shown in FIG. 17, the back-contact battery includes a surface passivation layer 13 disposed on the light-receiving surface, and the surface passivation layer 13 extends from the light-receiving surface to the side. And the back-contact battery further includes a second interface passivation layer 22 disposed on the backlight surface and located between the silicon substrate 100 and the second doped silicon layer 16, and the second interface passivation layer 22 extends from the backlight surface to the side. Based on this, on the side, the intrinsic silicon layer 15 includes the surface passivation layer 13 and the second interface passivation layer 22 stacked in a direction away from the side. In this case, on the side of the silicon substrate 100, there are two film layers, namely the surface passivation layer 13 and the second interface passivation layer 22, between the first doped silicon layer 12 and the second doped silicon layer 16. At this time, the intrinsic silicon layer 15 has a certain transmission resistance, which is beneficial to reducing the forward leakage current of the back-contact battery and is beneficial to balancing the conversion efficiency and hot spot risk of the back-contact battery. In addition, while obtaining a lower forward leakage current, there is no need to form a thicker intrinsic silicon layer 15, which results in a larger thickness of a single second interface passivation layer 22 or surface passivation layer 13, ensuring that the second interface passivation layer 22 has a lower tunneling resistance and the surface passivation layer 13 has a lower hindrance to light transmission, ensuring that the back-contact battery has a higher conversion efficiency. Among them, in the back-contact battery provided in the embodiments of the present application, the formation sequence of the surface passivation layer and the second interface passivation layer included in the intrinsic silicon layer is not specifically limited. It can be that the surface passivation layer is formed first and then the second interface passivation layer is formed. At this time, the intrinsic silicon layer includes the surface passivation layer and the second interface passivation layer arranged in sequence in a direction away from the side. Or, it can also be that the second interface passivation layer is formed first and then the surface passivation layer is formed. At this time, the intrinsic silicon layer includes the second interface passivation layer and the surface passivation layer arranged in sequence in a direction away from the side. Regarding the thickness of the intrinsic silicon layer on the side of the silicon substrate, as shown in FIGS. 16 and 17, on the side of the silicon substrate 100, the thicknesses of the respective parts of the intrinsic silicon layer 15 are the same. In this case, each part of the intrinsic silicon layer 15 provided on the side of the silicon substrate 100 has relatively high passivation performance and a protective effect, which can further reduce the carrier recombination rate on the side of the silicon substrate 100 and improve the structural reliability of the back contact battery. Alternatively, as shown in FIG. 18, on the side of the silicon substrate 100, the thickness of the intrinsic silicon layer 15 can also gradually increase in the direction from the light-receiving surface to the light-emitting surface. The application principle of the beneficial effects in this case can refer to the foregoing, and will not be elaborated here. Regarding the specific thickness of the intrinsic silicon layer provided on the side of the silicon substrate, it can be determined according to the anti-leakage requirements for the first doped silicon layer and the second doped silicon layer provided on the side of the silicon substrate in the actual application scenario, and no specific limitation is made here. Exemplarily, on the side of the silicon substrate, the thickness of the intrinsic silicon layer can be greater than or equal to 5 nm and less than or equal to 30 nm. In this case, on the side of the silicon substrate, when the thickness of the intrinsic silicon layer is within the above range, it is beneficial to prevent poor passivation performance and protective effect due to a relatively small thickness of the intrinsic silicon layer, ensure a relatively low carrier recombination rate and high structural reliability on the side, and at the same time, it is also beneficial to reduce the forward leakage loss of the back contact battery. It can also prevent the thickness of the second interface passivation layer (or the second interface passivation layer and the surface passivation layer) from being relatively large due to a relatively large thickness of the intrinsic silicon layer, ensure that the second interface passivation layer has a relatively low tunneling resistance, and the surface passivation layer has a relatively low hindrance to light transmission, ensuring that the back contact battery has a relatively high conversion efficiency. Optionally, as shown in FIG. 17, the back contact battery can further include an anti-reflection layer 207. On the light-receiving surface, the anti-reflection layer 207 is provided on the side of the surface passivation layer 13 away from the silicon substrate 100. The anti-reflection layer 207 extends from the light-receiving surface to the side, and on the side, the anti-reflection layer 207 is provided between the second doped silicon layer 16 and the transparent conductive layer 208. In this case, an additional anti-reflection layer 207 is added to the film layer provided on the side of the silicon substrate 100, which can further improve the protective effect on the side of the silicon substrate 100, reduce the risk of damage on the side of the silicon substrate 100, and reduce the forward leakage loss. In addition, in this case, the anti-reflection layer 207 is directly formed on the side of the second doped silicon layer 16 away from the silicon substrate 100. Compared with the anti-reflection layer 207 being directly formed on the surface passivation layer 13, when the anti-reflection layer 207 is directly formed on the side of the second doped silicon layer 16 away from the silicon substrate 100, the plating-around range of the anti-reflection layer 207 on the light-emitting surface side can be reduced, thereby reducing the etching amount when removing the plating-around of the anti-reflection layer 207 on the light-emitting surface and improving the manufacturing efficiency. Optionally, as shown in FIG. 18, the back-contact battery further includes a surface passivation layer 13 and an anti-reflection layer 207 that are sequentially disposed on the light-receiving surface along the thickness direction of the silicon substrate, and the surface passivation layer 13 and the anti-reflection layer 207 extend from the light-receiving surface to the side surface. Moreover, on the side surface and in a direction away from the side surface, the surface passivation layer 13 and the anti-reflection layer 207 are sequentially stacked between the second doped silicon layer 16 and the transparent conductive layer 208. In this case, the presence of the surface passivation layer 13 and the anti-reflection layer 207 can further improve the protection of the side surface of the silicon substrate 100 and reduce the risk of damage to the side surface of the silicon substrate 100. In a third aspect, an embodiment of the present application further provides a photovoltaic module, including the solar cell in any of the above embodiments. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples. In the above description, technical details such as the layout and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. Additionally, to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be combined advantageously. In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A solar cell, wherein, Comprising: A silicon substrate; The silicon substrate has an opposite light-receiving surface and a backlight surface, and a side surface disposed between the light-receiving surface and the backlight surface; A protective layer is provided on the side surface. Along the direction away from the silicon substrate, the protective layer includes a first conductive layer, an insulating layer, and a second conductive layer sequentially disposed on the side surface; the first conductive layer and the second conductive layer have opposite conductivity types.

2. The solar cell according to claim 1, wherein, Along the direction parallel to the backlight surface, the backlight surface has alternately arranged first regions and second regions; the first conductive layer is formed in the first region, and the second conductive layer is formed in the second region.

3. The solar cell according to claim 1, wherein, The protective layer further includes a first passivation layer located between the side surface and the first conductive layer, and a second passivation layer located between the insulating layer and the second conductive layer; Along the direction parallel to the backlight surface, the backlight surface has alternately arranged first regions and second regions; Along the direction away from the silicon substrate, the first passivation layer and the first conductive layer are sequentially formed in the first region, and the second passivation layer and the second conductive layer are sequentially formed in the second region; the insulating layer is provided between the first region and the second region.

4. The solar cell according to claim 3, wherein, The junction of the side surface and the backlight surface is the first position, the junction of the side surface and the light-receiving surface is the second position, and the thickness of the protective layer at the first position is greater than the thickness of the protective layer at the second position.

5. The solar cell according to claim 4, wherein The thickness of the protective layer at the first position is D1, and the thickness of the protective layer at the second position is D2, satisfying: 1 < D1 / D2 ≤ 10.

6. The solar cell according to claim 4, wherein, The thickness of the insulating layer on the backlight surface is H2, the thickness of the insulating layer on the side surface at the first position is H21, and the thickness of the insulating layer on the side surface at the second position is H22. H2, H21, and H22 satisfy at least one of the following relationships: H22 < H21 ≤ H2, 0.2 ≤ H22 / H21 < 1, 0.5 ≤ H21 / H2 ≤ 1, 0.2 ≤ H22 / H2 ≤ 0.

6.

7. The solar cell according to claim 4, wherein, The total thickness of the first passivation layer and the first conductive layer on the backlight surface is H1, the total thickness of the first passivation layer and the first conductive layer on the side surface at the first position is H11, and the total thickness of the first passivation layer and the first conductive layer on the side surface at the second position is H12. H1, H11, and H12 satisfy at least one of the following relationships: H12 < H11 ≤ H1, 0.2 ≤ H12 / H11 < 1, 0.5 ≤ H11 / H1 ≤ 1, 0.2 ≤ H12 / H1 ≤ 0.

6.

8. The solar cell according to claim 4, wherein, The total thickness of the second passivation layer and the second conductive layer on the backlight surface is H3, the total thickness of the second passivation layer and the second conductive layer at the first position on the side surface is H31, and the total thickness of the second passivation layer and the second conductive layer at the second position on the side surface is H32. H3, H31, and H32 satisfy at least one of the following relational expressions: H32 < H31 ≤ H3, 0.2 ≤ H32 / H31 < 1, 0.5 ≤ H31 / H3 ≤ 1, 0.2 ≤ H32 / H3 ≤ 0.

6.

9. The solar cell according to claim 4, wherein, The protective layer further includes a third passivation layer and an antireflection layer. The third passivation layer is disposed on a side of the second conductive layer away from the side surface, and the antireflection layer is disposed on a side of the third passivation layer away from the second conductive layer. In a direction away from the silicon substrate, the third passivation layer and the antireflection layer are sequentially formed on the light-receiving surface.

10. The solar cell according to claim 9, wherein, The total thickness of the third passivation layer and the antireflection layer on the light-receiving surface is H4, the total thickness of the third passivation layer and the antireflection layer at the first position on the side surface is H41, and the total thickness of the third passivation layer and the antireflection layer at the second position on the side surface is H42. H4, H41, and H42 satisfy at least one of the following relational expressions: H41 < H42 ≤ H4, 0.1 ≤ H42 / H41 < 1, 0.1 ≤ H41 / H4 ≤ 0.4, 0.5 ≤ H42 / H4 ≤ 0.

8.

11. The solar cell according to claim 4, wherein, The protective layer further includes a transparent conductive layer, and the transparent conductive layer is disposed on a side of the second conductive layer away from the side surface. The transparent conductive layer is provided in at least one of the first region and the second region, and the transparent conductive layer is disposed on a side of the first conductive layer and / or the second conductive layer away from the backlight surface.

12. The solar cell according to claim 11, wherein, The thickness of the transparent conductive layer on the backlight surface is H5, the thickness of the transparent conductive layer at the first position on the side surface is H51, and the thickness of the transparent conductive layer at the second position on the side surface is H52. H5, H51, and H52 satisfy at least one of the following relational expressions: H52 < H51 ≤ H5, 0.3 ≤ H52 / H51 < 1, 0.5 ≤ H51 / H5 ≤ 1, 0.2 ≤ H52 / H5 ≤ 0.

5.

13. The solar cell according to claim 1, wherein, The solar cell is a back contact cell. The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes a surface passivation layer and an antireflection layer. Wherein, the back contact cell includes: a first interface passivation layer, the first doped silicon layer, the surface passivation layer, the antireflection layer, an intrinsic silicon layer, the second doped silicon layer, and a transparent conductive layer, which are sequentially arranged on the side surface in a direction away from the silicon substrate. Wherein, in the thickness direction of the silicon substrate, the surface passivation layer and the antireflection layer are also sequentially arranged on the light-receiving surface, and the surface passivation layer and the antireflection layer extend from the light-receiving surface to the side surface.

14. The solar cell according to claim 13, wherein, The backlight surface includes a first region and a second region; the first interface passivation layer and the first doped silicon layer are located in the first region; the intrinsic silicon layer and the second doped silicon layer are located in the second region, extend from the second region to the first region, and cover part of the first interface passivation layer and the first doped silicon layer; The insulating layer further includes an insulating mask layer; the insulating mask layer is disposed between the first doped silicon layer on the side surface and the surface passivation layer, and the insulating mask layer is also disposed along the thickness direction of the silicon substrate between the intrinsic silicon layer and the first doped silicon layer on the backlight surface.

15. The solar cell according to claim 14, wherein, On the side surface of the silicon substrate, the thickness of the insulating mask layer gradually increases in the direction from the light-receiving surface to the backlight surface; And / or, the insulating mask layer disposed on the side surface is located on a partial region of the side surface; along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the insulating mask layer on the side surface to the thickness of the silicon substrate is less than or equal to 80%.

16. The solar cell according to claim 1, wherein, The solar cell is a back-contact cell; The first conductive layer is a first doped silicon layer, the second conductive layer is a second doped silicon layer, and the insulating layer includes an insulating mask layer; Wherein, the back-contact cell includes: a first interface passivation layer, the first doped silicon layer, the insulating mask layer, an intrinsic silicon layer, the second doped silicon layer, and a transparent conductive layer, which are sequentially disposed on the side surface in a direction away from the silicon substrate; wherein, the back-contact cell includes a surface passivation layer disposed on the light-receiving surface, and the surface passivation layer extends from the light-receiving surface to the side surface; the back-contact cell further includes a second interface passivation layer disposed on the backlight surface and between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the backlight surface to the side surface; on the side surface, the intrinsic silicon layer includes the surface passivation layer and the second interface passivation layer stacked in a direction away from the side surface.

17. The solar cell according to claim 16, wherein, The back-contact cell further includes an antireflection layer disposed on the light-receiving surface, and the antireflection layer extends from the light-receiving surface to the side surface; On the side surface, the antireflection layer is disposed between the second doped silicon layer and the transparent conductive layer in a direction away from the side surface.

18. The solar cell according to claim 13 or 16, wherein, The first interface passivation layer and the first doped silicon layer disposed on the side surface are only located on a partial region of the side surface and close to the backlight surface; Wherein, along the thickness direction of the silicon substrate, the ratio of the maximum extension length of the first interface passivation layer and the first doped silicon layer on the side surface to the thickness of the silicon substrate is greater than or equal to 70%; and / or, the surface of the region on the side surface that does not cover the first interface passivation layer and the first doped silicon layer is a textured surface, and the ratio of the maximum extension length of the textured surface on the side surface to the thickness of the silicon substrate is less than or equal to 30%; And / or, on the side surface, the surface reflectivity of the region that does not cover the first interface passivation layer and the first doped silicon layer is less than the surface reflectivity of the region that covers the first interface passivation layer and the first doped silicon layer; And / or, the surface of the region on the side surface that does not cover the first interface passivation layer and the first doped silicon layer is a matte surface; and / or, the surface of the region on the side surface that covers the first interface passivation layer and the first doped silicon layer is a polished surface.

19. The solar cell according to claim 13 or 16, wherein, The thicknesses of the respective parts of the first interface passivation layer and / or the first doped silicon layer are the same; And / or, on the side surface of the silicon substrate, the thicknesses of the surface passivation layer are equal, or the thickness of the surface passivation layer gradually increases in the direction from the backlight surface to the light-receiving surface; And / or, on the side surface of the silicon substrate, the thickness of at least one of the intrinsic silicon layer, the second doped silicon layer, and the transparent conductive layer gradually increases in the direction from the light-receiving surface to the backlight surface.

20. The solar cell according to claim 13 or 16, wherein The surface passivation layer provided on the side surface is located on a partial region of the side surface and is close to the light-receiving surface; in the thickness direction of the silicon substrate, the ratio of the maximum extension length of the surface passivation layer on the side surface to the thickness of the silicon substrate is less than or equal to 80%.

21. The solar cell according to claim 13 or 16, wherein, The material of the surface passivation layer includes at least one of aluminum oxide, intrinsic amorphous silicon, and doped silicon glass; And / or, The thickness of the first doped silicon layer is greater than or equal to 30 nm and less than or equal to 140 nm; And / or, The thickness of the intrinsic silicon layer is greater than or equal to 8 nm and less than or equal to 14 nm.

22. The solar cell according to claim 13 or 16, wherein, In the side surface of the silicon substrate, the region provided with the first interface passivation layer and the first doped silicon layer has a tower base-like texture structure; Wherein, the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower base-like texture structure.

23. The solar cell according to claim 13 or 16, wherein, The side surface of the silicon substrate has a tower base-like texture structure; Wherein, the thickness of the first interface passivation layer located at the bottom surface of the tower base-like texture structure is less than the thickness of the first interface passivation layer located at the side wall of the tower base-like texture structure; The thickness of the intrinsic silicon layer located at the bottom surface of the tower base-like texture structure is greater than the thickness of the intrinsic silicon layer located at the side wall of the tower base-like texture structure; and / or, the thickness of the second doped silicon layer located at the bottom surface of the tower base-like texture structure is greater than the thickness of the second doped silicon layer located at the side wall of the tower base-like texture structure.

24. The solar cell according to claim 13 or 16, wherein, A doped layer is formed in the side surface of the silicon substrate; the dopant in the doped layer includes the dopant in the first doped silicon layer.

25. A solar cell, the solar cell being a back-contact cell, wherein, The back contact battery includes: A silicon substrate, the silicon substrate includes a backlight surface and a light-receiving surface that are oppositely arranged, and a side surface connecting the backlight surface and the light-receiving surface; And, in the direction away from the side surface, a first interface passivation layer, a first doped silicon layer, an intrinsic silicon layer, a second doped silicon layer, and a transparent conductive layer are sequentially provided on the side surface; on the side surface of the silicon substrate, the first doped silicon layer and the intrinsic silicon layer are in direct contact; wherein, the conductive types of the first doped silicon layer and the second doped silicon layer are opposite.

26. The solar cell according to claim 25, wherein, The back-contact battery includes a surface passivation layer disposed on the light-receiving surface, and the surface passivation layer extends from the light-receiving surface to the side surface; the back-contact battery further includes a second interface passivation layer disposed on the backlight surface and located between the silicon substrate and the second doped silicon layer, and the second interface passivation layer extends from the backlight surface to the side surface; On the side surface, the intrinsic silicon layer includes the surface passivation layer and the second interface passivation layer which are stacked in a direction away from the side surface; And / or, on the side surface of the silicon substrate, the thicknesses of the respective portions of the intrinsic silicon layer are the same; And / or, on the side surface of the silicon substrate, the thickness of the intrinsic silicon layer is greater than or equal to 5 nm and less than or equal to 30 nm.

27. The solar cell according to claim 26, wherein, The back-contact battery further includes an antireflection layer; on the light-receiving surface, the antireflection layer is disposed on a side of the surface passivation layer away from the silicon substrate; the antireflection layer extends from the light-receiving surface to the side surface, and on the side surface, the antireflection layer is disposed between the second doped silicon layer and the transparent conductive layer.

28. The solar cell according to claim 25, wherein The back-contact battery further includes a surface passivation layer and an antireflection layer which are sequentially disposed on the light-receiving surface along the thickness direction of the silicon substrate, and the surface passivation layer and the antireflection layer extend from the light-receiving surface to the side surface; On the side surface and in a direction away from the side surface, the surface passivation layer and the antireflection layer are sequentially stacked between the second doped silicon layer and the transparent conductive layer.

29. The solar cell according to claim 25, wherein, A doped layer is formed in the side surface of the silicon substrate; the dopant in the doped layer includes the dopant in the first doped silicon layer.

30. A photovoltaic module, wherein, The photovoltaic module includes the solar cell according to any one of claims 1-24, or the photovoltaic module includes the solar cell according to any one of claims 25-29.

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