Pixel driving circuit and driving method therefor, and display apparatus

Abstract

A pixel driving circuit and a driving method therefor, and a display apparatus. The pixel driving circuit is electrically connected to a light-emitting device (L), and the pixel driving circuit comprises: a current control sub-circuit and a duration control sub-circuit, wherein the duration control sub-circuit is electrically connected to both a ramp signal end (SWP) and the current control sub-circuit, and is configured to provide a second driving signal to the current control sub-circuit under the control of a signal of the ramp signal end (SWP); and the current control sub-circuit is electrically connected to the light-emitting device (L), and is configured to provide a first driving signal to the light-emitting device (L) under the control of the second driving signal. The signal of the ramp signal end (SWP) is a reference signal during at least part of the time, and is a ramp signal during at least part of the time, wherein the voltage value of the reference signal is greater than the voltage value of the ramp signal within at least part of a period of time.

Description

Pixel driving circuit and driving method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs), quantum-dot light-emitting diodes (QLEDs), and micro-LEDs are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs, QLEDs, or micro-LEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit electrically connected to a light emitting device, wherein the pixel driving circuit comprises: a current control subcircuit and a duration control subcircuit;

[0006] The duration control subcircuit is electrically connected to the ramp signal terminal and the current control subcircuit, respectively, and is configured to provide a second drive signal to the current control subcircuit under the control of the signal of the ramp signal terminal;

[0007] The current control subcircuit is electrically connected to the light emitting device and is configured to provide a first driving signal to the light emitting device under the control of the second driving signal;

[0008] The signal at the ramp signal end is a reference signal at least part of the time and a ramp signal at least part of the time;

[0009] The voltage value of the reference signal is greater than the voltage value of the ramp signal during at least a partial time period.

[0010] In an exemplary embodiment, the duration control subcircuit includes: a ramp control subcircuit and a duration drive subcircuit;

[0011] The ramp control subcircuit is electrically connected to the ramp signal terminal and the fifth node, respectively, and is configured to provide the signal of the ramp signal terminal to the fifth node;

[0012] The duration driving sub-circuit is electrically connected to the fifth node and is configured to provide a second driving signal to the current control sub-circuit under the control of a signal at the fifth node.

[0013] In an exemplary embodiment, the ramp control subcircuit is further electrically connected to a first reset signal terminal, and is configured to provide the signal of the ramp signal terminal to the fifth node under the control of the signal of the first reset signal terminal.

[0014] In an exemplary embodiment, the ramp control subcircuit is configured to provide the signal of the ramp signal terminal to the fifth node under the control of the signal of the ramp signal terminal.

[0015] In an exemplary embodiment, the ramp control subcircuit includes: an eighth transistor;

[0016] The control electrode and the first electrode of the eighth transistor are electrically connected to the ramp signal terminal respectively, and the second electrode of the eighth transistor is electrically connected to the fifth node.

[0017] In an exemplary embodiment, the ramp control subcircuit is configured to provide the signal of the ramp signal terminal to the fifth node under the control of the signal of the fifth node.

[0018] In an exemplary embodiment, the ramp control subcircuit includes: an eighth transistor;

[0019] The control electrode and the second electrode of the eighth transistor are electrically connected to the fifth node respectively, and the first electrode of the eighth transistor is electrically connected to the ramp signal terminal.

[0020] In an exemplary embodiment, the ramp control subcircuit includes: an eighth transistor;

[0021] The control electrode of the eighth transistor is electrically connected to the first reset signal terminal, the first electrode of the eighth transistor is electrically connected to the ramp signal terminal, and the second electrode of the eighth transistor is electrically connected to the fifth node.

[0022] In an exemplary embodiment, the ramp control subcircuit includes: an eighth transistor and a second capacitor:

[0023] a control electrode of the eighth transistor electrically connected to the first reset signal terminal, a first electrode of the eighth transistor electrically connected to the ramp signal terminal, and a second electrode of the eighth transistor electrically connected to the fifth node;

[0024] A first end of the second capacitor is electrically connected to the ramp signal end, and a second end of the second capacitor is electrically connected to the fifth node.

[0025] In an exemplary embodiment, the duration control subcircuit is further electrically connected to the initial signal terminal, and the duration driving subcircuit includes: a ninth transistor; a control electrode of the ninth transistor is electrically connected to the fifth node;

[0026] The initial signal at the initial signal end and the reference signal satisfy the following relationship:

[0027] Vref-Vth8-Vinit>Vth9

[0028] Wherein, Vref is the voltage value of the reference signal, Vinit is the voltage value of the initial signal, Vth8 is the threshold voltage of the eighth transistor, and Vth9 is the threshold voltage of the ninth transistor.

[0029] In an exemplary embodiment, the duration control subcircuit is further electrically connected to the duration data signal terminal, and the duration driving subcircuit includes: a ninth transistor; a control electrode of the ninth transistor is electrically connected to the fifth node;

[0030] The duration data signal at the duration data signal terminal and the reference signal satisfy the following relationship:

[0031] Vref-V DataT <Vth8

[0032] Where Vref is the voltage value of the reference signal, V DataT is the voltage value of the duration data signal, and Vth8 is the threshold voltage of the eighth transistor.

[0033] In an exemplary embodiment, the duration control subcircuit is further electrically connected to the first light emitting signal terminal;

[0034] The time when the signal at the ramp signal end is a reference signal does not overlap with the time when the signal at the first luminous signal end is a valid level signal, and the time when the signal at the ramp signal end is a ramp signal at least partially overlaps with the time when the signal at the first luminous signal end is a valid level signal.

[0035] In an exemplary embodiment, the duration control subcircuit further includes: a duration node control subcircuit and a duration light emission control subcircuit;

[0036] The duration driving sub-circuit is further electrically connected to the fifth node, the sixth node and the first node respectively, and is configured to provide a second driving signal to the first node under the control of the signals of the fifth node and the sixth node;

[0037] The duration lighting control subcircuit is electrically connected to the first lighting signal terminal, the second lighting signal terminal, the first power terminal, the second power terminal, the sixth node, and the first node, respectively, and is configured to provide a signal from the first power terminal to the first node and a signal from the second power terminal to the sixth node under the control of signals from the first lighting signal terminal and the second lighting signal terminal;

[0038] The duration node control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the second power supply terminal, the second reset signal terminal, the first scan signal terminal, the fifth node and the sixth node, respectively, and is configured to provide the signal of the duration data signal terminal to the fifth node and the signal of the initial signal terminal to the sixth node under the control of the signals of the second reset signal terminal and the first scan signal terminal.

[0039] In an exemplary embodiment, the duration driving subcircuit includes: a ninth transistor, the duration node control subcircuit includes: a seventh transistor, a tenth transistor, a third capacitor, and a fourth capacitor, and the duration light emitting control subcircuit includes: an eleventh transistor and a twelfth transistor;

[0040] The control electrode of the seventh transistor is electrically connected to the second reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the sixth node;

[0041] a control electrode of the ninth transistor electrically connected to the fifth node, a first electrode of the ninth transistor electrically connected to the first node, and a second electrode of the ninth transistor electrically connected to the sixth node;

[0042] The control electrode of the tenth transistor is electrically connected to the first scan signal terminal, the first electrode of the tenth transistor is electrically connected to the duration data signal terminal, and the second electrode of the tenth transistor is electrically connected to the fifth node;

[0043] The control electrode of the eleventh transistor is electrically connected to the second light emitting signal terminal, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the first node;

[0044] The control electrode of the twelfth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the twelfth transistor is electrically connected to the second power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the sixth node;

[0045] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the sixth node;

[0046] A first end of the fourth capacitor is electrically connected to the sixth node, and a second end of the fourth capacitor is electrically connected to the second power supply end.

[0047] In an exemplary embodiment, the duration control subcircuit further includes: a duration node control subcircuit and a duration light emission control subcircuit;

[0048] The duration driving sub-circuit is further electrically connected to the fifth node, the sixth node, and the seventh node, respectively, and is configured to provide a second driving signal to the seventh node under the control of the signals of the fifth node and the sixth node;

[0049] The duration lighting control subcircuit is electrically connected to the first lighting signal terminal, the second lighting signal terminal, the first power terminal, the second power terminal, the sixth node, and the seventh node, respectively, and is configured to provide the signal of the first power terminal to the seventh node and the signal of the second power terminal to the sixth node under the control of the signals of the first lighting signal terminal and the second lighting signal terminal;

[0050] The duration node control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the second power supply terminal, the second reset signal terminal, the first scan signal terminal, the second scan signal terminal, the first node, the fifth node, the sixth node and the seventh node, respectively, and is configured to provide the signal of the duration data signal terminal to the fifth node, the signal of the initial signal terminal to the sixth node, and the signal of the seventh node to the first node under the control of the signals of the second reset signal terminal, the first scan signal terminal and the second scan signal terminal.

[0051] In an exemplary embodiment, the duration driving subcircuit includes: a ninth transistor, the duration node control subcircuit includes: a seventh transistor, a tenth transistor, a thirteenth transistor, a third capacitor, and a fourth capacitor, and the duration light emitting control subcircuit includes: an eleventh transistor and a twelfth transistor;

[0052] The control electrode of the seventh transistor is electrically connected to the second reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the sixth node;

[0053] a control electrode of the ninth transistor electrically connected to the fifth node, a first electrode of the ninth transistor electrically connected to the seventh node, and a second electrode of the ninth transistor electrically connected to the sixth node;

[0054] The control electrode of the tenth transistor is electrically connected to the first scan signal terminal, the first electrode of the tenth transistor is electrically connected to the duration data signal terminal, and the second electrode of the tenth transistor is electrically connected to the fifth node;

[0055] The control electrode of the eleventh transistor is electrically connected to the second light emitting signal terminal, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the seventh node;

[0056] The control electrode of the twelfth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the twelfth transistor is electrically connected to the second power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the sixth node;

[0057] a control electrode of the thirteenth transistor electrically connected to the second scan signal terminal, a first electrode of the thirteenth transistor electrically connected to the seventh node, and a second electrode of the thirteenth transistor electrically connected to the first node;

[0058] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the sixth node;

[0059] A first end of the fourth capacitor is electrically connected to the sixth node, and a second end of the fourth capacitor is electrically connected to the second power supply end.

[0060] In an exemplary embodiment, the light emitting device includes: a first electrode and a second electrode;

[0061] The current control subcircuit is electrically connected to the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal, the first node and the light-emitting device, respectively, and is configured to provide a first drive signal to the first pole of the light-emitting device under the control of the signals of the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal and the first node.

[0062] In an exemplary embodiment, the current control subcircuit includes: first to sixth transistors and a first capacitor;

[0063] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node;

[0064] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0065] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0066] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is connected to the current data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0067] The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0068] The control electrode of the sixth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting device;

[0069] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the fourth node;

[0070] The fourth node is electrically connected to the first electrode or the second electrode of the light emitting device.

[0071] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned pixel driving circuit.

[0072] In an exemplary embodiment, the invention further includes: a data unit electrically connected to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first light emitting signal terminal and the second light emitting signal terminal connected to the pixel driving circuit;

[0073] The content displayed by the display device includes: at least one display frame, in which the data unit is configured to provide a valid level signal to the first reset signal terminal and the second reset signal terminal in a first time period, and provide an invalid level signal to the first light-emitting signal terminal, the second light-emitting signal terminal and the first scan signal terminal; provide a valid level signal to the first reset signal terminal and the second light-emitting signal terminal in a second time period, and provide a valid level signal to the second reset signal terminal, the first light-emitting signal terminal and the first scan signal terminal; provide a valid level signal to the first scan signal terminal in a third time period, and provide an invalid level signal to the first reset signal terminal, the second reset signal terminal, the first light-emitting signal terminal and the second light-emitting signal terminal; provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first light-emitting signal terminal and the second light-emitting signal terminal in a fourth time period; provide a valid level signal to the first light-emitting signal terminal in a fifth time period, and provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal and the second light-emitting signal terminal.

[0074] In an exemplary embodiment, the data unit is also electrically connected to the second scanning signal terminal connected to the pixel driving circuit, and the data unit is configured to provide a valid level signal to the second scanning signal terminal in the second time period, the fourth time period and the fifth time period, and to provide an invalid level signal to the third scanning signal terminal in the first time period and the third time period.

[0075] In an exemplary embodiment, the data unit is further electrically connected to the ramp signal terminal connected to the pixel driving circuit, and is configured to provide a reference signal to the ramp signal terminal in the first time period to the fourth time period, and provide a ramp signal to the ramp signal terminal in the fifth time period.

[0076] In a third aspect, the present disclosure further provides a driving method for a pixel driving circuit, configured to drive the above-mentioned pixel driving circuit, the method comprising:

[0077] The duration control subcircuit provides a second drive signal to the current control subcircuit under the control of the signal at the ramp signal terminal;

[0078] The current control subcircuit provides the first driving signal to the light emitting device under the control of the second driving signal.

[0079] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0080] Summary of the Figures

[0081] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0082] FIG1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0083] FIG2 is a schematic diagram of the structure of a duration control subcircuit;

[0084] FIG3 is an equivalent circuit diagram 1 of the ramp control subcircuit;

[0085] FIG4 is a second equivalent circuit diagram of the ramp control subcircuit;

[0086] FIG5 is a third equivalent circuit diagram of the ramp control subcircuit;

[0087] FIG6 is a fourth equivalent circuit diagram of the ramp control subcircuit;

[0088] FIG7 is a structural diagram of a duration control subcircuit;

[0089] FIG8 is a partial equivalent circuit diagram of the duration control subcircuit provided in FIG7 ;

[0090] FIG9 is a second structural diagram of a duration control subcircuit;

[0091] FIG10 is a partial equivalent circuit diagram of the duration control subcircuit provided in FIG9 ;

[0092] FIG11 is a schematic structural diagram of a pixel driving circuit;

[0093] FIG12 is an equivalent circuit diagram of the current control subcircuit;

[0094] FIG13 is an equivalent circuit diagram 1 of a pixel driving circuit;

[0095] FIG14 is a second equivalent circuit diagram of a pixel driving circuit;

[0096] FIG15 is a third equivalent circuit diagram of a pixel driving circuit;

[0097] FIG16 is a fourth equivalent circuit diagram of a pixel driving circuit;

[0098] FIG17 is a fifth equivalent circuit diagram of a pixel driving circuit;

[0099] FIG18 is a sixth equivalent circuit diagram of a pixel driving circuit;

[0100] FIG19 is an equivalent circuit diagram 7 of a pixel driving circuit;

[0101] FIG20 is an equivalent circuit diagram of a pixel driving circuit;

[0102] FIG21 is an operation timing diagram of the pixel driving circuit provided in FIG13 to FIG16;

[0103] FIG22 is an operation timing diagram of the pixel driving circuit provided in FIG17 to FIG20.

[0104] Details

[0105] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0106] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0107] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0108] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0109] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0110] In this specification, a transistor refers to a device consisting of at least three elements: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode element, drain region, or drain electrode) and a source electrode (source electrode element, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0111] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0112] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0113] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0114] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0115] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0116] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0117] A display device includes multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit occupies a large space, and the display device cannot achieve a high pixel per inch (PPI).

[0118] Figure 1 is a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 1, the pixel driving circuit provided by an embodiment of the present disclosure is electrically connected to a light-emitting device and can be configured to drive the light-emitting device to emit light. The pixel driving circuit can include: a current control subcircuit and a duration control subcircuit.

[0119] As shown in Figure 1 , the duration control subcircuit is electrically connected to the ramp signal terminal SWP and the current control subcircuit, respectively, and is configured to provide a second drive signal to the current control subcircuit under the control of a signal from the ramp signal terminal SWP. The current control subcircuit is electrically connected to the light-emitting device and is configured to provide a first drive signal to the light-emitting device under the control of the second drive signal.

[0120] In an exemplary embodiment, the signal at the ramp signal terminal is a reference signal during at least a portion of the time and a ramp signal during at least a portion of the time, wherein the voltage value of the reference signal is greater than the voltage value of the ramp signal during at least a portion of the time period.

[0121] In an exemplary embodiment, the light-emitting device includes a current-driven device, and a current-type light-emitting diode may be used, such as a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED) or an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0122] In an exemplary embodiment, the light emitting device includes a first electrode, a second electrode, and an organic light emitting layer located between the first electrode and the second electrode. Exemplarily, the first electrode of the light emitting device is electrically connected to the current control subcircuit, and the second electrode of the light emitting device is electrically connected to the second power supply terminal VSS.

[0123] In an exemplary embodiment, the voltage value of the signal at the second power supply terminal VSS may be approximately -3V to -3.5V, and illustratively, the voltage value of the signal at the second power supply terminal VSS may be approximately -3.2V.

[0124] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0125] The pixel driving circuit provided in an embodiment of the present disclosure is electrically connected to a light-emitting device, wherein the pixel driving circuit includes: a current control subcircuit and a duration control subcircuit; the duration control subcircuit is electrically connected to the ramp signal terminal and the current control subcircuit, respectively, and is configured to provide a second driving signal to the current control subcircuit under the control of the signal at the ramp signal terminal. The current control subcircuit is electrically connected to the light-emitting device and is configured to provide a first driving signal to the light-emitting device under the control of the second driving signal. In an exemplary embodiment, the signal at the ramp signal terminal is a reference signal at least part of the time and a ramp signal at least part of the time. The voltage value of the reference signal is greater than the voltage value of the ramp signal at least part of the time period. The present disclosure can reduce the number of signal terminals connected to the pixel driving circuit by having the signal at the ramp signal terminal be a reference signal at least part of the time and a ramp signal at least part of the time, thereby achieving a high PPI of the display device.

[0126] Figure 2 is a schematic diagram of the structure of a duration control subcircuit. As shown in Figure 2, in an exemplary embodiment, the duration control subcircuit may include: a ramp control subcircuit and a duration drive subcircuit.

[0127] In an exemplary embodiment, as shown in FIG2 , the ramp control subcircuit is electrically connected to the ramp signal terminal SWP and the fifth node N5, respectively, and is configured to provide a signal from the ramp signal terminal SWP to the fifth node N5. The duration drive subcircuit is electrically connected to the fifth node N5 and is configured to provide a second drive signal to the current control subcircuit under control of the signal from the fifth node N5.

[0128] In an exemplary embodiment, as shown in FIG. 2 , the ramp control subcircuit is further electrically connected to the first reset signal terminal RST1 and configured to provide a signal of the ramp signal terminal SWP to the fifth node N5 under the control of the signal of the first reset signal terminal RST1 .

[0129] FIG3 is an equivalent circuit diagram of the ramp control subcircuit. As shown in FIG3 , in an exemplary embodiment, when the ramp control subcircuit is electrically connected to the ramp signal terminal SWP and the fifth node N5, the ramp control subcircuit can be configured to provide the signal of the ramp signal terminal SWP to the fifth node N5 under the control of the signal of the ramp signal terminal SWP.

[0130] In an exemplary embodiment, as shown in FIG3 , the ramp control subcircuit may include an eighth transistor T8 . The control electrode and first electrode of the eighth transistor T8 are respectively electrically connected to the ramp signal terminal SWP, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5 . In this embodiment, the control electrode and first electrode of the eighth transistor T8 are electrically connected to the ramp signal terminal SWP, i.e., the control electrode and first electrode of the eighth transistor T8 are connected to the same signal terminal, and the eighth transistor T8 acts as a diode.

[0131] In an exemplary embodiment, the eighth transistor T8 in FIG. 3 is an enhancement-mode transistor.

[0132] FIG4 is a second equivalent circuit diagram of the ramp control subcircuit. As shown in FIG4 , in an exemplary embodiment, when the ramp control subcircuit is electrically connected to the ramp signal terminal SWP and the fifth node N5, the ramp control subcircuit can be configured to provide a signal from the ramp signal terminal SWP to the fifth node N5 under control of a signal from the fifth node N5.

[0133] In an exemplary embodiment, as shown in FIG4 , the ramp control subcircuit may include an eighth transistor T8 . The control electrode and second electrode of the eighth transistor T8 are electrically connected to the fifth node N5 , respectively. The first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP . In this embodiment, the control electrode and second electrode of the eighth transistor T8 are connected to the same node, and the eighth transistor T8 acts as a diode.

[0134] In an exemplary embodiment, the eighth transistor T8 in FIG. 4 is a depletion-mode transistor.

[0135] FIG5 is a third equivalent circuit diagram of the ramp control subcircuit. As shown in FIG5 , in an exemplary embodiment, when the ramp control subcircuit is electrically connected to the ramp signal terminal SWP, the first reset signal terminal RST1, and the fifth node N5, the ramp control subcircuit may include an eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the first reset signal terminal RST1, the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5.

[0136] FIG6 is a fourth equivalent circuit diagram of a ramp control subcircuit. As shown in FIG6 , in an exemplary embodiment, when the ramp control subcircuit is electrically connected to the ramp signal terminal SWP, the first reset signal terminal RST1, and the fifth node N5, the ramp control subcircuit may include: an eighth transistor T8 and a second capacitor C2. The control electrode of the eighth transistor T8 is electrically connected to the first reset signal terminal RST1, the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the first terminal of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and the second terminal of the second capacitor C2 is electrically connected to the fifth node N5.

[0137] An exemplary structure of the ramp control subcircuit is shown in Figures 3 to 6. Those skilled in the art will readily appreciate that the implementation of the ramp control subcircuit is not limited thereto.

[0138] In an exemplary embodiment, Figure 7 is a schematic diagram of the structure of a duration control subcircuit, Figure 8 is a partial equivalent circuit diagram of the duration control subcircuit provided in Figure 7, Figure 9 is a schematic diagram of the structure of a duration control subcircuit, and Figure 10 is a partial equivalent circuit diagram of the duration control subcircuit provided in Figure 9. As shown in Figures 7 and 9, the duration control subcircuit may further include: a duration node control subcircuit and a duration light emission control subcircuit.

[0139] In an exemplary embodiment, as shown in FIG7 , the duration driving sub-circuit is further electrically connected to the fifth node N5, the sixth node N6, and the first node N1, respectively, and is configured to provide a second driving signal to the first node N1 under the control of the signals of the fifth node N5 and the sixth node N6; the duration light emitting control sub-circuit is electrically connected to the first light emitting signal terminal EM1, the second light emitting signal terminal EM2, the first power supply terminal VDD, the second power supply terminal VSS, the sixth node N6, and the first node N1, respectively, and is configured to provide a second driving signal to the first node N1 under the control of the signals of the first light emitting signal terminal EM1 and the second light emitting signal terminal EM2. A signal of the first power supply terminal VDD is provided to the sixth node N6, and a signal of the second power supply terminal VSS is provided to the sixth node N6; the duration node control sub-circuit is electrically connected to the duration data signal terminal DataT, the initial signal terminal INIT, the second power supply terminal VSS, the second reset signal terminal RST2, the first scan signal terminal Gate1, the fifth node N5 and the sixth node N6, respectively, and is configured to provide the signal of the duration data signal terminal DataT to the fifth node N5 and the signal of the initial signal terminal INIT to the sixth node N6 under the control of the signal of the second reset signal terminal RST2 and the first scan signal terminal Gate1.

[0140] In an exemplary embodiment, as shown in FIG8 , the duration driving subcircuit may include: a ninth transistor T9; the duration node control subcircuit may include: a seventh transistor T7, a tenth transistor T10, a third capacitor C3, and a fourth capacitor C4; and the duration light emission control subcircuit may include: an eleventh transistor T11 and a twelfth transistor T12. The control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, the first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and the second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; and the eleventh transistor T11 is electrically connected to the eleventh transistor T12. A control electrode of the eleventh transistor T11 is electrically connected to the second light-emitting signal terminal EM2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1; a control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0141] In an exemplary embodiment, as shown in FIG. 8 , the ninth transistor T9 is a driving transistor, and the seventh transistor T7 , the eighth transistor T8 , and the tenth transistor T10 to the twelfth transistor T12 are switching transistors.

[0142] In an exemplary embodiment, as shown in FIG9 , the duration driving sub-circuit is further electrically connected to the fifth node N5, the sixth node N6, and the seventh node N7, respectively, and is configured to provide a second driving signal to the seventh node N7 under the control of the signals of the fifth node N5 and the sixth node N6; the duration light emitting control sub-circuit is electrically connected to the first light emitting signal terminal EM1, the second light emitting signal terminal EM2, the first power supply terminal VDD, the second power supply terminal VSS, the sixth node N6, and the seventh node N7, respectively, and is configured to provide a signal of the first power supply terminal VDD to the seventh node N7 and a signal of the second power supply terminal VS to the sixth node N6 under the control of the signals of the first light emitting signal terminal EM1 and the second light emitting signal terminal EM2. S signal; the duration node control sub-circuit is electrically connected to the duration data signal terminal DataT, the initial signal terminal INIT, the second power supply terminal VSS, the second reset signal terminal RST2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first node N1, the fifth node N5, the sixth node N6 and the seventh node N7, respectively, and is configured to provide the signal of the duration data signal terminal DataT to the fifth node N5, the signal of the initial signal terminal INIT to the sixth node N6, and the signal of the seventh node N7 to the first node N1 under the control of the signals of the second reset signal terminal RST2, the first scan signal terminal Gate1 and the second scan signal terminal Gate2.

[0143] As shown in Figure 10, in an exemplary embodiment, the duration driving subcircuit includes: a ninth transistor T9, the duration node control subcircuit includes: a seventh transistor T7, a tenth transistor T10, a thirteenth transistor T13, a third capacitor C3 and a fourth capacitor C4, and the duration light emitting control subcircuit includes: an eleventh transistor T11 and a twelfth transistor T12. Among them, the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected to the seventh node N7, and the second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, the first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and the second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; the control electrode of the eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, and the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal V DD is electrically connected, a second electrode of the eleventh transistor T11 is electrically connected to the seventh node N7; a control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6; a control electrode of the thirteenth transistor T13 is electrically connected to the second scan signal terminal Gate2, a first electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7, and a second electrode of the thirteenth transistor T13 is electrically connected to the first node N1; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0144] In an exemplary embodiment, as shown in FIG. 10 , the ninth transistor T9 is a driving transistor, and the seventh transistor T7 , the eighth transistor T8 , and the tenth transistor T10 to the thirteenth transistor T13 are switching transistors.

[0145] In an exemplary embodiment, the configuration of the thirteenth transistor T13 facilitates the timing setting of the driver chip, and can provide a wider range of applications for the configuration of the driver chip, wherein the driver chip provides signals to multiple signal terminals connected to the pixel driving circuit.

[0146] Figures 8 and 10 illustrate an exemplary structure of a duration driving sub-circuit, an exemplary structure of a duration light-emitting control sub-circuit, and two exemplary structures of a duration node control sub-circuit. It is easy for those skilled in the art to understand that the implementation manners of the duration driving sub-circuit, the duration light-emitting control sub-circuit, and the duration node control sub-circuit are not limited thereto.

[0147] In an exemplary embodiment, the initial signal terminal INIT can continuously provide a constant voltage power signal.

[0148] In an exemplary embodiment, the first power supply terminal VDD can continuously provide a high voltage power signal.

[0149] In an exemplary embodiment, the voltage value of the signal of the first power supply terminal VDD can be about 2.5 volts (V) to 3 volts (V).

[0150] In an exemplary embodiment, the initial signal of the initial signal terminal INIT and the reference signal satisfy the following relationship: Vref - Vth8 - Vinit > Vth9, where Vref is the voltage value of the reference signal, Vinit is the voltage value of the initial signal, Vth8 is the threshold voltage of the eighth transistor T8, and Vth9 is the threshold voltage of the ninth transistor.

[0151] In an exemplary embodiment, the duration data signal of the duration data signal terminal DataT and the reference signal satisfy the following relationship: Vref - V DataT < Vth8, where V DataT is the voltage value of the duration data signal.

[0152] In an exemplary embodiment, the time when the signal of the ramp signal terminal SWP is the reference signal does not overlap with the time when the signal of the first light-emitting signal terminal EM1 is the valid level signal, and the time when the signal of the ramp signal terminal SWP is the ramp signal overlaps with the time when the signal of the first light-emitting signal terminal EM1 is the valid level signal at least partially.

[0153] In an exemplary embodiment, FIG. 11 is a schematic structural diagram of a pixel driving circuit. As shown in FIG. 11, a current control sub-circuit can be electrically connected to a current data signal terminal, an initial signal terminal INIT, a first power supply terminal VDD, a first scan signal terminal Gate1, a first reset signal terminal RST1, a first light-emitting signal terminal EM1, a first node N1, and a light-emitting device L respectively, and is configured to provide a first driving signal to the first pole of the light-emitting device L under the control of the signals of the current data signal terminal DataI, the initial signal terminal INIT, the first power supply terminal VDD, the first scan signal terminal Gate1, the first reset signal terminal RST1, the first light-emitting signal terminal EM1, and the first node N1.

[0154] In an exemplary embodiment, the light emitting device L includes a first electrode and a second electrode.

[0155] Figure 12 is an equivalent circuit diagram of the current control subcircuit. As shown in Figure 10, the current control subcircuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gat e1 is electrically connected, a first electrode of the fourth transistor T4 is electrically connected to the current data signal terminal, and a second electrode of the fourth transistor T4 is electrically connected to the third node N3; a control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2; a control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4.

[0156] In an exemplary embodiment, the fourth node N4 may be electrically connected to the first electrode of the light emitting device or the second electrode of the light emitting device. FIG12 illustrates the fourth node N4 and the first electrode of the light emitting device as an example.

[0157] In an exemplary embodiment, when the light-emitting device is an OLED or a QLED, the fourth node N4 is electrically connected to the first electrode of the light-emitting device; when the light-emitting device is a micro LED, the fourth node N4 is electrically connected to the first electrode of the light-emitting device or the second electrode of the light-emitting device. The present disclosure does not impose any limitations on this.

[0158] As shown in FIG12 , the third transistor T3 is a driving transistor, and the first transistor T1 , the second transistor T2 , and the fourth transistor T4 to the sixth transistor T6 are switching transistors.

[0159] Figure 12 shows an exemplary structure of a current control subcircuit. It will be readily understood by those skilled in the art that the implementation of the current control subcircuit is not limited thereto.

[0160] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0161] FIG13 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG13 , the current control subcircuit in the pixel driving circuit includes: first to sixth transistors T1 to T6 and a first capacitor C1, and the duration control subcircuit includes: seventh to twelfth transistors T7 to T12 and a third capacitor C3 and a fourth capacitor C4.Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, and the fourth transistor The first electrode of T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the control electrode of the seventh transistor T7 is electrically connected to the first reset signal terminal RST2. The second electrode is electrically connected to the sixth node N6; the control electrode and the first electrode of the eighth transistor T8 are electrically connected to the ramp signal terminal SWP respectively, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, the first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and the second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; the control electrode of the eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, and the eleventh transistor T A first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1; a control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0162] FIG14 is a second equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG14 , the current control subcircuit in the pixel driving circuit includes: first to sixth transistors T1 to T6 and a first capacitor C1, and the duration control subcircuit includes: seventh to twelfth transistors T7 to T12 and a third capacitor C3 and a fourth capacitor C4.Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, and the fourth transistor The first electrode of T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the control electrode of the seventh transistor T7 is electrically connected to the first reset signal terminal RST2. The second electrode is electrically connected to the sixth node N6; the control electrode and the second electrode of the eighth transistor T8 are electrically connected to the fifth node N5 respectively, and the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected to the first node N1, and the second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, the first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and the second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; the control electrode of the eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, and the eleventh transistor T A first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1; a control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0163] FIG15 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG15 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: a seventh transistor T7 to a twelfth transistor T12 and a third capacitor C3 and a fourth capacitor C4. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third The node N3 is electrically connected, the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode of the eighth transistor T8 is electrically connected to the first reset signal terminal RST1, the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, A first electrode of the ninth transistor T9 is electrically connected to the first node N1, and a second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; a control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, a first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and a second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; a control electrode of the eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1;A control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4. A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6. A first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0164] FIG16 is a fourth equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG16 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: a seventh transistor T7 to a twelfth transistor T12 and a second capacitor C2 and a fourth capacitor C4. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third The node N3 is electrically connected, the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode of the eighth transistor T8 is electrically connected to the first reset signal terminal RST1, the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, A first electrode of the ninth transistor T9 is electrically connected to the first node N1, and a second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; a control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, a first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and a second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; a control electrode of the eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1;A control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4. A first end of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and a second end of the second capacitor C2 is electrically connected to the fifth node N5. A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6. A first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0165] In an exemplary embodiment, at least one of the first to twelfth transistors T1 to T12 in the pixel driving circuits shown in FIG13 to FIG16 may be a P-type transistor or an N-type transistor. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0166] In an exemplary embodiment, the N-type transistor may be an oxide transistor. The active layer of the oxide transistor is made of an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0167] FIG17 is an equivalent circuit diagram 5 of a pixel driving circuit. In an exemplary embodiment, as shown in FIG17 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: a seventh transistor T7 to a thirteenth transistor T13 and a third capacitor C3 and a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L The control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode and the first electrode of the eighth transistor T8 are electrically connected to the ramp signal terminal SWP respectively, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected to the seventh node N7, and the second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1 is electrically connected, a first electrode of a tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and a second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; a control electrode of an eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the seventh node N7; a control electrode of a twelfth transistor T12 is electrically connected to the first light emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6;A control electrode of the thirteenth transistor T13 is electrically connected to the second scan signal terminal Gate2, a first electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7, and a second electrode of the thirteenth transistor T13 is electrically connected to the first node N1; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0168] FIG18 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG18 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: a seventh transistor T7 to a thirteenth transistor T13 and a third capacitor C3 and a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L The control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode and the second electrode of the eighth transistor T8 are electrically connected to the fifth node N5 respectively, and the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, the first electrode of the ninth transistor T9 is electrically connected to the seventh node N7, and the second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; the control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1 is electrically connected, a first electrode of a tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and a second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; a control electrode of an eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the seventh node N7; a control electrode of a twelfth transistor T12 is electrically connected to the first light emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6;A control electrode of the thirteenth transistor T13 is electrically connected to the second scan signal terminal Gate2, a first electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7, and a second electrode of the thirteenth transistor T13 is electrically connected to the first node N1; a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0169] FIG19 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG19 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: a seventh transistor T7 to a thirteenth transistor T13 and a third capacitor C3 and a fourth capacitor C4. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third The node N3 is electrically connected, the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode of the eighth transistor T8 is electrically connected to the first reset signal terminal RST1, the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, A first electrode of the ninth transistor T9 is electrically connected to the seventh node N7, and a second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; a control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, a first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and a second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; a control electrode of the eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the seventh node N7;A control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6. A control electrode of the thirteenth transistor T13 is electrically connected to the second scan signal terminal Gate2, a first electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7, and a second electrode of the thirteenth transistor T13 is electrically connected to the first node N1. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4. A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6. A first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0170] FIG20 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG20 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: a seventh transistor T7 to a thirteenth transistor T13 and a second capacitor C2 and a fourth capacitor C4. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third The node N3 is electrically connected, the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device L; the control electrode of the seventh transistor T7 is electrically connected to the second reset signal terminal RST2, the first electrode of the seventh transistor T7 is electrically connected to the initial signal terminal INIT, and the second electrode of the seventh transistor T7 is electrically connected to the sixth node N6; the control electrode of the eighth transistor T8 is electrically connected to the first reset signal terminal RST1, the first electrode of the eighth transistor T8 is electrically connected to the ramp signal terminal SWP, and the second electrode of the eighth transistor T8 is electrically connected to the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected to the fifth node N5, A first electrode of the ninth transistor T9 is electrically connected to the seventh node N7, and a second electrode of the ninth transistor T9 is electrically connected to the sixth node N6; a control electrode of the tenth transistor T10 is electrically connected to the first scan signal terminal Gate1, a first electrode of the tenth transistor T10 is electrically connected to the duration data signal terminal DataT, and a second electrode of the tenth transistor T10 is electrically connected to the fifth node N5; a control electrode of the eleventh transistor T11 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VDD, and a second electrode of the eleventh transistor T11 is electrically connected to the seventh node N7;A control electrode of the twelfth transistor T12 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal VSS, and a second electrode of the twelfth transistor T12 is electrically connected to the sixth node N6. A control electrode of the thirteenth transistor T13 is electrically connected to the second scan signal terminal Gate2, a first electrode of the thirteenth transistor T13 is electrically connected to the seventh node N7, and a second electrode of the thirteenth transistor T13 is electrically connected to the first node N1. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4. A first end of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and a second end of the second capacitor C2 is electrically connected to the fifth node N5. A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6. A first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0171] In an exemplary embodiment, at least one of the first to thirteenth transistors T1 to T13 in the pixel driving circuits provided in FIG. 17 to FIG. 20 may be a P-type transistor or an N-type transistor. Using transistors of the same type in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0172] In an exemplary embodiment, the N-type transistor may be an oxide transistor. The active layer of the oxide transistor is made of an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0173] In an exemplary embodiment, the first reset signal terminal RST1 is a single pulse signal and is an active level signal during the first and second time periods of at least one display frame, and is an inactive level signal during the third to fifth time periods. The first time period occurs before the second time period, the second time period occurs before the third time period, the third time period occurs before the fourth time period, and the fourth time period occurs before the fifth time period.

[0174] In an exemplary embodiment, the second reset signal terminal RST2 is a single pulse signal, and is a valid level signal in a first time period of at least one display frame, and is an invalid level signal in a second time period to a fifth time period.

[0175] In an exemplary embodiment, the first scan signal terminal Gate1 is a single pulse signal and is a valid level signal in the third time period of at least one display frame and is an invalid level signal in the first, second, fourth and fifth time periods.

[0176] In an exemplary embodiment, the signal of the first light emitting signal terminal EM1 is a single pulse signal, and is a valid level signal in the fifth time period of at least one display frame, and is an invalid level signal in the first to fourth time periods.

[0177] In an exemplary embodiment, the signal of the second light emitting signal terminal EM2 is a single pulse signal, and is a valid level signal in the second time period of at least one display frame, and is an invalid level signal in the first time period and the third time period to the fifth time period.

[0178] In an exemplary embodiment, before the signal at the first luminescence signal terminal EM1 reaches an active level (i.e., during the first to fourth time periods), the signal at the ramp signal terminal SWP serves as a reference signal. When the signal at the first luminescence signal terminal EM1 reaches an active level (i.e., during the fifth time period), the signal at the ramp signal terminal SWP serves as a ramp signal, with the voltage value of the ramp signal gradually increasing.

[0179] In an exemplary embodiment, the initial signal terminal INIT and the second power terminal VSS may be the same signal terminal.

[0180] In an exemplary embodiment, the time when the second scanning signal terminal Gate2 is an active level signal at least partially overlaps the time when the first emitting signal terminal EM1 is an active level signal. Exemplarily, the second scanning signal terminal Gate2 and the first emitting signal terminal EM1 can be the same signal terminal.

[0181] In an exemplary embodiment, when the second scanning signal terminal Gate2 and the first emitting signal terminal EM1 are different signal terminals, the signal of the second scanning signal terminal Gate2 includes two pulse signals. The second scanning signal terminal Gate2 is an active level signal during the second time period and the entire time period including the fourth time period and the fifth time period, and is an inactive level signal during the first time period and the third time period.

[0182] In an exemplary embodiment, at least one of the first capacitor C1 to the fourth capacitor C4 can be a capacitor device manufactured by a process. For example, the capacitor device can be realized by making a special capacitor electrode, and the multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, at least one of the first capacitor C1 to the fourth capacitor C4 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor in the first capacitor C1 to the fourth capacitor C4 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0183] Fig. 21 is an operation timing diagram of the pixel driving circuit provided in Fig. 13 to Fig. 16. The exemplary embodiments of the present disclosure are described below through the operation process of the pixel driving circuit illustrated in Fig. 13 to Fig. 16.

[0184] The pixel driving circuits in Figures 13 to 15 include twelve transistors (first transistor T1 to twelfth transistor T12) and three capacitors (first capacitor C1, third capacitor C3 to fourth capacitor C4). The pixel driving circuit in Figure 16 includes twelve transistors (first transistor T1 to twelfth transistor T12) and four capacitors (first capacitor C1 to fourth capacitor C4), and any transistor among the first transistor T1 to twelfth transistor T12 is an N-type transistor.

[0185] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG. 13 to FIG. 16 may include:

[0186] In the first phase S11, referred to as the initialization phase, the signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, while the first scan signal terminal Gate1, the first emission signal terminal EM1, and the second emission signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is a reference signal. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, and the tenth transistor T10 to the twelfth transistor T12 are turned off.

[0187] In the pixel driving circuit shown in FIG13 , since the eighth transistor T8 is an enhancement-mode transistor, it is turned on under the control of the reference signal at the ramp signal terminal SWP. In the pixel driving circuit shown in FIG14 , since the eighth transistor T8 is a depletion-mode transistor, it is turned on. In the pixel driving circuits shown in FIG15 and FIG16 , the eighth transistor T8 is turned on under the control of the signal at the first reset signal terminal RST1.

[0188] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is written to the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the initial signal terminal INIT is written to the sixth node N6, the sixth node N6 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the reference signal of the ramp signal terminal SWP is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. At the same time, since Vref-Vth8-Vinit>Vth9, the voltage difference between the fifth node N5 and the sixth node N6 can make the ninth transistor T9 turned on, and the signal of the sixth node N6 is written to the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The voltage difference between the first node N1 and the third node N3 can make the third transistor T3 turned on, and the light-emitting device L does not emit light. In this stage, the voltage value V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vinit, the light emitting device L does not emit light.

[0189] In an exemplary embodiment, the initialization of the fourth node N4 , the fifth node N5 , and the sixth node N6 may be performed in stages or simultaneously, which is not limited in the present disclosure.

[0190] In the second phase S12, referred to as the threshold compensation phase, the signals at the first reset signal terminal RST1 and the second emission signal terminal EM2 are high-level signals, while the signals at the second reset signal terminal RST2, the first scan signal terminal Gate1, and the first emission signal terminal EM1 are low-level signals. The signal at the ramp signal terminal SWP is a reference signal. The first transistor T1, the eighth transistor T8, and the eleventh transistor T11 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the twelfth transistor T12 are turned off.

[0191] In the pixel driving circuit shown in FIG13 , since the eighth transistor T8 is an enhancement-mode transistor, it is turned on under the control of the reference signal at the ramp signal terminal SWP. In the pixel driving circuit shown in FIG14 , since the eighth transistor T8 is a depletion-mode transistor, it is turned on. In the pixel driving circuits shown in FIG15 and FIG16 , the eighth transistor T8 is turned on under the control of the signal at the first reset signal terminal RST1.

[0192] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is continuously written into the fourth node N4, initializing (resetting) the fourth node N4, clearing the pre-stored voltage inside it, and completing the initialization. The eighth transistor T8 is turned on, and the reference signal of the ramp signal terminal SWP is written into the fifth node N5, initializing (resetting) the fifth node N5, clearing the pre-stored voltage inside it, and completing the initialization. The third transistor T3 and the ninth transistor T9 are continuously turned on, and the signal of the first power supply terminal VDD is written into the first node N1 through the turned-on eleventh transistor T11, so that the potential of the signal at the first node N1 gradually increases. The third transistor T3 is continuously turned on, and the signal of the first power supply terminal VDD is written into the sixth node N6 through the turned-on ninth transistor T9 and the turned-on eleventh transistor T11, so that the potential of the signal at the sixth node N6 gradually increases until the voltage value of the signal at the sixth node N6 reaches VDD. N6 =Vref-Vth9, at this time, the voltage stored in the third capacitor C3 is Vth9. When the voltage value of the signal at the sixth node N6 is V N6 =Vref-Vth9, the ninth transistor T9 starts to turn off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vref-Vth9, the light emitting device L does not emit light.

[0193] In the third phase S13, referred to as the data writing phase, the signal at the first scan signal terminal Gate1 is a high-level signal, while the first reset signal terminal RST1, the second reset signal terminal RST2, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is a reference signal. The current data signal terminal DataI is written with a current data signal, and the duration data signal terminal DataT is written with a duration data signal. The second transistor T2, the fourth transistor T4, and the tenth transistor T10 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 are turned off.

[0194] The second transistor T2 and the fourth transistor T4 are turned on, and the current data signal is charged to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 =V DataI +Vth3, V DataIis the voltage value of the current data signal, and Vth3 is the threshold voltage of the third transistor T3. The tenth transistor T10 is turned on, and the duration data signal is written into the fifth node N5. The voltage value of the signal at the fifth node N5 jumps from Vref in the previous stage to V in this stage DataT , V DataT is the voltage value of the duration data signal. Under the action of the third capacitor C3, the voltage value of the signal at the sixth node N6 jumps to V DataT -Vth9, and the ninth transistor T9 remains turned off. In this stage, the voltage value V N4 of the signal at the fourth node N4 = Vinit, and the voltage value V N5 of the signal at the fifth node N5 = V DataT , and the voltage value V N6 of the signal at the sixth node N6 = V DataT -Vth9, and the light-emitting device L does not emit light.

[0195] In the pixel driving circuit provided in FIGS. 第十三至图14, the duration data signal is written into the fifth node N5. Since Vref - V DataT < Vth8, therefore, the eighth transistor T8 is turned off. In the pixel driving circuits provided in FIGS. 15 and 16, under the control of the signal at the first reset signal terminal RST1, the eighth transistor T8 is turned off. When the eighth transistor T8 is turned off, the reference signal at the ramp signal terminal SWP will not be written into the fifth node N5, which can avoid the interference of the reference signal on the signal at the fifth node N5.

[0196] The fourth stage S14 is called the holding stage, and the signals at the first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals, and the signal at the ramp signal terminal SWP is the reference signal. The first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 to the twelfth transistor T12 are turned off. The third transistor T3 maintains the on state in the previous stage, and the ninth transistor T9 maintains the off state in the previous stage.

[0197] The fifth stage S15 is called the light-emitting stage, and the signal at the first light-emitting signal terminal EM1 is a high-level signal, and the signals at the first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the ramp signal. The fifth transistor T5, the sixth transistor T6, and the twelfth transistor T12 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are turned off.

[0198] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power signal from the first power supply terminal VDD provides a first driving signal to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, causing the light-emitting device L to emit light. As the voltage value of the ramp signal at the ramp signal terminal SWP gradually increases, the signal at the fifth node N5 gradually increases, and the ninth transistor T9 is turned on accordingly. The low-level signal from the second power supply terminal VSS is written to the first node N1 through the turned-on twelfth transistor T12 and ninth transistor T9, causing the third transistor N3 to turn off. At this time, the light-emitting device L does not emit light, thereby achieving control of the light-emission duration of the light-emitting device L by the duration control sub-current. That is, when the ninth transistor T9 is turned on, the light-emitting phase ends.

[0199] Figure 13 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases as the signal at the ramp signal terminal SWP increases, under the bootstrap effect of the first parasitic capacitance of the eighth transistor T8. The first parasitic capacitance is the capacitance between the gate electrode (also the first electrode) and the second electrode of the eighth transistor. Figure 14 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases as the signal at the ramp signal terminal SWP increases, under the bootstrap effect of the second parasitic capacitance of the eighth transistor T8. The second parasitic capacitance is the capacitance between the gate electrode (also the second electrode) and the first electrode of the eighth transistor. Figure 16 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases as the signal at the ramp signal terminal SWP increases, under the bootstrap effect of the third parasitic capacitance of the eighth transistor T8. The third parasitic capacitance is the capacitance between the first electrode and the second electrode of the eighth transistor. Figure 15 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases as the signal at the ramp signal terminal SWP increases, under the bootstrap effect of the second capacitor C2.

[0200] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode (ie, the first node N1) and the first electrode (the second node N2). DataI +Vth3, the voltage value of the signal at the second node N2 is Vdd, Vdd is the voltage value of the signal at the first power supply end, so the driving current of the third transistor T3 satisfies: I=K*(Vgs-Vth3) 2 =K*(V DataI -Vdd) 2

[0201] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0202] Fig. 22 is a timing diagram of the operation of the pixel driving circuit provided in Fig. 17 to Fig. 20. The exemplary embodiments of the present disclosure are described below through the operation process of the pixel driving circuit shown in Fig. 17 to Fig. 20.

[0203] The pixel driving circuits in Figures 17 to 19 include thirteen transistors (first transistor T1 to thirteen transistor T13) and three capacitors (first capacitor C1, third capacitor C3 to fourth capacitor C4), and the pixel driving circuit in Figure 20 includes thirteen transistors (first transistor T1 to thirteen transistor T13) and four capacitors (first capacitor C1 to fourth capacitor C4), and any transistor among the first transistor T1 to the thirteenth transistor T13 is an N-type transistor.

[0204] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG. 17 to FIG. 20 may include:

[0205] In the first phase S21, referred to as the initialization phase, the signals at the first reset signal terminal RST1 and the second reset signal terminal RST2 are high-level signals, while the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is a reference signal. The first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, and the tenth transistor T10 to the thirteenth transistor T13 are turned off.

[0206] In the pixel driving circuit shown in FIG16 , since the eighth transistor T8 is an enhancement-mode transistor, it is turned on under the control of the reference signal at the ramp signal terminal SWP. In the pixel driving circuit shown in FIG17 , since the eighth transistor T8 is a depletion-mode transistor, it is turned on. In the pixel driving circuits shown in FIG18 and FIG19 , the eighth transistor T8 is turned on under the control of the signal at the first reset signal terminal RST1.

[0207] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is written to the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The seventh transistor T7 is turned on, and the signal of the initial signal terminal INIT is written to the sixth node N6, the sixth node N6 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the reference signal of the ramp signal terminal SWP is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. At the same time, since Vref-Vth8-Vinit>Vth9, the voltage difference between the fifth node N5 and the sixth node N6 can make the ninth transistor T9 turned on, and the signal of the sixth node N6 is written to the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The voltage difference between the first node N1 and the third node N3 can make the third transistor T3 turned on, and the light-emitting device L does not emit light. In this stage, the voltage value V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vinit, the light emitting device L does not emit light.

[0208] In an exemplary embodiment, the initialization of the fourth node N4 , the fifth node N5 , and the sixth node N6 may be performed in stages or simultaneously, which is not limited in the present disclosure.

[0209] In the second phase S22, referred to as the threshold compensation phase, the signals at the first reset signal terminal RST1, the second scan signal terminal Gate2, and the second emission signal terminal EM2 are high-level signals, while the signals at the second reset signal terminal RST2, the first scan signal terminal Gate1, and the first emission signal terminal EM1 are low-level signals. The signal at the ramp signal terminal SWP is a reference signal. The first transistor T1, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, the seventh transistor T7, the tenth transistor T10, and the twelfth transistor T12 are turned off.

[0210] In the pixel driving circuit shown in FIG17 , since the eighth transistor T8 is an enhancement-mode transistor, it is turned on under the control of the reference signal at the ramp signal terminal SWP. In the pixel driving circuit shown in FIG18 , since the eighth transistor T8 is a depletion-mode transistor, it is turned on. In the pixel driving circuits shown in FIG19 and FIG20 , the eighth transistor T8 is turned on under the control of the signal at the first reset signal terminal RST1.

[0211] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is continuously written into the fourth node N4, initializing (resetting) the fourth node N4, clearing the pre-stored voltage inside it, and completing the initialization. The eighth transistor T8 is turned on, and the reference signal of the ramp signal terminal SWP is written into the fifth node N5, initializing (resetting) the fifth node N5, clearing the pre-stored voltage inside it, and completing the initialization. The third transistor T3 and the ninth transistor T9 are continuously turned on, and the signal of the first power supply terminal VDD is written into the first node N1 through the turned-on eleventh transistor T11 and the thirteenth transistor T13, so that the potential of the signal at the first node N1 gradually increases. The third transistor T3 is continuously turned on, and the signal of the first power supply terminal VDD is written into the sixth node N6 through the turned-on ninth transistor T9 and the eleventh transistor T11, so that the potential of the signal at the sixth node N6 gradually increases until the voltage value of the signal at the sixth node N6 reaches V N6 =Vref-Vth9, at this time, the voltage stored in the third capacitor C3 is Vth9. When the voltage value of the signal at the sixth node N6 is V N6 =Vref-Vth9, the ninth transistor T9 starts to turn off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vref-Vth9, the light emitting device L does not emit light.

[0212] In the third phase S23, referred to as the data writing phase, the signal at the first scanning signal terminal Gate1 is a high-level signal, while the first reset signal terminal RST1, the second reset signal terminal RST2, the first emission signal terminal EM1, the second scanning signal terminal Gate2, and the second emission signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is a reference signal. The current data signal terminal Data1 is written with a current data signal, and the duration data signal terminal DataT is written with a duration data signal. The second transistor T2, the fourth transistor T4, and the tenth transistor T10 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the eleventh through thirteenth transistors T11 through T13 are turned off.

[0213] The second transistor T2 and the fourth transistor T4 are turned on, and the current data signal is charged to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 =V DataI +Vth3, V DataIis the voltage value of the current data signal, and Vth3 is the threshold voltage of the third transistor T3. The tenth transistor T10 is turned on, and the duration data signal is written into the fifth node N5. The voltage value of the signal at the fifth node N5 jumps from Vref in the previous stage to V in this stage. DataT , V DataT is the voltage value of the duration data signal. Under the action of the third capacitor C3, the voltage value of the signal at the sixth node N6 jumps to V DataT - Vth9, and the ninth transistor T9 remains off. In this stage, the voltage value V N4 of the signal at the fourth node N4 = Vinit, the voltage value V N5 of the signal at the fifth node N5 = V DataT , and the voltage value V N6 of the signal at the sixth node N6 = V DataT - Vth9, and the light-emitting device L does not emit light.

[0214] In the pixel driving circuit provided in FIGS. 17 and 18, the duration data signal is written into the fifth node N5. Since Vref - V DataT < Vth8, therefore, the eighth transistor T8 is turned off. In the pixel driving circuit provided in FIGS. 19 and 20, under the control of the signal at the first reset signal terminal RST1, the eighth transistor T8 is turned off. When the eighth transistor T8 is turned off, the reference signal at the ramp signal terminal SWP will not be written into the fifth node N5, which can avoid the interference of the reference signal on the signal at the fifth node N5.

[0215] The fourth stage S24, called the sustain stage, the signal at the second scan signal terminal Gate2 is a high-level signal, and the signals at the first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals, and the signal at the ramp signal terminal SWP is a reference signal. The thirteenth transistor T13 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10 to the twelfth transistor T123 are turned off. The third transistor T3 maintains the on state in the previous stage, and the ninth transistor T9 maintains the off state in the previous stage.

[0216] In the fifth stage S25, referred to as the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the second scan signal terminal Gate2 are high-level signals, while the first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is a ramp signal. The fifth transistor T5, the sixth transistor T6, the twelfth transistor T12, and the thirteenth transistor T13 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, and the eleventh transistor T11 are turned off.

[0217] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power signal from the first power supply terminal VDD provides a first driving signal to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, causing the light-emitting device L to emit light. As the voltage value of the ramp signal at the ramp signal terminal SWP gradually increases, the signal at the fifth node N5 gradually increases, and the ninth transistor T9 is turned on accordingly. The low-level signal from the second power supply terminal VSS is written to the first node N1 through the turned-on twelfth transistor T12 and ninth transistor T9, causing the third transistor N3 to turn off. At this time, the light-emitting device L does not emit light, thereby achieving control of the light-emission duration of the light-emitting device L by the duration control sub-current. That is, when the ninth transistor T9 is turned on, the light-emitting phase ends.

[0218] FIG17 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases with the increase in the signal at the ramp signal terminal SWP due to the bootstrap effect of the first parasitic capacitance of the eighth transistor T8. The first parasitic capacitance is the capacitance between the gate electrode (also the first electrode) and the second electrode of the eighth transistor. FIG18 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases with the increase in the signal at the ramp signal terminal SWP due to the bootstrap effect of the second parasitic capacitance of the eighth transistor T8. The second parasitic capacitance is the capacitance between the gate electrode (also the second electrode) and the first electrode of the eighth transistor. FIG20 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases with the increase in the signal at the ramp signal terminal SWP due to the bootstrap effect of the third parasitic capacitance of the eighth transistor T8. The third parasitic capacitance is the capacitance between the first electrode and the second electrode of the eighth transistor. FIG19 shows that due to the gradual increase in the signal at the ramp signal terminal SWP, the signal at the fifth node N5 increases with the increase in the signal at the ramp signal terminal SWP due to the bootstrap effect of the second capacitor C2.

[0219] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode (ie, the first node N1) and the first electrode (the second node N2). DataI +Vth3, the voltage value of the signal at the second node N2 is Vdd, Vdd is the voltage value of the signal at the first power supply end, so the driving current of the third transistor T3 satisfies: I=K*(Vgs-Vth3) 2 =K*(V DataI -Vdd) 2

[0220] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0221] In an exemplary embodiment, in the current control subcircuit, the current data signal at the current data signal terminal DataT is compensated for at the first node N1 (i.e., the control electrode of the third transistor T3) via the fourth transistor T4, the third transistor T3, and the second transistor T2. During the compensation process, the third transistor T3 acts as a diode, meaning that the current control subcircuit utilizes diode compensation. This diode compensation reduces the impact of the parasitic capacitance of the light-emitting device L on the first drive signal, avoids data jumps caused by parasitic capacitance, and improves the reliability of the pixel drive circuit.

[0222] In an exemplary embodiment, in the duration control subcircuit, the power signal from the first power supply terminal VDD is extended to the sixth node N6 (i.e., the second electrode of the tenth transistor T10) via the twelfth transistor T12 and the tenth transistor T10. The duration control subcircuit employs a source-follower compensation method. This source-follower compensation method can extend the charging time, enabling the duration control subcircuit to more accurately control the light-emitting duration. Furthermore, the duration control subcircuit is not connected to the light-emitting device and is not affected by the parasitic capacitance of the light-emitting device L, further improving the reliability of the pixel driving circuit. The compensation time in the duration control subcircuit depends on the pulse length of the signal on the second light-emitting signal line EM2. The compensation time can be adjusted by adjusting the pulse length of the signal on the second light-emitting signal line EM2.

[0223] In an exemplary embodiment, the current control subcircuit may also adopt a source follower compensation method.

[0224] In an exemplary embodiment, the duration control subcircuit may also adopt a diode compensation method.

[0225] In an exemplary embodiment, the current control subcircuit and the duration control subcircuit of the present disclosure may employ different external compensation methods. For example, the current control subcircuit may employ a source-follower compensation method, and the duration control subcircuit may employ a diode compensation method, or alternatively, the current control subcircuit may employ a diode compensation method, and the duration control subcircuit may employ a source-follower compensation method.

[0226] In an exemplary embodiment, the current control subcircuit and the duration control subcircuit of the present disclosure may employ the same external compensation method. For example, the current control subcircuit may employ a source-follower compensation method, and the duration control subcircuit may employ a source-follower compensation method. Alternatively, the current control subcircuit may employ a diode compensation method, and the duration control subcircuit may employ a diode compensation method.

[0227] The present disclosure also provides a display device including a pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided in any of the above embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0228] In an exemplary embodiment, a display device may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, the display device may be one of a variety of electronic devices, and may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, VR devices, AR devices, wireless devices, personal data assistants (PS1s), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry), etc. The embodiments of the present disclosure do not impose any particular restrictions on the form of the above-mentioned display devices.

[0229] In an exemplary embodiment, the display device may further include a data unit electrically connected to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first light emitting signal terminal, and the second light emitting signal terminal connected to the pixel driving circuit.

[0230] In an exemplary embodiment, content displayed by a display device includes: at least one display frame, in which the data unit is configured to provide a valid level signal to the first reset signal terminal and the second reset signal terminal in a first time period, and provide an invalid level signal to the first light-emitting signal terminal, the second light-emitting signal terminal, and the first scan signal terminal; provide a valid level signal to the first reset signal terminal and the second light-emitting signal terminal in a second time period, and provide a valid level signal to the second reset signal terminal, the first light-emitting signal terminal, and the first scan signal terminal; provide a valid level signal to the first scan signal terminal in a third time period, and provide an invalid level signal to the first reset signal terminal, the second reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal; provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal in a fourth time period; provide a valid level signal to the first light-emitting signal terminal in a fifth time period, and provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, and the second light-emitting signal terminal.

[0231] In an exemplary embodiment, the data unit is also electrically connected to a second scanning signal terminal connected to the pixel driving circuit, and the data unit is configured to provide a valid level signal to the second scanning signal terminal in the second time period, the fourth time period, and the fifth time period, and to provide an invalid level signal to the third scanning signal terminal in the first time period and the third time period.

[0232] Exemplarily, the data unit may include a gate driving circuit.

[0233] In an exemplary embodiment, the data unit is further electrically connected to the ramp signal terminal connected to the pixel driving circuit, and is configured to provide a reference signal to the ramp signal terminal in the first time period to the fourth time period, and provide a ramp signal to the ramp signal terminal in the fifth time period.

[0234] The embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method of the pixel driving circuit may include the following steps:

[0235] Step 100: The duration control subcircuit provides a second drive signal to the current control subcircuit under the control of the signal at the ramp signal terminal.

[0236] Step 200: The current control subcircuit provides a first driving signal to the light emitting device under the control of a second driving signal.

[0237] The pixel driving circuit is the pixel driving circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be described in detail here.

[0238] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0239] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0240] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pixel driving circuit, electrically connected to a light-emitting device, wherein, The pixel driving circuit includes: a current control sub-circuit and a duration control sub-circuit; The duration control sub-circuit is electrically connected to the ramp signal terminal and the current control sub-circuit respectively, and is configured to provide a second driving signal to the current control sub-circuit under the control of the signal at the ramp signal terminal; The current control sub-circuit is electrically connected to the light-emitting device, and is configured to provide a first driving signal to the light-emitting device under the control of the second driving signal; The signal at the ramp signal terminal is a reference signal for at least part of the time and a ramp signal for at least part of the time; The voltage value of the reference signal is greater than the voltage value of the ramp signal in at least part of the time period.

2. The pixel driving circuit according to claim 1, wherein The duration control sub-circuit includes: a ramp control sub-circuit and a duration driving sub-circuit; The ramp control sub-circuit is electrically connected to the ramp signal terminal and a fifth node respectively, and is configured to provide the signal at the ramp signal terminal to the fifth node; The duration driving sub-circuit is electrically connected to the fifth node, and is configured to provide a second driving signal to the current control sub-circuit under the control of the signal at the fifth node.

3. The pixel driving circuit according to claim 2, wherein, The ramp control sub-circuit is further electrically connected to a first reset signal terminal, and is configured to provide the signal at the ramp signal terminal to the fifth node under the control of the signal at the first reset signal terminal.

4. The pixel driving circuit according to claim 2, wherein, The ramp control sub-circuit is configured to provide the signal at the ramp signal terminal to the fifth node under the control of the signal at the ramp signal terminal.

5. The pixel driving circuit according to claim 4, wherein, The ramp control sub-circuit includes: an eighth transistor; The control electrode and the first electrode of the eighth transistor are electrically connected to the ramp signal terminal respectively, and the second electrode of the eighth transistor is electrically connected to the fifth node.

6. The pixel driving circuit according to claim 2, wherein The ramp control sub-circuit is configured to provide the signal at the ramp signal terminal to the fifth node under the control of the signal at the fifth node.

7. The pixel driving circuit according to claim 6, wherein, The ramp control sub-circuit includes: an eighth transistor; The control electrode and the second electrode of the eighth transistor are electrically connected to the fifth node respectively, and the first electrode of the eighth transistor is electrically connected to the ramp signal terminal.

8. The pixel driving circuit according to claim 3, wherein, The ramp control sub-circuit includes: an eighth transistor; The control electrode of the eighth transistor is electrically connected to the first reset signal terminal, the first electrode of the eighth transistor is electrically connected to the ramp signal terminal, and the second electrode of the eighth transistor is electrically connected to the fifth node.

9. The pixel driving circuit according to claim 3, wherein, The ramp control sub-circuit includes: an eighth transistor and a second capacitor: The control electrode of the eighth transistor is electrically connected to the first reset signal terminal, the first electrode of the eighth transistor is electrically connected to the ramp signal terminal, and the second electrode of the eighth transistor is electrically connected to the fifth node; The first end of the second capacitor is electrically connected to the ramp signal terminal, and the second end of the second capacitor is electrically connected to the fifth node.

10. The pixel driving circuit according to any one of claims 3 to 9, wherein, The duration control sub-circuit is further electrically connected to an initial signal terminal, and the duration driving sub-circuit includes: a ninth transistor; the control electrode of the ninth transistor is electrically connected to the fifth node; The initial signal at the initial signal terminal and the reference signal satisfy the following relationship: Vref - Vth8 - Vinit > Vth9 Among them, Vref is the voltage value of the reference signal, Vinit is the voltage value of the initial signal, Vth8 is the threshold voltage of the eighth transistor, and Vth9 is the threshold voltage of the ninth transistor.

11. The pixel driving circuit according to any one of claims 3 to 9, wherein, The duration control sub-circuit is also electrically connected to the duration data signal terminal, and the duration driving sub-circuit includes: a ninth transistor; the control electrode of the ninth transistor is electrically connected to the fifth node; The duration data signal of the duration data signal terminal and the reference signal satisfy the following relationship: Vref-V DataT <Vth8 Among them, Vref is the voltage value of the reference signal, V DataT is the voltage value of the duration data signal, and Vth8 is the threshold voltage of the eighth transistor.

12. The pixel driving circuit according to claim 1, wherein, The duration control sub-circuit is also electrically connected to the first light-emitting signal terminal; The time when the signal at the ramp signal terminal is the reference signal and the time when the signal at the first light-emitting signal terminal is the valid level signal do not overlap, and the time when the signal at the ramp signal terminal is the ramp signal and the time when the signal at the first light-emitting signal terminal is the valid level signal overlap at least partially.

13. The pixel driving circuit according to any one of claims 2 to 9, wherein, The duration control sub-circuit further includes: a duration node control sub-circuit and a duration light-emitting control sub-circuit; The duration driving sub-circuit is also electrically connected to the fifth node, the sixth node, and the first node respectively, and is configured to provide a second driving signal to the first node under the control of the signals at the fifth node and the sixth node; The duration light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second power supply terminal, the sixth node, and the first node respectively, and is configured to provide the signal of the first power supply terminal to the first node and the signal of the second power supply terminal to the sixth node under the control of the signals at the first light-emitting signal terminal and the second light-emitting signal terminal; The duration node control sub-circuit is electrically connected to the duration data signal terminal, the initial signal terminal, the second power supply terminal, the second reset signal terminal, the first scan signal terminal, the fifth node, and the sixth node respectively, and is configured to provide the signal of the duration data signal terminal to the fifth node and the signal of the initial signal terminal to the sixth node under the control of the signals at the second reset signal terminal and the first scan signal terminal; 14. The pixel driving circuit according to claim 13, wherein, The duration driving sub-circuit includes: a ninth transistor, the duration node control sub-circuit includes: a seventh transistor, a tenth transistor, a third capacitor, and a fourth capacitor, and the duration light-emitting control sub-circuit includes: an eleventh transistor and a twelfth transistor; The control electrode of the seventh transistor is electrically connected to the second reset signal terminal, the first electrode of the seventh transistor is electrically connected to the initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the sixth node; The control electrode of the ninth transistor is electrically connected to the fifth node, the first electrode of the ninth transistor is electrically connected to the first node, and the second electrode of the ninth transistor is electrically connected to the sixth node; The control electrode of the tenth transistor is electrically connected to the first scan signal terminal, the first electrode of the tenth transistor is electrically connected to the duration data signal terminal, and the second electrode of the tenth transistor is electrically connected to the fifth node; The control electrode of the eleventh transistor is electrically connected to the second light-emitting signal terminal, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the first node; The control electrode of the twelfth transistor is electrically connected to the first light-emitting signal terminal, the first pole of the twelfth transistor is electrically connected to the second power supply terminal, and the second pole of the twelfth transistor is electrically connected to the sixth node; The first end of the third capacitor is electrically connected to the fifth node, and the second end of the third capacitor is electrically connected to the sixth node; The first end of the fourth capacitor is electrically connected to the sixth node, and the second end of the fourth capacitor is electrically connected to the second power supply terminal.

15. The pixel driving circuit according to any one of claims 2 to 9, wherein, The duration control sub-circuit further includes: a duration node control sub-circuit and a duration light-emitting control sub-circuit; The duration driving sub-circuit is further electrically connected to the fifth node, the sixth node, and the seventh node respectively, and is configured to provide a second driving signal to the seventh node under the control of the signals of the fifth node and the sixth node; The duration light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second power supply terminal, the sixth node, and the seventh node respectively, and is configured to provide the signal of the first power supply terminal to the seventh node and the signal of the second power supply terminal to the sixth node under the control of the signals of the first light-emitting signal terminal and the second light-emitting signal terminal; The duration node control sub-circuit is electrically connected to the duration data signal terminal, the initial signal terminal, the second power supply terminal, the second reset signal terminal, the first scan signal terminal, the second scan signal terminal, the first node, the fifth node, the sixth node, and the seventh node respectively, and is configured to provide the signal of the duration data signal terminal to the fifth node, the signal of the initial signal terminal to the sixth node, and the signal of the seventh node to the first node under the control of the signals of the second reset signal terminal, the first scan signal terminal, and the second scan signal terminal.

16. The pixel driving circuit according to claim 15, wherein, The duration driving sub-circuit includes: a ninth transistor, the duration node control sub-circuit includes: a seventh transistor, a tenth transistor, a thirteenth transistor, a third capacitor, and a fourth capacitor, and the duration light-emitting control sub-circuit includes: an eleventh transistor and a twelfth transistor; The control electrode of the seventh transistor is electrically connected to the second reset signal terminal, the first pole of the seventh transistor is electrically connected to the initial signal terminal, and the second pole of the seventh transistor is electrically connected to the sixth node; The control electrode of the ninth transistor is electrically connected to the fifth node, the first pole of the ninth transistor is electrically connected to the seventh node, and the second pole of the ninth transistor is electrically connected to the sixth node; The control electrode of the tenth transistor is electrically connected to the first scan signal terminal, the first pole of the tenth transistor is electrically connected to the duration data signal terminal, and the second pole of the tenth transistor is electrically connected to the fifth node; The control electrode of the eleventh transistor is electrically connected to the second light-emitting signal terminal, the first pole of the eleventh transistor is electrically connected to the first power supply terminal, and the second pole of the eleventh transistor is electrically connected to the seventh node; The control electrode of the twelfth transistor is electrically connected to the first light-emitting signal terminal, the first pole of the twelfth transistor is electrically connected to the second power supply terminal, and the second pole of the twelfth transistor is electrically connected to the sixth node; The control electrode of the thirteenth transistor is electrically connected to the second scan signal terminal, the first pole of the thirteenth transistor is electrically connected to the seventh node, and the second pole of the thirteenth transistor is electrically connected to the first node; The first end of the third capacitor is electrically connected to the fifth node, and the second end of the third capacitor is electrically connected to the sixth node; The first end of the fourth capacitor is electrically connected to the sixth node, and the second end of the fourth capacitor is electrically connected to the second power supply terminal.

17. The pixel driving circuit according to any one of claims 1, 14, and 16, wherein, The light emitting device includes: a first pole and a second pole; The current control sub-circuit is respectively electrically connected to the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light emitting signal terminal, the first node and the light emitting device, and is configured to provide a first drive signal to the first pole of the light emitting device under the control of the signals of the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light emitting signal terminal and the first node.

18. The pixel driving circuit according to claim 17, wherein, The current control sub-circuit includes: a first transistor to a sixth transistor and a first capacitor; The control pole of the first transistor is electrically connected to the first reset signal terminal, the first pole of the first transistor is electrically connected to the initial signal terminal, and the second pole of the first transistor is electrically connected to the fourth node; The control pole of the second transistor is electrically connected to the first scan signal terminal, the first pole of the second transistor is electrically connected to the first node, and the second pole of the second transistor is electrically connected to the second node; The control pole of the third transistor is electrically connected to the first node, the first pole of the third transistor is electrically connected to the second node, and the second pole of the third transistor is electrically connected to the third node; The control pole of the fourth transistor is electrically connected to the first scan signal terminal, the first pole of the fourth transistor is connected to the current data signal terminal, and the second pole of the fourth transistor is electrically connected to the third node; The control pole of the fifth transistor is electrically connected to the first light emitting signal terminal, the first pole of the fifth transistor is electrically connected to the first power supply terminal, and the second pole of the fifth transistor is electrically connected to the second node; The control pole of the sixth transistor is electrically connected to the first light emitting signal terminal, the first pole of the sixth transistor is electrically connected to the third node, and the second pole of the sixth transistor is electrically connected to the first pole of the light emitting device; The first end of the first capacitor is electrically connected to the first node, and the second end of the first capacitor is electrically connected to the fourth node; The fourth node is electrically connected to the first pole or the second pole of the light emitting device.

19. A display device, comprising: The pixel driving circuit according to any one of claims 1 to 18.

20. The display device according to claim 19 further comprises: A data unit, the data unit is electrically connected to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first light emitting signal terminal and the second light emitting signal terminal connected to the pixel driving circuit; The content displayed by the display device includes: at least one display frame. In at least one display frame, the data unit is configured to provide an effective level signal to the first reset signal terminal and the second reset signal terminal during a first time period, and provide an ineffective level signal to the first light-emitting signal terminal, the second light-emitting signal terminal, and the first scan signal terminal. During a second time period, it provides an effective level signal to the first reset signal terminal and the second light-emitting signal terminal, and provides an effective level signal to the second reset signal terminal, the first light-emitting signal terminal, and the first scan signal terminal. During a third time period, it provides an effective level signal to the first scan signal terminal, and provides an ineffective level signal to the first reset signal terminal, the second reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal. During a fourth time period, it provides an ineffective level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal. During a fifth time period, it provides an effective level signal to the first light-emitting signal terminal, and provides an ineffective level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, and the second light-emitting signal terminal.

21. The display device according to claim 20, wherein, The data unit is also electrically connected to the second scan signal terminal connected to the pixel driving circuit. The data unit is configured to provide an effective level signal to the second scan signal terminal during the second time period, the fourth time period, and the fifth time period, and provide an ineffective level signal to the third scan signal terminal during the first time period and the third time period.

22. The display device according to claim 20, wherein, The data unit is also electrically connected to the ramp signal terminal connected to the pixel driving circuit, and is configured to provide a reference signal to the ramp signal terminal during the first time period to the fourth time period, and provide a ramp signal to the ramp signal terminal during the fifth time period.

23. A driving method for a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 18. The method includes: The duration control sub-circuit provides a second driving signal to the current control sub-circuit under the control of the signal at the ramp signal terminal; The current control sub-circuit provides a first driving signal to the light-emitting device under the control of the second driving signal.

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