Pixel driving circuit and driving method therefor, and display apparatus

Abstract

A pixel driving circuit and a driving method therefor, and a display apparatus, wherein the pixel driving circuit is electrically connected to a light-emitting device (L). The pixel driving circuit comprises: a current control sub-circuit and a duration control sub-circuit, wherein the current control sub-circuit is configured to provide a first driving signal to the light-emitting device (L) under the control of signals of a current data signal end (DataI), an initial signal end (INIT), a first power supply end (VDD), a first scanning signal end (Gate1), a first reset signal end (RST1), a first light-emission signal end (EM1) and a first node (N1); and the duration control sub-circuit is configured to provide a second driving signal to the first node (N1) under the control of signals of a duration data signal end (DataT), the initial signal end (INIT), a reference signal end (REF), a ramp signal end (SWP), the first power supply end (VDD), a second power supply end (VSS), the first scanning signal end (Gate1), a second reset signal end (RST2), a third reset signal end (RST3), the first light-emission signal end (EM1) and a second light-emission signal end (EM2).

Description

Pixel driving circuit and driving method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs), quantum-dot light-emitting diodes (QLEDs), and micro-LEDs are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs, QLEDs, or micro-LEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit electrically connected to a light emitting device, wherein the pixel driving circuit comprises: a current control subcircuit and a duration control subcircuit;

[0006] The current control subcircuit is electrically connected to the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal, the first node, and the light-emitting device, and is configured to provide a first driving signal to the light-emitting device under the control of signals from the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal, and the first node;

[0007] The duration control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, the second light-emitting signal terminal and the first node, respectively, and is configured to provide a second drive signal to the first node under the control of signals from the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal and the second light-emitting signal terminal.

[0008] In an exemplary embodiment, the current control subcircuit is also electrically connected to the second scan signal terminal and is configured to provide a first driving signal to the light-emitting device under the control of the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the second scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal and the signal of the first node.

[0009] In an exemplary embodiment, the light emitting device includes: a first electrode and a second electrode, and the current control subcircuit includes: a first driving subcircuit, a first node control subcircuit, and a first light emission control subcircuit;

[0010] The first driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a first driving signal to the third node under the control of signals from the first node and the second node;

[0011] The first light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the first electrode of the light-emitting device, respectively, and is configured to provide a signal from the first power supply terminal to the second node and a signal from the third node to the first electrode of the light-emitting device under the control of a signal from the first light-emitting signal terminal;

[0012] The first node control subcircuit is electrically connected to the current data signal terminal, the initial signal terminal, the first scan signal terminal, the first reset signal terminal, the first node, the second node, the third node, and the fourth node, respectively, and is configured to, under the control of the signals of the first scan signal terminal and the first reset signal terminal, provide the signal of the initial signal terminal to the fourth node, provide the signal of the current data signal terminal to the third node, and provide the signal of the second node to the first node;

[0013] The fourth node is electrically connected to the first electrode of the light emitting device or the second electrode of the light emitting device.

[0014] In an exemplary embodiment, the light emitting device includes: a first electrode and a second electrode, and the current control subcircuit includes: a first driving subcircuit, a first node control subcircuit, and a first light emission control subcircuit;

[0015] The first driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a first driving signal to the third node under the control of signals from the first node and the second node;

[0016] The first light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the first power terminal, the second node, the third node, and the first electrode of the light-emitting device, respectively, and is configured to provide a signal from the first power terminal to the second node and a first driving signal to the first electrode of the light-emitting device under the control of a signal from the first light-emitting signal terminal;

[0017] The first node control subcircuit is electrically connected to the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the second scan signal terminal, the first reset signal terminal, the first node, the second node, the third node, and the fourth node, respectively, and is configured to, under the control of the signals of the first scan signal terminal, the first reset signal terminal, and the second scan signal terminal, provide the signal of the initial signal terminal to the fourth node, provide the signal of the current data signal terminal to the third node, and provide the signal of the second node or the first power supply terminal to the first node;

[0018] The fourth node is electrically connected to the first electrode of the light emitting device or the second electrode of the light emitting device.

[0019] In an exemplary embodiment, the first node control subcircuit includes: a first transistor, a second transistor, a fourth transistor and a first capacitor, the first driving subcircuit includes: a third transistor, and the first light emission control subcircuit includes: a fifth transistor and a sixth transistor;

[0020] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node;

[0021] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0022] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0023] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is connected to the current data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0024] The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0025] The control electrode of the sixth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting device;

[0026] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the fourth node.

[0027] In an exemplary embodiment, the first control subcircuit includes: a first transistor, a second transistor, a fourth transistor, a seventh transistor and a first capacitor, the first driving subcircuit includes: a third transistor, and the first light emitting control subcircuit includes: a fifth transistor and a sixth transistor;

[0028] The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node;

[0029] The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node;

[0030] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node;

[0031] The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is connected to the current data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node;

[0032] The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node;

[0033] The control electrode of the sixth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting device;

[0034] The control electrode of the seventh transistor is electrically connected to the second scan signal terminal, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the first node;

[0035] A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the fourth node.

[0036] In an exemplary embodiment, the duration control subcircuit is also electrically connected to the third scan signal terminal and is configured to provide a second drive signal to the first node under the control of signals from the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the third scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal and the second light-emitting signal terminal.

[0037] In an exemplary embodiment, the duration control subcircuit includes: a second driving subcircuit, a second node control subcircuit, and a second light emitting control subcircuit;

[0038] The second driving sub-circuit is electrically connected to the fifth node, the sixth node and the first node respectively, and is configured to provide a second driving signal to the first node under the control of the signals of the fifth node and the sixth node;

[0039] The second light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power terminal, the second power terminal, the sixth node, and the first node, respectively, and is configured to provide a signal from the first power terminal to the first node and a signal from the second power terminal to the sixth node under the control of signals from the first light-emitting signal terminal and the second light-emitting signal terminal;

[0040] The second node control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the second power supply terminal, the second reset signal terminal, the third reset signal terminal, the first scan signal terminal, the fifth node and the sixth node, respectively, and is configured to provide the signal of the reference signal terminal or the duration data signal terminal to the fifth node, provide the signal of the initial signal terminal to the sixth node, and drive the signal of the fifth node under the control of the signal of the second reset signal terminal, the third reset signal terminal and the first scan signal terminal.

[0041] In an exemplary embodiment, the duration control subcircuit includes: a second driving subcircuit, a second node control subcircuit, and a second light emitting control subcircuit;

[0042] The second driving sub-circuit is electrically connected to the fifth node, the sixth node, and the seventh node, respectively, and is configured to provide a second driving signal to the seventh node under the control of the signals of the fifth node and the sixth node;

[0043] The second light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power terminal, the second power terminal, the sixth node, and the seventh node, respectively, and is configured to provide a signal from the first power terminal to the seventh node and a signal from the second power terminal to the sixth node under the control of signals from the first light-emitting signal terminal and the second light-emitting signal terminal;

[0044] The second node control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the second power supply terminal, the second reset signal terminal, the third reset signal terminal, the first scan signal terminal, the third scan signal terminal, the first node, the fifth node, the sixth node and the seventh node, respectively, and is configured to provide the signal of the reference signal terminal or the duration data signal terminal to the fifth node, provide the signal of the initial signal terminal to the sixth node, provide the signal of the seventh node to the first node, and drive the signal of the fifth node under the action of the signal of the ramp signal terminal.

[0045] In an exemplary embodiment, the second node control subcircuit includes: an eighth transistor, a ninth transistor, an eleventh transistor, a second capacitor, a third capacitor, and a fourth capacitor; the second driving subcircuit includes: a tenth transistor; and the second light emitting control subcircuit includes: a twelfth transistor and a thirteenth transistor;

[0046] a control electrode of the eighth transistor electrically connected to the second reset signal terminal, a first electrode of the eighth transistor electrically connected to the initial signal terminal, and a second electrode of the eighth transistor electrically connected to the sixth node;

[0047] a control electrode of the ninth transistor electrically connected to the third reset signal terminal, a first electrode of the ninth transistor electrically connected to the reference signal terminal, and a second electrode of the ninth transistor electrically connected to the fifth node;

[0048] a control electrode of the tenth transistor is electrically connected to the fifth node, a first electrode of the tenth transistor is electrically connected to the first node, and a second electrode of the tenth transistor is electrically connected to the sixth node;

[0049] The control electrode of the eleventh transistor is electrically connected to the first scan signal terminal, the first electrode of the eleventh transistor is electrically connected to the duration data signal terminal, and the second electrode of the eleventh transistor is electrically connected to the fifth node;

[0050] The control electrode of the twelfth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the first node;

[0051] The control electrode of the thirteenth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the sixth node;

[0052] A first end of the second capacitor is electrically connected to the ramp signal end, and a second end of the second capacitor is electrically connected to the fifth node;

[0053] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the sixth node;

[0054] A first end of the fourth capacitor is electrically connected to the sixth node, and a second end of the fourth capacitor is electrically connected to the second power supply end.

[0055] In example embodiments, at least one transistor among the first to thirteenth transistors is an oxide transistor.

[0056] In an exemplary embodiment, the second node control subcircuit includes: an eighth transistor, a ninth transistor, an eleventh transistor, a fourteenth transistor, a second capacitor, a third capacitor, and a fourth capacitor; the second driving subcircuit includes: a tenth transistor; and the second light emission control subcircuit includes: a twelfth transistor and a thirteenth transistor;

[0057] a control electrode of the eighth transistor electrically connected to the second reset signal terminal, a first electrode of the eighth transistor electrically connected to the initial signal terminal, and a second electrode of the eighth transistor electrically connected to the sixth node;

[0058] a control electrode of the ninth transistor electrically connected to the third reset signal terminal, a first electrode of the ninth transistor electrically connected to the reference signal terminal, and a second electrode of the ninth transistor electrically connected to the fifth node;

[0059] a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to the seventh node, and a second electrode of the tenth transistor electrically connected to the sixth node;

[0060] The control electrode of the eleventh transistor is electrically connected to the first scan signal terminal, the first electrode of the eleventh transistor is electrically connected to the duration data signal terminal, and the second electrode of the eleventh transistor is electrically connected to the fifth node;

[0061] The control electrode of the twelfth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node;

[0062] The control electrode of the thirteenth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the sixth node;

[0063] A control electrode of the fourteenth transistor is electrically connected to the third scan signal terminal, a first electrode of the fourteenth transistor is electrically connected to the seventh node, and a second electrode of the fourteenth transistor is electrically connected to the first node;

[0064] A first end of the second capacitor is electrically connected to the ramp signal end, and a second end of the second capacitor is electrically connected to the fifth node;

[0065] A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the sixth node;

[0066] A first end of the fourth capacitor is electrically connected to the sixth node, and a second end of the fourth capacitor is electrically connected to the second power supply end.

[0067] In example embodiments, at least one transistor among the first to fourteenth transistors is an oxide transistor.

[0068] In an exemplary embodiment, the initial signal terminal and the second power terminal are the same signal terminal.

[0069] In an exemplary embodiment, the first reset signal terminal and the third reset signal terminal are the same signal terminal.

[0070] In an exemplary embodiment, the second scan signal terminal and the first reset signal terminal are the same signal terminal.

[0071] In an exemplary embodiment, a time when the signal at the third scanning signal terminal is an active level signal at least partially overlaps a time when the signal at the first light emitting signal terminal is an active level signal.

[0072] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned pixel driving circuit.

[0073] In an exemplary embodiment, the invention further includes: a data unit electrically connected to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light emitting signal terminal and the second light emitting signal terminal connected to the pixel driving circuit;

[0074] The content displayed by the display device includes: at least one display frame, in which the data unit is configured to provide a valid level signal to the first reset signal terminal, the second reset signal terminal, and the third reset signal terminal in a first time period, and provide an invalid level signal to the first light-emitting signal terminal, the second light-emitting signal terminal, and the first scan signal terminal; provide a valid level signal to the first reset signal terminal, the third reset signal terminal, and the second light-emitting signal terminal in a second time period, and provide a valid level signal to the second reset signal terminal, the first light-emitting signal terminal, and the first scan signal terminal; provide a valid level signal to the first scan signal terminal in a third time period, and provide an invalid level signal to the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal; provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal in a fourth time period; provide a valid level signal to the first light-emitting signal terminal in a fifth time period, and provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, and the second light-emitting signal terminal.

[0075] In an exemplary embodiment, the data unit is also electrically connected to the second scanning signal terminal connected to the pixel driving circuit, and the data unit is configured to provide a valid level signal to the second scanning signal terminal in the first time period and the second time period, and to provide an invalid level signal to the second scanning signal terminal in the third time period to the fifth time period.

[0076] In an exemplary embodiment, the data unit is further electrically connected to a third scanning signal terminal connected to the pixel driving circuit, and the data unit is configured to provide a valid level signal to the third scanning signal terminal in the second time period, the fourth time period, and the fifth time period, and provide an invalid level signal to the third scanning signal terminal in the first time period and the third time period, or provide an invalid level signal to the third scanning signal terminal from the first time period to the fourth time period, and provide a valid level signal to the third scanning signal terminal in the fifth time period.

[0077] In an exemplary embodiment, the data unit is further electrically connected to the ramp signal terminal connected to the pixel driving circuit, and is configured to provide a constant voltage signal to the ramp signal terminal in the first time period to the fourth time period, and provide a ramp signal to the ramp signal terminal in the fifth time period.

[0078] In a third aspect, the present disclosure further provides a driving method for a pixel driving circuit, configured to drive the above-mentioned pixel driving circuit, the method comprising:

[0079] The duration control subcircuit provides a second driving signal to the first node under the control of signals at the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal;

[0080] The current control subcircuit provides a first driving signal to the light emitting device under the control of the current data signal terminal, the initial signal terminal, the first power terminal, the first scan signal terminal, the first reset signal terminal, the first light emitting signal terminal and the signal of the first node.

[0081] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0082] Summary of the Figures

[0083] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0084] FIG1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0085] FIG2 is a structural schematic diagram of a current control subcircuit;

[0086] FIG3 is an equivalent circuit diagram of the current control subcircuit provided in FIG2 ;

[0087] FIG4 is a second structural diagram of a current control subcircuit;

[0088] FIG5 is an equivalent circuit diagram of the current control subcircuit provided in FIG4 ;

[0089] FIG6 is a structural diagram of a duration control subcircuit;

[0090] FIG7 is an equivalent circuit diagram of the duration control subcircuit provided in FIG6 ;

[0091] FIG8 is a second structural diagram of a duration control subcircuit;

[0092] FIG9 is an equivalent circuit diagram of the duration control subcircuit provided in FIG8 ;

[0093] FIG10 is an equivalent circuit diagram 1 of a pixel driving circuit;

[0094] FIG11 is a second equivalent circuit diagram of a pixel driving circuit;

[0095] FIG12 is a third equivalent circuit diagram of a pixel driving circuit;

[0096] FIG13 is a fourth equivalent circuit diagram of a pixel driving circuit;

[0097] FIG14 is an operation timing diagram of the pixel driving circuit provided in FIG10 ;

[0098] FIG15 is an operation timing diagram of the pixel driving circuit provided in FIG11 ;

[0099] FIG16 is an operation timing diagram of the pixel driving circuit provided in FIG12 ;

[0100] FIG17 is a timing diagram of the operation of the pixel driving circuit provided in FIG13 .

[0101] Details

[0102] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0103] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0104] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0105] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0106] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0107] In this specification, a transistor refers to a device consisting of at least three elements: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode element, drain region, or drain electrode) and a source electrode (source electrode element, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0108] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0109] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0110] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0111] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0112] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0113] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0114] A display device includes multiple submodules, each of which includes multiple subpixels. Each subpixel includes multiple pixel driver circuits and light-emitting devices. The pixel driver circuit consists of two parts: one that determines the duration of light emission and the other that generates a constant current. These two parts of the pixel driver circuit are affected by the capacitance of the light-emitting devices, resulting in color shift and low grayscale accuracy in the display device.

[0115] Figure 1 is a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 1, the pixel driving circuit provided by an embodiment of the present disclosure is electrically connected to a light-emitting device and can be configured to drive the light-emitting device to emit light. The pixel driving circuit can include: a current control subcircuit and a duration control subcircuit.

[0116] As shown in FIG1 , the current control subcircuit is electrically connected to the current data signal terminal DataI, the initial signal terminal INIT, the first power supply terminal VDD, the first scan signal terminal Gate1, the first reset signal terminal RST1, the first light-emitting signal terminal EM1, the first node N1 and the light-emitting device, and is configured to provide a first driving signal to the light-emitting device under the control of the signals of the current data signal terminal DataI, the initial signal terminal INIT, the first power supply terminal VDD, the first scan signal terminal Gate1, the first reset signal terminal RST1, the first light-emitting signal terminal EM1 and the first node N1; the duration control subcircuit is electrically connected to the duration data signal terminal DataT, the initial signal terminal INIT, the reference signal terminal REF , the ramp signal terminal SWP, the first power supply terminal VDD, the second power supply terminal VSS, the first scan signal terminal Gate1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2 and the first node N1 are electrically connected, and are configured to provide a second driving signal to the first node N1 under the control of signals from the duration data signal terminal DataT, the initial signal terminal INIT, the reference signal terminal REF, the ramp signal terminal SWP, the first power supply terminal VDD, the second power supply terminal VSS, the first scan signal terminal Gate1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2.

[0117] In an exemplary embodiment, as shown in FIG. 1 , the second electrode of the light emitting device is further electrically connected to the second power supply terminal VSS.

[0118] In an exemplary embodiment, the first power terminal VDD may continuously provide a high voltage power signal, and the second power terminal VSS may continuously provide a low voltage power signal.

[0119] In an exemplary embodiment, the voltage value of the signal of the first power supply terminal VDD may be approximately 2.5 volts (V) to 3 volts (V).

[0120] In an exemplary embodiment, the voltage value of the signal at the second power supply terminal VSS may be approximately -3V to -3.5V, and illustratively, the voltage value of the signal at the second power supply terminal VSS may be approximately -3.2V.

[0121] In an exemplary embodiment, the initial signal terminal INIT may continuously provide a constant voltage power signal.

[0122] In an exemplary embodiment, the light-emitting device includes a current-driven device, and a current-type light-emitting diode may be used, such as a micro light-emitting diode (Micro LED) or a mini light-emitting diode (Mini LED) or an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). The typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0123] In an exemplary embodiment, the light emitting device includes a first electrode, a second electrode, and an organic light emitting layer located between the first electrode and the second electrode. Exemplarily, the first electrode of the light emitting device is electrically connected to the current control subcircuit, and the second electrode of the light emitting device is electrically connected to the second power supply terminal.

[0124] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0125] The pixel driving circuit provided in the embodiment of the present disclosure is electrically connected to the light-emitting device, wherein the pixel driving circuit includes: a current control subcircuit and a time length control subcircuit; the current control subcircuit is electrically connected to the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal, the first node and the light-emitting device, and is configured to provide a first driving signal to the light-emitting device under the control of the signals of the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal and the first node; the time length The control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, the second light-emitting signal terminal, and the first node, and is configured to provide a second drive signal to the first node under the control of the signals at the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal. The present disclosure reduces the influence of the capacitance of the light-emitting device on the current control subcircuit and the duration control subcircuit through the cooperation of the current control subcircuit and the duration control subcircuit, improves the color deviation of the display device where the pixel drive circuit is located, and improves the grayscale expansion accuracy of the display device.

[0126] In an exemplary embodiment, as shown in Figure 1, the current control sub-circuit may also be electrically connected to the second scan signal terminal Gate2, and is configured to provide a first driving signal to the light-emitting device under the control of the current data signal terminal DataI, the initial signal terminal INIT, the first power supply terminal VDD, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal RST1, the first light-emitting signal terminal EM1 and the signal of the first node N1.

[0127] In an exemplary embodiment, as shown in Figure 1, the duration control sub-circuit may also be electrically connected to the third scan signal terminal Gate3, and is configured to provide a second driving signal to the first node N1 under the control of signals from the duration data signal terminal DataT, the initial signal terminal INIT, the reference signal terminal REF, the ramp signal terminal SWP, the first power supply terminal VDD, the second power supply terminal VSS, the first scan signal terminal Gate1, the third scan signal terminal Gate3, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2.

[0128] FIG2 is a schematic diagram of a current control subcircuit. As shown in FIG2 , in an exemplary embodiment, the current control subcircuit is electrically connected to the current data signal terminal Data1, the initial signal terminal INIT, the first power supply terminal VDD, the first scan signal terminal Gate1, the first reset signal terminal RST1, the first light-emitting signal terminal EM1, the first node N1, and the light-emitting device. The current control subcircuit may include: a first driving subcircuit, a first node control subcircuit, and a first light-emitting control subcircuit.

[0129] As shown in FIG2 , the first driver sub-circuit is electrically connected to a first node N1, a second node N2, and a third node N3, respectively, and is configured to provide a first drive signal to the third node N3 under control of signals from the first and second nodes N1 and N2. The first light-emission control sub-circuit is electrically connected to a first light-emission signal terminal EM1, a first power supply terminal VDD, a second node N2, a third node N3, and a first electrode of the light-emitting device L, respectively, and is configured to provide a signal from the first power supply terminal VDD to the second node N2 and a signal from the third node N3 to the first electrode of the light-emitting device L under control of a signal from the first light-emission signal terminal EM1. The first node control sub-circuit is electrically connected to the current data signal terminal DataI, the initial signal terminal INIT, the first scan signal terminal Gate1, the first reset signal terminal RST1, the first node N1, the second node N2, the third node N3 and the fourth node N4, respectively, and is configured to provide the signal of the initial signal terminal INIT to the fourth node N4, provide the signal of the current data signal terminal DataI to the third node N3, and provide the signal of the second node N2 to the first node N1 under the control of the signals of the first scan signal terminal Gate1 and the first reset signal terminal RST1.

[0130] In an exemplary embodiment, the fourth node N4 is electrically connected to the first electrode of the light emitting device or the second electrode of the light emitting device. FIG2 illustrates the fourth node N4 and the first electrode of the light emitting device as an example.

[0131] In an exemplary embodiment, when the light-emitting device is an OLED or a QLED, the fourth node N4 is electrically connected to the first electrode of the light-emitting device; when the light-emitting device is a micro LED, the fourth node N4 is electrically connected to the first electrode of the light-emitting device or the second electrode of the light-emitting device. The present disclosure does not impose any limitations on this.

[0132] FIG3 is an equivalent circuit diagram of the current control subcircuit provided in FIG2 . As shown in FIG3 , in an exemplary embodiment, the first node control subcircuit may include: a first transistor T1, a second transistor T2, a fourth transistor T4 and a first capacitor C1, the first drive subcircuit may include: a third transistor T3, and the first light emitting control subcircuit may include: a fifth transistor T5 and a sixth transistor T6. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1. The first electrode of the fourth transistor T4 is electrically connected to the current data signal terminal DataI, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting device; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the fourth node N4.

[0133] In an exemplary embodiment, the third transistor T3 is a driving transistor. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are switching transistors.

[0134] FIG4 is a second schematic diagram of the structure of a current control subcircuit. As shown in FIG4 , in an exemplary embodiment, the current control subcircuit is electrically connected to the current data signal terminal Data1, the initial signal terminal INIT, the first power supply terminal VDD, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal RST1, the first light-emitting signal terminal EM1, the first node N1, and the light-emitting device. The current control subcircuit may include: a first driving subcircuit, a first node control subcircuit, and a first light-emitting control subcircuit.

[0135] As shown in FIG4 , the first driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide a first driving signal to the third node N3 under the control of the signals of the first node N1 and the second node N2; the first light-emitting control sub-circuit is electrically connected to the first light-emitting signal terminal EM1, the first power supply terminal VDD, the second node N2, the third node N3, and the first electrode of the light-emitting device, respectively, and is configured to provide a signal of the first power supply terminal VDD to the second node N2 and provide the first driving signal to the first electrode of the light-emitting device under the control of the signal of the first light-emitting signal terminal EM1; the first node control sub-circuit is electrically connected to the current data signal terminal EM1, the first power supply terminal VDD, the second node N2, the third node N3, and the first electrode of the light-emitting device, respectively. The signal terminal DataI, the initial signal terminal INIT, the first power supply terminal VDD, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal RST1, the first node N1, the second node N2, the third node N3 and the fourth node N4 are electrically connected and configured to provide the signal of the initial signal terminal INIT to the fourth node N4, provide the signal of the current data signal terminal DataI to the third node N3, and provide the signal of the second node N2 or the first power supply terminal VDD to the first node N1 under the control of the signals of the first scan signal terminal Gate1, the first reset signal terminal RST1 and the second scan signal terminal Gate2.

[0136] In an exemplary embodiment, the fourth node N4 is electrically connected to the first electrode of the light emitting device or the second electrode of the light emitting device. FIG4 illustrates the fourth node N4 and the first electrode of the light emitting device as an example.

[0137] In an exemplary embodiment, when the light-emitting device is an OLED or a QLED, the fourth node N4 is electrically connected to the first electrode of the light-emitting device; when the light-emitting device is a micro LED, the fourth node N4 is electrically connected to the first electrode of the light-emitting device or the second electrode of the light-emitting device. The present disclosure does not impose any limitations on this.

[0138] Figure 5 is an equivalent circuit diagram of the current control subcircuit provided in Figure 4. As shown in Figure 5, in an exemplary embodiment, the first control subcircuit may include a first transistor T1, a second transistor T2, a fourth transistor T4, a seventh transistor T7, and a first capacitor C1, the first driving subcircuit may include a third transistor T3, and the first light emission control subcircuit may include a fifth transistor T5 and a sixth transistor T6. Wherein, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is electrically connected to the current data signal terminal Data1, and the fourth transistor T 4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light emitting device L; the control electrode of the seventh transistor T7 is electrically connected to the second scan signal terminal Gate2, the first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VDD, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the first end of the first capacitor C1 is electrically connected to the first node N1, and the second end of the first capacitor C1 is electrically connected to the fourth node N4.

[0139] In an exemplary embodiment, the third transistor T3 is a driving transistor. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are switching transistors.

[0140] An exemplary structure of the current control subcircuit is shown in Figures 3 and 5. Those skilled in the art will readily appreciate that the implementation of the current control subcircuit is not limited thereto.

[0141] In an exemplary embodiment, the seventh transistor T7 can be provided to independently reset the gate electrode of the third transistor T3 , which is beneficial for the current control sub-circuit clock to be in a deterministic state and can improve the stability of the pixel driving current.

[0142] Figure 6 is a structural schematic diagram of a duration control subcircuit. As shown in Figure 6, in an exemplary embodiment, the duration control subcircuit may include: a second driving subcircuit, a second node control subcircuit, and a second light emitting control subcircuit.

[0143] As shown in FIG6 , the second driving sub-circuit is electrically connected to the fifth node N5, the sixth node N6, and the first node N1, respectively, and is configured to provide a second driving signal to the first node N1 under the control of signals from the fifth node N5 and the sixth node N6. The second light-emission control sub-circuit is electrically connected to the first light-emitting signal terminal EM1, the second light-emitting signal terminal EM2, the first power supply terminal VDD, the second power supply terminal VSS, the sixth node N6, and the first node N1, respectively, and is configured to provide a signal from the first power supply terminal VDD to the first node N1 and a signal from the second power supply terminal VSS to the sixth node N6 under the control of signals from the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2. The second node control sub-circuit is electrically connected to the duration data signal terminal DataT, the initial signal terminal INIT, the reference signal terminal REF, the ramp signal terminal SWP, the second power supply terminal VSS, the second reset signal terminal RST2, the third reset signal terminal RST3, the first scan signal terminal Gate1, the fifth node N5 and the sixth node N6, and is configured to provide the signal of the reference signal terminal REF or the duration data signal terminal DataT to the fifth node N5, and provide the signal of the initial signal terminal INIT to the sixth node N6 under the control of the signal of the second reset signal terminal RST2, the third reset signal terminal RST3 and the first scan signal terminal Gate1, and drive the signal of the fifth node N5 under the action of the signal of the ramp signal terminal SWP.

[0144] FIG7 is an equivalent circuit diagram of the duration control subcircuit provided in FIG6 . As shown in FIG7 , in an exemplary embodiment, the second node control subcircuit may include: an eighth transistor T8, a ninth transistor T9, an eleventh transistor T11, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; the second driving subcircuit may include: a tenth transistor T10; and the second light emitting control subcircuit may include: a twelfth transistor T12 and a thirteenth transistor T13. The control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal RST2, the first electrode of the eighth transistor T8 is electrically connected to the initial signal terminal INIT, and the second electrode of the eighth transistor T8 is electrically connected to the sixth node N6; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal RST3, the first electrode of the ninth transistor T9 is electrically connected to the reference signal terminal REF, and the second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5 The first electrode of the tenth transistor T10 is electrically connected to the first node N1, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; the control electrode of the eleventh transistor T11 is electrically connected to the first scan signal terminal Gate1, the first electrode of the eleventh transistor T11 is electrically connected to the duration data signal terminal DataT, and the second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5; the control electrode of the twelfth transistor T12 is electrically connected to the second light emitting signal terminal EM2, the first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VDD, and the second electrode of the twelfth transistor T12 is electrically connected to the first node N1. a control electrode of the thirteenth transistor T13 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal VSS, and a second electrode of the thirteenth transistor T13 is electrically connected to the sixth node N6; a first end of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and a second end of the second capacitor C2 is electrically connected to the fifth node N5; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0145] In an exemplary embodiment, the tenth transistor T10 is a driving transistor, and the eighth transistor T8, the ninth transistor T9, and the eleventh to thirteenth transistors T11 to T13 are switching transistors.

[0146] Figure 8 is a second structural diagram of a duration control subcircuit. As shown in Figure 8 , in an exemplary embodiment, the duration control subcircuit may include: a second driving subcircuit, a second node control subcircuit, and a second light emitting control subcircuit.

[0147] As shown in FIG8 , the second driving sub-circuit is electrically connected to the fifth node N5, the sixth node N6, and the seventh node N7, respectively, and is configured to provide a second driving signal to the seventh node N7 under the control of signals from the fifth node N5 and the sixth node N6. The second light-emission control sub-circuit is electrically connected to the first light-emission signal terminal EM1, the second light-emission signal terminal EM2, the first power supply terminal VDD, the second power supply terminal VSS, the sixth node N6, and the seventh node N7, respectively, and is configured to provide a signal from the first power supply terminal VDD to the seventh node N7 and a signal from the second power supply terminal VSS to the sixth node N6 under the control of signals from the first light-emission signal terminal EM1 and the second light-emission signal terminal EM2. The second node control sub-circuit is electrically connected to the duration data signal terminal DataT, the initial signal terminal INIT, the reference signal terminal REF, the ramp signal terminal SWP, the second power supply terminal VSS, the second reset signal terminal RST2, the third reset signal terminal RST3, the first scan signal terminal Gate1, the third scan signal terminal Gate3, the first node N1, the fifth node N5, the sixth node N6 and the seventh node N7, respectively, and is configured to provide the signal of the reference signal terminal REF or the duration data signal terminal DataT to the fifth node N5, provide the signal of the initial signal terminal INIT to the sixth node N6, provide the signal of the seventh node N7 to the first node N1, and drive the signal of the fifth node N5 under the action of the signal of the ramp signal terminal SWP.

[0148] Figure 9 is an equivalent circuit diagram of the duration control subcircuit provided in Figure 8. As shown in Figure 9, in an exemplary embodiment, the second node control subcircuit may include an eighth transistor T8, a ninth transistor T9, an eleventh transistor T11, a fourteenth transistor T14, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; the second driving subcircuit may include a tenth transistor T10; and the second light emission control subcircuit may include a twelfth transistor T12 and a thirteenth transistor T13. Among them, the control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal RST2, the first electrode of the eighth transistor T8 is electrically connected to the initial signal terminal INIT, and the second electrode of the eighth transistor T8 is electrically connected to the sixth node N6; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal RST3, the first electrode of the ninth transistor T9 is electrically connected to the reference signal terminal REF, and the second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the seventh node N7, and the second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; the control electrode of the eleventh transistor T11 is electrically connected to the first scan signal terminal Gate1, the first electrode of the eleventh transistor T11 is electrically connected to the duration data signal terminal DataT, and the second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5; the control electrode of the twelfth transistor T12 is electrically connected to the second light emitting signal terminal EM2, and the tenth transistor T13 is electrically connected to the first scan signal terminal Gate1. A first electrode of the second transistor T12 is electrically connected to the first power supply terminal VDD, and a second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7; a control electrode of the thirteenth transistor T13 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal VSS, and a second electrode of the thirteenth transistor T13 is electrically connected to the sixth node N6; a control electrode of the fourteenth transistor T14 is electrically connected to the third scan signal terminal Gate3, a first electrode of the fourteenth transistor T14 is electrically connected to the seventh node N7, and a second electrode of the fourteenth transistor T14 is electrically connected to the first node N1; a first end of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and a second end of the second capacitor C2 is electrically connected to the fifth node N5; a first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6; a first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0149] In an exemplary embodiment, the tenth transistor T10 is a driving transistor, and the eighth transistor T8, the ninth transistor T9, and the eleventh to fourteenth transistors T11 to T14 are switching transistors.

[0150] An exemplary structure of the duration control subcircuit is shown in Figures 7 and 9. Those skilled in the art will readily appreciate that the implementation of the duration control subcircuit is not limited thereto.

[0151] In an exemplary embodiment, the configuration of the fourteenth transistor T14 is beneficial to the timing setting of the driving chip, and can provide a wider range of applicability for the configuration of the driving chip.

[0152] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0153] Figure 10 is an equivalent circuit diagram 1 of a pixel driving circuit. In an exemplary embodiment, as shown in Figure 10, the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: an eighth transistor T8 to a thirteenth transistor T13 and a second capacitor C2 to a fourth capacitor C4. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third node N 3, a second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light emitting device L; a control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal RST2, a first electrode of the eighth transistor T8 is electrically connected to the initial signal terminal INIT, and a second electrode of the eighth transistor T8 is electrically connected to the sixth node N6; a control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal RST3, a first electrode of the ninth transistor T9 is electrically connected to the reference signal terminal REF, and a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; a control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, and a control electrode of the tenth transistor T10 is electrically connected to the fifth node N5. A first electrode of the transistor T10 is electrically connected to the first node N1, and a second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; a control electrode of the eleventh transistor T11 is electrically connected to the first scan signal terminal Gate1, a first electrode of the eleventh transistor T11 is electrically connected to the duration data signal terminal DataT, and a second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5; a control electrode of the twelfth transistor T12 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VDD, and a second electrode of the twelfth transistor T12 is electrically connected to the first node N1;A control electrode of the thirteenth transistor T13 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal VSS, and a second electrode of the thirteenth transistor T13 is electrically connected to the sixth node N6. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4. A first end of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and a second end of the second capacitor C2 is electrically connected to the fifth node N5. A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6. A first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0154] In an exemplary embodiment, the first to sixth transistors T1 to T6 and the eighth to thirteenth transistors T8 to T13 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0155] In an exemplary embodiment, at least one of the first to sixth transistors T1 to T6 and the eighth to thirteenth transistors T8 to T13 may be an N-type transistor. Any one of the first to sixth transistors T1 to T6 and the eighth to thirteenth transistors T8 to T13 may be an N-type transistor.

[0156] In an exemplary embodiment, at least one of the first to sixth transistors T1 to T6 and the eighth to thirteenth transistors T8 to T13 may have a double gate structure or a bottom gate structure to facilitate adjustment of the threshold voltage of the transistor.

[0157] In an exemplary embodiment, at least one of the first to sixth transistors T1 to T6 and the eighth to thirteenth transistors T8 to T13 may be an oxide transistor. The active layer of the oxide transistor may be an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0158] FIG11 is a second equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG11 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a seventh transistor T7 and a first capacitor C1, and the duration control subcircuit includes: an eighth transistor T8 to a thirteenth transistor T13 and a second capacitor C2 to a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third node The first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VDD, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal RST2, the first electrode of the eighth transistor T8 is electrically connected to the initial signal terminal INIT, and the second electrode of the eighth transistor T8 is electrically connected to the sixth node N6; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal RST3 a first electrode of the ninth transistor T9 is electrically connected to the reference signal terminal REF, a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; a control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, a first electrode of the tenth transistor T10 is electrically connected to the first node N1, and a second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; a control electrode of the eleventh transistor T11 is electrically connected to the first scan signal terminal Gate1, a first electrode of the eleventh transistor T11 is electrically connected to the duration data signal terminal DataT, and a second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5;A control electrode of the twelfth transistor T12 is electrically connected to the second light-emitting signal terminal EM2, a first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VDD, and a second electrode of the twelfth transistor T12 is electrically connected to the first node N1. A control electrode of the thirteenth transistor T13 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal VSS, and a second electrode of the thirteenth transistor T13 is electrically connected to the sixth node N6. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4. A first end of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and a second end of the second capacitor C2 is electrically connected to the fifth node N5. A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6. A first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0159] In an exemplary embodiment, the first to thirteenth transistors T1 to T13 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0160] In an exemplary embodiment, at least one of the first to thirteenth transistors T1 to T13 may be an N-type transistor. Any one of the first to thirteenth transistors T1 to T13 may be an N-type transistor.

[0161] In an exemplary embodiment, at least one of the first to thirteenth transistors T1 to T13 may adopt a double-gate structure or a bottom-gate structure to facilitate adjustment of a threshold voltage of the transistor.

[0162] In an exemplary embodiment, at least one of the first to thirteenth transistors T1 to T13 may be an oxide transistor. The active layer of the oxide transistor may be an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0163] Figure 12 is the equivalent circuit diagram 3 of the pixel driving circuit. In an exemplary embodiment, as shown in Figure 12, the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a sixth transistor T6 and a first capacitor C1, and the duration control subcircuit includes: an eighth transistor T8 to a fourteenth transistor T14 and a second capacitor C2 to a fourth capacitor C4. Among them, the control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third node N 3, the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light emitting device; the control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal RST2, the first electrode of the eighth transistor T8 is electrically connected to the initial signal terminal INIT, and the second electrode of the eighth transistor T8 is electrically connected to the sixth node N6; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal RST3, the first electrode of the ninth transistor T9 is electrically connected to the reference signal terminal REF, and the second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, and the tenth transistor T10 is electrically connected to the fifth node N5. A first electrode of the transistor T10 is electrically connected to the seventh node N7, and a second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; a control electrode of the eleventh transistor T11 is electrically connected to the first scan signal terminal Gate1, a first electrode of the eleventh transistor T11 is electrically connected to the duration data signal terminal DataT, and a second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5; a control electrode of the twelfth transistor T12 is electrically connected to the second light emitting signal terminal EM2, a first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VDD, and a second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7;A control electrode of the thirteenth transistor T13 is electrically connected to the first light-emitting signal terminal EM1, a first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal VSS, and a second electrode of the thirteenth transistor T13 is electrically connected to the sixth node N6. A control electrode of the fourteenth transistor T14 is electrically connected to the third scan signal terminal Gate3, a first electrode of the fourteenth transistor T14 is electrically connected to the seventh node N7, and a second electrode of the fourteenth transistor T14 is electrically connected to the first node N1. A first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the fourth node N4. A first end of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and a second end of the second capacitor C2 is electrically connected to the fifth node N5. A first end of the third capacitor C3 is electrically connected to the fifth node N5, and a second end of the third capacitor C3 is electrically connected to the sixth node N6. A first end of the fourth capacitor C4 is electrically connected to the sixth node N6, and a second end of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0164] In an exemplary embodiment, the first to sixth transistors T1 to T6 and the eighth to fourteenth transistors T8 to T14 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0165] In an exemplary embodiment, at least one of the first to sixth transistors T1 to T6 and the eighth to fourteenth transistors T8 to T14 may be an N-type transistor. Any one of the first to sixth transistors T1 to T6 and the eighth to fourteenth transistors T8 to T14 may be an N-type transistor.

[0166] In an exemplary embodiment, at least one of the first to sixth transistors T1 to T6 and the eighth to fourteenth transistors T8 to T14 may have a double gate structure or a bottom gate structure to facilitate adjustment of the threshold voltage of the transistor.

[0167] In an exemplary embodiment, at least one of the first to sixth transistors T1 to T6 and the eighth to fourteenth transistors T8 to T14 may be an oxide transistor. The active layer of the oxide transistor may be an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0168] FIG13 is a fourth equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, as shown in FIG13 , the current control subcircuit in the pixel driving circuit includes: a first transistor T1 to a seventh transistor T7 and a first capacitor C1, and the duration control subcircuit includes: an eighth transistor T8 to a fourteenth transistor T14 and a second capacitor C2 to a fourth capacitor C4. The control electrode of the first transistor T1 is electrically connected to the first reset signal terminal RST1, the first electrode of the first transistor T1 is electrically connected to the initial signal terminal INIT, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4; the control electrode of the second transistor T2 is electrically connected to the first scan signal terminal Gate1, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the first node N1. The second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal Gate1, the first electrode of the fourth transistor T4 is connected to the current data signal terminal Data1, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the control electrode of the fifth transistor T5 is electrically connected to the first light-emitting signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the first light-emitting signal terminal EM1, and the first electrode of the sixth transistor T6 is electrically connected to the third node The first electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VDD, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1; the control electrode of the eighth transistor T8 is electrically connected to the second reset signal terminal RST2, the first electrode of the eighth transistor T8 is electrically connected to the initial signal terminal INIT, and the second electrode of the eighth transistor T8 is electrically connected to the sixth node N6; the control electrode of the ninth transistor T9 is electrically connected to the third reset signal terminal RST3 a first electrode of the ninth transistor T9 is electrically connected to the reference signal terminal REF, a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5; a control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, a first electrode of the tenth transistor T10 is electrically connected to the seventh node N7, and a second electrode of the tenth transistor T10 is electrically connected to the sixth node N6; a control electrode of the eleventh transistor T11 is electrically connected to the first scan signal terminal Gate1, a first electrode of the eleventh transistor T11 is electrically connected to the duration data signal terminal DataT, and a second electrode of the eleventh transistor T11 is electrically connected to the fifth node N5;The control electrode of the twelfth transistor T12 is electrically connected to the second light emitting signal terminal EM2, the first electrode of the twelfth transistor T12 is electrically connected to the first power supply terminal VDD, and the second electrode of the twelfth transistor T12 is electrically connected to the seventh node N7; the control electrode of the thirteenth transistor T13 is electrically connected to the first light emitting signal terminal EM1, the first electrode of the thirteenth transistor T13 is electrically connected to the second power supply terminal VSS, and the second electrode of the thirteenth transistor T13 is electrically connected to the sixth node N6; the control electrode of the fourteenth transistor T14 is electrically connected to the third scan signal terminal Gate3, and the first electrode of the fourteenth transistor T14 is electrically connected to the seventh node N7. The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the fourth node N4. The first terminal of the second capacitor C2 is electrically connected to the ramp signal terminal SWP, and the second terminal of the second capacitor C2 is electrically connected to the fifth node N5. The first terminal of the third capacitor C3 is electrically connected to the fifth node N5, and the second terminal of the third capacitor C3 is electrically connected to the sixth node N6. The first terminal of the fourth capacitor C4 is electrically connected to the sixth node N6, and the second terminal of the fourth capacitor C4 is electrically connected to the second power supply terminal VSS.

[0169] In an exemplary embodiment, the first to fourteenth transistors T1 to T14 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process, reduce the manufacturing difficulty of the display panel, and improve the product yield.

[0170] In an exemplary embodiment, at least one of the first to fourteenth transistors T1 to T14 may be an N-type transistor. For example, any one of the first to fourteenth transistors T1 to T14 may be an N-type transistor.

[0171] In an exemplary embodiment, at least one of the first to fourteenth transistors T1 to T14 may adopt a double-gate structure or a bottom-gate structure to facilitate adjustment of a threshold voltage of the transistor.

[0172] In an exemplary embodiment, at least one of the first to fourteenth transistors T1 to T14 may be an oxide transistor. The active layer of the oxide transistor may be an oxide semiconductor. Oxide thin film transistors have advantages such as low leakage current, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0173] In an exemplary embodiment, the first reset signal terminal RST1 is a single pulse signal and is an active level signal during the first and second time periods of at least one display frame, and is an inactive level signal during the third to fifth time periods. The first time period occurs before the second time period, the second time period occurs before the third time period, the third time period occurs before the fourth time period, and the fourth time period occurs before the fifth time period.

[0174] In an exemplary embodiment, the second reset signal terminal RST2 is a single pulse signal, and is a valid level signal in a first time period of at least one display frame, and is an invalid level signal in a second time period to a fifth time period.

[0175] In an exemplary embodiment, the third reset signal terminal RST3 is a single pulse signal, and is a valid level signal in the first and second time periods of at least one display frame, and is an invalid level signal in the third to fifth time periods.

[0176] In an exemplary embodiment, the first scan signal terminal Gate1 is a single pulse signal and is a valid level signal in the third time period of at least one display frame and is an invalid level signal in the first, second, fourth and fifth time periods.

[0177] In an exemplary embodiment, the signal of the first light emitting signal terminal EM1 is a single pulse signal, and is a valid level signal in the fifth time period of at least one display frame, and is an invalid level signal in the first to fourth time periods.

[0178] In an exemplary embodiment, the signal of the second light emitting signal terminal EM2 is a single pulse signal, and is a valid level signal in the second time period of at least one display frame, and is an invalid level signal in the first time period and the third time period to the fifth time period.

[0179] In an exemplary embodiment, before the signal at the first luminous signal terminal EM1 becomes an active level signal (i.e., during the first to fourth time periods), the signal at the ramp signal terminal SWP becomes a first signal, which is a constant voltage signal. The voltage value of the first signal may be 5 volts to 7 volts, and illustratively, the voltage value of the first signal may be 6 volts. When the signal at the first luminous signal terminal EM1 becomes an active level signal (i.e., during the fifth time period), the signal at the ramp signal terminal SWP becomes a second signal, which is a ramp signal, and the voltage value of the second signal gradually increases.

[0180] In an exemplary embodiment, the initial signal terminal INIT and the second power terminal VSS may be the same signal terminal.

[0181] In an exemplary embodiment, the first reset signal terminal RST1 and the third reset signal terminal RST3 may be the same signal terminal.

[0182] In an exemplary embodiment, the second scan signal terminal Gate2 and the first reset signal terminal RST1 may be the same signal terminal.

[0183] In an exemplary embodiment, the time when the signal of the third scanning signal terminal Gate3 is an active level signal at least partially overlaps the time when the signal of the first emitting signal terminal EM1 is an active level signal. Exemplarily, the third scanning signal terminal Gate3 and the first emitting signal terminal EM1 can be the same signal terminal.

[0184] In an exemplary embodiment, when the third scan signal terminal Gate3 and the first light-emitting signal terminal EM1 are different signal terminals, the signal of the third scan signal terminal Gate3 includes two pulse signals. The third scan signal terminal Gate3 is an active level signal during the second time period and the entire time period including the fourth time period and the fifth time period, and is an inactive level signal during the first time period and the third time period.

[0185] In an exemplary embodiment, the voltage value of the signal at the reference signal terminal REF may be approximately 2 volts to 3 volts. Exemplarily, the voltage value of the signal at the reference signal terminal REF may be approximately 2.5 volts.

[0186] In an exemplary embodiment, the voltage value of the signal at the initial signal terminal INIT may be approximately 1 volt to 2 volts. Exemplarily, the voltage value of the signal at the initial signal terminal INIT may be approximately 1.5 volts.

[0187] In an exemplary embodiment, at least one of the first capacitor C1 to the fourth capacitor C4 can be a capacitor device manufactured by a process. For example, the capacitor device can be realized by making a special capacitor electrode, and the multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, at least one of the first capacitor C1 to the fourth capacitor C4 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of at least one of the first capacitor C1 to the fourth capacitor C4 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0188] FIG14 is an operating timing diagram of the pixel driving circuit provided in FIG10. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit illustrated in FIG10. The pixel driving circuit in FIG10 includes twelve transistors (first to sixth transistors T1 to T6, eighth to thirteenth transistors T8 to T13) and four capacitors (first to fourth capacitors C1 to C4). The first to sixth transistors T1 to T6, eighth to thirteenth transistors T8 to T13 are N-type transistors.

[0189] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0190] In the first phase S11, referred to as the initialization phase, the signals at the first reset signal terminal RST1, the second reset signal terminal RST2, and the third reset signal terminal RST3 are high-level signals, while the first scan signal terminal Gate1, the first emission signal terminal EM1, and the second emission signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the eighth transistor T8, and the ninth transistor T9 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, and the eleventh transistor T11 to the thirteenth transistor T13 are turned off.

[0191] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is written to the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The eighth transistor T8 is turned on, and the signal of the initial signal terminal INIT is written to the sixth node N6, the sixth node N6 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal terminal REF is written to the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. At the same time, the voltage difference between the fifth node N5 and the sixth node N6 can make the tenth transistor T10 turned on, and the signal of the sixth node N6 is written to the first node N1, the first node N1 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The voltage difference between the first node N1 and the third node N3 can make the third transistor T3 turned on, and the light-emitting device L does not emit light. In this stage, the voltage value V of the signal at the fourth node N4 is N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vinit.

[0192] In an exemplary embodiment, the initialization of the fourth node N4 , the fifth node N5 , and the sixth node N6 may be performed in stages or simultaneously, which is not limited in the present disclosure.

[0193] In the second phase S12, referred to as the threshold compensation phase, the signals at the first reset signal terminal RST1, the second emission signal terminal EM2, and the third reset signal terminal RST3 are high-level signals, while the second reset signal terminal RST2, the first scan signal terminal Gate1, and the first emission signal terminal EM1 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the ninth transistor T9, and the twelfth transistor T12 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.

[0194] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is continuously written into the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal terminal REF is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The third transistor T3 and the tenth transistor T10 are continuously turned on, and the signal of the first power supply terminal VDD is written into the first node N1 through the turned-on twelfth transistor T12, so that the potential of the signal of the first node N1 gradually increases. The third transistor T3 is continuously turned on, and the signal of the first power supply terminal VDD is written into the sixth node N6 through the turned-on tenth transistor T10 and the twelfth transistor T12, so that the potential of the signal of the sixth node N6 gradually increases until the voltage value of the signal of the sixth node N6 reaches V N6 =Vref-Vth2, where Vth2 is the threshold voltage of the tenth transistor T10. At this time, the voltage stored in the third capacitor C3 is Vth2. When the voltage value of the signal at the sixth node N6 is V N6 =Vref-Vth2, the tenth transistor T10 starts to turn off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vref-Vth2, the light emitting device L does not emit light.

[0195] In the third phase S13, referred to as the data writing phase, the signal at the first scanning signal terminal Gate1 is a high-level signal, while the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal, the current data signal terminal Data1 is written with a current data signal, and the duration data signal terminal DataT is written with a duration data signal. The second transistor T2, the fourth transistor T4, and the eleventh transistor T11 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are turned off.

[0196] The second transistor T2 and the fourth transistor T4 are turned on, and the current data signal is charged to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2 until the voltage value of the signal at the first node N1 reaches V N1 =V DataI +Vth1, V DataI is the voltage value of the current data signal, Vth1 is the threshold voltage of the third transistor T3. When the eleventh transistor T11 is turned on, the time data signal is written into the fifth node N5, and the voltage value of the signal at the fifth node N5 jumps from Vref in the previous stage to V in the current stage. DataT , V DataT is the voltage value of the time-long data signal. Under the action of the third capacitor C3, the voltage value of the signal at the sixth node N6 jumps to V DataT -Vth2, the tenth transistor T10 is continuously turned off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =V DataT , the voltage value V of the signal at the sixth node N6 N6 =V DataT -Vth2, the light-emitting device L does not emit light.

[0197] In the fourth phase S14, referred to as the sustain phase, the first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals, and the signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 to the thirteenth transistor T13 are turned off. The third transistor T3 remains in the on state from the previous phase, and the tenth transistor T10 remains in the off state from the previous phase.

[0198] In the fifth stage S15, referred to as the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the second signal. The fifth transistor T5, the sixth transistor T6, and the thirteenth transistor T13 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are turned off.

[0199] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power signal of the first power supply terminal VDD provides a first driving signal to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the light-emitting device L emits light. In this stage, the voltage value of the signal at the ramp signal terminal SWP gradually increases. Under the action of the second capacitor C2, the signal of the fifth node N5 also gradually increases. When the voltage value of the signal at the fifth node N5 reaches V N5 When the voltage value of the signal at the fifth node N5 reaches V N5 = V1, the tenth transistor T10 is turned on, and the low-level signal of the second power supply terminal VSS is written to the first node N1 through the turned-on thirteenth transistor T13 and the tenth transistor T10, so that the third transistor N3 is turned off. At this time, the light-emitting device L does not emit light, thereby realizing the control of the light-emitting duration of the light-emitting device L by the duration control sub-current. That is, when the tenth transistor T10 is turned on, the light-emitting stage ends.

[0200] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode (ie, the first node N1) and the first electrode (the second node N2). DataI +Vth1, the voltage value of the signal at the second node N2 is Vdd, Vdd is the voltage value of the signal at the first power supply end, so the driving current of the third transistor T3 satisfies: I=K*(Vgs-Vth1) 2 =K*(V DataI -Vdd) 2

[0201] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0202] FIG15 is an operating timing diagram of the pixel driving circuit shown in FIG11. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit shown in FIG11. The pixel driving circuit in FIG11 includes thirteen transistors (first transistor T1 to thirteen transistor T13) and four capacitors (first capacitor C1 to fourth capacitor C4). The first transistor T1 to the thirteenth transistor T13 are N-type transistors.

[0203] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0204] In the first phase S21, referred to as the initialization phase, the signals at the first reset signal terminal RST1, the second reset signal terminal RST2, the second scan signal terminal Gate2, and the third reset signal terminal RST3 are high-level signals, while the signals at the first scan signal terminal Gate1, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, and the eleventh transistor T11 to the thirteenth transistor T13 are turned off.

[0205] The first transistor T1 is turned on, and the signal from the initial signal terminal INIT is written to the fourth node N4, initializing (resetting) the fourth node N4 and clearing the pre-stored voltage therein, completing initialization. The eighth transistor T8 is turned on, and the signal from the initial signal terminal INIT is written to the sixth node N6, initializing (resetting) the sixth node N6 and clearing the pre-stored voltage therein, completing initialization. The ninth transistor T9 is turned on, and the signal from the reference signal terminal REF is written to the fifth node N5, initializing (resetting) the fifth node N5 and clearing the pre-stored voltage therein, completing initialization. The seventh transistor T7 is turned on, and the signal from the first power supply terminal VDD is written to the first node N1, initializing (resetting) the first node N1 and clearing the pre-stored voltage therein, completing initialization. The voltage difference between the first node N1 and the third node N3 can cause the third transistor T3 to turn on, and the light-emitting device L does not emit light.

[0206] In an exemplary embodiment, the initialization of the fourth node N4 , the fifth node N5 , and the sixth node N6 may be performed in stages or simultaneously, which is not limited in the present disclosure.

[0207] In the second stage S22, referred to as the threshold compensation stage, the signals at the first reset signal terminal RST1, the second emission signal terminal EM2, and the third reset signal terminal RST3 are high-level signals, while the second scan signal terminal Gate2, the second reset signal terminal RST2, the first scan signal terminal Gate1, and the first emission signal terminal EM1 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the ninth transistor T9, and the twelfth transistor T12 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.

[0208] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is continuously written into the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal terminal REF is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The third transistor T3 and the tenth transistor T10 are continuously turned on, and the signal of the first power supply terminal VDD is written into the first node N1 through the turned-on twelfth transistor T12, so that the potential of the signal of the first node N1 gradually increases. The third transistor T3 is continuously turned on, and the signal of the first power supply terminal VDD is written into the sixth node N6 through the turned-on tenth transistor T10 and the twelfth transistor T12, so that the potential of the signal of the sixth node N6 gradually increases until the voltage value of the signal of the sixth node N6 reaches V N6 =Vref-Vth2, where Vth2 is the threshold voltage of the tenth transistor T10. At this time, the voltage stored in the third capacitor C3 is Vth2. When the voltage value of the signal at the sixth node N6 is V N6 =Vref-Vth2, the tenth transistor T10 starts to turn off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vref-Vth2, the light emitting device L does not emit light.

[0209] In the third phase S23, referred to as the data writing phase, the signal at the first scan signal terminal Gate1 is a high-level signal, while the second scan signal terminal Gate2, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal, the current data signal terminal Data1 is written with a current data signal, and the duration data signal terminal DataT is written with a duration data signal. The second transistor T2, the fourth transistor T4, and the eleventh transistor T11 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the twelfth transistor T12, and the thirteenth transistor T13 are turned off.

[0210] The second transistor T2 and the fourth transistor T4 are turned on, and the current data signal is charged to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2 until the voltage value of the signal at the first node N1 meets V N1 =V DataI +Vth1, V DataI is the voltage value of the current data signal, Vth1 is the threshold voltage of the third transistor T3. When the eleventh transistor T11 is turned on, the time data signal is written into the fifth node N5, and the voltage value of the signal at the fifth node N5 jumps from Vref in the previous stage to V in the current stage. DataT , V DataT is the voltage value of the time-long data signal. Under the action of the third capacitor C3, the voltage value of the signal at the sixth node N6 jumps to V DataT -Vth2, the tenth transistor T10 is continuously turned off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =V DataT , the voltage value of the signal at the sixth node N6 is V N6 =V DataT -Vth2, the light-emitting device L does not emit light.

[0211] In the fourth phase S24, referred to as the sustain phase, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals, and the signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the second transistor T2, the fourth transistor T4 to the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 to the thirteenth transistor T13 are turned off. The third transistor T3 remains on, and the tenth transistor T10 remains off, as in the previous phase.

[0212] In the fifth stage S25, referred to as the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the second signal. The fifth transistor T5, the sixth transistor T6, and the thirteenth transistor T13 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are turned off.

[0213] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power signal of the first power supply terminal VDD provides a first driving signal to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the light-emitting device L emits light. In this stage, the voltage value of the signal at the ramp signal terminal SWP gradually increases. Under the action of the second capacitor C2, the signal of the fifth node N5 also gradually increases. When the voltage value of the signal at the fifth node N5 reaches V N5 When the voltage value of the signal at the fifth node N5 reaches V N5 = V1, the tenth transistor T10 is turned on, and the low-level signal of the second power supply terminal VSS is written to the first node N1 through the turned-on thirteenth transistor T13 and the tenth transistor T10, so that the third transistor N3 is turned off. At this time, the light-emitting device L does not emit light, thereby realizing the control of the light-emitting duration of the light-emitting device L by the duration control sub-current. That is, when the tenth transistor T10 is turned on, the light-emitting stage ends.

[0214] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode (ie, the first node N1) and the first electrode (the second node N2). DataI +Vth1, the voltage value of the signal at the second node N2 is Vdd, Vdd is the voltage value of the signal at the first power supply terminal, and thus the driving current of the third transistor T3 is: I=K*(Vgs-Vth1) 2 =K*(V DataI -Vdd) 2

[0215] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0216] FIG16 is an operating timing diagram of the pixel driving circuit provided in FIG12. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit illustrated in FIG12. The pixel driving circuit in FIG12 includes thirteen transistors (first to sixth transistors T1 to T6, eighth to fourteenth transistors T8 to T14) and four capacitors (first to fourth capacitors C1 to C4). The first to sixth transistors T1 to T6, eighth to fourteenth transistors T8 to T14 are N-type transistors.

[0217] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0218] In the first phase S31, referred to as the initialization phase, the signals at the first reset signal terminal RST1, the second reset signal terminal RST2, and the third reset signal terminal RST3 are high-level signals, while the first scan signal terminal Gate1, the third scan signal terminal Gate3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the eighth transistor T8, and the ninth transistor T9 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, and the eleventh transistor T11 to the fourteenth transistor T14 are turned off.

[0219] The first transistor T1 is turned on, and the signal from the initial signal terminal INIT is written to the fourth node N4, initializing (resetting) the fourth node N4 and clearing the pre-stored voltage therein, completing initialization. The eighth transistor T8 is turned on, and the signal from the initial signal terminal INIT is written to the sixth node N6, initializing (resetting) the sixth node N6 and clearing the pre-stored voltage therein, completing initialization. The ninth transistor T9 is turned on, and the signal from the reference signal terminal REF is written to the fifth node N5, initializing (resetting) the fifth node N5 and clearing the pre-stored voltage therein, completing initialization. At the same time, the voltage difference between the fifth node N5 and the sixth node N6 can turn on the tenth transistor T10. Since no signal is input from the first node N1 to the third node N3, the third transistor T3 remains off, and the light-emitting device L does not emit light.

[0220] In an exemplary embodiment, the initialization of the fourth node N4 , the fifth node N5 , and the sixth node N6 may be performed in stages or simultaneously, which is not limited in the present disclosure.

[0221] In the second stage S32, referred to as the threshold compensation stage, the signals at the first reset signal terminal RST1, the second emission signal terminal EM2, the third reset signal terminal RST3, and the third scan signal terminal Gate3 are high-level signals, while the second reset signal terminal RST2, the first scan signal terminal Gate1, and the first emission signal terminal EM1 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the ninth transistor T9, the twelfth transistor T12, and the fourteenth transistor T14 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.

[0222] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is continuously written into the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal terminal REF is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The tenth transistor T10 is continuously turned on, and the signal of the first power supply terminal VDD is written into the first node N1 through the turned-on twelfth transistor T12 and the fourteenth transistor T14, so that the potential of the signal at the first node N1 gradually increases. The third transistor T3 is turned on, and the signal of the first power supply terminal VDD is written into the sixth node N6 through the turned-on tenth transistor T10 and the twelfth transistor T12, so that the potential of the signal at the sixth node N6 gradually increases until the voltage value of the signal at the sixth node N6 reaches V N6=Vref-Vth2, where Vth2 is the threshold voltage of the tenth transistor T10. At this time, the voltage stored in the third capacitor C3 is Vth2. When the voltage value of the signal at the sixth node N6 is V N6 =Vref-Vth2, the tenth transistor T10 starts to turn off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vref-Vth2, the light emitting device L does not emit light.

[0223] In the third phase S33, referred to as the data writing phase, the signal at the first scanning signal terminal Gate1 is a high-level signal, while the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the third scanning signal terminal Gate3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal, the current data signal terminal Data1 is written with a current data signal, and the duration data signal terminal DataT is written with a duration data signal. The second transistor T2, the fourth transistor T4, and the eleventh transistor T11 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the twelfth through fourteenth transistors T12 through T14 are turned off.

[0224] The second transistor T2 and the fourth transistor T4 are turned on, and the current data signal is charged to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2 until the voltage value of the signal at the first node N1 meets V N1 =V DataI +Vth1, V DataI is the voltage value of the current data signal, Vth1 is the threshold voltage of the third transistor T3. When the eleventh transistor T11 is turned on, the time data signal is written into the fifth node N5, and the voltage value of the signal at the fifth node N5 jumps from Vref in the previous stage to V in the current stage. DataT , V DataT is the voltage value of the time-long data signal. Under the action of the third capacitor C3, the voltage value of the signal at the sixth node N6 jumps to V DataT -Vth2, the tenth transistor T10 is continuously turned off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =V DataT , the voltage value of the signal at the sixth node N6 is V N6 =V DataT -Vth2, the light-emitting device L does not emit light.

[0225] In the fourth phase S34, referred to as the sustain phase, the signal at the third scan signal terminal Gate3 is a high-level signal. The first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The fourteenth transistor T14 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 to the fourteenth transistor T14 are turned off. The third transistor T3 remains on in the previous phase, and the tenth transistor T10 remains off in the previous phase.

[0226] In the fifth stage S35, referred to as the light-emitting stage, the signal at the first light-emitting signal terminal EM1 is a high-level signal, while the first scan signal terminal Gate1, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the second signal. The fifth transistor T5, the sixth transistor T6, the thirteenth transistor T13, and the fourteenth transistor T14 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, the eleventh transistor T11, and the twelfth transistor T12 are turned off.

[0227] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power signal of the first power supply terminal VDD provides a first driving signal to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the light-emitting device L emits light. In this stage, the voltage value of the signal at the ramp signal terminal SWP gradually increases. Under the action of the second capacitor C2, the signal of the fifth node N5 also gradually increases. When the voltage value of the signal at the fifth node N5 reaches V N5 When the voltage value of the signal at the fifth node N5 reaches V N5 = V1, the tenth transistor T10 is turned on, and the low-level signal of the second power supply terminal VSS is written to the first node N1 through the turned-on thirteenth transistor T13, the tenth transistor T10, and the fourteenth transistor T14, so that the third transistor N3 is turned off. At this time, the light-emitting device L does not emit light, thereby realizing the control of the light-emitting duration of the light-emitting device L by the duration control sub-current. That is, when the tenth transistor T10 is turned on, the light-emitting stage ends.

[0228] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode (ie, the first node N1) and the first electrode (the second node N2). DataI +Vth1, the voltage value of the signal at the second node N2 is Vdd, Vdd is the voltage value of the signal at the first power supply terminal, and thus the driving current of the third transistor T3 is: I=K*(Vgs-Vth1) 2 =K*(V DataI -Vdd) 2

[0229] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0230] FIG17 is an operating timing diagram of the pixel driving circuit shown in FIG13. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit shown in FIG13. The pixel driving circuit in FIG13 includes fourteen transistors (first transistor T1 to fourteenth transistor T14) and four capacitors (first capacitor C1 to fourth capacitor C4). The first transistor T1 to fourteenth transistor T14 are N-type transistors.

[0231] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0232] In the first phase S41, referred to as the initialization phase, the signals at the first reset signal terminal RST1, the second reset signal terminal RST2, the second scan signal terminal Gate2, and the third reset signal terminal RST3 are high-level signals, while the signals at the first scan signal terminal Gate1, the third scan signal terminal Gate3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on. The second transistor T2, the fourth transistor T6, and the eleventh transistor T11 through the fourteenth transistor T14 are turned off.

[0233] The first transistor T1 is turned on, and the signal from the initial signal terminal INIT is written to the fourth node N4, initializing (resetting) the fourth node N4 and clearing the pre-stored voltage therein, completing initialization. The eighth transistor T8 is turned on, and the signal from the initial signal terminal INIT is written to the sixth node N6, initializing (resetting) the sixth node N6 and clearing the pre-stored voltage therein, completing initialization. The ninth transistor T9 is turned on, and the signal from the reference signal terminal REF is written to the fifth node N5, initializing (resetting) the fifth node N5 and clearing the pre-stored voltage therein, completing initialization. The seventh transistor T7 is turned on, and the signal from the first power supply terminal VDD is written to the first node N1, initializing (resetting) the first node N1 and clearing the pre-stored voltage therein, completing initialization. The voltage difference between the first node N1 and the third node N3 can cause the third transistor T3 to turn on, and the light-emitting device L does not emit light.

[0234] In an exemplary embodiment, the initialization of the fourth node N4 , the fifth node N5 , and the sixth node N6 may be performed in stages or simultaneously, which is not limited in the present disclosure.

[0235] In the second stage S42, referred to as the threshold compensation stage, the signals at the first reset signal terminal RST1, the second emission signal terminal EM2, the third scan signal terminal Gate3, and the third reset signal terminal RST3 are high-level signals, while the second scan signal terminal Gate2, the second reset signal terminal RST2, the first scan signal terminal Gate1, and the first emission signal terminal EM1 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The first transistor T1, the ninth transistor T9, the twelfth transistor T12, and the fourteenth transistor T14 are turned on. The second transistor T2, the fourth transistor T4 to the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the eleventh transistor T11, and the thirteenth transistor T13 are turned off.

[0236] The first transistor T1 is turned on, and the signal of the initial signal terminal INIT is continuously written into the fourth node N4, the fourth node N4 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal terminal REF is written into the fifth node N5, the fifth node N5 is initialized (reset), the pre-stored voltage inside it is cleared, and the initialization is completed. The third transistor T3 and the tenth transistor T10 are continuously turned on, and the signal of the first power supply terminal VDD is continuously written into the first node N1 through the turned-on twelfth transistor T12 and the fourteenth transistor T14. The third transistor T3 is continuously turned on, and the signal of the first power supply terminal VDD is written into the sixth node N6 through the turned-on tenth transistor T10 and the twelfth transistor T12, so that the potential of the signal of the sixth node N6 gradually increases until the voltage value of the signal of the sixth node N6 reaches VDD. N6=Vref-Vth2, where Vth2 is the threshold voltage of the tenth transistor T10. At this time, the voltage stored in the third capacitor C3 is Vth2. When the voltage value of the signal at the sixth node N6 is V N6 =Vref-Vth2, the tenth transistor T10 starts to turn off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =Vref, the voltage value of the signal at the sixth node N6 V N6 =Vref-Vth2, the light emitting device L does not emit light.

[0237] In the third phase S43, referred to as the data writing phase, the signal at the first scan signal terminal Gate1 is a high-level signal, while the second scan signal terminal Gate2, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the third scan signal terminal Gate3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal, the current data signal terminal Data1 is written with a current data signal, and the duration data signal terminal DataT is written with a duration data signal. The second transistor T2, the fourth transistor T4, and the eleventh transistor T11 are turned on. The first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the twelfth through fourteenth transistors T12 through T14 are turned off.

[0238] The second transistor T2 and the fourth transistor T4 are turned on, and the current data signal is charged to the first node N1 through the turned-on fourth transistor T4, the third transistor T3 and the second transistor T2 until the voltage value of the signal at the first node N1 meets V N1 =V DataI +Vth1, V DataI is the voltage value of the current data signal, Vth1 is the threshold voltage of the third transistor T3. When the eleventh transistor T11 is turned on, the time data signal is written into the fifth node N5, and the voltage value of the signal at the fifth node N5 jumps from Vref in the previous stage to V in the current stage. DataT , V DataT is the voltage value of the time-long data signal. Under the action of the third capacitor C3, the voltage value of the signal at the sixth node N6 jumps to V DataT -Vth2, the tenth transistor T10 is continuously turned off. In this stage, the voltage value of the signal at the fourth node N4 is V N4 = Vinit, the voltage value of the signal at the fifth node N5 V N5 =V DataT , the voltage value V of the signal at the sixth node N6 N6 =VDataT -Vth2, the light-emitting device L does not emit light.

[0239] In the fourth phase S44, referred to as the sustain phase, the signal at the third scan signal terminal Gate3 is a high-level signal. The first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the first signal. The fourteenth transistor T14 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4 to the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 to the thirteenth transistor T13 are turned off. The third transistor T3 remains on, as in the previous phase, and the tenth transistor T10 remains off.

[0240] In the fifth stage S45, referred to as the light-emitting stage, the signals at the first light-emitting signal terminal EM1 and the third scan signal terminal Gate3 are high-level signals, while the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first reset signal terminal RST1, the second reset signal terminal RST2, the third reset signal terminal RST3, and the second light-emitting signal terminal EM2 are low-level signals. The signal at the ramp signal terminal SWP is the second signal. The fifth transistor T5, the sixth transistor T6, the thirteenth transistor T13, and the fourteenth transistor T14 are turned on. The first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the eleventh transistor T11 and the twelfth transistor T12 are turned off.

[0241] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power signal of the first power supply terminal VDD provides a first driving signal to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, and the light-emitting device L emits light. In this stage, the voltage value of the signal at the ramp signal terminal SWP gradually increases. Under the action of the second capacitor C2, the signal of the fifth node N5 also gradually increases. When the voltage value of the signal at the fifth node N5 reaches V N5 When the voltage value of the signal at the fifth node N5 reaches V N5= V1, the tenth transistor T10 is turned on, and the low-level signal of the second power supply terminal VSS is written to the first node N1 through the turned-on thirteenth transistor T13, the tenth transistor T10, and the fourteenth transistor T14, causing the third transistor N3 to be turned off. At this time, the light-emitting device L does not emit light, thereby achieving the control of the light-emitting duration of the light-emitting device L by the duration control sub-current. That is, when the tenth transistor T10 is turned on, the light-emitting phase ends. That is, when the tenth transistor T10 is turned on, the light-emitting phase ends.

[0242] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control electrode (ie, the first node N1) and the first electrode (the second node N2). DataI +Vth1, the voltage value of the signal at the second node N2 is Vdd, Vdd is the voltage value of the signal at the first power supply terminal, and thus the driving current of the third transistor T3 is: I=K*(Vgs-Vth1) 2 =K*(V DataI -Vdd) 2

[0243] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device L, K is a constant, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0244] In an exemplary embodiment, in the current control subcircuit, the current data signal at the current data signal terminal DataT is compensated for at the first node N1 (i.e., the control electrode of the third transistor T3) via the fourth transistor T4, the third transistor T3, and the second transistor T2. During the compensation process, the third transistor T3 acts as a diode, meaning that the current control subcircuit utilizes diode compensation. This diode compensation reduces the impact of the parasitic capacitance of the light-emitting device L on the first drive signal, avoids data jumps caused by parasitic capacitance, and improves the reliability of the pixel drive circuit.

[0245] In an exemplary embodiment, in the duration control subcircuit, the power signal from the first power supply terminal VDD is extended to the sixth node N6 (i.e., the second electrode of the tenth transistor T10) via the twelfth transistor T12 and the tenth transistor T10. The duration control subcircuit employs a source-follower compensation method. This source-follower compensation method can extend the charging time, enabling the duration control subcircuit to more accurately control the light-emitting duration. Furthermore, the duration control subcircuit is not connected to the light-emitting device and is not affected by the parasitic capacitance of the light-emitting device L, further improving the reliability of the pixel driving circuit. The compensation time in the duration control subcircuit depends on the pulse length of the signal on the second light-emitting signal line EM2. The compensation time can be adjusted by adjusting the pulse length of the signal on the second light-emitting signal line EM2.

[0246] The current control subcircuit and the duration control subcircuit in the present disclosure adopt different external compensation methods.

[0247] In a display device where the pixel driving circuit provided by an embodiment of the present disclosure is located, the worse the uniformity of the parasitic capacitance of different light-emitting devices or the more severe the color deviation, the better the improvement effect of the pixel driving circuit provided by the present disclosure on the display effect of the display device.

[0248] The present disclosure also provides a display device including a pixel driving circuit. The pixel driving circuit is the pixel driving circuit provided in any of the above embodiments, and its implementation principle and effect are similar, which will not be described in detail here.

[0249] In an exemplary embodiment, a display device may be any device that displays text or images, whether in motion (e.g., video) or fixed (e.g., still images). More specifically, the display device may be one of a variety of electronic devices, and may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, VR devices, AR devices, wireless devices, personal digital assistants (PS1s), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, camera view displays (e.g., displays for rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays for images of a piece of jewelry). The embodiments of the present disclosure do not impose any particular restrictions on the form of the above-mentioned display devices.

[0250] In an exemplary embodiment, the display device further includes: a data unit electrically connected to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light emitting signal terminal, and the second light emitting signal terminal connected to the pixel driving circuit.

[0251] In an exemplary embodiment, content displayed by a display device includes: at least one display frame, in which the data unit is configured to provide a valid level signal to a first reset signal terminal, a second reset signal terminal, and a third reset signal terminal in a first time period, and provide an invalid level signal to a first light-emitting signal terminal, a second light-emitting signal terminal, and a first scan signal terminal; provide a valid level signal to the first reset signal terminal, the third reset signal terminal, and the second light-emitting signal terminal in a second time period, and provide a valid level signal to the second reset signal terminal, the first light-emitting signal terminal, and the first scan signal terminal; provide a valid level signal to the first scan signal terminal in a third time period, and provide an invalid level signal to the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal; provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal in a fourth time period; provide a valid level signal to the first light-emitting signal terminal in a fifth time period, and provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, and the second light-emitting signal terminal.

[0252] In an exemplary embodiment, the data unit is also electrically connected to the second scanning signal terminal connected to the pixel driving circuit, and the data unit is configured to provide a valid level signal to the second scanning signal terminal in the first time period and the second time period, and to provide an invalid level signal to the second scanning signal terminal in the third time period to the fifth time period.

[0253] In an exemplary embodiment, the data unit is further electrically connected to a third scanning signal terminal connected to the pixel driving circuit, and the data unit is configured to provide a valid level signal to the third scanning signal terminal in the second time period, the fourth time period, and the fifth time period, and provide an invalid level signal to the third scanning signal terminal in the first time period and the third time period, or provide an invalid level signal to the third scanning signal terminal from the first time period to the fourth time period, and provide a valid level signal to the third scanning signal terminal in the fifth time period.

[0254] Exemplarily, the data unit may include a gate driving circuit.

[0255] In an exemplary embodiment, the data unit is further electrically connected to the ramp signal terminal connected to the pixel driving circuit, and is configured to provide a constant voltage signal to the ramp signal terminal in the first time period to the fourth time period, and provide a ramp signal to the ramp signal terminal in the fifth time period.

[0256] The embodiment of the present disclosure further provides a driving method of a pixel driving circuit, which is configured to drive the pixel driving circuit. The driving method of the pixel driving circuit may include the following steps:

[0257] The duration control subcircuit provides a second drive signal to the first node under the control of signals at the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal and the second light-emitting signal terminal.

[0258] The current control subcircuit provides a first driving signal to the light emitting device under the control of the current data signal terminal, the initial signal terminal, the first power terminal, the first scan signal terminal, the first reset signal terminal, the first light emitting signal terminal and the signal of the first node.

[0259] The pixel driving circuit is the pixel driving circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be described in detail here.

[0260] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0261] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0262] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pixel driving circuit electrically connected to a light emitting device, wherein: The pixel driving circuit includes: a current control subcircuit and a duration control subcircuit; The current control subcircuit is electrically connected to the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal, the first node, and the light-emitting device, and is configured to provide a first driving signal to the light-emitting device under the control of signals from the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal, and the first node; The duration control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, the second light-emitting signal terminal and the first node, respectively, and is configured to provide a second drive signal to the first node under the control of signals from the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal and the second light-emitting signal terminal.

2. The pixel driving circuit according to claim 1, wherein: The current control subcircuit is also electrically connected to the second scan signal terminal and is configured to provide a first drive signal to the light-emitting device under the control of the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the second scan signal terminal, the first reset signal terminal, the first light-emitting signal terminal and the signal of the first node.

3. The pixel driving circuit according to claim 1, wherein: The light emitting device comprises: a first electrode and a second electrode, and the current control subcircuit comprises: a first driving subcircuit, a first node control subcircuit and a first light emitting control subcircuit; The first driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a first driving signal to the third node under the control of signals from the first node and the second node; The first light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the first power supply terminal, the second node, the third node, and the first electrode of the light-emitting device, respectively, and is configured to provide a signal from the first power supply terminal to the second node and a signal from the third node to the first electrode of the light-emitting device under the control of a signal from the first light-emitting signal terminal; The first node control subcircuit is electrically connected to the current data signal terminal, the initial signal terminal, the first scan signal terminal, the first reset signal terminal, the first node, the second node, the third node, and the fourth node, respectively, and is configured to, under the control of the signals of the first scan signal terminal and the first reset signal terminal, provide the signal of the initial signal terminal to the fourth node, provide the signal of the current data signal terminal to the third node, and provide the signal of the second node to the first node; The fourth node is electrically connected to the first electrode of the light emitting device or the second electrode of the light emitting device.

4. The pixel driving circuit according to claim 2, wherein: The light emitting device comprises: a first electrode and a second electrode, and the current control subcircuit comprises: a first driving subcircuit, a first node control subcircuit and a first light emitting control subcircuit; The first driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a first driving signal to the third node under the control of signals from the first node and the second node; The first light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the first power terminal, the second node, the third node, and the first electrode of the light-emitting device, respectively, and is configured to provide a signal from the first power terminal to the second node and a first driving signal to the first electrode of the light-emitting device under the control of a signal from the first light-emitting signal terminal; The first node control subcircuit is respectively connected to the current data signal terminal, the initial signal terminal, the first power supply terminal, the first scan signal terminal, the second scan signal terminal, the first reset signal terminal, the first node, the second node, the third node and the fourth node. The nodes are electrically connected and configured to provide a signal from the initial signal terminal to the fourth node, a signal from the current data signal terminal to the third node, and a signal from the second node or the first power supply terminal to the first node under the control of signals from the first scan signal terminal, the first reset signal terminal, and the second scan signal terminal; The fourth node is electrically connected to the first electrode of the light emitting device or the second electrode of the light emitting device.

5. The pixel driving circuit according to claim 3, wherein: The first node control subcircuit includes: a first transistor, a second transistor, a fourth transistor and a first capacitor; the first driving subcircuit includes: a third transistor; the first light emitting control subcircuit includes: a fifth transistor and a sixth transistor; The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node; The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is connected to the current data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting device; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the fourth node.

6. The pixel driving circuit according to claim 4, wherein: The first control subcircuit includes: a first transistor, a second transistor, a fourth transistor, a seventh transistor and a first capacitor; the first drive subcircuit includes: a third transistor; the first light emitting control subcircuit includes: a fifth transistor and a sixth transistor; The control electrode of the first transistor is electrically connected to the first reset signal terminal, the first electrode of the first transistor is electrically connected to the initial signal terminal, and the second electrode of the first transistor is electrically connected to the fourth node; The control electrode of the second transistor is electrically connected to the first scan signal terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the third node; The control electrode of the fourth transistor is electrically connected to the first scan signal terminal, the first electrode of the fourth transistor is connected to the current data signal terminal, and the second electrode of the fourth transistor is electrically connected to the third node; The control electrode of the fifth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting device; The control electrode of the seventh transistor is electrically connected to the second scan signal terminal, the first electrode of the seventh transistor is electrically connected to the first power supply terminal, and the second electrode of the seventh transistor is electrically connected to the first node; A first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to the fourth node.

7. The pixel driving circuit according to any one of claims 1, 5 and 6, wherein: The duration control subcircuit is also electrically connected to the third scan signal terminal and is configured to provide a second drive signal to the first node under the control of signals from the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the third scan signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal and the second light-emitting signal terminal.

8. The pixel driving circuit according to any one of claims 1, 5 and 6, wherein: The duration control subcircuit includes: a second driving subcircuit, a second node control subcircuit and a second light emitting control subcircuit; The second driving sub-circuit is electrically connected to the fifth node, the sixth node and the first node respectively, and is configured to provide a second driving signal to the first node under the control of the signals of the fifth node and the sixth node; The second light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power terminal, the second power terminal, the sixth node, and the first node, respectively, and is configured to provide a signal from the first power terminal to the first node and a signal from the second power terminal to the sixth node under the control of signals from the first light-emitting signal terminal and the second light-emitting signal terminal; The second node control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the second power supply terminal, the second reset signal terminal, the third reset signal terminal, the first scan signal terminal, the fifth node and the sixth node, respectively, and is configured to provide the signal of the reference signal terminal or the duration data signal terminal to the fifth node, provide the signal of the initial signal terminal to the sixth node, and drive the signal of the fifth node under the control of the signal of the second reset signal terminal, the third reset signal terminal and the first scan signal terminal.

9. The pixel driving circuit according to claim 7, wherein: The duration control subcircuit includes: a second driving subcircuit, a second node control subcircuit and a second light emitting control subcircuit; The second driving sub-circuit is electrically connected to the fifth node, the sixth node, and the seventh node, respectively, and is configured to provide a second driving signal to the seventh node under the control of the signals of the fifth node and the sixth node; The second light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power terminal, the second power terminal, the sixth node, and the seventh node, respectively, and is configured to provide a signal from the first power terminal to the seventh node and a signal from the second power terminal to the sixth node under the control of signals from the first light-emitting signal terminal and the second light-emitting signal terminal; The second node control subcircuit is electrically connected to the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the second power supply terminal, the second reset signal terminal, the third reset signal terminal, the first scan signal terminal, the third scan signal terminal, the first node, the fifth node, the sixth node and the seventh node, respectively, and is configured to provide the signal of the reference signal terminal or the duration data signal terminal to the fifth node, provide the signal of the initial signal terminal to the sixth node, provide the signal of the seventh node to the first node, and drive the signal of the fifth node under the action of the signal of the ramp signal terminal.

10. The pixel driving circuit according to claim 8, wherein: The second node control subcircuit includes: an eighth transistor, a ninth transistor, an eleventh transistor, a second capacitor, a third capacitor, and a fourth capacitor; the second driving subcircuit includes: a tenth transistor; and the second light emitting control subcircuit includes: a twelfth transistor and a thirteenth transistor; a control electrode of the eighth transistor electrically connected to the second reset signal terminal, a first electrode of the eighth transistor electrically connected to the initial signal terminal, and a second electrode of the eighth transistor electrically connected to the sixth node; a control electrode of the ninth transistor electrically connected to the third reset signal terminal, a first electrode of the ninth transistor electrically connected to the reference signal terminal, and a second electrode of the ninth transistor electrically connected to the fifth node; a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to the first node, and a second electrode of the tenth transistor electrically connected to the sixth node; The control electrode of the eleventh transistor is electrically connected to the first scan signal terminal, the first electrode of the eleventh transistor is electrically connected to the duration data signal terminal, and the second electrode of the eleventh transistor is electrically connected to the fifth node; The control electrode of the twelfth transistor is electrically connected to the second light emitting signal terminal, and the first electrode of the twelfth transistor is electrically connected to the first power supply terminal. The first terminal is electrically connected to the second electrode of the twelfth transistor, and the second electrode of the twelfth transistor is electrically connected to the first node; The control electrode of the thirteenth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the sixth node; A first end of the second capacitor is electrically connected to the ramp signal end, and a second end of the second capacitor is electrically connected to the fifth node; A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the sixth node; A first end of the fourth capacitor is electrically connected to the sixth node, and a second end of the fourth capacitor is electrically connected to the second power supply end.

11. The pixel driving circuit according to claim 10, wherein: At least one transistor among the first to thirteenth transistors is an oxide transistor.

12. The pixel driving circuit according to claim 9, wherein: The second node control subcircuit includes: an eighth transistor, a ninth transistor, an eleventh transistor, a fourteenth transistor, a second capacitor, a third capacitor, and a fourth capacitor; the second driving subcircuit includes: a tenth transistor; and the second light emitting control subcircuit includes: a twelfth transistor and a thirteenth transistor; a control electrode of the eighth transistor electrically connected to the second reset signal terminal, a first electrode of the eighth transistor electrically connected to the initial signal terminal, and a second electrode of the eighth transistor electrically connected to the sixth node; a control electrode of the ninth transistor electrically connected to the third reset signal terminal, a first electrode of the ninth transistor electrically connected to the reference signal terminal, and a second electrode of the ninth transistor electrically connected to the fifth node; a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to the seventh node, and a second electrode of the tenth transistor electrically connected to the sixth node; The control electrode of the eleventh transistor is electrically connected to the first scan signal terminal, the first electrode of the eleventh transistor is electrically connected to the duration data signal terminal, and the second electrode of the eleventh transistor is electrically connected to the fifth node; The control electrode of the twelfth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and the second electrode of the twelfth transistor is electrically connected to the seventh node; The control electrode of the thirteenth transistor is electrically connected to the first light emitting signal terminal, the first electrode of the thirteenth transistor is electrically connected to the second power supply terminal, and the second electrode of the thirteenth transistor is electrically connected to the sixth node; A control electrode of the fourteenth transistor is electrically connected to the third scan signal terminal, a first electrode of the fourteenth transistor is electrically connected to the seventh node, and a second electrode of the fourteenth transistor is electrically connected to the first node; A first end of the second capacitor is electrically connected to the ramp signal end, and a second end of the second capacitor is electrically connected to the fifth node; A first end of the third capacitor is electrically connected to the fifth node, and a second end of the third capacitor is electrically connected to the sixth node; A first end of the fourth capacitor is electrically connected to the sixth node, and a second end of the fourth capacitor is electrically connected to the second power supply end.

13. The pixel driving circuit according to claim 12, wherein: At least one transistor among the first to fourteenth transistors is an oxide transistor.

14. The pixel driving circuit according to claim 1, wherein: The initial signal terminal and the second power terminal are the same signal terminal.

15. The pixel driving circuit according to claim 1, wherein: The first reset signal terminal and the third reset signal terminal are the same signal terminal.

16. The pixel driving circuit according to claim 2, wherein: The second scan signal terminal and the first reset signal terminal are the same signal terminal.

17. The pixel driving circuit according to claim 7, wherein: The time when the signal at the third scanning signal terminal is a valid level signal at least partially overlaps with the time when the signal at the first light-emitting signal terminal is a valid level signal.

18. A display device comprising: The pixel driving circuit according to any one of claims 1 to 17.

19. The display device according to claim 18, further comprising: a data unit electrically connected to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light emitting signal terminal and the second light emitting signal terminal connected to the pixel driving circuit; The content displayed by the display device includes: at least one display frame, in which the data unit is configured to provide a valid level signal to the first reset signal terminal, the second reset signal terminal, and the third reset signal terminal in a first time period, and provide an invalid level signal to the first light-emitting signal terminal, the second light-emitting signal terminal, and the first scan signal terminal; provide a valid level signal to the first reset signal terminal, the third reset signal terminal, and the second light-emitting signal terminal in a second time period, and provide a valid level signal to the second reset signal terminal, the first light-emitting signal terminal, and the first scan signal terminal; provide a valid level signal to the first scan signal terminal in a third time period, and provide an invalid level signal to the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal; provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal in a fourth time period; provide a valid level signal to the first light-emitting signal terminal in a fifth time period, and provide an invalid level signal to the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, and the second light-emitting signal terminal.

20. The display device according to claim 19, wherein The data unit is also electrically connected to the second scanning signal terminal connected to the pixel driving circuit. The data unit is configured to provide a valid level signal to the second scanning signal terminal in the first time period and the second time period, and to provide an invalid level signal to the second scanning signal terminal in the third time period to the fifth time period.

21. The display device according to claim 19 or 20, wherein: The data unit is also electrically connected to the third scanning signal terminal connected to the pixel driving circuit. The data unit is configured to provide a valid level signal to the third scanning signal terminal in the second time period, the fourth time period and the fifth time period, and provide an invalid level signal to the third scanning signal terminal in the first time period and the third time period, or provide an invalid level signal to the third scanning signal terminal from the first time period to the fourth time period, and provide a valid level signal to the third scanning signal terminal in the fifth time period.

22. The display device according to claim 19, wherein The data unit is also electrically connected to the ramp signal terminal connected to the pixel driving circuit, and is configured to provide a constant voltage signal to the ramp signal terminal from the first time period to the fourth time period, and provide a ramp signal to the ramp signal terminal in the fifth time period.

23. A method for driving a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 17, the method comprising: The duration control subcircuit provides a second driving signal to the first node under the control of signals at the duration data signal terminal, the initial signal terminal, the reference signal terminal, the ramp signal terminal, the first power supply terminal, the second power supply terminal, the first scan signal terminal, the first reset signal terminal, the second reset signal terminal, the third reset signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal; The current control subcircuit provides a first driving signal to the light emitting device under the control of the current data signal terminal, the initial signal terminal, the first power terminal, the first scan signal terminal, the first reset signal terminal, the first light emitting signal terminal and the signal of the first node.

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