Display panel and display apparatus

Abstract

A display panel and a display apparatus, which belong to the technical field of display. The display panel comprises a base substrate (SBT), a driving layer (DRL) and a pixel layer (PIXL), which are sequentially stacked, wherein the driving layer (DRL) is provided with a pixel driving circuit for driving sub-pixels (PIX), and is provided with a scanning signal line (GL) that extends in a row direction (DH) and a data signal line (DL) that extends in a column direction (DV); the pixel driving circuit comprises a data writing transistor (T4), a first electrode of the data writing transistor (T4) being electrically connected to the data signal line (DL), and a gate electrode of the data writing transistor (T4) being electrically connected to the scanning signal line (GL); the driving layer (DRL) comprises a transistor layer (TL) and a first source-drain metal layer (SD1), which are sequentially stacked on the base substrate (SBT); the gate electrode of the data writing transistor (T4) is arranged on the transistor layer (TL), and the scanning signal line (GL) is arranged on the first source-drain metal layer (SD1); and the gate electrode of the data writing transistor (T4) is electrically connected to the scanning signal line (GL) by means of a via hole. The display panel and the display apparatus provided with the display panel facilitate an improvement in display uniformity.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202410116962.7, filed on January 26, 2024, entitled “Display Panel and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] With the development of display panel technology, higher requirements have been placed on the display uniformity of display panels. The gate voltage of the data write transistor T4 can determine the switching degree of the data write transistor T4, and the switching degree of the data write transistor T4 directly affects the voltage of the gate of the data signal write drive transistor. Different gate voltages will lead to uneven display, affecting the uniformity of the display panel.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] An object of the present disclosure is to provide a display panel and a display device to improve the display uniformity of the display panel.

[0007] According to a first aspect of the present disclosure, a display panel is provided, comprising a base substrate, a drive layer, and a pixel layer stacked in sequence; the drive layer is provided with a pixel drive circuit for driving sub-pixels, and is provided with scan signal lines extending in a row direction and data signal lines extending in a column direction; the pixel drive circuit includes a data write transistor, a first electrode of the data write transistor being electrically connected to the data signal line, and a gate of the data write transistor being electrically connected to the scan signal line;

[0008] The driving layer includes a transistor layer and a first source-drain metal layer stacked in sequence on the base substrate; the gate of the data writing transistor is set in the transistor layer, and the scanning signal line is set in the first source-drain metal layer; the gate of the data writing transistor and the scanning signal line are electrically connected through a via.

[0009] According to one embodiment of the present disclosure, the transistor layer includes a low-temperature polycrystalline silicon semiconductor layer, a first gate insulating layer and a first gate layer stacked in sequence on a base substrate; the channel region of the data write transistor is located in the low-temperature polycrystalline silicon semiconductor layer; the first gate layer is provided with a transfer structure, and the gate of the data write transistor is located in the transfer structure; the transfer structure is electrically connected to the scanning signal line through a plurality of vias.

[0010] According to an embodiment of the present disclosure, the switching structure extends along a row direction, and the gates of two data writing transistors adjacent to the same row are located in the same switching structure.

[0011] According to one embodiment of the present disclosure, the display panel is further provided with an initialization running line extending along the row direction and an initialization column running line extending along the column direction. The initialization running line and the initialization column running line are electrically connected through a via at the overlapping point. The initialization running line and the initialization column running line are used to load the initialization voltage.

[0012] According to one embodiment of the present disclosure, the driving layer includes a transistor layer and a first source-drain metal layer;

[0013] The initialization running line is located in the transistor layer; the initialization column routing includes a main section of the initialization column routing located in the first source and drain metal layer and a bridge section of the initialization column routing located in the transistor layer, and the main section of the initialization column routing is electrically connected to the overlapping initialization running line through a via; the main sections of two adjacent initialization column routings along the column direction are connected through the bridge section of the initialization column routing; the bridge section of the initialization column routing overlaps with the scanning signal line.

[0014] According to an embodiment of the present disclosure, the initialization column routing includes a first initial column routing, a second initial column routing, and a third initial column routing;

[0015] The initial walking line includes a first initial walking line, a second initial walking line and a third initial walking line;

[0016] The first initial column wiring is connected to the first initial wiring through a via, and is used to load a first initialization voltage;

[0017] The second initial column wiring is connected to the second initial wiring through a via, and is used to load a second initialization voltage;

[0018] The third initial column wiring is connected to the third initial wiring through a via, and is used to load a third initialization voltage.

[0019] According to one embodiment of the present disclosure, the display panel includes a circuit area arranged in an array; the circuit area includes a first sub-circuit area and a second sub-circuit area adjacent to each other along a row direction; each thin film transistor of a pixel driving circuit is disposed in the first sub-circuit area and the second sub-circuit area;

[0020] The circuit area rows are each provided with a first initial running line, a second initial running line, and a third initial running line;

[0021] The circuit area column includes a first circuit area column, a second circuit area column and a third circuit area column arranged periodically; the first circuit area column is provided with a first initial column routing line; the second circuit area column is provided with a second initial column routing line; the third circuit area column is provided with a third initial column routing line.

[0022] According to an embodiment of the present disclosure, in the circuit area column, the initialization column wiring extends along a boundary line between the first sub-circuit area and the second sub-circuit area.

[0023] According to one embodiment of the present disclosure, the transistor layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer, and a third gate layer stacked in sequence;

[0024] The bridge section of the initialization column wiring is located in one of the first gate layer, the second gate layer and the third gate layer, and the initialization wiring is located in at least one of the other two layers.

[0025] According to an embodiment of the present disclosure, the bridge section of the initialization column wiring is located in the second gate layer; and the initialization wiring is located in the third gate layer.

[0026] According to an embodiment of the present disclosure, the driving layer includes a transistor layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence;

[0027] The initialization line is located in the transistor layer; the initialization column line is located in the second source and drain metal layer;

[0028] The first source / drain metal layer is provided with a transfer portion of an initialization column line, the initialization column line is electrically connected to the transfer portion of the initialization column line through a via hole, and the transfer portion of the initialization column line is electrically connected to the corresponding initialization line through a via hole.

[0029] According to an embodiment of the present disclosure, the first source-drain metal layer includes a first bridge portion, and the first bridge portion is connected to the gate of the driving transistor through a via hole;

[0030] The display panel further includes a metal light-shielding layer;

[0031] The metal shading layer is arranged on a side of the base substrate close to the driving layer; the metal shading layer has a first isolation trace arranged along the column direction; the orthographic projection of the first isolation trace on the base substrate is located between the first pole of the data writing transistor and the orthographic projection of the first bridge portion on the base substrate.

[0032] According to an embodiment of the present disclosure, the pixel circuit further includes a driving transistor; the first source-drain metal layer includes a first bridge portion, and the first bridge portion is connected to the gate of the driving transistor through a via hole;

[0033] The display panel further includes a metal light-shielding layer;

[0034] The metal light shielding layer is arranged on a side of the base substrate close to the driving layer; the metal light shielding layer has a first partition trace arranged along the column direction; the orthographic projection of the first bridge portion on the base substrate is located within the orthographic projection of the first partition trace on the base substrate.

[0035] According to one embodiment of the present disclosure, the second source-drain metal layer is further provided with a second conductive structure portion; the second conductive structure portion is electrically connected through a power supply voltage line located on the third source-drain metal layer; the orthographic projection of the first bridging portion on the base substrate is located within the orthographic projection of the second metal portion on the base substrate.

[0036] According to an embodiment of the present disclosure, the metal light-shielding layer can be loaded with a power supply voltage.

[0037] According to a second aspect of the present disclosure, a display device is provided, including a display panel.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0040] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0041] FIG1-1 is a schematic diagram of a pixel driving circuit and sub-pixels in an exemplary embodiment of the present disclosure.

[0042] 1-2 are schematic diagrams of a pixel driving circuit in an exemplary embodiment of the present disclosure.

[0043] FIG2 is a diagram showing a film layer structure of a display panel in an exemplary embodiment of the present disclosure.

[0044] FIG3 is a schematic diagram of a low-temperature polysilicon semiconductor layer in an exemplary embodiment of the present disclosure.

[0045] FIG4-1 is a schematic diagram of a first gate layer in an exemplary embodiment of the present disclosure.

[0046] FIG4-2 is a schematic diagram of a stack of a low-temperature polysilicon semiconductor layer and a first gate layer in an exemplary embodiment of the present disclosure.

[0047] FIG5-1 is a schematic diagram of a second gate layer in an exemplary embodiment of the present disclosure.

[0048] FIG5-2 is a schematic diagram of a stack of a low-temperature polysilicon semiconductor layer, a first gate layer, and a second gate layer in an exemplary embodiment of the present disclosure.

[0049] FIG6 is a schematic diagram of a metal oxide semiconductor layer in an exemplary embodiment of the present disclosure.

[0050] FIG. 7 is a schematic diagram of a third gate layer in an exemplary embodiment of the present disclosure.

[0051] FIG8-1 is a schematic diagram of a first source / drain metal layer in an exemplary embodiment of the present disclosure.

[0052] FIG8-2 is a schematic diagram of a stack of a low-temperature polysilicon semiconductor layer, a first gate layer, and a first source-drain metal layer in an exemplary embodiment of the present disclosure.

[0053] FIG9 is a schematic diagram of a second source / drain metal layer in an exemplary embodiment of the present disclosure.

[0054] FIG10 is a schematic diagram of a third source / drain metal layer in an exemplary embodiment of the present disclosure.

[0055] FIG11 is a schematic diagram of a metal light-shielding layer in an exemplary embodiment of the present disclosure.

[0056] FIG12 is a schematic diagram of initialization wiring in the row direction and initialization wiring in the column direction in an exemplary implementation of the present disclosure.

[0057] FIG13 is a schematic diagram illustrating the relative positions of the metal light-shielding layer and the first bridge portion in an exemplary embodiment of the present disclosure.

[0058] FIG14 is a schematic diagram of a switching structure simultaneously applying a second scanning signal to data writing transistors in two adjacent circuit areas along a row direction in an exemplary embodiment of the present disclosure.

[0059] FIG15 is a schematic diagram showing the layout of initialization routing lines and initialization column routing lines in an exemplary embodiment of the present disclosure.

[0060] FIG16 is a schematic diagram showing a first initialization column trace connected to a first initialization trace through a via (black dots represent via connection locations) in an exemplary embodiment of the present disclosure.

[0061] FIG17 is a schematic diagram showing a second initialization column wiring and a second initialization wiring connected through vias (black dots represent via connection locations) in an exemplary embodiment of the present disclosure.

[0062] FIG18 is a schematic diagram showing a third initialization column wiring and a third initialization wiring connected through vias (black dots represent via connection locations) in an exemplary embodiment of the present disclosure.

[0063] FIG19 is a schematic diagram of the arrangement of pixel electrodes in an exemplary embodiment of the present disclosure.

[0064] Explanation of the accompanying symbols: PA, circuit area; PA1, first sub-circuit area; PA2, second sub-circuit area; MA1, first bridge portion; MA2, second bridge portion; MA3, third bridge portion; MA4, fourth bridge portion; MA5, fifth bridge portion; MA6, sixth bridge portion; MA7, seventh bridge portion; MA8, eighth bridge portion; MA9, ninth bridge portion; MB1, first metal portion; MB2, second metal portion; MB3, third metal portion; MB4, fourth metal portion; MA10, sixteenth bridge portion; MA11, seventeenth bridge portion; MC1, first conductive portion; MC2, second conductive portion; MC3, third conductive portion; SWL1, first backup line; SWL2, second backup line; SBT, substrate; DRL, drive layer; TL, transistor layer; PSCL, low-temperature polysilicon semiconductor Body layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; GT3, third gate layer; ILD, interlayer dielectric layer; SD1, first source-drain metal layer; SD2, second source-drain metal layer; SD3, third source-drain metal layer; PLN1, first planarization layer; PLN2, second planarization layer; OSCL, metal oxide semiconductor layer; PLN3, third planarization layer; PDL, pixel definition layer; COML, common electrode layer; EL, light-emitting functional layer; PEL, pixel electrode layer; PIXL, pixel layer; TFE, thin film encapsulation layer; T 1. First reset transistor; T2. Threshold compensation transistor; T3. Driving transistor; T4. Data writing transistor; T5. First light emission control transistor; T6. Second light emission control transistor; T7. Electrode reset transistor; T8. Second reset transistor; CST. Storage capacitor; CP1. First electrode; CP2. Second electrode; Vinit1. First initialization voltage; Vinit2. Second initialization voltage; Vinit3. Third initialization voltage; RP. First reset control signal; RH. Second reset control signal; GN. First scan signal; GP. Second scan signal; VDD. Power supply voltage; VSS. Reference voltage; EM. Light emission signal; Data. Data signal T1A, channel region of the first reset transistor; T2A, threshold compensation transistor; T3A, channel region of the drive transistor; T4A, channel region of the data write transistor; T5A, channel region of the first light emission control transistor; T6A, channel region of the second light emission control transistor; T7A, channel region of the electrode reset transistor; T8A, channel region of the second reset transistor; HB1, first upper via region; HB2, second upper via region; HB3, third upper via region; HB4, fourth upper via region; HB5, fifth upper via region; HB6, sixth upper via region; HB7, seventh upper via region; HB8, eighth upper via region; HB9, ninth upper via region; HB10, tenth upper via region;HB11, the eleventh upper via area; HB12, the twelfth upper via area; HB13, the thirteenth upper via area; HB14, the fourteenth upper via area; HB15, the fifteenth upper via area; HB16, the sixteenth upper via area; HB17, the seventeenth upper via area; HB18, the eighteenth upper via area; HB19, the nineteenth upper via area; HB20, the twentieth upper via area; HB21, the twenty-first upper via area; HB22, the twenty-second upper via area; HB23, the twenty-third upper via area; HB24, the twenty-fourth upper via area; HB25, the twenty-fifth upper via area; HB26, the twenty-sixth upper via area; HA1, the first lower via area; HA2, the second lower via area; HA3, the third lower via area; HA4, The fourth lower via area; HA5, the fifth lower via area; HA6, the sixth lower via area; HA7, the seventh lower via area; HA8, the eighth lower via area; HA9, the ninth lower via area; HA10, the tenth lower via area; HA11, the eleventh lower via area; HA12, the twelfth lower via area; HA13, the thirteenth lower via area; HA14, the fourteenth lower via area; HA15, the fifteenth lower via area; HA16, the sixteenth lower via area; HA17, the seventeenth lower via area; HA18, the eighteenth lower via area; HA19, the nineteenth lower via area; HA20, the twentieth lower via area; HA21, the twenty-first lower via area; HA22, the twenty-second lower via area; HA23, the twenty-third lower via area; HA24 , the 24th lower via area; HA25, the 25th lower via area; HA26, the 26th lower via area; DH, row direction; DV, column direction; GA1, transfer structure; GB1, jump structure; GNLA, the first upper scan signal line; GNLB, the first lower scan signal line; GPL, the second scan signal line; EML, the light emitting signal line; RPL, the first reset control signal line; RHL, the second reset control signal line; BSM, the metal shielding layer; BL1, the first partition line; BL2, the second partition line; LSP, the partition block body; GL, the scan signal line; DL, the data signal line; HL, the initialization line; HL1, the first initial line; HL2, the second initial line; H L3, third initialization line; VL, initialization column line; VLX, main section of initialization column line; VLX1, main section of first initialization column line; VLX2, main section of second initialization column line; VLX3, main section of third initialization column line; VLY, bridge section of initialization column line; VLY1, bridge section of first initialization column line; VLY2, bridge section of second initialization column line; VLY3, bridge section of third initialization column line; VL1, first initialization column line; VL2, second initialization column line; VL3, third initialization column line; N1, first node; N2, second node; N3, third node; N4, fourth node; N5, fifth node; N6, sixth node; N7, seventh node;N8, eighth node; N9, ninth node; VPA1, first circuit area column; VPA2, second circuit area column; VPA3, third circuit area column; HPA, circuit area row; VPA, circuit area column; X1, first transfer via; X2, second transfer via. DETAILED DESCRIPTION

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0066] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0067] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0068] Structural layer A is located on the side of structural layer B facing away from the base substrate. This means that structural layer A is formed on the side of structural layer B facing away from the base substrate. When structural layer B is a patterned structure, part of structural layer A may also be located at the same physical height as structural layer B or lower than the physical height of structural layer B, with the base substrate serving as a height reference.

[0069] A transistor refers to an element comprising at least three terminals: a gate, a second pole, and a first pole. The transistor has a channel region between the second pole (drain electrode terminal, drain region, or drain electrode) and the first pole (source electrode terminal, source region, or source electrode), and current can flow through the second pole, the channel region, and the first pole. The channel region refers to the region through which current mainly flows. In the embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "first pole" and the "second pole" are sometimes interchanged, that is, the "first pole" and the "second pole" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "first pole" and the "second pole" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.

[0070] With the development of display panel technology, higher requirements have been placed on the display quality of display panels. In display panels, display uniformity is an important factor in measuring the quality of the display panel. The pixel driving circuit has a data write transistor, which is used to receive a data voltage and write the data voltage into the gate of the driving transistor. The display panel is provided with a data signal line extending along the row direction, and the data signal line is used to load a second scanning signal to the gate of the data write transistor; the data write transistor is turned on in response to the data signal line. The conduction time of the data write transistor determines the charging time of the pixel driving circuit, and thus determines the charging rate of the pixel driving circuit. In the related art, the data signal line is provided in the gate layer, which will result in a relatively large resistance of the data signal line and a large voltage drop across the data signal line; the conduction time of the data write transistor at different positions along the row direction is different, which may result in different charging rates of the pixel driving circuit and affect display uniformity.

[0071] Based on this, referring to Figures 1-1, 2, 8-1, 10 and 14, an embodiment of the present disclosure provides a display panel, which includes a base substrate SBT, a driving layer DRL and a pixel layer PIXL stacked in sequence; the driving layer DRL is provided with a pixel driving circuit for driving the sub-pixel PIX (see Figure 1-1), and is provided with a scanning signal line GL extending along the row direction DH (see Figure 8-1) and a data signal line DL extending along the column direction DV (see Figure 10); the pixel driving circuit includes a data write transistor T4, a first electrode of the data write transistor T4 is electrically connected to the data signal line DL, and a gate of the data write transistor T4 is electrically connected to the scanning signal line GL; the driving layer DRL includes a transistor layer TL and a first source-drain metal layer SD1 stacked in sequence on the base substrate SBT; the gate of the data write transistor T4 is provided in the transistor layer TL, and the scanning signal line GL is provided in the first source-drain metal layer SD1; the gate of the data write transistor T4 is electrically connected to the scanning signal line GL through a via.

[0072] In the disclosed embodiment, a scan signal line GL is disposed on the first source / drain metal layer SD1, and the gate voltage is applied to the gate of the data write transistor T4 via the scan signal line GL. Compared to the various metal layers in the transistor layer TL, the first source / drain metal layer SD1 has better conductivity. Compared to disposing the scan signal line GL in a metal layer within the transistor layer TL, disposing the scan signal line GL in the first source / drain metal layer SD1 can reduce the gate voltage drop, improve the uniformity of the gate voltage across the scan signal line GL, and thus improve the uniformity of the conduction time of the data write transistors T4 connected to different locations on the scan signal line GL, thereby improving display uniformity.

[0073] In one embodiment of the present disclosure, the sheet resistance of the metal layer in the transistor layer TL is greater than the sheet resistance of the first source / drain metal layer SD1. For example, the sheet resistance of the metal layer in the transistor layer TL is at least 1.5 times the sheet resistance of the first source / drain metal layer SD1. Exemplarily, the sheet resistance of the metal layer in the transistor layer TL is 1.5 times, 2.0 times, 2.5 times, 3.0 times, or 3.5 times the sheet resistance of the first source / drain metal layer SD1.

[0074] In one embodiment of the present disclosure, at least one metal layer in the transistor layer TL is made of molybdenum, for example, all metal layers in the transistor layer TL are made of molybdenum. Of course, at least one metal layer in the transistor layer TL may be made of a composite material or a multilayer metal.

[0075] In one embodiment of the present disclosure, the first source / drain metal layer SD1 includes multiple metal layers, for example, a bottom protective metal layer, a main metal layer, and a top protective metal layer stacked in sequence. The main metal layer is made of a highly conductive material, such as aluminum or copper. The bottom protective metal layer and the top protective metal layer can protect the main metal layer from corrosion that could affect other film layers, or improve adhesion between the main metal layer and other film layers. For example, the bottom protective metal layer and the top protective metal layer can be made of titanium or molybdenum.

[0076] In one example, the first source / drain metal layer SD1 includes a titanium metal layer / an aluminum metal layer / a titanium metal layer stacked in sequence.

[0077] In another example, the first source / drain metal layer SD1 includes a molybdenum metal layer / a copper metal layer / a molybdenum metal layer stacked in sequence.

[0078] Figures 1-2 illustrate equivalent circuit diagrams of a pixel driving circuit according to an embodiment of the present disclosure. It is understood that the pixel driving circuit according to an embodiment of the present disclosure may also be a pixel driving circuit with other structures. When the structure of the pixel driving circuit changes, the structures of the various film layers according to the embodiment of the present disclosure may also be adaptively adjusted.

[0079] In the example of Figures 1-2, the pixel driving circuit may include a first reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, an electrode reset transistor T7, a second reset transistor T8, and a storage capacitor Cst. The threshold compensation transistor T2 is an N-type thin film transistor, such as a metal oxide thin film transistor; the remaining thin film transistors are P-type thin film transistors, such as low-temperature polysilicon thin film transistors.

[0080] A first electrode of the first reset transistor T1 is connected to the eighth node N8. The first electrode of the first reset transistor T1 is used to apply a first initialization voltage Vinit1. The gate of the first reset transistor T1 is used to apply a first reset control signal RP. A second electrode of the first reset transistor T1 is connected to the third node N3. The first reset transistor T1 is used to apply the first initialization voltage Vinit1 to the third node N3 in response to the first reset control signal RP.

[0081] A first electrode of the threshold compensation transistor T2 is electrically connected to the third node N3, a second electrode of the threshold compensation transistor T2 is electrically connected to the first node N1, and a gate of the threshold compensation transistor T2 is configured to apply the first scan signal GN. The threshold compensation transistor T2 is configured to be turned on in response to the first scan signal GN and write the first initialization voltage Vinit1 applied to the first electrode of the first reset transistor T1 into the first node N1.

[0082] The first electrode of the driving transistor T3 is connected to the second node N2, the second electrode of the driving transistor T3 is connected to the third node N3, and the gate of the driving transistor T3 is connected to the first node N1. The driving transistor T3 is configured to output a driving current under the control of the voltage on the N1 node.

[0083] A first electrode of the data write transistor T4 is connected to the seventh node N7. The first electrode of the data write transistor T4 is used to load the data signal Data. A second electrode of the data write transistor T4 is electrically connected to the second node N2. A gate of the data write transistor T4 is used to load the second scan signal GP. The data write transistor T4 is used to load the data signal Data to the second node N2 in response to the second scan signal GP.

[0084] The first electrode of the first light-emitting control transistor T5 is connected to the fifth node N5, the first electrode of the first light-emitting control transistor T5 is used to load the power supply voltage VDD, the second electrode of the first light-emitting control transistor T5 is connected to the second node N2, and the gate of the first light-emitting control transistor T5 is used to load the light-emitting signal EM.

[0085] A first electrode of the second emission control transistor T6 is connected to the third node N3, a second electrode of the second emission control transistor T6 is connected to the fourth node N4, and a gate of the second emission control transistor T6 is used to apply the emission signal EM. The first emission control transistor T5 and the second emission control transistor T6 are used to be turned on in response to the emission signal EM.

[0086] A first electrode of the electrode reset transistor T7 is connected to the ninth node N9. The first electrode of the electrode reset transistor T7 is used to apply the second initialization voltage Vinit2. The gate of the electrode reset transistor T7 is used to apply the second reset control signal RH. A second electrode of the electrode reset transistor T7 is connected to the fourth node N4. The electrode reset transistor T7 is used to apply the second initialization voltage Vinit2 to the fourth node N4 in response to the second reset control signal RH.

[0087] A first electrode of the second reset transistor T8 is connected to the sixth node N6. The first electrode of the second reset transistor T8 is used to apply the third initialization voltage Vinit3. The gate of the second reset transistor T8 is used to apply the second reset control signal RH. The second electrode of the second reset transistor T8 is connected to the second node N2. The second reset transistor T8 is used to apply the third initialization voltage Vinit3 to the second node N2 in response to the second reset control signal RH.

[0088] The pixel electrode PE of the light-emitting element (not specifically shown in the drawings of this specification) is electrically connected to the pixel driving circuit, the common electrode is used to load the reference voltage VSS, one end of the storage capacitor Cst is connected to the first node N1, and the other end is connected to the fifth node N5.

[0089] Optionally, the base substrate SBT may be an inorganic material base substrate SBT or an organic material base substrate SBT; of course, it may also be a composite substrate formed by laminating an inorganic material base substrate SBT and an organic material base substrate SBT. For example, in some embodiments of the present disclosure, the base substrate SBT may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass.

[0090] In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0091] Optionally, referring to Figures 1-2 and 2, in the driving layer DRL, any pixel driving circuit may include a thin film transistor and a storage capacitor Cst (not shown in Figure 2 of the present application). Furthermore, the thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0092] It is understandable that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0093] Optionally, referring to FIG2 , the driving layer DRL may include a semiconductor layer (e.g., a low-temperature polysilicon semiconductor layer PSCL and a metal oxide semiconductor layer OSCL) stacked between the substrate SBT and the pixel layer PIXL, a gate insulating layer (e.g., a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3), a gate layer (e.g., a first gate layer GT1, a second gate layer GT2, and a third gate layer GT3), an interlayer dielectric layer ILD, a source-drain metal layer (e.g., a first source-drain metal layer SD1, a second source-drain metal layer SD2, and a third source-drain metal layer SD3), a planarization layer (e.g., a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3), etc. Each thin film transistor and storage capacitor Cst may be formed by film layers such as a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer ILD, a source-drain metal layer, and the like; of course, other film layers may also be used. The positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. Furthermore, the semiconductor layer can be used to form the active layer of the transistor (including the first electrode, the second electrode and the channel region of the transistor), and can also be formed into partial wiring or conductive structure by conductorization when necessary. The first source-drain metal layer SD1 can be used to form the scanning signal line GL; the gate layer can be used to form one or more gate layer wirings such as the reset control wiring and the light emitting control wiring, and can also be used to form the gate of the transistor, and can also be used to form part or all of the electrode plates of the storage capacitor Cst. The source-drain metal layer can be used to form source-drain metal layer wirings such as data wiring and drive power supply voltage wiring, and can also be used to form part of the electrode plates of the storage capacitor Cst.

[0094] Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a metal light shielding layer BSM located between the semiconductor layer and the substrate SBT. As needed, any of the above-mentioned semiconductor layers, gate layers, source / drain metal layers and other film layers may also be multi-layered. For example, the driving layer DRL may include two different semiconductor layers, or two or three source / drain metal layers, or two or three gate layers. Accordingly, the insulating film layers in the driving layer DRL (such as a gate insulating layer, an interlayer dielectric layer ILD, a planarization layer, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0095] Optionally, referring to FIG2 , the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EL, and a common electrode layer COML stacked in sequence. The pixel electrode layer PEL has a plurality of pixel electrodes PE in the display area of ​​the display panel. The pixel definition layer PDL has a plurality of through pixel openings corresponding to the plurality of pixel electrodes, and any one of the pixel openings exposes at least a portion of the corresponding pixel electrode PE. For example, the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of ​​the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode (the area directly connected to the light-emitting functional layer EL), thereby defining the light-emitting region and light-emitting area of ​​the sub-pixel. The common electrode layer COML serves as a common electrode and covers the light-emitting functional layer EL. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EL, so that the light-emitting functional layer EL emits light. The portion of the light-emitting functional layer EL located between the pixel electrode and the common electrode layer COML can serve as a light-emitting functional unit of the sub-pixel. The pixel electrode PE, the common electrode layer COML, and the light-emitting functional unit form a light-emitting element serving as a sub-pixel. One of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel, and the other serves as a cathode of the sub-pixel.

[0096] In this example, the display panel is an OLED (organic light-emitting diode) display panel. The light-emitting functional layer EL may include an organic light-emitting layer, and may include one or more of a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer. Furthermore, the organic light-emitting layer may include a light-emitting layer host material and a light-emitting layer guest material. The light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material.

[0097] It is understandable that the display panel may also be other types of display panels, for example, a QLED display panel, a QD-OLED display panel or other types of display panels.

[0098] Referring to Figure 2, the display panel may further include a thin film encapsulation layer TFE, which may be provided on the surface of the pixel layer PIXL away from the substrate SBT, and may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing aging of the material in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. Among them, the edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer.

[0099] For example, the thin film encapsulation layer (TFE) includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, which are sequentially stacked on the side of the pixel layer (PIXL) away from the substrate (SBT). Of course, in other embodiments of the present disclosure, the display panel may not include a thin film encapsulation layer (TFE), but may use other methods to encapsulate and protect the pixel layer.

[0100] In one embodiment, referring to FIG2 , the transistor layer TL includes a low-temperature polycrystalline silicon semiconductor layer PSCL, a first gate insulating layer GI1, and a first gate layer GT1, which are sequentially stacked on a substrate SBT. Referring to FIG3 , FIG4-1 , and FIG4-2 , the channel region T4A of the data write transistor is located in the low-temperature polycrystalline silicon semiconductor layer PSCL. The first gate layer GT1 is provided with a transfer structure GA1 (see FIG4-1 ), which overlaps with the channel region T4A of the data write transistor (see FIG4-2 ). In this example, the gate of the data write transistor T4 is located in the transfer structure GA1. Specifically, the portion of the transfer structure GA1 that overlaps with the channel region T4A of the data write transistor serves as the gate of the data write transistor T4 to control whether the data write transistor T4 is turned on or off. Referring to FIG8-1 and FIG8-2 , a scan signal line GL is provided in the first source / drain metal layer SD1 and extends along DH. The transfer structure GA1 is electrically connected to the scan signal line GL through a via. In this embodiment, the second scanning signal GP is loaded onto the scanning signal line GL, and the scanning signal line GL loads the second scanning signal GP onto the switching structure GA1 through at least one via hole, thereby controlling the data writing transistor T4.

[0101] In one example, the transfer structure GA1 is electrically connected to the scan signal line GL through multiple vias, for example, two vias (see FIG. 14 , where the two vias include a first transfer hole X1 and a second transfer hole X2). This helps reduce the contact resistance on the transfer structure GA1, further uniformizes the second scan signal GP on different transfer structures GA1, and helps reduce the delay when the data write transistor T4 is turned on, thereby improving the charging time.

[0102] In one example, referring to Figures 3, 4-1, and 14, the transfer structure GA1 extends along the row direction DH and overlaps with the channel region T4A of two adjacent data write transistors in the same row (the specific state of the overlap between the transfer structure GA1 and the channel region T4A of the data write transistor is not specifically shown in this figure). The second scan signal GP loaded on the first source-drain metal layer SD1 is loaded onto the transfer structure GA1 via the scan signal line GL. The transfer structure GA1 simultaneously loads the second scan signal GP to the two adjacent data write transistors T4 in the same row, so that the second scan signals GP loaded on adjacent data write transistors T4 are identical and tend to be synchronized, thereby achieving relatively uniform second scan signals GP loaded on the data write transistors T4 on the display panel, thereby achieving nearly uniform switching levels of the data write transistors T4 on the display panel, which helps to improve the uniformity of the display panel.

[0103] In one embodiment of the present disclosure, referring to FIG12 , the display panel is further provided with an initialization line HL extending in the row direction and an initialization column line VL extending in the column direction. The initialization line HL and the initialization column line VL are electrically connected at the intersection through a via (e.g., the position indicated by the black dot in FIG12 ). The initialization line HL and the initialization column line VL are used to load the initialization voltage. By extending the initialization line HL in the row direction DH and the initialization column line VL in the column direction DV, and connecting the initialization line HL and the initialization column line VL at the intersection through a via, a grid-like distribution of the initialization voltage can be achieved, which helps to reduce the difference in the initialization voltage in the display panel, thereby improving the display uniformity of the display panel.

[0104] In some embodiments of the present disclosure, referring to Figures 2 and 12 , the drive layer DRL includes a transistor layer TL and a first source / drain metal layer SD1; an initialization trace HL is located in the transistor layer TL; and an initialization column trace VL includes a main segment VLX of the initialization column trace located in the first source / drain metal layer SD1 and a bridge segment VLY of the initialization column trace located in the transistor layer TL. The main segment VLX of the initialization column trace is electrically connected to the initialization trace HL through a via; the main segments VLX of two adjacent initialization column traces along the column direction are connected by the bridge segment VLY of the initialization column trace.

[0105] In the embodiment of the present disclosure, the scanning signal line GL is arranged in the first source-drain metal layer SD1 (see Figure 8-1), which will isolate the portion of the initialization column trace VL located in the first source-drain metal layer SD1 and cause the initialization column trace VL to form a discontinuous main segment VLX of the initialization column trace in the first source-drain metal layer SD1; in this embodiment, a bridge segment VLY of the initialization column trace is set in the transistor layer TL (see Figure 5-2), and the bridge segment VLY of the initialization column trace crosses the scanning signal line GL and electrically connects the main segments VLX of two adjacent initialization column traces, thereby ensuring the electrical continuity of the initialization column trace VL.

[0106] Of course, in other embodiments of the present disclosure, the bridge segment VLY of the initialization column trace may also be disposed in other film layers, such as the second source / drain metal layer SD2, the third source / drain metal layer SD3, the low-temperature polysilicon semiconductor layer PSCL (where the bridge segment VLY of the initialization column trace is conductive), etc., as long as the bridge segment VLY of the initialization column trace is not located in the first source / drain metal layer SD1 and does not overlap with the scan signal line GL. In this way, the scan signal line GL can be ensured to extend continuously on the first source / drain metal layer SD1, ensuring that the scan signal line GL has low impedance.

[0107] In some embodiments of the present disclosure, referring to FIG. 12 and FIG. 15 , the initialization column lines VL include a first initial column line VL1 , a second initial column line VL2 , and a third initial column line VL3 ; and the initialization running lines HL include a first initial running line HL1 , a second initial running line HL2 , and a third initial running line HL3 .

[0108] 16 , the first initial column wiring VL1 is connected to the first initial wiring HL1 through a via and is used to load the first initialization voltage Vinit1; this can achieve a grid distribution of the first initialization voltage Vinit1, which helps to reduce the difference in the first initialization voltage Vinit1 in the display panel and improve the display uniformity of the display panel.

[0109] Referring to Figure 17, the second initial column line VL2 is connected to the second initial line HL2 through a via and is used to load the second initialization voltage Vinit2; this can achieve a grid distribution of the second initialization voltage Vinit2, which helps to reduce the difference in the second initialization voltage Vinit2 in the display panel and improve the display uniformity of the display panel.

[0110] As shown in Figure 18 , the third initialization column line VL3 is connected to the third initialization line HL3 through a via and is used to apply the third initialization voltage Vinit3. This allows for a grid-like distribution of the third initialization voltage Vinit3, helping to reduce variations in the third initialization voltage Vinit3 across the display panel and improve display uniformity.

[0111] In some embodiments of the present disclosure, referring to FIG. 12 and FIG. 15 , a step-by-step PA of a display panel array is shown. The circuit area PA includes a first sub-circuit area PA1 and a second sub-circuit area PA2 adjacently arranged along the row direction DH. Thin-film transistors of a pixel driving circuit are respectively arranged in the first sub-circuit area PA1 and the second sub-circuit area PA2. A circuit area row HPA includes circuit areas PA arranged in the same row. Within at least one circuit area row HPA, for example, within each circuit area row HPA, a first initial running line HL1, a second initial running line HL2, and a third initial running line HL3 are arranged. A circuit area column VPA includes circuit areas PA arranged in the same column. The circuit area column VPA includes a first circuit area column VPA1, a second circuit area column VPA2, and a third circuit area column VPA3 arranged periodically; the first circuit area column VPA1 includes a first initial column trace VL1; the second circuit area column VPA2 includes a second initial column trace VL2; and the third circuit area column VPA3 includes a third initial column trace VL3.

[0112] In this embodiment, a first initial running line HL1, a second initial running line HL2 and a third initial running line HL3 are provided in each circuit area row HPA, which can ensure that the first initialization voltage Vinit1, the second initialization voltage Vinit2 and the third initialization voltage Vinit3 maintain a large distribution density in the column direction DV, thereby facilitating the improvement of the uniformity of the first initialization voltage Vinit1, the second initialization voltage Vinit2 and the third initialization voltage Vinit3, and facilitating the loading of the first initialization voltage Vinit1, the second initialization voltage Vinit2 and the third initialization voltage Vinit3 to the pixel driving circuit respectively.

[0113] In this embodiment, each circuit area column VPA is provided with one of the first initialization column trace VL1, the second initialization column trace VL2, and the third initialization column trace VL3. This prevents the provision of too many initialization column traces VL, which would otherwise increase the width of the circuit area PA (the dimension of the circuit area PA in the row direction DH) and reduce resolution. The periodic arrangement of the first circuit area column VPA1, the second circuit area column VPA2, and the third circuit area column VPA3 ensures a relatively uniform distribution grid for the first initialization voltage Vinit1, the second initialization voltage Vinit2, and the third initialization voltage Vinit3. It also allows the distribution grids of the three signals, namely, the first initialization voltage Vinit1, the second initialization voltage Vinit2, and the third initialization voltage Vinit3, to be close to each other, thereby improving display uniformity.

[0114] In some embodiments of the present disclosure, in the circuit area column VPA, the initialization column trace VL extends along the boundary line between the first sub-circuit area PA1 and the second sub-circuit area PA2. That is, a portion of the initialization column trace VL is located in the first sub-circuit area PA1 and the other portion is located in the second sub-circuit area PA2. Accordingly, the initialization column trace VL is connected to the initialization trace HL through a via, and the initialization column trace VL can also be located on the boundary line between the first sub-circuit area PA1 and the second sub-circuit area PA2. In this embodiment, the initialization column trace VL is provided at the edge of the first sub-circuit area PA1 and the second sub-circuit area PA2 rather than in the middle of the first sub-circuit area PA1 and the second sub-circuit area PA2, which can reduce the impact of the setting of the initialization column trace VL on other structures of the pixel driving circuit, which is conducive to reducing the design cost of the display panel.

[0115] In some embodiments of the present disclosure, referring to Figures 2 and 12 , the transistor layer TL includes a low-temperature polysilicon semiconductor layer PSCL, a first gate layer GT1, a second gate layer GT2, a metal oxide semiconductor layer OSCL, and a third gate layer GT3, which are stacked in sequence. The bridge segment VLY of the initialization column trace is located in one of the first gate layer GT1, the second gate layer GT2, and the third gate layer GT3, while the main segment VLX of the initialization trace is located in at least one of the other two layers.

[0116] For example, referring to Figure 5-1 , the bridge segment VLY of the initialization column trace is located on the second gate layer GT2, and referring to Figure 7 , the initialization trace HL is located on the third gate layer GT3. Referring to Figure 8-1 , the main segment VLX of the initialization column trace is located on the first source / drain metal layer SD1. The main segments VLX of two adjacent initialization column traces are electrically connected via the bridge segment VLY of the initialization column trace. The main segment VLX of the initialization column trace is also electrically connected to the initialization trace HL, thereby applying the initialization voltage to the main segment VLX of the initialization column trace, the bridge segment VLY of the initialization column trace, and the initialization trace HL.

[0117] For another example, in one embodiment, the bridge segment VLY of the initialization column trace can be set on the first gate layer GT1, the main segment VLX of the initialization column trace is set on the first source and drain metal layer SD1, and the initialization trace HL is set on the third gate layer GT3.

[0118] For another example, in one embodiment, the bridge segment VLY of the initialization column trace can be set on the first gate layer GT1, the main segment VLX of the initialization column trace is set on the first source and drain metal layer SD1, and the initialization trace HL is set on the second gate layer GT2.

[0119] For another example, in one embodiment, the bridge segment VLY of the initialization column trace can be set on the third gate layer GT3, the main segment VLX of the initialization column trace is set on the first source and drain metal layer SD1, and the initialization trace HL is set on the second gate layer GT2.

[0120] In the above example, the initialization column line VL includes VLX located in the first source / drain metal layer SD1 , and the initialization column line VL needs to be provided with a bridge segment VLY to avoid the scanning signal line GL, so a jumper design is adopted.

[0121] It is understood that in some other embodiments of the present disclosure, the scan signal line GL may adopt a jumper design, and the initialization column trace VL may be disposed in the first source / drain metal layer SD1. For example, the initialization column trace VL is located in the first source / drain metal layer SD1, extends along the column direction DV, and penetrates the circuit area column VPA. The scan signal line GL includes a main segment of the initialization trace located in the first source / drain metal layer SD1 and a main segment of the initialization trace located in TL. The main segment of the initialization trace is electrically connected to the first bridge portion MA1 via a via, and the bridge segment of the initialization trace overlaps the initialization column trace VL. The main segments of two adjacent initialization traces are electrically connected via the bridge segment of the initialization trace.

[0122] It can also be understood that in some other embodiments of the present disclosure, the initialization column line VL can also be set in other film layers other than the first source and drain metal layer SD1, so that the scanning signal line GL and the initialization column line VL can overlap with each other without short circuiting.

[0123] When the initialization voltage is loaded on the main segment VLX of the initialization running line, the main segment VLX of the initialization running line located on the third gate layer GT3 loads the initialization voltage to the bridge segment VLY of the initialization column line located on the second gate layer GT2, and the other end of the bridge segment VLY of the initialization column line located on the second gate layer GT2 loads the initialization voltage to the main segment VLX of another initialization column line adjacent in the column direction on the third gate layer GT3, thereby realizing the jumper design of the initialization column line VL.

[0124] For example, the drive layer DRL includes a transistor layer TL, a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3, which are stacked in sequence. The initialization line HL is located in the transistor layer TL. The initialization column line VL is located in the second source / drain metal layer SD2. A transition portion for the initialization column line is provided on the first source / drain metal layer SD1 (not specifically shown in the drawings of this specification). The initialization column line VL is electrically connected via the transition portion of the initialization column line. The transition portion VLA of the initialization column line is electrically connected to the corresponding initialization line HL via a via. In this example, the scan signal line GL is located in the first source / drain metal layer SD1, and the initialization column line VL is located in the second source / drain metal layer SD2. The two layers are located in different metal layers. Therefore, the initialization column line VL does not need to jump to avoid the scan signal line GL.

[0125] In some embodiments of the present disclosure, referring to Figures 2, 11, and 13, the pixel driving circuit further includes a driving transistor T3; the first source-drain metal layer SD1 includes a first bridge portion MA1, and the first bridge portion MA1 is connected to the gate of the driving transistor T3 through a via; the display panel further includes a metal shading layer BSM; the metal shading layer BSM is arranged on a side of the base substrate SBT close to the driving layer DRL; the metal shading layer BSM has a first isolation trace BL1 arranged along the column direction DV; the orthographic projection of the first isolation trace BL1 on the base substrate SBT is located between the first electrode of the data writing transistor T4 and the orthographic projection of the first bridge portion MA1 on the base substrate SBT.

[0126] In this embodiment, the first isolation line BL1 can electromagnetically shield the first bridge portion MA1 and the first electrode of the data write transistor T4, reduce the crosstalk of the signal jump of the first electrode of the data write transistor T4 on the first bridge portion MA1, and improve the voltage stability of the first bridge portion MA1.

[0127] In an example, a power supply voltage VDD may be applied to the metal light shielding layer BSM to further stabilize the voltage of the first bridge portion MA1 .

[0128] In another embodiment of the present disclosure, the first source-drain metal layer SD1 includes a first bridge portion MA1, which is connected to the gate of the driving transistor T3 through a via; the display panel also includes a metal shading layer BSM; the metal shading layer BSM is arranged on the side of the base substrate SBT close to the driving layer DRL; the metal shading layer BSM has a first partition trace BL1 arranged along the column direction DV; the orthographic projection of the first bridge portion MA1 on the base substrate SBT is located within the orthographic projection of the first partition trace BL1 on the base substrate SBT.

[0129] In this embodiment, the first isolation trace BL1 can provide electromagnetic shielding between the first bridge MA1 and the first electrode of the data write transistor T4, reducing crosstalk caused by signal transitions at the first electrode of the data write transistor T4 on the first bridge MA1 and improving the voltage stability of the first bridge MA1. The power supply voltage VDD can be applied to the metal light shielding layer BSM to further stabilize the voltage of MA1.

[0130] In one embodiment of the present disclosure, referring to Figures 2 and 11 , the metal light shielding layer (BSM) may further include a second barrier trace BL2 and a barrier block body LSP arranged along the row direction DH. The second barrier trace BL2 and the barrier block body LSP are electrically connected. Two adjacent LSPs in the same column are electrically connected via SL1, and two adjacent LSPs in the same row are electrically connected via SL2. This allows the metal light shielding layer (BSM) to be gridded, thereby shielding against external electromagnetic interference.

[0131] Optionally, the orthographic projection of the channel region of the driving transistor T3 on the metal light shielding layer BSM is located within the partition block body LSP. Therefore, the partition block body LSP can shield the external light from shining on the channel region of the driving transistor T3, preventing the driving transistor T3 from being affected by light and causing performance changes.

[0132] In some embodiments of the present disclosure, the second source-drain metal layer SD2 further includes a second metal portion MB2. This second metal portion MB2 is electrically connected to the power supply voltage trace VDDL located in the third source-drain metal layer SD3. The second metal portion MB2 covers the first bridge portion MA1. This covering of the first bridge portion MA1 provides electromagnetic shielding for the first bridge portion MA1, thereby improving the voltage stability of the first bridge portion MA1.

[0133] In some embodiments of the present disclosure, the first isolation trace BL1 can be loaded with a power supply voltage VDD.

[0134] As follows, an example of an embodiment of the present disclosure is exemplarily introduced by taking the film layer structure of the first exemplary pixel driving circuit as an example.

[0135] Figure 3 is a schematic diagram of the structure of a low-temperature polycrystalline silicon semiconductor layer PSCL in one example. Referring to Figure 3 , the low-temperature polycrystalline silicon semiconductor layer PSCL includes a first reset transistor T1, a driver transistor T3, a data write transistor T4, a first emission control transistor T5, a second emission control transistor T6, an electrode reset transistor T7, and a first electrode, second electrode, and channel region of the second reset transistor T8. The channel region T5A of the first emission control transistor and the channel region T6A of the second emission control transistor are arranged along the row direction DH, while the channel region T4A of the data write transistor and the first emission control transistor T5 are arranged along the column direction DV. Along the row direction DH, the channel region T3A of the driver transistor is located between the channel region T5A of the first emission control transistor and the channel region T6A of the second emission control transistor. Along the column direction DV, the channel region T7A of the electrode reset transistor and the channel region T5A of the first emission control transistor are located on either side of the channel region T3A of the driver transistor. The second electrode of the data write transistor T4, the second electrode of the first light emission control transistor T5, and the first electrode of the drive transistor T3 are connected to each other, the second electrode of the drive transistor T3 and the first electrode of the second light emission control transistor T6 are electrically connected, and the second electrode of the electrode reset transistor T7 and the second electrode of the second light emission control transistor T6 are electrically connected. In two adjacent rows of drive circuits, the channel region T7A of the electrode reset transistor of the upper row drive circuit is adjacent to the channel region T4A of the data write transistor of the lower row drive circuit, and the second electrode of the second reset transistor T8 is electrically connected to the second electrode of the first light emission control transistor T5.

[0136] The low-temperature polycrystalline silicon semiconductor layer PSCL is provided with a thirteenth lower via area HA13, a seventh lower via area HA7, a twelfth lower via area HA12, a third lower via area HA3, a ninth lower via area HA9, a fourth lower via area HA4, an eleventh lower via area HA11, an eighth lower via area HA8, a fifth lower via area HA5, and a fourteenth lower via area HA14; the thirteenth lower via area HA13 is located at the first electrode of the first reset transistor T1; the seventh lower via area HA7 is located at the second electrode of the first reset transistor T1; the twelfth lower via area HA12 is located at the data write The first electrode of the transistor T4; the third lower via area HA3 is located at the second electrode of the first light-emitting control transistor T5; the ninth lower via area HA9 is located at the first electrode of the first light-emitting control transistor T5; the fourth lower via area HA4 is located at the second electrode of the second reset transistor T8; the eleventh lower via area HA11 is located at the first electrode of the second reset transistor T8; the eighth lower via area HA8 is located at the second electrode of the second light-emitting control transistor T6; the fifth lower via area HA5 is located at the second electrode of the driving transistor T3; and the fourteenth lower via area HA14 is located at the first electrode of the electrode reset transistor T7.

[0137] FIG4 is a schematic diagram of the structure of the first gate layer GT1 in an example. Referring to FIG4 , the first gate layer GT1 is provided with a light-emitting signal line EML, a first reset control signal line RPL, a second reset control signal line RHL, a second scan signal line GPL (transfer structure GA1), and a first electrode CP1 of the storage capacitor Cst along the row direction DH; wherein the first reset control signal line RPL extends along the row direction DH and is used to load the first reset control signal RP to the first reset transistor T1; the second reset control signal line RHL extends along the row direction DH and is used to load the second reset control signal RH to the second reset transistor T8; the light-emitting signal line EML extends along the row direction DH and overlaps with the channel region T5A of the first light-emitting control transistor and the channel region T6A of the second light-emitting control transistor in sequence to multiplex the first light-emitting control transistor T5 and the second light-emitting control transistor T6. The gate of the control transistor T6, the light-emitting signal line EML is used to load the light-emitting signal EM to the first light-emitting control transistor T5 and the second light-emitting control transistor T6; the first electrode CP1 of the storage capacitor Cst overlaps with the channel area T3A of the driving transistor to be multiplexed as the gate of the driving transistor T3, and the first electrode CP1 is provided with a first lower via area HA1; the second scan signal line GPL (transfer structure GA1) extends along the row direction DH, and the second scan signal line GPL (transfer structure GA1) can overlap with the channel area T4A of the data write transistor to be multiplexed as the gate of the data write transistor T4. The second scan signal line GPL (transfer structure GA1) is used to load the second scan signal GP to the data write transistor T4, and the transfer structure GA1 is provided with a twenty-fifth lower via area HA25.

[0138] FIG5-2 is a schematic diagram of a stacked structure of a low-temperature polysilicon semiconductor layer PSCL, a first gate layer GT1, and a second gate layer GT2 in an example.

[0139] FIG5-1 is a schematic diagram of the structure of the second gate layer GT2 in one example. Referring to FIG5-1 , the second gate layer GT2 is provided with a jump structure GB1 (bridging segment VLY of the initialization column trace), a first lower scan signal trace GNLB, and a second electrode CP2 of the storage capacitor Cst. The jump structure GB1 (bridging segment VLY of the initialization column trace) extends along the column direction DV and is used to electrically connect the main segments VLX of two adjacent initialization column traces in the column direction. The first lower scan signal trace GNLB extends along the column direction DV. The second electrode CP2 of the storage capacitor Cst overlaps with the first electrode CP1 of the storage capacitor Cst, and a relief hole is provided to expose a portion of the first electrode CP1 of the storage capacitor Cst. The second electrode CP2 of the storage capacitor Cst is also provided with a tenth lower via area HA10.

[0140] Figure 6 is a schematic diagram of the structure of a metal oxide semiconductor layer (OSCL) in one example. Referring to Figure 6 , the metal oxide semiconductor layer (OSCL) includes a second electrode, a first electrode, and a channel region of a threshold compensation transistor (T2). Along the column direction (DV), the channel region (T1A) of the first reset transistor (T1A) is located on the side of the channel region (T2A) of the threshold compensation transistor (T2A) away from the channel region (T3A) of the drive transistor. The channel region (T2A) of the threshold compensation transistor (T2A) and the channel region (T5A) of the first emission control transistor (T5A) are located on either side of the channel region (T3A) of the drive transistor. Along the row direction (DH), the channel region (T4A) of the data write transistor (T1A) of the next row of drive circuits and the channel region (T7A) of the first reset transistor (T1) are located on either side of the channel region (T7A) of the electrode reset transistor (T7A) of the previous row of drive circuits. The second electrode of the first reset transistor (T1) and the second electrode of the threshold compensation transistor (T2) are interconnected, and the channel regions (T1A) of the first reset transistor (T1A) and (T2A) of the threshold compensation transistor (T2A) are interlaced in the row direction (DH). The metal oxide semiconductor layer (OSCL) also includes a second lower via region (HA2) and a sixth lower via region (HA6).

[0141] FIG7 is a schematic diagram of the structure of the third gate layer GT3 in an example. Referring to FIG7 , the third gate layer GT3 is provided with a first upper scan signal trace GNLA along the row direction DH, a first initial trace HL1 in the row direction, a second initial trace HL2, and a third initial trace HL3; wherein the first initial trace HL1 extends along the row direction DH, and can be used to load the first initialization voltage Vinit1, and the first initial trace HL1 is also provided with a twenty-second lower via area HA22; the second initial trace HL2 extends along the row direction DH, and can be used to load the second initialization voltage Vinit2, and the second initial trace HL2 is also provided with a twenty-third lower via area HA 23; the third initial running line HL3 extends along the row direction DH, and the third initial running line HL3 can be used to load the third initialization voltage Vinit3. The third initial running line HL3 is also provided with a nineteenth lower via area HA19; the first upper scanning signal line GNLA extends along the row direction DH, and is used to load the first scanning signal GN to the threshold compensation transistor T2. The first upper scanning signal line GNLA overlaps with the channel area T2A of the threshold compensation transistor to be multiplexed as the gate of the threshold compensation transistor T2. The first upper scanning signal line GNLA and the first lower scanning signal line GNLB work together to load the first scanning signal GN to the threshold compensation transistor T2.

[0142] FIG8-1 is a schematic diagram of the structure of the first source-drain metal layer SD1 in an example. Referring to FIG8-1 , the first source-drain metal layer SD1 is provided with the following bridge portion:

[0143] A first upper via area HB1 and a second upper via area HB2 are provided on the first bridge portion MA1, wherein the first upper via area HB1 overlaps with the first lower via area HA1 and is connected through a via; the second upper via area HB2 overlaps with the second lower via area HA2 and is connected through a via; in this way, the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first bridge portion MA1.

[0144] A third upper via area HB3 and a fourth upper via area HB4 are provided on the second bridge portion MA2, wherein the third upper via area HB3 overlaps with the third lower via area HA3 and is connected through a via; wherein the fourth upper via area HB4 overlaps with the fourth lower via area HA4 and is connected through a via; in this way, the second electrode of the first light-emitting control transistor T5 is electrically connected to the second electrode of the second reset transistor T8 through the second bridge portion MA2.

[0145] The third bridge portion MA3 is provided with a seventh upper via area HB7, a fifth upper via area HB5 and a sixth upper via area HB6, wherein the fifth upper via area HB5 overlaps with the fifth lower via area HA5 and is connected through a via; the sixth upper via area HB6 overlaps with the sixth lower via area HA6 and is connected through a via; the seventh upper via area HB7 overlaps with the seventh lower via area HA7 and is connected through a via; in this way, the second electrode of the driving transistor T3, the second electrode of the threshold compensation transistor T2 and the second electrode of the first reset transistor T1 are electrically connected through the third bridge portion MA3.

[0146] An eighth upper via area HB8 and a fifteenth lower via area HA15 are provided on the fourth bridge portion MA4, wherein the eighth upper via area HB8 overlaps with the eighth lower via area HA8 and is connected through a via; the fifteenth upper via area HB15 overlaps with the fifteenth lower via area HA15 and is connected through a via; in this way, the signal of the second source-drain metal layer SD2 is electrically connected to the second electrode of the second light-emitting control transistor T6 through the fourth bridge portion MA4.

[0147] The fifth bridge portion MA5 is provided with a tenth upper via area HB10, a ninth upper via area HB9 and a seventeenth lower via area HA17, wherein the tenth upper via area HB10 overlaps with the tenth lower via area HA10 and is connected through a via; the ninth upper via area HB9 overlaps with the ninth lower via area HA9 and is connected through a via; in this way, the signal of the second source-drain metal layer SD2 is electrically connected to the first electrode of the first light-emitting control transistor T5 and the second electrode CP2 of the storage capacitor Cst through the fifth bridge portion MA5.

[0148] An eleventh upper via area HB11 and a nineteenth upper via area HB19 are provided on the sixth bridge portion MA6, wherein the eleventh upper via area HB11 overlaps with the eleventh lower via area HA11 and is connected through a via; the nineteenth upper via area HB19 overlaps with the nineteenth lower via area HA19 and is connected through a via; in this way, the first electrode of the second reset transistor T8 is electrically connected to the third gate layer GT3 through the sixth bridge portion MA6, so as to realize the loading of the third initialization voltage Vinit3 to the first electrode of the second reset transistor T8 through the third initial running line HL3 in the row direction.

[0149] A twentieth lower via area HA20 and a twelfth upper via area HB12 are provided on the seventh bridge portion MA7, wherein the twelfth upper via area HB12 overlaps with the twelfth lower via area HA12 and is connected through a via; in this way, the signal on the second source-drain metal layer SD2 is electrically connected to the first electrode of the data write transistor T4 through the seventh bridge portion MA7.

[0150] A twenty-second upper via area HB22 and a thirteenth upper via area HB13 are provided on the eighth bridge portion MA8, wherein the twenty-second upper via area HB22 overlaps with the twenty-second lower via area HA22 and is connected through a via; the thirteenth upper via area HB13 overlaps with the thirteenth lower via area HA13 and is connected through a via; in this way, the first reset transistor T1S is electrically connected to the third gate layer GT3 through the eighth bridge portion MA8, so as to realize the loading of the first initialization voltage Vinit1 to the first electrode of the first reset transistor T1 through the first initial running line HL1 in the row direction.

[0151] The fourteenth upper via area HB14 and the twenty-third upper via area HB23 are provided on the ninth bridge portion MA9, wherein the fourteenth upper via area HB14 overlaps with the fourteenth lower via area HA14 and is connected through a via; wherein the twenty-third upper via area HB23 overlaps with the twenty-third lower via area HA23 and is connected through a via; in this way, the ninth bridge portion MA9 is electrically connected to the first electrode of the electrode reset transistor T7 and the third gate layer GT3, so as to realize the loading of the second initialization voltage Vinit2 to the first electrode of the electrode reset transistor T7 through VTL2.

[0152] The sixteenth bridge portion MA10 is provided with a twenty-fourth upper via HB24 and a twenty-sixth upper via HB26. The twenty-fourth upper via HB24 overlaps with the twenty-fourth lower via HA24 and is connected via a via. The twenty-sixth upper via HB26 overlaps with the twenty-sixth lower via HA26 and is connected via a via. This implements a jumper design for the initialization column trace VL.

[0153] The seventeenth bridge portion MA11 is provided with a twenty-fifth upper via hole HB25 , wherein the twenty-fifth upper via hole HB25 overlaps with the twenty-fifth lower via hole HA25 and is connected through the via hole, so that the second scanning signal GP loaded on the seventeenth bridge portion MA11 is loaded onto the transfer structure GA1 .

[0154] FIG8-2 is a schematic diagram of a stacked structure of a low-temperature polysilicon semiconductor layer PSCL, a first gate layer GT1, a second gate layer GT2, and a first source / drain metal layer SD1 in an example.

[0155] FIG9 is a schematic diagram of the structure of the second source / drain metal layer SD2 in an example. Referring to FIG9 , the second source / drain metal layer SD2 is provided with a first metal portion MB1, a second metal portion MB2, a third metal portion MB3, and a fourth metal portion MB4;

[0156] A 21st lower via area HA21 and a 20th upper via area HB20 are provided on the first metal part MB1; wherein the 20th upper via area HB20 overlaps with the 20th lower via area HA20 and is connected through vias; thus, the power supply voltage VDD is loaded onto the seventh bridge part MA7 through the fourteenth bridge part MB7.

[0157] A seventeenth upper via area HB17 and an eighteenth lower via area HA18 are provided on the second metal portion MB2. The seventeenth upper via area HB17 overlaps with the seventeenth lower via area HA17 and is connected through vias. Thus, the power supply voltage VDD is loaded onto the fifth bridge portion MA5 through the twelfth bridge portion MB5.

[0158] A fifteenth upper via area HB15 and a sixteenth lower via area HA16 are provided on the third metal part MB3; wherein the fifteenth upper via area HB15 overlaps with the fifteenth lower via area HA15 and is connected through vias; thus, the power supply voltage VDD is loaded onto the fourth bridge part MA4 through the third metal part MB3.

[0159] Figure 9 is a schematic diagram of the structure of the second source / drain metal layer SD2 in one example. Referring to Figure 9 , in some circuit areas PA, the data signal lines DL are electrically connected to the first backup structure MB4 (equivalent to the fourth metal portion MB4 on the second source / drain metal layer SD2) through vias. This first backup structure MB4 extends to connect to the first backup line SWL1. This allows the data voltage on the data signal lines DL to be applied to the first backup structure MB4.

[0160] 9 and 10 , in some circuit areas PA, the second backup line SWL2 is electrically connected to the first backup structure MB4 through vias, and the first backup structure MB4 extends to connect to the first backup line SWL1 , so that the data voltage of the second backup line SWL2 is applied to the first backup line SWL1 .

[0161] In one example, at least one data signal line DL is electrically connected to the first spare structure MB4 in one circuit area PA through a via, and the first spare structure MB4 extends to the first spare structure MB4. In another circuit area PA, the above-mentioned first spare line SWL1 is connected to the first spare structure MB4, and the first spare structure MB4 is connected to the second spare line SWL2 through a via. In this way, by loading the data voltage to the above-mentioned second spare line SWL2, the data voltage can be loaded to the above-mentioned data signal line DL through the above-mentioned first spare line SWL1. Furthermore, the above-mentioned data signal line DL is separated from the above-mentioned second spare line SWL2 by a plurality of sub-circuit area columns. In this way, the display panel can adopt FIAA technology (narrow border technology) to reduce the border of the display panel.

[0162] FIG10 is a schematic diagram of the structure of the third source / drain metal layer SD3 in an example. Referring to FIG10 , the third source / drain metal layer SD3 is provided with a first conductive portion MC1, a second conductive portion MC2, a third conductive portion MC3, and a second backup line SWL2;

[0163] The third conductive portion MC3 is provided with a sixteenth upper via area HB16 , wherein the sixteenth upper via area HB16 overlaps with the sixteenth lower via area HA16 and is connected through a via; thus, the power supply voltage VDD is loaded onto the third metal portion MB3 through the third conductive portion MC3 .

[0164] The second conductive portion MC2 is provided with an eighteenth upper via area HB18 , wherein the eighteenth upper via area HB18 overlaps with the eighteenth lower via area HA18 and is connected through a via; thus, the power supply voltage VDD is loaded onto the second metal portion MB2 through the second conductive portion MC2 .

[0165] The first conductive portion MC1 is provided with a 21st upper via area HB21 , wherein the 21st upper via area HB21 overlaps with the 21st lower via area HA21 and is connected through a via hole; thus, the data voltage is applied to the first metal portion MB1 through the first conductive portion MC1 .

[0166] Figure 19 is a schematic diagram of the structure of a pixel electrode PE in one example. Referring to Figure 19 and Figure 10 , the pixel electrode PE is electrically connected to the third conductive portion MC3 via a via. Furthermore, as shown in Figure 19 , this application may also provide a pixel arrangement based on the arrangement of the pixel electrodes PE, but this is not specifically described in this application.

[0167] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel, characterized in that, It includes a substrate substrate, a driving layer, and a pixel layer which are stacked in sequence; the driving layer is provided with a pixel driving circuit for driving sub-pixels, and a scanning signal line extending in the row direction and a data signal trace extending in the column direction are provided; the pixel driving circuit includes a data writing transistor, a first pole of the data writing transistor is electrically connected to the data signal trace, and a gate of the data writing transistor is electrically connected to the scanning signal line; The driving layer includes a transistor layer and a first source-drain metal layer which are stacked in sequence on the substrate substrate; the gate of the data writing transistor is provided on the transistor layer, and the scanning signal line is provided on the first source-drain metal layer; the gate of the data writing transistor and the scanning signal line are electrically connected through a via.

2. The display panel according to claim 1, wherein The transistor layer includes a low-temperature polycrystalline silicon semiconductor layer, a first gate insulating layer, and a first gate layer which are stacked in sequence on the substrate substrate; the channel region of the data writing transistor is located in the low-temperature polycrystalline silicon semiconductor layer; the first gate layer is provided with a transfer structure, and the gate of the data writing transistor is located in the transfer structure; The transfer structure is electrically connected to the scanning signal line through a plurality of vias.

3. The display panel according to claim 2, characterized in that, The transfer structure extends in the row direction, and the gates of two adjacent data writing transistors in the same row are located in the same transfer structure.

4. The display panel according to claim 2, wherein The display panel is further provided with an initialization walking line extending in the row direction and an initialization column trace extending in the column direction. The initialization walking line and the initialization column trace are electrically connected through a via at the overlapping portion, and the initialization walking line and the initialization column trace are used to load an initialization voltage.

5. The display panel according to claim 4, wherein The driving layer includes a transistor layer and a first source-drain metal layer; The initialization walking line is located in the transistor layer; the initialization column trace includes a main segment of the initialization column trace located in the first source-drain metal layer and a bridging segment of the initialization column trace located in the transistor layer. The main segment of the initialization column trace is electrically connected to the overlapping initialization walking line through a via; the main segments of two adjacent initialization column traces in the column direction are connected through the bridging segment of the initialization column trace; the bridging segment of the initialization column trace overlaps with the scanning signal line.

6. The display panel according to claim 4, wherein, The initialization column trace includes a first initial column trace, a second initial column trace, and a third initial column trace; The initial walking line includes a first initial walking line, a second initial walking line, and a third initial walking line; Wherein, the first initial column trace is connected to the first initial walking line through a via and is used to load a first initialization voltage; The second initial column trace is connected to the second initial walking line through a via and is used to load a second initialization voltage; The third initial column trace is connected to the third initial walking line through a via and is used to load a third initialization voltage.

7. The display panel according to claim 1, wherein The display panel includes a circuit region arranged in an array; the circuit region includes a first sub-circuit region and a second sub-circuit region adjacent to each other in the row direction; each thin film transistor of a pixel driving circuit is respectively provided in the first sub-circuit region and the second sub-circuit region; The circuit area rows are each provided with a first initial running line, a second initial running line, and a third initial running line; The circuit area column includes a first circuit area column, a second circuit area column and a third circuit area column arranged periodically; the first circuit area column is provided with a first initial column routing; the second circuit area column is provided with a second initial column routing; the third circuit area column is provided with a third initial column routing.

8. The display panel according to claim 7, wherein, In the circuit area column, the initialization column wiring extends along a boundary line between the first sub-circuit area and the second sub-circuit area.

9. The display panel according to claim 1, wherein The transistor layer includes a low-temperature polysilicon semiconductor layer, a first gate layer, a second gate layer, a metal oxide semiconductor layer and a third gate layer which are stacked in sequence; The bridge section of the initialization column wiring is located in one of the first gate layer, the second gate layer and the third gate layer, and the initialization wiring is located in at least one of the other two layers.

10. The display panel according to claim 9, wherein The bridge section of the initialization column wiring is located in the second gate layer; and the initialization wiring is located in the third gate layer.

11. The display panel according to claim 4, characterized in that, The driving layer includes a transistor layer, a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer stacked in sequence; The initialization line is located in the transistor layer; the initialization column line is located in the second source and drain metal layer; The first source / drain metal layer is provided with a transfer portion of an initialization column line, the initialization column line is electrically connected to the transfer portion of the initialization column line through a via hole, and the transfer portion of the initialization column line is electrically connected to the corresponding initialization line through a via hole.

12. The display panel according to any one of claims 1 to 11, characterized in that, The pixel circuit further includes a driving transistor; the first source-drain metal layer includes a first bridge portion, and the first bridge portion is connected to the gate of the driving transistor through a via hole; The display panel further includes a metal light-shielding layer; The metal shading layer is arranged on a side of the base substrate close to the driving layer; the metal shading layer has a first isolation trace arranged along the column direction; the orthographic projection of the first isolation trace on the base substrate is located between the first pole of the data writing transistor and the orthographic projection of the first bridge portion on the base substrate.

13. The display panel according to any one of claims 1 to 11, characterized in that, The first source-drain metal layer includes a first bridge portion, and the first bridge portion is connected to the gate of the driving transistor through a via hole; The display panel further includes a metal light-shielding layer; The metal light shielding layer is arranged on a side of the base substrate close to the driving layer; the metal light shielding layer has a first partition trace arranged along the column direction; the orthographic projection of the first bridge portion on the base substrate is located within the orthographic projection of the first partition trace on the base substrate.

14. The display panel according to claim 11, wherein The second source-drain metal layer is also provided with a second metal portion; the second metal portion is electrically connected through a power supply voltage trace located on the third source-drain metal layer; the orthographic projection of the first bridging portion on the base substrate is located within the orthographic projection of the second metal portion on the base substrate.

15. The display panel according to claim 12 or 13, characterized in that, The metal light shielding layer can be loaded with a power supply voltage.

16. A display device, characterized in that, The display device comprises the display panel according to any one of claims 1 to 15.

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