Back-contact cell and manufacturing method therefor

Abstract

The present invention relates to the technical field of photovoltaics. Disclosed are a back-contact cell and a manufacturing method therefor, which aim to improve the surface passivation effect of a surface passivation layer with regard to the side of a backlit surface of a silicon substrate and reduce the carrier recombination rate of the side of a backlit surface of the back-contact cell. The back-contact cell comprises a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer and a surface passivation layer, wherein in a backlit surface of the silicon substrate, a region corresponding to the first doped semiconductor layer is a first region, a region corresponding to the second doped semiconductor layer is a second region, and a region between the first region and the second region adjacent thereto is a spacing region; in the spacing region, a region adjacent to the first doped semiconductor layer is a first spacing sub-region, and the remaining region is a second spacing sub-region, the surface of the first spacing sub-region being a flat surface; and the surface passivation layer covers the first doped semiconductor layer, the second doped semiconductor layer and the spacing region.

Description

Back contact battery and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back-contact cell and a manufacturing method thereof. Background Art

[0002] A back-contact cell is a solar cell with no electrodes on the light-facing side of the cell. Instead, both the positive and negative electrodes are located on the backside of the cell. This reduces shading of the cell by the electrodes, increases the cell's short-circuit current, and improves the cell's energy conversion efficiency. Furthermore, a surface passivation layer can be formed on the backside of the back-contact cell to reduce the carrier recombination rate on this side, thereby improving the cell's photoelectric conversion efficiency.

[0003] However, the surface passivation layer in the existing back-contact cell has a poor passivation effect on the backlight side, which is not conducive to improving the photoelectric conversion efficiency of the back-contact cell. Summary of the Invention

[0004] The purpose of the present invention is to provide a back-contact battery and a method for manufacturing the same, which are used to improve the surface passivation effect of the surface passivation layer on the backlight side of the silicon substrate, reduce the carrier recombination rate on the backlight side of the back-contact battery, and help improve the photoelectric conversion efficiency of the back-contact battery.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a back-contact cell comprising: a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer, and a surface passivation layer. The first doped semiconductor layer and the second doped semiconductor layer are alternately spaced and arranged parallel to the silicon substrate on the backlight side of the silicon substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types. On the backlight side of the silicon substrate, the region corresponding to the first doped semiconductor layer is the first region, the region corresponding to the second doped semiconductor layer is the second region, and the region between the first region and the adjacent second region is the spacer region. Along the arrangement direction of the first and second regions, within the spacer region, the region adjacent to the first doped semiconductor layer is the first spacer region, and the remaining region is the second spacer region. The surfaces of the first spacer region and the second spacer region are both recessed into the silicon substrate relative to the surface of the first region, and the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region. The surface of the first spacer region is flat. The surface passivation layer covers the first doped semiconductor layer, the second doped semiconductor layer, and the spacer region.

[0006] When the above technical solution is adopted, in the back-contact battery provided by the present invention, the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types are alternately spaced and distributed on the backlight side of the silicon substrate in a direction parallel to the silicon substrate. Based on this, the spacing region on the backlight side of the silicon substrate can isolate the above-mentioned first doped semiconductor layer and the second doped semiconductor layer, reduce the carrier recombination rate at the lateral junction of the first doped semiconductor layer and the second doped semiconductor layer, and help improve the photoelectric conversion efficiency of the back-contact battery. Secondly, in the spacing region, the part adjacent to the first region is the first spacer region, and the remaining region is the second spacer region. In addition, the surface of the first spacer region and the surface of the second region are both concave into the silicon substrate relative to the surface of the first region, and the surface of the second spacer region is concave into the silicon substrate relative to the surface of the first spacer region. In this case, since the first doped semiconductor layer is formed on the first area of ​​the backlight surface and the second doped semiconductor layer is formed on the second area of ​​the backlight surface, when the surface of the second area is recessed into the silicon substrate relative to the surface of the first area, it is beneficial to at least partially stagger the first doped semiconductor layer and the second doped semiconductor layer, which are located on the backlight side of the silicon substrate and have opposite conductivity types, along the thickness direction of the silicon substrate, thereby further reducing the risk of leakage on the backlight side and improving the electrical reliability of the back-contact battery.

[0007] In addition, the back-contact cell provided by the present invention further includes a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacer region to chemically passivate the backlight-removing side of the first and second doped semiconductor layers, as well as the spacer region, thereby reducing the carrier recombination rate. Based on this, the first spacer region has a flat surface. Compared to a velvet surface, a flat surface has a smaller specific surface area. Within a certain range, the thickness of the surface passivation layer is inversely proportional to the specific surface area of ​​the surface below it, and the passivation effect of the surface passivation layer is directly proportional to its thickness. Therefore, the thickness of the surface passivation layer formed on the first spacer region is greater than the thickness of the surface formed on the velvet surface, and the corresponding passivation effect of the surface passivation layer on the first spacer region is greater than the passivation effect of the surface passivation layer on the velvet surface. In this case, compared to existing back-contact cells in which all the spacer regions have a velvet surface, the back-contact cell provided by the present invention has at least the first spacer region included in the spacer region. In this case, the surface passivation layer has a higher surface passivation effect on the first spacer region, which further reduces the carrier recombination rate in the first spacer region and further improves the photoelectric conversion efficiency of the back-contact cell.

[0008] As a possible implementation solution, along the arrangement direction of the first region and the second region, the length of the spacing region is greater than or equal to 20 μm and less than or equal to 110 μm.

[0009] When the above technical solution is adopted, the length of the spacing region is within the above range, which can prevent leakage between the first doped semiconductor layer and the second doped semiconductor layer due to the small spacing, thereby ensuring the high electrical reliability of the back-contact battery. In addition, it can also prevent the large spacing from causing the first doped semiconductor layer and / or the second doped semiconductor layer to form a smaller area on the backlight side, resulting in the inability of carriers on the backlight side to be collected by the first doped semiconductor layer and / or the second doped semiconductor layer in a timely manner and be conducted away by the corresponding electrodes, further reducing the carrier recombination rate on the backlight side.

[0010] As a possible implementation solution, along the arrangement direction of the first region and the second region, the length of the first spacer region is greater than or equal to 1000 nm and less than or equal to 3000 nm.

[0011] When the above technical solution is adopted, the length of the first spacer region is within the above range, which can prevent the surface passivation layer from significantly improving the passivation effect of the spacer region due to the small length of the first spacer region, thereby ensuring that the backlight side has a lower carrier recombination rate. In addition, in the actual manufacturing process, the flat surface of the first spacer region is due to the suspended end portion of the first doped semiconductor layer at least located above the first spacer region during the formation of the second doped semiconductor layer (the suspended end portion will be removed before the surface passivation layer is formed). Under the protective effect of the suspended end portion, the corresponding etching solution will only corrode the second spacer region, and the surface of the first spacer region will not be affected by the etching solution, resulting in uneven surface due to reasons such as excessive etching. Based on this, the length of the first spacer region is within the above range, which can also prevent the manufacturing difficulty caused by the need to form a long suspended end portion during the manufacturing process due to the large length of the first spacer region, thereby reducing the manufacturing difficulty of the back contact battery.

[0012] As a possible implementation solution, the surface of the first spacer region is flush with the surface of the second region.

[0013] When using the above technical solution, in the actual manufacturing process, after forming a full-layer first doped semiconductor layer on the backlight side, the first doped semiconductor layer needs to be selectively etched. After the selective etching, the surfaces of the spacer region and the second region are both recessed inward relative to the surface of the first region, and the recesses are of the same depth. Based on this, when the surfaces of the first spacer region and the second region are flush, that is, the surfaces of the first spacer region and the second region are recessed into the silicon substrate to the same depth, it is no longer necessary to selectively etch the first spacer region or the second region again after the first doped semiconductor layer is selectively etched. This simplifies the manufacturing process of the back-contact cell and can also reduce the thickness of the silicon substrate, facilitating thin-film production.

[0014] As a possible implementation solution, the depth of the surface of the first spacer region recessed into the silicon substrate relative to the surface of the first region is greater than or equal to 500 nm and less than or equal to 2500 nm.

[0015] When the above technical solution is adopted, the depth of the surface of the first spacer region recessed into the silicon substrate is within the above range. This can prevent the first doped semiconductor layer and the second doped semiconductor layer, which are both located on the backlight side of the silicon substrate and have opposite conductivity types, from being offset to a smaller extent along the thickness direction of the silicon substrate due to the smaller depth, further reducing the risk of leakage on the backlight side. In addition, in the actual manufacturing process, after forming a groove structure that is recessed into the silicon substrate relative to the surface of the first region in the spacer region and the second region on the backlight side of the silicon substrate, the end of the first doped semiconductor layer adjacent to the spacer region can be suspended, and the surface of the first spacer region can be recessed into the silicon substrate. Based on this, the depth of the surface of the first spacer region recessed into the silicon substrate is within the above range, which can also prevent the suspended end of the first doped semiconductor layer from being affected by the etching liquid for etching the silicon substrate due to the large depth of the groove structure, resulting in a shorter length of the end suspended on the spacer region (thus resulting in a smaller length of the first spacer region), ensuring that the surface passivation layer has a higher passivation effect on the spacer region; it can also prevent the use of a thicker silicon substrate due to the large depth of the above-mentioned groove structure, thereby reducing the manufacturing cost of the back-contact battery while facilitating the thin-film production of the back-contact battery.

[0016] As a possible implementation, the surface of the second spacer region is a velvet surface. In this case, because the velvet surface has a light-trapping effect, when the surface of the second spacer region is a velvet surface, more light can be refracted through the surface of the second spacer region into the silicon substrate, further improving the photoelectric conversion efficiency of the back-contact cell.

[0017] As a possible implementation solution, the depth of the surface of the second spacer region recessed into the silicon substrate relative to the surface of the first region is greater than or equal to 3 μm and less than or equal to 5 μm.

[0018] When adopting the above technical solution, in the actual manufacturing process, after forming the first doped semiconductor layer and forming the groove structure in the second region and the spacer region, a second doped semiconductor layer is deposited on the backlight side and selectively etched. To prevent leakage, after removing the portion of the second doped semiconductor layer located on the second spacer region, etching is often continued downward to a certain depth to ensure that the portion of the second doped semiconductor layer located on the second spacer region is completely removed. Based on this, the depth of the second spacer region's surface recessed into the silicon substrate within the above range can prevent the high risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types caused by the smaller depth, thereby ensuring that the back contact cell has higher electrical reliability. In addition, it is understood that the greater the depth of the second spacer region's surface recessed into the silicon substrate, the longer the etching time of the corresponding etching solution, and the greater the impact of the corresponding etching solution on other structures. Based on this, the depth of the surface of the second spacer region recessed into the silicon substrate is within the above range, which can also prevent the suspended end of the first doped semiconductor layer and the first spacer region from being affected by the corrosive liquid and shortened in length due to the greater depth, thereby ensuring that the surface passivation layer has a higher passivation effect on the spacer region; it can also prevent the need to use a thicker silicon substrate due to the greater depth of the surface of the second spacer region recessed into the silicon substrate, thereby reducing the manufacturing cost of the back-contact battery and facilitating the thin-film production of the back-contact battery.

[0019] As a possible implementation scheme, in the side wall of the above-mentioned spacer region adjacent to the first doped semiconductor layer, at least part of the side wall surface is inclined relative to the horizontal plane so that the cross-sectional area of ​​at least part of the spacer region gradually increases in the direction from the light-facing surface to the backlight surface.

[0020] When using the above technical solution, the cross-sectional area of ​​the spacer region on the side facing the light is smaller than the cross-sectional area on the side facing the backlight, which helps increase the distance between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity type, reduces the risk of leakage on the backlight side of the back-contact cell, and ensures the back-contact cell has high electrical reliability. In addition, the portion of the sidewall of the spacer region adjacent to the first doped semiconductor layer that is inclined relative to the plane also helps reflect light, allowing more light to enter the silicon substrate from the backlight side of the back-contact cell due to reflection from the portion of the sidewall of the spacer region adjacent to the first doped semiconductor layer that is inclined relative to the plane, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0021] As a possible implementation, the sidewall surface of the portion of the spacer region adjacent to the first doped semiconductor layer, which is located near the backlight surface, is perpendicular to the horizontal plane. This provides another possible implementation for the morphology of the portion of the spacer region adjacent to the first doped semiconductor layer in the back-contact cell provided by the present invention, thereby improving the applicability of the back-contact cell provided by the present invention in different application scenarios.

[0022] As a possible implementation solution, the back-contact cell further includes a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer.

[0023] When adopting the above technical solution, the first passivation layer and the first doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the first area on the backlight surface of the silicon substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0024] As a possible implementation solution, the back-contact cell further includes a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

[0025] When adopting the above-mentioned technical solution, the second passivation layer and the second doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the second area on the backlight surface of the silicon substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0026] As a possible implementation solution, when the back contact cell includes a first passivation layer, and the first passivation layer is a tunneling passivation layer, the first doped semiconductor layer is a doped polysilicon layer.

[0027] As a possible implementation solution, when the back contact cell includes a second passivation layer, and the second passivation layer is a tunneling passivation layer, the second doped semiconductor layer is a doped polysilicon layer.

[0028] In a second aspect, the present invention provides a method for manufacturing a back-contact solar cell, comprising the following steps: first, providing a silicon substrate. A back-illuminated side of the silicon substrate comprises first and second regions arranged alternately and spaced parallel to the silicon substrate, and a region between the first region and the adjacent second region is referred to as a spacer region. Within the spacer region, along the arrangement of the first and second regions, the region adjacent to the first region is referred to as a first spacer region, and the remaining region is referred to as a second spacer region. Next, forming a first doped semiconductor layer on the first region and the first spacer region; and forming a recessed structure recessed into the silicon substrate in the spacer region and the second region, such that the end of the first doped semiconductor layer adjacent to the spacer region is suspended. The bottom of the recessed structure is a flat surface. Next, depositing a second doped semiconductor layer on the first doped semiconductor layer and within the recessed structure, and forming a first mask layer on the portion of the second doped semiconductor layer located in the second region. Next, using the first mask layer as a mask, selectively removing the portion of the second doped semiconductor layer located in the first region and the spacer region, and recessing the surface of the second spacer region relative to the surface of the first spacer region into the silicon substrate. Next, the suspended end portion of the first doped semiconductor layer is removed, the first mask layer is removed, and then a surface passivation layer is formed covering the first doped semiconductor layer, the second doped semiconductor layer and the spacer region.

[0029] As a possible implementation, after providing a silicon substrate and before depositing a second doped semiconductor layer on the first doped semiconductor layer and within the recessed structure, the method for manufacturing a back-contact cell further includes the following steps: forming a full-layer first doped semiconductor layer on the backlit surface of the silicon substrate; and disposing a second mask layer on the portion of the first doped semiconductor layer located in the first region and the first spacer region. Next, under the masking action of the second mask layer, the portion of the first doped semiconductor layer located in the second spacer region and the second region is selectively removed. Next, under the masking action of the second mask layer, the recessed structure is formed in the spacer region and the second region.

[0030] As a possible implementation scheme, the material of the first doped semiconductor layer includes silicon. Furthermore, the above-mentioned steps of forming a first doped semiconductor layer arranged as a whole layer on the backlight surface of the silicon substrate, and providing a second mask layer on the portion of the first doped semiconductor layer located in the first region and the first spacer region include: forming a first intrinsic semiconductor layer arranged as a whole layer on the backlight surface of the silicon substrate. Then, the first intrinsic semiconductor layer is doped to form the first doped semiconductor layer from the first intrinsic semiconductor layer, and a first doped silicon glass layer arranged as a whole layer is formed on the first doped semiconductor layer. Next, a laser etching process is used to heat-treat the portion of the first doped silicon glass layer located in the second spacer region and the second region, so that the portion of the first doped silicon glass layer that has not been heat-treated (i.e., the portion located in the first region and the first spacer region) forms a second mask layer. Then, the heat-treated portion of the first doped silicon glass layer is removed.

[0031] When the above technical solution is employed, when the material of the first doped semiconductor layer includes silicon, the material of the first intrinsic semiconductor layer used to form the first doped semiconductor layer also includes silicon. Based on this, after doping the first intrinsic semiconductor layer, not only is the first doped semiconductor layer obtained, but a first doped silica glass layer can also be formed entirely on the first doped semiconductor layer. Subsequently, a laser etching process is used to heat treat a portion of the first doped silica glass layer. During this process, the laser-treated portion of the first doped silica glass layer has reduced density and is easily removed. In contrast, the untreated portion of the first doped silica glass layer has a higher density and is not easily removed. Consequently, after the heat treatment, different portions of the first doped silica glass layer have different etching selectivities, resulting in a second mask layer for patterning the first doped semiconductor layer. This eliminates the need for additional mask materials and mask deposition steps to obtain the second mask layer, thereby reducing the manufacturing cost of back-contact solar cells and simplifying the manufacturing process for back-contact solar cells.

[0032] As a possible implementation, a wet chemical process is used, and under the masking action of a second mask layer, a groove structure is formed in the spacer region and the second region. In this case, the process temperature of the wet chemical process is greater than or equal to 61°C and less than or equal to 83°C; and / or the process time of the wet chemical process is greater than or equal to 60 seconds and less than or equal to 450 seconds; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 1% and less than or equal to 15%; and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 3%.

[0033] When the above technical solution is adopted, the process temperature and process time of the wet chemical process will affect the specifications of the groove structure formed by the wet chemical process and the specifications of the end portion suspended in the first doped semiconductor layer. Based on this, the process temperature of the wet chemical process is within the above range, which can prevent the depth of the groove structure, the suspended height and length of the end portion suspended in the first doped semiconductor layer from being small due to the low process temperature. In addition, it can also prevent the depth of the groove structure from being large due to the high process temperature. The depth of the above-mentioned groove structure is equal to the depth of the first spacer region recessed into the silicon substrate relative to the surface of the first region. Based on this, the beneficial effects of preventing the depth of the groove structure, the suspended height and length of the end portion suspended in the first doped semiconductor layer from being small, and preventing the depth of the groove structure from being large can be referred to the above. Secondly, the beneficial effects of the process time and the volume ratio of the alkaline component within the above range are similar to the beneficial effects of the process temperature being greater than or equal to 61°C and less than or equal to 83°C, and will not be repeated here. In addition, when the volume ratio of the polishing additive in the wet chemical etching solution is within the above range, the flatness of the bottom surface of the groove structure can be improved, and the passivation effect of the surface passivation layer on the first spacer region can be further enhanced.

[0034] As a possible implementation solution, under the masking effect of the first mask layer, the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region, and the surface of the second spacer region is textured.

[0035] As a possible implementation scheme, the material of the above-mentioned second doped semiconductor layer includes silicon. In addition, the above-mentioned steps of depositing the second doped semiconductor layer on the first doped semiconductor layer and in the groove structure, and forming a first mask layer on the portion of the second doped semiconductor layer located in the second region include: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer and in the groove structure. Next, the second intrinsic semiconductor layer is doped to form a second doped semiconductor layer from the second intrinsic semiconductor layer, and a second doped silicon glass layer is formed on the second doped semiconductor layer. Then, a laser etching process is used to heat-treat the portion of the second doped silicon glass layer located in the first region and the spacing region, so that the portion of the second doped silicon glass layer located in the second region (i.e., not heat-treated) forms the first mask layer. Then, the heat-treated portion of the second doped silicon glass layer is removed.

[0036] In the above technical solution, when the material of the second doped semiconductor layer includes silicon, the material of the second intrinsic semiconductor layer used to form the second doped semiconductor layer also includes silicon. Based on this, after doping the second intrinsic semiconductor layer, not only is the second doped semiconductor layer obtained, but a second doped silica glass layer can also be formed entirely on the second doped semiconductor layer. Then, a laser etching process is used to heat treat the portions of the second doped silica glass layer located in the first region and the spacing region. During this process, the laser-treated portions of the second doped silica glass layer have reduced density and are easily removed. In contrast, the portions of the second doped silica glass layer located in the second region are not laser-treated, and their density is higher, making them less easily removed. Consequently, after the heat treatment, different portions of the second doped silica glass layer have different etching selectivities, resulting in a first mask layer for patterning the second doped semiconductor layer. This eliminates the need for additional mask materials and mask deposition steps to obtain the first mask layer, thereby reducing the manufacturing cost of back-contact solar cells and simplifying the manufacturing process for back-contact solar cells.

[0037] As a possible implementation scheme, a wet chemical process is used, and under the masking action of the first mask layer, the portion of the second doped semiconductor layer located on the first region and the spacer region is selectively removed, and the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region. In this case, the process temperature of the above-mentioned wet chemical process is greater than or equal to 61°C and less than or equal to 83°C; and / or the process time of the wet chemical process is greater than or equal to 100 seconds and less than or equal to 500 seconds; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 1% and less than or equal to 3.5%; and / or the wet chemical etching solution used in the wet chemical process contains a texturing additive, and the volume ratio of the texturing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 2%.

[0038] When the above technical solution is adopted, the process temperature and process time of the wet chemical process will affect the depth to which the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region through the wet chemical process. Based on this, the process temperature of the wet chemical process is within the above range, which can prevent the surface of the second spacer region from being recessed into the silicon substrate to a smaller depth relative to the surface of the first spacer region due to a lower process temperature. In addition, it can also prevent the surface of the second spacer region from being recessed into the silicon substrate to a greater depth relative to the surface of the first spacer region due to a higher process temperature. Among them, the beneficial effects of preventing the surface of the second spacer region from being recessed into the silicon substrate to a smaller or greater depth relative to the surface of the first spacer region can be referred to the above. Secondly, the beneficial effects of the process time and the volume ratio of the alkaline component within the above range are similar to the beneficial effects of the process temperature being greater than or equal to 61°C and less than or equal to 83°C, and will not be repeated here. In addition, the volume ratio of the texturing additive within the above-mentioned range can prevent the need to use a thicker silicon substrate to manufacture the back-contact battery due to the relatively large volume, which is conducive to the realization of thin-film production; it can also prevent the relatively small volume from resulting in the velvet structure formed on the surface of the second spacer area being small in size, resulting in an unsatisfactory light trapping effect on the surface of the second spacer area, ensuring that more light can be refracted into the silicon substrate through the surface of the second spacer area, further improving the photoelectric conversion efficiency of the back-contact battery.

[0039] As a possible implementation scheme, the manufacturing method of the back-contact battery also includes forming a first passivation layer, which includes the following steps: after the step of providing a silicon substrate, before the step of forming a first doped semiconductor layer on the first region and the first spacer region, forming a first passivation layer on the first region and the first spacer region.

[0040] As a possible implementation, the method for manufacturing a back-contact cell further includes forming a second passivation layer, comprising the following steps: after forming a recessed structure recessed into the silicon substrate on the spacer region and the second region, and before depositing the second doped semiconductor layer on the first doped semiconductor layer and within the recessed structure, depositing the second passivation layer on the first doped semiconductor layer and within the recessed structure. Furthermore, after selectively removing the portion of the second doped semiconductor layer located on the first region and the spacer region under the masking action of a first mask layer, and before causing the surface of the second spacer region to be recessed into the silicon substrate relative to the surface of the first spacer region, selectively removing the portion of the second passivation layer located on the first region and the spacer region under the masking action of the first mask layer.

[0041] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0043] FIG1 is a longitudinal cross-sectional SEM image of the structure of a back contact battery in the related art;

[0044] FIG2 is a longitudinal cross-sectional SEM image of the structure of a back-contact battery provided by an embodiment of the present invention;

[0045] FIG3 is a longitudinal cross-sectional SEM image of the structure of a back-contact battery provided by an embodiment of the present invention;

[0046] FIG4 is a longitudinal cross-sectional SEM image of the structure of a back-contact battery provided in an embodiment of the present invention;

[0047] FIG5 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided by an embodiment of the present invention;

[0048] FIG6 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0049] FIG7 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0050] FIG8 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0051] FIG9 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0052] FIG10 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0053] FIG11 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0054] FIG12 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0055] FIG13 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0056] FIG14 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0057] FIG15 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0058] FIG16 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0059] FIG17 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0060] FIG18 is a schematic structural diagram of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0061] FIG19 is a schematic structural diagram of a back-contact battery during the manufacturing process provided by an embodiment of the present invention.

[0062] Figure numerals: 11 is a silicon substrate, 12 is a first doped semiconductor layer, 13 is a second doped semiconductor layer, 14 is a first region, 15 is a second region, 16 is a spacer region, 17 is a first spacer region, 18 is a second spacer region, 19 is a surface passivation layer, 20 is a first passivation layer, 21 is a second passivation layer, 22 is a groove structure, 23 is a first mask layer, 24 is a second mask layer, 25 is a first intrinsic semiconductor layer, 26 is a first doped silicon glass layer, 27 is a second intrinsic semiconductor layer, and 28 is a second doped silicon glass layer. DETAILED DESCRIPTION

[0063] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0064] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0065] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0067] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0068] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells convert sunlight into electricity. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0069] When both the positive and negative electrodes of a solar cell are located on the backlight side of the solar cell, the solar cell is a back-contact cell. The light-facing side of this back-contact cell is not obstructed by metal electrodes. Therefore, compared to solar cells with obstructed light-facing sides, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, and are currently one of the technological directions for achieving high-efficiency crystalline silicon cells. Furthermore, forming a surface passivation layer on the backlight side of the semiconductor substrate included in the back-contact cell can reduce the carrier recombination rate on the backlight side of the semiconductor substrate, thereby improving the operating performance of the back-contact cell.

[0070] Specifically, existing back-contact cells typically include a silicon substrate, a first doped semiconductor layer, a second doped semiconductor layer, and a surface passivation layer. The first doped semiconductor layer and the second doped semiconductor layer are alternately spaced and arranged parallel to the silicon substrate on the backlight side of the silicon substrate. The surface passivation layer covers the first doped semiconductor layer, the second doped semiconductor layer, and the portion of the backlight side between the first doped semiconductor layer and the second doped semiconductor layer, thereby passivating the backlight sides of the first doped semiconductor layer and the second doped semiconductor layer, as well as the portion of the backlight side of the silicon substrate between the first doped semiconductor layer and the second doped semiconductor layer, thereby reducing the carrier recombination rate.

[0071] However, as shown in FIG1 , in the existing back-contact battery, the surface of the region where the backlight side of the silicon substrate 11 is located between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 is a velvet surface. Compared with a flat surface, a velvet surface has a larger specific surface area. Within a certain range, the thickness of the surface passivation layer is inversely proportional to the specific surface area of ​​the surface of the corresponding region below it; at the same time, the passivation effect of the surface passivation layer is proportional to its own thickness. Therefore, when the surface of the region where the backlight side of the silicon substrate 11 is located between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 is a velvet surface, the thickness of the surface passivation layer formed on this part of the surface is relatively small, resulting in poor passivation effect of the silicon substrate 11 on the backlight side, which is not conducive to improving the photoelectric conversion efficiency of the back-contact battery.

[0072] To address the above-mentioned technical issues, in a first aspect, embodiments of the present invention provide a back-contact cell. As shown in Figures 2 to 5, the back-contact cell comprises: a silicon substrate 11, a first doped semiconductor layer 12, a second doped semiconductor layer 13, and a surface passivation layer 19. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 are alternately spaced and distributed along a direction parallel to the silicon substrate 11 on the backlight side of the silicon substrate 11. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types. On the backlight side of the silicon substrate 11, the region corresponding to the first doped semiconductor layer 12 is a first region 14, the region corresponding to the second doped semiconductor layer 13 is a second region 15, and the region between the first region 14 and the adjacent second region 15 is a spacer region 16. Along the arrangement direction of the first region 14 and the second region 15, in the spacer region 16, the region adjacent to the first doped semiconductor layer 12 is a first spacer sub-region 17, and the remaining region is a second spacer sub-region 18. The surfaces of the first spacer region 17 and the second region 15 are both recessed into the silicon substrate 11 relative to the surface of the first region 14, and the surface of the second spacer region 18 is recessed into the silicon substrate 11 relative to the surface of the first spacer region 17. The first spacer region 17 has a flat surface. The surface passivation layer 19 covers the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacer region 16.

[0073] It should be noted that the first spacer region has a flat surface, which is a flat surface in a broad sense relative to the velvet surface. As shown in Figures 2 and 3, the surface of the first spacer region 17 can have certain ups and downs, or it can be an absolutely flat surface, as long as it is ensured that the surface of the first spacer region 17 is flatter than the velvet surface; secondly, the transition between the first spacer region 17 and the second spacer region 18 can be a regular right angle or obtuse angle, or a relatively smooth transition. In actual application, the area corresponding to the first spacer region 17 in the silicon substrate can be considered as a platform structure adjacent to the second spacer region. It can be understood that a flat surface has a smaller specific surface area than a velvet surface, and the thickness of the surface passivation layer formed on the first spacer region 17 with a flat surface will be greater than the thickness formed on the velvet surface itself. In this case, compared with the surface passivation layer formed on the velvet surface, the surface passivation layer formed on the first spacer region 17 with a flat surface has a higher surface passivation effect and fewer recombination centers, which is beneficial to further reduce the recombination rate of carriers in the first spacer region 17 and further improve the photoelectric conversion efficiency of the back contact battery.

[0074] When the above technical solution is adopted, as shown in FIG5 , in the back-contact cell provided by the embodiment of the present invention, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of opposite conductivity types are alternately spaced and distributed on the backlight side of the silicon substrate 11 in a direction parallel to the silicon substrate 11. Based on this, the spacing region 16 provided on the backlight side of the silicon substrate 11 can isolate the above-mentioned first doped semiconductor layer 12 and the second doped semiconductor layer 13, reduce the carrier recombination rate at the lateral junction of the first doped semiconductor layer 12 and the second doped semiconductor layer 13, and help improve the photoelectric conversion efficiency of the back-contact cell. Secondly, as shown in FIG2 to FIG5 , in the spacing region 16, the portion adjacent to the first doped semiconductor layer 12 is the first spacer region 17, and the remaining area is the second spacer region 18. Moreover, the surface of the first spacer region 17 and the surface of the second region 15 are both recessed into the silicon substrate 11 relative to the surface of the first region 14. In this case, because the first doped semiconductor layer 12 is formed on the first region 14 on the backlight side, and the second doped semiconductor layer 13 is formed on the second region 15 on the backlight side, when the surface of the second region 15 is recessed into the silicon substrate 11 relative to the surface of the first region 14, it is beneficial to at least partially stagger the first doped semiconductor layer 12 and the second doped semiconductor layer 13, which are located on the backlight side of the silicon substrate 11 and have opposite conductivity types, along the thickness direction of the silicon substrate 11, further reducing the risk of leakage on the backlight side and improving the electrical reliability of the back-contact battery. In addition, as shown in Figure 5, the back-contact battery provided by one embodiment of the present invention also includes a surface passivation layer 19 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacer region 16 to chemically passivate the backlight side of the first doped semiconductor layer 12 and the second doped semiconductor layer 13, as well as the spacer region 16, to reduce the carrier recombination rate. Based on this, the above-mentioned first spacer region 17 has a flat surface. Compared with a velvet surface, the flat surface has a smaller specific surface area. Within a certain range, the thickness of the surface passivation layer 19 is inversely proportional to the specific surface area of ​​the surface below it, and the passivation effect of the surface passivation layer 19 is proportional to its thickness. Therefore, the thickness of the surface passivation layer 19 formed on the first spacer region 17 is greater than its thickness formed on the velvet surface. Accordingly, the passivation effect of the surface passivation layer 19 on the first spacer region 17 is greater than its passivation effect on the velvet surface. In this case, compared with existing back-contact cells in which all parts of the surface of the spacer region are velvet, an embodiment of the present invention provides a back-contact cell in which at least the surface of the first spacer region 17 included in the spacer region 16 is flat. In this case, the surface passivation layer 19 has a higher surface passivation effect on the first spacer region 17, which is beneficial for further reducing the recombination rate of carriers in the first spacer region 17 and further improving the photoelectric conversion efficiency of the back-contact cell.

[0075] In actual applications, as shown in FIG5 , the light-facing surface of the silicon substrate 11 can be a flat surface; alternatively, the light-facing surface of the silicon substrate can be a velvet surface. Because a velvet surface traps light, a velvet surface can reduce the reflectivity of the light-facing surface, allowing more light to be refracted from the light-facing surface into the silicon substrate for absorption and utilization, thereby improving the photoelectric conversion efficiency of the back-contact solar cell.

[0076] In addition, from a scope perspective, the boundaries of the first region, second region, and spacing region on the backlight side of the aforementioned silicon substrate, as well as the boundaries of the first spacer region and the second spacer region in the spacing region, are virtual boundaries. As shown in FIG5 , the first doped semiconductor layer 12 is formed on the first region 14. Therefore, the scope of the first region 14 on the backlight side of the silicon substrate 11 can be determined based on the requirements for the formation scope of the first doped semiconductor layer 12 in the actual application scenario. Secondly, the second doped semiconductor layer 13 is formed on the second region 15. Therefore, the scope of the second region 15 on the backlight side of the silicon substrate 11 can be determined based on the requirements for the formation scope of the second doped semiconductor layer 13 in the actual application scenario. As for the spacing region 16, as described above, the spacing region 16 can isolate the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of opposite conductivity types, thereby suppressing leakage. Therefore, the scope of the spacing region 16 on the backlight side can be determined based on the requirements for the leakage prevention spacing between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 in the actual application scenario.

[0077] Exemplarily, along the arrangement direction of the first region and the second region, the length of the spacing region may be greater than or equal to 20 μm and less than or equal to 110 μm. For example, the length of the spacing region may be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm or 110 μm, etc. In this case, the length of the spacing region is within the above range, which can prevent leakage between the first doped semiconductor layer and the second doped semiconductor layer due to the small spacing, thereby ensuring that the back contact battery has high electrical reliability. In addition, it can also prevent the carriers on the backlight side from being collected by the first doped semiconductor layer and / or the second doped semiconductor layer in a timely manner and being led out by the corresponding electrode due to the large spacing, thereby further reducing the carrier recombination rate on the backlight side.

[0078] As shown in Figures 15 and 16 , the surface of the first spacer region 17 can be flat. As shown in Figure 15 , the surface of the second spacer region can also be flat; or, as shown in Figure 16 , the surface of the second spacer region can also be velvet. It is understood that the surface of the first spacer region 17 is flat because during the manufacturing process, the first doped semiconductor layer 12 has at least an overhanging end portion located above the first spacer region 17 (as shown in Figure 18 , this overhanging end portion is removed before forming the surface passivation layer). Protected by this overhanging end portion, the corresponding etching solution only etches the second spacer region 18, while the surface of the first spacer region 17 is not affected by the etching solution, which could cause unevenness due to overetching, thereby forming the first spacer region 17 with a flat surface. Therefore, the range of the first spacer region 17 and the second spacer region 18 can be determined based on the length of the overhanging end portion of the first doped semiconductor layer 12 during actual manufacturing and actual needs, and is not specifically limited here.

[0079] Exemplarily, along the arrangement direction of the first region and the second region, the length of the first spacer region can be greater than or equal to 1000nm and less than or equal to 3000nm. For example, the length of the first spacer region can be 1000nm, 1300nm, 1600nm, 1900nm, 2000nm, 2300nm, 2600nm, 2900nm or 3000nm, etc. In this case, the length of the first spacer region is within the above range, which can prevent the surface passivation layer from significantly improving the passivation effect of the spacer region due to the small length of the first spacer region, thereby ensuring that the backlight side has a lower carrier recombination rate. In addition, it can also prevent the manufacturing difficulty caused by the need to form a long suspended end portion during the manufacturing process due to the large length of the first spacer region, which is conducive to reducing the manufacturing difficulty of the back contact battery.

[0080] In terms of the depth of the recess, the depth of the first spacer region, the second spacer region and the second region respectively recessed into the silicon substrate on the backlight surface can be determined according to the actual application scenario, as long as it is ensured that the surface of the first spacer region and the surface of the second region are recessed into the silicon substrate relative to the surface of the first region, and the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region.

[0081] Specifically, the surfaces of the first spacer region and the second region can be offset along the thickness direction of the silicon substrate. Alternatively, as shown in FIG5 , the surface of the first spacer region 17 and the surface of the second region 15 can be flush. In this case, in the actual manufacturing process, as shown in FIG9 to FIG11 , after forming a full layer of the first doped semiconductor layer 12 on the backlight side, the first doped semiconductor layer 12 needs to be selectively etched. After the selective etching, the surfaces of the spacer region 16 and the second region 15 are both recessed inward relative to the surface of the first region 14, and the recesses are to the same depth. Based on this, when the surfaces of the first spacer region 17 and the second region 15 are flush, the surfaces of the first spacer region 17 and the second region 15 are recessed into the silicon substrate 11 to the same depth. In this case, it is not necessary to selectively etch the first spacer region 17 or the second region 15 after the first doped semiconductor layer 12 is selectively etched. This simplifies the manufacturing process of the back-contact cell and reduces the thickness of the silicon substrate 11, facilitating thin-film production.

[0082] As for the specific depth of the surface of the first spacer region recessed into the silicon substrate relative to the surface of the first region, illustratively, the depth can be greater than or equal to 500nm and less than or equal to 2500nm. For example, the depth of the surface of the first spacer region recessed into the silicon substrate can be 500nm, 1000nm, 1500nm, 2000nm or 2500nm, etc. In this case, the depth of the surface of the first spacer region recessed into the silicon substrate is within the above range, which can prevent the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, which are located on the backlight side of the silicon substrate and have a smaller degree of offset along the thickness direction of the silicon substrate due to the smaller depth, thereby further reducing the risk of leakage on the backlight side. In addition, in the actual manufacturing process, as shown in Figures 10 and 11, after a groove structure 22 is formed on the spacing region 16 and the second region 15 on the backlight side of the silicon substrate 11, which is recessed into the silicon substrate 11 relative to the surface of the first region 14, the end of the first doped semiconductor layer 12 adjacent to the spacing region 16 can be suspended, and the depth of the surface of the first spacer region 17 recessed into the silicon substrate 11 is the same as the depth of the groove structure 22. Based on this, the depth of the surface of the first spacer region 17 recessed into the silicon substrate 11 is within the above-mentioned range, which can also prevent the suspended end of the first doped semiconductor layer 12 from being affected by the etching solution for etching the silicon substrate 11 due to the large depth of the surface of the first spacer region 17 recessed into the silicon substrate 11, resulting in a shorter length of the end suspended on the spacer region 16 (thus resulting in a shorter length of the first spacer region 17), ensuring that the surface passivation layer 19 has a higher passivation effect on the spacer region 16; it can also prevent the need to use a thicker silicon substrate 11 due to the large depth of the surface of the first spacer region 17 recessed into the silicon substrate 11, thereby reducing the manufacturing cost of the back-contact battery while facilitating the thin-film production of the back-contact battery.

[0083] Exemplarily, the depth to which the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first region can be greater than or equal to 3 μm and less than or equal to 5 μm. For example, the depth to which the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first region can be greater than or equal to 3 μm and less than or equal to 5 μm. In this case, in the actual manufacturing process, after forming the first doped semiconductor layer and forming the groove structure on the second region and the spacer region, the second doped semiconductor layer is deposited on the backlight side and selectively etched. To prevent leakage, after removing the portion of the second doped semiconductor layer located on the second spacer region, etching is continued downward to a certain depth to ensure that the portion of the second doped semiconductor layer located on the second spacer region is completely removed. Based on this, the depth to which the surface of the second spacer region is recessed into the silicon substrate within the above range can prevent the high risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types due to the smaller depth, thereby ensuring that the back-contact battery has high electrical reliability. Furthermore, it is understood that the greater the depth of the second spacer region's surface recessed into the silicon substrate, the longer the etching time of the corresponding etching solution, and the greater the impact of the corresponding etching solution on other structures. Based on this, the depth of the second spacer region's surface recessed into the silicon substrate within the aforementioned range can also prevent the extended length of the first doped semiconductor layer's overhanging end and the first spacer region from being affected by the etching solution due to the greater depth, thereby ensuring that the surface passivation layer has a higher passivation effect on the spacer region. It can also prevent the need for a thicker silicon substrate due to the greater depth of the second spacer region's surface recessed into the silicon substrate, thereby reducing the manufacturing cost of the back-contact cell and facilitating the thin-film production of the back-contact cell.

[0084] In terms of morphology, as described above, the surface of the first spacer region can be a flat surface; the surface of the second spacer region can be a flat surface or a velvet surface. As described above, compared with the existing back-contact battery in which the spacer regions are all velvet, the flat surface has a smaller specific surface area, a thicker surface passivation layer, a higher surface passivation effect and fewer recombination centers, which is conducive to further reducing the recombination rate of carriers in the spacer region with a flat surface, and further improving the photoelectric conversion efficiency of the back-contact battery. It should be noted that when the surface of the second spacer region is a velvet surface, the depth of the surface of the second spacer region recessed into the silicon substrate refers to: along the thickness direction of the silicon substrate, the depth of the middle part of the velvet structure on the surface of the second spacer region recessed into the silicon substrate relative to the surface of the first region.

[0085] As for the sidewall morphology of the spacer region, each portion of the sidewall surface adjacent to the first doped semiconductor layer in the spacer region can be arranged perpendicular to the horizontal plane. Alternatively, as shown in Figures 2 to 5, among the sidewalls adjacent to the first doped semiconductor layer 12 in the above-mentioned spacer region 16, at least a portion of the sidewall surface is arranged at an angle relative to the horizontal plane, so that the cross-sectional area of ​​at least a portion of the spacer region 16 gradually increases from the light-facing side to the backlight side. In this case, the cross-sectional area of ​​the spacer region 16 close to the light-facing side is smaller than the cross-sectional area of ​​the spacer region 16 close to the backlight side, which is beneficial to increase the distance between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of the opposite conductivity type, reduce the leakage risk on the backlight side of the back contact battery, and ensure that the back contact battery has high electrical reliability. In addition, the portion of the side wall adjacent to the spacer region 16 and the first doped semiconductor layer 12 that is inclined to the horizontal plane is also beneficial for reflecting light, which allows more light to enter the silicon substrate 11 from the backlight side of the back contact cell under the reflection effect of the portion of the side wall adjacent to the spacer region 16 and the first doped semiconductor layer 12 that is inclined to the horizontal plane, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0086] In the above case, the angle between the portion of the side wall adjacent to the first doped semiconductor layer in the spacing region that is inclined relative to the horizontal plane and the horizontal plane can be determined based on the actual manufacturing process and the requirements for the reflection of light by the side wall of the groove structure, and is not specifically limited here.

[0087] Exemplarily, the angle between the portion of the sidewall of the spacer region adjacent to the first doped semiconductor layer that is tilted relative to the horizontal plane and the horizontal plane may be greater than or equal to 52° and less than or equal to 58°. For example, the angle between the portion of the sidewall of the spacer region adjacent to the first doped semiconductor layer that is tilted relative to the horizontal plane and the horizontal plane may be 52°, 53°, 54°, 55°, 56°, 57°, or 58°, etc. In this case, if the angle is within the above range, it can ensure that more light can enter the silicon substrate and be utilized by the silicon substrate due to the greater reflection effect of the portion of the sidewall of the spacer region adjacent to the first doped semiconductor layer that is tilted relative to the horizontal plane, thereby further improving the utilization rate of light by the back contact cell.

[0088] In addition, in the above case, as shown in Figures 2, 3 and 5, the surface of each portion of the side wall adjacent to the spacer region 16 and the first doped semiconductor layer 12 can be tilted relative to the horizontal plane. Alternatively, as shown in Figure 4, only a portion of the surface of the side wall adjacent to the spacer region 16 and the first doped semiconductor layer 12 is tilted relative to the horizontal plane, while the surface of the portion close to the backlight surface is perpendicular to the horizontal plane. In this case, another possible implementation scheme can be provided for the morphology of the portion adjacent to the first doped semiconductor layer 12 in the back contact battery provided in the embodiment of the present invention, which is beneficial to improving the applicability of the back contact battery provided in the embodiment of the present invention in different application scenarios.

[0089] The height of the surface perpendicular to the horizontal plane can be determined according to the actual manufacturing process and is not specifically limited here.

[0090] As for the morphology of the sidewalls of the spacer region adjacent to the second doped semiconductor layer, each portion of the surface of the sidewalls of the spacer region adjacent to the second doped semiconductor layer can be arranged perpendicular to the horizontal plane. Alternatively, as shown in FIG2 , the sidewalls of the spacer region 16 adjacent to the second doped semiconductor layer 13 can also be arranged obliquely to the horizontal plane.

[0091] Regarding the above-mentioned first doped semiconductor layer, in terms of materials, the material of the above-mentioned first doped semiconductor layer can be a semiconductor material such as silicon, silicon germanium, germanium or gallium arsenide. In terms of the arrangement of the material, the crystal phase of the first doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single crystal or polycrystalline, etc. In terms of conductivity type, the conductivity type of the first doped semiconductor layer can be opposite to the conductivity type of the silicon substrate, or it can be the same as the conductivity type of the silicon substrate. As for the thickness of the first doped semiconductor layer, it can be set according to actual needs and is not specifically limited here. For example, the thickness of the first doped semiconductor layer can be greater than or equal to 100nm and less than or equal to 500nm.

[0092] In actual applications, the first doped semiconductor layer can be formed directly on the first region of the silicon substrate. Alternatively, as shown in FIG5 , the back-contact cell further includes a first passivation layer 20 located between the first region 14 of the silicon substrate 11 and the first doped semiconductor layer 12. In this case, the first passivation layer 20 and the first doped semiconductor layer 12 can form a selective contact structure to chemically passivate the first region 14 on the backlight side of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0093] Specifically, the material of the first passivation layer can be determined according to the material of the first doped semiconductor layer and the type of the selective contact structure composed of the first passivation layer and the first doped semiconductor layer in actual application scenarios, and is not specifically limited here.

[0094] For example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure, the first doped semiconductor layer is a doped polysilicon layer, and the first passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include silicon oxide, aluminum oxide, or titanium oxide.

[0095] For another example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a heterogeneous contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0096] The thickness of the first passivation layer can be set according to actual needs and is not specifically limited here. For example, the thickness of the first passivation layer can be greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0097] For the second doped semiconductor layer, the material and thickness of the second doped semiconductor layer may refer to the material and thickness of the first doped semiconductor layer described above, and will not be repeated here.

[0098] In addition, in actual applications, the second doped semiconductor layer can be formed directly on the second region of the silicon substrate. Alternatively, as shown in Figure 5, the back-contact cell also includes a second passivation layer 21 located between the second region 15 of the silicon substrate 11 and the second doped semiconductor layer 13. In this case, the second passivation layer 21 and the second doped semiconductor layer 13 can form a selective contact structure to chemically passivate the second region 15 of the backlight side of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0099] Specifically, the material of the second passivation layer can be determined according to the material of the second doped semiconductor layer and the type of the selective contact structure composed of the second passivation layer and the second doped semiconductor layer in actual application scenarios, and is not specifically limited here.

[0100] For example, when the selective contact structure formed by the second passivation layer and the second doped semiconductor layer is a tunneling passivation contact structure, the second doped semiconductor layer is a doped polysilicon layer, and the second passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include silicon oxide, aluminum oxide, or titanium oxide.

[0101] For another example, when the selective contact structure formed by the second passivation layer and the second doped semiconductor layer is a heterogeneous contact structure, the second doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the second passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0102] The surface passivation layer may be made of any insulating material having a passivating effect, such as silicon oxide, aluminum oxide, or silicon nitride. The thickness of the surface passivation layer may be determined according to the actual application scenario and is not specifically limited here.

[0103] In a second aspect, embodiments of the present invention provide a method for manufacturing a back-contact battery. The manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 6 to 19. Specifically, the method for manufacturing a back-contact battery includes the following steps:

[0104] First, a silicon substrate is provided. On one side of the backlight surface of the silicon substrate, a spacer region is formed, comprising first and second regions alternately spaced parallel to the silicon substrate, and a region between the first region and the adjacent second region. Along the arrangement direction of the first and second regions, the region adjacent to the first region in the spacer region is the first spacer sub-region, and the remaining region is the second spacer sub-region.

[0105] Specifically, the ranges of the first region, the second region, and the first spacer sub-region and the second spacer sub-region included in the spacer region on the backlight side can be referred to above and will not be repeated here.

[0106] Next, as shown in FIG11 , a first doped semiconductor layer 12 is formed on the first region 14 and the first spacer region 17. Furthermore, a recessed groove structure 22 is formed in the spacer region 16 and the second region 15, recessed into the silicon substrate 11, so that the end of the first doped semiconductor layer 12 adjacent to the spacer region 16 is suspended. The bottom of the recessed groove structure 22 is a flat surface.

[0107] In an actual manufacturing process, as shown in FIG9 , after providing a silicon substrate 11, a first doped semiconductor layer 12 can be formed entirely on the backlight surface of the silicon substrate 11, and a second mask layer 24 can be disposed on the portion of the first doped semiconductor layer 12 located in the first region 14 and the first spacer region 17. Next, as shown in FIG10 , under the masking action of the second mask layer 24, the portion of the first doped semiconductor layer 12 located in the second spacer region 18 and the second region 15 is selectively removed, thereby obtaining the overhanging end portion of the first doped semiconductor layer 12 relative to the first spacer region 17. Next, as shown in FIG11 , under the masking action of the second mask layer 24, a groove structure 22 is formed in the spacer region 16 and the second region 15.

[0108] The material and thickness of the first doped semiconductor layer can be referenced above. Regarding the second mask layer, the material of the second mask layer can be any material that can function as a mask and is not specifically limited here. Furthermore, the specific materials used for the first doped semiconductor layer and the second mask layer can determine the specific process for forming the doped semiconductor layer and the second mask layer.

[0109] For example, when the material of the first doped semiconductor layer comprises silicon, the steps of forming the first doped semiconductor layer as a whole layer on the backlit surface of the silicon substrate and providing a second mask layer on the portion of the first doped semiconductor layer located in the first region and the first spacer region may include the following steps: As shown in FIG6 , a first intrinsic semiconductor layer 25 is formed as a whole layer on the backlit surface of the silicon substrate 11. Next, as shown in FIG7 , the first intrinsic semiconductor layer 25 is doped to form the first doped semiconductor layer 12, and a first doped silicon glass layer 26 is formed as a whole layer on the first doped semiconductor layer 12. Next, as shown in FIG8 , the portion of the first doped silicon glass layer located in the second spacer region 18 and the second region 15 is heat-treated using a laser etching process to form a second mask layer 24 on the portion of the first doped silicon glass layer that has not been heat-treated (i.e., the portion located in the first region and the first spacer region). Then, as shown in FIG9 , the heat-treated portion of the first doped silicon glass layer is removed.

[0110] Specifically, the material of the first doped semiconductor layer includes silicon, which may mean that the material of the first doped semiconductor layer only includes silicon; or it may also mean that the material of the first doped semiconductor layer includes both silicon and other semiconductor materials such as germanium silicon. Secondly, in the actual manufacturing process, chemical vapor deposition and other processes can be used to form a first intrinsic semiconductor layer that is arranged on the backlight side as a whole layer. Next, the first intrinsic semiconductor layer can be doped using diffusion and other processes. After the above-mentioned doping treatment, not only the first doped semiconductor layer can be obtained, but also a first doped silicon glass layer that is arranged as a whole layer on the first doped semiconductor layer can be formed. Then, a laser etching process is used to heat-treat part of the first doped silicon glass layer. At this time, as shown in Figure 8, the density of the laser-treated portion of the first doped silicon glass layer becomes poor, and it is easy to be removed. The portions of the first doped silica glass layer that have not been laser-treated are denser and less easily removed. Consequently, after heat treatment, different portions of the first doped silica glass layer have different etching selectivities, resulting in a second mask layer 24 for patterning the first doped semiconductor layer 12. This eliminates the need for forming additional mask materials or performing additional mask deposition processes to obtain the second mask layer 24 located on the first region and the first spacer region, thereby reducing the manufacturing cost of back-contact cells and simplifying the manufacturing process for back-contact cells. The specific conditions of the laser etching process can be set based on the actual application scenario and are not specifically limited here.

[0111] For example, the laser used in the laser etching process may be a nanosecond laser, a picosecond laser, or a femtosecond laser, etc. The laser etching process may have a power greater than or equal to 10W and less than or equal to 100W, and the diameter of the laser spot may be greater than or equal to 50 μm and less than or equal to 300 μm.

[0112] Of course, when the material of the first doped semiconductor layer includes silicon, or when the material of the first doped semiconductor layer does not include silicon, chemical vapor deposition and doping processes can also be used to form the first doped semiconductor layer disposed entirely on the backlight side. Then, chemical vapor deposition and etching processes can be used to form a mask layer made of other materials such as silicon nitride that have a masking function.

[0113] Furthermore, after forming the second mask layer, a wet chemical process or other process can be employed, and under the masking action of the mask layer, the portion of the first doped semiconductor layer located above the second spacer region and the second region can be selectively removed. A recessed structure recessed into the silicon substrate relative to the surface of the first region is formed in the spacer region and the second region. This prevents damage to the silicon substrate caused by the high-temperature laser and improves the yield of the back-contact cell. Furthermore, when forming the recessed structure using a wet chemical process, since the wet chemical etching solution etches the silicon substrate in a generally isotropic manner, this facilitates increasing the length of the suspended end portion of the first doped semiconductor layer, thereby facilitating the formation of a flat surface in the first spacer region.

[0114] Specifically, the process conditions for selectively etching the first doped semiconductor layer can be determined according to the adopted etching process, the material of the first doped semiconductor layer, and the specifications of the formed groove structure, etc., and are not specifically limited here.

[0115] For example, when a wet chemical process is used to form the groove structure in the spacer region and the second region under the masking action of the second mask layer, the process temperature of the wet chemical process can be greater than or equal to 61°C and less than or equal to 83°C. In addition, the process time of the wet chemical process can be greater than or equal to 60 seconds and less than or equal to 450 seconds. Secondly, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (such as NaOH or KOH) in the alkaline wet chemical etching solution is greater than or equal to 1% and less than or equal to 15%. For example, the process temperature of the wet chemical process can be 61°C, 70°C, 75°C, 80°C, or 83°C. The process time of the wet chemical process can be 60 seconds, 100 seconds, 200 seconds, 300 seconds, 400 seconds, or 450 seconds. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution can be 1%, 3%, 6%, 9%, 12%, or 15%, etc. In this case, the process temperature and process time of the wet chemical process will affect the specifications of the groove structure formed by the wet chemical process and the specifications of the suspended end portion of the first doped semiconductor layer. Therefore, if the process temperature of the wet chemical process is within the above range, the depth of the groove structure, the height and length of the suspended end portion of the first doped semiconductor layer, and the length thereof can be prevented from being reduced due to a low process temperature. Furthermore, the depth of the groove structure can be prevented from being increased due to a high process temperature. The depth of the groove structure is equal to the depth of the first spacer region recessed into the silicon substrate. The beneficial effects of preventing the depth of the groove structure, the height and length of the suspended end portion of the first doped semiconductor layer from being reduced, and preventing the depth of the groove structure from being increased can be found in the above description. Secondly, the beneficial effects of the process time and the volume ratio of the alkaline component within the above ranges are similar to the beneficial effects of the process temperature being greater than or equal to 65° C. and less than or equal to 85° C., and will not be repeated here.

[0116] In addition, polishing additives can be added to the wet chemical etching solution to improve the surface flatness of the bottom of the groove structure formed, and further improve the passivation effect of the surface passivation layer on the spacing area. Specifically, the composition of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution can be determined according to the actual application scenario, and are not specifically limited here. For example, the polishing additive may include sodium benzoate, a defoaming agent, and a surfactant. The volume ratio of the polishing additive in the wet chemical etching solution may be greater than or equal to 0.5% and less than or equal to 3%.

[0117] It should be noted that when the manufactured back-contact battery also includes a first passivation layer located between the first region and the first doped semiconductor layer, the manufacturing method of the back-contact battery also includes: after the step of providing a silicon substrate and before the step of forming the first doped semiconductor layer on the first region and the first spacer region, a deposition and etching process is used to form a first passivation layer on the first region and the first spacer region.

[0118] Alternatively, as shown in FIG6 , after providing the silicon substrate 11, a process such as chemical vapor deposition can be used to form a first passivation layer 20 disposed entirely on the backlight side. Then, as shown in FIG9 and FIG10 , after forming a second mask layer 24 and selectively etching the first doped semiconductor layer 12 under the masking action of the second mask layer 24, the first passivation layer 20 is selectively etched. In this case, there is no need to form an additional mask layer to form the first passivation layer 20 between the first region 14 and the first doped semiconductor layer 12, simplifying the manufacturing process of the back-contact cell.

[0119] Next, after the groove structure is formed, as shown in FIG12 , a second doped semiconductor layer 13 is deposited on the first doped semiconductor layer 12 and in the groove structure 22 ; and as shown in FIG15 , a first mask layer 23 is formed on the portion of the second doped semiconductor layer 13 located in the second region 15 .

[0120] Specifically, the material and thickness of the second doped semiconductor layer can be found in the previous section and will not be further described here. As for the first mask layer, its material can be any material that can function as a mask. In actual manufacturing, the formation process and specific steps of the second doped semiconductor layer and the second mask layer can be determined based on the materials of the second doped semiconductor layer and the second mask layer.

[0121] For example, when the material of the second doped semiconductor layer includes silicon, the steps of depositing the second doped semiconductor layer on the first doped semiconductor layer and within the recessed structure, and forming a first mask layer on the portion of the second doped semiconductor layer located in the second region, may include the following steps: as shown in FIG12 , depositing a second intrinsic semiconductor layer 27 on the first doped semiconductor layer 12 and within the recessed structure 22. Next, as shown in FIG13 , the second intrinsic semiconductor layer is doped to form a second doped semiconductor layer 13, and a second doped silica glass layer 28 is formed entirely on the second doped semiconductor layer 13. Next, as shown in FIG14 , the portions of the second doped silica glass layer located in the first region 14 and the spacer region 16 are heat-treated using a laser etching process to form the first mask layer 23 on the portion of the second doped silica glass layer located in the second region 15 (i.e., the portion that has not been heat-treated). Then, as shown in FIG15 , the heat-treated portion of the second doped silica glass layer is removed.

[0122] Specifically, the material of the second doped semiconductor layer includes silicon, which may mean that the material of the second doped semiconductor layer only includes silicon; or it may also mean that the material of the second doped semiconductor layer includes both silicon and other semiconductor materials such as germanium silicon. Secondly, in the actual manufacturing process, chemical vapor deposition and other processes can be used to form a second intrinsic semiconductor layer that is arranged on the backlight side as a whole layer. Next, the second intrinsic semiconductor layer can be doped using diffusion and other processes. After the above-mentioned doping treatment, not only the second doped semiconductor layer can be obtained, but also a second doped silicon glass layer that is arranged as a whole layer can be formed on the second doped semiconductor layer. Then, a laser etching process is used to heat-treat the portion of the second doped silicon glass layer located in the first region and the spacing region. At this time, the density of the laser-treated portion of the second doped silicon glass layer becomes poorer, and it is easy to be removed. The portion of the second doped silica glass layer located in the second region is not laser-treated and has a high density, making it difficult to remove. Consequently, after heat treatment, different portions of the second doped silica glass layer have different etching selectivities, thereby obtaining a first mask layer for patterning the second doped semiconductor layer. This eliminates the need to form additional mask materials or perform additional mask deposition steps to obtain the first mask layer located in the second region, thereby reducing the manufacturing cost of back-contact cells and simplifying the manufacturing process for back-contact cells. The specific conditions of the aforementioned laser etching process can be found in the previous section and are not specifically limited here.

[0123] Of course, when the material of the second doped semiconductor layer includes silicon, or when the material of the second doped semiconductor layer does not include silicon, chemical vapor deposition and doping processes can also be used to form a whole second doped semiconductor layer disposed on the backlight side. Then, chemical vapor deposition and etching processes can be used to form a first mask layer made of other materials such as silicon nitride that have a masking function.

[0124] Next, as shown in Figure 16, under the masking action of the first mask layer 23, the portion of the second doped semiconductor layer 13 located on the first region 14 and the spacer region 16 is selectively removed, and the surface of the second spacer region 18 is recessed into the silicon substrate 11 relative to the surface of the first spacer region 17.

[0125] In actual manufacturing, a wet chemical process or other process can be employed, and under the masking action of the first mask layer, the portion of the second doped semiconductor layer located on the first region and the spacer region can be selectively removed. Furthermore, the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region. This prevents damage to the silicon substrate caused by the high-temperature laser, thereby improving the yield of the back-contact cell. Specifically, the process conditions for the above-described operation can be determined based on the etching process used, the material of the second doped semiconductor layer, and the depth to which the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region, and are not specifically limited herein.

[0126] For example, when a wet chemical process is used, and under the masking action of the first mask layer, the portion of the second doped semiconductor layer located on the first region and the spacer region is selectively removed, and the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region to form a textured surface, the process temperature of the wet chemical process can be greater than or equal to 61°C and less than or equal to 83°C. Furthermore, the process time of the wet chemical process can be greater than or equal to 100 seconds and less than or equal to 500 seconds. Furthermore, the wet chemical etching solution used in the wet chemical process can be an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (such as NaOH or KOH) in the alkaline wet chemical etching solution can be greater than or equal to 1% and less than or equal to 3.5%. For example, the process temperature of the wet chemical process can be 61°C, 70°C, 75°C, 80°C, or 83°C. The process time of the wet chemical process can be 100 seconds, 200 seconds, 300 seconds, 400 seconds, or 500 seconds. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution can be 1%, 1.5%, 2%, 2.5%, 3%, or 3.5%, etc. In this case, the process temperature and process time of the wet chemical process both affect the depth to which the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region during the wet chemical process. Therefore, keeping the process temperature of the wet chemical process within the above range can prevent the surface of the second spacer region from recessing into the silicon substrate to a smaller depth relative to the surface of the first spacer region due to a lower process temperature. Furthermore, it can also prevent the surface of the second spacer region from recessing into the silicon substrate to a greater depth relative to the surface of the first spacer region due to a higher process temperature. The beneficial effects of preventing the surface of the second spacer region from recessing into the silicon substrate to a smaller or greater depth relative to the surface of the first spacer region can be found in the previous description. Furthermore, the beneficial effects of keeping the process time and the volume ratio of the alkaline component within the above range are similar to those of keeping the process temperature greater than or equal to 61°C and less than or equal to 83°C, and will not be further elaborated here.

[0127] In addition, as shown in Figure 16, under the masking action of the first mask layer 23, the surface of the second spacer region 18 is recessed into the silicon substrate 11 relative to the surface of the first spacer region 17, and the surface of the second spacer region 18 can also be textured. In this case, the formation of a velvet surface on the surface of the second spacer region can be achieved by adding a texturing additive to the wet chemical etching solution used in the above-mentioned wet chemical process. Specifically, the type of the above-mentioned texturing additive and the volume ratio of the texturing additive in the wet chemical etching solution can be determined according to the size of the velvet structure and the actual application scenario. For example: the texturing additive may include sodium benzoate, a defoaming agent, a surfactant, and the like. The volume ratio of the texturing additive in the wet chemical etching solution may be greater than or equal to 0.5% and less than or equal to 2%. In this case, the volume ratio of the texturing additive within the above range can prevent the need to use a thicker silicon substrate to manufacture the back contact cell due to the relatively large volume, which is conducive to the realization of thin-film production; it can also prevent the relatively small volume from resulting in the velvet structure formed on the surface of the second spacer region being small in size, resulting in an unsatisfactory light trapping effect on the surface of the second spacer region, ensuring that more light can be refracted into the silicon substrate through the surface of the second spacer region, further improving the photoelectric conversion efficiency of the back contact cell.

[0128] It should be noted that the above-mentioned texturing additive and polishing additive may have the same composition, but have different effects under different process times, process temperatures and different volume ratios.

[0129] It should be noted that when the manufactured back-contact cell also includes a second passivation layer located between the second region and the second doped semiconductor layer, the second passivation layer can be deposited on the first doped semiconductor layer and within the groove structure after forming a groove structure recessed into the silicon substrate in the spacer region and the second region, and before depositing the second doped semiconductor layer on the first doped semiconductor layer and within the groove structure. As shown in Figure 15, the second passivation layer 21 is deposited on the first doped semiconductor layer 12 and within the groove structure 22. Specifically, the second passivation layer 21 can be formed using a process such as chemical vapor deposition. The material and thickness of the second passivation layer 21 can be referred to above.

[0130] Specifically, after the step of selectively removing the portion of the second doped semiconductor layer located on the first region and the spacer region under the masking action of the first mask layer, and before the step of recessing the surface of the second spacer region into the silicon substrate relative to the surface of the first spacer region, the portion of the second passivation layer located on the first region and the spacer region under the masking action of the first mask layer is selectively removed under the masking action of the first mask layer. As shown in Figures 18 and 19, a wet chemical process or other process can be used, and the portion of the second passivation layer 21 located on the first region 14 and the spacer region 16 can be selectively removed under the masking action of the first mask layer 23.

[0131] Next, as shown in FIG. 17 and FIG. 18 , the suspended end portion of the first doped semiconductor layer 12 is removed; and the first mask layer is removed.

[0132] Specifically, ultrasonic cleaning or other methods can be used to remove the suspended end portion of the first doped semiconductor layer. The process conditions for this ultrasonic cleaning method can be determined based on the specifications of the suspended end portion of the first doped semiconductor layer, the material of the first doped semiconductor layer, and actual needs, and are not specifically limited here. For example, the ultrasonic frequency can be greater than 30 kHz, and the cleaning temperature can be greater than or equal to 20°C and less than or equal to 80°C.

[0133] Next, the first mask layer can be removed using a wet chemical process or other similar process. Furthermore, the present invention does not specifically limit the order of removing the first mask layer and removing the overhanging end portion of the first doped semiconductor layer. The overhanging end portion of the first doped semiconductor layer can be removed after the first mask layer. Alternatively, the overhanging end portion of the first doped semiconductor layer can be removed first, followed by the first mask layer.

[0134] 19 , a surface passivation layer 19 is formed covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacer region 16. Specifically, the surface passivation layer 19 can be formed by processes such as physical vapor deposition or chemical vapor deposition. The material and thickness of the surface passivation layer 19 can be referred to above.

[0135] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0136] In addition, the present invention also provides a comparative example and an example to illustrate the manufacturing process and working performance of the back-contact battery provided by the present invention. Table 1 shows the test results of the back-contact battery corresponding to Example 1 and Comparative Example 1.

[0137] Example 1

[0138] In the first step, the single crystal silicon wafer is subjected to alkaline polishing treatment using an alkaline solution having a concentration of 15% to form a smooth and clean silicon surface.

[0139] In the second step, a tunnel oxide layer and an intrinsic polysilicon layer are sequentially deposited on the surface of the single crystal silicon wafer, wherein the thickness of the tunnel oxide layer is 1.8 nm and the thickness of the intrinsic polysilicon layer is 350 nm.

[0140] The third step is to perform boron doping on the deposited intrinsic polysilicon layer to form a P-type doped polysilicon layer; and to form a borosilicate glass layer on the P-type doped polysilicon layer. The boron doping concentration is 8×10 19 / cm 3 .

[0141] The fourth step is to heat-treat the borosilicate glass layer using a laser etching process to prepare a mask layer with a specific pattern. The laser can be a picosecond laser with a processing power of 40W and a spot diameter of 200μm.

[0142] In the fifth step, under the masking action of the mask layer, a portion of the P-type doped polysilicon layer is selectively removed. The single-crystal silicon wafer is then surface-etched to form a groove structure, with the ends of the P-type doped polysilicon layer adjacent to the groove structure left suspended. The etching solution used mainly consists of alkali and polishing additives. The alkali concentration in the etching solution is 5%, the etching temperature is 82°C, the process time is 300 seconds, the volume ratio of the polishing additive is 2%, and the main components of the polishing additive include sodium benzoate, a defoaming agent, and a surfactant.

[0143] Step 6: Form a tunnel oxide layer and an N-type doped polysilicon layer stacked in sequence at the bottom of the groove structure. The N-type doped polysilicon layer has a thickness greater than or equal to 150 nm and less than or equal to 180 nm. The tunnel oxide layer has a thickness greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0144] Step 7: Texturing the portion of the backlight surface located between the N-type doped polysilicon layer and the P-type doped polysilicon layer. (It should be noted that this embodiment 1 is described using the portion of the backlight surface located between the N-type doped polysilicon layer and the P-type doped polysilicon layer (i.e., the second spacer region described above) as a texturing surface as an example. This does not mean that the portion of the backlight surface located between the N-type doped polysilicon layer and the P-type doped polysilicon layer can only have a texturing surface. When the portion of the backlight surface located between the N-type doped polysilicon layer and the P-type doped polysilicon layer has a flat surface, the corresponding operation of Step 7 can be omitted.)

[0145] Step 8: Remove the suspended end portion of the P-type doped polysilicon layer.

[0146] Comparative Example 1

[0147] The manufacturing method corresponding to Comparative Example 1 is identical to the manufacturing process of Example 1, except for steps 4, 5, and 8. In the manufacturing method provided in Comparative Example 1, after the deposited intrinsic polysilicon layer is subjected to boron doping, and before forming a tunneling oxide layer and an N-type doped polysilicon layer stacked in sequence at the bottom of the groove structure, the borosilicate glass layer is removed, and the formed tunneling oxide layer and doped polysilicon layer are selectively etched using a laser etching process, thereby forming a groove structure with sidewalls perpendicular to the horizontal plane in the silicon substrate.

[0148] Table 1 Test results of back contact cells corresponding to Example 1 and Comparative Example 1

[0149] It can be seen from the data shown in Table 1 that in the back-contact battery formed by the manufacturing method provided in Example 1, the surface passivation layer has a better passivation effect on the spacer area, so the working efficiency, open-circuit voltage, short-circuit current and fill factor of the back-contact battery obtained by the corresponding manufacturing method of Comparative Example 1 are higher, that is, the back-contact battery provided by the embodiment of the present invention has higher working performance.

[0150] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0151] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A back contact battery, characterized in that: include: Silicon substrate; A first doped semiconductor layer and a second doped semiconductor layer are alternately distributed on a side of a backlight surface of the silicon substrate in a direction parallel to the silicon substrate; The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; On the backlight side of the silicon substrate, the area corresponding to the first doped semiconductor layer is the first area, the area corresponding to the second doped semiconductor layer is the second area, and the area between the first area and the second area adjacent to the first area is the spacing area; Along the arrangement direction of the first region and the second region, in the spacer region, the region adjacent to the first doped semiconductor layer is a first spacer sub-region, and the remaining region is a second spacer sub-region; the surface of the first spacer sub-region and the surface of the second region are both recessed into the silicon substrate relative to the surface of the first region, and the surface of the second spacer sub-region is recessed into the silicon substrate relative to the surface of the first spacer sub-region; the surface of the first spacer sub-region is a flat surface; and a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacer region.

2. The back contact battery according to claim 1, characterized in that Along the arrangement direction of the first region and the second region, the length of the spacing region is greater than or equal to 20 μm and less than or equal to 110 μm; and / or, Along the arrangement direction of the first region and the second region, the length of the first spacer region is greater than or equal to 1000 nm and less than or equal to 3000 nm.

3. The back contact battery according to claim 1, characterized in that The surface of the first spacer region is flush with the surface of the second region; and / or, A depth by which a surface of the first spacer region is recessed into the silicon substrate relative to a surface of the first region is greater than or equal to 500 nm and less than or equal to 2500 nm.

4. The back contact battery according to claim 1, characterized in that The surface of the second spacer region is a suede surface; and / or, A depth of a surface of the second spacer region recessed into the silicon substrate relative to a surface of the first region is greater than or equal to 3 μm and less than or equal to 5 μm.

5. The back contact battery according to claim 1, characterized in that At least a portion of the sidewall surface of the spacer region adjacent to the first doped semiconductor layer is inclined relative to a horizontal plane, so that the cross-sectional area of at least a portion of the spacer region gradually increases from the light-facing surface to the backlight surface; and / or, In the sidewall of the spacing region adjacent to the first doped semiconductor layer, a sidewall surface of a portion close to the backlight surface is arranged perpendicular to a horizontal plane.

6. The back contact battery according to claim 1, characterized in that The back contact cell further includes a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer; and / or, The back-contact cell further includes a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

7. The back contact battery according to claim 6, characterized in that In the case where the back contact cell includes the first passivation layer, and the first passivation layer is a tunneling passivation layer, the first doped semiconductor layer is a doped polysilicon layer; and / or, In the case that the back contact cell includes the second passivation layer, and the second passivation layer is a tunneling passivation layer, the second doped semiconductor layer is a doped polysilicon layer.

8. A method for manufacturing a back contact battery, characterized in that: The following steps are involved: A silicon substrate is provided; a backlight side of the silicon substrate has a first region and a second region alternately spaced and distributed in a direction parallel to the silicon substrate, and a spacing region between the first region and the second region adjacent to the first region; Along the arrangement direction of the first region and the second region, in the spacing region, the region adjacent to the first region is the first spacing sub-region, and the remaining region is the second spacing sub-region; forming a first doped semiconductor layer on the first region and the first spacer region; and forming a groove structure recessed into the silicon substrate on the spacer region and the second region, so that an end portion of the first doped semiconductor layer adjacent to the spacer region is suspended; The bottom of the groove structure is a flat surface; depositing a second doped semiconductor layer on the first doped semiconductor layer and in the groove structure, and forming a first mask layer on a portion of the second doped semiconductor layer located in the second region; Under the masking effect of the first mask layer, selectively removing the portion of the second doped semiconductor layer located on the first region and the spacer region, and causing the surface of the second spacer region to be recessed into the silicon substrate relative to the surface of the first spacer region; removing the suspended end portion of the first doped semiconductor layer; and removing the first mask layer; A surface passivation layer is formed covering the first doped semiconductor layer, the second doped semiconductor layer and the spacer region.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that: After providing the silicon substrate and before depositing the second doped semiconductor layer on the first doped semiconductor layer and in the groove structure, the method for manufacturing a back contact battery further includes the following steps: forming a first doped semiconductor layer in its entirety on the backlight surface of the silicon substrate, and disposing a second mask layer on a portion of the first doped semiconductor layer located in the first region and the first spacer region; Under the masking effect of the second mask layer, selectively removing the portion of the first doped semiconductor layer located on the second spacer region and the second region; Under the masking effect of the second mask layer, the groove structure is formed on the spacer region and the second region.

10. The method for manufacturing a back contact battery according to claim 9, wherein: The material of the first doped semiconductor layer includes silicon; The steps of forming a first doped semiconductor layer in its entirety on the backlight surface of the silicon substrate, and providing a second mask layer on a portion of the first doped semiconductor layer located in the first region and the first spacer region include: forming a first intrinsic semiconductor layer on the backlight surface of the silicon substrate; performing a doping treatment on the first intrinsic semiconductor layer so that the first intrinsic semiconductor layer forms the first doped semiconductor layer, and forming a first doped silicon glass layer entirely disposed on the first doped semiconductor layer; Using a laser etching process, heat-treating portions of the first doped silicon glass layer located in the second spacer region and the second region, so that portions of the first doped silicon glass layer that have not been heat-treated form the second mask layer; The heat-treated portion of the first doped silicon glass layer is removed.

11. The method for manufacturing a back contact battery according to claim 9, wherein: The groove structure is formed on the spacer region and the second region by using a wet chemical process and under the masking effect of the second mask layer; wherein, The process temperature of the wet chemical process is greater than or equal to 61°C and less than or equal to 83°C; and / or, the process time of the wet chemical process is greater than or equal to 60s and less than or equal to 450s; and / or, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 1% and less than or equal to 15%; and / or, the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 3%.

12. The method for manufacturing a back contact battery according to claim 8, wherein: Under the masking effect of the first mask layer, the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region, and the surface of the second spacer region is textured.

13. The method for manufacturing a back contact battery according to any one of claims 8 to 12, characterized in that: The material of the second doped semiconductor layer includes silicon; The step of depositing a second doped semiconductor layer on the first doped semiconductor layer and in the groove structure, and forming a first mask layer on a portion of the second doped semiconductor layer located in the second region comprises: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer and in the recessed structure; performing a doping treatment on the second intrinsic semiconductor layer so that the second intrinsic semiconductor layer forms a second doped semiconductor layer, and forming a second doped silicon glass layer entirely disposed on the second doped semiconductor layer; Using a laser etching process, heat-treating the portion of the second doped silicon glass layer located in the first region and the spacer region, so that the portion of the second doped silicon glass layer located in the second region forms the first mask layer; The heat-treated portion of the second doped silicon glass layer is removed.

14. The method for manufacturing a back contact battery according to any one of claims 8 to 12, characterized in that: A wet chemical process is used, and under the masking action of the first mask layer, the portion of the second doped semiconductor layer located on the first region and the spacer region is selectively removed, and the surface of the second spacer region is recessed into the silicon substrate relative to the surface of the first spacer region; wherein, The process temperature of the wet chemical process is greater than or equal to 61°C and less than or equal to 83°C; and / or, the process time of the wet chemical process is greater than or equal to 100s and less than or equal to 500s; and / or, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 1% and less than or equal to 3.5%; and / or, the wet chemical etching solution used in the wet chemical process contains a texturing additive, and the volume ratio of the texturing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 2%.

15. The method for manufacturing a back contact battery according to any one of claims 8 to 12, characterized in that: The manufacturing method of the back-contact battery also includes forming a first passivation layer, which includes the following steps: after the step of providing a silicon substrate, before the step of forming a first doped semiconductor layer on the first region and the first spacer region, forming a first passivation layer on the first region and the first spacer region.

16. The method for manufacturing a back contact battery according to any one of claims 8 to 12, characterized in that: The method for manufacturing a back-contact cell further includes forming a second passivation layer between the second region and the second doped semiconductor layer, which includes the following steps: After the step of forming a recessed structure recessed into the silicon substrate on the spacer region and the second region, and before the step of depositing the second doped semiconductor layer on the first doped semiconductor layer and in the recessed structure, a second passivation layer is deposited on the first doped semiconductor layer and in the recessed structure; After the step of selectively removing the portion of the second doped semiconductor layer located on the first region and the spacer region under the masking action of the first mask layer, and before the step of making the surface of the second spacer region concave into the silicon substrate relative to the surface of the first spacer region, the portion of the second passivation layer located on the first region and the spacer region is selectively removed under the masking action of the first mask layer.

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