Electronic circuits for acquiring the threshold voltage of a power transistor

Abstract

The invention relates to a device (10, 20) for monitoring the state of health of a power transistor, comprising: - means (8) for applying an ultra-slow triggering voltage (VGS) to this transistor; - means (12-22) for measuring the dip in gate voltage (VGS) that follows the Miller plateau.

Description

[0001] Description

[0002] Title: ELECTRONIC CIRCUITS FOR ACQUIRING THE THRESHOLD VOLTAGE OF A

[0003] POWER TRANSISTOR

[0004] TECHNICAL FIELD AND PRIOR ART

[0005] The invention relates to the field of power electronics, and in particular that of electrification and electric power hybridization in general and particularly in aeronautics.

[0006] In this context, there is a need for high-performance, integrated, reliable and secure power electronic systems. The power module for motor control is a key function on which significant efforts must be concentrated. The introduction of wide-gap power semiconductor components such as the silicon carbide (SiC) MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) within the power module has made it possible to reduce the on-board mass and volume by 15 to 30% and increase electrical efficiency by 2 to 3 points.

[0007] SiC MOSFETs are power semiconductor devices that offer many advantages, such as high performance, increased energy efficiency, and improved high-temperature resistance compared to traditional silicon (Si) MOSFETs. However, their adoption in the aerospace industry still presents certain challenges that limit their maturity and widespread deployment.

[0008] In particular, there are no means of monitoring the reliability of these transistors in continuous operation and in a non-intrusive manner. The same problem arises more generally for semiconductor transistors based on wide-gap semiconductors, such as GaN technology. By "wide gap", we mean an energy gap or a height of the band gap Eg separating the last occupied states of the valence band and the first free states of the conduction band, which is larger than for silicon. The same problem also arises for MOSFETs made of traditional silicon (Si). However, monitoring the health of such a transistor, especially a wide-gap one, especially a SiC MOSFET, is a major challenge for its adoption in applications with high reliability and long potential lifetimes, such as aeronautics.Indeed, during its operation within a power converter, performance drops linked to the aging of the component may appear. These performance degradations result from variations in intrinsic physical parameters, particularly in the case of a SiC MOSFET, linked to electrical charge trapping phenomena, for example, in the case of a SiC MOSFET, within the silicon dioxide (SiO?) gate oxide layer in the presence of defects at the interface with the SiC substrate.

[0009] These effects are even more marked in SiC technology than in Si technology given the lower quality of production of the gate oxide layer which is itself, in parallel, subjected to greater stress in the electric field on SiC MOSFET.

[0010] Indeed, in a silicon MOSFET, the gate oxide (SiO?) is generally well-matched to the silicon crystal structure. Silicon and silicon dioxide have a natural chemical affinity, which facilitates the growth of a native, uniform, and low-deficiency gate oxide layer. In contrast, silicon carbide (SiC) has a different and more complex crystal structure compared to silicon. Growing a high-quality gate oxide layer on SiC is more difficult due to the less natural nature of the interface between SiC and SiO?.

[0011] Crystal defects in the gate oxide layer of Si MOSFETs are generally less frequent and more stable. Manufacturing technologies for SiO on Si are highly developed, allowing for the production of high-quality oxide layers with few defects. In the case of SiC MOSFETs, the growth of gate oxide on SiC may be more prone to the formation of defects. These defects can include oxygen vacancies, structural imperfections, and recombination sites. They can be caused by differences in atomic mobility between SiC and SiO, thermal stresses during the manufacturing process, and other factors. All of these defects can give rise to charge traps in the gate oxide. This tunneling can occur either at the surface, at the SiC / SiO interface, or deeper in the bulk of the oxide.Tunneling is a quantum process that allows electrons to "tunnel" through an energy barrier that, conventionally in silicon, would be too high for them to pass through. In the context of SiC MOSFETs, tunneling occurs when channel electrons, under the influence of the gate voltage, acquire enough kinetic energy to pass through the thin gate oxide layer and become trapped within it.

[0012] These trapping phenomena on SiC MOSFETs are complex and depend on the voltage bias conditions of the gate oxide (DC component and AC component related to the control switching). They are also exacerbated at high operating temperatures. Trapping leads on the one hand to a slow but continuous increase in the threshold voltage VTH, and on the other hand, to a decrease in the p mobility of electrons in the channel. The combination of these two effects leads on the one hand to an increase in the channel resistance, and therefore conduction losses, and on the other hand to an increase in the Miller plateau amplitude, thus reducing the switching speed (especially the dv / dt at ignition whose loss component is dominant) and increasing the switching losses.

[0013] There are several secondary indicators of the health of a SiC MOSFET: the on-state resistance RDSON, the duration and amplitude of the Miller plateau. These quantities are certainly impacted by the aging of the transistor, but are made up of several other components, each providing contributions that drown out the intrinsic variations due to the component's own aging. Their relevance for monitoring the health of the transistor can then be questioned.

[0014] There are other indirect indicators such as the IGSS gate and drain leakage currents I DSS, the internal gate resistance RGINT( GS) and the characteristic Ciss = f( cs) (see in particular A. El Boubkari, Development of fast, precise and integrated CMOS features, for optimal switching and internal protection of SiC MOSFET inverters (hal. science, 2023)): • The IGSS gate leakage current increases by several orders of magnitude between a healthy component (a few hundred femtoamperes) and a component with a cracked gate (about 10mA). The measurement of this parameter requires an extremely precise and stable differential measurement of the voltage across the external gate resistance but IGSS does not act as a precursor, but rather as a final indicator of irreversible degradation.This leakage measurement as a precursor (before cracking of the gate oxide) is possible thanks to a dedicated driver channel as explained in the application PCT / FR2023 / 051145 with a sensitivity of 30nA. However, its implementation remains complex.

[0015] • Monitoring drain leaks is based on measuring an observable on the power side (between drain and source) and must be accurate to the order of a milliampere, making it not feasible in practice within a converter.

[0016] • It is shown that by performing a VGS sweep from negative to positive values ​​using a static characteristics tracer (e.g. Keysight B1505A), a shift in the "flatband" voltage appears for the aged component. A similar property can be obtained by sweeping on RGINT(GS) and monitoring the variation of this value. However, this method remains difficult to apply to an on-board measurement.

[0017] The main indicator whose variations faithfully reflect the evolution of the health status of the component remains the threshold voltage VTH. However, in the current state of the art, this parameter is not currently directly measurable in real time when the transistor is integrated within a power converter in operation and subjected to a switching regime.

[0018] STATEMENT OF THE INVENTION

[0019] The present invention aims to solve all or part of the problems set out above.

[0020] It proposes in particular an electronic circuit for monitoring, for example within a power converter, the state of health of a MOSFET power transistor, by measuring in real time the threshold voltage of the transistor VTH. The invention relates in particular to a device for tracking or monitoring the state of health of a MOSFET power transistor comprising:

[0021] - means for supplying or applying to a MOSFET power transistor a starting voltage (VGS), these means comprising at least one resistor (R3, R4), forming an external gate resistance, of at least 10 kΩ;

[0022] - means for measuring or estimating the grid voltage dip (VGS) following the Miller plateau.

[0023] The first means can provide a MOSFET power transistor with an "ultra slow" start-up voltage (VGS).

[0024] The transistor is, for example, of the wide-gap semiconductor type, such as SiC or GaN technology. By "wide gap", we mean an energy gap or height of the forbidden band Eg separating the last occupied states of the valence band and the first free states of the conduction band, which is larger than silicon. Alternatively, it can also be a silicon (Si) MOSFET transistor.

[0025] Thus the invention makes it possible to estimate the threshold voltage of the transistor by measuring the dip in the gate voltage (VGS) which follows the Miller plateau.

[0026] The invention therefore proposes a real-time monitoring device, which can be embedded. The integration of this type of device makes it possible to detect early signs of degradation and aging of MOSFETs, in particular SiC MOSFETs, thus enabling rapid intervention to avoid more serious problems.

[0027] According to one embodiment, a monitoring device according to the invention may comprise means or a stage for detecting the cancellation of the derivative of the gate voltage (VGS).

[0028] Optionally, means or a comparison stage may or may be provided to compare the value of the derivative of VGS to a comparison threshold value.

[0029] Preferably, the comparison threshold value is negative.

[0030] According to a particular embodiment, the comparison means or stage comprise(s) means forming hysteresis. A device according to the invention may further comprise means for storing a value of said dip.

[0031] For example, it includes at least one sample-and-hold device to maintain the said trough value.

[0032] The means for storing a minimum value of said trough may include a capacitor. They may also be associated with means forming a switch.

[0033] A device according to the invention may further comprise second means for applying a voltage to a power MOSFET transistor, these second means comprising at least one resistor of low value relative to said resistor forming an external gate resistance.

[0034] Such a device may further comprise means for controlling the first means and the second Pulse Width Modulation (PWM) means.

[0035] A device according to the invention may further comprise means of synchronization with a current sensor, to synchronize a measurement or an estimation of the dip in the grid voltage (VGS) which follows the Miller plateau with a charging current, which is preferably then zero.

[0036] A device according to the invention may further comprise means for providing a control signal - which may come from digital control means - for the application of a trigger voltage (VGS) to the power MOSFET transistor.

[0037] The invention also relates to a method for monitoring the health status of a power transistor, for example of the MOSFET-SiC or HEMT p-GaN or MOSFET-Si type or, more generally, of a power transistor of any other technology (providing a strong non-linearity of Cgd with the voltage Vds) or of a power transistor of the MOSFET-Si type, implementing a device as described above and in the remainder of the present application.

[0038] The invention also relates to a power converter or module comprising several power transistors and at least one device as described above and in the remainder of the present application. The invention also relates to an aircraft comprising at least one power converter or module according to the invention.

[0039] BRIEF DESCRIPTION OF THE FIGURES

[0040] - [Fig. IA], [Fig. IC] illustrate the dependency link between CGD and VDS, representing the CGD curve as a function of VDS (figure IA), and the time evolution of respectively VDS (figure IB), and VGS (figure IC) of a MOSFET - SiC transistor;

[0041] - [Fig. 2A], [Fig. 2B] represent the influence of the driver voltage VDD on the shape of the VGS trough (figure 2A) and on VDS (figure 2B);

[0042] - [Fig. 3] represents a comparison of the VGS waveforms between a new component with healthy oxide (curve I) and a stressed component with aged oxide (curve II);

[0043] - [Fig. 4] schematically represents a measurement chain for analog monitoring of the dip with VGS derivative and direct sampling;

[0044] - [Fig. 5A], [Fig. 5B] represent simulation results of the time evolution of VGS and (dVcs / dt);

[0045] - [Fig. 6A], [Fig. 6B] represent the same curves as in BABB figures with, in addition, the output of the sample-and-hold (EB);

[0046] - [Fig. 7A], [Fig. 7A1], [Fig. 7B] [Fig. 7B1], [Fig. 7C], [Fig. 7C1], represent a possible embodiment of means for automatically memorizing the hollow;

[0047] - [Fig. 8] schematically represents another possible embodiment of means for memorizing the hollow;

[0048] - [Fig. 9] schematically represents a measuring chain for analog monitoring with automatic storage of the hollow;

[0049] - [Fig. 10A], [Fig. 10C] represent simulation results of the time evolution of VGS (Figure 10A) and (dVcs / dt) (Figure 10C) with the waveforms of interest and the signal for opening the switch and blocking the sample-and-hold device (Figure 10B);

[0050] - [Fig. 11] and [Fig. 12] respectively represent examples of detailed embodiments of the circuits of figures 4 and 9; - [Fig. 13A], [Fig. 13B], [Fig. 14A] and [Fig. 14B] represent an application of the invention to a Pulse Width Modulation control frame

[0051] (MLI);

[0052] - [Fig. 15A], [Fig. 15B] represent an application of the invention to a three-phase inverter involving common mode control on a line of low-side (A) and high-side (B) transistors;

[0053] - [Fig. 16] represents an application of the invention to a switching according to the invention around the zero of a load current;

[0054] - [Fig. 17] represents an electronic gate control circuit.

[0055] - [Fig. 18] represents an example of control timing diagrams for the device of Figure 17;

[0056] - [Fig. 19] represents an implementation of the synchronization of a measurement according to the invention with a current sensor.

[0057] DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0058] The invention relates to a method for monitoring the health status of a power transistor, in particular based on a wide gap semiconductor, for example such as SiC or GaN, i.e. comprising an energy gap or a height of the forbidden band Eg separating the last occupied states of the valence band and the first free states of the conduction band, which is greater than silicon. This is for example a transistor of the SiC MOSFET type or a p-GaN HEMT (high electron mobility transistor made of gallium nitride) or a power transistor of any other technology (providing a strong non-linearity of Cgd with the voltage Vds). But the invention also applies to power transistors of the Si MOSFET type. In the following, most of the explanations are given for a SiC MOSFET type transistor.

[0059] According to the invention, such a monitoring method implements monitoring of the threshold voltage VTH thereof. This quantity is however not directly accessible. An observable which relatively faithfully transcribes the variations in VTH is the Miller plateau during a firing commutation. The amplitude of this plateau is dependent on several other parameters, as shown by the equation

[0060] (1) below:

[0061] [Math 1] in which VP is the amplitude of the Miller plateau, ICH the load current, GFS the transconductance of the transistor, Coss the internal output capacitance of the MOSFET, VDS the drain-source voltage, X the parameter translating the “short-channel” effect on the SiC MOSFET and generating an oblique plane evolution of the plateau.

[0062] In order to keep only the influence of VTH on this Miller plateau, we seek to minimize the parasitic contributions on the plateau voltage, therefore to minimize ICH (to minimize ICH / GFS) and to have a very large “dt” (to minimize dVos / dt), f(À, VDS) being a parameter specific to the transistor on which we cannot act.

[0063] For example, a very slow switching of the transistor is achieved, the switching time then being greater than that of the nominal switching with very high external gate resistance RG (several kQ, for example RG=10kQ), whereas the nominal value RGNOM of external gate resistance RG for a "nominal" switching is for example about 10Q: the switching slowdown factor is therefore here 1000 compared to a normal or nominal switching, under low external gate resistance, therefore fast, at zero load current. The influence of the parameters which are not of interest here on the amplitude of the plateau is then minimized, and the duration of the plateau is increased to facilitate its reading (for example on an oscilloscope) and / or its extraction.

[0064] To this end, for example, we aim for RG (external grid resistance) to be at least 100 times higher than its nominal value RGNOM.

[0065] In other words, we are trying to control the switching of the transistor in a slow or very slow manner, by varying the value of the external gate resistance RG, that is to say the resistance applied to the gate of the transistor (while Rcint designates the internal gate resistance, intrinsic to the transistor and its technology). Thus, during the Miller plateau, the buffer does not bring more charges to the internal gate-source capacitance CGS than the internal gate-drain capacitance CGD pumps it.

[0066] According to one embodiment, it is possible, for example, to increase the current delivered by the driver to the gate IG by the gate-drain current ICGD, which leads to the following condition (the numerical values ​​are specific to the SiC MOSFET component used during tests (C2M0080120D)):

[0067] [Math 2]

[0068] Let R G » (20-5) / lOOpF . 200V / s

[0069] We therefore obtain: RG » 750Q; we can therefore take for example RG equal to approximately 10kO.

[0070] Switching is then slowed down by a factor of about 1000 compared to normal switching under a gate resistance RG of 100.

[0071] An example of an electronic circuit 100 for controlling the gate of a power transistor 32, for example a SiC MOSFET, is presented in figure 17. It comprises:

[0072] - on the one hand, first means (a buffer) 15 of conventional control, also called “Fast”, which can be set to high impedance via a dedicated control input 17 (“Enable Fast”). These means 15 are associated with the gate resistors R1-R2 (Ri for priming, R2 for blocking), which are low-value resistors (for example typically 10Q);

[0073] - on the other hand, second means (buffer) 12, also called “Ultra-Slow”, connected, in parallel with the means 15, to the gate of the power transistor 32 to be driven. These means 15 are associated with the gate resistors R3-R4, which are greater than Ri and R2 by a factor of, for example, 1000 (R3 and R4 have a value of 10kQ in this example). The power supplies of these two means 12, 15 (VDDX and Vssx) can be adjusted independently of each other.

[0074] Figure 17 represents an architecture, called “multi-buffer” type, comprising the means or circuits 12, 15, mounted in parallel, for close electronic control of the gate of a power transistor 32, for example a transistor of a power converter as illustrated in figures 15A and 15B. This figure highlights the dedicated control channel (comprising the means 12 and the resistors F and F ) for measuring and monitoring VTH (VGSTH) for monitoring the health status of the transistor.

[0075] A device according to the invention, for example that of figure 17, applies equally well to a measurement on a “high side” component (for example the transistor 42i of figure 15A), as on a “low side” component (for example the transistor 42? of figure 15A).

[0076] Figure 18 shows an example of control timing diagrams for the device of Figure 17, the “ultra-slow” mode being activated when the “fast” mode is inhibited and vice versa. A measurement according to the invention can be carried out when the “ultra-slow” mode is activated.

[0077] The inventors observed that VGS (shown in Figure IC) corresponds to the trough appearing after the Miller plateau.

[0078] This dip appears at low drain-source voltage VDS (represented in Figure 1B): in the zone of strong non-linearity of the internal drain-gate capacitance CGD (represented in Figure 1A), from an instant ti. This strong variation in capacitance then generates a charge pump effect from the gate to the drain, thus causing a dip to appear on VGS through the high external gate resistance (here: 10kQ), a dip which is visible in Figure IC.

[0079] This dip appears at time ti, corresponding to the end of the switching dVos / dt, when CGD becomes highly non-linear. The electrical charges thus drawn from the gate to the drain discharge CGS and contribute to reducing VGS. On the other hand, the control circuit (or "gate driver") of the transistor injects charges to the gate through the external gate resistor. These two antagonistic phenomena are in competition, and the contribution made by the control circuit takes over when CGS stops varying, which allows the gate charge and therefore the switching to be resumed and continued.

[0080] Tests at reduced VDD voltage (control circuit supply voltage) were conducted. These tests show the impact of a reduced contribution of the charge supply by the control circuit on the dip phenomenon mentioned above. It appears that the minimum value of the dip tends towards the intrinsic threshold value VTH. This is explained by the fact that at the end of the plateau, at the beginning of the dip, the ICGD current drawn by CGD from the gate to the drain passes through the transistor channel, the formation of which depends on the gate bias VGS. As ICGD discharges the gate, the channel narrows (pinches off), and limits the current that can pass through the channel: this slows down the phenomenon and lengthens the duration of the dip.

[0081] This is valid, and visible at reduced VDD, because the driver injects few charges into the gate, which allows the dip voltage to approach, to touch the gate voltage VTH of the transistor at the limit of channel conduction, as illustrated in figures 2A and 2B; in these figures, we have represented the evolution of VGS (figure 2A; in this figure, SMU means "source measurement unit") and VDS (figure 2B) for various values ​​of VDD, between 10 V and 20 V as indicated in these figures.

[0082] Therefore, the dip in the grid voltage appears as a reliable, new, low-noise indicator, corresponding to a VTH image. The value of this dip can be defined as the difference between the Miller plateau level and the absolute minimum value of the dip. We will place ourselves in good conditions to measure or estimate the dip in the grid voltage with, preferably:

[0083] - a slowed down ignition switching, for example by about 1000 times, compared to a conventional ignition; this can be obtained by using an external gate resistance RG 1000 times higher than the nominal case;

[0084] - a zero load current during this ignition; Figures 15A to 16 illustrate implementations for monitoring the health status of a transistor within a three-phase power converter, and to enable measurement at zero load current. Figures 15A-15B illustrate simultaneous ultra-slow ignition on the 3 low-side transistors (15A) or on the 3 high-side transistors (15B) within a three-phase power inverter. Such a control strategy makes it possible to avoid the circulation of currents in the triggered transistors. Figure 16 illustrates the use of a current sensor 43 on a phase of a motor to synchronize the ultra-slow measurement around the cancellation of the load current; - a reduced supply voltage of the driver 12 (VDDI in Figure 17), for example less than or equal to 10V; whereas a nominal or “normal” voltage of the driver 12, for example between 15V and 20V, is higher than this reduced value.Indeed, as already explained above, at supply voltage V. Of , reduced, the minimum value of the dip tends towards the intrinsic threshold value of the transistor. In other words, the dip, an indicator of the state of health, then approaches VTH and therefore the physical phenomenon of charge trapping; this indicator then becomes all the more relevant. But this requires an adjustable VDD power supply, which means the use of additional components: the implementation is therefore more complex.

[0085] At nominal VDD (= 20V; in this case, VDD is not reduced), the variations of this dip (represented as a function of time in figure 3 on which curve I represents these variations for a new transistor, with healthy oxide and curve II for a stressed transistor, with aged oxide) follow in a relative manner the variations of VTH and then also give an indication of the state of degradation of the gate oxide layer.

[0086] Analog implementations of tracking the dip on the gate voltage are proposed below.

[0087] A first implementation, with direct sampling, is based on a derivative of VGS: the amplitude of the plateau on VGS will increase over time depending on the trapping state of the oxide layer but its overall dynamics will remain unchanged, as shown in Figure 3, which allows comparison of VGS waveforms between a new component with healthy oxide (curve I) and a stressed component with aged oxide (after 24 hours of stress at VGS = 35 V, curve II).

[0088] Cancelling the derivative of VGS therefore appears to be a means of detecting the appearance of the dip. Comparing this derivative to a threshold, preferably adjustable, makes it possible to generate the command to control a blocking sampler on VGS. This method makes it possible to sample and store the value of VGS at the instant when its derivative intersects with a threshold.

[0089] A diagram of a circuit or device 10 for implementing this solution is given in Figure 4, in which: - means 8 (control isolator, optocoupler) isolate the digital control commands from the rest of the electronic circuit; these means 8 provide the interface or link between the digital control commands and the electronic components of the circuit; they provide the “ultra slow” boot control signal; the control signal for activating these means is sent by digital control means, for example an FPGA;

[0090] ■ means 12 (or buffer) control the transistor under test 32 and allow it to be started slowly; the gate control signal comes from the means 12, passes through the external gate resistor 12', the VGS signal which comes out of 12' contains information on the state of health of the transistor under test;

[0091] - means 34 forming an instrumentation amplifier (these means 34 making it possible to copy and isolate the signal), which make it possible to read, reconstruct and process VGS via an impedance adaptation; in fact, under a gate resistance of such a high value (10kQ) the slightest gate leakage path becomes non-negligible. A simple resistive voltage divider bridge for capturing VGS is therefore not possible here due to the current leaks at low total resistance of such a divider bridge, and its sensitivity to noise at high resistance;

[0092] - a stage 14 for calculating the derivative is then applied to the VGS image obtained at the output of the means 12;

[0093] - a threshold comparison stage 16 makes it possible to compare the derivative with a predetermined threshold;

[0094] - means 18 forming a flip-flop make it possible to generate and maintain at a certain state a control edge from the result of the comparison of the threshold and the derivative.

[0095] The output of the means 18, as well as the VGS data obtained at the output of the means 12, are applied to the input of a sampler-blocker 20. The value(s) of V hollow can then:

[0096] - be used as an indicator of the evolution of transistor aging

[0097] 32: - and / or be digitized by an analog-digital converter

[0098] (CAN) to be processed and then possibly stored in a digital control unit (FPGA type for example);

[0099] - be compared over time to monitor the evolution of the health status of the transistor 32 tested.

[0100] Examples of embodiments of the various means 12-23 are given in figures 11 and 12 as well as below, in connection with these figures 11 and 12.

[0101] A simulation using “LTspice” software using ideal components (which come directly from the LTspice library provided with the software) was carried out.

[0102] The results of this simulation are illustrated in Figures 5A and 5B. An “Ultra-Slow” triggering under a very high external grid resistance RG (for example 1000 times higher than the normal or nominal resistance, which has a value generally around 10Q), R3, R4 (as already explained above) respecting the condition established beforehand (factor for example 1000 already mentioned above), for example Rc=10kQ was carried out on a test bench. The VGS load curve (whose time evolution is represented in Figure 5A) is extracted from the oscilloscope in the form of a point file, then imported into the simulation software as a voltage source profile. Figure 5B represents the time evolution of the derivative of VGS (derivative obtained at the output of the derivative stage 14).

[0103] As seen in Figures 5A and 5B, comparing the derivative of VGS to a threshold of 0V leads to a risk of false triggering and generation of unwanted edges, particularly in the plateau zone. This is why a negative safety threshold is chosen (for example: -0.6V). It thus makes it possible to establish a safety margin with respect to the 0V threshold, thus avoiding false triggers and obtaining clear intersections with the negative part of the derivative. This negative part corresponds to the start of the trough, in the decreasing zone of VGS. The waveform 21 at the output of the sample-and-hold circuit 23 (EB) is shown in Figures 6A and 6B. Its output performs a value hold (around the trough) when it receives a control edge on its clock input.

[0104] It therefore appears that the output of the sample-and-hold circuit 23 is maintained at a voltage value close to that of the dip. This "direct" method has the advantage of relying on a reduced number of components. However, in order to obtain a measurement that is as faithful as possible, we seek to ensure that the control edge of the sample-and-hold circuit appears at the minimum of the dip. This can be achieved by adjusting the threshold and the bandwidth of the differentiator stage 14.

[0105] Another implementation, with trough memorization, is based on automatic memorization of the minimum value of the trough. It is shown in Figures 7A - 9.

[0106] Figure 7A schematically represents means 22a for memorizing the dip. These means comprise 2 diodes 221, 223 arranged inverted and in parallel as well as a capacitor 224 for memorizing the dip value.

[0107] Initially (Figure 7A, Figure 7A1), the representative signal of VGS charges the capacitance 224, until the end of the Miller plateau.

[0108] In a second step (figure 7B, figure 7B1), the voltage across the terminals of capacitor 224 decreases, which corresponds to the trough following the Miller plateau.

[0109] Finally, in a 3 e time (figure 7C, figure 7C1), the capacitor 224 recharges through the forward diode 221 when VGS rises.

[0110] In other words, the means 22a do not allow the trough to be correctly memorized because the memory capacity 224 CMEM recharges through the direct diode 221 when VGS rises.

[0111] Therefore, as illustrated in Figure 8, means 22 are used, comprising means forming a switch 226 upstream of the direct diode 221; these means 226 make it possible to dynamically open the circuit to prevent this undesirable recharging of the capacitor 224 CMEM and so that the voltage across the terminals of the latter is maintained (apart from leaks) at the value of the dip. As can be understood from Figure 7C1, the control of the opening of the means 226 preferably occurs before zone 3 and as long as VGS > VCREUX.

[0112] As shown in Figure 9, the switch opening order will be generated by flip-flop 18 of the trigger chain. Figure 8 represents the contents of the means 22 forming the storage block of the hollow of Figure 9. The other elements of this Figure 9 have already been described above, the reference 32 again designating the transistor tested.

[0113] In this configuration, the input of the sample-and-hold circuit 23 (EB) is now the voltage of the memory capacity CMEM which corresponds to the minimum value of the dip. In comparison with the "direct" solution described above in connection with Figure 4, an analog pre-processing stage is added (for dip storage) and makes it possible to make the dip value available at the input of the sample-and-hold circuit 23. Once the dip value has been stored by CMEM, the sample-and-hold circuit 23 receives a blocking edge and their output is maintained at a value as close as possible to the true dip value.

[0114] The diodes 221, 223 used in the dip storage stage are preferably AOP (operational amplifier) ​​compensated diodes to overcome their threshold voltage.

[0115] The simulation results in Figures 10A - 10C show that the CMEM voltage correctly copies VGS and maintains itself at the trough value. As seen in Figure 10B, the order to open the switch (to prevent VMEM from rising) is sent at the beginning of the trough. A delay (see Figure 10A) can be introduced (analogously, for example with an RC-type delay circuit, or digitally (flip-flops and digital control unit) at the digital control unit) on the same signal that is sent to the blocking port of the sample-and-hold circuit 23 so that VMEM has time to decrease to VCREUX.

[0116] Figure 11 shows a detailed analog implementation of a circuit

[0117] 10 analog tracking of the dip on VGS. Figure 12 represents a detailed analog implementation of a circuit 20 for analog tracking of the dip on VGS, with storage of the dip value.

[0118] In these figures 11 and 12:

[0119] - the means 18 forming a flip-flop make it possible to generate the control edge of the sample-and-hold circuit 23 (figure 11), the control order of the analog switch of the dip storage block 22 (figure 12) and the control edge of the “Sample_Ready” signal (figures 11, 12) through an isolator T1 indicating to a digital control unit (for example an FPGA) that it can start acquiring the dip value extracted at the output of the chain;

[0120] - the dip voltage extraction chains are illustrated with a 32 power MOSFET gate drive buffer 12 with high gate resistance;

[0121] - a controlled and regulated current source 25 (= 2mA) allows for priming, in order to be able to precisely measure CGD, which is proportional to the duration of the plateau;

[0122] - the state of the flip-flop means 18 is initialized from the signal from the Ultra-Slow priming means 8;

[0123] - the derivative comparator stage 16 is equipped with hysteresis means to avoid possible rebounds;

[0124] - reference 32 designates a transistor under test;

[0125] - reference 34 designates an amplifier arranged at the input of the means 14 forming a comparator.

[0126] An implementation of the measurement of the dip voltage according to the invention within a Pulse Width Modulation (PWM) control frame is described below, in connection with Figures 13A-14B.

[0127] At no load, with zero load current, an “Ultra-Slow” measurement (according to the invention) of the dip voltage under high gate resistance can be carried out punctually within a PWM frame during active switching of high duty cycle ignition to allow sufficient time for the slowed charging of VGS and the dip measurement. The example of an Ultra-Slow measurement on a high-side component is given in figures 13A.

[0128] To perform a measurement on a low-side component (figure 13B), we wait for half a modulation period for the duty cycle of the “low-side” to be maximum.

[0129] In order to minimize the measurement duration and limit the impact on the PWM control frame, a measurement with switched gate resistors is presented in Figures 14A-14B. With this method, only the plateau and trough area of ​​interest is slowed down and elongated to facilitate measurement and extraction, and also to increase the signal-to-noise ratio of this area. Such “Ultra-Slow” switching (according to the invention), called condensed, makes it possible to perform a measurement of the trough within a switching period (for example, if the switching frequency foEc = 20kHz, then the period TDEC = 50ps, the measurement can be made in a maximum of 20ps, see Figures 6A-7C).

[0130] Figures 15A, 15B and 16, discussed below, illustrate implementations of health monitoring within a three-phase power converter, allowing measurement at zero load current.

[0131] We present, in connection with figures 15A - 15B, an application of a measurement according to the invention to the common mode control on a three-phase inverter (at zero speed).

[0132] A boot switching according to the invention (called "Ultra-Slow") is carried out simultaneously on the 3 "low-side" MOSFETs 42?, 424, 42e (Figure 15A) then on the 3 "high-side" MOSFETs 42i, 42s, 42s (Figure 15B). This makes it possible to carry out the boot switching without load current which would disturb the measurement of the dip. This also makes it possible to obtain information on the health status of 3 MOSFETs at the same time.

[0133] More precisely, when a motor 40 is connected to an inverter 42 (comprising the transistors 42i-42e), the cancellation of the current in the phases of the motor can be produced in such a way as to return to the case explained above in connection with the figures

[0134] 13A - 14B. For this, a homopolar (or common mode) control is applied to the transistors 42i-42e so as to cancel all the phase-to-phase voltages at the terminals of the motor 40 and to tend towards a zero current in the phases. The motor has previously been set to zero speed. As soon as the currents are canceled, a procedure identical or similar to that explained above in connection with figures 13A - 14B can be implemented; a device such as described above is then applied, for example in connection with figures 11 or 12, to each of the transistors 42i-42e.

[0135] Figure 16 shows an application of monitoring according to the invention to “Ultra-Slow” switching around the load current zero: in the case of a motor 40 running and in the presence of currents in the phases, it is possible to operate the “Ultra-Slow” switching as described above by synchronizing this procedure with the current crossing through zero: a measurement according to the invention (called “ultra-Slow”) is synchronized with a current sensor 43. Figure 19 represents an implementation of the synchronization of a measurement according to the invention, as described above, with such a current sensor 43. The signal coming from the latter is compared to a threshold by comparison means 45, then a control edge is generated by means 47 and sent to digital control means 49. The other components 8, 12 of this figure have already been described above, as well as the measuring chain 10 (figure 11) or 20 (figure 12).Reference 32 still designates the transistor under test.

Claims

Claims 1. Device for monitoring the health status of a power MOSFET transistor (32) comprising: - first means (8, 12) for applying a starting voltage (VGS) to a power MOSFET transistor, these means (8, 12) comprising at least one resistor (R3, R4), forming an external gate resistance, of at least 10 kΩ, to be applied to the gate of the transistor; - means (12-22) for measuring a grid voltage dip (VGS) which follows the Miller plateau.

2. Device according to claim 1, comprising a stage (14) for detecting the cancellation of the derivative of the gate voltage (VGS).

3. Device according to claim 2, comprising a comparison stage (16), for comparing the value of the derivative of VGS with a comparison threshold value.

4. Device according to claim 3, the comparison threshold value being negative.

5. Device according to one of claims 3 or 4, the comparison stage (16) comprising means (161) forming hysteresis.

6. Device according to one of claims 1 to 5, comprising means (23, 22, 22a) for storing a value of said hollow.

7. Device according to claim 6, comprising at least one sample-and-hold device (23) for maintaining said trough value.

8. Device according to one of claims 6 or 7, the means for memorizing a minimum value of said hollow comprising a capacitor (224).

9. Device according to claim 8, the means for memorizing a minimum value of said hollow comprising means (226) forming a switch.

10. Device according to one of claims 1 to 9, further comprising second means (15) for applying a voltage to a power MOSFET transistor (32), these means comprising at least one resistor (Ri, R?) of low value relative to said resistor forming an external gate resistor (R3, R4).

11. Device according to claim 10, further comprising means for controlling the first means (8, 12) and the second means (15) with Pulse Width Modulation (PWM).

12. Device according to one of claims 1 to 11, further comprising means (8) for providing a control signal for the application of a trigger voltage (VGS) to the power MOSFET transistor (32).

13. Device according to one of claims 1 to 12, further comprising means (45, 47, 49) for synchronization with a current sensor (43).

14. Method for monitoring the health status of a power transistor, for example of the MOSFET-SiC or HEMT p-GaN type or of a power transistor of the MOSFET-Si type, implementing a device according to one of the preceding claims.

15. Power converter or module comprising several power transistors (42i-42e) and at least one device according to one of claims 1 to 13, coupled to at least one of the transistors.

16. Aircraft comprising at least one converter or power module according to claim 15.

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