Display substrate and display apparatus

Abstract

Provided is a display substrate, comprising: a base substrate; a driving circuit layer, which comprises a plurality of first pixel driving circuit groups located in a first display region; a first conductive layer, which comprises a plurality of first trace groups, wherein each first trace group comprises a first power source signal line and two trace sub-groups respectively located on two sides of the first power source signal line in a first direction, and each trace sub-group comprises a first signal trace and a second signal trace; and a second conductive layer, which is located between the driving circuit layer and the first conductive layer, and comprises a plurality of third signal traces and a plurality of fourth signal traces, wherein the first power source signal lines are electrically connected to a pixel driving circuit unit by means of the third signal traces, the plurality of fourth signal traces include a plurality of first adapter traces, the plurality of second signal traces include a plurality of second adapter traces located in a second display region, and the second adapter traces are used for receiving data signals provided by binding pads and connecting the data signals to the first pixel driving circuit groups by means of the first adapter traces and the trace sub-groups.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the rapid development of the display industry in recent years, consumers have increasingly stringent requirements for display bezel widths. Narrow and even zero-bezel displays have gradually become a trend in the display industry. How to reduce the display bezel without compromising display quality is a major concern for display product developers.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute prior art.

[0004] Summary of the Invention

[0005] In one aspect, a display substrate is provided, the display substrate comprising a display area and a peripheral area located around the display area, the display substrate comprising:

[0006] substrate;

[0007] a driving circuit layer located on the base substrate, the driving circuit layer comprising a plurality of pixel driving circuit groups arranged along a first direction, the pixel driving circuit groups comprising a plurality of pixel driving circuit units arranged along a second direction, the first direction intersecting the second direction, the display area comprising a first display area and a second display area arranged along the first direction, the first display area being located on a side of the second display area close to the peripheral area, the plurality of pixel driving circuit groups comprising a plurality of first pixel driving circuit groups located in the first display area and a plurality of second pixel driving circuit groups located in the second display area;

[0008] a first conductive layer, located on a side of the driving circuit layer away from the base substrate, the first conductive layer comprising a plurality of first routing groups arranged along a first direction, the first routing group comprising a first power signal line and two sub-routing groups respectively located on either side of the first power signal line along the first direction, the sub-routing groups comprising a first signal routing line and a second signal routing line arranged along the first direction, the first power signal line, the first signal routing line, and the second signal routing line all extending along the second direction, and one sub-routing group being electrically connected to each of the pixel driving circuit units in one pixel driving circuit group;

[0009] a second conductive layer located between the driving circuit layer and the first conductive layer, the second conductive layer comprising a plurality of third signal lines and a plurality of fourth signal lines, the plurality of third signal lines and the plurality of fourth signal lines being alternately arranged along the second direction, and the third signal lines and the fourth signal lines extending along the first direction; and

[0010] a plurality of binding pads located on the base substrate, the peripheral area comprising a first peripheral area located on one side of the display area along the second direction, and the plurality of binding pads located in the first peripheral area;

[0011] Wherein, the first power signal line is electrically connected to the pixel driving circuit unit through the third signal line; and

[0012] The plurality of fourth signal lines include a plurality of first transfer lines, and the plurality of second signal lines include a plurality of second transfer lines located in the second display area, and the second transfer lines are used to receive the data signal provided by the binding pad and connect the data signal to the first pixel driving circuit group through the first transfer line and the sub-line group.

[0013] According to some exemplary embodiments, the first power signal line includes a plurality of signal blocks spaced apart along the second direction, adjacent signal blocks are electrically connected via a signal connection segment, and the signal connection segment is directly connected to the third signal line.

[0014] According to some exemplary embodiments, the signal block includes a first portion and a second portion arranged along a first direction, the first portion is directly connected to the second portion, and the signal connection section is directly connected to both the first portion and the second portion.

[0015] According to some exemplary embodiments, the signal block includes a first sub-block, a second sub-block, and a third sub-block arranged along the second direction, the first sub-block is directly connected to the second sub-block, and a size of the first sub-block along the first direction is smaller than a size of the second sub-block along the first direction, and the second sub-block is directly connected to the third sub-block, and a size of the second sub-block along the first direction is smaller than a size of the third sub-block along the first direction;

[0016] The first signal line includes a plurality of first connection blocks, which are located on a side of the adjacent second signal line away from the second sub-block. The second signal line includes a plurality of second connection blocks, which are adjacent to the first sub-block.

[0017] According to some exemplary embodiments, the second signal trace includes a second signal segment connected between two adjacent second connection blocks, the second signal segment includes a first sub-segment, a second sub-segment, and a third sub-segment arranged along the second direction, a portion of the first sub-segment is adjacent to the second sub-block, a portion of the second sub-segment is adjacent to the third sub-block, and the third sub-segment is connected and disposed between the first sub-segment and the second sub-segment;

[0018] The first subsegment and the second subsegment extend along the second direction, the second subsegment is closer to the adjacent first signal trace than the first subsegment, one end of the third subsegment is connected to the first subsegment and extends along a third direction until the other end is connected to the second subsegment, and the third direction intersects with the second direction.

[0019] According to some exemplary embodiments, the first conductive layer further includes a plurality of anode connecting portions, and one anode connecting portion is provided on each side of the signal connection segment along the first direction.

[0020] According to some exemplary embodiments, a first insulating layer is provided between the first conductive layer and the second conductive layer, the first insulating layer has a plurality of first vias, and the signal connection segment is electrically connected to the third signal trace through the first vias; and

[0021] The display substrate further includes a second insulating layer located on a side of the first conductive layer away from the base substrate, and a first electrode layer located on a side of the second insulating layer away from the base substrate, the second insulating layer having a plurality of second via holes, and the first electrode layer is electrically connected to the anode connecting portion through the second via holes;

[0022] The orthographic projection of the first via hole on the base substrate is located between the orthographic projections of two adjacent second via holes on the base substrate.

[0023] According to some exemplary embodiments, a first pixel driving circuit groups are located in the first display area, the 1st pixel driving circuit group is closest to the second display area, and the ath first pixel driving circuit group is farthest from the second display area; and

[0024] The first sub-routing group electrically connected to the first first pixel driving circuit group is electrically connected to the binding pad via the first first transfer routing line and the first second transfer routing line, and the d-th sub-routing group electrically connected to the d-th first pixel driving circuit group is electrically connected to the binding pad via the d-th first transfer routing line and the d-th second transfer routing line, where 2≤d≤a, and a and d are integers;

[0025] The first first transfer line is closer to the first peripheral area than the dth first transfer line, and the first second transfer line is closer to the first display area than the dth second transfer line.

[0026] According to some exemplary embodiments, there is a first insulating layer between the first conductive layer and the second conductive layer, the first insulating layer has multiple third vias and multiple fourth vias, the second transfer trace is electrically connected to the binding pad, the second transfer trace is electrically connected to the first transfer trace through the third via, and the sub-trace group is electrically connected to the first transfer trace through the fourth via.

[0027] According to some exemplary embodiments, the second signal routing line in the sub-routing group is electrically connected to the first transfer routing line through the fourth via hole, and the second signal routing line is electrically connected to the first pixel driving circuit group.

[0028] According to some exemplary embodiments, the second signal routing in the sub-routing group is electrically connected to the first transfer routing through the fourth via, the second signal routing is electrically connected to the adjacent first signal routing through at least one bridge bar, and the first signal routing is electrically connected to the first pixel driving circuit group.

[0029] According to some exemplary embodiments, the bridge bar is located on the first conductive layer, and an orthographic projection of the bridge bar on the base substrate is located within an orthographic projection of the second conductive layer on the base substrate.

[0030] According to some exemplary embodiments, the orthographic projection of the bridge bar on the substrate is located within the orthographic projection of the third signal trace on the substrate; and / or

[0031] The orthographic projection of the bridge bar on the base substrate is located within the orthographic projection of the fourth signal trace on the base substrate.

[0032] According to some exemplary embodiments, the first transfer trace has a first break and a second break, the first break is located on a side of the third via away from the fourth via, and the second break is located on a side of the fourth via away from the third via.

[0033] According to some exemplary embodiments, the orthographic projections of the first fracture and the second fracture on the base substrate are located within the orthographic projection of the first conductive layer on the base substrate.

[0034] According to some exemplary embodiments, the first fractures are arranged in a row along the second direction at intervals; and / or

[0035] The second fractures are arranged in a row at intervals along the second direction.

[0036] According to some exemplary embodiments, the second transfer trace has a third break, and the third break is located on a side of the third via away from the first peripheral area.

[0037] According to some exemplary embodiments, an orthographic projection of the third fracture on the base substrate is located within an orthographic projection of the second conductive layer on the base substrate.

[0038] According to some exemplary embodiments, an orthographic projection of the third fracture on the substrate is located within an orthographic projection of the third signal trace on the substrate.

[0039] According to some exemplary embodiments, an orthographic projection of the third fracture on the substrate is located within an orthographic projection of the third signal trace closest to the third via on the substrate.

[0040] According to some exemplary embodiments, the third fractures are arranged in a row at intervals along the first direction.

[0041] According to some exemplary embodiments, the second signal trace electrically connected to the first transfer trace is a third transfer trace, the third transfer trace has a fourth break and a fifth break, the fourth break is located on a side of the fourth via away from the first peripheral area, and the fifth break is located on a side of the fourth via close to the first peripheral area; and

[0042] The third transfer trace includes a third transfer section cut between the fourth break and the fifth break, and the third transfer section is electrically connected to the adjacent first signal trace through at least one of the bridge bars;

[0043] Among the two adjacent third transition segments, the length of the third transition segment close to the second display area is greater than the length of the third transition segment far from the second display area.

[0044] According to some exemplary embodiments, the fourth fractures are arranged in a row along the first direction at intervals; and

[0045] Of the two adjacent fifth fractures, the fifth fracture close to the second display area is closer to the first peripheral area than the fifth fracture far from the second display area.

[0046] According to some exemplary embodiments, the second signal routing electrically connected to the first transfer routing is a third transfer routing, the third transfer routing is electrically connected to the adjacent first signal routing through at least one bridge bar, and the third transfer routing extends continuously from one end of the display area close to the first peripheral area to an end of the display area away from the first peripheral area.

[0047] According to some exemplary embodiments, a connection trend line of each of the third vias intersects a connection trend line of each of the fourth vias.

[0048] According to some exemplary embodiments, the first insulating layer has a plurality of fifth vias, the second signal trace is electrically connected to the fourth signal trace through the fifth vias, the plurality of fifth vias include a plurality of fifth via groups, a connection trend line of a portion of the fifth vias in the fifth via group is a first connection trend line, and a connection trend line of a remaining portion of the fifth vias in the fifth via group is a second connection trend line;

[0049] The first connection trend line is substantially parallel to the connection trend lines of each third via hole, and the second connection trend line is substantially parallel to the connection trend lines of each fourth via hole.

[0050] According to some exemplary embodiments, the first insulating layer has a plurality of fifth vias, the second signal trace is electrically connected to the fourth signal trace through the fifth vias, the plurality of fifth vias include a plurality of fifth via groups, a connection trend line of a portion of the fifth vias in the fifth via group is a first connection trend line, and a connection trend line of a remaining portion of the fifth vias in the fifth via group is a second connection trend line;

[0051] The first connection trend line is not parallel to the connection trend lines of the third via holes, and the second connection trend line is not parallel to the connection trend lines of the fourth via holes.

[0052] According to some exemplary embodiments, the first insulating layer has a plurality of fifth vias, the second signal trace is electrically connected to the fourth signal trace through the fifth vias, the plurality of fifth vias include a plurality of fifth via groups, and the connection trend lines of each of the fifth vias in the fifth via group are X-shaped, W-shaped or M-shaped.

[0053] According to some exemplary embodiments, the fourth signal trace includes a plurality of third connection blocks, and the plurality of third connection blocks include a plurality of first connection sub-blocks and a plurality of second connection sub-blocks;

[0054] A first insulating layer is provided between the first conductive layer and the second conductive layer, the first insulating layer having a plurality of vias, the orthographic projections of the plurality of vias on the base substrate being located within the orthographic projections of the plurality of first connecting sub-blocks on the base substrate, the first connecting sub-blocks being electrically connected to the second signal traces through the vias, and the second connecting sub-blocks being separated from the second signal traces by the first insulating layer; and

[0055] The display substrate further includes a first electrode layer located on a side of the first conductive layer away from the base substrate, and at least a portion of an orthographic projection of the second connecting sub-block on the base substrate is located within the orthographic projection of the first electrode layer on the base substrate.

[0056] According to some exemplary embodiments, the first transfer trace has a first break and a second break, the first break is located on a side of the third via away from the fourth via, the second break is located on a side of the fourth via away from the third via, the first breaks are arranged in a row along the second direction, and the second breaks are arranged in a row along the second direction.

[0057] The first transfer trace has a first transfer segment cut between the first break and the second break, and in the remaining plurality of first transfer segments except the first transfer segment farthest from the first peripheral area, the first transfer segment further has at least one sixth break;

[0058] In the first transition section, the orthographic projection of the sixth break closest to the first display area on the base substrate is located within the orthographic projection of the first power signal line closest to the third via on the base substrate, and the first power signal line is located on a side of the third via away from the first display area, the orthographic projections of two adjacent sixth breaks on the base substrate are respectively located within the orthographic projections of two adjacent first power signal lines on the base substrate, and the orthographic projections of the first break and the adjacent sixth break on the base substrate are respectively located within the orthographic projections of two adjacent first power signal lines on the base substrate; and

[0059] The second signal trace electrically connected to the first transfer trace through the fourth via is a third transfer trace, the third transfer trace having a fourth break and a fifth break, the fourth break being located on a side of the fourth via away from the first peripheral area, the fifth break being located on a side of the fourth via close to the first peripheral area, the fourth breaks being arranged in a row at intervals along the first direction, and the fifth breaks being arranged in a row at intervals along the first direction;

[0060] The third transfer line has a third transfer section cut between the fourth break and the fifth break, and a seventh break is provided between any two adjacent second connection blocks in the third transfer section; and

[0061] The second transfer trace has a third break, the third break is located on a side of the third via away from the first peripheral area, and an orthographic projection of the third break on the substrate is located within an orthographic projection of the third signal trace closest to the third via on the substrate;

[0062] Among the remaining second transfer lines except the second transfer line farthest from the first display area, the second transfer lines further have at least one eighth break, and the eighth break farthest from the first peripheral area is aligned with the fourth breaks along the first direction;

[0063] In the portion where the second transfer line is cut off between the third break and the eighth break farthest from the first peripheral area, the eighth break is provided between any two adjacent second connection blocks;

[0064] Wherein, in a portion of the first transfer section located at a portion of the third via hole away from the first display area, one of two adjacent third connection blocks is the first connection sub-block, the other is the second connection sub-block, and the third connection block adjacent to the third via hole is the second connection sub-block; and

[0065] Each of the third connection blocks in a portion of the fourth signal trace other than the first transfer section is the first connection sub-block.

[0066] According to some exemplary embodiments, the display substrate includes a first source-drain metal layer located on a side of the driving circuit layer away from the base substrate, a second source-drain metal layer located on a side of the first source-drain metal layer away from the base substrate, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the base substrate;

[0067] Wherein, the first conductive layer is the third source-drain metal layer, and the second conductive layer is the second source-drain metal layer.

[0068] According to some exemplary embodiments, the third signal trace includes a plurality of first signal segments and a plurality of second signal segments alternately arranged along a first direction, and adjacent first signal segments are directly connected to the second signal segments; and

[0069] The orthographic projection of the first signal segment on the substrate partially overlaps with the orthographic projection of the first signal trace on the substrate, and the orthographic projection of the second signal segment on the substrate is spaced apart from the orthographic projection of the first signal trace on the substrate;

[0070] The size of the first signal segment along the second direction is greater than the size of the fourth signal trace along the second direction, and the orthographic projection of the second signal segment on the substrate partially overlaps with the orthographic projection of the signal block on the substrate.

[0071] According to some exemplary embodiments, the display substrate includes a first source-drain metal layer located on a side of the driving circuit layer away from the base substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the base substrate;

[0072] The first conductive layer is the second source-drain metal layer, and the second conductive layer is the first source-drain metal layer.

[0073] According to some exemplary embodiments, the third signal trace includes a plurality of first signal segments and a plurality of second signal segments alternately arranged along a first direction, and adjacent first signal segments are directly connected to the second signal segments; and

[0074] The orthographic projection of the first signal segment on the substrate partially overlaps with the orthographic projection of the first signal trace on the substrate, and the orthographic projection of the second signal segment on the substrate is spaced apart from the orthographic projection of the first signal trace on the substrate;

[0075] The size of the first signal segment along the second direction is greater than the size of the fourth signal trace along the second direction, and the orthographic projection of the second signal segment on the substrate is spaced apart from the orthographic projection of the signal block on the substrate. In another aspect, a display device is provided, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Other objects and advantages of the present disclosure will become apparent from the following description of the present disclosure with reference to the accompanying drawings, which will help to provide a comprehensive understanding of the present disclosure.

[0077] FIG1 schematically shows a plan view of a display substrate according to some embodiments of the present disclosure.

[0078] FIG. 2 exemplarily shows an enlarged schematic diagram of the area A1 in FIG. 1 .

[0079] FIG3 schematically shows a plan view of a first conductive layer in a display region of a display substrate according to some embodiments of the present disclosure.

[0080] FIG. 4 exemplarily shows an enlarged schematic diagram of the area B1 in FIG. 3 .

[0081] FIG5 schematically shows a plan view of a second conductive layer in a display region of a display substrate according to some embodiments of the present disclosure.

[0082] FIG. 6 exemplarily shows an enlarged schematic diagram of the area B2 in FIG. 5 .

[0083] FIG. 7 schematically shows an enlarged view of area A2 in FIG. 1 .

[0084] FIG8 schematically shows a plan view of a combination of a first conductive layer and a second conductive layer in a display area of ​​a display panel according to an embodiment of the present disclosure.

[0085] FIG9 schematically shows an equivalent circuit diagram of a pixel driving circuit unit according to an embodiment of the present disclosure.

[0086] 10A to 10J are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0087] 10A illustrates a combination of a first active layer and a first gate metal layer; FIG. 10B illustrates a second gate metal layer; FIG. 10C illustrates a combination of a first active layer, a first gate metal layer, and a second gate metal layer; FIG. 10D illustrates a combination of a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, and a third gate metal layer; FIG. 10E illustrates a first source / drain metal layer; FIG. 10F illustrates a combination of a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, and a A combination of a first source-drain metal layer; Figure 10G illustrates the second source-drain metal layer; Figure 10H illustrates the combination of the first active layer, the first gate metal layer, the second gate metal layer, the second active layer, the third gate metal layer, the first source-drain metal layer and the second source-drain metal layer; Figure 10I illustrates the third source-drain metal layer; Figure 10J illustrates the combination of the first active layer, the first gate metal layer, the second gate metal layer, the second active layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer.

[0088] FIG11 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0089] FIG12A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0090] FIG12B schematically shows an enlarged schematic diagram of region C1 in FIG12A .

[0091] FIG12C schematically shows an enlarged view of region C4 in FIG12A .

[0092] FIG13A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0093] FIG13B schematically shows an enlarged view of region C2 in FIG13A .

[0094] FIG14A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0095] FIG14B schematically shows an enlarged view of region C3 in FIG14A .

[0096] FIG15A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0097] FIG15B schematically shows an enlarged view of region C5 in FIG15A .

[0098] FIG16A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0099] FIG16B schematically shows an enlarged view of region C6 in FIG16A .

[0100] FIG17 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0101] FIG18 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0102] FIG19 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A4 in FIG1 .

[0103] FIG20 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A4 in FIG1 .

[0104] FIG21 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A4 in FIG1 .

[0105] FIG22 schematically shows a plan view of a first conductive layer, a second conductive layer, and a first electrode layer in some display panels according to embodiments of the present disclosure, in which the first conductive layer, the second conductive layer, and the first electrode layer are located in area A3 in FIG1 .

[0106] FIG23 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0107] FIG24 schematically shows a plan view of a second conductive layer in a display region of a display substrate according to some embodiments of the present disclosure.

[0108] FIG25 schematically shows a plan view of a combination of a first conductive layer and a second conductive layer in a display area of ​​a display panel according to an embodiment of the present disclosure.

[0109] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0110] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of the various exemplary embodiments. However, it is apparent that the various exemplary embodiments can be implemented without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments can be different, but not necessarily exclusive. For example, the specific shape, configuration, and characteristics of the exemplary embodiment can be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0111] In the accompanying drawings, the sizes and relative sizes of the elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0112] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to," or "directly coupled to," another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XY, YZ, and XZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0113] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, a first element may be named a second element, and similarly, a second element may be named a first element without departing from the scope of the exemplary embodiments.

[0114] Figure 1 schematically shows a planar schematic diagram of a display substrate according to an embodiment of the present disclosure, in which a display area, a peripheral area, a first peripheral area and a binding pad are schematically shown. Figure 2 exemplarily shows an enlarged schematic diagram of area A1 in Figure 1. Figure 3 schematically shows a planar schematic diagram of a first conductive layer in a display substrate according to an embodiment of the present disclosure. Figure 4 exemplarily shows an enlarged schematic diagram of area B1 in Figure 3. Figure 5 schematically shows a planar schematic diagram of a second conductive layer in a display substrate according to an embodiment of the present disclosure. Figure 6 exemplarily shows an enlarged schematic diagram of area B2 in Figure 5. Figure 7 schematically shows an enlarged schematic diagram of area A2 in Figure 1.

[0115] 1 , the display substrate includes a display area AA and a peripheral area NA located around the display area AA. The display substrate includes a base substrate 100 , a driving circuit layer 200 located on the base substrate 100 , and a plurality of bonding pads BP.

[0116] 1 and 2 , at least a portion of the driver circuit layer 200 is located in the display area AA. The driver circuit layer 200 includes a plurality of pixel driver circuit groups PD arranged along a first direction X. For example, the driver circuit layer 200 includes 2n pixel driver circuit groups PD, where n is a positive integer. The pixel driver circuit groups PD include a plurality of pixel driver circuit units PDA arranged along a second direction Y. The display area includes a first display area AA1 and a second display area AA2 arranged along the first direction X. The first display area AA1 is located between the second display area AA2 and the peripheral area NA. The plurality of pixel driver circuit groups PD include a plurality of first pixel driver circuit groups PD1 located in the first display area AA1 and a plurality of second pixel driver circuit groups PD2 located in the second display area AA2. Here, it should be understood that there is no difference in circuit structure between the first pixel driving circuit group PD1 and the second pixel driving circuit group PD2. Here, only for the purpose of more clearly describing the technical solution of the embodiment of the present disclosure, the pixel driving circuit group PD located in the first display area AA1 is defined as the first pixel driving circuit group PD1, and the pixel driving circuit group PD located in the second display area AA2 is defined as the second pixel driving circuit group PD2.

[0117] For example, a display substrate includes a plurality of sub-pixels, each sub-pixel includes one of the aforementioned pixel driving circuit units PDA and one light-emitting device. Within each sub-pixel, the pixel driving circuit unit PDA is electrically connected to the light-emitting device. The plurality of sub-pixels are arranged in the same manner as the plurality of pixel driving circuit units PDA. The plurality of sub-pixels includes 2n sub-pixel columns arranged along a first direction, and each sub-pixel column includes a plurality of sub-pixels arranged along a second direction.

[0118] 1 , the display substrate may include two first display areas AA1 , which are respectively located on both sides of the second display area AA2 along the first direction X. Exemplarily, the two first display areas AA1 are substantially symmetrically disposed on both sides of the second display area AA2 .

[0119] For example, the first direction X intersects the second direction Y. Exemplarily, the first direction X is perpendicular to the second direction Y.

[0120] 1 , multiple bonding pads BP are located in the peripheral area NA. The peripheral area NA includes a first peripheral area NA1 located on one side of the display area AA along the second direction Y. Multiple bonding pads BP are located in the first peripheral area NA1. The bonding pads BP are spaced apart along the first direction, and multiple bonding pads BP are located outside the second display area AA2 along the second direction Y. The bonding pads BP are used to electrically connect to the bonding pins of the driver chip. The bonding pads BP are also electrically connected to the driver circuit layer 200 via corresponding signal traces, thereby connecting the corresponding drive signals in the driver chip to the driver circuit layer 200.

[0121] The display substrate also includes a first conductive layer, a second conductive layer, a first insulating layer and a third insulating layer. The first conductive layer is located on the side of the driving circuit layer away from the base substrate, the second conductive layer is located between the driving circuit layer and the first conductive layer, the first insulating layer is located between the first conductive layer and the second conductive layer, and the third insulating layer is located between the second conductive layer and the driving circuit layer.

[0122] Referring to Figures 3 and 4 , the first conductive layer includes n first routing groups LX arranged along a first direction X. The first routing group LX includes a first power signal line VDD and two sub-routing groups LA located on either side of the first power signal line VDD along the first direction X. The sub-routing groups LA include a first signal routing line L1 and a second signal routing line L2 arranged along the first direction X. For example, in one sub-routing group LA, the second signal routing line L2 is located between the first signal routing line L1 and the first power signal line VDD. In other words, the first routing group LX includes five signal routing lines, specifically, the first signal routing line L1, the second signal routing line L2, the first power signal line VDD, the second signal routing line L2, and the first signal routing line L1, arranged in sequence along the first direction X. The first power signal line VDD, the first signal routing line L1, and the second signal routing line L2 all extend along the second direction Y.

[0123] 1 to 3 , the number of pixel driving circuit groups PD is the same as the number of sub-routing groups LA, the number of pixel driving circuit groups PD is twice the number of the first routing groups LX, and one sub-routing group LA is electrically connected to each pixel driving circuit unit PDA in a corresponding pixel driving circuit group PD.

[0124] 5 and 6 , the second conductive layer may include a plurality of third signal traces L3 and a plurality of fourth signal traces L4 , wherein the plurality of third signal traces L3 and the plurality of fourth signal traces L4 are alternately arranged along the second direction Y, and the third signal traces L3 and the fourth signal traces L4 extend along the first direction X. For example, the second conductive layer may include m third signal traces L3 and m fourth signal traces L4 , where m is a positive integer.

[0125] With reference to Figures 1 to 6 , the first power signal line VDD is electrically connected to the pixel driver circuit unit PDA via the third signal line L3. That is, the first power signal line VDD is directly connected to the third signal line L3 to achieve electrical connection, and the third signal line L3 is directly connected to the corresponding pixel driver circuit unit PDA to achieve electrical connection. The third signal line L3 is used to receive the first power signal transmitted by the first power signal line VDD and connect the first power signal to the corresponding pixel driver circuit unit PDA.

[0126] With reference to Figures 1 and 7 , the plurality of fourth signal lines L4 include a plurality of first transfer lines LT1, and the plurality of second signal lines L2 include a plurality of second transfer lines LT2. The second transfer lines LT2 are located in the second display area AA2. Specifically, m1 of the m fourth signal lines L4 serve as first transfer lines LT1, which are used to transfer data signals. The remaining fourth signal lines L4 can be used to transmit other drive signals, where m1 is a positive integer less than m. n1 of the 2n second signal lines L2 serve as second transfer lines LT2, which are used to transfer data signals. The remaining second signal lines L2 can be used to transmit other drive signals, where n1 is a positive integer less than 2n. The second transfer lines LT2 receive data signals from the bonding pads BP and sequentially connect the data signals to the corresponding first pixel driver circuit group PD via the corresponding first transfer lines LT1 and the sub-line group LA.

[0127] Referring to Figures 1, 2, 3 and 7, specifically, in the first pixel driving circuit group PD1 located in the first display area AA1 and the sub-routing group LA electrically connected to it, the sub-routing group LA is electrically connected to the binding pad BP through the first transfer routing LT1 and the second transfer routing LT2, and the sub-routing group LA is electrically connected to the pixel driving circuit group PD, so that the sub-routing group LA can receive the data signal provided by the binding pad BP and connect the data signal to the first pixel driving circuit group PD1.

[0128] For example, the sub-routing group LA located in the first display area AA1 is electrically connected to a corresponding first transfer routing line LT1, and the first transfer routing line LT1 is electrically connected to a corresponding second transfer routing line LT2. Furthermore, the second transfer routing line LT2 extends to the first peripheral area NA1 and is electrically connected to a corresponding binding pad BP.

[0129] For example, the electrical connection method between the sub-route group LA and the first transfer route LT1 can be that the second signal route L2 in the sub-route group LA is electrically connected to the first transfer route LT1 through a via in the first insulating layer. The solid circles in Figure 7 schematically indicate the connection position between the second signal route L2 and the first transfer route LT1.

[0130] For example, the first transfer trace LT1 is electrically connected to the second transfer trace LT2 through a via hole in the first insulating layer. The hollow dots in FIG. 7 schematically indicate the connection positions of the first transfer trace LT1 and the second transfer trace LT2.

[0131] For example, the electrical connection between the sub-routing group LA and the pixel driving circuit group PD may be that the second signal routing line L2 in the sub-routing group LA is directly electrically connected to the pixel driving circuit group PD.

[0132] For example, the electrical connection between the sub-routing group LA and the pixel driving circuit group PD may be that the second signal routing line L2 in the sub-routing group LA is electrically connected to the first signal routing line L1 , and then the first signal routing line L1 is electrically connected to the pixel driving circuit group PD.

[0133] In the second pixel driver circuit group PD2 and the electrically connected sub-route group LA located in the second display area AA2, the first signal lines L1 in the sub-route group LA are electrically connected to the second pixel driver circuit group PD2. The first signal lines L1 extend to the first peripheral area NA1 and are electrically connected to corresponding bonding pads BP. The first signal lines L1 are configured to receive data signals provided by the bonding pads BP and connect the data signals to the pixel driver circuit group PD. In other words, each of the first signal lines L1 located in the second display area AA2 functions as a data signal line for transmitting data signals.

[0134] In this display substrate, each pixel driving circuit group PD in the first display area AA1 close to the peripheral area NA is connected to the data signal through the corresponding sub-route group LA, but the sub-route group LA is not directly electrically connected to the binding pad BP. Instead, it is electrically connected to the binding pad BP in sequence through the first transfer route LT1 and the second transfer route LT2 set in the display area. In this way, there is no need to set a fan-out route for transferring data signals in the first frame area, that is, the technology of setting the fan-out route in the display area (Fanout In AA, abbreviated as FIAA in English) is adopted, which effectively narrows the width of the first peripheral area NA1, thereby meeting the requirements of the narrow-frame display substrate.

[0135] On the other hand, the first power signal line VDD is not directly connected to the pixel driving circuit group PD. Instead, the first power signal line VDD is electrically connected to the third signal line L3, and then the first power signal is respectively connected to the pixel driving circuit unit PD by the third signal line L3. This arrangement is equivalent to reducing the number of connection structures in the first power signal line VDD for transferring the first power signal to the pixel driving circuit group PD by half, thereby reducing the layout space of the first power signal line VDD to alleviate the problem of tight wiring space in the first conductive layer.

[0136] On this basis, it is possible to further provide a second signal line L2 on each side of the first power signal line VDD along the first direction, so that the number of second signal lines L2 is set to be the same as the number of pixel drive circuit groups PD, that is, the number of second signal lines L2 is set to be larger, thereby reducing the space occupied by the second transfer lines LT2. Accordingly, the layout space of the remaining second signal lines L2 not used as the second transfer lines LT2 is also increased, so that the layout space of the second signal lines L2 that can be used to transmit other constant voltage signals is larger, which is conducive to improving the uniformity of the distribution of the transmitted constant voltage signal in the display area. For example, the constant voltage signal here can be the second power signal or the first power signal.

[0137] According to some exemplary embodiments, referring to FIG. 4 , the first power signal line VDD includes a plurality of signal blocks V1 spaced apart along a second direction Y. Adjacent signal blocks V1 are electrically connected via a signal connection segment V2. A size of the signal blocks V1 along the first direction X is significantly larger than a size of the signal connection segment V2 along the first direction X. For example, the size of the signal blocks V1 along the first direction X is greater than twice the size of the signal connection segment V2 along the first direction X.

[0138] For example, the display substrate further includes a first electrode layer located on a side of the second conductive layer away from the base substrate. The first electrode layer includes a first electrode, which serves as the anode of the light-emitting device in the sub-pixel. The orthographic projection of the signal block on the base substrate partially overlaps with the orthographic projection of the first electrode on the base substrate. In addition to transmitting the first power signal, the signal block V1 also serves to level the first electrode.

[0139] FIG8 schematically shows a plan view of a combination of a first conductive layer and a second conductive layer in a display panel according to an embodiment of the present disclosure.

[0140] 8 , the first insulating layer has a first via H01 between the signal connection section V2 and the third signal line L3 , and the signal connection section V2 is electrically connected to the third signal line L3 through the first via H01 .

[0141] According to some exemplary embodiments, referring to FIG4 , the signal block V1 includes a first portion V11 and a second portion V12 arranged along a first direction X, the first portion V11 and the second portion V12 are directly connected, and the signal connection segment V2 is directly connected to both the first portion V11 and the second portion V12.

[0142] For example, the first portion V11 and the second portion V12 are substantially mirror-imaged along the first direction X, and the signal connection segment V2 is directly connected to both the first portion V11 and the second portion V12 , that is, the signal connection segment V2 is approximately centrally connected to the signal block V1 .

[0143] It should be noted that the first part V11 and the second part V12 are completely mirror-imaged in the theoretical design. However, due to factors such as process accuracy, there will be certain deviations in the shapes of the first part V11 and the second part V12. Here, basically mirror-imaged can be understood as the size deviation of the first part V11 and the second part V12 being within ±10% or ±5%.

[0144] Similarly, the signal connection segment V2 being approximately connected to the center of the signal block V1 can be understood as the connection position of the signal connection segment V2 and the signal block V1 deviating from the center of the signal block V1 by ±10% or ±5%.

[0145] According to some exemplary embodiments, referring to FIG4 , the signal block V1 includes a first sub-block V1a, a second sub-block V1b, and a third sub-block V1c arranged along the second direction Y, the first sub-block V1a is directly connected to the second sub-block V1b, and the size of the first sub-block V1a along the first direction X is smaller than the size of the second sub-block V1b along the first direction X, the second sub-block V1b is directly connected to the third sub-block V1c, and the size of the second sub-block V1b along the first direction X is smaller than the size of the third sub-block V1c along the first direction X.

[0146] The first signal line L1 includes multiple first connection blocks L11, which are located on a side of the adjacent second signal line L2 away from the second sub-block V1b. The second signal line L2 includes multiple second connection blocks L21, which are adjacent to the first sub-block V1a.

[0147] That is, the shape of the signal block V1 is stepped. In areas where space is allowed, the width of the signal block V1 is wider. In areas where other structures are provided, such as the first connection block L11 or the first connection block L11, the width of the signal block V1 is correspondingly narrowed.

[0148] According to some exemplary embodiments, the second signal trace L2 includes a second signal segment L22 connected between two adjacent second connection blocks L21. The second signal segment L22 includes a first sub-segment L221, a second sub-segment L222, and a third sub-segment L223 arranged along the second direction Y. A portion of the first sub-segment L221 is adjacent to the second sub-block V1b, a portion of the second sub-segment L222 is adjacent to the third sub-block V1c, and the third sub-segment L223 is connected and arranged between the first sub-segment L221 and the second sub-segment L222.

[0149] The first subsegment L221 and the second subsegment L222 extend along the second direction Y. The second subsegment L222 is closer to the adjacent first signal line L1 than the first subsegment L221. One end of the third subsegment L223 is connected to the first subsegment L221 and extends along the third direction until the other end is connected to the second subsegment L222. The third direction intersects the second direction Y. The second signal segment L22 is configured as a zigzag line, with at least a portion of the second signal segment L22 configured to bend conformally with the edge of the signal block V1. This helps reduce the wiring space for the second signal line L2, thereby allowing a second signal line L2 to be provided on either side of a first power signal line VDD along the first direction X.

[0150] According to some exemplary embodiments, the first signal line L1 includes a first signal segment L12 connected between two adjacent first connection blocks L11 , and the first signal segment L12 is a straight line extending along the second direction.

[0151] According to some exemplary embodiments, the first conductive layer further includes a plurality of anode connection portions 71, with one anode connection portion 71 provided on each side of the signal connection segment V2 along the first direction X. Because the signal connection segment V2 is approximately centrally connected to the signal block V1 and is relatively narrow, there is ample space on both sides of the signal connection segment V2 along the first direction X for providing the anode connection portion 71. The anode connection portion 71 is used to electrically connect the first electrode of the light-emitting device, i.e., the anode of the light-emitting device, to the pixel driving circuit unit.

[0152] According to some exemplary embodiments, referring to FIG8 , the display substrate further includes a second insulating layer located on a side of the first conductive layer away from the base substrate, and a first electrode layer located on a side of the second insulating layer away from the base substrate. The second insulating layer has a plurality of second via holes H02, and the first electrode layer is electrically connected to the anode connection portion 71 through the second via holes H02. The orthographic projection of the first via hole H01 on the base substrate is located between the orthographic projections of two adjacent second via holes H02 on the base substrate.

[0153] According to some exemplary embodiments, the pixel driving circuit unit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, or 8T2C structure.

[0154] FIG9 schematically shows an equivalent circuit diagram of a pixel driving circuit unit according to an embodiment of the present disclosure.

[0155] 9 , the pixel driving circuit unit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor C. The pixel driving circuit is electrically connected to a first power signal line VDD, a second power signal line VSS, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a first initialization signal line Vinit1, and a second initialization signal line Vinit2, respectively.

[0156] For example, as shown in Figure 12, the first transistor T1 is a first reset transistor, the second transistor T2 is a threshold compensation transistor, the third transistor T3 is a driving transistor, the fourth transistor T4 is a data writing transistor, the fifth transistor T5 is a second light-emitting control transistor, the sixth transistor T6 is a first light-emitting control transistor, and the seventh transistor T7 is a second reset control transistor.

[0157] For example, the first electrode of the first transistor T1 is electrically connected to the N1 node, that is, electrically connected to the gate electrode of the third transistor T3, the second electrode of the first transistor T1 is electrically connected to the first initialization signal line Vinit1 to receive the first initialization signal, and the gate electrode of the first transistor T1 is electrically connected to the first scan signal line S1 to receive the first scan signal.

[0158] The second transistor T2 is also a threshold compensation transistor. The first electrode of the second transistor T2 is electrically connected to the N1 node, that is, electrically connected to the gate electrode of the third transistor T3. The second electrode of the second transistor T2 is electrically connected to the N3 node, that is, the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3. The gate electrode of the second transistor T2 is electrically connected to the second scan signal line S2 to receive the second scan signal.

[0159] A gate electrode of the third transistor T3 is electrically connected to the N1 node, so as to be electrically connected to the first plate of the storage capacitor C, the first electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0160] The fourth transistor T4 is also the data writing transistor. The first electrode of the fourth transistor T4 is electrically connected to the data signal line Data to receive the data signal. The second electrode of the fourth transistor T4 is electrically connected to the second node N2, that is, the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the third transistor T3. The gate electrode of the fourth transistor T4 is electrically connected to the third scan signal line S3 to receive the third scan signal.

[0161] The fifth transistor T5 is also the second light-emitting control transistor. The first electrode of the fifth transistor T5 is electrically connected to the first power signal line VDD to receive the first power signal. The second electrode of the fifth transistor T5 is electrically connected to the second node N2, that is, the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The gate electrode of the fifth transistor T5 is electrically connected to the fourth scan signal line S4 to receive the fourth scan signal.

[0162] The sixth transistor T6 is also the first light-emitting control transistor. A first electrode of the sixth transistor T6 is electrically connected to the N3 node, i.e., the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3. A second electrode of the sixth transistor T6 is electrically connected to the fourth node N4, i.e., the second electrode of the sixth transistor T6 is electrically connected to the anode of the light-emitting device 120. A gate electrode of the sixth transistor T6 is electrically connected to the fourth scan signal line S4 to receive a fourth scan signal. The gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 can both be electrically connected to the fourth scan signal line S4 to receive the same scan signal. The gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 can also be electrically connected to different scan signal lines to receive different scan signals.

[0163] A first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line Vinit2 to receive the second initialization signal. A second electrode of the seventh transistor T7 is electrically connected to the fourth node N4, i.e., the second electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting device 120. A gate electrode of the seventh transistor T7 is electrically connected to the third scan signal line S3 to receive the third scan signal. The gate electrode of the seventh transistor T7 and the gate electrode of the fourth transistor T4 can both be electrically connected to the third scan signal line S3 to receive the same scan signal. The gate electrode of the seventh transistor T7 and the gate electrode of the fourth transistor T4 can also be electrically connected to different scan signal lines to receive different scan signals.

[0164] The first plate of the storage capacitor C is electrically connected to the N1 node, ie, electrically connected to the gate electrode of the third transistor T3 , and the second plate of the storage capacitor C is electrically connected to the first power signal line VDD.

[0165] The pixel driving circuit unit can be electrically connected to the light-emitting device 120 in the sub-pixel. The light-emitting device 120 can be an organic light-emitting diode (OLED). The pixel driving circuit is used to drive the light-emitting device 120 to emit light. The light-emitting device 120 can be electrically connected between the second electrode of the sixth transistor T6 and the second power signal line VSS.

[0166] For example, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors. Exemplarily, the first transistor T1 and the second transistor T2 may be N-type transistors, and the third transistor T3 to the seventh transistor T7 may be P-type transistors.

[0167] For example, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon transistors, or oxide transistors, or low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0168] For example, the first transistor T1 and the second transistor T2 may be metal oxide transistors, and the third transistor T3 to the seventh transistor T7 may be low temperature polysilicon transistors.

[0169] For example, the first power signal line VDD refers to a signal line that outputs a first power signal and can be electrically connected to a voltage source to output a constant voltage signal, such as a positive voltage signal. The second power signal line VSS refers to a signal line that outputs a second power signal and can be electrically connected to a voltage source to output a constant voltage signal, such as a negative voltage signal.

[0170] It should be noted that FIG9 exemplarily shows a circuit diagram of a pixel driving circuit unit, but the embodiments of the present disclosure are not limited thereto and can be replaced with other conventional pixel driving circuit units in the art according to actual needs.

[0171] According to some exemplary embodiments, the display substrate includes a base substrate, a first active layer located on the base substrate, a first gate insulating layer located on a side of the first active layer away from the base substrate, a first gate metal layer located on a side of the first gate insulating layer away from the base substrate, a second gate insulating layer located on a side of the first gate metal layer away from the base substrate, a second gate metal layer located on a side of the second gate insulating layer away from the base substrate, a third gate insulating layer located on a side of the second gate metal layer away from the base substrate, a second active layer located on a side of the third gate insulating layer away from the base substrate, a fourth gate insulating layer located on a side of the second active layer away from the base substrate, and a A third gate metal layer, an interlayer insulating layer located on the side of the third gate metal layer away from the substrate, a first source-drain metal layer located on the side of the interlayer insulating layer away from the substrate, a passivation layer located on the side of the first source-drain metal layer away from the substrate, a first planarizing layer located on the side of the passivation layer away from the substrate, a second source-drain metal layer located on the side of the first planarizing layer away from the substrate, a second planarizing layer located on the side of the second source-drain metal layer away from the substrate, a third source-drain metal layer located on the side of the second planarizing layer away from the substrate, a third planarizing layer located on the side of the third source-drain metal layer away from the substrate, and a first electrode layer located on the side of the third planarizing layer away from the substrate. The first conductive layer is the third source-drain metal layer, the second conductive layer is the second source-drain metal layer, and the first insulating layer is the second planarizing layer.

[0172] 10A to 10J are plan views of some film layers in a display substrate located in a display area according to some exemplary embodiments of the present disclosure;

[0173] 10A illustrates a combination of a first active layer and a first gate metal layer; FIG. 10B illustrates a second gate metal layer; FIG. 10C illustrates a combination of a first active layer, a first gate metal layer, and a second gate metal layer; FIG. 10D illustrates a combination of a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, and a third gate metal layer; FIG. 10E illustrates a first source / drain metal layer; FIG. 10F illustrates a combination of a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, and a A combination of a first source-drain metal layer; Figure 10G illustrates the second source-drain metal layer; Figure 10H illustrates the combination of the first active layer, the first gate metal layer, the second gate metal layer, the second active layer, the third gate metal layer, the first source-drain metal layer and the second source-drain metal layer; Figure 10I illustrates the third source-drain metal layer; Figure 10J illustrates the combination of the first active layer, the first gate metal layer, the second gate metal layer, the second active layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer and the third source-drain metal layer.

[0174] 10A , the first active layer Poly may include at least a third active portion of the third transistor T3, a fourth active portion of the fourth transistor T4, a fifth active portion of the fifth transistor T5, a sixth active portion of the sixth transistor T6, and a seventh active portion of the seventh transistor T7, and the third through seventh active portions in a single pixel driving circuit are interconnected as an integrated structure. It should be noted that in FIG10A , the seventh active portion of the seventh transistor T7 is the active portion structure of the pixel driving circuit located in the Mth row, while the third through sixth active portions of the third through sixth transistors T3 through T6, which are connected as an integrated structure, are the active portion structure of the pixel driving circuit located in the M+1th row. Therefore, the third through seventh active portions are spaced apart from each other, but in a single pixel driving circuit, the third through seventh active portions are interconnected as an integrated structure.

[0175] The active portion of each transistor includes a channel portion and first and second electrodes located on either side of the channel portion. The first active layer Poly includes the third channel portion 23, first electrode 23S, and second electrode 23D of the third transistor T3; the fourth channel portion 24, first electrode 24S, and second electrode 24D of the fourth transistor T4; the fifth channel portion 25, first electrode 25S, and second electrode 25D of the fifth transistor T5; the sixth channel portion 26, first electrode 26S, and second electrode 26D of the sixth transistor T6; and the fifth channel portion 27, first electrode 27S, and second electrode 27D of the seventh transistor T7.

[0176] In an exemplary embodiment, a first electrode 23S of the third transistor T3, a second electrode 24D of the fourth transistor T4, and a second electrode 25D of the fifth transistor T5 are all connected to the second node N2. A second electrode 23D of the third transistor T3 and a first electrode 26S of the sixth transistor T6 are all connected to the third node N3. A second electrode 26D of the sixth transistor T6 and a second electrode 27D of the seventh transistor T7 are all connected to the fourth node N4.

[0177] In an exemplary embodiment, the material of the first active layer Poly may be low-temperature polysilicon, that is, the third transistor T3 to the seventh transistor T7 are low-temperature polysilicon thin film transistors.

[0178] It should be noted that the first and second electrodes of each of the above-mentioned transistors can be structurally symmetrical, so the first electrode and the second electrode can be physically indistinguishable. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate electrode serving as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, the first and second electrodes of all or some of the transistors in the embodiments of the present disclosure can be interchanged as needed. For example, the first electrode is the source electrode and the second electrode is the drain electrode.

[0179] 10A , the first gate metal layer Gate1 at least includes a third scan signal line S3 , a fourth scan signal line S4 and a first conductive portion 31 .

[0180] In an exemplary embodiment, the first conductive portion 31 may be rectangular, with chamfered corners. The orthographic projection of the first conductive portion 31 on the substrate at least partially overlaps with the orthographic projection of the third active portion of the third transistor T3 on the substrate. The overlapping portion of the third active portion and the first conductive portion 31 serves as the third channel portion 23 of the third transistor T3, and the first conductive portion 31 serves as the gate electrode of the third transistor T3. For example, the first conductive portion 31 may also serve as the first plate of a storage capacitor.

[0181] In an exemplary embodiment, the third scan signal line S3 may be shaped like a zigzag line, with the main portion extending along the first direction X. The region where the third scan signal line S3 overlaps with the fourth channel portion 24 of the fourth transistor T4 may serve as the gate electrode of the fourth transistor T4. The third scan signal line S3 is used to provide a scan signal to the gate electrode of the fourth transistor T4. The region where the third scan signal line S3 overlaps with the seventh channel portion 27 of the seventh transistor T7 may serve as the gate electrode of the seventh transistor T7. The third scan signal line S3 is used to provide a scan signal to the gate electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 and the gate electrode of the fourth transistor T4 may be supplied with a scan signal by the same scan signal line.

[0182] In an exemplary embodiment, the fourth scan signal line S4 may be shaped like a zigzag line with a main portion extending along the first direction X. The region where the fourth scan signal line S4 overlaps with the fifth channel portion 25 of the fifth transistor T5 may serve as the gate electrode of the fifth transistor T5, and the region where the fourth scan signal line S4 overlaps with the sixth channel portion 26 of the sixth transistor T6 may serve as the gate electrode of the sixth transistor T6. The fourth scan signal line S4 is used to provide scan signals to the gate electrodes of the fifth transistor T5 and the sixth transistor T6, respectively.

[0183] In an exemplary embodiment, the third scanning signal line S3 and the fourth scanning signal line S4 can be designed with unequal widths, with the width being the dimension in the second direction Y, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. This is not limited in the present disclosure.

[0184] In an exemplary embodiment, after forming the first gate metal layer Gate1, the first active layer Poly can be conductorized using the first gate metal layer Gate1 as a shield. The portion of the first active layer Poly in the area shielded by the first gate metal layer Gate1 forms the channel portion of the third transistor T3 to the seventh transistor T7, and the portion of the first active layer Poly in the area not shielded by the first gate metal layer Gate1 is conductorized, that is, forming the first electrode and the second electrode of the third transistor T3 to the seventh transistor T7.

[0185] 10B , the second gate metal layer Gate2 at least includes a first scan signal line S11 , a second scan signal line S21 , a first initialization signal line Vinit1 , a second conductive portion 41 and a connecting trace 42 .

[0186] In an exemplary embodiment, the first scan signal line S11 may be in the shape of a line with a main portion extending along the first direction X. The first scan signal line S11 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between signal lines.

[0187] The second scan signal line S21 may be in the shape of a line with a main portion extending along the first direction X. The second scan signal line S21 may be designed with non-uniform widths, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between signal lines.

[0188] The first initialization signal line Vinit1 can be in the shape of a line with its main portion extending along the first direction X. The first initialization signal line Vinit1 can be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between signal lines. The first initialization signal line Vinit1 is used to electrically connect to the second electrode of the first transistor via a subsequently formed connection structure.

[0189] In an exemplary embodiment, the outline of the second conductive portion 41 can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second conductive portion 41 on the substrate at least partially overlaps with the orthographic projection of the first conductive portion 31 on the substrate. The second conductive portion 41 can serve as the second plate of the storage capacitor, and the first conductive portion 31 and the second conductive portion 41 together constitute the storage capacitor of the pixel driving circuit.

[0190] In an exemplary embodiment, referring to FIG. 10B and FIG. 10C , an opening 411 is provided on the second conductive portion 41. The opening 411 may be rectangular and located in the middle of the second conductive portion 41, forming a ring-shaped structure. The orthographic projection of the opening 411 on the substrate is located within the orthographic projection of the first conductive portion 31 on the substrate.

[0191] In an exemplary embodiment, two adjacent second conductive portions 41 along the first direction may be interconnected as a single unit. For example, the second conductive portion 41 in the Nth column and the second conductive portion 41 in the N+1th column are interconnected via a connecting trace 42. Because the second conductive portion 41 in each pixel driving circuit unit is electrically connected to a subsequently formed first power signal line, by forming the second conductive portions 41 of adjacent pixel driving circuit units into a single unit, it is possible to ensure that the multiple second plates in a unit row have the same potential, which is beneficial for improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display quality of the display substrate.

[0192] 10D , the second active layer IGZO may include a first active portion of the first transistor T1 and a second active portion of the second transistor T2, namely, the first channel portion 21, first electrode 21S, and second electrode 21D of the first transistor T1, and the second channel portion 22, first electrode 22S, and second electrode 22D of the second transistor T2. The first electrode 21S of the first transistor T1 is connected to the first electrode 22S of the second transistor T2, and the first active portion of the first transistor T1 is connected to the second active portion of the second transistor T2 to form an integrated structure.

[0193] In this exemplary embodiment, referring to FIG10B , the region where the first scan signal line S11 of the first gate metal layer Gate1 overlaps with the first channel portion 21 of the first transistor T1 may serve as the bottom gate electrode of the first transistor T1. Furthermore, the first scan signal line S11 may also serve as a shielding portion for the first transistor T1, shielding the first channel portion 21 of the first transistor T1 and ensuring the electrical performance of the first transistor T1.

[0194] In this exemplary embodiment, referring to FIG10B , the region where the second scan signal line S21 on the first gate metal layer Gate1 overlaps with the second channel portion 22 of the second transistor T2 can serve as the bottom gate electrode of the second transistor T2. Furthermore, the second scan signal line S21 can also serve as a shielding portion for the second transistor T2, shielding the second channel portion 22 of the second transistor T2 and ensuring the electrical performance of the second transistor T2.

[0195] In an exemplary embodiment, the second active layer may be made of an oxide semiconductor material, i.e., the first transistor T1 and the second transistor T2 are oxide transistors. For example, the second active layer may be made of indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0196] 10D , the third gate metal layer Gate3 may include a first scan signal line S12 and a second scan signal line S22 .

[0197] In an exemplary embodiment, the first scan signal line S12 may be in the shape of a line with a main portion extending along the first direction X. The region where the first scan signal line S12 overlaps with the first channel portion 21 of the first transistor T1 may serve as the top gate electrode of the first transistor T1. The first scan signal line S12 located on the third gate metal layer Gate3 and the first scan signal line S11 located on the first gate metal layer Gate1 may be configured to receive the same voltage signal. For example, the first scan signal line S12 located on the third gate metal layer Gate3 and the first scan signal line S11 located on the first gate metal layer Gate1 may be electrically connected in a peripheral region of the display substrate.

[0198] In an exemplary embodiment, the second scan signal line S22 may be in the shape of a line with a main portion extending along the first direction X. The region where the second scan signal line S22 overlaps with the second channel portion 22 of the second transistor T2 may serve as the top gate electrode of the second transistor T2. The second scan signal line S22 located on the third gate metal layer Gate3 and the second scan signal line S21 located on the first gate metal layer Gate1 may be configured to receive the same voltage signal. For example, the second scan signal line S22 located on the third gate metal layer Gate3 and the second scan signal line S21 located on the first gate metal layer Gate1 may be electrically connected in a peripheral region of the display substrate.

[0199] 10E , the first source / drain metal layer SD1 may include a first connection structure 51 , a second connection structure 52 , a third connection structure 53 , a fourth connection structure 54 , a fifth connection structure 55 and a second initialization signal line Vinit2 .

[0200] 10F , the second initialization signal line Vinit2 may be in the shape of a line with its main portion extending along the first direction X. The second initialization signal line Vinit2 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces parasitic capacitance between signal lines.

[0201] Referring to Figure 10F and Figure 10A, the orthographic projection of the second initialization signal line Vinit2 on the base substrate partially overlaps with the orthographic projection of the second electrode 27D of the seventh transistor T7 on the base substrate, and a ninth via hole H19 is provided in the overlapping area. The ninth via hole H19 is located in the first gate insulation layer, the second gate insulation layer, the third gate insulation layer, the fourth gate insulation layer and the interlayer insulation layer. The second initialization signal line Vinit2 is electrically connected to the second electrode 27D of the seventh transistor T7 through the ninth via hole H19 to connect the second initialization signal to the second electrode 27D of the seventh transistor T7.

[0202] Referring to Figure 10F and Figure 10A, the overlapping area of ​​the orthographic projection of the first connection structure 51 on the substrate and the orthographic projection of the first active layer Poly on the substrate is the area where the fourth node N4 is located. A first via hole H11 is provided in the overlapping area. The first via hole H11 is located in the first gate insulation layer, the second gate insulation layer, the third gate insulation layer, the fourth gate insulation layer and the interlayer insulation layer. The first connection structure 51 is electrically connected to the fourth node N4 of the first active layer Poly through the first via hole H11. The first connection structure 51 is also used to be electrically connected to other connection structures formed subsequently, so as to ultimately achieve electrical connection between the fourth node N4 and the anode of the light-emitting device.

[0203] 10F and 10D , the orthographic projection of the second connection structure 52 on the substrate partially overlaps with the orthographic projection of the first initialization signal line Vinit1 on the substrate. A second via H12 is provided in the overlapping region. The second via H12 is located in the third gate insulating layer, the fourth gate insulating layer, and the interlayer insulating layer. The second connection structure 52 is electrically connected to the first initialization signal line Vinit1 through the second via H12. Furthermore, the orthographic projection of the second connection structure 52 on the substrate partially overlaps with the orthographic projection of the second electrode 21D of the first transistor T1 on the substrate. A third via H13 is provided in the overlapping region. The third via H13 is located in the fourth gate insulating layer and the interlayer insulating layer. The second connection structure 52 is electrically connected to the second electrode 21D of the first transistor T1 through the third via H13. That is, the second connection structure 52 is electrically connected to the first initialization signal line Vinit1 and the second electrode 21D of the first transistor T1, respectively, thereby realizing the electrical connection between the first initialization signal line Vinit1 and the second electrode 21D of the first transistor T1, so that the first initialization signal line Vinit1 is connected to the second electrode 21D of the first transistor T1.

[0204] Referring to Figure 10F and Figure 10A, the orthographic projection of the third connection structure 53 on the substrate partially overlaps with the orthographic projection of the first electrode 24S of the fourth transistor T4 on the substrate, and a fourth via hole H14 is provided in the overlapping area. The fourth via hole H14 is located in the first gate insulation layer, the second gate insulation layer, the third gate insulation layer, the fourth gate insulation layer and the interlayer insulation layer. The third connection structure 53 is electrically connected to the first electrode 24S of the fourth transistor T4 through the fourth via hole H14. The first connection structure 51 is also used to be electrically connected to a data signal line formed subsequently, so that the data signal line can access the data signal to the first electrode 24S of the fourth transistor T4.

[0205] 10F and 10C , the orthographic projection of the fourth connection structure 54 on the substrate at least partially overlaps with the orthographic projection of the opening 411 on the substrate, and a fifth via H15 is provided in the overlapping area. The fifth via H15 is located in the second gate insulation layer, the third gate insulation layer, the fourth gate insulation layer and the interlayer insulation layer. The fourth connection structure 54 is electrically connected to the first conductive portion 31 through the fifth via H15, that is, the fourth connection structure 54 is electrically connected to the gate electrode of the third transistor.

[0206] With reference to Figures 10F and 10D , the orthographic projection of the fourth connection structure 54 on the substrate partially overlaps with the orthographic projection of the second active layer IGZO on the substrate, and the connection point between the first electrode 21S of the first transistor T1 and the first electrode 22S of the second transistor T2 is located in this overlapping region. A sixth via H16 is provided in this overlapping region. This sixth via H16 is located in the fourth gate insulating layer and the interlayer insulating layer. The fourth connection structure 54 is electrically connected to both the first electrode 21S of the first transistor T1 and the first electrode 22S of the second transistor T2 through this sixth via H16.

[0207] That is, one end of the fourth connection structure 54 is electrically connected to the gate electrode of the third transistor, and the other end is electrically connected to the first electrode 21S of the first transistor T1 and the first electrode 22S of the second transistor T2, thereby realizing an electrical connection between the first electrode 21S of the first transistor T1 and the gate electrode of the third transistor, and realizing an electrical connection between the first electrode 22S of the second transistor T2 and the gate electrode of the third transistor.

[0208] Referring to Figure 10F and Figure 10A, the overlapping area of ​​the orthographic projection of the fifth connection structure 55 on the substrate and the orthographic projection of the first active layer Poly on the substrate is the area where the third node N3 is located. A seventh via H17 is provided in the overlapping area. The seventh via H17 is located in the first gate insulation layer, the second gate insulation layer, the third gate insulation layer, the fourth gate insulation layer and the interlayer insulation layer. The fifth connection structure 55 is electrically connected to the third node N3 of the first active layer Poly through the seventh via H17.

[0209] 10F and 10D , the orthographic projection of the fifth connection structure 55 on the substrate partially overlaps with the orthographic projection of the second electrode 22D of the second transistor T2 on the substrate, and an eighth via hole H18 is provided in the overlapping area. The eighth via hole H18 is located in the fourth gate insulation layer and the interlayer insulation layer, and the fifth connection structure 55 is electrically connected to the second electrode 22D of the second transistor T2 through the eighth via hole H18.

[0210] That is, one end of the fifth connection structure 55 is electrically connected to the third node N3 of the first active layer Poly, and the other end is electrically connected to the second electrode 22D of the second transistor T2, thereby achieving electrical connection between the second electrode 22D of the second transistor T2 and the third node N3.

[0211] 10G , the second source / drain metal layer SD2 may include a third signal trace L3 , a fourth signal trace L4 , a first connection structure 61 , and a second connection structure 62 .

[0212] 10H and 10F , the orthographic projection of the first connection structure 61 on the substrate at least partially overlaps with the orthographic projection of the third connection structure 53 located on the first source / drain metal layer SD1. A first via H21 is provided in the overlapping region. The first via H21 is located between the passivation layer and the first planarization layer. The first connection structure 61 is electrically connected to the third connection structure 53 through the first via H21. Because the third connection structure 53 is electrically connected to the first electrode 24S of the fourth transistor T4, the first connection structure 61 is also electrically connected to the first electrode 24S of the fourth transistor T4.

[0213] 10H and 10F , the orthographic projection of the second connection structure 62 on the substrate at least partially overlaps with the orthographic projection of the first connection structure 51 located on the first source / drain metal layer SD1. A second via H22 is provided in the overlapping region. The second via H22 is located between the passivation layer and the first planarization layer. The second connection structure 62 is electrically connected to the first connection structure 51 through the second via H22. Because the first connection structure 51 is electrically connected to the fourth node N4 of the first active layer Poly, the second connection structure 62 is electrically connected to the fourth node N4 of the first active layer Poly.

[0214] 10H and 10A , the orthographic projection of the third signal line L3 on the substrate at least partially overlaps with the orthographic projection of the first electrode 25S of the fifth transistor T5 on the substrate, and a third via H23 is provided in the overlapping area, through which the third signal line L3 is electrically connected to the first electrode 25S of the fifth transistor T5.

[0215] 10I , the third source-drain metal layer SD3 may include an anode connection portion 71 , a first power signal line VDD, a first signal line L1 , and a second signal line L2 .

[0216] With reference to Figures 10J and 10H , the orthographic projection of the anode connection portion 71 on the substrate at least partially overlaps with the orthographic projection of the second connection structure 62 located in the second source / drain metal layer SD2. A first via H31 is provided in this overlapping region. This first via H31 is located in the second planarization layer, and the anode connection portion 71 is electrically connected to the second connection structure 62 located in the second source / drain metal layer SD2 through this first via H31. Furthermore, because the second connection structure 62 is electrically connected to the fourth node N4 of the first active layer Poly, the anode connection portion 71 is electrically connected to the fourth node N4 of the first active layer Poly. The anode connection portion 71 is also electrically connected to the first electrode in the first electrode layer, that is, to the anode of the light-emitting device, ultimately electrically connecting the anode of the light-emitting device to the fourth node N4 of the first active layer Poly.

[0217] Referring to Figure 10J, the orthographic projection of the first power signal line VDD on the substrate partially overlaps with the orthographic projection of the third signal line L3 on the substrate. A second via H32 is provided in the overlapping area. The second via H32 is located in the second planarization layer. The first power signal line VDD is electrically connected to the third signal line L3 through the second via H32. Since the third signal line L3 is electrically connected to the first electrode of the fifth transistor, the first power signal line VDD connects the first power signal to the first electrode of the fifth transistor through the conversion of the third signal line L3.

[0218] On the other hand, a plurality of first power signal lines VDD extending along the second direction Y are electrically connected to a plurality of third signal lines L3 extending along the first direction X to form a grid of signal lines, which is beneficial to improving the distribution uniformity of the first power signal in the display area.

[0219] With reference to Figures 10J and 10H , in the pixel driving circuit unit located in the second display area, the orthographic projection of the first signal line L1 on the substrate at least partially overlaps with the orthographic projection of the first connection structure 61 on the substrate. A via is provided in this overlapping area, through which the first signal line L1 is electrically connected to the first connection structure 61. Furthermore, because the first connection structure 61 is electrically connected to the first electrode of the fourth transistor, the first signal line L1 is electrically connected to the first electrode of the fourth transistor, allowing the first signal line L1 to connect the data signal to the first electrode of the fourth transistor. Here, the first signal line L1 serves as a data signal line. The connection method between the first signal line L1 in the first display area and other structures is detailed in other embodiments.

[0220] With reference to Figures 10J and 10H , the second signal lines L2 and L4, which are not used for transferring data signals, can be used to transmit constant voltage signals, such as the first power signal or the second power signal. For example, both the second signal lines L2 and L4 are used to transmit the second power signal. The second signal lines L2 and L4 are electrically connected via vias in the second planarization layer to form a grid of signal lines, which helps improve the uniformity of the distribution of the second power signal across the display area. The second signal lines L2 are electrically connected to the cathode of the light-emitting device in the peripheral area, thereby connecting the second power signal to the cathode of the light-emitting device.

[0221] According to some exemplary embodiments, a first pixel driving circuit groups are located in the first display area, the 1st pixel driving circuit group is closest to the second display area, and the ath first pixel driving circuit group is farthest from the second display area, where a is a positive integer less than 2n.

[0222] The first sub-routing group electrically connected to the first first pixel driving circuit group is electrically connected to the bonding pad via the first first transfer routing line and the first second transfer routing line, and the dth sub-routing group electrically connected to the dth first pixel driving circuit group is electrically connected to the bonding pad via the dth first transfer routing line and the dth second transfer routing line, where 2≤d≤a, and d is an integer. The first first transfer routing line is closer to the first peripheral area than the dth first transfer routing line, and the first second transfer routing line is closer to the first display area than the dth second transfer routing line.

[0223] 7 , 7 sub-routing groups electrically connected to the first pixel driving circuit group are schematically shown. Specifically, the first sub-routing group LA1 electrically connected to the first first pixel driving circuit group is electrically connected to the binding pad BP through the first first transfer routing line LT11 and the first second transfer routing line LT21; the second sub-routing group LA1 electrically connected to the second first pixel driving circuit group is electrically connected to the binding pad BP through the second first transfer routing line LT12 and the second second transfer routing line LT22; the third sub-routing group LA3 electrically connected to the third first pixel driving circuit group is electrically connected to the binding pad BP through the third first transfer routing line LT13 and the third second transfer routing line LT23; the fourth sub-routing group LA4 electrically connected to the fourth first pixel driving circuit group is electrically connected to the binding pad BP through the fourth first transfer routing line LT14 and the fourth second transfer routing line LT25. The first transfer trace LT14 and the fourth second transfer trace LT24 are electrically connected to the binding pad BP; the fifth sub-route group LA5 electrically connected to the fifth first pixel driving circuit group is electrically connected to the binding pad BP through the fifth first transfer trace LT15 and the fifth second transfer trace LT25; the sixth sub-route group LA6 electrically connected to the sixth first pixel driving circuit group is electrically connected to the binding pad BP through the sixth first transfer trace LT16 and the sixth second transfer trace LT26; the seventh sub-route group LA7 electrically connected to the seventh first pixel driving circuit group is electrically connected to the binding pad BP through the seventh first transfer trace LT17 and the seventh second transfer trace LT27.

[0224] The first transfer trace LT11 is closest to the first peripheral area NA1, and the seventh first transfer trace LT17 is farthest from the first peripheral area NA1. The first second transfer trace LT21 is closest to the first display area AA1, and the seventh second transfer trace LT27 is farthest from the first display area AA1.

[0225] FIG11 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0226] According to some exemplary embodiments, referring to FIG. 11 , a first insulating layer is provided between the first conductive layer and the second conductive layer. The first insulating layer has a plurality of third vias H03 and a plurality of fourth vias H04. The plurality of third vias H03 are located in the second display area AA2, and the plurality of fourth vias H04 are located in the first display area AA1. The second transfer trace LT2 is electrically connected to the bonding pad. The second transfer trace LT2 is electrically connected to the first transfer trace LT1 via the third via H03. The sub-trace group LA is electrically connected to the first transfer trace LT1 via the fourth via H04. In this manner, the electrical connection between the sub-trace group LA and the bonding pad is achieved.

[0227] Figure 11 exemplarily illustrates six first transfer traces LT1 and six second transfer traces LT2. The six first transfer traces LT1 are electrically connected to the six second transfer traces LT2 via six third vias H03. The six first transfer traces LT1 are electrically connected to the six sub-trace groups LA located in the first display area AA1 via six fourth vias H04. The specific number of first transfer traces LT1 and second transfer traces LT2 depends on actual process requirements and is not limited in this embodiment of the present disclosure.

[0228] According to some exemplary embodiments, referring to FIG. 11 , the second signal line L2 in the sub-line group LA located in the first display area AA1 is electrically connected to the first transfer line LT1 via the fourth via H04, and the second signal line L2 is electrically connected to the first pixel driver circuit group. After the data signal is connected to the second signal line L2 via the first transfer line LT1 and the second transfer line LT2, the second signal line L2 is directly electrically connected to the corresponding first pixel driver circuit group, thereby connecting the data signal to each pixel driver circuit unit in the first pixel driver circuit group. In other words, the second signal line L2 serves as the data signal line for the corresponding sub-pixel column. The first signal line L1 in the sub-line group LA does not participate in the data signal connection and can therefore be used to transmit other constant voltage signals required by the display substrate.

[0229] Figure 12A schematically illustrates a plan view of a first conductive layer and a second conductive layer in some display panels according to embodiments of the present disclosure, located in region A3 of Figure 1. Figure 12B schematically illustrates an enlarged schematic view of region C1 of Figure 12A. Figure 12C schematically illustrates an enlarged schematic view of region C4 of Figure 12A.

[0230] According to some exemplary embodiments, referring to Figures 12A and 12B, the second signal line L2 in the sub-line group LA located within the first display area AA1 is electrically connected to the first transfer line LT1 via a fourth via H04. The second signal line L2 is electrically connected to the first signal line L1 in the sub-line group LA via at least one bridge bar LQ. The first signal line L1 is electrically connected to each pixel driver circuit unit in the corresponding first pixel driver circuit group. After the data signal is connected to the second signal line L2 via the first transfer line LT1 and the second transfer line LT2, the data signal is then connected from the second signal line L2 to the first signal line L1 via the bridge bar LQ, and finally connected to each pixel driver circuit unit via the first signal line L1. With this arrangement, for both the first pixel driver circuit group located in the first display area AA1 and the second pixel driver circuit group located in the second display area AA2, data signals are connected to the pixel driver circuit units via the first signal line L1, ensuring consistency of the data signal lines in the first display area AA1 and the second display area AA2.

[0231] According to some exemplary embodiments, referring to Figures 12A and 12C , the bridge bar LQ is located on the first conductive layer. That is, the bridge bar LQ, the first signal trace L1, and the second signal trace L2 are located on the same layer, and the bridge bar LQ, the first signal trace L1, and the second signal trace L2 are connected as a single structure. The orthographic projection of the bridge bar LQ on the base substrate is located within the orthographic projection of the second conductive layer on the base substrate. By placing the bridge bar LQ in the area where the second conductive layer is located, that is, placing the bridge bar LQ in an area with a metal structure, the problem of display unevenness that can be detected by the human eye due to the installation of the bridge bar LQ can be effectively avoided.

[0232] In FIG12A , a bridge bar LQ is exemplarily shown in each sub-route group LA electrically connected to the first transfer route LT1. It should be understood that the first signal route L1 and the second signal route L2 can also be electrically connected through multiple bridge bars LQ. The embodiment of the present disclosure does not impose any special limitation on the bridge bar LQ.

[0233] According to some exemplary embodiments, referring to FIG. 12B , the orthographic projection of the bridge strip LQ on the substrate is located within the orthographic projection of the third signal trace L3 on the substrate.

[0234] Figure 13A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, located in area A3 in Figure 1. Figure 13B schematically shows an enlarged view of area C2 in Figure 13A.

[0235] According to some exemplary embodiments, referring to FIG. 13A and FIG. 13B , the orthographic projection of the bridge strip LQ on the substrate is located within the orthographic projection of the fourth signal trace L4 on the substrate.

[0236] Figure 14A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to embodiments of the present disclosure, located in area A3 in Figure 1. Figure 14B schematically shows an enlarged view of area C3 in Figure 14A.

[0237] According to some exemplary embodiments, referring to FIG. 14A and FIG. 14B , a portion of the orthographic projection of the bridge strip LQ on the substrate substrate is located within the orthographic projection of the fourth signal trace L4 on the substrate substrate, and a portion of the orthographic projection of the bridge strip LQ on the substrate substrate is located within the orthographic projection of the third signal trace L3 on the substrate substrate.

[0238] Figure 15A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to embodiments of the present disclosure located in area A3 in Figure 1. Figure 15B schematically shows an enlarged view of area C5 in Figure 15A.

[0239] According to some exemplary embodiments, referring to FIG. 15A , the first transfer trace LT1 has a first break K1 and a second break K2. The first break K1 is located on the side of the third via H03 away from the fourth via H04, and the second break K2 is located on the side of the fourth via H04 away from the third via H03. The first transfer trace LT1 has a first transfer segment LT1a that is interrupted between the first break K1 and the second break K2. The first transfer segment LT1a is used to transfer data signals, while the remaining portion of the first transfer trace LT1, excluding the first transfer segment LT1a, can be used to transmit other constant voltage signals required by the display substrate.

[0240] According to some exemplary embodiments, referring to FIG. 15A , the orthographic projections of the first break K1 and the second break K2 on the substrate are located within the orthographic projection of the first conductive layer on the substrate. By arranging the first break K1 and the second break K2 in an area where the first conductive layer is located, that is, by arranging the first break K1 and the second break K2 in an area with a metal structure, the occurrence of visually discernible display unevenness caused by the first break K1 and the second break K2 can be effectively avoided. For example, the orthographic projections of the first break K1 and the second break K2 on the substrate are located within the orthographic projection of the first power signal line VDD on the substrate.

[0241] According to some exemplary embodiments, the first crevices are spaced apart and arranged in a row along the second direction; and / or the second crevices are spaced apart and arranged in a row along the second direction. For example, referring to FIG15A , the first crevices K1 are spaced apart and arranged in a row along the second direction Y, and the second crevices K2 are spaced apart and arranged in a row along the second direction Y. This arrangement ensures that the lengths of the first transfer sections LT1a are equal, thereby ensuring that the loading of each first transfer section LT1a when transferring data signals is consistent.

[0242] According to some exemplary embodiments, referring to FIG. 15A , for the first transfer trace LT1 farthest from the first peripheral region (i.e., the topmost first transfer trace LT1 shown in the figure), the orthographic projection of the first break K1 in this first transfer trace LT1 on the substrate is located within the orthographic projection of the first power signal line VDD closest to the third via H03 on the substrate. The first breaks K1 in other first transfer traces LT1 closer to the first peripheral region are positioned according to the position of the first break K1 farthest from the first peripheral region, such that the first breaks K1 are arranged in a row along the second direction Y at intervals.

[0243] It should be understood that the orthographic projection of the first break K1 on the substrate is located within the orthographic projection of the first power signal line VDD on the substrate closest to the third via H03. The third via H03 here refers to the third via H03 that electrically connects the first transfer trace LT1 of the first break K1 with the second transfer trace LT2.

[0244] For the first transfer trace LT1 farthest from the first peripheral region (i.e., the topmost first transfer trace LT1 shown in the figure), the orthographic projection of the second break K2 in this first transfer trace LT1 on the substrate is located within the orthographic projection of the first power signal line VDD closest to the fourth via H04 on the substrate. The second breaks K2 in the other first transfer traces LT1 closer to the first peripheral region are positioned according to the position of the second break K2 farthest from the first peripheral region, so that the second breaks K2 are arranged in a row along the second direction Y with intervals therebetween.

[0245] It should be understood that the orthographic projection of the second break K2 on the substrate is located within the orthographic projection of the first power signal line VDD on the substrate closest to the fourth via H04. The fourth via H04 here refers to the fourth via H04 that electrically connects the first transfer trace LT1 of the second break K2 with the second signal trace L2.

[0246] According to some exemplary embodiments, referring to FIG15A , the second transfer trace LT2 has a third break K3, which is located on a side of the third via H03 away from the first peripheral area. Referring to FIG15B , the third break K3 divides the second transfer trace LT2 into two parts. The portion between the third break K3 and the binding pad (i.e., the portion located below the third break K3 shown in FIG15A ) serves as the second transfer segment LT2a, which is used to transfer data signals. The remaining portion (i.e., the portion located above the third break K3 shown in FIG15A ) does not participate in the transfer of data signals and can be used to transmit other constant voltage signals required by the display substrate.

[0247] According to some exemplary embodiments, referring to FIG. 15A , the orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the second conductive layer on the substrate. For example, the orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the third signal trace L3 on the substrate. By placing the third break K3 in the area where the second conductive layer is located, that is, placing the third break K3 in an area with a metal structure, the problem of display unevenness that can be detected by the human eye due to the placement of the third break K3 can be effectively avoided.

[0248] According to some exemplary embodiments, referring to FIG. 15A , the orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the third via H03 on the substrate. This minimizes the length of the second transfer section LT2a, i.e., minimizes the load on the second transfer section LT2a, while maintaining the ability of the second transfer section LT2a to transfer data signals. At the same time, the remaining portion of the second transfer trace LT2 available for transmitting other constant-voltage signals is maximized.

[0249] It should be understood that the orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the third signal trace L3 on the substrate closest to the third via H03. The third via H03 here refers to the third via H03 that electrically connects the second transfer trace LT2 of the third break K3 with the first transfer trace LT1.

[0250] According to some exemplary embodiments, referring to FIG. 15A , the second signal trace L2 in the sub-trace group is directly electrically connected to the first pixel driver circuit group. That is, the second signal trace L2 serves as the data signal line for the column of sub-pixels. Therefore, the load generated when the data signal is transferred from the bonding pad to the second signal trace L2 is generated by the first transfer section LT1a and the second transfer section LT2a.

[0251] Furthermore, the first breaks K1 are arranged in a row along the second direction Y, and the second breaks K2 are arranged in a row along the second direction Y. Furthermore, the orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the third via H03 on the substrate. In this way, the load on each first transfer segment LT1a remains consistent, and only the load on each second transfer segment LT2a varies. Therefore, when transmitting data signals to different first pixel driver circuit groups, the load difference is caused solely by the different lengths of the second transfer segments LT2a. In other words, there is only one factor causing the load difference, allowing the driver chip to compensate for the data signal accordingly.

[0252] Figure 16A schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to embodiments of the present disclosure, located in area A3 in Figure 1. Figure 16B schematically shows an enlarged view of area C6 in Figure 16A.

[0253] According to some exemplary embodiments, referring to Figure 16A, the second signal trace L2 electrically connected to the first transfer segment LT1a serves as the third transfer trace LT3. The third transfer trace LT3 is electrically connected to the first signal trace L1 in the sub-trace group LA through at least one bridge bar LQ. The first signal trace L1 is then electrically connected to the corresponding first pixel driving circuit group for connecting the data signal to each pixel driving circuit unit of the first pixel driving circuit group.

[0254] Referring to Figures 16A and 16B , the third transfer trace LT3 extends continuously from one end of the display area near the first peripheral area to the other end of the display area far from the first peripheral area. In other words, there is no break in the third transfer trace LT3. The third transfer trace LT3 is electrically connected to the adjacent first signal trace L1 via one or more bridge strips LQ, effectively connecting the third transfer trace LT3 and the first signal trace L1 in parallel. The resistance of the third transfer trace LT3 and the first signal trace L1, combined in parallel, is lower than that of the first signal trace L1 alone, thus mitigating IR drop during data signal transmission.

[0255] For example, referring to Figures 16A and 16B, for any third transfer trace LT3, a bridge bar LQ is set in all areas where the third signal trace L3 is provided to electrically connect the third transfer trace LT3 with the adjacent first signal trace L1, that is, the third transfer trace LT3 is electrically connected to the adjacent first signal trace L1 through multiple bridge bars LQ, and the orthographic projections of the multiple bridge bars LQ on the substrate are respectively located within the orthographic projections of the multiple third signal traces L3 on the substrate.

[0256] Based on this, whether or not to provide breaks on the first and second transfer traces LT1 and LT2 can be determined based on actual process requirements. For example, referring to Figure 16A , the first transfer trace LT1 is provided with a first break K1 and a second break K2, while the second transfer trace LT2 is provided with a third break K3. Specifically, the first breaks K1 are arranged in a row along the second direction Y, and the second breaks K2 are arranged in a row along the second direction Y. Furthermore, the orthographic projection of the third break K3 on the substrate lies within the orthographic projection of the third signal trace L3 closest to the third via H03.

[0257] FIG17 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0258] 17 , the third breaks K3 in the second transfer traces LT2 are arranged in a row along the first direction X. This arrangement ensures that the lengths of the second transfer segments LT2a are equal, thereby ensuring that the loads on the second transfer segments LT2a are consistent.

[0259] According to some exemplary embodiments, referring to FIG. 17 , for a second transfer trace LT2 farthest from the first display area AA1, the orthographic projection of the third break K3 in the second transfer trace LT2 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the third via H03 on the substrate. The third breaks K3 in other second transfer traces LT2 closer to the first display area AA1 are positioned according to the position of the third break K3 farthest from the first display area AA1, such that the third breaks K3 are arranged in a row along the first direction X at intervals.

[0260] It should be understood that the orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the third signal trace L3 on the substrate closest to the third via H03. The third via H03 here refers to the third via H03 that electrically connects the second transfer trace LT2 of the third break K3 with the first transfer trace LT1.

[0261] According to some exemplary embodiments, referring to FIG. 17 , the second signal trace L2 in the trace group is directly electrically connected to the first pixel driver circuit group. That is, the second signal trace L2 serves as the data signal line for the column of sub-pixels. Therefore, the load generated when the data signal is transferred from the bonding pad to the second signal trace L2 is generated on the first transfer section LT1a and the second transfer section LT2a.

[0262] Furthermore, the first breaks K1 are arranged in a row along the second direction Y, the second breaks K2 are arranged in a row along the second direction Y, and the third breaks K3 are arranged in a row along the first direction X. With this arrangement, the lengths of the first transfer sections LT1a and the second transfer sections LT2a are equal. Therefore, when transferring different second signal traces L2, the loads generated by the first transfer sections LT1a and the second transfer sections LT2a remain consistent.

[0263] FIG18 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A3 in FIG1 .

[0264] According to some exemplary embodiments, referring to FIG. 18 , the second signal trace L2 electrically connected to the first transfer trace LT1 is a third transfer trace LT3. The third transfer trace LT3 is located in the first display area AA1. The third transfer trace LT3 has a fourth break K4 and a fifth break K5. The fourth break K4 is located on the side of the fourth via H04 away from the first peripheral area, and the fifth break K5 is located on the side of the fourth via H04 closer to the first peripheral area. The third transfer trace LT3 includes a third transfer segment LT3a interrupted between the fourth break K4 and the fifth break K5. The third transfer segment LT3a is electrically connected to the adjacent first signal trace L1 via at least one bridge LQ. The first signal trace L1 is electrically connected to the corresponding first pixel driver circuit group to receive data signals.

[0265] At this time, the first signal line L1 serves as the data signal line of the column of sub-pixels. Therefore, when the data signal is transferred from the bonding pad to the first signal line L1, the load is generated on the first transfer section LT1a, the second transfer section LT2a, and the third transfer section LT3a.

[0266] Furthermore, the first breaks K1 are arranged in a row along the second direction Y, and the second breaks K2 are arranged in a row along the second direction Y. This arrangement ensures that the lengths of the first transfer sections LT1a are equal, thereby ensuring that the loads of the first transfer sections LT1a when transferring data signals are consistent.

[0267] In addition, the orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the third via H03 on the substrate. This ensures that the length of the second transfer section LT2a is kept as short as possible without affecting the data signal transfer function of the second transfer section LT2a, thereby minimizing the load on the second transfer section LT2a. Specifically, the second transfer section LT2a electrically connected to the first pixel driver circuit group closest to the second display area AA2 is the shortest, i.e., the second transfer section LT2a electrically connected to the first signal trace L1 closest to the second display area AA2 is the shortest; the second transfer section LT2a electrically connected to the first pixel driver circuit group farthest from the second display area AA2 is the longest, i.e., the second transfer section LT2a electrically connected to the first signal trace L1 farthest from the second display area AA2 is the longest.

[0268] To compensate for the load differences caused by the varying lengths of different second transfer segments LT2a, the length of the third transfer segment LT3a closest to the second display area AA2 is set to be greater than the length of the third transfer segment LT3a farther from the second display area AA2. Consequently, for the first signal line L1 closest to the second display area AA2, the second transfer segment LT2a electrically connected thereto is the shortest, and the third transfer segment LT3a electrically connected thereto is the longest. For the first signal line L1 farthest from the second display area AA2, the second transfer segment LT2a electrically connected thereto is the longest, and the third transfer segment LT3a electrically connected thereto is the shortest. This configuration minimizes the load generated by transferring data signals to different first signal lines while balancing the load, thereby reducing the power consumption of the display panel.

[0269] According to some exemplary embodiments, referring to Figure 18, in order to achieve that the length of the third transition segment LT3a close to the second display area AA2 is greater than the length of the third transition segment LT3a away from the second display area AA2, the fourth breaks K4 are arranged in a row along the first direction X; among the two adjacent fifth breaks K5, the fifth break K5 close to the second display area is closer to the first peripheral area than the fifth break K5 away from the second display area AA2.

[0270] According to some exemplary embodiments, referring to FIG. 18 , for the third transfer trace LT3 farthest from the second display area AA2, the orthographic projection of the fourth break K4 in the third transfer trace LT3 on the substrate substrate is located within the orthographic projection of the third signal trace L3 closest to the fourth via H04 on the substrate substrate. The fourth breaks K4 in other third transfer traces LT3 closer to the second display area AA2 are arranged according to the position of the fourth break K4 farthest from the second display area AA2, such that the fourth breaks K4 are arranged in a row spaced apart along the first direction X. Furthermore, for each third transfer trace LT3, the orthographic projection of its fifth break K5 on the substrate substrate is located within the orthographic projection of the third signal trace L3 closest to the corresponding fourth via H04 on the substrate substrate.

[0271] It should be understood that the orthographic projection of the fourth break K4 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the fourth via H04 on the substrate. Here, the fourth via H04 refers to the fourth via H04 that electrically connects the third transfer trace LT3 and the first transfer trace LT1 provided with the fourth break K4. Similarly, the orthographic projection of the fifth break K5 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the fourth via H04 on the substrate. Here, the fourth via H04 refers to the fourth via H04 that electrically connects the third transfer trace LT3 and the first transfer trace LT1 provided with the fifth break K5.

[0272] FIG19 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A4 in FIG1 .

[0273] According to some exemplary embodiments, referring to FIG19 , a first insulating layer is provided between the first conductive layer and the second conductive layer. The first insulating layer has a plurality of third vias H03 and a plurality of fourth vias H04. Referring to FIG11 , the second transfer trace LT2 is electrically connected to the first transfer trace LT1 via the third vias H03, and the sub-trace group LA is electrically connected to the first transfer trace LT1 via the fourth vias H04. The connection trend lines of the third vias H03 and the fourth vias H04 intersect, that is, the connection trend lines of the third vias H03 and the fourth vias H04 are substantially V-shaped.

[0274] According to some exemplary embodiments, the first insulating layer has a plurality of fifth vias H05, and the plurality of second signal traces L2 are electrically connected to the plurality of fourth signal traces L4 through the plurality of fifth vias H05. Portions of the second signal traces L2 and the fourth signal traces L4 that do not require data signal transfer can be used to transmit constant voltage signals. These portions of the second signal traces L2 and the fourth signal traces L4 are electrically connected through the fifth vias H05 to form a grid of signal traces.

[0275] The plurality of fifth vias H05 include a plurality of fifth via groups H05A. A connecting trend line of a portion of the fifth vias H05 within the fifth via group H05A is a first connecting trend line F1, and a connecting trend line of the remaining portion of the fifth vias H05 within the fifth via group H05A is a second connecting trend line F2. The first connecting trend line F1 is substantially parallel to the connecting trend lines of each third via H03, and the second connecting trend line F2 is substantially parallel to the connecting trend lines of each fourth via H04.

[0276] It should be noted that the “substantially parallel” here should be understood as the angle between the extension directions of the two being smaller than a preset value, for example, the angle being smaller than 5 degrees or the angle being smaller than 10 degrees.

[0277] FIG20 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A4 in FIG1 .

[0278] According to some exemplary embodiments, the first insulating layer has a plurality of fifth vias H05, and the plurality of second signal traces L2 are electrically connected to the plurality of fourth signal traces L4 through the plurality of fifth vias H05. The connection trend line of a portion of the fifth vias H05 within the fifth via group H05A is a first connection trend line F1, and the connection trend line of the remaining portion of the fifth vias H05 within the fifth via group H05A is a second connection trend line F2. The first connection trend line F1 is not parallel to the connection trend lines of each third via H03, and the second connection trend line F2 is not parallel to the connection trend lines of each fourth via H04. The position distribution of the connection points between the second and fourth signal traces for transferring data signals is set to be inconsistent with the position distribution of the connection points between the second and fourth signal traces for transmitting constant voltage signals, thereby breaking the periodicity of the connection point position distributions and reducing visual mura.

[0279] It should be noted that “non-parallel” here should be understood as the angle between the extension directions of the two being greater than a preset value, for example, the angle being greater than 5 degrees or the angle being greater than 10 degrees.

[0280] FIG21 schematically shows a plan view of a first conductive layer and a second conductive layer in some display panels according to an embodiment of the present disclosure, in which the first conductive layer and the second conductive layer are located in area A4 in FIG1 .

[0281] According to some exemplary embodiments, the connection trend lines of each fifth via in the fifth via group are X-shaped, W-shaped, or M-shaped, thereby differing from the V-shaped trend lines formed by the third and fourth vias. This allows for a difference in the distribution of connection points between the second and fourth signal traces for transferring data signals and the distribution of connection points between the second and fourth signal traces for transmitting constant voltage signals. For example, referring to FIG. 21 , the connection trend lines of each fifth via H05 in the fifth via group H05A are X-shaped.

[0282] Figure 22 schematically illustrates a plan view of the first conductive layer, the second conductive layer, and the first electrode layer in some display panels according to embodiments of the present disclosure, located in area A3 of Figure 1. Figure 23 schematically illustrates a plan view of the first conductive layer and the second conductive layer in some display panels according to embodiments of the present disclosure, located in area A3 of Figure 1.

[0283] According to some exemplary embodiments, referring to FIG. 6 , FIG. 22 , and FIG. 23 , the fourth signal trace L4 includes a plurality of third connection blocks L41 , and the plurality of third connection blocks L41 include a plurality of first connection sub-blocks L411 and a plurality of second connection sub-blocks L412 .

[0284] A first insulating layer is disposed between the first conductive layer and the second conductive layer. The first insulating layer has multiple vias H. The orthographic projections of the vias H on the substrate are located within the orthographic projections of the first connector blocks L411 on the substrate. Specifically, the first insulating layer has vias H in the region of the first connector block L411, but no vias in the region of the second connector block L412. The first connector block L411 is electrically connected to the second signal trace L2 via the vias, while the second connector block L412 is separated from the second signal trace L2 by the first insulating layer.

[0285] For example, the plurality of vias H include a plurality of third vias H03, a plurality of fourth vias H04, and a plurality of fifth vias H05. The third vias H03 are vias electrically connecting the first transfer trace LT1 and the second transfer trace LT2, and the fourth vias H04 are vias electrically connecting the first transfer trace LT1 and the third transfer trace LT3. Excluding the third and fourth vias H03 and H04, the remaining vias are defined as fifth vias H05.

[0286] The display substrate further includes a first electrode layer 300 located on a side of the first conductive layer away from the base substrate. At least a portion of the orthographic projection of the second connection sub-block LT2 on the base substrate is located within the orthographic projection of the first electrode layer 300 on the base substrate. The first electrode shields areas where vias H are not provided, thereby eliminating display mura caused by the non-periodic distribution of vias H.

[0287] For example, the orthographic projection of the second connection sub-block LT2 on the base substrate is located within the orthographic projection of the first electrode layer 300 on the base substrate.

[0288] According to some exemplary embodiments, the first electrode layer 300 includes a plurality of first electrodes 310 arranged in an array. The display substrate further includes a pixel defining layer located on a side of the first electrode layer away from the base substrate. The pixel defining layer includes a plurality of pixel openings 400, with each pixel opening 400 exposing one first electrode 310. The orthographic projection of the pixel opening 400 on the base substrate is spaced apart from the orthographic projection of the via H on the base substrate.

[0289] 22 , the pixel opening 400 is in the shape of a rounded rectangle. Alternatively, the pixel opening 400 is in the shape of a circle, an ellipse, a diamond, or the like.

[0290] According to some exemplary embodiments, the multiple first electrodes 310 include multiple first sub-electrodes 311, multiple second sub-electrodes 312 and multiple third sub-electrodes 313, the display substrate includes multiple first light-emitting devices, multiple second light-emitting devices and multiple third devices, the first sub-electrode 311 serves as the anode of the first light-emitting device, the second sub-electrode 312 serves as the anode of the second light-emitting device, and the third sub-electrode 313 serves as the anode of the third light-emitting device.

[0291] For example, the first light emitting device emits red light, the second light emitting device emits green light, and the third light emitting device emits blue light.

[0292] According to some exemplary embodiments, referring to Figure 23, the first transfer trace LT1 has a first break K1 and a second break K2, the first break K1 is located on the side of the third via H03 away from the fourth via H04, and the second break K2 is located on the side of the fourth via H04 away from the third via H03, and the first breaks K1 are arranged in a row along the second direction Y, and the second breaks K2 are arranged in a row along the second direction Y.

[0293] For example, for the first transfer trace LT1 farthest from the first peripheral region (i.e., the first transfer trace LT1 located at the top as shown in the figure), the orthographic projection of the first break K1 in this first transfer trace LT1 on the substrate is located within the orthographic projection of the first power signal line closest to the third via H03 on the substrate. The first breaks K1 in other first transfer traces LT1 closer to the first peripheral region are arranged according to the position of the first break K1 farthest from the first peripheral region, so that the first breaks K1 are arranged in a row along the second direction Y at intervals.

[0294] For example, for the first transfer trace LT1 farthest from the first peripheral region (i.e., the topmost first transfer trace LT1 shown in the figure), the orthographic projection of the second break K2 in this first transfer trace LT1 on the substrate is located within the orthographic projection of the first power signal line closest to the fourth via H04 on the substrate. The second breaks K2 in other first transfer traces LT1 closer to the first peripheral region are positioned according to the position of the second break K2 farthest from the first peripheral region, such that the second breaks K2 are arranged in a row along the second direction Y at intervals.

[0295] The first transfer trace LT1 has a first transfer segment LT1a interrupted between the first break K1 and the second break K2. In the remaining plurality of first transfer segments LT1a except the first transfer segment LT1a farthest from the first peripheral area, the first transfer segment LT1a further has at least one sixth break K6.

[0296] In the first transfer section LT1a, the orthographic projection of the sixth break K6 closest to the first display area AA1 on the substrate is located within the orthographic projection of the first power signal line VDD closest to the third via H03 on the substrate (refer to Figure 11), and the first power signal line VDD is located on the side of the third via H03 away from the first display area AA1, and the orthographic projections of the two adjacent sixth breaks K6 on the substrate are respectively located within the orthographic projections of the two adjacent first power signal lines VDD on the substrate, and the orthographic projections of the first break K1 and the adjacent sixth break K6 on the substrate are respectively located within the orthographic projections of the two adjacent first power signal lines VDD on the substrate.

[0297] The second signal line electrically connected to the first transfer line LT1 through the fourth via H04 is the third transfer line LT3. The third transfer line LT3 has a fourth break K4 and a fifth break K5. The fourth break K4 is located on the side of the fourth via H04 away from the first peripheral area, and the fifth break K5 is located on the side of the fourth via H04 close to the first peripheral area. The fourth breaks K4 are arranged in a row along the first direction X, and the fifth breaks K5 are arranged in a row along the first direction X.

[0298] For example, for the third transfer trace LT3 farthest from the second display area AA2, the orthographic projection of the fourth break K4 in the third transfer trace LT3 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the fourth via H04 on the substrate. The fourth breaks K4 in other third transfer traces LT3 closer to the second display area AA2 are positioned according to the position of the fourth break K4 farthest from the second display area AA2, such that the fourth breaks K4 are arranged in a row along the first direction X at intervals.

[0299] For example, for the third transfer trace LT3 closest to the second display area AA2, the orthographic projection of the fifth break K5 in the third transfer trace LT3 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the fourth via H04 on the substrate. The fifth breaks K5 in other third transfer traces LT3 further away from the second display area AA2 are positioned according to the position of the fifth break K5 closest to the second display area AA2, such that the fifth breaks K5 are arranged in a row along the first direction X at intervals.

[0300] The third transfer trace LT3 has a third transfer section LT3a interrupted between the fourth break K4 and the fifth break K5. A seventh break K7 is provided between any two adjacent second connection blocks L21 in the third transfer section LT3a.

[0301] The second transfer trace LT2 has a third break K3, which is located on a side of the third via H03 away from the first peripheral area. The orthographic projection of the third break K3 on the substrate is located within the orthographic projection of the third signal trace L3 closest to the third via H03 on the substrate.

[0302] In the remaining second transfer traces LT2, excluding the second transfer trace LT2 farthest from the first display area AA1, the second transfer trace LT2 further has at least one eighth break K8. The eighth break K8 farthest from the first peripheral area is aligned with each of the fourth breaks K4 along the first direction X. Furthermore, in the portion of the second transfer trace LT2 cut between the third break K3 and the eighth break K8 farthest from the first peripheral area, an eighth break K8 is provided between any two adjacent second connection blocks L21.

[0303] Among them, in the part where the first transfer segment LT1a is located in the third via hole H03 away from the first display area AA1, one of the two adjacent third connection blocks L41 is the first connection sub-block L411, and the other is the second connection sub-block L412, and the third connection block L41 adjacent to the third via hole H03 is the second connection sub-block L412.

[0304] In addition, in each fourth signal line L4, each third connection block in the portion other than the first transfer section LT1a is a first connection sub-block L411, and each first connection sub-block L411 in this portion is electrically connected to the second signal line L2 through the fifth via H05.

[0305] According to some exemplary embodiments, the display substrate includes a first source-drain metal layer located on a side of the drive circuit layer away from the base substrate, a second source-drain metal layer located on a side of the first source-drain metal layer away from the base substrate, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the base substrate. That is, the display substrate has three source-drain metal layers, wherein the first conductive layer is the third source-drain metal layer, and the second conductive layer is the second source-drain metal layer.

[0306] According to some exemplary embodiments, referring to FIG6 , the third signal trace L3 includes a plurality of first signal segments L31 and a plurality of second signal segments L32 alternately arranged along a first direction X, with adjacent first signal segments L31 and second signal segments L32 directly connected. Referring to FIG8 , the orthographic projection of the first signal segment L31 on the substrate partially overlaps with the orthographic projection of the first signal trace L1 on the substrate, and the orthographic projection of the second signal segment L32 on the substrate is spaced apart from the orthographic projection of the first signal trace L1 on the substrate. The dimension of the first signal segment L31 along the second direction Y is greater than the dimension of the fourth signal trace L4 along the second direction Y, and the orthographic projection of the second signal segment L32 on the substrate partially overlaps with the orthographic projection of the signal block V1 on the substrate.

[0307] According to some exemplary embodiments, the display substrate includes a first source-drain metal layer located on a side of the driving circuit layer away from the base substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the base substrate; that is, the display substrate has two layers of source-drain metal layers, wherein the first conductive layer is the second source-drain metal layer, and the second conductive layer is the first source-drain metal layer.

[0308] Compared to a display substrate with two source / drain metal layers, a display substrate with three source / drain metal layers has the same film layers except for the source / drain metal layers. The second source / drain metal layer in the display substrate with two source / drain metal layers and the third source / drain metal layer in the display substrate with three source / drain metal layers also have the same structure. The second source / drain metal layer in the display substrate with two source / drain metal layers can be considered to be a combination of the first and second source / drain metal layers in the display substrate with three source / drain metal layers.

[0309] FIG24 schematically shows a plan view of a second conductive layer in a display region of a display substrate according to some embodiments of the present disclosure.

[0310] 24 , the second conductive layer, or the first source / drain metal layer, may include a first connection structure 51, a second connection structure 52, a third connection structure 53, a fourth connection structure 54, a fifth connection structure 55, and a second initialization signal line Vinit2. The first connection structure 51, the second connection structure 52, the third connection structure 53, the fourth connection structure 54, and the fifth connection structure 55 are similar in configuration and function to the connection structures in the first source / drain metal layer of the display substrate having three source / drain metal layers in the aforementioned embodiment, and are not further described here.

[0311] Furthermore, the first source / drain metal layer also includes a third signal trace L3 and a fourth signal trace L4. This integrates the signal traces originally located in the second source / drain metal layer of a display substrate having three source / drain metal layers into the first source / drain metal layer. Specifically, the third signal trace L3 is interposed between the third connection structure 53, the fourth connection structure 54, the second initialization signal trace Vinit2, and the first connection structure 51. The fourth signal trace L4 is interposed between the second initialization signal trace Vinit2 and the second connection structure 52.

[0312] According to some exemplary embodiments, referring to FIG. 24 , the third signal trace L3 includes a plurality of first signal segments L31 and a plurality of second signal segments L32 alternately arranged along the first direction X, and adjacent first signal segments L31 and second signal segments L32 are directly connected.

[0313] FIG25 schematically shows a plan view of a combination of a first conductive layer and a second conductive layer in a display area of ​​a display panel according to an embodiment of the present disclosure.

[0314] Referring to Figure 25 , the orthographic projection of the first signal segment L31 on the substrate partially overlaps with the orthographic projection of the first signal trace L1 on the substrate, while the orthographic projection of the second signal segment L32 on the substrate is spaced apart from the orthographic projection of the first signal trace L1 on the substrate. The dimension of the first signal segment L31 along the second direction Y is larger than the dimension of the fourth signal trace L4 along the second direction Y, and the orthographic projection of the second signal segment L32 on the substrate is spaced apart from the orthographic projection of the signal block V1 on the substrate. This means that the first signal segment L31 retains a relatively wide width, while the width of the second signal segment L32 is somewhat narrowed due to wiring space limitations.

[0315] In another aspect, a display device is provided, comprising the display substrate described above. The display device may be a display device such as a liquid crystal display, electronic paper, or an OLED (Organic Light-Emitting Diode) display, as well as any product or component with touch and display functions, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigation system, that includes such a display device.

[0316] It should be understood that the display devices according to some exemplary embodiments of the present disclosure have all the features and advantages of the above-mentioned display substrate. These features and advantages can be referred to in the above description of the display substrate and will not be repeated here.

[0317] As used herein, the terms "substantially," "about," "approximately," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately," as used herein, are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0318] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate includes a display area and a peripheral area located around the display area, and the display substrate includes: substrate; a driving circuit layer located on the base substrate, the driving circuit layer comprising a plurality of pixel driving circuit groups arranged along a first direction, the pixel driving circuit groups comprising a plurality of pixel driving circuit units arranged along a second direction, the first direction intersecting the second direction, the display area comprising a first display area and a second display area arranged along the first direction, the first display area being located on a side of the second display area close to the peripheral area, the plurality of pixel driving circuit groups comprising a plurality of first pixel driving circuit groups located in the first display area and a plurality of second pixel driving circuit groups located in the second display area; a first conductive layer, located on a side of the driving circuit layer away from the base substrate, the first conductive layer comprising a plurality of first routing groups arranged along a first direction, the first routing group comprising a first power signal line and two sub-routing groups respectively located on either side of the first power signal line along the first direction, the sub-routing groups comprising a first signal routing line and a second signal routing line arranged along the first direction, the first power signal line, the first signal routing line, and the second signal routing line all extending along the second direction, and one sub-routing group being electrically connected to each of the pixel driving circuit units in one pixel driving circuit group; a second conductive layer located between the driving circuit layer and the first conductive layer, the second conductive layer comprising a plurality of third signal lines and a plurality of fourth signal lines, the plurality of third signal lines and the plurality of fourth signal lines being alternately arranged along the second direction, and the third signal lines and the fourth signal lines extending along the first direction; and a plurality of binding pads located on the base substrate, the peripheral area comprising a first peripheral area located on one side of the display area along the second direction, and the plurality of binding pads located in the first peripheral area; Wherein, the first power signal line is electrically connected to the pixel driving circuit unit through the third signal line; and The plurality of fourth signal lines include a plurality of first transfer lines, and the plurality of second signal lines include a plurality of second transfer lines located in the second display area, and the second transfer lines are used to receive the data signal provided by the binding pad and connect the data signal to the first pixel driving circuit group through the first transfer line and the sub-line group.

2. The display substrate according to claim 1, wherein The first power signal line includes a plurality of signal blocks spaced apart along the second direction, adjacent signal blocks are electrically connected via a signal connection segment, and the signal connection segment is directly connected to the third signal line.

3. The display substrate according to claim 2, wherein: The signal block includes a first part and a second part arranged along a first direction, the first part is directly connected to the second part, and the signal connection section is directly connected to both the first part and the second part.

4. The display substrate according to claim 3, wherein: The signal block includes a first sub-block, a second sub-block, and a third sub-block arranged along the second direction, the first sub-block is directly connected to the second sub-block, and a size of the first sub-block along the first direction is smaller than a size of the second sub-block along the first direction, the second sub-block is directly connected to the third sub-block, and a size of the second sub-block along the first direction is smaller than a size of the third sub-block along the first direction; The first signal line includes a plurality of first connection blocks, which are located on a side of the adjacent second signal line away from the second sub-block. The second signal line includes a plurality of second connection blocks, which are adjacent to the first sub-block.

5. The display substrate according to claim 4, wherein: The second signal trace includes a second signal segment connected between two adjacent second connection blocks, the second signal segment includes a first sub-segment, a second sub-segment, and a third sub-segment arranged along a second direction, a portion of the first sub-segment is adjacent to the second sub-block, a portion of the second sub-segment is adjacent to the third sub-block, and the third sub-segment is connected and arranged between the first sub-segment and the second sub-segment; The first subsegment and the second subsegment extend along the second direction, the second subsegment is closer to the adjacent first signal trace than the first subsegment, one end of the third subsegment is connected to the first subsegment and extends along a third direction until the other end is connected to the second subsegment, and the third direction intersects with the second direction.

6. The display substrate according to any one of claims 2 to 5, wherein: The first conductive layer further includes a plurality of anode connecting portions, and one anode connecting portion is respectively provided on both sides of the signal connection section along the first direction.

7. The display substrate according to claim 6, wherein: A first insulating layer is provided between the first conductive layer and the second conductive layer, the first insulating layer has a plurality of first via holes, and the signal connection segment is electrically connected to the third signal trace through the first via holes; and The display substrate further includes a second insulating layer located on a side of the first conductive layer away from the base substrate, and a first electrode layer located on a side of the second insulating layer away from the base substrate, the second insulating layer having a plurality of second via holes, and the first electrode layer is electrically connected to the anode connecting portion through the second via holes; The orthographic projection of the first via hole on the base substrate is located between the orthographic projections of two adjacent second via holes on the base substrate.

8. The display substrate according to any one of claims 4 to 7, wherein: a first pixel driving circuit groups are located in the first display area, the 1st pixel driving circuit group is closest to the second display area, and the ath first pixel driving circuit group is farthest from the second display area; and The first sub-routing group electrically connected to the first first pixel driving circuit group is electrically connected to the binding pad via the first first transfer routing line and the first second transfer routing line, and the d-th sub-routing group electrically connected to the d-th first pixel driving circuit group is electrically connected to the binding pad via the d-th first transfer routing line and the d-th second transfer routing line, where 2≤d≤a, and a and d are integers; The first first transfer line is closer to the first peripheral area than the dth first transfer line, and the first second transfer line is closer to the first display area than the dth second transfer line.

9. The display substrate according to claim 8, wherein: There is a first insulating layer between the first conductive layer and the second conductive layer, the first insulating layer has multiple third vias and multiple fourth vias, the second transfer trace is electrically connected to the binding pad, the second transfer trace is electrically connected to the first transfer trace through the third via, and the sub-trace group is electrically connected to the first transfer trace through the fourth via.

10. The display substrate according to claim 9, wherein: The second signal routing line in the sub-routing group is electrically connected to the first transfer routing line through the fourth via hole, and the second signal routing line is electrically connected to the first pixel driving circuit group.

11. The display substrate according to claim 9, wherein: The second signal routing in the sub-routing group is electrically connected to the first transfer routing through the fourth via, the second signal routing is electrically connected to the adjacent first signal routing through at least one bridge bar, and the first signal routing is electrically connected to the first pixel driving circuit group.

12. The display substrate according to claim 11, wherein: The bridge bar is located on the first conductive layer, and an orthographic projection of the bridge bar on the base substrate is located within an orthographic projection of the second conductive layer on the base substrate.

13. The display substrate according to claim 12, wherein: The orthographic projection of the bridge bar on the substrate is located within the orthographic projection of the third signal trace on the substrate; and / or The orthographic projection of the bridge bar on the base substrate is located within the orthographic projection of the fourth signal trace on the base substrate.

14. The display substrate according to any one of claims 9 to 13, wherein: The first transfer trace has a first break and a second break. The first break is located on a side of the third via hole away from the fourth via hole, and the second break is located on a side of the fourth via hole away from the third via hole.

15. The display substrate according to any one of claims 14, wherein: The orthographic projections of the first fracture and the second fracture on the base substrate are located within the orthographic projection of the first conductive layer on the base substrate.

16. The display substrate according to claim 14 or 15, wherein: The first fractures are arranged in a row at intervals along the second direction; and / or The second fractures are arranged in a row at intervals along the second direction.

17. The display substrate according to any one of claims 9 to 16, wherein: The second transfer trace has a third break, and the third break is located on a side of the third via hole away from the first peripheral area.

18. The display substrate according to claim 17, wherein: The orthographic projection of the third fracture on the base substrate is located within the orthographic projection of the second conductive layer on the base substrate.

19. The display substrate according to claim 18, wherein: The orthographic projection of the third fracture on the base substrate is located within the orthographic projection of the third signal trace on the base substrate.

20. The display substrate according to claim 19, wherein The orthographic projection of the third fracture on the substrate is located within the orthographic projection of the third signal trace closest to the third via on the substrate.

21. The display substrate according to any one of claims 17 to 19, wherein: The third fractures are arranged in a row at intervals along the first direction.

22. The display substrate according to claim 20, wherein: The second signal trace electrically connected to the first transfer trace is a third transfer trace, the third transfer trace having a fourth break and a fifth break, the fourth break being located on a side of the fourth via away from the first peripheral area, and the fifth break being located on a side of the fourth via close to the first peripheral area; as well as The third transfer trace includes a third transfer section cut between the fourth break and the fifth break, and the third transfer section is electrically connected to the adjacent first signal trace through at least one of the bridge bars; Among the two adjacent third transition segments, the length of the third transition segment close to the second display area is greater than the length of the third transition segment far from the second display area.

23. The display substrate according to claim 22, wherein: The fourth fractures are arranged in a row along the first direction at intervals; and Of the two adjacent fifth fractures, the fifth fracture close to the second display area is closer to the first peripheral area than the fifth fracture far from the second display area.

24. The display substrate according to any one of claims 9 to 21, wherein: The second signal routing electrically connected to the first transfer routing is a third transfer routing, the third transfer routing is electrically connected to the adjacent first signal routing through at least one bridge bar, and the third transfer routing extends continuously from one end of the display area close to the first peripheral area to the end of the display area away from the first peripheral area.

25. The display substrate according to any one of claims 9 to 24, wherein: The connection trend line of each of the third via holes intersects with the connection trend line of each of the fourth via holes.

26. The display substrate according to claim 25, wherein: The first insulating layer has a plurality of fifth vias, the second signal trace is electrically connected to the fourth signal trace through the fifth vias, the plurality of fifth vias include a plurality of fifth via groups, a connection trend line of a portion of the fifth vias in the fifth via group is a first connection trend line, and a connection trend line of a remaining portion of the fifth vias in the fifth via group is a second connection trend line; The first connection trend line is substantially parallel to the connection trend lines of each third via hole, and the second connection trend line is substantially parallel to the connection trend lines of each fourth via hole.

27. The display substrate according to claim 25, wherein: The first insulating layer has a plurality of fifth vias, the second signal trace is electrically connected to the fourth signal trace through the fifth vias, the plurality of fifth vias include a plurality of fifth via groups, a connection trend line of a portion of the fifth vias in the fifth via group is a first connection trend line, and a connection trend line of a remaining portion of the fifth vias in the fifth via group is a second connection trend line; The first connection trend line is not parallel to the connection trend lines of the third via holes, and the second connection trend line is not parallel to the connection trend lines of the fourth via holes.

28. The display substrate according to claim 25, wherein The first insulating layer has a plurality of fifth vias, and the second signal line is electrically connected to the fourth signal line through the fifth vias. The plurality of fifth vias include a plurality of fifth via groups, and the connection trend lines of each of the fifth vias in the fifth via group are X-shaped, W-shaped or M-shaped.

29. The display substrate according to any one of claims 10 to 13, wherein: The fourth signal routing includes a plurality of third connection blocks, and the plurality of third connection blocks include a plurality of first connection sub-blocks and a plurality of second connection sub-blocks; A first insulating layer is provided between the first conductive layer and the second conductive layer, the first insulating layer having a plurality of vias, the orthographic projections of the plurality of vias on the base substrate being located within the orthographic projections of the plurality of first connecting sub-blocks on the base substrate, the first connecting sub-blocks being electrically connected to the second signal traces through the vias, and the second connecting sub-blocks being separated from the second signal traces by the first insulating layer; and The display substrate further includes a first electrode layer located on a side of the first conductive layer away from the base substrate, and at least a portion of an orthographic projection of the second connecting sub-block on the base substrate is located within the orthographic projection of the first electrode layer on the base substrate.

30. The display substrate according to claim 29, wherein The first transfer trace has a first break and a second break, the first break is located on a side of the third via away from the fourth via, the second break is located on a side of the fourth via away from the third via, the first breaks are arranged in a row along the second direction, and the second breaks are arranged in a row along the second direction. The first transfer trace has a first transfer segment cut between the first break and the second break, and in the remaining plurality of first transfer segments except the first transfer segment farthest from the first peripheral area, the first transfer segment further has at least one sixth break; In the first transition section, an orthographic projection of the sixth break closest to the first display area on the substrate is located within an orthographic projection of the first power signal line closest to the third via on the substrate, and the first power signal line is located on a side of the third via away from the first display area; the orthographic projections of two adjacent sixth breaks on the substrate are respectively located within the orthographic projections of two adjacent first power signal lines on the substrate; and the orthographic projections of the first break and the adjacent sixth break on the substrate are respectively located within the orthographic projections of two adjacent first power signal lines on the substrate; as well as The second signal trace electrically connected to the first transfer trace through the fourth via is a third transfer trace, the third transfer trace having a fourth break and a fifth break, the fourth break being located on a side of the fourth via away from the first peripheral area, the fifth break being located on a side of the fourth via close to the first peripheral area, the fourth breaks being arranged in a row at intervals along the first direction, and the fifth breaks being arranged in a row at intervals along the first direction; The third transfer line has a third transfer section cut between the fourth break and the fifth break, and a seventh break is provided between any two adjacent second connection blocks in the third transfer section; as well as The second transfer trace has a third break, the third break is located on a side of the third via away from the first peripheral area, and an orthographic projection of the third break on the substrate is located within an orthographic projection of the third signal trace closest to the third via on the substrate; Among the remaining second transfer lines except the second transfer line farthest from the first display area, the second transfer lines further have at least one eighth break, and the eighth break farthest from the first peripheral area is aligned with the fourth breaks along the first direction; In the portion where the second transfer line is cut off between the third break and the eighth break farthest from the first peripheral area, the eighth break is provided between any two adjacent second connection blocks; Wherein, in a portion of the first transfer section located at a portion of the third via hole away from the first display area, one of two adjacent third connection blocks is the first connection sub-block, the other is the second connection sub-block, and the third connection block adjacent to the third via hole is the second connection sub-block; and Each of the third connection blocks in a portion of the fourth signal trace other than the first transfer section is the first connection sub-block.

31. The display substrate according to claim 2-30, wherein: The display substrate comprises a first source-drain metal layer located on a side of the driving circuit layer away from the base substrate, a second source-drain metal layer located on a side of the first source-drain metal layer away from the base substrate, and a third source-drain metal layer located on a side of the second source-drain metal layer away from the base substrate; Wherein, the first conductive layer is the third source-drain metal layer, and the second conductive layer is the second source-drain metal layer.

32. The display substrate according to claim 31, wherein The third signal routing includes a plurality of first signal segments and a plurality of second signal segments alternately arranged along a first direction, and adjacent first signal segments are directly connected to adjacent second signal segments; as well as The orthographic projection of the first signal segment on the substrate partially overlaps with the orthographic projection of the first signal trace on the substrate, and the orthographic projection of the second signal segment on the substrate is spaced apart from the orthographic projection of the first signal trace on the substrate; The size of the first signal segment along the second direction is greater than the size of the fourth signal trace along the second direction, and the orthographic projection of the second signal segment on the substrate partially overlaps with the orthographic projection of the signal block on the substrate.

33. The display substrate according to any one of claims 2 to 30, wherein: The display substrate comprises a first source-drain metal layer located on a side of the driving circuit layer away from the base substrate, and a second source-drain metal layer located on a side of the first source-drain metal layer away from the base substrate; The first conductive layer is the second source-drain metal layer, and the second conductive layer is the first source-drain metal layer.

34. The display substrate according to claim 33, wherein: The third signal routing includes a plurality of first signal segments and a plurality of second signal segments alternately arranged along a first direction, and adjacent first signal segments are directly connected to adjacent second signal segments; as well as The orthographic projection of the first signal segment on the substrate partially overlaps with the orthographic projection of the first signal trace on the substrate, and the orthographic projection of the second signal segment on the substrate is spaced apart from the orthographic projection of the first signal trace on the substrate; The size of the first signal segment along the second direction is greater than the size of the fourth signal trace along the second direction, and the orthographic projection of the second signal segment on the substrate is spaced apart from the orthographic projection of the signal block on the substrate.

35. A display device, wherein: The display device comprises a display panel according to any one of claims 1-34.

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