Gate drive circuit and display panel

Abstract

A gate drive circuit and a display panel. When a pull-up control module (30) controls a first voltage end (VGL) to be electrically connected to a second node (N2), an inverter module (10) disables an electrical connection between a low-frequency clock signal end (LC) and a third node (N3) on the basis of the potential of the second node (N2), and the inverter module (10) controls, on the basis of the potential of a first node (N1), the first voltage end (VGL) to be electrically connected to the third node (N3); and a pull-down holding module (20) disables an electrical connection between the first voltage end (VGL) and the first node (N1) on the basis of the potential of the third node (N3).

Description

Gate drive circuit and display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] In a gate drive circuit, two transistors are often provided to respectively raise and lower the potential of a first node in order for the gate drive circuit to output the required gate control signal, thereby causing the output transistor to be in an on or off state depending on the potential of the first node. However, during the process of the output transistor transitioning from an off state to an on state in response to the potential of the first node, the transistor that pulls down the potential of the first node also transitions from an on state to an off state. Consequently, while the potential of the first node is raised by the transistor that raises the potential of the first node, the transistor that pulls down the potential of the first node will remain in an on state for a certain period of time, affecting the effect of raising the potential of the first node and resulting in temperature rise and reduced reliability in the gate drive circuit. SUMMARY OF THE INVENTION

[0003] Embodiments of the present application provide a gate driving circuit and a display panel, which can improve the problems of temperature rise and reduced reliability of the gate driving circuit.

[0004] An embodiment of the present application provides a gate drive circuit, comprising an inverting module, a pull-down maintaining module, and a pull-up control module. The inverting module is electrically connected to a first voltage terminal, a first node, a second node, and a third node. The inverting module is configured to control signal transmission between the first voltage terminal and the third node based on the potential of the first node, and to control signal transmission between a low-frequency clock signal terminal and the third node based on the potential of the second node. The pull-down maintaining module is electrically connected to the first voltage terminal, the first node, and the third node. The pull-down maintaining module is configured to control signal transmission between the first voltage terminal and the first node based on the potential of the third node. The pull-up control module is electrically connected to the first voltage terminal, the first node, and the second node. The pull-up control module is configured to pull up the potential of the first node based on a pull-up control signal, and to control signal transmission between the first voltage terminal and the second node based on the pull-up control signal. Among them, when the pull-up control module is configured to electrically connect the first voltage end and the second node according to the pull-up control signal, the inverting module is configured to disconnect the electrical connection between the low-frequency clock signal end and the third node according to the potential of the second node, and control the electrical connection between the first voltage end and the third node according to the potential of the first node, and the pull-down maintenance module is configured to disconnect the electrical connection between the first voltage end and the first node according to the potential of the third node.

[0005] The present application also provides a display panel, comprising a gate drive unit, the gate drive unit comprising a plurality of any of the above-mentioned gate drive circuits, the plurality of gate drive circuits being cascaded, wherein the n-4th-level gate control signal output by the n-4th-level gate drive circuit serves as the pull-up control signal received by the pull-up control module of the nth-level gate drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] FIG1 is a block diagram of a gate drive circuit according to an embodiment of the present invention;

[0007] FIG2 is a schematic structural diagram of a gate drive circuit provided in an embodiment of the present application;

[0008] FIG3 is a schematic structural diagram of another gate drive circuit provided in an embodiment of the present application;

[0009] FIG4 is a timing diagram of a corresponding gate drive circuit provided in an embodiment of the present application;

[0010] FIG5 is a simulation timing diagram of a gate drive circuit before improvement according to an embodiment of the present application;

[0011] FIG6 is a simulation timing diagram of an improved gate drive circuit according to an embodiment of the present application;

[0012] FIG7 is a schematic structural diagram of a display panel provided in an embodiment of the present application;

[0013] FIG8 is a cascade relationship diagram of multiple gate drive circuits provided in an embodiment of the present application;

[0014] FIG9 is a schematic diagram showing the corresponding relationship between the gate drive circuit and the high-frequency clock signal provided in an embodiment of the present application;

[0015] FIG10 is a driving timing diagram of the display panel provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0016] To make the purpose, technical solutions and effects of this application clearer and more specific, the following further describes this application in detail with reference to the accompanying drawings and examples. It should be understood that the specific examples described herein are only used to explain this application and are not intended to limit this application.

[0017] Optionally, in some embodiments, the pull-up control module includes a first control unit and a second control unit. The first control unit includes a first transistor, wherein the control terminal of the first transistor is configured to receive the pull-up control signal, the input terminal of the first transistor is electrically connected to the control terminal of the first transistor, and the output terminal of the first transistor is electrically connected to the first node. The second control unit includes a second transistor, wherein the control terminal of the second transistor is configured to receive the pull-up control signal, the input terminal of the second transistor is electrically connected to the first voltage terminal, and the output terminal of the second transistor is electrically connected to the second node.

[0018] Optionally, in some embodiments, the inverting module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, the input terminal of the third transistor is electrically connected to the control terminal of the third transistor, and the output terminal of the third transistor is electrically connected to the second node. The control terminal of the fourth transistor is electrically connected to the second node, the input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and the output terminal of the fourth transistor is electrically connected to the third node. The control terminal of the fifth transistor is electrically connected to the first node, the input terminal of the fifth transistor is electrically connected to the first voltage terminal, and the output terminal of the fifth transistor is electrically connected to the second node. The control terminal of the sixth transistor is electrically connected to the first node, the input terminal of the sixth transistor is electrically connected to the first voltage terminal, and the output terminal of the sixth transistor is electrically connected to the third node.

[0019] Optionally, in some embodiments, the pull-down maintenance module includes a seventh transistor, the control end of the seventh transistor is electrically connected to the third node, the input end of the seventh transistor is electrically connected to the first voltage end, and the output end of the seventh transistor is electrically connected to the first node.

[0020] Optionally, in some embodiments, the pull-up control module further includes a third control unit, the third control unit includes an eighth transistor, the control end of the eighth transistor is configured to receive the pull-up control signal, the input end of the eighth transistor is electrically connected to the first voltage end, and the output end of the eighth transistor is electrically connected to the third node.

[0021] Optionally, in some embodiments, the second node includes a first sub-node and a second sub-node, the third node includes a third sub-node and a fourth sub-node, and the low-frequency clock signal terminal includes a first low-frequency clock signal terminal and a second low-frequency clock signal terminal.

[0022] The inverting module includes a first inverting unit and a second inverting unit, wherein the output end of the third transistor, the control end of the fourth transistor, and the output end of the fifth transistor of the first inverting unit are electrically connected to the first sub-node, the output end of the fourth transistor and the output end of the sixth transistor of the first inverting unit are electrically connected to the third sub-node, and the control end of the third transistor and the input end of the fourth transistor of the first inverting unit are electrically connected to the first low-frequency clock signal end; the output end of the third transistor, the control end of the fourth transistor, and the output end of the fifth transistor of the second inverting unit are electrically connected to the second sub-node, the output end of the fourth transistor and the output end of the sixth transistor of the second inverting unit are electrically connected to the fourth sub-node, and the control end of the third transistor and the input end of the fourth transistor of the second inverting unit are electrically connected to the second low-frequency clock signal end.

[0023] The pull-down maintaining module includes a first pull-down maintaining unit and a second pull-down maintaining unit, wherein the control end of the seventh transistor of the first pull-down maintaining unit is electrically connected to the third sub-node, and the control end of the seventh transistor of the second pull-down maintaining unit is electrically connected to the fourth sub-node.

[0024] The second control unit of the pull-up control module includes a first sub-control unit and a second sub-control unit, the output end of the second transistor of the first sub-control unit is electrically connected to the first sub-node, and the output end of the second transistor of the second sub-control unit is electrically connected to the second sub-node.

[0025] The third control unit of the pull-up control module includes a third sub-control unit and a fourth sub-control unit, the output end of the eighth transistor of the third sub-control unit is electrically connected to the third sub-node, and the output end of the eighth transistor of the fourth sub-control unit is electrically connected to the fourth sub-node.

[0026] Optionally, in some embodiments, the pull-down maintenance module includes a ninth transistor, the control end of the ninth transistor is electrically connected to the third node, the input end of the ninth transistor is electrically connected to the first voltage end, and the output end of the ninth transistor is electrically connected to the signal output end of the gate drive circuit.

[0027] Optionally, in some embodiments, the gate drive circuit further comprises an output module, a pull-down control module, and a reset module. The output module comprises an output transistor and a first capacitor, wherein the control terminal of the output transistor is electrically connected to the first node, the input terminal of the output transistor is electrically connected to the high-frequency clock signal terminal, and the output terminal of the output transistor is electrically connected to the signal output terminal of the gate drive circuit. The first capacitor is connected in series between the first node and the signal output terminal. The pull-down control module comprises a first pull-down transistor, wherein the control terminal of the first pull-down transistor is configured to receive a pull-down control signal, the input terminal of the first pull-down transistor is electrically connected to the first voltage terminal, and the output terminal of the first pull-down transistor is electrically connected to the first node. The reset module comprises a first reset transistor and a second reset transistor, wherein the control terminal of the first reset transistor and the control terminal of the second reset transistor are configured to receive a reset control signal, the input terminal of the first reset transistor and the input terminal of the second reset transistor are electrically connected to the first voltage terminal, the output terminal of the first reset transistor is electrically connected to the first node, and the output terminal of the second reset transistor is electrically connected to the signal output terminal of the gate drive circuit.

[0028] Optionally, in some embodiments, the voltage of the low-frequency clock signal transmitted by the low-frequency clock signal terminal during the sensing phase of the display panel is lower than the voltage of the low-frequency clock signal during the display phase of the display panel.

[0029] The present application provides a gate drive circuit and a display panel. A pull-up control module is electrically connected to a first voltage terminal, a first node, and a second node; an inverting module is electrically connected to the first voltage terminal, the first node, the second node, and the third node; and a pull-down sustaining module is electrically connected to the first voltage terminal, the first node, and the third node. When the pull-up control module electrically connects the first voltage terminal and the second node according to a pull-up control signal, the inverting module disconnects the electrical connection between the low-frequency clock signal terminal and the third node according to the potential of the second node, and the inverting module controls the electrical connection between the first voltage terminal and the third node according to the potential of the first node. Meanwhile, the pull-down sustaining module disconnects the electrical connection between the first voltage terminal and the first node according to the potential of the third node. Consequently, when the pull-up control module electrically connects the first voltage terminal and the second node according to the pull-up control signal, the low-frequency clock signal transmitted by the low-frequency clock signal terminal no longer acts on the third node, and only the first voltage signal supplied by the first voltage terminal acts on the third node. This improves the control speed of the pull-down sustaining module disconnecting the electrical connection between the first voltage terminal and the first node, thereby improving the problems of temperature rise and reduced reliability of the gate drive circuit.

[0030] Specifically, FIG1 is a principle block diagram of a gate drive circuit provided in an embodiment of the present application. The embodiment of the present application provides a gate drive circuit, which includes an inverting module 10 , a pull-down maintaining module 20 and a pull-up control module 30 .

[0031] The inverting module 10 is electrically connected to the first voltage terminal VGL, the first node N1, the second node N2 and the third node N3. The inverting module 10 is configured to control the signal transmission between the first voltage terminal VGL and the third node N3 according to the potential of the first node N1, and to control the signal transmission between the low-frequency clock signal terminal LC and the third node N3 according to the potential of the second node N2.

[0032] The pull-down maintaining module 20 is electrically connected to the first voltage terminal VGL, the first node N1 and the third node N3. The pull-down maintaining module 20 is configured to control signal transmission between the first voltage terminal VGL and the first node N1 according to the potential of the third node N3.

[0033] The pull-up control module 30 is electrically connected to the first voltage terminal VGL, the first node N1 and the second node N2. The pull-up control module 30 is configured to pull up the potential of the first node N1 according to a pull-up control signal UCS, and control the signal transmission between the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS.

[0034] Wherein, when the pull-up control module 30 is configured to electrically connect the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS, the inverting module 10 is configured to disconnect the electrical connection between the low-frequency clock signal terminal LC and the third node N3 according to the potential of the second node N2, and the inverting module 10 is configured to control the electrical connection between the first voltage terminal VGL and the third node N3 according to the potential of the first node N1, and the pull-down maintaining module 20 is configured to disconnect the electrical connection between the first voltage terminal VGL and the first node N1 according to the potential of the third node N3, so as to maintain the first voltage terminal VGL and the first node N1 in the pull-up control circuit. When module 30 electrically connects the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS, the low-frequency clock signal transmitted by the low-frequency clock signal terminal LC no longer acts on the third node N3, and only the first voltage signal supplied by the first voltage terminal VGL acts on the third node N3, so that the pull-down maintenance module 20 controls the electrical connection between the first voltage terminal VGL and the first node N1 to be disconnected only according to the action of the first voltage signal, which is beneficial to advance the time of disconnection of the electrical connection between the first voltage terminal VGL and the first node N1, thereby improving the problems of temperature rise and reduced reliability of the gate drive circuit.

[0035] Optionally, referring to FIG1 , in some embodiments, the pull-up control module 30 includes a first control unit 301 and a second control unit 302. The first control unit 301 is configured to control the raising of the potential of the first node N1 according to the pull-up control signal UCS, and the second control unit 302 is configured to control the signal transmission between the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS.

[0036] Fig. 2 is a schematic diagram of the structure of a gate driving circuit provided in an embodiment of the present application. Optionally, in some embodiments, the first control unit 301 includes a first transistor T1, and the second control unit 302 includes a second transistor T2.

[0037] The control terminal of the first transistor T1 is configured to receive the pull-up control signal UCS, the input terminal of the first transistor T1 is electrically connected to the control terminal of the first transistor T1 , and the output terminal of the first transistor T1 is electrically connected to the first node N1 .

[0038] The control end of the second transistor T2 is configured to receive the pull-up control signal UCS, the input end of the second transistor T2 is electrically connected to the first voltage end VGL, and the output end of the second transistor T2 is electrically connected to the second node N2.

[0039] 2 , in some embodiments, the inverting module 10 includes an inverting unit, and the inverting unit includes a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , and a sixth transistor T6 .

[0040] The control end of the third transistor T3 is electrically connected to the low-frequency clock signal end LC, the input end of the third transistor T3 is electrically connected to the control end of the third transistor T3, and the output end of the third transistor T3 is electrically connected to the second node N2.

[0041] The control end of the fourth transistor T4 is electrically connected to the second node N2 , the input end of the fourth transistor T4 is electrically connected to the low-frequency clock signal end LC, and the output end of the fourth transistor T4 is electrically connected to the third node N3 .

[0042] The control end of the fifth transistor T5 is electrically connected to the first node N1 , the input end of the fifth transistor T5 is electrically connected to the first voltage end VGL, and the output end of the fifth transistor T5 is electrically connected to the second node N2 .

[0043] The control end of the sixth transistor T6 is electrically connected to the first node N1 , the input end of the sixth transistor T6 is electrically connected to the first voltage end VGL, and the output end of the sixth transistor T6 is electrically connected to the third node N3 .

[0044] The third transistor T3 is configured to control signal transmission between the low-frequency clock signal terminal LC and the second node N2 according to the low-frequency clock signal transmitted by the low-frequency clock signal terminal LC, the fourth transistor T4 is configured to control signal transmission between the low-frequency clock signal terminal LC and the third node N3 according to the potential of the second node N2, the fifth transistor T5 is configured to control signal transmission between the first voltage terminal VGL and the second node N2 according to the potential of the first node N1, and the sixth transistor T6 is configured to control signal transmission between the first voltage terminal VGL and the third node N3 according to the potential of the first node N1.

[0045] Please continue to refer to Figure 2. In some embodiments, the pull-down maintenance module 20 includes a pull-down maintenance unit, and the pull-down maintenance unit includes a seventh transistor T7. The control end of the seventh transistor T7 is electrically connected to the third node N3, the input end of the seventh transistor T7 is electrically connected to the first voltage end VGL, and the output end of the seventh transistor T7 is electrically connected to the first node N1.

[0046] Optionally, please continue to refer to Figure 1. In some embodiments, the pull-up control module 30 also includes a third control unit 303, and the third control unit 303 is configured to control the signal transmission between the first voltage terminal VGL and the third node N3 according to the pull-up control signal UCS, so as to improve the control speed of the pull-down maintenance module 20 to disconnect the electrical connection between the first voltage terminal VGL and the first node N1 when the pull-up control module 30 electrically connects the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS, thereby further improving the problems of temperature rise and reduced reliability of the gate drive circuit.

[0047] Please continue to refer to Figure 2. In some embodiments, the third control unit 303 includes an eighth transistor T8, the control end of the eighth transistor T8 is configured to receive the pull-up control signal UCS, the input end of the eighth transistor T8 is electrically connected to the first voltage end VGL, and the output end of the eighth transistor T8 is electrically connected to the third node N3.

[0048] Optionally, in some embodiments, the pull-down maintaining module 20 is also electrically connected to the signal output terminal Gout of the gate drive circuit, and the pull-down maintaining module 20 is also configured to control the signal transmission between the first signal terminal and the signal output terminal Gout according to the potential of the third node N3.

[0049] Accordingly, please continue to refer to Figure 2. In some embodiments, the pull-down maintenance module 20 includes a ninth transistor T9, the control end of the ninth transistor T9 is electrically connected to the third node N3, the input end of the ninth transistor T9 is electrically connected to the first voltage end VGL, and the output end of the ninth transistor T9 is electrically connected to the signal output end Gout of the gate drive circuit.

[0050] Optionally, in some embodiments, the pull-down maintenance module 20 can electrically connect the output end of the seventh transistor T7 to the signal output end Gout, so as to omit the ninth transistor T9 by reusing the seventh transistor T7, thereby reducing the number of transistors used in the gate drive circuit.

[0051] Continuing with FIG1 , the gate drive circuit further includes an output module 40 , which is electrically connected to the first node N1 and the signal output terminal Gout of the gate drive circuit. The output module 40 is configured to control signal transmission between the high-frequency clock signal terminal CK and the signal output terminal Gout according to the potential of the first node N1 .

[0052] Accordingly, please continue to refer to Figure 2. In some embodiments, the output module 40 includes an output transistor To and a first capacitor C1. The control end of the output transistor To is electrically connected to the first node N1, the input end of the output transistor To is electrically connected to the high-frequency clock signal end CK, the output end of the output transistor To is electrically connected to the signal output end Gout of the gate drive circuit, and the first capacitor C1 is connected in series between the first node N1 and the signal output end Gout.

[0053] Please continue to refer to Figure 1. In some embodiments, the gate drive circuit also includes a pull-down control module 50, which is electrically connected to the first node N1 and the first voltage terminal VGL. The pull-down control module 50 is configured to control the signal transmission between the first node N1 and the first voltage terminal VGL according to a pull-down control signal DCS.

[0054] Accordingly, please continue to refer to Figure 2. In some embodiments, the pull-down control module 50 includes a first pull-down transistor Td1, the control end of the first pull-down transistor Td1 is configured to receive the pull-down control signal DCS, the input end of the first pull-down transistor Td1 is electrically connected to the first voltage end VGL, and the output end of the first pull-down transistor Td1 is electrically connected to the first node N1.

[0055] Optionally, in some embodiments, the pull-down control module 50 is also electrically connected to the signal output terminal Gout of the gate drive circuit, and the pull-down control module 50 is further configured to control the signal transmission between the first voltage terminal VGL and the signal output terminal Gout according to the pull-down control signal DCS.

[0056] Correspondingly, the pull-down control module 50 includes a second pull-down transistor, the control end of the second pull-down transistor is configured to receive the pull-down control signal DCS, the input end of the second pull-down transistor is electrically connected to the first voltage end VGL, and the output end of the second pull-down transistor is electrically connected to the signal output end Gout.

[0057] Please continue to refer to Figure 1. In some embodiments, the gate drive circuit also includes a reset module 60, which is electrically connected to the first node N1, the first voltage terminal VGL and the signal output terminal Gout of the gate drive circuit. The reset module 60 is configured to control the signal transmission between at least one of the first node N1 and the signal output terminal Gout and the first voltage terminal VGL according to a reset control signal Rst.

[0058] Optionally, please continue to refer to Figure 2. In some embodiments, the reset module 60 includes a first reset transistor Ti1 and a second reset transistor Ti2, and the control end of the first reset transistor Ti1 and the control end of the second reset transistor Ti2 are configured to receive a reset control signal Rst, the input end of the first reset transistor Ti1 and the input end of the second reset transistor Ti2 are electrically connected to the first voltage end VGL, the output end of the first reset transistor Ti1 is electrically connected to the first node N1, and the output end of the second reset transistor Ti2 is electrically connected to the signal output end Gout of the gate drive circuit.

[0059] Optionally, in some embodiments, the reset module 60 may include one of the first reset transistor Ti1 and the second reset transistor Ti2 .

[0060] Optionally, in some embodiments, the reset module 60 includes a reset transistor, wherein a control terminal of the reset transistor is configured to receive a reset control signal Rst, an input terminal of the reset transistor is electrically connected to the first voltage terminal VGL, and an output terminal of the reset transistor is electrically connected to at least one of the first node N1 and the signal output terminal Gout. By electrically connecting the output terminal of the reset transistor to both the first node N1 and the signal output terminal Gout, the number of transistors used in the gate drive circuit can be reduced, thereby saving costs. Furthermore, when the gate drive circuit is applied to a display panel, the display panel can be designed to have a narrow bezel.

[0061] Optionally, in some embodiments, the gate drive circuit further includes a level transmission module, which is electrically connected to the first node N1, the high-frequency clock signal terminal CK and the level transmission output terminal of the gate drive circuit, and the level transmission module is configured to control the signal transmission between the high-frequency clock signal terminal CK and the level transmission output terminal according to the potential of the first node N1.

[0062] Optionally, the stage transfer module includes a stage transfer transistor, the control end of the stage transfer transistor is electrically connected to the first node N1, the input end of the stage transfer transistor is electrically connected to the high-frequency clock signal end CK, and the output end of the stage transfer transistor is electrically connected to the stage transmission output end.

[0063] Optionally, in some embodiments, the pull-down maintenance module 20 further includes a tenth transistor, the control end of the tenth transistor is electrically connected to the third node N3, the input end of the tenth transistor is electrically connected to the first voltage end VGL, and the output end of the tenth transistor is electrically connected to the stage transmission output end.

[0064] Optionally, in some embodiments, the reset module 60 further includes a third reset transistor, the control end of the third reset transistor is configured to receive the reset control signal Rst, the input end of the third reset transistor is electrically connected to the first voltage end VGL, and the output end of the third reset transistor is electrically connected to the stage transmission output end.

[0065] It is understood that to reduce the number of transistors included in the gate drive circuit, the tenth transistor can be omitted by reusing the seventh transistor T7. That is, the output terminal of the seventh transistor T7 is also electrically connected to the stage transmission output terminal. Similarly, the third reset transistor can be omitted by reusing the reset transistor. That is, the output terminal of the reset transistor is also electrically connected to the stage transmission output terminal.

[0066] Figure 3 is a schematic diagram of the structure of another gate drive circuit provided by an embodiment of the present application. In some embodiments, the gate drive circuit may be provided with two inverting units, so that the two inverting units operate alternately at regular intervals, thereby extending the life cycle of the gate drive circuit. Accordingly, to match the configuration of the two inverting units, the pull-down maintenance module 20 includes two pull-down maintenance units, the second control unit 302 of the pull-up control module 30 may include two sub-control units, and the third control unit 303 of the pull-up control module 30 may include two sub-control units.

[0067] Correspondingly, the second node N2 includes a first subnode N21 and a second subnode N22, and the third node N3 includes a third subnode N31 and a fourth subnode N32. The low-frequency clock signal terminal LC includes a first low-frequency clock signal terminal LC1 and a second low-frequency clock signal terminal LC2.

[0068] The inverting module 10 includes a first inverting unit 101 and a second inverting unit 102. The output terminal of the third transistor T31, the control terminal of the fourth transistor T41, and the output terminal of the fifth transistor T51 of the first inverting unit 101 are electrically connected to the first sub-node N21. The output terminal of the fourth transistor T41 and the output terminal of the sixth transistor T61 of the first inverting unit 101 are electrically connected to the third sub-node N31. The control terminal of the third transistor T31 and the input terminal of the fourth transistor T41 of the first inverting unit 101 are electrically connected to the first low-frequency clock signal terminal LC1. The output terminal of the third transistor T32, the control terminal of the fourth transistor T42, and the output terminal of the fifth transistor T52 of the second inverting unit 102 are electrically connected to the second sub-node N22, the output terminal of the fourth transistor T42 and the output terminal of the sixth transistor T62 of the second inverting unit 102 are electrically connected to the fourth sub-node N32, and the control terminal of the third transistor T32 and the input terminal of the fourth transistor T42 of the second inverting unit 102 are electrically connected to the second low-frequency clock signal terminal LC2.

[0069] The pull-down maintaining module 20 includes a first pull-down maintaining unit 201 and a second pull-down maintaining unit 202. The control terminal of the seventh transistor T71 of the first pull-down maintaining unit 201 is electrically connected to the third sub-node N31, and the control terminal of the seventh transistor T72 of the second pull-down maintaining unit 202 is electrically connected to the fourth sub-node N32.

[0070] Optionally, in some embodiments, the control end of the ninth transistor T91 of the first pull-down maintaining unit 201 is electrically connected to the third subnode N31, and the control end of the ninth transistor T92 of the second pull-down maintaining unit 202 is electrically connected to the fourth subnode N32.

[0071] The second control unit 302 of the pull-up control module 30 includes a first sub-control unit 3021 and a second sub-control unit 3022. The output end of the second transistor T21 of the first sub-control unit 3021 is electrically connected to the first sub-node N21, and the output end of the second transistor T22 of the second sub-control unit 3022 is electrically connected to the second sub-node N22.

[0072] The third control unit 303 of the pull-up control module 30 includes a third sub-control unit 3031 and a fourth sub-control unit 3032. The output end of the eighth transistor T81 of the third sub-control unit 3031 is electrically connected to the third sub-node N31, and the output end of the eighth transistor T82 of the fourth sub-control unit 3032 is electrically connected to the fourth sub-node N32.

[0073] It should be noted that the second transistor T21 of the first sub-control unit 3021 and the second transistor T22 of the second sub-control unit 3022 are two transistors, rather than a single transistor. Similarly, the third transistor T31 of the first inverting unit 101 and the third transistor T32 of the second inverting unit 102 are two transistors, the fourth transistor T41 of the first inverting unit 101 and the fourth transistor T42 of the second inverting unit 102 are two transistors, the fifth transistor T51 of the first inverting unit 101 and the fifth transistor T52 of the second inverting unit 102 are two transistors, and the sixth transistor T61 of the first inverting unit 101 and the sixth transistor T62 of the second inverting unit 102 are two transistors. The seventh transistor T71 of the first pull-down maintaining unit 201 and the seventh transistor T72 of the second pull-down maintaining unit 202 are two transistors, the eighth transistor T81 of the third sub-control unit 3031 and the eighth transistor T82 of the fourth sub-control unit 3032 are two transistors, and the ninth transistor T91 of the first pull-down maintaining unit 201 and the ninth transistor T92 of the second pull-down maintaining unit 202 are two transistors.

[0074] Figure 4 is a timing diagram of the corresponding gate drive circuit provided in an embodiment of the present application, assuming that all transistors included in the gate drive circuit are N-type transistors; in the gate drive circuit shown in Figure 2, the low-frequency clock signal transmitted by the low-frequency clock signal terminal LC is taken as an example to illustrate the working principle of the gate drive circuit shown in Figure 2.

[0075] In the first phase t1, the reset signal Rst is in a high-level state, the pull-up control signal UCS, the high-frequency clock signal CKa transmitted by the high-frequency clock signal terminal CK, and the pull-down control signal DCS are in a low-level state. The first reset transistor Ti1 and the second reset transistor Ti2 are turned on, and the first voltage terminal VGL is electrically connected to the first node N1 and the signal output terminal Gout.

[0076] In the second phase t2, the pull-up control signal UCS is in a high-level state, the high-frequency clock signal CKa transmitted by the high-frequency clock signal terminal CK and the pull-down control signal DCS are in a low-level state. The first transistor T1, the second transistor T2, the output transistor To, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, and the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the first pull-down transistor Td1, the first reset transistor Ti1, and the second reset transistor Ti2 are turned off.

[0077] In the third phase t3, the high-frequency clock signal CKa is in a high-level state, the pull-up control signal UCS and the pull-down control signal DCS are in a low-level state, the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned off, the output transistor To, the fifth transistor T5, and the sixth transistor T6 remain turned on, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the first pull-down transistor Td1 remain turned off, and the gate control signal Scan output by the signal output terminal Gout is in a high-level state.

[0078] In the fourth phase t4, the pull-down control signal DCS is in a high-level state, the pull-up control signal UCS and the high-frequency clock signal CKa are in a low-level state, the first transistor T1, the second transistor T2, and the eighth transistor T8 remain off, the first pull-down transistor Td1 is turned on, the output transistor To, the fifth transistor T5, and the sixth transistor T6 are turned off, and the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the ninth transistor T9 are turned on.

[0079] In the gate drive circuit shown in Figure 3, the first low-frequency clock signal LCa supplied by the first low-frequency clock signal terminal LC1 can have one of a high level state and a low level state, and the second low-frequency clock signal LCb supplied by the second low-frequency clock signal terminal LC2 can have the other of a high level state and a low level state.

[0080] FIG5 is a simulation timing diagram of the gate drive circuit according to an embodiment of the present application before improvement, and FIG6 is a simulation timing diagram of the gate drive circuit according to an embodiment of the present application after improvement. In particular, L1 represents the potential change curve of the first node N1, L21 represents the potential change curve of the second node N2 before improvement, L22 represents the potential change curve of the second node N2 after improvement, and L3 represents the gate control signal Scan at the signal output terminal Gout. The inventors of the present application conducted simulation analysis on the gate drive circuit before and after improvement. The simulation results show that, before improvement, there is an overlapping time period ta between the potential rise process of the first node N1 and the potential fall process of the second node N2, causing the seventh transistor T7 to be turned on during the corresponding time period ta, resulting in a leakage path between the first node N1 and the first voltage terminal VGL. After the improvement, before the potential of the first node N1 is raised, the potential of the second node N2 can be pulled down to the voltage corresponding to the first voltage terminal VGL under the control of the pull-up control module 30, thereby reducing the leakage between the first node N1 and the first voltage terminal VGL during the process of the potential raising of the first node N1, improving the potential raising effect of the first node N1, and then improving the problems of temperature rise and reduced reliability of the gate drive circuit.

[0081] FIG7 is a schematic structural diagram of a display panel provided in an embodiment of the present application. The present application further provides a display panel including a gate driving unit GDU, wherein the gate driving unit includes a plurality of any of the above-mentioned gate driving circuits (as shown in GDC in FIG7 ).

[0082] Continuing with FIG. 7 , the display panel includes a plurality of sub-pixels Spi, a plurality of scan lines SL, and a plurality of data lines DL. The plurality of sub-pixels Spi are electrically connected to the gate driving unit GDU, the plurality of scan lines SL, and the plurality of data lines DL. The plurality of sub-pixels Spi achieve display based on a plurality of gate control signals output by the gate driving unit GDU. The plurality of gate control signals are transmitted to the plurality of sub-pixels Spi via the scan lines SL.

[0083] FIG8 is a diagram illustrating a cascade relationship of multiple gate drive circuits provided in an embodiment of the present application. Optionally, in some embodiments, multiple gate drive circuits are cascaded. The pull-up control signal UCS received by the first x gate drive circuits in the multiple cascaded gate drive circuits is provided by a device such as a control chip.

[0084] For example, the pull-up control signal UCS received by the first two stages of gate driver circuits in the multiple cascaded gate driver circuits is provided by the control chip. That is, the control chip generates a first start signal STV1 and a second start signal STV2. The first start signal STV1 serves as the pull-up control signal UCS received by the first stage of gate driver circuit GDC1 in the multiple cascaded gate driver circuits, and the second start signal STV2 serves as the pull-up control signal UCS received by the second stage of gate driver circuit GDC2 in the multiple cascaded gate driver circuits.

[0085] Optionally, the control chip includes a timing controller, etc.

[0086] Optionally, the np-th-stage gate control signal Scan(np) outputted from the signal output terminal Gout by the np-th-stage gate driver circuit GDC(np) or the np-th-stage transmission control signal outputted from the stage transmission output terminal by the np-th-stage gate driver circuit GDC(np) corresponds to the pull-up control signal UCS received by the n-th-stage gate driver circuit GDC(n), where n>1 and m≥1.

[0087] Optionally, the n-4th-level gate control signal Scan(n-4) output by the n-4th-level gate drive circuit GDC(n-4) serves as the pull-up control signal UCS received by the pull-up control module 30 of the nth-level gate drive circuit GDC(n).

[0088] Optionally, in some embodiments, the n+qth-stage gate control signal Scan(n+q) outputted from the signal output terminal Gout by the n+qth-stage gate driver circuit GDC(n+q) or the n+qth-stage stage transmission control signal outputted from the stage transmission output terminal by the n+qth-stage gate driver circuit GDC(n+q) corresponds to the pull-up control signal UCS received by the nth-stage gate driver circuit GDC(n), where q≥1.

[0089] Optionally, the n+4th-stage gate control signal Scan(n+4) output by the n+4th-stage gate driving circuit GDC(n+4) serves as the pull-down control signal DCS received by the nth-stage gate driving circuit GDC(n).

[0090] Optionally, in some embodiments, the plurality of gate drive circuits share the low-frequency clock signal supplied by the low-frequency clock signal terminal LC, i.e., the plurality of gate drive circuits are electrically connected to the low-frequency clock signal terminal LC. Furthermore, the plurality of gate drive circuits are electrically connected to the first low-frequency clock signal terminal LC1 and the second low-frequency clock signal terminal LC2.

[0091] Optionally, in some embodiments, the plurality of gate driving circuits share a plurality of high-frequency clock signals CKa, so as to reduce the number of high-frequency clock signals CKa applied to the display panel and save border layout space.

[0092] Optionally, the plurality of gate driving circuits share y high-frequency clock signals CKa, where y is 2, 4, 6, 8, 12, etc.

[0093] Figure 9 is a schematic diagram of the correspondence between the gate drive circuit and the high-frequency clock signal provided by an embodiment of the present application. Optionally, in some embodiments, a plurality of the gate drive circuits share 8 high-frequency clock signals CKa, the high-frequency clock signal CKa received by the 8z+1-th level gate drive circuit GDC (8z+1) corresponds to the first high-frequency clock signal CK1, the high-frequency clock signal CKa received by the 8z+2-th level gate drive circuit GDC (8z+2) corresponds to the second high-frequency clock signal CK2, the high-frequency clock signal CKa received by the 8z+3-th level gate drive circuit GDC (8z+3) corresponds to the third high-frequency clock signal CK3, the high-frequency clock signal CKa received by the 8z+4-th level gate drive circuit GDC (8z+4) corresponds to the third high-frequency clock signal CK4. CKa corresponds to the fourth high-frequency clock signal CK4, the high-frequency clock signal CKa received by the 8z+5th-level gate drive circuit GDC (8z+5) corresponds to the fifth high-frequency clock signal CK5, the high-frequency clock signal CKa received by the 8z+6th-level gate drive circuit GDC (8z+6) corresponds to the sixth high-frequency clock signal CK6, the high-frequency clock signal CKa received by the 8z+7th-level gate drive circuit GDC (8z+7) corresponds to the seventh high-frequency clock signal CK7, and the high-frequency clock signal CKa received by the 8z+8th-level gate drive circuit GDC (8z+8) corresponds to the eighth high-frequency clock signal CK8. Wherein, z≥0.

[0094] Figure 10 is a driving timing diagram of a display panel provided in an embodiment of the present application. Optionally, in some embodiments, the display panel supports not only display functions but also touch functions. Thus, a frame duration may include at least one display phase Dt and at least one sensing phase St. In some embodiments, the sensing phase St may correspond to a touch phase.

[0095] However, when the display panel enters the sensing stage St from the display stage Dt, the potential of the first node N1 of some gate driver circuits has been raised, but the corresponding high-frequency clock signal CKa is not yet at a high level, so the output gate control signal is not yet at a valid level. Therefore, when the display panel re-enters the display stage Dt from the sensing stage St, it is necessary to resume operation of some gate driver circuits so that the gate control signals output by the multiple gate driver circuits meet display requirements.

[0096] If the potential of the first node N1 of the gate drive circuit of the partial stage changes during the sensing stage St, the degree of conduction of the output transistor To will change. Subsequently, when the display panel re-enters the display stage Dt from the sensing stage St, the voltage corresponding to the effective level state of the gate control signal output by the gate drive circuit of the partial stage will be different, thereby causing charging differences in the sub-pixels of the corresponding rows in the display panel, and then causing problems such as display stripes.

[0097] If, in the sensing stage St, the potential change of the first node N1 of the gate driving circuit of the partial stage causes the output transistor To to be cut off, then when the display panel re-enters the display stage Dt from the sensing stage St, the gate control signal output by the gate driving circuit of the partial stage will not have a valid level state, and the multi-stage gate driving circuits cascaded thereafter will also output gate control signals that do not have a valid level state because the corresponding pull-up control signal UCS has no valid level state, thereby causing the sub-pixels of the corresponding row in the display panel to be unable to perform the charging action, and then display abnormalities and other problems.

[0098] Therefore, in the sensing stage St, it is necessary to keep the potential of the first node N1 of the gate driving circuit of at least some stages stable so that when the display panel re-enters the display stage Dt from the sensing stage St, the multiple gate control signals output by the multi-stage gate driving circuit can normally have a valid level state, thereby improving the display problem.

[0099] To this end, in the sensing stage St, the pull-down maintenance module 20 can be kept in a setting of disconnecting the electrical connection between the first voltage terminal VGL and the first node N1 by controlling the low-frequency clock signal terminal LC to correspond to the low-frequency clock signal, so that the potential of the first node N1 of the gate drive circuit of at least part of the stage remains stable.

[0100] Optionally, in some embodiments, the voltage of the low-frequency clock signal LCS transmitted by the low-frequency clock signal terminal LC in the sensing stage St of the display panel is less than the voltage of the low-frequency clock signal LCS in the display stage Dt of the display panel, so that the potential of the first node N1 of the gate drive circuit of at least part of the stage remains stable.

[0101] Optionally, in the sensing stage St, the low-frequency clock signal LCS can jump between a first voltage and a second voltage, but in order to keep the potential of the first node N1 of the gate drive circuit of at least part of the stage stable in the sensing stage St, the first voltage and the second voltage are both lower than the voltage of the low-frequency clock signal LCS in the display stage Dt of the display panel.

[0102] Optionally, in some embodiments, when the first inverting unit 101 is working and the second inverting unit 102 is not working, the voltage of the first low-frequency clock signal LCa transmitted by the first low-frequency clock signal terminal LC1 in the sensing stage St of the display panel is less than the voltage of the first low-frequency clock signal LCa in the display stage Dt of the display panel, so that the potential of the first node N1 of the gate drive circuit of at least part of the stage remains stable.

[0103] Optionally, in some embodiments, when the first inverting unit 101 is not working and the second inverting unit 102 is working, the voltage of the second low-frequency clock signal LCb transmitted by the second low-frequency clock signal terminal LC2 in the sensing stage St of the display panel is less than the voltage of the second low-frequency clock signal LCb in the display stage Dt of the display panel, so as to keep the potential of the first node N1 of the gate drive circuit of at least part of the stage stable.

[0104] Optionally, in the display stage Dt, the first low-frequency clock signal LCa and the second low-frequency clock signal LCb are inverted, so that only one inverting unit works in one display stage Dt.

[0105] Optionally, in the display phase Dt of consecutive t frames, the first low-frequency clock signal LCa has one of a high level state and a low level state, and the second low-frequency clock signal LCb has the other of a high level state and a low level state.

[0106] Optionally, every t frames of data displayed by the display panel, the first low-frequency clock signal LCa transitions from a first level state to a second level state, and the second low-frequency clock signal LCb transitions from a second level state to a first level state. The first level state is one of a high level state and a low level state, and the second level state is the other of the high level state and the low level state. Optionally, t is 100.

[0107] Optionally, during the blanking interval, the first low-frequency clock signal LCa transitions between a first level state and a second level state, and the second low-frequency clock signal LCb transitions between a second level state and a first level state.

[0108] Optionally, the blanking interval stage includes a vertical blanking interval Bt stage.

[0109] Optionally, the reset control signal Rst may have an effective level state at the beginning of each frame, so that the reset module 60 controls the first voltage terminal VGL in the gate drive circuit to be electrically connected to at least one of the first node N1 and the signal output terminal Gout according to the reset control signal Rst.

[0110] Optionally, the plurality of gate driving circuits share the same reset control signal Rst, so as to reduce the number of control signals used by the gate driving unit and reduce the control complexity of the display panel.

[0111] It can be understood that when the gate driving circuit used in the display panel includes a stage transmission module, the settings and corresponding effects of each gate driving circuit in the gate driving unit can be obtained by referring to the corresponding similar reasoning described when the gate driving circuit does not include a stage transmission module, and will not be repeated here.

[0112] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. A gate drive circuit, wherein: include: an inverting module, electrically connected to the first voltage terminal, the first node, the second node, and the third node, and configured to control signal transmission between the first voltage terminal and the third node according to the potential of the first node, and to control signal transmission between the low-frequency clock signal terminal and the third node according to the potential of the second node; a pull-down maintaining module, electrically connected to the first voltage terminal, the first node, and the third node, and configured to control signal transmission between the first voltage terminal and the first node according to the potential of the third node; as well as a pull-up control module, electrically connected to the first voltage terminal, the first node, and the second node, configured to pull up the potential of the first node according to a pull-up control signal, and control signal transmission between the first voltage terminal and the second node according to the pull-up control signal; Among them, when the pull-up control module is configured to electrically connect the first voltage end and the second node according to the pull-up control signal, the inverting module is configured to disconnect the electrical connection between the low-frequency clock signal end and the third node according to the potential of the second node, and control the electrical connection between the first voltage end and the third node according to the potential of the first node, and the pull-down maintenance module is configured to disconnect the electrical connection between the first voltage end and the first node according to the potential of the third node.

2. The gate drive circuit according to claim 1, wherein: The pull-up control module includes: a first control unit, comprising a first transistor, wherein a control terminal of the first transistor is configured to receive the pull-up control signal, an input terminal of the first transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the first transistor is electrically connected to the first node; and The second control unit includes a second transistor, wherein the control end of the second transistor is configured to receive the pull-up control signal, the input end of the second transistor is electrically connected to the first voltage end, and the output end of the second transistor is electrically connected to the second node.

3. The gate driving circuit according to claim 2, wherein: The inverting module includes: a third transistor, wherein a control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, an input terminal of the third transistor is electrically connected to the control terminal of the third transistor, and an output terminal of the third transistor is electrically connected to the second node; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the second node, an input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and an output terminal of the fourth transistor is electrically connected to the third node; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the first node, an input terminal of the fifth transistor is electrically connected to the first voltage terminal, and an output terminal of the fifth transistor is electrically connected to the second node; and a sixth transistor, wherein a control terminal of the sixth transistor is electrically connected to the first node, an input terminal of the sixth transistor is electrically connected to the first voltage terminal, and an output terminal of the sixth transistor is electrically connected to the third node.

4. The gate driving circuit according to claim 3, wherein: The pull-down maintaining module includes: a seventh transistor, wherein a control terminal of the seventh transistor is electrically connected to the third node, an input terminal of the seventh transistor is electrically connected to the first voltage terminal, and an output terminal of the seventh transistor is electrically connected to the first node.

5. The gate driving circuit according to claim 4, wherein: The pull-up control module further includes: The third control unit includes an eighth transistor, the control end of the eighth transistor is configured to receive the pull-up control signal, the input end of the eighth transistor is electrically connected to the first voltage end, and the output end of the eighth transistor is electrically connected to the third node.

6. The gate driving circuit according to claim 5, wherein: The second node includes a first sub-node and a second sub-node, and the third node includes a third sub-node and a fourth sub-node; The low-frequency clock signal terminal includes a first low-frequency clock signal terminal and a second low-frequency clock signal terminal; The inverting module includes a first inverting unit and a second inverting unit, wherein the output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor of the first inverting unit are electrically connected to the first sub-node, the output terminal of the fourth transistor and the output terminal of the sixth transistor of the first inverting unit are electrically connected to the third sub-node, and the control terminal of the third transistor and the input terminal of the fourth transistor of the first inverting unit are electrically connected to the first low-frequency clock signal terminal; the output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor of the second inverting unit are electrically connected to the second sub-node, the output terminal of the fourth transistor and the output terminal of the sixth transistor of the second inverting unit are electrically connected to the fourth sub-node, and the control terminal of the third transistor and the input terminal of the fourth transistor of the second inverting unit are electrically connected to the second low-frequency clock signal terminal; The pull-down maintaining module includes a first pull-down maintaining unit and a second pull-down maintaining unit, wherein the control terminal of the seventh transistor of the first pull-down maintaining unit is electrically connected to the third sub-node, and the control terminal of the seventh transistor of the second pull-down maintaining unit is electrically connected to the fourth sub-node; The second control unit of the pull-up control module includes a first sub-control unit and a second sub-control unit, wherein the output terminal of the second transistor of the first sub-control unit is electrically connected to the first sub-node, and the output terminal of the second transistor of the second sub-control unit is electrically connected to the second sub-node; The third control unit of the pull-up control module includes a third sub-control unit and a fourth sub-control unit, the output end of the eighth transistor of the third sub-control unit is electrically connected to the third sub-node, and the output end of the eighth transistor of the fourth sub-control unit is electrically connected to the fourth sub-node.

7. The gate driving circuit according to claim 1, wherein: The pull-down maintenance module includes a ninth transistor, the control end of the ninth transistor is electrically connected to the third node, the input end of the ninth transistor is electrically connected to the first voltage end, and the output end of the ninth transistor is electrically connected to the signal output end of the gate drive circuit.

8. The gate driving circuit according to claim 1, wherein: The gate drive circuit further includes: an output module, comprising an output transistor and a first capacitor, wherein a control terminal of the output transistor is electrically connected to the first node, an input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, an output terminal of the output transistor is electrically connected to a signal output terminal of the gate drive circuit, and the first capacitor is connected in series between the first node and the signal output terminal; a pull-down control module, comprising a first pull-down transistor, wherein a control terminal of the first pull-down transistor is configured to receive a pull-down control signal, an input terminal of the first pull-down transistor is electrically connected to the first voltage terminal, and an output terminal of the first pull-down transistor is electrically connected to the first node; and A reset module includes a first reset transistor and a second reset transistor, wherein the control end of the first reset transistor and the control end of the second reset transistor are configured to receive a reset control signal, the input end of the first reset transistor and the input end of the second reset transistor are electrically connected to the first voltage end, the output end of the first reset transistor is electrically connected to the first node, and the output end of the second reset transistor is electrically connected to the signal output end of the gate drive circuit.

9. The gate driving circuit according to claim 8, wherein: The pull-down control module includes a second pull-down transistor, the control end of the second pull-down transistor is configured to receive the pull-down control signal, the input end of the second pull-down transistor is electrically connected to the first voltage end, and the output end of the second pull-down transistor is electrically connected to the signal output end.

10. The gate driving circuit according to claim 8, wherein: The gate drive circuit further includes: The stage transfer module includes a stage transfer transistor, the control end of the stage transfer transistor is electrically connected to the first node, the input end of the stage transfer transistor is electrically connected to the high-frequency clock signal end, and the output end of the stage transfer transistor is electrically connected to the stage transmission output end of the gate drive circuit.

11. The gate driving circuit according to claim 10, wherein: The pull-down maintaining module further includes a tenth transistor, the control end of the tenth transistor is electrically connected to the third node, the input end of the tenth transistor is electrically connected to the first voltage end, and the output end of the tenth transistor is electrically connected to the stage transmission output end.

12. The gate driving circuit according to claim 10, wherein: The reset module also includes a third reset transistor, the control end of the third reset transistor is configured to receive the reset control signal, the input end of the third reset transistor is electrically connected to the first voltage end, and the output end of the third reset transistor is electrically connected to the stage transmission output end.

13. A display panel, wherein: The gate driving unit includes a plurality of gate driving circuits, and the plurality of gate driving circuits are cascaded; At least one of the gate drive circuits comprises: an inverting module, electrically connected to the first voltage terminal, the first node, the second node, and the third node, and configured to control signal transmission between the first voltage terminal and the third node according to the potential of the first node, and to control signal transmission between the low-frequency clock signal terminal and the third node according to the potential of the second node; a pull-down maintaining module, electrically connected to the first voltage terminal, the first node, and the third node, and configured to control signal transmission between the first voltage terminal and the first node according to the potential of the third node; and a pull-up control module, electrically connected to the first voltage terminal, the first node, and the second node, configured to pull up the potential of the first node according to a pull-up control signal, and control signal transmission between the first voltage terminal and the second node according to the pull-up control signal; Wherein, when the pull-up control module is configured to electrically connect the first voltage terminal and the second node according to the pull-up control signal, the inversion module is configured to disconnect the electrical connection between the low-frequency clock signal terminal and the third node according to the potential of the second node, and control the electrical connection between the first voltage terminal and the third node according to the potential of the first node, and the pull-down maintenance module is configured to disconnect the electrical connection between the first voltage terminal and the first node according to the potential of the third node; The n-4th-level gate control signal output by the n-4th-level gate driving circuit serves as the pull-up control signal received by the pull-up control module of the nth-level gate driving circuit.

14. The display panel according to claim 13, wherein: The voltage of the low-frequency clock signal transmitted by the low-frequency clock signal terminal during the sensing phase of the display panel is lower than the voltage of the low-frequency clock signal during the display phase of the display panel.

15. The display panel according to claim 13, wherein: The display panel includes a plurality of sub-pixels, and the plurality of sub-pixels are electrically connected to the gate driving unit.

16. The display panel according to claim 13, wherein: The pull-up control module includes: a first transistor, wherein a control terminal of the first transistor is configured to receive the pull-up control signal, an input terminal of the first transistor is electrically connected to the control terminal of the first transistor, and an output terminal of the first transistor is electrically connected to the first node; and A second transistor, wherein the control terminal of the second transistor is configured to receive the pull-up control signal, the input terminal of the second transistor is electrically connected to the first voltage terminal, and the output terminal of the second transistor is electrically connected to the second node.

17. The display panel according to claim 16, wherein: The inverting module includes: a third transistor, wherein a control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, an input terminal of the third transistor is electrically connected to the control terminal of the third transistor, and an output terminal of the third transistor is electrically connected to the second node; a fourth transistor, wherein a control terminal of the fourth transistor is electrically connected to the second node, an input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and an output terminal of the fourth transistor is electrically connected to the third node; a fifth transistor, wherein a control terminal of the fifth transistor is electrically connected to the first node, an input terminal of the fifth transistor is electrically connected to the first voltage terminal, and an output terminal of the fifth transistor is electrically connected to the second node; and a sixth transistor, wherein a control terminal of the sixth transistor is electrically connected to the first node, an input terminal of the sixth transistor is electrically connected to the first voltage terminal, and an output terminal of the sixth transistor is electrically connected to the third node.

18. The display panel according to claim 17, wherein: The pull-down maintaining module includes: a seventh transistor, wherein a control terminal of the seventh transistor is electrically connected to the third node, an input terminal of the seventh transistor is electrically connected to the first voltage terminal, and an output terminal of the seventh transistor is electrically connected to the first node.

19. The display panel according to claim 18, wherein: The pull-up control module further includes: An eighth transistor, wherein the control terminal of the eighth transistor is configured to receive the pull-up control signal, the input terminal of the eighth transistor is electrically connected to the first voltage terminal, and the output terminal of the eighth transistor is electrically connected to the third node.

20. The display panel according to claim 13, wherein The gate drive circuit further includes: an output module, comprising an output transistor and a first capacitor, wherein a control terminal of the output transistor is electrically connected to the first node, an input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, an output terminal of the output transistor is electrically connected to a signal output terminal of the gate drive circuit, and the first capacitor is connected in series between the first node and the signal output terminal; a pull-down control module, comprising a first pull-down transistor, wherein a control terminal of the first pull-down transistor is configured to receive a pull-down control signal, an input terminal of the first pull-down transistor is electrically connected to the first voltage terminal, and an output terminal of the first pull-down transistor is electrically connected to the first node; and A reset module includes a first reset transistor and a second reset transistor, wherein the control end of the first reset transistor and the control end of the second reset transistor are configured to receive a reset control signal, the input end of the first reset transistor and the input end of the second reset transistor are electrically connected to the first voltage end, the output end of the first reset transistor is electrically connected to the first node, and the output end of the second reset transistor is electrically connected to the signal output end of the gate drive circuit.

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