Semiconductor structure and method for forming same

Abstract

A semiconductor structure and a method for forming same. The method comprises: providing a substrate, wherein a first opening is formed in the substrate, and the first opening exposes part of the sidewall surface of the substrate; forming in the first opening a first barrier layer and a second barrier layer located on the surface of the first barrier layer; forming a dielectric layer structure on the surface of the substrate; and forming a second opening in the dielectric layer structure, wherein the second opening exposes the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and part of the surface of the first barrier layer. In an etching process for forming the second opening, a ratio of the etching rate of the material of the second barrier layer to the etching rate of the material of the first barrier layer is a first ratio. The material loss of the second barrier layer is greater than that of the first barrier layer within the same period of time, so that a composite barrier layer consisting of both the first barrier layer and the second barrier layer exhibits increased lateral and vertical loss during high-aspect-ratio etching compared to a barrier layer consisting of only the first barrier layer, thereby increasing a bottom critical dimension of the second opening obtained by etching.

Description

Semiconductor structure and method for forming the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 29, 2024, with application number 2024101243076 and invention name “Semiconductor structure and method for forming the same”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0003] With the development of 3D NAND flash memory, the introduction of three-dimensional structures in 3D flash memory has further increased the depth-to-width ratio of these structures, placing higher demands on etching technology. The material of the etch stop layer has a significant impact on the critical dimensions and morphology of the etched structure.

[0004] However, currently, in high aspect ratio etching, the etch stop layer still has defects.

[0005] Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the morphology of the structure after etching.

[0007] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate has a first opening, the first opening exposing a portion of the sidewall surface of the substrate; forming a first barrier layer and a second barrier layer located on the surface of the first barrier layer in the first opening; forming a dielectric layer structure on the surface of the substrate; forming a second opening in the dielectric layer structure, the second opening exposing the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer, wherein the etching process for forming the second opening has a first ratio between the etching rate of the second barrier layer material and the etching rate of the first barrier layer material.

[0008] Optionally, the method for forming the first barrier layer includes: forming an initial first barrier layer in the first opening; flattening the initial first barrier layer until the surface of the initial first barrier layer is flush with the substrate; and etching back the initial first barrier layer to form a first barrier layer.

[0009] Optionally, the method for forming the second barrier layer includes: forming an initial second barrier layer on the surface of the first barrier layer; and planarizing the initial second barrier layer until the substrate surface is exposed to form the second barrier layer.

[0010] Optionally, the back etching method includes: dry etching.

[0011] Optionally, the thickness ratio of the first barrier layer to the second barrier layer is in the range of 3:7 to 7:3.

[0012] Optionally, the material of the first barrier layer includes aluminum oxide; the thickness of the first barrier layer is in the range of: The formation process of the first barrier layer includes: physical vapor deposition and chemical vapor deposition; the process parameters of the formation process of the first barrier layer include: the time range for depositing the first barrier layer is 25 minutes to 45 minutes, the gas pressure intensity for depositing the first barrier layer is 1 torr to 2 torr, and the temperature range for depositing the first barrier layer is 350°C to 450°C.

[0013] Optionally, the material of the second barrier layer includes silicon oxide; the thickness of the second barrier layer is in the range of: The formation process of the second barrier layer includes HARP; the process parameters of the formation process of the second barrier layer include: the time range for depositing the second barrier layer is 25 minutes to 45 minutes, the gas pressure intensity for depositing the second barrier layer is 600 torr, the temperature range for depositing the second barrier layer is 500°C to 600°C, the gas for depositing the second barrier layer includes tetraethoxysilane and ozone, the flow range of the tetraethoxysilane is: 1000sccm to 10000sccm, and the flow range of the ozone is: 50000sccm to 10000sccm.

[0014] Optionally, the first ratio ranges from 10:1 to 20:1.

[0015] Optionally, the method for forming the second opening includes: forming a hard mask layer on the surface of the dielectric layer structure; etching the dielectric layer structure using the hard mask layer as a mask to form a second opening, wherein the second opening exposes the side wall surface of the dielectric layer structure, the side wall surface of the second barrier layer, and part of the surface of the first barrier layer.

[0016] Optionally, the dielectric layer structure includes: a stack of several first dielectric layers and second dielectric layers; the number of layers of the first dielectric layer ranges from 1 to 3 layers; the number of layers of the second dielectric layer ranges from 1 to 3 layers; the material of the first dielectric layer includes: silicon oxide, silicon nitride, silicon oxynitride and amorphous carbon; the material of the second dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride and amorphous carbon.

[0017] Optionally, after forming the second opening, the method further includes: forming a channel in the second opening; after forming the channel, removing the first dielectric layer, and forming a gate layer between adjacent second dielectric layers; after forming the gate layer, removing the second dielectric layer, and performing source-drain doping on the channel exposed by the adjacent gate layer; and after performing source-drain doping, forming a source-drain conductive layer between adjacent gate layers.

[0018] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate having a first opening, the first opening exposing a portion of the sidewall surface of the substrate; a first barrier layer located in the first opening and a second barrier layer located on the surface of the first barrier layer, the material of the second barrier layer being different from that of the first barrier layer; a device layer located on the surface of the substrate, the device layer having a second opening, the second opening exposing the sidewall surface of the device layer, the sidewall surface of the second barrier layer and a portion of the surface of the first barrier layer.

[0019] Optionally, the first barrier layer material includes aluminum oxide; the thickness of the first barrier layer is in the range of:

[0020] Optionally, the second barrier layer material includes silicon oxide; the thickness of the second barrier layer is in the range of:

[0021] Optionally, the thickness ratio of the first barrier layer to the second barrier layer is in the range of 3:7 to 7:3.

[0022] Optionally, it further includes: a channel located in the second opening.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] In the semiconductor structure of the technical solution of the present invention, the material of the second barrier layer is different from the material of the first barrier layer. The etching conditions can be adjusted for the second barrier layer and the first barrier layer materials so that the loss of the second barrier layer is greater than the loss of the first barrier layer. As a result, the composite barrier layer of the first and second barrier layers has increased lateral and longitudinal losses in high aspect ratio etching compared to the barrier layer made of only the first barrier layer material, thereby increasing the critical bottom size of the second opening obtained by etching, solving the problem of incomplete etching of the second opening, and improving the morphology of the second opening.

[0025] In the method for forming a semiconductor structure invented by the present invention, a first barrier layer and a second barrier layer located on the surface of the first barrier layer are formed in the first opening. The etching process for forming the second opening has a first ratio between the etching rate of the second barrier layer material and the etching rate of the first barrier layer material. The loss of the second barrier layer is greater than the loss of the first barrier layer. As a result, the composite barrier layer of the first and second barrier layers has increased lateral and longitudinal losses in high aspect ratio etching compared to the barrier layer made of only the first barrier layer material. The bottom critical dimension of the second opening obtained by etching is increased, thereby solving the problem of incomplete etching of the second opening and improving the morphology of the second opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] 1 to 8 are schematic cross-sectional views of the formation process of a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] As described in the background art, in the existing high aspect ratio etching, the etch stop layer still has defects.

[0028] In an embodiment of a high aspect ratio etch stop layer, aluminum oxide is used as the stop layer, resulting in insufficient etching and a small critical dimension of the etched opening.

[0029] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, wherein a first barrier layer and a second barrier layer located on the surface of the first barrier layer are formed in the first opening, and the etching process for forming the second opening has a first ratio between the etching rate of the second barrier layer material and the etching rate of the first barrier layer material, and the loss of the second barrier layer is greater than the loss of the first barrier layer, so that the composite barrier layer of the first and second barrier layers has increased lateral and longitudinal losses in high aspect ratio etching compared to the barrier layer made of only the first barrier layer material, and the bottom critical dimension of the second opening obtained by etching is increased, thereby solving the problem of incomplete etching of the second opening and improving the morphology of the second opening.

[0030] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0031] 1 to 8 are schematic cross-sectional views of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0032] Referring to FIG. 1 , a substrate 100 is provided. The substrate 100 has a first opening 101 therein. The first opening 101 exposes a portion of a sidewall surface of the substrate 100 .

[0033] The substrate 100 may be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0034] The first opening 101 provides a structural basis for the subsequent formation of a first barrier layer 103 and a second barrier layer 105 located on the surface of the first barrier layer 103 .

[0035] The size of the first opening 101 along a direction parallel to the surface of the substrate 100 ranges from 50 nm to 150 nm.

[0036] The depth range of the first opening 101 is:

[0037] A first barrier layer 103 and a second barrier layer 105 located on the surface of the first barrier layer 103 are formed in the first opening 101. Please refer to Figures 2 to 6 for details.

[0038] Referring to FIG. 2 , an initial first barrier layer 102 is formed in the first opening 101 .

[0039] The material of the initial first barrier layer 102 includes aluminum oxide.

[0040] The initial first barrier layer 102 is formed by a chemical vapor deposition method.

[0041] The thickness range of the initial first barrier layer 102 is:

[0042] The process parameters of the formation process of the initial first barrier layer 102 include: the time range of depositing the initial first barrier layer 102 is 25 minutes to 45 minutes, the gas pressure intensity of depositing the initial first barrier layer 102 is 1 torr to 2 torr, and the temperature range of depositing the initial first barrier layer 102 is 350°C to 450°C.

[0043] The initial first barrier layer 102 provides a structural basis for the subsequent formation of the first barrier layer 103 .

[0044] During the subsequent etching process for forming the second opening, the etching rate of the second barrier layer material has a first ratio to the etching rate of the first barrier layer material, with the first ratio ranging from 10:1 to 20:1. Therefore, the etching rate of the initial first barrier layer 102 is lower than the etching rate of the subsequently formed second barrier layer 105. Over the same period of time, the material loss of the second barrier layer 105 is greater than the material loss of the first barrier layer 103. This results in increased lateral and vertical loss of the subsequently formed composite barrier layer of the first and second barrier layers 103 and 105 compared to a barrier layer made of only the first barrier layer 103 during high-aspect-ratio etching. This increases the critical dimension of the bottom of the resulting second opening 109, thereby resolving the issue of incomplete etching of the second opening 109 and improving the morphology of the second opening 109.

[0045] Referring to FIG. 3 , the initial first barrier layer 102 is planarized until the surface of the initial first barrier layer 102 is flush with the substrate 100 .

[0046] The purpose of the planarization process is to make the thickness of the initial first barrier layer 102 uniform, thereby providing a structural basis for subsequent etching back.

[0047] Planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical-mechanical polishing. Specifically, in this embodiment, the planarization method is chemical-mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical-mechanical polishing, through the combined action of chemical and mechanical forces, avoids the surface damage caused by mechanical polishing alone and the shortcomings of chemical polishing alone, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical-mechanical polishing is widely used for high-planarization of various materials at the nanoscale.

[0048] Referring to FIG. 4 , the initial first barrier layer 102 is etched back to form a first barrier layer 103 .

[0049] The etching back method includes dry etching.

[0050] Specifically, in this embodiment, the material of the first barrier layer 103 includes aluminum oxide; the thickness range of the first barrier layer 103 is:

[0051] During the subsequent etching process for forming the second opening, the etching rate of the second barrier layer material is proportional to the etching rate of the first barrier layer material, with the first ratio ranging from 10:1 to 20:1. Therefore, the etching rate of the first barrier layer 103 during this etching process is lower than the etching rate of the subsequently formed second barrier layer 105. The loss of the second barrier layer 105 material is greater than the loss of the first barrier layer 103 material over the same period of time. This results in increased lateral and vertical loss of the composite barrier layer of the first and second barrier layers 103 and 105 compared to the barrier layer composed solely of the first barrier layer 103 during high-aspect-ratio etching. This increases the critical dimension of the bottom of the etched second opening 109, resolving the issue of incomplete etching of the second opening 109 and improving the morphology of the second opening 109.

[0052] Referring to FIG. 5 , an initial second barrier layer 104 is formed on the surface of the first barrier layer 103 .

[0053] The material of the initial second barrier layer 104 includes silicon oxide.

[0054] The initial second barrier layer 104 is formed by a method including HARP.

[0055] The thickness range of the initial second barrier layer 104 is:

[0056] The process parameters of the formation process of the initial second barrier layer 104 include: the time range for depositing the initial second barrier layer 104 is 25 minutes to 45 minutes, the gas pressure intensity for depositing the initial second barrier layer 104 is 600 torr, the temperature range for depositing the initial second barrier layer 104 is 500°C to 600°C, the gas for depositing the initial second barrier layer 104 includes tetraethoxysilane and ozone, the flow rate range of the tetraethoxysilane is: 1000sccm to 10000sccm, and the flow rate range of the ozone is: 50000sccm to 10000sccm.

[0057] The initial second barrier layer 104 provides a structural basis for the subsequent formation of the second barrier layer 105 .

[0058] During the subsequent etching process for forming the second opening, the etching rate of the second barrier layer material is proportional to the etching rate of the first barrier layer material, with the first ratio ranging from 10:1 to 20:1. Therefore, the etching rate of the first barrier layer 103 during the etching process is lower than the etching rate of the initial second barrier layer 104. The material loss of the initial second barrier layer 104 is greater than the material loss of the first barrier layer 103 over the same period of time. This results in increased lateral and vertical loss of the subsequently formed composite barrier layer of the first barrier layer 103 and the second barrier layer 105 compared to a barrier layer formed solely from the first barrier layer 103 during high-aspect-ratio etching. This increases the critical dimension of the bottom of the resulting second opening 109, thereby resolving the issue of incomplete etching of the second opening 109 and improving the morphology of the second opening 109.

[0059] 6 , the initial second barrier layer 104 is planarized until the surface of the substrate 100 is exposed, thereby forming a second barrier layer 105 .

[0060] Planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical-mechanical polishing. Specifically, in this embodiment, the planarization method is chemical-mechanical polishing. Unlike traditional purely mechanical or purely chemical polishing methods, chemical-mechanical polishing, through the combined action of chemical and mechanical forces, avoids the surface damage caused by mechanical polishing alone and the shortcomings of chemical polishing alone, such as slow polishing speed, poor surface flatness, and poor polishing consistency. Chemical-mechanical polishing is widely used for high-planarization of various materials at the nanoscale.

[0061] The purpose of the planarization process is to make the second barrier layer 105 uniform in thickness and located within the first opening 101 .

[0062] Specifically, in this embodiment, the material of the second barrier layer 105 includes silicon oxide; the thickness range of the second barrier layer 105 is:

[0063] Specifically, in this embodiment, the thickness ratio of the first barrier layer 103 to the second barrier layer 105 is in a range of 3:7 to 7:3.

[0064] In the subsequent etching process for forming the second opening, the etching rate of the second barrier layer material has a first ratio to the etching rate of the first barrier layer material, with the first ratio ranging from 10:1 to 20:1. Therefore, the etching rate of the second barrier layer 105 material in this etching process is greater than the etching rate of the first barrier layer 103 material. During the same period of time, the material loss of the second barrier layer 105 is greater than the material loss of the first barrier layer 103. This results in increased lateral and vertical loss of the composite barrier layer of the first and second barrier layers 103 and 105 compared to a barrier layer made of only the first barrier layer 103 during high-aspect-ratio etching. This increases the critical dimension of the bottom of the second opening 109 obtained by the subsequent etching, thereby resolving the issue of incomplete etching of the second opening 109 and improving the morphology of the second opening 109.

[0065] Referring to FIG. 7 , a dielectric layer structure 106 is formed on the surface of the substrate 100 .

[0066] Specifically, in this embodiment, the dielectric layer structure 106 includes a stack of a plurality of first dielectric layers 107 and a second dielectric layer 108 , and the first dielectric layers 107 and the second dielectric layers 108 are used to form a NAND flash memory.

[0067] In other embodiments, the dielectric layer structure can also be a single layer or multiple layers of other materials.

[0068] Specifically, in this embodiment, the thickness of the dielectric layer structure 106 ranges from 2 μm to 10 μm; the number of layers of the first dielectric layer 107 ranges from 1 to 3 layers; and the number of layers of the second dielectric layer 108 ranges from 1 to 3 layers.

[0069] The material of the first dielectric layer 107 includes silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon.

[0070] The material of the second dielectric layer 108 includes silicon oxide, silicon nitride, silicon oxynitride, and amorphous carbon.

[0071] The first dielectric layer 107 provides a structural foundation for the subsequent formation of a gate layer.

[0072] The second dielectric layer 108 provides a structural foundation for the subsequent formation of source and drain conductive layers.

[0073] Please refer to Figure 8. A second opening 109 is formed in the dielectric layer structure 106. The second opening 109 exposes the sidewall surface of the dielectric layer structure 106, the sidewall surface of the second barrier layer 105, and a portion of the surface of the first barrier layer 103. The etching process for forming the second opening 109 has a first ratio between the etching rate of the second barrier layer 103 material and the etching rate of the first barrier layer 103 material.

[0074] The first ratio ranges from 10:1 to 20:1.

[0075] The method for forming the second opening 109 includes: forming a hard mask layer (not shown) on the surface of the dielectric layer structure 106; etching the dielectric layer structure 106 using the hard mask layer as a mask to form the second opening 109, wherein the second opening 109 exposes the sidewall surface of the dielectric layer structure 106, the sidewall surface of the second barrier layer 105, and a portion of the surface of the first barrier layer 103.

[0076] The etching method includes wet etching and dry etching.

[0077] The etching process has a first ratio between the etching rate of the second barrier layer 103 material and the etching rate of the first barrier layer 103 material. The first ratio ranges from 10:1 to 20:1. The etching rate of the first barrier layer 103 material is lower than the etching rate of the second barrier layer 105 material. Over the same period of time, the loss of the second barrier layer 105 material is greater than the loss of the first barrier layer 103 material. This results in increased lateral and vertical loss of the composite barrier layer of the first and second barrier layers 103 and 105 material compared to a barrier layer made of only the first barrier layer 103 material during high aspect ratio etching. This increases the critical bottom dimension of the etched second opening 109, thereby resolving the issue of incomplete etching of the second opening 109 and improving the morphology of the second opening 109.

[0078] After forming the second opening 109, the process further includes: forming a channel (not shown) in the second opening 109; after forming the channel, removing the first dielectric layer 107, and forming a gate layer (not shown) between adjacent second dielectric layers 108; after forming the gate layer, removing the second dielectric layer 108, and performing source-drain doping on the channel exposed by the adjacent gate layer; and after performing source-drain doping, forming a source-drain conductive layer (not shown) between adjacent gate layers.

[0079] Correspondingly, an embodiment of the present invention also proposes a semiconductor structure, please continue to refer to Figure 8, including: a substrate 100, having a first opening 101 (as shown in Figure 1), the first opening 101 exposing a portion of the sidewall surface of the substrate 100; a first barrier layer 103 located in the first opening 101 and a second barrier layer 105 located on the surface of the first barrier layer 103, the material of the second barrier layer 105 is different from that of the first barrier layer 103; a device layer 106 located on the surface of the substrate 100, the device layer having a second opening 109, the second opening 109 exposing the sidewall surface of the device layer 106, the sidewall surface of the second barrier layer 105 and a portion of the surface of the first barrier layer 103.

[0080] The semiconductor structure includes a substrate 100 having a first opening 101 , wherein the first opening 101 exposes a portion of a sidewall surface of the substrate 100 .

[0081] The substrate 100 may be made of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0082] The size of the first opening 101 along a direction parallel to the surface of the substrate 100 ranges from 50 nm to 150 nm.

[0083] The depth range of the first opening 101 is:

[0084] The semiconductor structure includes a first barrier layer 103 located in the first opening 101 and a second barrier layer 105 located on a surface of the first barrier layer 103 . The material of the second barrier layer 105 is different from that of the first barrier layer 103 .

[0085] The material of the first barrier layer 103 includes aluminum oxide; the thickness of the first barrier layer 103 is in the range of:

[0086] The material of the second barrier layer 105 includes silicon oxide; the thickness of the second barrier layer 105 is in the range of:

[0087] The thickness ratio of the first barrier layer 103 to the second barrier layer 105 is in a range of 3:7 to 7:3.

[0088] The semiconductor structure includes a device layer 106 located on the surface of the substrate 100 , with a second opening 109 therein. The second opening 109 exposes the sidewall surface of the device layer 106 , the sidewall surface of the second barrier layer 105 , and a portion of the surface of the first barrier layer 103 .

[0089] The thickness of the device layer 106 ranges from 2 μm to 10 μm.

[0090] The semiconductor structure includes a channel (not shown) located in the second opening 109 .

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate having a first opening, wherein the first opening exposes a portion of a sidewall surface of the substrate; a first barrier layer located in the first opening and a second barrier layer located on a surface of the first barrier layer, wherein the material of the second barrier layer is different from that of the first barrier layer; A device layer is located on the surface of the substrate, and a second opening is formed in the device layer. The second opening exposes the sidewall surface of the device layer, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer.

2. The semiconductor structure according to claim 1, wherein The first barrier layer material includes aluminum oxide; the thickness of the first barrier layer ranges from:

3. The semiconductor structure according to claim 1, wherein: The second barrier layer material includes silicon oxide; the thickness range of the second barrier layer is:

4. The semiconductor structure according to claim 1, wherein: The thickness ratio of the first barrier layer to the second barrier layer is in a range of 3:7 to 7:

3.

5. The semiconductor structure according to claim 1, wherein Also includes: A channel is located within the second opening.

6. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a first opening therein, wherein the first opening exposes a portion of a sidewall surface of the substrate; forming a first barrier layer in the first opening and a second barrier layer located on a surface of the first barrier layer; forming a dielectric layer structure on the surface of the substrate; A second opening is formed in the dielectric layer structure, wherein the second opening exposes the sidewall surface of the dielectric layer structure, the sidewall surface of the second barrier layer, and a portion of the surface of the first barrier layer. The etching process for forming the second opening etches the second barrier layer material. The rate has a first ratio to an etch rate of the first barrier layer material.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the first barrier layer includes: forming an initial first barrier layer in the first opening; flattening the initial first barrier layer until the surface of the initial first barrier layer is flush with the substrate; and etching back the initial first barrier layer to form a first barrier layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the second barrier layer includes: forming an initial second barrier layer on the surface of the first barrier layer; and performing a planarization process on the initial second barrier layer until the substrate surface is exposed to form a second barrier layer.

9. The method for forming a semiconductor structure according to claim 7, wherein: The etching back method includes dry etching.

10. The method for forming a semiconductor structure according to claim 6, wherein: The thickness ratio of the first barrier layer to the second barrier layer is in a range of 3:7 to 7:

3.

11. The method for forming a semiconductor structure according to claim 6, wherein: The material of the first barrier layer includes aluminum oxide; the thickness range of the first barrier layer is: The formation process of the first barrier layer includes: physical vapor deposition and chemical vapor deposition; the process parameters of the formation process of the first barrier layer include: the time range for depositing the first barrier layer is 25 minutes to 45 minutes, the gas pressure intensity for depositing the first barrier layer is 1 torr to 2 torr, and the temperature range for depositing the first barrier layer is 350°C to 450°C.

12. The method for forming a semiconductor structure according to claim 6, wherein: The material of the second barrier layer includes silicon oxide; the thickness range of the second barrier layer is: The formation process of the second barrier layer includes HARP; The process parameters of the formation process of the second barrier layer include: the time range for depositing the second barrier layer is 25 minutes to 45 minutes, the gas pressure intensity for depositing the second barrier layer is 600 torr, the temperature range for depositing the second barrier layer is 500°C to 600°C, and the gas for depositing the second barrier layer includes tetraethoxysilane and ozone, the flow rate range of the tetraethoxysilane is: 1000sccm to 10000sccm, and the flow rate range of the ozone is: 50000sccm to 10000sccm.

13. The method for forming a semiconductor structure according to claim 6, wherein: The first ratio ranges from 10:1 to 20:

1.

14. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the second opening includes: forming a hard mask layer on the surface of the dielectric layer structure; etching the dielectric layer structure using the hard mask layer as a mask to form a second opening, wherein the second opening exposes the side wall surface of the dielectric layer structure, the side wall surface of the second barrier layer, and a portion of the surface of the first barrier layer.

15. The method for forming a semiconductor structure according to claim 6, wherein: The dielectric layer structure includes: a stack of several first dielectric layers and second dielectric layers; the number of layers of the first dielectric layer ranges from 1 to 3 layers; the number of layers of the second dielectric layer ranges from 1 to 3 layers; the materials of the first dielectric layer include: silicon oxide, silicon nitride, silicon oxynitride and amorphous carbon; the materials of the second dielectric layer include: silicon oxide, silicon nitride, silicon oxynitride and amorphous carbon.

16. The method for forming a semiconductor structure according to claim 15, wherein: After forming the second opening, the method further includes: forming a channel in the second opening; after forming the channel, removing the first dielectric layer and forming a gate layer between adjacent second dielectric layers; after forming the gate layer, removing the second dielectric layer and performing source-drain doping on the channel exposed by the adjacent gate layer; and after performing source-drain doping, forming a source-drain conductive layer between adjacent gate layers.

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