Chip and preparation method therefor, and memory and electronic device

Abstract

The present application relates to the field of semiconductors. Provided are a chip and a preparation method therefor, and a memory and an electronic device, which can prevent the situation where the size of a vertical transistor cannot be scaled down due to process limitations. The chip comprises a vertical transistor. The vertical transistor comprises: a first electrode, a channel and a second electrode, which are sequentially stacked on a substrate, wherein the channel comprises a trench; a first gate dielectric layer and a second gate dielectric layer, which are both in contact with a side wall of the trench, wherein the first gate dielectric layer and the second gate dielectric layer are both located in the trench, or the first gate dielectric layer and the second gate dielectric layer are both located outside the trench; and a first gate electrode and a second gate electrode, which are spaced apart, wherein the first gate electrode is arranged on the side of the first gate dielectric layer that faces away from the channel, and the second gate electrode is arranged on the side of the second gate dielectric layer that faces away from the channel.

Description

Chip and preparation method thereof, memory, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 4, 2024, with application number 202410161330.2 and application name “CHIP AND ITS MANUFACTURING METHOD, MEMORY, AND ELECTRONIC DEVICE”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductors, and in particular to a chip and a method for manufacturing the same, a memory, and an electronic device. Background Art

[0003] Memory is widely used in electronic devices. With the advancement of chip technology, memory size, like processors, continues to shrink, improving density and storage performance. Memory consists of multiple memory cells, each of which includes a transistor and a capacitor.

[0004] Existing technologies can realize high-density memory cells by utilizing vertical transistors and integrating vertical transistors and capacitor structures in the vertical direction, which is expected to achieve further miniaturization of memory.

[0005] However, the current mainstream vertical transistor structure is a gate-all-around structure, which requires a first through-hole to be opened in the gate, a gate dielectric layer to be deposited within the first through-hole, a second through-hole to be opened at the bottom of the gate dielectric layer, and a channel to be formed in the second through-hole to ensure contact between the channel and the bottom electrode. In other words, in a plane perpendicular to the vertical direction, the size of the vertical transistor is affected by the dimensions of the gate, gate dielectric layer, and channel, resulting in a large area occupied by a single transistor, which is not conducive to the scaling of vertical transistors.

[0006] Summary of the Invention

[0007] In order to solve the above technical problems, the present application provides a chip and its preparation method, a memory, and an electronic device, which can avoid the inability to miniaturize the size of vertical transistors due to process limitations.

[0008] In a first aspect, the present application provides a chip comprising a vertical transistor, the vertical transistor comprising: a first electrode, a channel, and a second electrode sequentially stacked on a substrate, the channel comprising a trench; a first gate dielectric layer and a second gate dielectric layer, both of which are in contact with the sidewalls of the trench; both of which are located in the trench, or both of which are located outside the trench; and a first gate and a second gate arranged at intervals, the first gate being located on the side of the first gate dielectric layer facing away from the channel, and the second gate being located on the side of the second gate dielectric layer facing away from the channel.

[0009] In the present application, by spacing the first gate and the second gate, the first gate and the second gate can be located at different positions in the channel. Therefore, compared with the solution in which the vertical transistor only includes a first gate that is not a ring gate or only includes a second gate that is not a ring gate, the first gate and the second gate can gate the channel at different positions, thereby reducing leakage of the channel.

[0010] Moreover, on the one hand, because the first gate and the second gate of the present application are no longer in a surrounding shape, and the first gate dielectric layer and the second gate dielectric layer are no longer in a surrounding shape, the present application no longer uses the process of the related art to first form the first through hole in the surrounding gate and then form the second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the area where the channel is to be formed, grooves are cut between adjacent sacrificial structures, and then the first gate dielectric layer and the second gate dielectric layer, as well as the first gate and the second gate, are formed on the sidewalls of the sacrificial structure. Afterwards, by removing the sacrificial structure and forming a channel at the location of the sacrificial structure, the channel can be brought into contact with the first electrode. That is, the present application does not need to form a second through hole between the first gate dielectric layer and the second gate dielectric layer, thereby avoiding the process limitations of forming the second through hole, which prevents the size of the vertical transistor from being miniaturized.

[0011] On the other hand, since the first gate and the second gate are spaced apart rather than surrounding the channel, the total area of ​​the first gate and the second gate is smaller than the total area of ​​the gate in the ring gate solution, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, thereby achieving miniaturization of the vertical transistor; at the same time, the first gate dielectric layer and the second gate dielectric layer used to isolate the channel from the first gate and the second gate can also be spaced apart rather than surrounding the channel. Therefore, the total area of ​​the first gate dielectric layer and the second gate dielectric layer of the present application is smaller than the total area of ​​the gate dielectric layer in the ring gate solution, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, thereby achieving miniaturization of the vertical transistor. The Y direction can be the direction from the first gate to the second gate, and the Z direction can be the direction from the first electrode to the second electrode.

[0012] On this basis, due to process limitations, the process of opening a hole at the bottom of the gate dielectric layer generally requires reserving a certain etching area (for example, reserving a space of approximately 20nm in the X and Y directions). Given a certain size of the second through-hole, the embodiment of the present application can reduce the thickness of the channel in the X and Y directions by opening a trench in the channel, thereby improving the gate control capability of the vertical transistor.

[0013] In some possible implementations, the first gate dielectric layer and the second gate dielectric layer are both located outside the trench, the first gate is located on a side of the first gate dielectric layer away from the channel, and the second gate is located on a side of the second gate dielectric layer away from the channel.

[0014] In some possible implementations, the chip further includes a first insulating layer that fills the trench, thereby separating the first electrode from the second electrode. Alternatively, the trench further includes a bottom adjacent to the sidewalls, the bottom contacting the first electrode, and the second electrode filling the trench.

[0015] Those skilled in the art will understand that the region of the channel that overlaps with the first and second gates and is located between the first and second electrodes is called the channel region. When the second electrode is filled in the trench, the size of the channel region in the Z direction will be smaller than when the first insulating layer is filled in the trench. Therefore, to ensure gate control capability and avoid the channel region being too small in the Z direction, the overlap between the second electrode and the first and second gates in the Z direction cannot be too large. For example, in this application, the overlap between the second electrode and the first and second gates in the Z direction does not exceed 30 nm.

[0016] In some possible implementations, the first gate dielectric layer and the second gate dielectric layer are both located in the trench, and the chip further includes a first insulating layer that fills the trench. The first gate is disposed between the first gate dielectric layer and the first insulating layer, and the second gate is disposed between the second gate dielectric layer and the first insulating layer.

[0017] In some possible implementations, there are multiple vertical transistors, multiple vertical transistors arranged along the column direction share the same first electrode, and multiple vertical transistors arranged along the row direction share the same first gate and the same second gate.

[0018] In some possible implementations, when the first gate dielectric layer and the second gate dielectric layer are both located in the trenches, channels of adjacent vertical transistors arranged along the column direction are connected.

[0019] In some possible implementations, the first gate and the second gate are arranged opposite to each other.

[0020] In some possible implementations, when both the first gate dielectric layer and the second gate dielectric layer are located outside the trench, the longitudinal cross-section of the trench is U-shaped, or the cross-section of the trench is a closed circle. The longitudinal cross-section of the trench is the interface of the trench along a plane containing a first direction and a second direction, where the first direction is the direction from the first electrode to the second electrode, and the second direction is the direction from the first gate to the second gate. The cross-section of the trench is the cross-section of the trench along the second direction.

[0021] In a second aspect, the present application provides a chip comprising a vertical transistor, the vertical transistor comprising: a first electrode, a channel, and a second electrode stacked sequentially on a substrate; the second electrode comprising a first sub-electrode and a second sub-electrode arranged opposite each other, the channel comprising a first channel located between the first electrode and the first sub-electrode, and a second channel located between the first electrode and the second sub-electrode; a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the sidewalls of the first channel, and the second gate dielectric layer contacting the sidewalls of the second channel; a first gate and a second gate arranged opposite each other, the first gate being arranged on the side of the first gate dielectric layer facing away from the first channel, and the second gate being arranged on the side of the second gate dielectric layer facing away from the second channel.

[0022] Compared to related technologies, the present invention can split a vertical transistor into a first vertical transistor and a second vertical transistor, thereby improving integration density. Compared to the dual-gate vertical transistor provided in the previous embodiment, the spacing between the center of the first vertical transistor and the center of the second vertical transistor in the direction from the first vertical transistor to the second vertical transistor can be less than 30nm. In other words, the pitch between the first vertical transistor and the second vertical transistor can be less than 30nm. When applied to DRAM, it can achieve a smaller unit area than advanced processes 1beta and 1gamma.

[0023] Moreover, on the one hand, because the first gate and the second gate of the present application are no longer in a surrounding shape, and the first gate dielectric layer and the second gate dielectric layer are no longer in a surrounding shape, the present application no longer uses the process of the related art to first form the first through hole in the surrounding gate and then form the second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the area where the channel is to be formed, grooves are cut between adjacent sacrificial structures, and then the first gate dielectric layer and the second gate dielectric layer, as well as the first gate and the second gate, are formed on the sidewalls of the sacrificial structure. Afterwards, by removing the sacrificial structure and forming a channel at the location of the sacrificial structure, the channel can be brought into contact with the first electrode. That is, the present application does not need to form a second through hole between the first gate dielectric layer and the second gate dielectric layer, thereby avoiding the process limitations of forming the second through hole, which prevents the size of the vertical transistor from being miniaturized.

[0024] On the other hand, the first gate and the second gate are arranged relative to each other, rather than being arranged around the channel as in the related art. Therefore, the sizes of the first vertical transistor and the second vertical transistor in the X direction and the Y direction can be reduced, so that the first vertical transistor and the second vertical transistor can be miniaturized; at the same time, the first gate dielectric layer and the second gate dielectric layer can also be arranged relative to each other, rather than surrounding the channel. Therefore, the total area of ​​the first gate dielectric layer and the second gate dielectric layer of the present application is smaller than the total area of ​​the gate dielectric layer in the ring gate scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, so that the vertical transistor can be miniaturized.

[0025] In some possible implementations, the first channel and the second channel form a trench, and the chip further includes a first insulating layer, which is filled in the trench.

[0026] In some possible implementations, the first gate dielectric layer and the second gate dielectric layer are both located outside the trench, the first gate is arranged on the side of the first gate dielectric layer facing away from the first channel, and the second gate is arranged on the side of the second gate dielectric layer facing away from the second channel; or, the first gate dielectric layer and the second gate dielectric layer are both located in the trench, the first gate is arranged between the first gate dielectric layer and the first insulating layer, and the second gate is arranged between the second gate dielectric layer and the second insulating layer.

[0027] In some possible implementations, the first channel is disconnected from the second channel.

[0028] In a third aspect, the present application provides a memory comprising a memory array, the memory array comprising the chip described in the first aspect or the second aspect, and further comprising a capacitor electrically connected to the vertical transistor in the chip.

[0029] In some possible implementations, the memory array includes the chip described in the first aspect, and the memory array also includes word lines and bit lines; the gate of the vertical transistor is electrically connected to the word line, the first electrode is electrically connected to the bit line, and the second electrode is electrically connected to the capacitor; or, the memory array includes the chip described in the second aspect, and the memory array also includes a write word line, a read word line, and a bit line; the second gate is electrically connected to the write word line, the second sub-electrode is electrically connected to the first gate, the first sub-electrode is electrically connected to the read word line, and the first electrode is electrically connected to the bit line.

[0030] The third aspect and any implementation of the third aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can be referred to the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and will not be repeated here.

[0031] In a fourth aspect, the present application provides an electronic device comprising a circuit board and the chip described in the first aspect or the chip described in the second aspect or the memory described in the third aspect, wherein the chip or the memory is arranged on the circuit board.

[0032] The fourth aspect and any implementation of the fourth aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can be found in the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and are not further described here.

[0033] In a fifth aspect, the present application provides a chip fabrication method, comprising: forming a first electrode, a first sacrificial layer, a second insulating layer, and a third insulating layer on a substrate; the first sacrificial layer covering the surface of the first electrode facing away from the substrate; the second insulating layer being located between adjacent first electrodes and between adjacent first sacrificial layers in a third direction; and the third insulating layer being located between adjacent first electrodes and covering the sidewalls of the first electrode in a second direction. A first gate dielectric layer, a second gate dielectric layer, a first gate, and a second gate are formed on the side of the third insulating layer facing away from the substrate; the first gate dielectric layer being located between the first gate and the second insulating layer, the second gate dielectric layer being located between the second gate and the second insulating layer, and the first gate and the second gate being spaced apart. The first sacrificial layer is removed to form a recess to expose the surface of the first electrode facing away from the substrate, and a channel and the first insulating layer are sequentially filled in the recess. A second electrode is formed on the side of the channel and the first insulating layer facing away from the substrate; wherein the second direction is perpendicular to the third direction, and both the second and third directions are perpendicular to the first direction from the first electrode to the second electrode.

[0034] In this application, a first sacrificial layer and a second insulating layer are first formed. Etchback is then used to create grooves between adjacent first sacrificial layers and adjacent second insulating layers. Then, first and second gate dielectric layers, as well as first and second gate electrodes, are formed on the sidewalls of the first and second sacrificial layers. Subsequently, the first sacrificial layer is removed and a channel is formed in the location of the first sacrificial layer, thereby enabling contact between the channel and the first electrode. This eliminates the need for forming a second via between the first and second gate dielectric layers, thereby avoiding the limitations of the process for forming the second via that prevents the vertical transistor from being miniaturized.

[0035] In some possible implementations, the second electrode includes a first sub-electrode and a second sub-electrode disposed opposite each other, and the channel includes a first channel and a second channel. The first channel is located between the first electrode and the first sub-electrode, and the second channel is located between the first electrode and the second sub-electrode.

[0036] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can be found in the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and are not further described here.

[0037] In a sixth aspect, the present application provides a chip fabrication method, comprising: forming a third sacrificial layer, a fifth insulating layer, and a first electrode on a substrate; the third sacrificial layer having a hollow portion extending through the third sacrificial layer; filling the hollow portion with the first electrode and the fifth insulating layer, wherein the vertical distance from the surface of the fifth insulating layer facing away from the substrate to the substrate is greater than the vertical distance from the surfaces of the three sacrificial layers facing away from the substrate to the substrate; forming a first gate dielectric layer, a second gate dielectric layer, a first gate, and a second gate; the first gate dielectric layer being positioned between the first gate and the fifth insulating layer, the second gate dielectric layer being positioned between the second gate and the fifth insulating layer, and the first gate being spaced apart from the second gate. Removing the fifth insulating layer, and forming a channel in the hollow portion, the channel comprising a first channel and a second channel. Forming a second electrode on the side of the channel facing away from the substrate, the second electrode comprising a first sub-electrode and a second sub-electrode disposed opposite each other; the first channel being positioned between the first electrode and the first sub-electrode, and the second channel being positioned between the first electrode and the second sub-electrode.

[0038] In this application, the channel is brought into contact with the first electrode by forming a fifth insulating layer in the region where the channel is to be formed, then forming first and second gate dielectric layers, as well as first and second gate electrodes, on the sidewalls of the fifth insulating layer. The fifth insulating layer is then removed, and a channel is formed in the location of the fifth insulating layer. In other words, this application eliminates the need to form a second via between the first and second gate dielectric layers, thereby avoiding the limitations of the process for forming the second via that would prevent the vertical transistor from being miniaturized.

[0039] In some possible implementations, the first channel and the second channel form a trench. Before forming the second electrode on the side of the channel facing away from the substrate, the preparation method further includes: filling the trench with a first insulating layer.

[0040] In some possible implementations, forming a third sacrificial layer, a fifth insulating layer, and a first electrode on a substrate includes: forming a third sacrificial layer and a fourth insulating layer on the substrate, with a hollow portion extending through the third sacrificial layer and the fourth insulating layer; sequentially filling the hollow portion with the first electrode and the fifth insulating layer; and removing the fourth insulating layer.

[0041] The sixth aspect and any implementation of the sixth aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the sixth aspect and any implementation of the sixth aspect can be found in the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and are not further described here.

[0042] In a seventh aspect, the present application provides a chip fabrication method, comprising: forming a first electrode and a fourth sacrificial layer on a substrate; the fourth sacrificial layer being located on a side of the first electrode facing away from the substrate; forming a first gate and a second gate on either side of the adjacent fourth sacrificial layer; forming a first gate dielectric layer, a second gate dielectric layer, a channel, and a second electrode; the channel being located on a side of the first gate dielectric layer facing away from the first gate and a side of the second gate dielectric layer facing away from the second gate; and the second electrode being located on a side of the channel facing away from the substrate.

[0043] In this application, the channel is brought into contact with the first electrode by forming a fourth sacrificial layer in the region where the channel is to be formed, then forming a first gate dielectric layer and a second gate dielectric layer, as well as a first gate and a second gate electrode, on the sidewalls of the fourth sacrificial layer. The fourth sacrificial layer is then removed, and a channel is formed in the location of the fourth sacrificial layer. In other words, this application eliminates the need to form a second via between the first and second gate dielectric layers, thereby avoiding the limitations of the process for forming the second via that would prevent the vertical transistor from being miniaturized.

[0044] In some possible implementations, forming the first gate dielectric layer, the second gate dielectric layer, and the channel includes: sequentially forming a gate dielectric layer and a dummy channel on the first gate and the second gate. Etching back the dummy channel, leaving the dummy channel covering the sidewalls of the gate dielectric layer. Under the protection of the dummy channel, removing the portion of the gate dielectric layer not covered by the dummy channel to obtain the first gate dielectric layer and the second gate dielectric layer. Removing the dummy channel, and forming a channel on the side of the first gate dielectric layer facing away from the first gate and on the side of the second gate dielectric layer and the second gate.

[0045] The seventh aspect and any implementation of the seventh aspect correspond to the first aspect, the second aspect, and any implementation of the first and second aspects, respectively. The technical effects corresponding to the seventh aspect and any implementation of the seventh aspect can be found in the technical effects corresponding to the first aspect, the second aspect, and any implementation of the first and second aspects, and are not further described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a top view of a memory array provided in the related art;

[0047] Figures 2a-2d are structural diagrams of a vertical transistor provided in an embodiment of the present application;

[0048] FIG2e is a top view of a vertical transistor provided in an embodiment of the present application;

[0049] FIG2f is a schematic structural diagram of a channel provided in an embodiment of the present application;

[0050] 3a-3b are structural diagrams of a vertical transistor provided in an embodiment of the present application;

[0051] FIG4 a is a structural diagram of a vertical transistor provided in an embodiment of the present application;

[0052] FIG4 b is a schematic structural diagram of a channel provided in an embodiment of the present application;

[0053] FIG5a is a schematic structural diagram of a channel provided in an embodiment of the present application;

[0054] 5b-5c are structural diagrams of a vertical transistor provided in an embodiment of the present application;

[0055] FIG6 is a structural diagram of a vertical transistor provided in an embodiment of the present application;

[0056] 7a-7e are structural diagrams of a vertical transistor provided in an embodiment of the present application;

[0057] 8a-8c are structural diagrams of a vertical transistor provided in an embodiment of the present application;

[0058] 8d-8e are top views of a vertical transistor provided in an embodiment of the present application;

[0059] 9a-9b are structural diagrams of a vertical transistor provided in an embodiment of the present application;

[0060] Figures 10a-10d are structural diagrams of a storage unit provided in an embodiment of the present application;

[0061] FIG10e is a circuit diagram of the memory cell shown in FIG10d;

[0062] FIG11a is a top view of a storage unit provided in an embodiment of the present application;

[0063] FIG11b is a circuit diagram of the memory cell shown in FIG11a;

[0064] FIG12 is a flow chart of the preparation of a chip provided in an embodiment of the present application;

[0065] Figures 13a to 13f are three views of the chip during the preparation process provided in an embodiment of the present application;

[0066] Figures 14a to 14f are three views of the chip during the preparation process provided in an embodiment of the present application;

[0067] Figures 15a to 15g are three views of the chip during the preparation process provided in an embodiment of the present application;

[0068] FIG16 is a flow chart of the preparation of a chip provided in an embodiment of the present application;

[0069] Figures 17a to 17k are three views of the chip during the preparation process provided in an embodiment of the present application;

[0070] FIG18 is a flow chart of the preparation of a chip provided in an embodiment of the present application;

[0071] Figures 19a-19j are three views of the chip during the preparation process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0073] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0074] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0075] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0076] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0077] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a memory.

[0078] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0079] For ease of explanation, the following uses a mobile phone as an example. The mobile phone may include a processor, which includes logic circuits and memory. The memory includes a storage array, a storage controller, and a decoder. The logic circuit can read and write data to the storage array through the storage controller and decoder.

[0080] Take dynamic random access memory (DRAM) as an example. DRAM is widely used in electronic devices. Due to the capacitor structure used in traditional DRAM, DRAM scaling is slower than that of processors, resulting in a performance gap and making it increasingly difficult to improve the overall storage and computing performance of electronic devices.

[0081] Existing technologies utilize vertical transistors and integrate them with capacitor structures in a vertical direction to achieve high-density memory cells, which is expected to further miniaturize memory. In addition, vertical transistors can also be applied to devices other than memory, which is not limited in the present embodiment.

[0082] However, as shown in Figure 1, the current mainstream vertical transistor structure is a wrap-around gate structure, which requires a first through-hole to be opened in the gate, a gate dielectric layer to be deposited in the first through-hole, and then a second through-hole to be opened at the bottom of the gate dielectric layer. A channel is formed in the second through-hole and an etching area is reserved. On the one hand, in a plane perpendicular to the vertical direction (Z direction) (the plane where the XY direction is located), the size of the vertical transistor is affected by the size of the gate, the gate dielectric layer, the channel, and the reserved etching area, resulting in a large area occupied by a transistor, which is not conducive to the miniaturization of the vertical transistor. On the other hand, after the gate dielectric layer is drilled to obtain the second through-hole, the channel filled in the second through-hole can contact the bottom electrode. However, due to process limitations, the size of the second through-hole is large, which limits the miniaturization of the vertical transistor.

[0083] For example, the total thickness of the gate in the X direction is approximately 10 nm, the total thickness of the gate dielectric layer in the X direction is approximately 10 nm, the diameter of the channel in the second through hole and the reserved etching area is 30 nm, and the spacing between adjacent transistors in the X direction is approximately 15 nm. In this way, the size occupied by a transistor in the X direction is approximately 65 nm. Based on this, an embodiment of the present application provides a chip, which includes a vertical transistor, and the gate of the transistor includes a first gate and a second gate arranged opposite to each other. By reducing the area occupied by the gate, the miniaturization of the vertical transistor is achieved.

[0084] Specifically, as shown in Figures 2a-2d, the vertical transistor includes a first electrode 11, a channel 12, and a second electrode 13, which are sequentially stacked on a substrate 10. Channel 12 includes a trench. The first electrode 11 is a source electrode, and the second electrode 13 is a drain electrode; alternatively, the first electrode 11 is a drain electrode, and the second electrode 13 is a source electrode. In this application, the direction from the first electrode 11 to the second electrode 13 may be the Z direction. Herein, the Z direction is the first direction, the Y direction is the second direction, and the X direction is the third direction. The following descriptions will refer to the Z direction, the Y direction, and the X direction.

[0085] The vertical transistor further includes a first gate dielectric layer 14, a second gate dielectric layer 15, a first gate electrode 16, and a second gate electrode 17. The first gate dielectric layer 14 and the second gate dielectric layer 15 are both in contact with the sidewalls of the trench. The first gate electrode 16 is disposed on the side of the first gate dielectric layer 14 facing away from the channel 12, and the second gate electrode 17 is disposed on the side of the second gate dielectric layer 15 facing away from the channel 12. Furthermore, the first gate electrode 16 and the second gate electrode 17 are spaced apart. Thus, the first gate dielectric layer 14, which isolates the first gate electrode 16 from the channel 12, and the second gate dielectric layer 15, which isolates the second gate electrode 17 from the channel 12, can also be spaced apart.

[0086] Figure 2a shows 2*2 vertical transistors, the first electrode 11 can extend along the Y direction, and the two vertical transistors arranged along the Y direction can share the first electrode 11; the first gate dielectric layer 14, the first gate electrode 16, the second gate dielectric layer 15, and the second gate electrode 17 can extend along the X direction, and the two vertical transistors arranged along the X direction can share the first gate dielectric layer 14, the first gate electrode 16, the second gate dielectric layer 15, and the second gate electrode 17.

[0087] Of course, as shown in Figure 2d, the vertical transistor may also include an independent first electrode 11, a first gate dielectric layer 14, a first gate electrode 16, a second gate dielectric layer 15, a second gate electrode 17, and a second electrode 13. That is, whether the multiple transistors are arranged along the X direction or along the Y direction, they do not share the first electrode 11, the first gate dielectric layer 14, the first gate electrode 16, the second gate dielectric layer 15, the second gate electrode 17, and the second electrode 13.

[0088] In some possible implementations, the embodiments of the present application do not limit the relative positions of the first gate 16 and the second gate 17, as long as the first gate 16 and the second gate 17 are spaced apart. Optionally, the first gate 16 and the second gate 17 can be arranged relative to each other. For the convenience of description, the following description is based on the example of the relative arrangement of the first gate 16 and the second gate 17, unless otherwise specified. In addition, those skilled in the art should know that in a vertical transistor, the first gate 16 and the second gate 17 can be electrically connected to jointly control the conduction or shutdown of the vertical transistor, that is, the vertical transistor in the embodiment of the present application is a dual-gate vertical transistor.

[0089] In the present application, by spacing the first gate 16 and the second gate 17, the first gate 16 and the second gate 17 can be located at different positions of the channel 12. Therefore, compared with the solution in which the vertical transistor only includes the non-ring gate first gate 16 or only includes the non-ring gate second gate 17, the first gate 16 and the second gate 17 can gate the channel 12 at different positions, thereby reducing leakage of the channel 12.

[0090] Furthermore, on the one hand, because the first gate 16 and the second gate 17 of the present application are no longer in a surrounding shape, and the first gate dielectric layer 14 and the second gate dielectric layer 15 are no longer in a surrounding shape, the present application no longer uses the related art process of first forming a first through hole in the surrounding gate and then forming a second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the area where the channel 12 is to be formed, grooves are cut between adjacent sacrificial structures, and then the first gate dielectric layer 14 and the second gate dielectric layer 15, as well as the first gate 16 and the second gate 17, are formed on the sidewalls of the sacrificial structure. Thereafter, by removing the sacrificial structure and forming the channel 12 at the location of the sacrificial structure, the channel 12 can be brought into contact with the first electrode 11. That is, the present application does not need to form a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 15, thereby avoiding the process limitations of forming the second through hole that prevent the size of the vertical transistor from being miniaturized.

[0091] On the other hand, since the first gate 16 and the second gate 17 are arranged at intervals instead of surrounding the channel 12, the total area of ​​the first gate 16 and the second gate 17 is smaller than the total area of ​​the gate in the ring gate scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, so that the vertical transistor can be miniaturized; at the same time, the first gate dielectric layer 14 and the second gate dielectric layer 15 used to isolate the channel 12 from the first gate 16 and the second gate 17 can also be arranged at intervals instead of surrounding the channel 12. Therefore, the total area of ​​the first gate dielectric layer 14 and the second gate dielectric layer 15 of the present application is smaller than the total area of ​​the gate dielectric layer in the ring gate scheme, thereby reducing the size of the vertical transistor in the X direction and / or the Y direction, so that the vertical transistor can be miniaturized.

[0092] On this basis, due to process limitations, the process of opening a hole at the bottom of the gate dielectric layer generally requires reserving a certain etching area (for example, reserving a space of approximately 20nm in the X and Y directions). Given a certain size of the second through hole, the embodiment of the present application can reduce the thickness of the channel 12 in the X and Y directions by opening a trench in the channel, thereby improving the gate control capability of the vertical transistor.

[0093] In some possible implementations, the groove may include sidewalls but not a bottom; or, in addition to the sidewalls, the groove may also include a bottom adjacent to the sidewalls. Of course, in other possible implementations, the channel 12 may not include a groove but may be a solid, integral structure, or the channel 12 may be a hollow structure.

[0094] On this basis, the longitudinal cross-section of the trench is U-shaped (Figures 4a and 4b), or the cross-section of the trench is a closed circle (Figures 2a and 2f). In the case where the cross-section of the trench is a closed circle, the cross-section of the trench can be, for example, a "mouth" shape (Figure 2f), a circle, an ellipse, or other closed shapes. The longitudinal cross-section of the trench is a cross-section of the trench along the Z direction, and the cross-section of the trench is a cross-section of the trench along the direction from the first gate 16 to the second gate 17.

[0095] As shown in FIG2c , when the trench includes a bottom adjacent to the sidewalls, the second electrode 13 can be filled in the trench. Because the trench of channel 12 includes a bottom, the second electrode 13 does not directly contact the first electrode 11. Alternatively, as shown in FIG2b , regardless of whether the trench includes a bottom, the chip can further include a first insulating layer 21, which can be filled in the trench to separate the first electrode 11 from the second electrode 13.

[0096] Those skilled in the art will appreciate that the region of the channel 12 that overlaps with the first gate 16 and the second gate 17 and is located between the first electrode 11 and the second electrode 13 is referred to as the channel region. When the second electrode 13 is filled in the trench, the dimension of the channel region in the Z direction will be smaller than when the trench is filled with the first insulating layer 21. Therefore, to ensure gate control capability and prevent the dimension of the channel region in the Z direction from being too small, the overlap dimension of the second electrode 13 with the first gate 16 and the second gate 17 in the Z direction cannot be too large. For example, in the present application, the overlap dimension of the second electrode 13 with the first gate 16 and the second gate 17 in the Z direction does not exceed 30 nm.

[0097] In some possible implementations, the surface of the trench sidewall facing the first pole 11 is assumed to be the first surface, and the surface of the trench sidewall facing the second pole 13 is assumed to be the second surface. Outside the trench, the surface adjacent to the first surface and the second surface is the outer sidewall of the trench; inside the trench, the surface adjacent to the first surface and the second surface is the inner sidewall of the trench.

[0098] As shown in FIG2a to FIG2e, the first gate dielectric layer 14 and the second gate dielectric layer 15 can be both located outside the trench, and the first gate dielectric layer 14 and the second gate dielectric layer 15 are both in contact with the outer sidewall of the trench, and the first gate 16 and the second gate 17 are also arranged outside the trench.

[0099] Alternatively, as shown in FIG3a and FIG3b , when the first insulating layer 21 is filled in the trench, the first gate dielectric layer 14 and the second gate dielectric layer 15 may also be located in the trench, with the first gate dielectric layer 14 and the second gate dielectric layer 15 both in contact with the inner sidewalls of the trench, the first gate 16 and the second gate 17 also disposed in the trench, and the first insulating layer 21 disposed between the first gate 16 and the second gate 17. In this case, to prevent contact between the trench and the first gate 16 and the second gate 17, the trench 12 may not include a bottom.

[0100] As shown in Figures 3a and 3b, when both the first gate 16 and the second gate 17 are located within the trench, the channels 12 of adjacent vertical transistors are connected above the first electrode 11 along the direction from the first gate 16 to the second gate 17. Compared to a case where the channels 12 of adjacent vertical transistors are disconnected, connecting the channels 12 of adjacent vertical transistors above the first electrode 11 can increase the contact area between the channels 12 and the first electrode 11. In this case, the longitudinal cross-section of the portion of the channel 12 located between the first gate dielectric layer 14 and the second gate dielectric layer 15 of the adjacent vertical transistors can be U-shaped.

[0101] In some possible implementations, as shown in Figures 5a-5c, the channel 12 further includes an extension portion in addition to the groove, and the extension portion contacts the second pole 13. The extension portion is connected to the sidewall of the groove and extends outward to increase the contact area between the channel 12 and the second pole 13.

[0102] In addition, in some possible implementations, as shown in Figures 5b and 5c, the longitudinal cross-sections of the first gate dielectric layer 14 and the second gate dielectric layer 15 can be L-shaped, and the first gate dielectric layer 14 is located both between the first gate 16 and the channel 12 and between the first gate 16 and the first pole 11; the second gate dielectric layer 15 is located both between the second gate 17 and the channel 12 and between the second gate 17 and the first pole 11.

[0103] Based on this structure, the embodiment of the present application does not limit the size of each structure in the vertical transistor.

[0104] Optionally, in the Z direction, the gate length of the first gate 16 and the second gate 17 can range from 10nm to 150nm; the vertical distance between the first gate 16 and the second gate 17 and the first pole 11 can range from 5nm to 50nm; the vertical distance between the first gate 16 and the second gate 17 and the second pole 13 can range from 5nm to 50nm.

[0105] Taking the first gate 16 and the second gate 17 outside the trench as an example, in the X direction or the Y direction, the total diameter of the channel 12 can range from 10nm to 150nm, the sidewall thickness of the channel 12 can range from 1nm to 15nm, and the diameter of the trench does not exceed 148nm; the thickness of the first gate 16 and the second gate 17 can range from 3nm to 50nm; the width of the second electrode 13 can range from 10nm to 150nm; the spacing between the centers of adjacent vertical transistors can range from 15nm to 200nm; the spacing between the centers of the channels 12 of adjacent vertical transistors can range from 15nm to 200nm.

[0106] In some possible implementations, the vertical transistors of the present application can be independent isolated devices, that is, the first gate 16 of any vertical transistor is not shared with the first gate 16 of other vertical transistors on the chip, the second gate 17 of any vertical transistor is not shared with the second gate 17 of other vertical transistors on the chip, the first pole 11 of any vertical transistor is not shared with the first pole 11 of other vertical transistors on the chip, and the second pole 13 of any vertical transistor is not shared with the second pole 13 of other vertical transistors on the chip.

[0107] The multiple vertical transistors of the present application can also form a connected array structure. For example, as shown in Figure 3a, along the Y direction, multiple vertical transistors located in the same column share the same first electrode 11; and / or, along the X direction, multiple vertical transistors located in the same row share the same first gate 16 and the same second gate 17.

[0108] In some possible implementations, as shown in FIG. 2 a and FIG. 3 a , multiple vertical transistors on a chip are not stacked in the Z direction; or, as shown in FIG. 6 , vertical transistors may be stacked in multiple layers in the Z direction.

[0109] Continuing with FIG6 , when vertical transistors are stacked in multiple layers in the Z direction, the second electrode 13 of the lower vertical transistor can be reused as the first electrode 11 of the upper vertical transistor. Of course, other connection methods can also be used between the transistors stacked in the Z direction, and this embodiment of the application is not limited to this.

[0110] In addition, the longitudinal cross-sections of the first gate dielectric layer 14 and the second gate dielectric layer 15 may have other shapes besides an L-shape. As shown in FIG7a , the longitudinal cross-sections of the first gate dielectric layer 14 and the second gate dielectric layer 15 may also be rectangular, with the first gate dielectric layer 14 being located between the first gate 16 and the channel 12, and the second gate dielectric layer 15 being located between the second gate 17 and the channel 12. As shown in FIG7b , when both the first gate 16 and the second gate 17 are located on the side of the channel 12 facing away from the first insulating layer 21, the first gate dielectric layer 14 surrounds the first gate 16 and exposes the surface of the first gate 16 facing away from the channel 12. On this basis, the first gate dielectric layer 14 may further extend in the Z direction toward the first stage 11 and / or the second pole 13; the second gate dielectric layer 15 surrounds the second gate 17 and exposes the surface of the second gate 17 facing away from the channel 12. On this basis, the second gate dielectric layer 15 may further extend in the Z direction toward the first stage 11 and / or the second pole 13.

[0111] The structure can be implemented by first digging a groove on the side of the sacrificial structure, then forming a first gate dielectric layer 14 and a second gate dielectric layer 15 in the groove, and then forming a first gate 16 on the first gate dielectric layer 14 and a second gate 17 on the second gate dielectric layer 15. Since the groove digging process is more controllable and has higher process precision, the gate lengths of the first gate 16 and the second gate 17 filled in the groove are more controllable.

[0112] In some possible implementations, a buffer layer may be further included between the first electrode 11 and / or the second electrode 13 and the channel 12. As shown in FIG7c , the buffer layer 30 is disposed between the first electrode 11 and the channel 12; as shown in FIG7d , the buffer layer 30 is disposed between the second electrode 13 and the channel 12; and as shown in FIG7e , the buffer layer 30 is disposed between the first electrode 11 and the channel 12, and between the second electrode 13 and the channel 12.

[0113] In some possible implementations, the embodiments of the present application do not limit the materials of each structure in the vertical transistor.

[0114] Optionally, the channel 12 may be an oxide semiconductor material deposited by a deposition process such as atomic layer deposition (ALD), and the material may include elements such as indium (In), gallium (Ga), zinc (Zn), tin (Sn), tungsten (W), magnesium (Mg), aluminum (Al), and silicon (Si), such as indium gallium zinc oxide (InGaZnO), indium tin oxide (InSnO), indium gallium oxide (InGaO), and indium magnesium oxide (InMgO). By using an oxide semiconductor material as the material of the channel 12, the leakage of the vertical transistor can be reduced. In the scenario where the vertical transistor is applied to a memory, the retention time of the memory can be improved, the power consumption of the memory can be reduced, and the area of ​​the capacitor in the memory can be reduced, thereby improving the integration density.

[0115] Of course, the material of the channel 12 in the present application can also be an amorphous structure, a partially crystallized structure, or contain other semiconductor materials, such as polycrystalline silicon poly-Si, amorphous silicon a-Si, two-dimensional materials, etc.

[0116] The material of the first gate dielectric layer 14 and the second gate dielectric layer 15 may include an oxide dielectric material, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium silicon oxide (HfSiO), etc., or may be a nitride such as silicon nitride (SiN), or the material of the first gate dielectric layer 14 and the second gate dielectric layer 15 may include HfO2 and Al2O3.

[0117] The first gate 16 and the second gate 17 can both be single layers, or they can both be stacked layers. Taking the case where the first gate 16 and the second gate 17 are both single layers as an example, the materials of the first gate 16 and the second gate 17 can include metals such as tungsten (W), ruthenium (Ru), nickel (Ni), molybdenum (Mo), or alloy materials such as platinum nickel (NiPt); alternatively, the materials of the first gate 16 and the second gate 17 can also be conductive oxides / nitrides, such as InSnO, titanium nitride (TiN), tantalum nitride (TaN), etc. Taking the case where the first gate 16 and the second gate 17 are both stacked layers as an example, the first gate 16 and the second gate 17 can both be stacked layers of TaN and W. The TaN layer is located between the W layer and the first gate dielectric layer 14 / the second gate dielectric layer 15.

[0118] The materials of the first electrode 11 and the second electrode 13 may include metal, nitride or alloy electrodes, for example, W, Ni, Mo, Ru, NiPt, TiN. The materials of the first electrode 11 and the second electrode 13 may also be conductive oxides, such as InSnO.

[0119] The material of the first insulating layer 21 may be oxide, nitride, oxycarbide, etc., for example, silicon oxide (SiO), SiN, silicon oxycarbide (SiOC), aluminum oxide (AlO), etc.

[0120] In another embodiment, as shown in Figures 8a to 9b, an embodiment of the present application further provides a chip, which includes a vertical transistor, and the processing transistor includes a first electrode 11, a channel 12, and a second electrode 13 stacked in sequence. Among them, the second electrode 13 includes a first sub-electrode 131 and a second sub-electrode 132 arranged opposite to each other. For example, the first electrode 11 is a source, the second electrode 13 is a drain, the first sub-electrode 131 is a first drain, and the second sub-electrode 132 is a second drain. Alternatively, the first electrode 11 is a drain, the second electrode 13 is a source, the first sub-electrode 131 is a first source, and the second sub-electrode 132 is a second source. In the present application, the direction from the first electrode 11 to the second electrode 13 can be the Z direction.

[0121] The chip also includes a first gate dielectric layer 14 and a second gate dielectric layer 15, both of which contact the sidewalls of the channel. The portion of the channel 12 that contacts the first gate dielectric layer 14 is called the first channel 121, and is located between the first electrode 11 and the first sub-electrode 131. The portion of the channel 12 that contacts the second gate dielectric layer 15 is called the second channel 122, and is located between the first electrode 11 and the second sub-electrode 132.

[0122] The chip further includes a first gate 16 and a second gate 17 disposed opposite each other. The first gate 16 is disposed on the side of the first gate dielectric layer 14 facing away from the channel 12, and the second gate 17 is disposed on the side of the second gate dielectric layer 15 facing away from the channel 12. Furthermore, since the first gate 16 and the second gate 17 are disposed opposite each other, the first gate dielectric layer 14 for isolating the first gate 16 from the channel 12 and the second gate dielectric layer 15 for isolating the second gate 17 from the channel 12 can also be disposed opposite each other.

[0123] The vertical transistors obtained from the above structure are respectively a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first electrode 11, a first channel 121, a first sub-electrode 131, a first gate dielectric layer 14, and a first gate 16. The second vertical transistor includes a first electrode 11, a second channel 122, a second sub-electrode 132, a second gate dielectric layer 15, and a second gate 17. As in the previous embodiment, the first electrode 11 of the first vertical transistor and the first electrode 11 of the second vertical transistor are shared, or the first electrode 11 of the first vertical transistor and the first electrode 11 of the second vertical transistor may not be shared. The first gate 16 is used to control whether the first vertical transistor is turned on or off, and the second gate 17 is used to control whether the second vertical transistor is turned on or off. That is, the first vertical transistor and the second vertical transistor in the embodiment of the present application are both single-gate vertical transistors.

[0124] Compared to related technologies, the present invention can split a vertical transistor into a first vertical transistor and a second vertical transistor, thereby improving integration density. Compared to the dual-gate vertical transistor provided in the previous embodiment, the spacing between the center of the first vertical transistor and the center of the second vertical transistor in the direction from the first vertical transistor to the second vertical transistor can be less than 30nm. In other words, the pitch between the first vertical transistor and the second vertical transistor can be less than 30nm. When applied to DRAM, it can achieve a smaller unit area than advanced processes 1beta and 1gamma.

[0125] Furthermore, because the first gate 16 and the second gate 17 of the present application are no longer in a surrounding shape, and the first gate dielectric layer 14 and the second gate dielectric layer 15 are no longer in a surrounding shape, the present application no longer uses the related art process of first forming a first through hole in the surrounding gate and then forming a second through hole in the gate dielectric layer. Instead, a sacrificial structure (such as a sacrificial layer, a dummy channel, etc.) is first formed in the area where the channel 12 is to be formed, grooves are cut between adjacent sacrificial structures, and then the first gate dielectric layer 14 and the second gate dielectric layer 15, as well as the first gate 16 and the second gate 17, are formed on the sidewalls of the sacrificial structure. Subsequently, by removing the sacrificial structure and forming the channel 12 at the location of the sacrificial structure, the channel 12 can be brought into contact with the first electrode 11. That is, the present application does not need to form a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 14, thereby avoiding the process limitations of forming the second through hole that prevent the size of the vertical transistor from being miniaturized.

[0126] On the other hand, the first gate 16 and the second gate 17 are arranged relative to each other, rather than being arranged around the channel 12 as in the related art. Therefore, the sizes of the first vertical transistor and the second vertical transistor in the X direction and the Y direction can be reduced, so that the first vertical transistor and the second vertical transistor can be miniaturized; at the same time, the first gate dielectric layer 14 and the second gate dielectric layer 15 can also be arranged relative to each other, rather than surrounding the channel 12. Therefore, the total area of ​​the first gate dielectric layer 14 and the second gate dielectric layer 15 of the present application is smaller than the total area of ​​the gate dielectric layer in the ring gate scheme, thereby reducing the size of the vertical transistor in the X direction and / or direction, so that the vertical transistor can be miniaturized.

[0127] In some possible implementations, the embodiments of the present application do not limit the relative positions of the first sub-electrode 131 and the second sub-electrode 132; as long as the first sub-electrode 131 and the second sub-electrode 132 are disposed opposite each other, it suffices. Alternatively, as shown in FIG8d , the first sub-electrode 131 and the second sub-electrode 132 may be disposed directly opposite each other in the X or Y direction; or, as shown in FIG8e , the first sub-electrode 131 and the second sub-electrode 132 may be disposed opposite each other but not completely opposite each other in the X or Y direction.

[0128] Similarly, the embodiments of the present application do not limit the relative positions of the first gate 16 and the second gate 17; as long as the first gate 16 and the second gate 17 are disposed opposite each other, they are sufficient. Alternatively, the first sub-electrode 131 and the second sub-electrode 132 may be disposed opposite each other in the X or Y direction; or, the first gate 16 and the second gate 17 may be disposed opposite each other but not completely opposite each other in the X or Y direction.

[0129] For the convenience of description, unless otherwise specified, the following description is based on the example that the first sub-electrode 131 and the second sub-electrode 132 are opposite to each other in the Y direction, and the first gate 16 and the second gate 17 are opposite to each other in the Y direction.

[0130] In some possible implementations, as shown in FIG8b , since the first electrode 11 of the first vertical transistor and the first electrode 11 of the second vertical transistor are shared, the first channel 121 and the second channel 122 can be connected without a short circuit problem; alternatively, as shown in FIG8c , the first channel 121 and the second channel 122 can be disconnected. Compared to the solution in which the first channel 121 and the second channel 122 are disconnected, the solution in which the first channel 121 and the second channel 122 can be connected does not require etching to disconnect the first channel 121 and the second channel 122, and the process is simple. Compared to the solution in which the first channel 121 and the second channel 122 can be connected, the solution in which the first channel 121 and the second channel 122 are disconnected not only improves the crosstalk between the first vertical transistor and the second vertical transistor caused by the connection between the first channel 121 and the second channel 122, but also facilitates the preparation of a first vertical transistor and a second vertical transistor that are not connected.

[0131] When the first channel 121 is connected to the second channel 122, as shown in Figure 8a, the first channel 121 and the second channel 122 form a solid integral structure or a hollow structure; or, referring to Figure 2f, the first channel 121 and the second channel 122 form a groove with a bottom, or in other words, a groove including a bottom is provided in the channel 12, and the cross-section of the groove is a closed circle. For example, the cross-section of the groove can be a closed shape such as a "mouth" shape, a circle, an ellipse, etc.; or, as shown in Figures 4a-4b, the longitudinal section of the groove is U-shaped.

[0132] As shown in Figure 8c, when the first channel 121 and the second channel 122 are disconnected, the first channel 121 and the second channel 122 can both be independent columns, and the columnar first channel 121 and the second channel 122 constitute a groove without a bottom. In other words, a groove without a bottom is opened in the channel 12.

[0133] When the first channel 121 and the second channel 122 form a trench and the trench has a bottom, the second electrode 13 can be filled in the trench. Because the trench of the channel 12 includes a bottom, the second electrode 13 does not directly contact the first electrode 11. Alternatively, as shown in Figures 8b and 8c, regardless of whether the trench includes a bottom, the chip may further include a first insulating layer 21, which can be filled in the trench to separate the first electrode 11 and the second electrode 13.

[0134] In some possible implementations, the surface of the trench facing the first pole 11 is considered the first surface, and the surface of the trench facing the second pole 13 is considered the second surface. Outside the trench, the surface adjacent to the first surface and the second surface is considered the outer sidewall of the trench; inside the trench, the surface adjacent to the second surface and the bottom of the trench is considered the inner sidewall of the trench.

[0135] As shown in FIG8a-8c, the first gate dielectric layer 14 and the second gate dielectric layer 15 can be both located outside the trench, and the first gate dielectric layer 14 and the second gate dielectric layer 15 are both in contact with the outer sidewall of the trench, and the first gate 16 and the second gate 17 are also arranged outside the trench.

[0136] Alternatively, as shown in Figures 9a and 9b, when the trench is filled with the first insulating layer 21, the first gate dielectric layer 14 and the second gate dielectric layer 15 can also be located in the trench, with the first gate dielectric layer 14 and the second gate dielectric layer 15 both in contact with the inner sidewalls of the trench, the first gate 16 and the second gate 17 also disposed in the trench, and the first insulating layer 21 disposed between the first gate 16 and the second gate 17. In this case, to prevent the trench from contacting the first gate 16 and the second gate 17, the trench 12 may not include a bottom.

[0137] As shown in Figures 9a and 9b, when both the first gate 16 and the second gate 17 are located within the trench, the channels 12 of adjacent vertical transistors are connected above the first electrode 11 along the direction from the first gate 16 to the second gate 17. Compared to a case where the channels 12 of adjacent vertical transistors are disconnected, connecting the channels 12 of adjacent vertical transistors above the first electrode 11 can increase the contact area between the channels 12 and the first electrode 11. In this case, the longitudinal cross-section of the portion of the channel 12 located between the first gate dielectric layer 14 and the second gate dielectric layer 15 of the adjacent vertical transistors can be U-shaped.

[0138] As shown in Figure 8c, channel 12 also includes an extension portion in addition to the groove, and the extension portion contacts the second electrode 13. The extension portion is connected to the sidewall of the groove and extends outward to increase the contact area between channel 12 and second electrode 13. For example, taking the longitudinal cross-section of channel 12 as an example, the extension portion of first channel 121 extends away from the second channel 122, and the extension portion of second channel 122 extends away from the first channel 121.

[0139] On this basis, as shown in Figures 8b and 8c, the longitudinal cross-sections of the first gate dielectric layer 14 and the second gate dielectric layer 15 can be L-shaped, and the first gate dielectric layer 14 is located both between the first gate 16 and the channel 12 and between the first gate 16 and the first pole 11; the second gate dielectric layer 15 is located both between the second gate 17 and the channel 12 and between the second gate 17 and the first pole 11.

[0140] In addition, for the dimensions and materials of each structure in the chip of the embodiment of the present application, reference can be made to the dimensions and materials of each structure in the chip of the previous embodiment, and the embodiment of the present application will not be repeated here.

[0141] The vertical transistors provided in the above two embodiments can be applied to a memory device, wherein the memory device includes a memory array, the memory array includes memory cells, and the memory cells include at least one vertical transistor and at least one capacitor. The capacitor includes a first electrode 41, a second electrode 42, and a dielectric layer located between the first electrode 41 and the second electrode 42.

[0142] As shown in FIG10 a , the capacitor is disposed above the vertical transistor, and the first electrode 41 of the capacitor is electrically connected to the second electrode 13 of the vertical transistor.

[0143] As shown in FIG10 b , the capacitor is disposed below the vertical transistor, and the first electrode 41 of the capacitor is electrically connected to the first electrode 11 of the vertical transistor.

[0144] As shown in FIG10 c , the capacitor is disposed above the vertical transistor, and the first electrode 41 of the capacitor is reused as the second electrode 13 of the vertical transistor, forming a structure in which the capacitor wraps the vertical transistor.

[0145] As shown in Figure 10d, single-gate vertical transistors are stacked in multiple layers in the Z direction. A capacitor is also provided above or below each vertical transistor, and the second electrode 42 of the capacitor is electrically connected to the second electrode 13 of the vertical transistor. As shown in Figure 10d, taking two vertical transistors stacked in the Z direction as an example, the capacitor, vertical transistor, vertical transistor, and capacitor are stacked in the Z direction in sequence. The second electrode 13 of the vertical transistor located below is shared with the first electrode 11 of the vertical transistor located above.

[0146] The vertical transistor and capacitor shown in Figure 10d can be applied to the circuit diagram shown in Figure 10e , which shows a circuit diagram of a memory device. Each memory cell in the memory device is a 1T1C device, consisting of one vertical transistor and one capacitor. A common bit line BL is located between two rows of memory cells in Figure 10e . Corresponding to the structure shown in Figure 10d , the memory device includes n columns of bit lines BL and m rows of word lines WL. The memory cells on either side of the bit line BL are controlled by different word lines WL.

[0147] The figure shows four rows of memory cells in the same column, corresponding to word lines WL0 through WL3. This structure doubles the memory density. Furthermore, because two rows of memory cells share the same bit line BL, only one layer of bit line BL is required between them, saving masks and improving the capacity-to-cost ratio.

[0148] In some possible implementations, the embodiments of the present application are applicable to 2T0C memory cells in addition to 1T1C memory cells. Figures 11a and 11b show a top view of a 2T0C memory cell. In the figure, the memory cell includes a first vertical transistor and a second vertical transistor with a single gate. In addition to sharing a first electrode 11 and being electrically connected to the bit line BL, the first vertical transistor and the second vertical transistor have a second sub-electrode 132 electrically connected to a pre-node SN (e.g., SN00 in Figure 11a) with the first gate 16 of the first vertical transistor. In addition, the second gate is electrically connected to the write word line WWL in the memory array, and the first sub-electrode 131 is electrically connected to the read word line RWL.

[0149] It should be understood that to demonstrate that the second sub-electrode 132 of the second vertical transistor is also electrically connected to the pre-node SN with the first gate 16 of the first vertical transistor, the top view shown in FIG11 a shows the first gate 16 and the second gate 17. However, in an actual structure, the first gate 16 and the second gate 17 should be shielded by insulating material, the first gate is electrically connected to the second sub-electrode 132 via a through-hole in the insulating material, and the second gate is electrically isolated from the second sub-electrode 132 by the insulating material.

[0150] Compared with storage cells that require RBL (read BL) and WBL (write BL), this circuit structure reduces one bit line, has a simpler winding structure, occupies a smaller area, and can achieve higher array density.

[0151] This structure features a second vertical transistor serving as the write transistor (Wtr) in the 2T0C memory cell, and a first vertical transistor serving as the read transistor (Rtr) in the 2T0C memory cell. Because the first gate SN of the read FET is an independent electrode, the interconnected first gates 16 of multiple first vertical transistors in the same row on the Rtr side are now separated and independent in the 2T0C, while the second gates 17 of multiple second vertical transistors in the same row on the Wtr side remain connected.

[0152] Of course, the vertical transistors and capacitors in the memory cell may also be arranged and electrically connected in other ways, which is not limited in the embodiments of the present application.

[0153] In another embodiment, the embodiment of the present application also provides a method for preparing a chip. As described in the above embodiment, the vertical transistors on the chip can be divided into dual-gate vertical transistors and single-gate vertical transistors. The preparation process of chips provided with dual-gate vertical transistors and single-gate vertical transistors will be described below in conjunction with the accompanying drawings.

[0154] In the first case, both the first gate 16 and the second gate 17 are in contact with the outer sidewalls of the channel 12, and the vertical transistor on the chip is a dual-gate vertical transistor. As shown in FIG12 , this structure can be implemented by the following steps:

[0155] S110, as shown in FIG13a, a first conductive layer 111 and a first sacrificial layer 51 are sequentially deposited on the substrate 10; as shown in FIG13b, the first conductive layer 111 and the first sacrificial layer 51 are patterned, and the patterned first conductive layer 111 becomes the first electrode 11. The patterned first sacrificial layer covers the surface of the first electrode 11 facing away from the substrate 10. Next, as shown in FIG13c, a second insulating layer 22 is formed on the first sacrificial layer 51 and the first electrode 11, and the second insulating layer 22 completely covers the first sacrificial layer 51 and the first electrode 11. Polishing is then performed, for example, by chemical mechanical polishing (CMP); as shown in FIG13d, the second insulating layer 22 is patterned, and along the X direction, the patterned second insulating layer 22 is located between adjacent first electrodes 11 and between adjacent first sacrificial layers 51.

[0156] S120, as shown in FIG13e, a third insulating layer 23 is formed on the first sacrificial layer 51, the first pole 11, and the second insulating layer 22, and the third insulating layer 23 completely covers the first pole 11, the side walls of the first sacrificial layer 51, and the side walls of the second insulating layer 22, exposing the surface of the second insulating layer 22 and the first sacrificial layer 51 facing away from the substrate 10; as shown in FIG13f, the third insulating layer 23 is etched back, and in the Y direction, the third insulating layer 23 after etching back is located between adjacent first poles 11 and covers the side walls of the first pole 11, exposing part of the side walls of the second insulating layer 22 and the first sacrificial layer 51 and the surface facing away from the substrate 10, wherein the etching depth of the third insulating layer 23 determines the vertical distance between the subsequent first gate 16 and the second gate 17 and the first pole 11. Next, as shown in FIG14a , a gate dielectric layer 141 and a second conductive layer 161 are sequentially formed on the third insulating layer 23 and the second insulating layer 22 , wherein the gate dielectric layer 141 completely covers the sidewalls and the surface of the second insulating layer 22 facing away from the substrate 10 , as well as the surface of the third insulating layer 23 facing away from the substrate 10 ; as shown in FIG14b , the second conductive layer 161 is etched back to etch the second conductive layer 161 to a certain depth and expose a portion of the surface of the gate dielectric layer 141 .

[0157] S130, as shown in Figure 14c, a second sacrificial layer 52 is formed on the gate dielectric layer 141, and the second sacrificial layer 52 completely covers the side walls and the surface of the gate dielectric layer 141 on the side facing away from the substrate 10, as well as the surface of the second conductive layer 161 on the side facing away from the substrate 10; as shown in Figure 14d, the second sacrificial layer 52 is etched back, and the side walls of the second sacrificial layer 52 are retained and in contact with the outer side walls of the gate dielectric layer 141. As shown in Figure 14e, under the protection of the second sacrificial layer 52, the second conductive layer 161 and the gate dielectric layer 141 are etched back, and the portions of the second conductive layer 161 and the gate dielectric layer 141 covering the side walls of the second insulating layer 22 are retained. The retained portions of the gate dielectric layer 141 are the first gate dielectric layer 14 and the second gate dielectric layer 15, and the retained portions of the second conductive layer 161 are the first gate dielectric layer 16 and the second gate dielectric layer 17. Both the first gate dielectric layer 14 and the second gate dielectric layer 15 are in contact with the outer side walls of the second insulating layer 22. The first gate 16 is located on the side of the first gate dielectric layer 14 away from the second insulating layer 22, and the second gate is located on the side of the second gate dielectric layer 15 away from the second insulating layer 22.

[0158] S140, as shown in FIG14f, continues to form an insulating material on the first gate dielectric layer 14, the second gate dielectric layer 15, the first gate electrode 16, the second gate electrode 17, and the second sacrificial layer 52. This insulating material can be the same as the material of the third insulating layer 23, collectively referred to as the third insulating layer 23. The third insulating layer 23 covers the sidewalls of the first gate dielectric layer 14, the second gate dielectric layer 15, the first gate electrode 16, the second gate electrode 17, and the second sacrificial layer 52.

[0159] S150, as shown in FIG15a, removes the first sacrificial layer 51 and forms a groove in the area where the channel 12 to be formed is located to expose the first electrode 11. The figure shows that in the above process, the second insulating layer 22 and the third insulating layer 23 around the first gate dielectric layer 14 and the second gate dielectric layer 15 may also be partially etched, so that the first gate dielectric layer 14 and the second gate dielectric layer 15 may protrude. As shown in FIG15b, the semiconductor layer 121 and the first insulating layer 21 are formed in sequence. The semiconductor layer 121 and the first insulating layer 21 cover the second insulating layer 22, the third insulating layer 23, the first gate dielectric layer 14 and the second gate dielectric layer 15. Since the first gate dielectric layer 14 and the second gate dielectric layer 15 protrude, the portion of the semiconductor layer 121 that overlaps with the first gate dielectric layer 14 and the second gate dielectric layer 15 also protrudes. The portion of the semiconductor layer 121 that overlaps with the area between the first gate dielectric layer 14 and the second gate dielectric layer 15 forms a trench. Next, as shown in FIG15 c , the first insulating layer 21 is etched back. After etching, the first insulating layer 21 is located in the trench of the semiconductor layer 121 .

[0160] The YZ and XZ views in FIG15a are side views, which do not show the area where the channel 12 to be formed is located. However, the XY top view in FIG15a shows that after removing the first sacrificial layer 51, the surface of the first electrode 11 facing away from the substrate 10 is exposed, and a groove is formed in the area where the channel 12 to be formed is located. The groove is surrounded by the first electrode 11, the second insulating layer 22, the first gate dielectric layer 14, and the second gate dielectric layer 15. Furthermore, the semiconductor layer 121 to be formed can be filled in the groove, and after the subsequent step S160, the portion of the semiconductor layer 121 located in the groove becomes the channel 12.

[0161] S160, as shown in Figures 15d and 15e, a third conductive layer 1311 and a hard mask 60 are sequentially formed on the semiconductor layer 121 and the first insulating layer 21. As shown in Figures 15f and 15g, under the protection of the hard mask 60, the third conductive layer 1311 and the semiconductor layer 121 are partially removed in sequence to obtain the second electrode 13 and the channel 12. The second electrode 13 is in contact with the surface of the channel 12 facing away from the substrate 10. Next, the hard mask 60 is removed to obtain the dual-gate vertical transistor in the first embodiment described above, in which both the first gate 16 and the second gate 17 are in contact with the outer sidewalls of the channel 12.

[0162] Of course, if the second electrode 13 formed in S160 includes a first sub-electrode 131 and a second sub-electrode 132 arranged opposite to each other, this process step can also be used to form a single-gate first vertical transistor and a single-gate second vertical transistor (eg, FIG. 8 b ).

[0163] In the present application, a first sacrificial layer 51 and a second insulating layer 22 are first formed, grooves are created between adjacent first sacrificial layers 51 and adjacent second insulating layers 22 by etching back, and then first and second gate dielectric layers 14, 15, and first and second gate electrodes 16, 17 are formed on the sidewalls of the first and second sacrificial layers 51, 22. Subsequently, the first sacrificial layer 51 is removed, and a channel 12 is formed at the location of the first sacrificial layer 51, thereby enabling contact between the channel 12 and the first electrode 11. In other words, the present application eliminates the need to form a second through hole between the first and second gate dielectric layers 14, thereby avoiding the inability to scale the vertical transistor due to process limitations associated with forming the second through hole.

[0164] In the second case, the first gate 16 and the second gate 17 are both in contact with the outer sidewalls of the channel 12, and the vertical transistors on the chip include a first vertical transistor with a single gate and a second vertical transistor with a single gate. As shown in FIG16 , this structure can be implemented by the following steps:

[0165] S210, as shown in FIG17a, sequentially forms a third sacrificial layer 53 and a fourth insulating layer 24 on the substrate 10. The third sacrificial layer 53 and the fourth insulating layer 24 have a hollow portion that penetrates the third sacrificial layer 53 and the fourth insulating layer 24 in the Z direction. The hollow portion is filled with the first electrode 11. In the Z direction, the thickness of the first electrode 11 is less than the depth of the hollow portion. As shown in FIG17b, a fifth insulating layer 25 is formed in the hollow portion, and the fourth insulating layer 24 is removed.

[0166] S220, as shown in FIG17c, a first gate dielectric layer 14 and a second gate dielectric layer 15 are formed on the outer sidewalls of the fifth insulating layer 25, and a first gate 16 and a second gate 17 are formed under the protection of the first protective layer 61. The first gate dielectric layer 14 is located between the first gate 16 and the fifth insulating layer 24, and the second gate dielectric layer 15 is located between the second gate 17 and the fifth insulating layer 25, and the first gate 16 and the second gate 17 are spaced apart.

[0167] S230, as shown in FIG17d, a sixth insulating layer 26 is formed on the sidewalls of the first gate 16 and the second gate 17 to cover the sidewalls of the first gate 16 and the second gate 17. Next, the fifth insulating layer 25 is removed to expose the first electrode 11.

[0168] S240 , forming a semiconductor layer 121 , wherein the semiconductor layer 121 extends from the hollow portion to the outside of the hollow portion.

[0169] In some possible implementation methods, as shown in Figure 17e, if the channel 12 to be formed is a solid integral structure or a hollow structure, the semiconductor layer 121 can fill the part of the hollow portion except the first pole 11, and then the semiconductor layer 121 is partially removed to obtain a semiconductor layer middle pattern 1211, and the semiconductor layer middle pattern 1211 extends along the Y direction.

[0170] Alternatively, as shown in Figure 17f, if the channel 12 to be formed also has a groove, and the groove is filled with a first insulating layer 21, the semiconductor layer 121 partially fills the first pole 11 in contact with the bottom in the hollow portion. After the semiconductor layer 121 is formed, the first insulating layer 21 is also filled into the hollow portion, and the first insulating layer 21 completely covers the semiconductor layer 121; then, as shown in Figure 17g, the portion of the first insulating layer 21 except the hollow portion is removed; as shown in Figure 17h, the semiconductor layer 121 is partially removed to obtain a semiconductor layer intermediate pattern 1211, and the semiconductor layer intermediate pattern 1211 extends along the Y direction.

[0171] At step S250, as shown in FIG17i , a third conductive layer 1311 and a hard mask 60 are formed. As shown in FIG17j , under the protection of the hard mask 60, the third conductive layer 1311 is removed to obtain the second electrode 13. The second electrode 13 includes a first sub-electrode 131 and a second sub-electrode 132 disposed opposite each other. The mask 60 can then be removed.

[0172] S260, as shown in FIG17k, partially removes the semiconductor layer intermediate pattern 1211 to obtain the channel 12, which includes a first channel 121 and a second channel 122. The first channel 121 is located between the first electrode 11 and the first sub-electrode 131, and the second channel 122 is located between the first electrode 11 and the second sub-electrode 132. Thus, the single-gate vertical transistor in the second embodiment described above is obtained, in which the first gate 16 and the second gate 17 are both in contact with the outer sidewalls of the channel 12.

[0173] Of course, if the second electrode 13 in a vertical transistor formed in S250 is an integral structure rather than including the first sub-electrode 131 and the second sub-electrode 132 arranged opposite to each other, and the first channel 121 and the second channel 122 formed in S260 form a groove, the first insulating layer 21 can also be filled in the groove to use this process step to form a dual-gate vertical transistor (for example, Figures 2a and 2b).

[0174] In the present application, the fifth insulating layer 25 is formed in the region where the channel 12 is to be formed, and then the first gate dielectric layer 14 and the second gate dielectric layer 15, as well as the first gate electrode 16 and the second gate electrode 17, are formed on the sidewalls of the fifth insulating layer 25. Thereafter, the fifth insulating layer 25 is removed, and the channel 12 is formed at the location of the fifth insulating layer 25, so that the channel 12 can be brought into contact with the first electrode 11. That is, the present application does not require the formation of a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 14, thereby avoiding the limitation of the process for forming the second through hole that prevents the size of the vertical transistor from being reduced.

[0175] In the third case, the first gate 16 and the second gate 17 are both in contact with the inner sidewall of the channel 12, and the vertical transistor on the chip can be a dual-gate vertical transistor or a single-gate vertical transistor. As shown in FIG18 , this structure can be implemented by the following steps:

[0176] S310, as shown in FIG19a, a first electrode 11, an etch stop layer 70, and a fourth sacrificial layer 54 are sequentially formed on the substrate 10. In some possible implementations, the fourth sacrificial layer 54 may be directly formed on the first electrode 11 without forming the etch stop layer 70.

[0177] S320, as shown in FIG19b, the fourth sacrificial layer 54 is partially removed. The remaining fourth sacrificial layer 54 can serve as the first insulating layer 21 between the first gate 16 and the second gate 17 to be formed. Next, as shown in FIG19c and FIG19d, the area around the fourth sacrificial layer 54 is first filled with a second conductive layer 161, and then a second protective layer 71 is formed in the area where the first gate 16 and the second gate 17 to be formed are located.

[0178] S330, as shown in Figure 19e, under the protection of the second protective layer 71, the second conductive layer 161 and the etch stop layer 70 are partially removed in sequence to obtain the first gate 16 and the second gate 17, and the retained etch stop layer 70 overlaps with the first gate 16, the second gate 17, and the fourth sacrificial layer 54.

[0179] S340, as shown in FIG19f, a gate dielectric layer 141 and a dummy channel 72 are sequentially formed. The gate dielectric layer 14 completely covers the first gate 16, the second gate 17, and the surface of the fourth sacrificial layer 54 facing away from the substrate 10, as well as the surface of the substrate 10. The dummy channel 72 is etched back to remove the portion of the dummy channel 72 except for the sidewalls. The remaining dummy channel 72 covers the sidewalls of the gate dielectric layer 141. Next, as shown in FIG19g, under the protection of the dummy channel 72, the portion of the gate dielectric layer 141 not covered by the dummy channel 72 is removed to obtain the first gate dielectric layer 14 and the second gate dielectric layer 15.

[0180] S350, as shown in FIG19h, remove the dummy channel 72 and form a semiconductor layer 121. Next, as shown in FIG19i, form a seventh insulating layer 27, which is used to isolate adjacent vertical transistors in the Y direction.

[0181] Afterwards, referring to the first and second cases described above, the semiconductor layer 121 can also be partially removed to obtain the channel 12 according to the dual-gate vertical transistor or the single-gate vertical transistor; and the second electrode 13 can be formed above the channel 12, which will not be described in detail here. In addition, as shown in Figure 19j, after the channel 12 is obtained by using this process step, Figure 19j shows the first channel 121, the second channel 122, the first channel 121, and the second channel 122 in sequence along the Y direction. The present application can also form the second electrode 13 on the middle second channel 122 and the first channel 121. In this way, the dual-gate vertical transistor proposed in the first embodiment can also be prepared through this process step, in which the first gate 16 and the second gate 17 are outside the trench.

[0182] In the present application, by forming a fourth sacrificial layer 54 in the region where the channel 12 is to be formed, then forming a first gate dielectric layer 14 and a second gate dielectric layer 15, as well as a first gate electrode 16 and a second gate electrode 17 on the sidewalls of the fourth sacrificial layer 54, then removing the fourth sacrificial layer 54 and forming the channel 12 at the location of the fourth sacrificial layer 54, the channel 12 can be brought into contact with the first electrode 11. That is, the present application does not require forming a second through hole between the first gate dielectric layer 14 and the second gate dielectric layer 14, thereby avoiding the process limitations of forming the second through hole that prevent the size of the vertical transistor from being reduced.

[0183] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the first two embodiments and will not be repeated here.

[0184] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip, characterized in that: A vertical transistor is included, the vertical transistor comprising: A first electrode, a channel, and a second electrode are sequentially stacked on a substrate, wherein the channel includes a groove; a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer and the second gate dielectric layer are both in contact with sidewalls of the trench; the first gate dielectric layer and the second gate dielectric layer are both located in the trench, or the first gate dielectric layer and the second gate dielectric layer are both located outside the trench; A first gate and a second gate are spaced apart, wherein the first gate is disposed on a side of the first gate dielectric layer away from the channel, and the second gate is disposed on a side of the second gate dielectric layer away from the channel.

2. The chip according to claim 1, characterized in that The first gate dielectric layer and the second gate dielectric layer are both located outside the trench. The first gate is located on a side of the first gate dielectric layer away from the trench, and the second gate is located on a side of the second gate dielectric layer away from the trench.

3. The chip according to claim 2, characterized in that The chip further includes a first insulating layer, and the first insulating layer is filled in the groove; or, The trench further includes a bottom adjacent to the sidewalls, wherein the bottom is in contact with the first pole; the second pole is filled in the trench.

4. The chip according to claim 1, characterized in that The first gate dielectric layer and the second gate dielectric layer are both located in the trench, and the chip further includes a first insulating layer, which is filled in the trench; The first gate is disposed between the first gate dielectric layer and the first insulating layer, and the second gate is disposed between the second gate dielectric layer and the first insulating layer.

5. The chip according to any one of claims 1 to 4, characterized in that: There are multiple vertical transistors; The plurality of vertical transistors arranged along the column direction share the same first electrode; The plurality of vertical transistors arranged along a row direction share the same first gate and the same second gate.

6. The chip according to claim 5, characterized in that When both the first gate dielectric layer and the second gate dielectric layer are located in the trench, channels of adjacent vertical transistors arranged along the column direction are connected.

7. The chip according to any one of claims 1 to 6, characterized in that: The first gate and the second gate are arranged opposite to each other.

8. The chip according to any one of claims 2-3, 5-7, characterized in that: In the case where both the first gate dielectric layer and the second gate dielectric layer are located outside the trench, the longitudinal section of the trench is U-shaped, or the cross section of the trench is a closed circle; The longitudinal section of the groove is the interface of the groove along the plane where the first direction and the second direction are located, the first direction is the direction from the first pole to the second pole, and the second direction is the direction from the first gate to the second gate; the cross-section of the groove is the cross-section of the groove along the second direction.

9. A chip, characterized in that: A vertical transistor is included, the vertical transistor comprising: A first electrode, a channel, and a second electrode are sequentially stacked on a substrate; the second electrode includes a first sub-electrode and a second sub-electrode opposite to each other, and the channel includes a first channel located between the first electrode and the first sub-electrode and a second channel located between the first electrode and the second sub-electrode; a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer contacts the sidewall of the first channel, and the second gate dielectric layer contacts the sidewall of the second channel; A first gate and a second gate are arranged opposite to each other, wherein the first gate is arranged on a side of the first gate dielectric layer away from the first channel, and the second gate is arranged on a side of the second gate dielectric layer away from the second channel.

10. The chip according to claim 9, characterized in that The first channel and the second channel form a trench, and the chip further includes a first insulating layer filled in the trench.

11. The chip according to claim 10, characterized in that The first gate dielectric layer and the second gate dielectric layer are both located outside the trench, the first gate is located on a side of the first gate dielectric layer away from the first channel, and the second gate is located on a side of the second gate dielectric layer away from the second channel; or The first gate dielectric layer and the second gate dielectric layer are both located in the trench, the first gate is disposed between the first gate dielectric layer and the first insulating layer, and the second gate is disposed between the second gate dielectric layer and the second insulating layer.

12. The chip according to claim 10, characterized in that The first channel is disconnected from the second channel.

13. A memory, characterized in that: Comprising a storage array, the storage array comprising the chip according to any one of claims 1 to 8 or any one of claims 9 to 12; The memory array further includes a capacitor electrically connected to the vertical transistor in the chip.

14. The memory according to claim 13, wherein: The memory array comprises the chip according to any one of claims 1 to 8, and the memory array further comprises a word line and a bit line; the gate of the vertical transistor is electrically connected to the word line, the first electrode is electrically connected to the bit line, and the second electrode is electrically connected to the capacitor; or, The memory array includes the chip described in any one of claims 9 to 12, and the memory array also includes a write word line, a read word line, and a bit line; the second gate is electrically connected to the write word line, the second sub-electrode is electrically connected to the first gate, the first sub-electrode is electrically connected to the read word line, and the first electrode is electrically connected to the bit line.

15. An electronic device, characterized in that: It comprises a circuit board and the chip according to any one of claims 1 to 8 or the chip according to any one of claims 9 to 12 or the memory according to any one of claims 13 to 14, wherein the chip or the memory is arranged on the circuit board.

16. A method for preparing a chip, characterized in that: include: forming a first electrode, a first sacrificial layer, a second insulating layer, and a third insulating layer on the substrate; The first sacrificial layer covers a surface of the first electrode facing away from the substrate; In the third direction, the second insulating layer is located between adjacent first electrodes and between adjacent first sacrificial layers; In the second direction, the third insulating layer is located between adjacent first electrodes and covers the sidewalls of the first electrodes; A first gate dielectric layer, a second gate dielectric layer, a first gate, and a second gate are formed on a side of the third insulating layer facing away from the substrate; the first gate dielectric layer is located between the first gate and the second insulating layer, the second gate dielectric layer is located between the second gate and the second insulating layer, and the first gate and the second gate are spaced apart; removing the first sacrificial layer to form a groove to expose the surface of the first electrode facing away from the substrate, and sequentially filling the groove with a channel and a first insulating layer; A second pole is formed on the side of the channel and the first insulating layer facing away from the substrate; wherein the second direction is perpendicular to the third direction, and both the second direction and the third direction are perpendicular to the first direction from the first pole to the second pole.

17. The preparation method according to claim 16, characterized in that The second electrode includes a first sub-electrode and a second sub-electrode arranged opposite to each other, and the channel includes a first channel and a second channel; The first channel is located between the first electrode and the first sub-electrode, and the second channel is located between the first electrode and the second sub-electrode.

18. A method for preparing a chip, characterized in that: include: forming a third sacrificial layer, a fifth insulating layer, and a first electrode on the substrate; wherein the third sacrificial layer has a hollow portion, and the hollow portion penetrates the third sacrificial layer; The first electrode and the fifth insulating layer are filled in the hollow portion, and a vertical distance from a surface of the fifth insulating layer facing away from the substrate to the substrate is greater than a vertical distance from a surface of the three sacrificial layers facing away from the substrate to the substrate; A first gate dielectric layer, a second gate dielectric layer, a first gate electrode, and a second gate electrode are formed; the first gate dielectric layer is located between the first gate electrode and the second gate electrode; The second gate dielectric layer is located between the second gate and the fifth insulating layer, and the first gate and the second gate are spaced apart; removing the fifth insulating layer and forming a channel in the hollow portion, wherein the channel includes a first channel and a second channel; A second electrode is formed on the side of the channel away from the substrate, and the second electrode includes a first sub-electrode and a second sub-electrode arranged opposite to each other; the first channel is located between the first electrode and the first sub-electrode, and the second channel is located between the first electrode and the second sub-electrode.

19. The preparation method according to claim 18, characterized in that The first channel and the second channel form a groove; Before forming the second electrode on the side of the channel facing away from the substrate, the preparation method further includes: A first insulating layer is filled in the trench.

20. The preparation method according to claim 18 or 19, characterized in that: The step of forming a third sacrificial layer, a fifth insulating layer, and a first electrode on the substrate includes: forming the third sacrificial layer and the fourth insulating layer on the substrate, wherein the hollow portion penetrates the third sacrificial layer and the fourth insulating layer; sequentially filling the first electrode and the fifth insulating layer in the hollow portion; The fourth insulating layer is removed.

21. A method for preparing a chip, characterized in that: include: forming a first electrode and a fourth sacrificial layer on a substrate; wherein the fourth sacrificial layer is located on a side of the first electrode away from the substrate; forming a first gate and a second gate on both sides of the fourth sacrificial layer respectively; A first gate dielectric layer, a second gate dielectric layer, a channel, and a second electrode are formed; the channel is arranged on a side of the first gate dielectric layer away from the first gate and a side of the second gate dielectric layer away from the second gate; the second electrode is located on a side of the channel away from the substrate.

22. The preparation method according to claim 21, characterized in that Forming a first gate dielectric layer, a second gate dielectric layer, and a channel, including: forming a gate dielectric layer and a dummy channel on the first gate and the second gate in sequence; etching back the dummy channel, so that the remaining dummy channel covers the sidewall of the gate dielectric layer; Under the protection of the dummy channel, removing a portion of the gate dielectric layer not covered by the dummy channel to obtain the first gate dielectric layer and the second gate dielectric layer; The dummy channel is removed, and channels are formed on the side of the first gate dielectric layer away from the first gate electrode and on the side of the second gate dielectric layer and the second gate electrode.

Images