Display panel and driving method therefor, and display apparatus

Description

Display panel, driving method thereof, and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device. Background Art

[0002] Display devices such as liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays include multiple pixels arranged in an array. When the display device is displaying, a data chip needs to output pixel voltages to the pixel units through many data transmission lines.

[0003] In order to reduce the number of data transmission lines, a multiplexing (DEMUX) sub-circuit is set between the data chip and each data transmission line. Several MUX control lines are used to control the conduction of multiple thin-film transistors in the multiplexing sub-circuit, so that each data transmission line can be connected to multiple pixel units through the multiplexing sub-circuit, reducing the number of data driver chip ports.

[0004] However, in the existing double dataline multi-MUX architecture, the charging order of multiple MUXs corresponding to the same color is different, resulting in different compensation times, which will cause brightness differences and thus affect the display effect. Summary of the Invention

[0005] The purpose of the present application is to provide a display panel with uniform brightness and good display effect, a driving method thereof, and a display device.

[0006] The present application discloses a display panel, comprising:

[0007] A plurality of pixel units, wherein the plurality of pixel units are arranged in an array on the display panel;

[0008] A source driver module, the source driver module comprising a data driver chip and a plurality of multiplexing circuits; the data driver chip comprising a plurality of output ports, each of the output ports being connected to a plurality of the multiplexing circuits and outputting a plurality of pre-charge signals and data signals to the data lines under the control of the plurality of the multiplexing circuits;

[0009] The two data lines control a column of pixel units.

[0010] Optionally, the display panel further includes:

[0011] A gate driving module, wherein the gate driving module outputs a gate driving signal to the gate lines, and a row of the gate lines controls a row of the pixel units;

[0012] One of the two data lines controls the pixel units in odd rows, and the other controls the pixel units in even rows;

[0013] The multiplexing circuit controls the data driving chip to output the pre-charge signal before the effective level section of the gate driving signal;

[0014] The multiplexing circuit controls the data driving chip to output the data signal in the valid level section of the gate driving signal.

[0015] Optionally, two adjacent rows of gate lines form a group, the gate drive signals of the gate lines in the same group are in phase, and the gate drive signals of the next group of gate lines lag behind the gate drive signals of the current group by one phase.

[0016] Optionally, the plurality of pixel units include:

[0017] a first pixel unit of a first color, a second pixel unit of a second color, and a third pixel unit of a third color, wherein the first color, the second color, and the third color are different;

[0018] The pixel units in odd rows are arranged in a periodic sequence of the first pixel unit, the second pixel unit, the third pixel unit, and the second pixel unit; the pixel units in even rows are arranged in a periodic sequence of the third pixel unit, the second pixel unit, the first pixel unit, and the second pixel unit.

[0019] Optionally, each of the output ports is connected to four of the multiplexing circuits to generate four of the pre-charge signals and four of the data signals; the four pre-charge signals form a group, the four data signals form a group, and the four data lines form a group; a group of the data lines receives a group of the pre-charge signals and a group of the data signals; a group of the pre-charge signals is output before the effective level segment of the gate drive signal corresponding to a group of the gate lines, and a group of the data signals is output in the effective level segment of the gate drive signal corresponding to a group of the gate lines.

[0020] Optionally, the plurality of pixel units include:

[0021] a first pixel unit of a first color, a second pixel unit of a second color, and a third pixel unit of a third color, wherein the first color, the second color, and the third color are different;

[0022] The pixel units in odd rows are periodically arranged in the order of the first pixel unit, the second pixel unit, and the third pixel unit; the pixel units in even rows are periodically arranged in the order of the third pixel unit, the second pixel unit, and the first pixel unit.

[0023] Optionally, each of the output ports is connected to three of the multiplexing circuits to generate three of the pre-charge signals and three of the data signals; the three pre-charge signals form a group, the three data signals form a group, and the three data lines form a group; a group of the data lines receives a group of the pre-charge signals and a group of the data signals; a group of the pre-charge signals is output before the effective level segment of the gate drive signal corresponding to a group of the gate lines, and a group of the data signals is output in the effective level segment of the gate drive signal corresponding to a group of the gate lines.

[0024] Optionally, the plurality of pixel units include:

[0025] A first pixel unit of a first color, a second pixel unit of a second color, and a third pixel unit of a third color, wherein the first color, the second color, and the third color are different;

[0026] The pixel units in each row are periodically arranged in the order of the third pixel unit, the second pixel unit and the first pixel unit.

[0027] Optionally, the gate driving signal of the gate lines in the next row lags behind the gate driving signal of the gate lines in the current row by half a phase.

[0028] Optionally, each of the output ports is connected to six of the multiplexing circuits to generate six pre-charge signals and six data signals, three of the six pre-charge signals form a group, three of the six data signals form a group, three data lines form a group, and one of the two adjacent groups of data lines receives a group of pre-charge signals and data signals, and the other group of data lines receives another group of pre-charge signals and data signals; one group of data signals is output in the first half phase of the effective level segment of a corresponding group of gate drive signals, and the other group of data signals is output in the second half phase of the effective level segment of a corresponding group of gate drive signals.

[0029] The present application also discloses a method for driving a display panel, wherein the display panel comprises:

[0030] A plurality of pixel units, wherein the plurality of pixel units are arranged in an array on the display panel;

[0031] A source driver module, the source driver module comprising a data driver chip and a plurality of multiplexing circuits; the data driver chip comprising a plurality of output ports, each of the output ports being connected to the plurality of multiplexing circuits and outputting signals to data lines under the control of the plurality of multiplexing circuits; two data lines controlling a column of pixel units; one of the two data lines controlling the pixel units in odd rows, and the other controlling the pixel units in even rows;

[0032] A gate driving module, the gate driving module outputs a gate driving signal to the gate lines; a row of the gate lines controls a row of the pixel units;

[0033] The driving method includes:

[0034] Each of the output ports outputs a plurality of pre-charge signals to the data lines under the control of the plurality of multiplexing circuits, wherein the phases of the plurality of pre-charge signals are located before the effective level segment of the corresponding gate driving signal;

[0035] Each of the output ports outputs a plurality of data signals to the data lines under the control of a plurality of the multiplexing circuits. The phases of the plurality of data signals are located in the effective level section corresponding to the gate driving signal.

[0036] Optionally, two adjacent rows of gate lines form a group, the gate drive signals controlling the gate lines in the same group are in phase, and the gate drive signals controlling the next group of gate lines lag behind the gate drive signals of the current group by one phase;

[0037] Each of the output ports is connected to four of the multiplexing circuits, and the four multiplexing circuits control the output ports to generate four pre-charge signals and four data signals; the four pre-charge signals form a group, the four data signals form a group, and the four data lines form a group;

[0038] Control a group of the data lines to receive a group of the pre-charge signals and a group of the data signals; control a group of the pre-charge signals to be output before the effective level segment of the gate drive signal corresponding to a group of the gate lines, and control a group of the data signals to be output in the effective level segment of the gate drive signal corresponding to a group of the gate lines.

[0039] Optionally, two adjacent rows of gate lines form a group, the gate drive signals controlling the gate lines in the same group are in phase, and the gate drive signals controlling the next group of gate lines lag behind the gate drive signals of the current group by one phase;

[0040] Each of the output ports is connected to three of the multiplexing circuits, and the three multiplexing circuits control the output ports to generate three of the pre-charge signals and three of the data signals; the three pre-charge signals form a group, the three data signals form a group, and the three data lines form a group;

[0041] Control two adjacent groups of data lines to receive the same group of pre-charge signals and the same group of data signals; control one group of pre-charge signals to be output before the effective level segment of the gate drive signal of the corresponding group of gate lines, and control one group of data signals to be output in the effective level segment of the gate drive signal of the corresponding group of gate lines.

[0042] Optionally, the gate driving signal for controlling the gate lines in the next row lags behind the gate driving signal for the gate lines in the current row by half a phase;

[0043] Each of the output ports is connected to six of the multiplexing circuits, and the six multiplexing circuits control the output ports to generate six pre-charge signals and six data signals, wherein three of the six pre-charge signals form a group, and three of the six data signals form a group, and three data lines form a group;

[0044] Controlling one of the two adjacent groups of data lines to receive one group of the pre-charge signal and the data signal, and the other group of data lines to receive the other group of the pre-charge signal and the data signal;

[0045] One group of the data signals is controlled to be output in the first half phase of the effective level segment corresponding to one group of the gate drive signals, and another group of the data signals is controlled to be output in the second half phase of the effective level segment corresponding to one group of the gate drive signals.

[0046] The present application also discloses a display device, which includes the above-mentioned display panel.

[0047] Compared with the related art, the present application controls the data driver chip to output pre-charge signals and data signals to the data line through a multi-way distribution circuit, thereby solving the problem in the double dataline multi-MUX architecture that the charging order of multiple MUXs corresponding to the same color is different, resulting in different compensation times and causing brightness differences.

[0048] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0050] FIG1 is a schematic structural diagram of a display panel in an embodiment of the present application.

[0051] FIG2 is a schematic structural diagram of a display panel in an embodiment of the present application.

[0052] FIG. 3 is a timing diagram of the display panel in FIG. 2 .

[0053] FIG4 is a schematic structural diagram of a display panel according to an embodiment of the present application.

[0054] FIG. 5 is a timing diagram of the display panel in FIG. 4 .

[0055] FIG6 is a schematic structural diagram of a display panel according to an embodiment of the present application.

[0056] FIG. 7 is a timing diagram of the display panel in FIG. 6 . DETAILED DESCRIPTION

[0057] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0058] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those having ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0059] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0060] As shown in FIG1 , the present application provides a display panel, which includes:

[0061] A plurality of pixel units 100, wherein the plurality of pixel units 100 are arranged in an array on the display panel;

[0062] The source driver module 200 includes a data driver chip 210 and a plurality of multiplexing circuits. The data driver chip 210 includes a plurality of output ports, each of which is connected to a plurality of the multiplexing circuits and outputs a plurality of pre-charge signals and data signals to the data lines under the control of the plurality of the multiplexing circuits.

[0063] The two data lines control a column of pixel units 100 .

[0064] This application uses a multiplexing circuit to control the data driver chip to output pre-charge signals and data signals to the data line, solving the problem in the double dataline multi-MUX architecture where the charging order of multiple MUXs corresponding to the same color is different, resulting in different compensation times and causing brightness differences.

[0065] The following will describe in detail the various embodiments of the present application that are consistent with the above-mentioned creative concepts.

[0066] As shown in Figures 1 to 3 , the present application provides a display panel that includes a display area 1000 and a non-display area 2000 disposed around the display area 1000 .

[0067] A plurality of pixel units 100 are provided in the display area 1000. The plurality of pixel units 100 are arranged in an array in the display area 1000. For example, in a rectangular display panel, the plurality of pixel units 100 can be arranged in a rectangular array in the display panel. The plurality of pixel units 100 include a first pixel unit having a first color, a second pixel unit having a second color, and a third pixel unit having a third color, and the first color, the second color, and the third color are different. Optionally, the first color can be one of red, green, or blue, the second color can be another of red, green, or blue, and the third color can be the last of red, green, or blue. This application is described by taking the first color being blue, the second color being green, and the third color being red as an example.

[0068] The non-display area 2000 is provided with a source driver module 200 and a gate driver module 300. The source driver module 200 transmits a data signal to the pixel unit 100 via the data line to drive the pixel unit 100 to emit light. The gate driver module 300 transmits a gate drive signal to the pixel unit 100 via the gate line to control whether the data line transmits a data signal to the pixel unit 100. Optionally, the source driver module 200 can be arranged at the bottom relative to the display panel, and the gate driver module 300 can be arranged at the side relative to the display panel. A plurality of gate lines are uniformly arranged on the display panel along the column direction, each gate line extends along the row direction of the display panel, and one gate line controls a row of pixel units 100. A plurality of data lines are arranged on the display panel along the row direction, each data line extends along the column direction of the display panel, and two data lines jointly control a column of pixel units 100.

[0069] The source driver module 200 includes a data driver chip 210 and a plurality of multiplexing circuits. The data driver chip 210 includes a plurality of output ports, each of which is connected to a plurality of multiplexing circuits and outputs a plurality of pre-charge signals and data signals to the data lines under the control of the plurality of multiplexing circuits. For example, the data driver chip 210 includes fifty output ports (S1, S2, S3 ... S49, S50), each of which is connected to four multiplexing circuits (MUX1, MUX2, MUX3, MUX4). Take the connection of S1 to four multiplexing circuits (MUX1, MUX2, MUX3, MUX4) as an example. S1 generates four pre-charge signals and four data signals under the control of the four multiplexing circuits, and outputs the four pre-charge signals to the four data lines (D1, D2, D3, D4) respectively, and outputs the four data signals to the four data lines (D1, D2, D3, D4) respectively. Similarly, fifty output terminals (S1, S2, S3, ..., S49, S50) can generate two hundred pre-charge signals and two hundred data signals. If two data lines drive one column of pixel units 100, then one hundred columns of pixel units 100 can be driven by two hundred data lines.

[0070] The gate driver module 300 includes a plurality of gate driver units (GOAs) arranged along the column direction of the display panel. The multiple GOA units arranged along the column direction can be cascaded or non-cascaded. Each GOA unit is connected to a row of gate lines. The GOA unit generates a gate drive signal and transmits the gate drive signal to a row of pixel units 100 corresponding to the gate line through the gate line.

[0071] The source driver module 200 outputs a precharge signal before the active level section of the corresponding gate drive signal, and outputs a data signal during the active level section of the gate drive signal. That is, the multiplexing circuit controls the data driver chip 210 to output the precharge signal before the active level section of the gate drive signal. The multiplexing circuit controls the data driver chip 210 to output the data signal during the active level section of the gate drive signal.

[0072] As shown in Figures 1 to 3, in an optional embodiment, the pixel units in odd rows are arranged in a periodic sequence of the first pixel unit, the second pixel unit, the third pixel unit, and the second pixel unit; the pixel units in even rows are arranged in a periodic sequence of the third pixel unit, the second pixel unit, the first pixel unit, and the second pixel unit.

[0073] That is, the pixel units in odd rows are arranged in a periodic sequence of blue pixel units, green pixel units, red pixel units, and green pixel units, and the pixel units in even rows are arranged in a periodic sequence of red pixel units, green pixel units, blue pixel units, and green pixel units. G1, G2, ..., Ga control the first row, second row, ..., a-th row of pixel units 100, respectively, where a is an integer greater than 1. D1 and D2 control the first column, D3 and D4 control the second column, ..., D2b-1 and D2b control the b-th column of pixel units 100, where b is an integer greater than 1. The data lines of odd columns are connected to the odd-numbered pixel units 100 in the controlled columns, and the data lines of even columns are connected to the even-numbered pixel units 100 in the controlled columns.

[0074] Two adjacent rows of gate lines are one group in the gate drive module 300, and the gate drive signals of the same group of gate lines are in phase, and the gate drive signal of the next group of gate lines lags behind one phase than the gate drive signal of this group of gate lines. For example, G1 and G2 are one group, and G3 and G4 are one group... G2a-1 and G2a are the same group, and a is an integer greater than 1. The gate drive signals of the same group of gate lines are in phase, and the gate drive signal of the next group of gate lines lags behind one phase than the gate drive signal of this group of gate lines. That is, the gate drive signal of GOA2a-1 and GOA2a outputs is in phase, and the gate drive signal of G2a-1 and G2a outputs lags behind one phase of the gate drive signal of G2a-3 and G2a-2 outputs, and a is an integer greater than 1.

[0075] Each output port (S1, S2 ...) of gate driver chip 210 in source driver module 200 is all connected with four multiplexing circuits (MUX1, MUX2, MUX3, MUX4), produces four pre-charge signals and four data signals.Four pre-charge signals are one group, and four data signals are one group, and four data lines are one group.One group of data lines receives one group of pre-charge signals and one group of data signals.One group of pre-charge signals is output before the effective level section of the gate drive signal of corresponding one group of gate lines, and one group of pre-charge signals is output in the effective level section of the gate drive signal of corresponding one group of gate lines.For example, S1 is connected with MUX1, MUX2, MUX3, MUX4, produces four pre-charge signals and four data signals under the control of MUX1, MUX2, MUX3, MUX4, and four pre-charge signals are output to D1, D2, D3, D4 respectively before the effective level section of gate drive signal, and four data signals are output to D1, D2, D3, D4 respectively in the effective level section of gate drive signal. Optionally, the four precharge signals output to D1, D2, D3, and D4 are phase-synchronized, and the four data signals output to D1, D2, D3, and D4 are phase-delayed in the order of D3, D4, D2, and D1.

[0076] Specifically, S1 is connected to MUX1, MUX2, MUX3, and MUX4, and generates four pre-charge signals and four data signals under the control of MUX1, MUX2, MUX3, and MUX4. The four pre-charge signals are output to D1, D2, D3, and D4 respectively before the effective level segments of G1 and G2, and the four data signals are output to D1, D2, D3, and D4 respectively during the effective level segments of G1 and G2. Optionally, the four pre-charge signals output to D1, D2, D3, and D4 are phase-synchronized. The four data signals output to D1, D2, D3, and D4 lag in phase in the order of D3, D4, D2, and D1.

[0077] S2 is connected to MUX1, MUX2, MUX3, and MUX4, and generates four pre-charge signals and four data signals under the control of MUX1, MUX2, MUX3, and MUX4. The four pre-charge signals are output to D5, D6, D7, and D8 respectively before the effective level segments of G1 and G2, and the four data signals are output to D5, D6, D7, and D8 respectively during the effective level segments of G1 and G2. Optionally, the four pre-charge signals output to D5, D6, D7, and D8 are phase-synchronized. The four data signals output to D5, D6, D7, and D8 lag in phase in the order of D7, D8, D5, and D6.

[0078] S2n-1 is connected to MUX1, MUX2, MUX3, and MUX4, and generates four pre-charge signals and four data signals under the control of MUX1, MUX2, MUX3, and MUX4. The four pre-charge signals are output to D8n-7, D8n-6, D8n-5, and D8n-4 respectively before the effective level section of G1 and G2, and the four data signals are output to D8n-7, D8n-6, D8n-5, and D8n-4 respectively during the effective level section of G1 and G2. Optionally, the four pre-charge signals output to D8n-7, D8n-6, D8n-5, and D8n-4 are phase-synchronized. The four data signals output to D8n-7, D8n-6, D8n-5, and D8n-4 lag in phase in the order of D8n-5, D8n-4, D8n-6, and D8n-7. n is an integer greater than 1.

[0079] S2n is connected to MUX1, MUX2, MUX3, and MUX4, and generates four pre-charge signals and four data signals under the control of MUX1, MUX2, MUX3, and MUX4. The four pre-charge signals are output to D8n-3, D8n-2, D8n-1, and D8n respectively before the effective level section of G1 and G2, and the four data signals are output to D8n-3, D8n-2, D8n-1, and D8n respectively during the effective level section of G1 and G2. Optionally, the four pre-charge signals output to D8n-3, D8n-2, D8n-1, and D8n are phase-synchronized. The four data signals output to D8n-3, D8n-2, D8n-1, and D8n lag in phase in the order of D8n-1, D8n, D8n-3, and D8n-2. n is an integer greater than 1.

[0080] In this way, the scanning and emitting of the first and second rows of pixel units 100 are completed. Similarly, the pixel units 100 in other rows are scanned and emitted step by step according to the phase sequence of the GOA signal of each row.

[0081] As shown in Figures 1, 4, and 5, in an optional embodiment, the pixel cells in odd rows are arranged in a sequential periodic arrangement of a first pixel cell, a second pixel cell, and a third pixel cell. The pixel cells in even rows are arranged in a sequential periodic arrangement of a third pixel cell, a second pixel cell, and a first pixel cell. That is, the pixel cells in odd rows are arranged in a sequential periodic arrangement of a blue pixel cell, a green pixel cell, and a red pixel cell, while the pixel cells in even rows are arranged in a sequential periodic arrangement of a red pixel cell, a green pixel cell, and a blue pixel cell. G1, G2, ..., Ga control the first row, the second row, ..., the a-th row of pixel cells 100, respectively, where a is an integer greater than 1. D1 and D2 control the first column, D3 and D4 control the second column, ..., D2b-1 and D2b control the b-th column of pixel cells 100, where b is an integer greater than 1. The data lines of the odd columns are connected to the odd-row pixel cells 100 in the controlled columns, and the data lines of the even columns are connected to the even-row pixel cells 100 in the controlled columns.

[0082] Two adjacent rows of gate lines are one group in the gate drive module 300, and the gate drive signals of the same group of gate lines are in phase, and the gate drive signal of the next group of gate lines lags behind one phase than the gate drive signal of this group of gate lines. For example, G1 and G2 are one group, and G3 and G4 are one group... G2a-1 and G2a are the same group, and a is an integer greater than 1. The gate drive signals of the same group of gate lines are in phase, and the gate drive signal of the next group of gate lines lags behind one phase than the gate drive signal of this group of gate lines. That is, the gate drive signal of GOA2a-1 and GOA2a outputs is in phase, and the gate drive signal of G2a-1 and G2a outputs lags behind one phase of the gate drive signal of G2a-3 and G2a-2 outputs, and a is an integer greater than 1.

[0083] Each output port (S1, S2 ...) of the gate driver chip 210 in the source driver module 200 is connected to three multiplexing circuits (MUX1, MUX2, MUX3) to generate three pre-charge signals and three data signals. Three pre-charge signals form a group, three data signals form a group, and three data lines form a group. A group of data lines receives a group of pre-charge signals and a group of data signals. A group of pre-charge signals is output before the effective level segment of the gate drive signal of a corresponding group of gate lines, and a group of pre-charge signals is output in the effective level segment of the gate drive signal of a corresponding group of gate lines.

[0084] For example, S1 is connected to MUX1, MUX2, and MUX3, and generates three pre-charge signals and three data signals under the control of MUX1, MUX2, MUX3, and MUX4. The three pre-charge signals are output to D1, D2, and D3, respectively, before the effective level section of the gate drive signal, and the three data signals are output to D1, D2, and D3, respectively, during the effective level section of the gate drive signal. Optionally, the three pre-charge signals output to D1, D2, and D3 are phase-synchronized. The three data signals output to D1, D2, and D3 lag in phase in the order of D3, D2, and D1.

[0085] Specifically, S1 is connected to MUX1, MUX2, and MUX3, and generates three pre-charge signals and three data signals under the control of MUX1, MUX2, and MUX3. The three pre-charge signals are output to D1, D2, and D3 respectively before the effective level segments of G1 and G2, and the three data signals are output to D1, D2, and D3 respectively during the effective level segments of G1 and G2. Optionally, the three pre-charge signals output to D1, D2, and D3 are phase-synchronized. The three data signals output to D1, D2, and D3 lag in phase in the order of D3, D2, and D1.

[0086] S2 is connected to MUX1, MUX2, and MUX3, and generates three pre-charge signals and three data signals under the control of MUX1, MUX2, and MUX3. The three pre-charge signals are output to D4, D5, and D6 respectively before the active level segments of G1 and G2, and the three data signals are output to D4, D5, and D6 respectively during the active level segments of G1 and G2. Optionally, the three pre-charge signals output to D4, D5, and D6 are phase-synchronized. The three data signals output to D4, D5, and D6 lag in phase in the order of D4, D5, and D6.

[0087] S2n-1 is connected to MUX1, MUX2, and MUX3, and generates three pre-charge signals and three data signals under the control of MUX1, MUX2, and MUX3. The three pre-charge signals are output to D6n-5, D6n-4, and D6n-3 respectively before the effective level section of G1 and G2, and the three data signals are output to D6n-5, D6n-4, and D6n-3 respectively during the effective level section of G1 and G2. Optionally, the three pre-charge signals output to D6n-5, D6n-4, and D6n-3 are phase-synchronized. The three data signals output to D6n-5, D6n-4, and D6n-3 lag in phase in the order of D6n-3, D6n-4, and D6n-5. n is an integer greater than 1.

[0088] S2n is connected to MUX1, MUX2, and MUX3, and generates three pre-charge signals and three data signals under the control of MUX1, MUX2, and MUX3. The three pre-charge signals are output to D6n-2, D6n-1, and D6n respectively before the effective level section of G1 and G2, and the three data signals are output to D6n-2, D6n-1, and D6n respectively during the effective level section of G1 and G2. Optionally, the three pre-charge signals output to D6n-2, D6n-1, and D6n are phase-synchronized. The three data signals output to D6n-2, D6n-1, and D6n lag in phase in the order of D6n-2, D6n-1, and D6n. n is an integer greater than 1.

[0089] In this way, the scanning and emitting of the first and second rows of pixel units 100 are completed. Similarly, the pixel units 100 in other rows are scanned and emitted step by step according to the phase sequence of the GOA signal of each row.

[0090] As shown in Figures 1, 6 and 7, in an optional embodiment, each row of pixel units is arranged in a sequential periodic arrangement of the third pixel unit, the second pixel unit and the first pixel unit. That is, each row of pixel units is arranged in a sequential periodic arrangement of the red pixel unit, the green pixel unit and the blue pixel unit. G1, G2...Ga respectively control the first row, the second row...the a-th row of pixel units 100, where a is an integer greater than 1. D1 and D2 control the first column, D3 and D4 control the second column...D2b-1 and D2b control the b-th column of pixel units 100, where b is an integer greater than 1. The data lines of the odd columns are connected to the odd-numbered row pixel units 100 in the controlled columns, and the data lines of the even columns are connected to the even-numbered row pixel units 100 in the controlled columns.

[0091] In the gate drive module 300, the gate drive signal of the next row of gate lines lags behind the gate drive signal of the current row of gate lines by half a phase. For example, the gate drive signal of G2 lags behind the gate drive signal of G1 by half a phase, and the gate drive signal of Ga lags behind the gate drive signal of Ga-1 by half a phase. That is, the gate drive signal output by GOAa lags behind the gate drive signal output by GOAa-1 by half a phase, and the first half of the effective level segment of the GOAa output gate drive signal overlaps with the second half of the effective level segment of the GOAa-1 output gate drive signal, where a is an integer greater than 1.

[0092] Each output port (S1, S2, ...) of the gate driver chip 210 in the source driver module 200 is connected to six multiplexing circuits (MUX1, MUX2, MUX3, MUX4, MUX5, MUX6) to generate six pre-charge signals and six data signals. Three of the six pre-charge signals form a group, and three of the six data signals form a group, with three data lines forming a group. One of the two adjacent groups of data lines receives a set of pre-charge signals and data signals, and the other group of data lines receives another set of pre-charge signals and data signals. One group of data signals is output in the first half of the phase corresponding to the effective level segment of a group of gate drive signals, and the other group of data signals is output in the second half of the phase corresponding to the effective level segment of a group of gate drive signals.

[0093] For example, S1 is connected to MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, and generates six pre-charge signals and six data signals under the control of MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6. Of the six pre-charge signals, the three pre-charge signals generated by MUX1, MUX3, and MUX5 form a group, and the three pre-charge signals generated by MUX2, MUX4, and MUX6 form a group. Of the six data signals, the three data signals generated by MUX1, MUX3, and MUX5 form a group, and the three data signals generated by MUX2, MUX4, and MUX6 form a group. Of two adjacent groups of data lines, one group receives a set of pre-charge signals and data signals, and the other group receives a different set of pre-charge signals and data signals. One group of data signals is output during the first half of the phase corresponding to the active level segment of the gate drive signal, and the other group of data signals is output during the second half of the phase corresponding to the active level segment of the gate drive signal. One set of pre-charge signals is output to one set of data lines before the active level section of the gate drive signal, and the two sets of data signals are output to the two sets of data lines respectively during the active level section of the gate drive signal. Optionally, the phases of the pre-charge signals of the same set of the six pre-charge signals are synchronized. The phases of the six data signals lag in sequence.

[0094] Specifically, S1 is connected to MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, and generates six pre-charge signals and six data signals under the control of MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6. Under the control of MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, six pre-charge signals and six data signals are output to D1, D2, D3, D4, D5, and D6, respectively. The pre-charge signals and data signals generated by MUX1, MUX3, and MUX5 form the first group, and the pre-charge signals and data signals generated by MUX2, MUX4, and MUX6 form the second group.

[0095] The pre-charge signal of the first group is output to D1, D2, and D3 respectively before the effective level segment of G1, and the data signal of the first group is output to D1, D3, and D5 respectively during the effective level segment of G1. Specifically, the data signal of the first group is output to D1, D3, and D5 respectively during the first half of the effective level segment of G1. Optionally, the three pre-charge signals output to D1, D3, and D5 are phase-synchronized. The three data signals output to D1, D3, and D5 are phase-lagged in the order of D3, D1, and D5.

[0096] The pre-charge signal of the second group is output to D2, D4, and D6 respectively in the effective level segment of G1, and the data signal of the second group is output to D2, D4, and D6 respectively in the effective level segment of G1. Specifically, the data signal of the second group is output to D2, D4, and D6 respectively in the second half of the effective level segment of G1, and the pre-charge signal of the second group is output to D2, D4, and D6 respectively between the data signal of the first group and the data signal of the second group. Optionally, the three pre-charge signals output to D2, D4, and D6 are phase-synchronized. The three data signals output to D2, D4, and D6 are phase-lagged in the order of D4, D2, and D6.

[0097] S2 is connected to MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, and generates six pre-charge signals and six data signals under the control of MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6. Under the control of MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, six pre-charge signals and six data signals are output sequentially to D7, D8, D9, D10, D11, and D12, respectively. The pre-charge signals and data signals generated by MUX1, MUX3, and MUX5 form the first group, while the pre-charge signals and data signals generated by MUX2, MUX4, and MUX6 form the second group.

[0098] The pre-charge signal of the first group is output to D7, D9, and D11 respectively before the effective level section of G1, and the data signal of the first group is output to D7, D9, and D11 respectively during the effective level section of G1. Specifically, the data signal of the first group is output to D7, D9, and D11 respectively during the first half of the effective level section of G1. Optionally, the three pre-charge signals output to D7, D9, and D11 are phase-synchronized. The three data signals output to D7, D9, and D11 are phase-lagged in the order of D9, D7, and D11.

[0099] The pre-charge signal of the second group is output to D8, D10, and D12 respectively in the effective level segment of G1, and the data signal of the second group is output to D8, D10, and D12 respectively in the effective level segment of G1. Specifically, the data signal of the second group is output to D8, D10, and D12 respectively in the second half of the effective level segment of G1, and the pre-charge signal of the second group is output to D8, D10, and D12 respectively between the data signal of the first group and the data signal of the second group. Optionally, the three pre-charge signals output to D8, D10, and D12 are phase-synchronized. The three data signals output to D8, D10, and D12 are phase-lagged in the order of D10, D8, and D12.

[0100] Sn is connected to MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, and generates six pre-charge signals and six data signals under the control of MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6. Under the control of MUX1, MUX2, MUX3, MUX4, MUX5, and MUX6, six pre-charge signals and six data signals are sequentially output to D6n-5, D6n-4, D6n-3, D6n-2, D6n-1, and D6n, respectively. The pre-charge signals and data signals generated by MUX1, MUX3, and MUX5 form the first group, while the pre-charge signals and data signals generated by MUX2, MUX4, and MUX6 form the second group. n is an integer greater than 1.

[0101] The pre-charge signal of the first group is output to D6n-5, D6n-3, and D6n-1 respectively before the effective level segment of G1, and the data signal of the first group is output to D6n-5, D6n-3, and D6n-1 respectively during the effective level segment of G1. Specifically, the data signal of the first group is output to D6n-5, D6n-3, and D6n-1 respectively during the first half of the effective level segment of G1. Optionally, the three pre-charge signals output to D6n-5, D6n-3, and D6n-1 are phase-synchronized. The three data signals output to D6n-5, D6n-3, and D6n-1 lag in phase in the order of D6n-3, D6n-5, and D6n-1.

[0102] The pre-charge signal of the second group is output to D6n-4, D6n-2, and D6n respectively in the effective level segment of G1, and the data signal of the second group is output to D6n-4, D6n-2, and D6n respectively in the effective level segment of G1. Specifically, the data signal of the second group is output to D6n-4, D6n-2, and D6n respectively in the second half of the effective level segment of G1, and the pre-charge signal of the second group is output to D6n-4, D6n-2, and D6n respectively between the data signal of the first group and the data signal of the second group. Optionally, the three pre-charge signals output to D6n-4, D6n-2, and D6n are phase-synchronized. The three data signals output to D6n-4, D6n-2, and D6n are phase-lagged in the order of D6n-2, D6n-4, and D6n.

[0103] In this way, the scanning and luminescence of the first row of pixel units 100 are completed. Since the first half of the effective level segment of the gate drive signal output by GOAa overlaps with the second half of the effective level segment of the gate drive signal output by GOAa-1, a is an integer greater than 1. Therefore, the first group of signals generated by S1 are output to D1, D3, and D5 respectively in the first half of the effective level segment of G2n-1, and the second group of data signals generated by S1 are output to D2, D4, and D6 respectively in the second half of the effective level segment of G2n-1. The first group of signals generated by S1 are output to D1, D3, and D5 respectively in the second half of the effective level segment of G2n, and the second group of data signals generated by S1 are output to D2, D4, and D6 respectively in the first half of the effective level segment of G2n. Similarly, the pixel units 100 of other rows are scanned and illuminated step by step according to the phase sequence of the GOA signals of each row.

[0104] The present application also discloses a method for driving a display panel, wherein the display panel comprises:

[0105] A plurality of pixel units, wherein the plurality of pixel units are arranged in an array on the display panel;

[0106] A source driver module, the source driver module comprising a data driver chip and a plurality of multiplexing circuits; the data driver chip comprising a plurality of output ports, each of the output ports being connected to the plurality of multiplexing circuits and outputting signals to data lines under the control of the plurality of multiplexing circuits; two data lines controlling a column of pixel units; one of the two data lines controlling the pixel units in odd rows, and the other controlling the pixel units in even rows;

[0107] A gate driving module, the gate driving module outputs a gate driving signal to the gate lines; a row of the gate lines controls a row of the pixel units;

[0108] The driving method includes:

[0109] Each of the output ports outputs a plurality of pre-charge signals to the data lines under the control of the plurality of multiplexing circuits, wherein the phases of the plurality of pre-charge signals are located before the effective level segment of the corresponding gate driving signal;

[0110] Each of the output ports outputs a plurality of data signals to the data lines under the control of a plurality of the multiplexing circuits. The phases of the plurality of data signals are located in the effective level section corresponding to the gate driving signal.

[0111] Optionally, two adjacent rows of gate lines form a group, the gate drive signals controlling the gate lines in the same group are in phase, and the gate drive signals controlling the next group of gate lines lag behind the gate drive signals of the current group by one phase;

[0112] Each of the output ports is connected to four of the multiplexing circuits, and the four multiplexing circuits control the output ports to generate four pre-charge signals and four data signals; the four pre-charge signals form a group, the four data signals form a group, and the four data lines form a group;

[0113] Control a group of the data lines to receive a group of the pre-charge signals and a group of the data signals; control a group of the pre-charge signals to be output before the effective level segment of the gate drive signal corresponding to a group of the gate lines, and control a group of the data signals to be output in the effective level segment of the gate drive signal corresponding to a group of the gate lines.

[0114] Optionally, two adjacent rows of gate lines form a group, the gate drive signals controlling the gate lines in the same group are in phase, and the gate drive signals controlling the next group of gate lines lag behind the gate drive signals of the current group by one phase;

[0115] Each of the output ports is connected to three of the multiplexing circuits, and the three multiplexing circuits control the output ports to generate three of the pre-charge signals and three of the data signals; the three pre-charge signals form a group, the three data signals form a group, and the three data lines form a group;

[0116] Control two adjacent groups of data lines to receive the same group of pre-charge signals and the same group of data signals; control one group of pre-charge signals to be output before the effective level segment of the gate drive signal of the corresponding group of gate lines, and control one group of data signals to be output in the effective level segment of the gate drive signal of the corresponding group of gate lines.

[0117] Optionally, the gate driving signal for controlling the gate lines in the next row lags behind the gate driving signal for the gate lines in the current row by half a phase;

[0118] Each of the output ports is connected to six of the multiplexing circuits, and the six multiplexing circuits control the output ports to generate six pre-charge signals and six data signals, wherein three of the six pre-charge signals form a group, and three of the six data signals form a group, and three data lines form a group;

[0119] Controlling one of the two adjacent groups of data lines to receive one group of the pre-charge signal and the data signal, and the other group of data lines to receive the other group of the pre-charge signal and the data signal;

[0120] One group of the data signals is controlled to be output in the first half phase of the effective level segment corresponding to one group of the gate drive signals, and another group of the data signals is controlled to be output in the second half phase of the effective level segment corresponding to one group of the gate drive signals.

[0121] The present application also discloses a display device, which includes the above-mentioned display panel.

[0122] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0123] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0124] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. An integrated circuit unit, characterized in that: include: A first control subcircuit is connected to the second clock signal terminal, the first power signal terminal and the first node, and controls the first node to an effective potential according to the second clock signal; a second control subcircuit connected to the first node, the second clock signal terminal, the third clock signal terminal, the fifth power signal terminal, and a plurality of strobe signal terminals, and controlling the first node to an inactive potential according to the third clock signal and the signals of the plurality of strobe signal terminals; a third control subcircuit connected to the first node, the second node, the third node, the fourth node, the third clock signal terminal, the fourth clock signal terminal, the second power signal terminal, the fifth power signal terminal, and the sixth power signal terminal, and controlling the second node and the third node to switch between a valid potential and an invalid potential; a fourth control subcircuit connected to the first node, the second node, the third node, the fourth node, the fourth clock signal terminal, the first power signal terminal, and the fifth power signal terminal, and controlling the fourth node to switch between an effective potential and an ineffective potential; The output sub-circuit is connected to the second node, the fourth node, the first clock signal terminal, the fourth power signal terminal and the output signal terminal, and outputs a driving signal under the control of the second node and the fourth node.

2. The integrated circuit unit according to claim 1, wherein: The integrated circuit unit further includes a reset subcircuit connected to the reset signal terminal, the first node, the second node, and the fourth control subcircuit, and resets the first node, the second node, and the fourth node.

3. The integrated circuit unit according to claim 1, wherein: The third control subcircuit includes a second node control module, and the second node control module includes: a twenty-second transistor, wherein a first electrode of the twenty-second transistor is connected to the second power signal terminal, a second electrode of the twenty-second transistor is connected to the second node, and a control electrode of the twenty-second transistor is connected to the third clock signal terminal; a twenty-third transistor, wherein a first electrode of the twenty-third transistor is connected to the fifth power signal terminal, a second electrode of the twenty-third transistor is connected to the second node, and a first control electrode of the twenty-third transistor is connected to the fourth node; A fourteenth transistor and a fifteenth transistor are connected in series between the fifth power signal terminal and the second node, a first control electrode of the fourteenth transistor is connected to the first node, and a first control electrode of the fifteenth transistor is connected to the fourth clock signal terminal.

4. The integrated circuit unit according to claim 3, wherein: The fourteenth transistor, the fifteenth transistor, and the twenty-third transistor have a multi-control electrode structure, and second control electrodes of the fourteenth transistor, the fifteenth transistor, and the twenty-third transistor are all connected to the third node.

5. The integrated circuit unit according to claim 1, wherein: The third control subcircuit includes a third node control module, and the third node control module includes: a twenty-first transistor, wherein a first electrode of the twenty-first transistor is connected to the third node, and a second electrode of the twenty-first transistor is connected to the sixth power signal terminal; a second energy storage unit connected between the third node and the fourth node; A nineteenth transistor and a twentieth transistor are connected in series between the third node and the second power signal terminal, the control electrode of the nineteenth transistor is connected to the first node, and the control electrode of the twentieth transistor is connected to the fourth clock signal terminal.

6. The integrated circuit unit according to claim 1, wherein: The third control subcircuit includes a third node control module, and the third node in the third node control module is directly connected to the sixth power signal terminal.

7. The integrated circuit unit according to claim 1, wherein: The second control subcircuit includes a number of parallel-connected gating transistors, the number of which is less than or equal to a number of the gating signal terminals, and the control electrode of each gating transistor is connected to one of the gating signal terminals.

8. The integrated circuit unit according to claim 7, wherein: The first electrodes of the plurality of parallel-connected selection transistors are connected to the third clock signal terminal, and the second electrodes are connected to the control electrode of the twelfth transistor to control the conduction between the second clock signal terminal and the first node.

9. The integrated circuit unit according to claim 8, characterized in that Among the selection signal terminals connected to the selection transistors, the pulse width of the selection signal at the nth selection signal terminal is twice the pulse width of the selection signal at the n-1th selection signal terminal.

10. The integrated circuit unit according to claim 9, characterized in that The high level width and the low level width of the selection signal in one cycle of each selection signal terminal are equal.

11. The integrated circuit unit according to claim 2, wherein: The fourth control subcircuit includes: a twenty-seventh transistor, wherein a first electrode of the twenty-seventh transistor is connected to the fifth power signal terminal, a second electrode of the twenty-seventh transistor is connected to the fourth node, and a first control electrode of the twenty-seventh transistor is connected to the third node; A twenty-fourth transistor and a twenty-sixth transistor are connected in series between the fourth node and the first power signal terminal, the control electrode of the twenty-fourth transistor is connected to the fourth clock signal terminal, and the control electrode of the twenty-sixth transistor is connected to the first node.

12. The integrated circuit unit according to claim 11, characterized in that The twenty-seventh transistor has a multi-control electrode structure, and the fourth control sub-circuit further includes: a thirty-third transistor, a first electrode of the thirty-third transistor being connected to the reset signal terminal, and a second electrode of the thirty-third transistor being connected to the fifth node; a fifth energy storage unit connected between the second node and the fifth node; A second control electrode of the twenty-seventh transistor is connected to the fifth node.

13. The integrated circuit unit according to claim 12, wherein: The fourth control subcircuit further includes: The twenty-ninth transistor has a multi-control electrode structure, the first electrode of the twenty-ninth transistor is connected to the fifth power supply signal terminal, the second electrode of the twenty-ninth transistor is connected to the first node, the first control electrode of the twenty-ninth transistor is connected to the third clock signal terminal, and the second control electrode of the twenty-ninth transistor is connected to the fifth node.

14. A gate drive circuit, characterized in that: It comprises a plurality of integrated circuit unit groups, wherein the integrated circuit unit group comprises at least one integrated circuit unit as described in any one of claims 1 to 13, the number of the selection signal terminals is twice the number of the selection transistors, and the selection signal terminals comprise a plurality of positive selection signal terminals and a plurality of negative selection signal terminals whose signals are opposite to those of the positive selection signal terminals.

15. The gate driving circuit according to claim 14, wherein: The integrated circuit unit group includes four integrated circuit units. The integrated circuit units in the same group are connected to the selected communication terminal in the same manner, and the integrated circuit units in the same group are connected to the clock signal terminals in different orders.

16. The gate driving circuit according to claim 15, wherein: Different groups of the integrated circuit units have different connections with the selection signal terminal.

17. A display panel, characterized in that: Comprising the gate drive circuit as described in any one of claims 14-16.

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