Display panel and display apparatus

Abstract

A display panel, comprising a display area (AA), a frame area (BB), and a pixel driving circuit (Pix) located in the display area (AA). The display panel further comprises: a base substrate (90) and a second source / drain layer, the second source / drain layer being located on one side of the base substrate (90), the second source / drain layer comprising a data line (Da) and at least one electrostatic transmission line (LE), the data line (Da) being used for providing a data signal to the pixel driving circuit (Pix), the data line (Da) being located in the display area (AA), the electrostatic transmission line (LE) being used for transmitting an electrostatic charge on the display panel, and the electrostatic transmission line (LE) being located in the frame area (BB). The display panel has high safety and stability. Also provided is a display apparatus comprising the display panel.

Description

Display panel, display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202410141239.4, filed on January 31, 2024, entitled “Display Panel, Display Device.” The disclosure of the aforementioned Chinese patent application is hereby incorporated by reference in its entirety as part of this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] In the related art, static electricity on the display panel can easily break down transistors in the pixel driving circuit, thereby causing abnormal display of the display panel.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes a display area, a frame area, and a pixel driving circuit located in the display area, and the display panel also includes: a base substrate and a second source and drain layer; the second source and drain layer is located on one side of the base substrate, the second source and drain layer includes a data line and at least one electrostatic transmission line, the data line is used to provide a data signal to the pixel driving circuit, the data line is located in the display area, the electrostatic transmission line is used to transmit electrostatic charge on the display panel, and the electrostatic transmission line is located in the frame area.

[0007] In an exemplary embodiment of the present disclosure, the display panel further includes: a signal line, wherein the signal line is located between the base substrate and the second source / drain layer, and the static electricity transmission line is connected to the signal line through a via hole.

[0008] In an exemplary embodiment of the present disclosure, the signal line includes at least one of a power line and an initial signal line; the power line is used to provide a power signal to the pixel driving circuit, and the initial signal line is used to provide an initial signal to the pixel driving circuit.

[0009] In an exemplary embodiment of the present disclosure, the frame area includes a power line integration area, and the display panel also includes: a first source and drain layer, the first source and drain layer is located between the base substrate and the second source and drain layer, the first source and drain layer includes: multiple first power lines and power access lines, multiple first power lines are located in the display area, the first power lines are used to provide high-level signals to the pixel driving circuit, the orthographic projection of the first power lines on the base substrate extends along the second direction and is distributed at intervals along the first direction, and the first direction and the second direction intersect; the power access line is located in the power line integration area, the orthographic projection of the power access line on the base substrate extends along the first direction, and the power access line connects multiple first power lines; at least one of the electrostatic transmission lines includes a first electrostatic transmission line, the orthographic projection of the first electrostatic transmission line on the base substrate and the orthographic projection of the power access line on the base substrate at least partially overlap, and the first electrostatic transmission line is connected to the power access line through a via.

[0010] In an exemplary embodiment of the present disclosure, the display panel further includes a virtual pixel driving circuit, the border area includes a virtual pixel area, and the virtual pixel driving circuit is located in the virtual pixel area; at least one of the electrostatic transmission lines includes at least one second electrostatic transmission line, and the second electrostatic transmission line is located in the virtual pixel area.

[0011] In an exemplary embodiment of the present disclosure, the display panel further includes: a first source-drain layer, the first source-drain layer being located between the base substrate and the second source-drain layer, the first source-drain layer including: a plurality of virtual power lines, the plurality of virtual power lines being located in the virtual pixel area, the orthographic projections of the virtual power lines on the base substrate extending along a second direction and being spaced apart along a first direction, the first direction and the second direction intersecting; the second electrostatic transmission line being connected to the virtual power lines through a via.

[0012] In an exemplary embodiment of the present disclosure, the first source and drain layer also includes: a virtual power connection line, the virtual power connection line is located in the virtual pixel area, the orthographic projection of the virtual power connection line on the substrate extends along the first direction and intersects with the orthographic projection of the virtual power line on the substrate; the orthographic projection of the second electrostatic transmission line on the substrate intersects with the orthographic projection of the virtual power connection line on the substrate, and the second electrostatic transmission line is directly connected to the virtual power connection line through a via.

[0013] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes multiple transistors, and the first source and drain layer further includes: one or more bridge portions, which are connected to the transistors through vias; wherein at least some of the bridge portions are connected to the virtual power line.

[0014] In an exemplary embodiment of the present disclosure, at least one of the second electrostatic transmission lines includes: a plurality of first sub-electrostatic transmission lines, the orthographic projections of the first sub-electrostatic transmission lines on the substrate extending along the second direction and spaced apart along the first direction, and the first direction and the second direction intersect.

[0015] In an exemplary embodiment of the present disclosure, at least one of the second electrostatic transmission lines further includes: at least one second sub-electrostatic transmission line, the orthographic projection of at least one of the second sub-electrostatic transmission lines on the base substrate extending along the first direction and spaced apart along the second direction; the orthographic projection of the second sub-electrostatic transmission line on the base substrate intersects with the orthographic projection of the first sub-electrostatic transmission line on the base substrate.

[0016] In an exemplary embodiment of the present disclosure, at least one of the electrostatic transmission lines includes a plurality of the second electrostatic transmission lines, and the plurality of the second electrostatic transmission lines form a grid structure, and the hollow shape of the grid structure includes one or more of a circle, a polygon, and an irregular shape.

[0017] In an exemplary embodiment of the present disclosure, the orthographic projection of the data line on the base substrate extends along a second direction, and the display panel further includes a binding area, the binding area, the display area, and the frame area are distributed in the second direction, and the display area is located between the binding area and the frame area.

[0018] In an exemplary embodiment of the present disclosure, the border area includes a power line integration area and a dummy pixel area, and the power line integration area is located between the dummy pixel area and the display area.

[0019] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes: a driving transistor and a fourth transistor. A first electrode of the fourth transistor is connected to a data line, and a second electrode is connected to the first electrode of the driving transistor.

[0020] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0021] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0023] FIG1 is a schematic diagram of a circuit structure of a pixel driving circuit in an exemplary embodiment of a display panel disclosed herein;

[0024] FIG2 is a timing diagram of signals at each node in a driving method of the pixel driving circuit shown in FIG1 ;

[0025] FIG3 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0026] FIG4 is a structural diagram of the display area in the display panel shown in FIG3 ;

[0027] FIG5 is a structural diagram of the first active layer in FIG4 ;

[0028] FIG6 is a structural diagram of the first gate layer in FIG4 ;

[0029] FIG7 is a structural diagram of the second gate layer in FIG4 ;

[0030] FIG8 is a structural diagram of the first source and drain layer in FIG4 ;

[0031] FIG9 is a structural diagram of the second source and drain layer in FIG4 ;

[0032] FIG10 is a structural diagram of the first active layer and the first gate layer in FIG4 ;

[0033] FIG11 is a structural layout diagram of the first active layer, the first gate layer, and the second gate layer in FIG4 ;

[0034] FIG12 is a structural layout diagram of the first active layer, the first gate layer, the second gate layer, and the first source and drain layer in FIG4 ;

[0035] FIG13 is a partial cross-sectional view of the display panel shown in FIG4 taken along dotted line EE;

[0036] FIG14 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0037] FIG15 is a schematic structural diagram of a local area D of the display panel shown in FIG14 ;

[0038] FIG16 is a schematic structural diagram of another exemplary embodiment of a display panel according to the present disclosure. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0040] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0041] As shown in Figure 1, a circuit structure diagram of a pixel driving circuit in an exemplary embodiment of a display panel of the present disclosure is shown. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first transistor T1 has a first electrode connected to the first initial signal terminal Vinit1, a second electrode connected to the node N, and a gate connected to the first reset signal terminal Re1. The second transistor T2 has a first electrode connected to the gate of the driving transistor T3, a second electrode connected to the second electrode of the driving transistor T3, and a gate connected to the first gate drive signal terminal G1. The gate of the driving transistor T3 is connected to the node N. The fourth transistor T4 has a first electrode connected to the data signal terminal Da, a second electrode connected to the first electrode of the driving transistor T3, and a gate connected to the first gate drive signal terminal G1. The fifth transistor T5 has a first electrode connected to the first power supply terminal VDD, a second electrode connected to the first electrode of the driving transistor T3, and a gate connected to the enable signal terminal EM. The sixth transistor T6 has a first electrode connected to the second electrode of the driving transistor T3, and a gate connected to the enable signal terminal EM. The seventh transistor T7 has a first electrode connected to the second initial signal terminal Vinit2, a second electrode connected to the second electrode of the sixth transistor T6, and a gate connected to the second reset signal terminal Re2. The first electrode of the capacitor C is connected to the gate of the driving transistor T3, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit OLED and is used to drive the light-emitting unit OLED to emit light. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit OLED can be connected to the second power supply terminal VSS. The first power supply terminal VDD is a high-level power supply terminal, and the second power supply terminal VSS is a low-level power supply terminal. The first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors.

[0042] As shown in Figure 2, it is a timing diagram of the signals at each node in a driving method of the pixel driving circuit shown in Figure 1. Among them, G1 represents the timing of the signal at the first gate driving signal terminal G1, Re1 represents the timing of the signal at the first reset signal terminal Re1, Re2 represents the timing of the signal at the second reset signal terminal Re2, EM represents the timing of the signal at the enable signal terminal EM, and Da represents the timing of the signal at the data signal terminal Da. The driving method of the pixel driving circuit may include a reset phase t1, a data writing phase t2, and a light-emitting phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N. In the data writing phase t2: the second reset signal terminal Re2 and the first gate drive signal terminal G1 output a low-level signal, the fourth transistor T4, the second transistor T2, and the seventh transistor T7 are turned on, and at the same time, the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. The second initial signal terminal Vinit2 inputs a second initial signal to the second electrode of the sixth transistor T6. In the light-emitting phase t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth at the node N. The output current I of the driving transistor in the pixel driving circuit of the present disclosure = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 Where μ is carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driver transistor channel; L is the length of the driver transistor channel; Vgs is the gate-source voltage difference of the driver transistor; and Vth is the threshold voltage of the driver transistor. This pixel driver circuit can avoid the influence of the driver transistor threshold on its output current.

[0043] FIG3 is a schematic structural diagram of an exemplary embodiment of a display panel according to the present disclosure. The display panel may include a display area AA, a border area BB, and a plurality of pixel driving circuits as shown in FIG1 located in the display area AA. The plurality of pixel driving circuits may be arranged in an array along a first direction X and a second direction Y, where the first direction X and the second direction Y intersect. For example, the first direction X is a row direction, and the second direction is a column direction. The display panel may also include a base substrate, an active layer, a first gate layer, a second gate layer, a first source and drain layer, and a second source and drain layer, stacked in sequence, with an insulating layer disposed between the aforementioned structural layers. Among them, part of the structure of the active layer can be used to form the channel region of the transistor in the pixel driving circuit; part of the structure of the first gate layer can be used to form the gate of the transistor in the pixel driving circuit; part of the structure of the second gate layer can be used to form the second electrode of the capacitor in the pixel driving circuit; the first source and drain layer includes multiple bridge portions and a first power line, the bridge portion is used to connect the transistor in the pixel driving circuit through a via, for example, the bridge portion can be connected to the source, drain, or gate of the transistor through a via, the first power line is used to provide a high-level power signal to the pixel driving circuit, for example, the first power line can be used to provide the first power terminal in Figure 1; at least part of the structure of the second source and drain layer is used to form a data line, and the data line is used to provide a data signal to the data signal terminal of the pixel driving circuit.

[0044] For example, as shown in Figures 4-12, Figure 4 is the structural layout of the display area in the display panel shown in Figure 3, Figure 5 is the structural layout of the first active layer in Figure 4, Figure 6 is the structural layout of the first gate layer in Figure 4, Figure 7 is the structural layout of the second gate layer in Figure 4, Figure 8 is the structural layout of the first source and drain layer in Figure 4, Figure 9 is the structural layout of the second source and drain layer in Figure 4, Figure 10 is the structural layout of the first active layer and the first gate layer in Figure 4, Figure 11 is the structural layout of the first active layer, the first gate layer, and the second gate layer in Figure 4, and Figure 12 is the structural layout of the first active layer, the first gate layer, the second gate layer, and the first source and drain layer in Figure 4.

[0045] As shown in Figures 4, 5, and 10, the first active layer may include a first active portion 71, a second active portion 72, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The first active portion 71 is used to form the channel region of the first transistor T1, the second active portion 72 is used to form the channel region of the second transistor T2, the third active portion 73 is used to form the channel region of the driving transistor T3, the fourth active portion 74 is used to form the channel region of the fourth transistor T4, the fifth active portion 75 is used to form the channel region of the fifth transistor T5, the sixth active portion 76 is used to form the channel region of the sixth transistor T6, and the seventh active portion 77 is used to form the channel region of the seventh transistor T7. The first active portion 71 includes a fourth sub-active portion 714 and a fifth sub-active portion 715, and the second active portion 72 includes a first sub-active portion 721 and a second sub-active portion 722. The first active layer may further include a sixth sub-active portion 716 connected between the fourth sub-active portion 714 and the fifth sub-active portion 715, a third sub-active portion 723 connected between the first sub-active portion 721 and the second sub-active portion 722, an eighth active portion 78 connected between the second active portion 72 and the first active portion 71, a ninth active portion 79 connected to the side of the fourth active portion 74 away from the third active portion 73, a tenth active portion 710 connected to the side of the first active portion 71 away from the second active portion 72, an eleventh active portion 711 connected between the sixth active portion 76 and the seventh active portion 77, a twelfth active portion 712 connected to the side of the fifth active portion 75 away from the third active portion 73, and a thirteenth active portion 713 connected to the side of the seventh active portion 77 away from the sixth active portion 76. The first active layer may be formed of polysilicon material. Accordingly, the first transistor T1 , the second transistor T2 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.

[0046] As shown in Figures 4, 6, and 10, the first gate layer may include: a first reset signal line Re1, a second reset signal line Re2, a first gate line G1, an enable signal line EM, and a first conductive portion 11. The first reset signal line Re1 is used to provide the first reset signal terminal in Figure 1, the second reset signal line Re2 is used to provide the second reset signal terminal in Figure 1, the first gate line G1 is used to provide the first gate drive signal terminal in Figure 1, and the enable signal line EM is used to provide the enable signal terminal in Figure 1. The orthographic projection of the first reset signal line Re1 on the base substrate may extend along the first direction X and overlap the orthographic projection of the first active portion 71 on the base substrate. Part of the first reset signal line Re1 forms the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the base substrate may extend along the first direction X and overlap the orthographic projection of the seventh active portion 77 on the base substrate. Part of the second reset signal line Re2 forms the gate of the seventh transistor T7. The orthographic projection of the enable signal line EM on the substrate can extend along the first direction X and overlap the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. A portion of the structure of the enable signal line EM is used to form the gate of the fifth transistor T5, while another portion of the structure of the enable signal line EM is used to form the gate of the sixth transistor T6. The orthographic projection of the first gate line G1 on the substrate extends along the first direction X and overlaps the orthographic projection of the second active portion 72 and the orthographic projection of the fourth active portion 74 on the substrate. A portion of the structure of the first gate line G1 is used to form the gate of the second transistor T2, while another portion of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 is used to form the gate of the drive transistor T3. The first conductive portion 11 can also serve as the first electrode of the capacitor C. Among them, the orthographic projection of the first conductive portion 11 on the substrate can be located between the orthographic projection of the first gate line G1 on the substrate and the orthographic projection of the enable signal line EM on the substrate. The orthographic projection of the first reset signal line Re1 on the substrate can be located on a side of the orthographic projection of the first gate line G1 on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. The orthographic projection of the second reset signal line Re2 on the substrate can be located on a side of the orthographic projection of the enable signal line EM on the substrate away from the orthographic projection of the first conductive portion 11 on the substrate. In adjacent rows of pixel driving circuits, the second reset signal line Re2 in the pixel driving circuit of the previous row can be shared as the first reset signal line Re1 in the pixel driving circuit of this row. This setting can reduce the size of the pixel driving circuit in the second direction Y.In addition, the display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0047] As shown in Figures 4, 7, and 11, the second gate layer may include a first initial signal line Vinit1, a second initial signal line Vinit2, a second conductive portion 22, and a third conductive portion 23. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 1, and the second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 1. The orthographic projection of the first initial signal line Vinit1 on the base substrate and the orthographic projection of the second initial signal line Vinit2 on the base substrate can both extend along the first direction X. The orthographic projection of the third conductive portion 23 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the third conductive portion 23 can be used to form the second electrode of the capacitor C, wherein a plurality of third conductive portions 23 distributed in the first direction X can be connected in sequence. In adjacent rows of pixel driving circuits, the orthographic projection of the first initial signal line Vinit1 in the pixel driving circuits of the next row on the substrate can be located between the orthographic projection of the second initial signal line Vinit2 in the pixel driving circuits of the current row on the substrate and the orthographic projection of the second reset signal line Re2 in the pixel driving circuits of the current row on the substrate. This arrangement can further reduce the size of the pixel driving circuit in the second direction. The second conductive portion 22 can include a third sub-conductive portion 223, the orthographic projection of the third sub-conductive portion 223 on the substrate at least partially overlapping with the orthographic projection of the third sub-active portion 723 on the substrate. The second conductive portion 22 can be connected to a stable voltage source, and the third sub-conductive portion 223 can stabilize the third sub-active portion 723, thereby alleviating the problem of leakage to the source and drain of the second transistor T2 caused by voltage changes in the third sub-active portion 723. The orthographic projection of the first initial signal line Vinit1 on the substrate can at least partially overlap with the orthographic projection of the sixth sub-active portion 716 in the pixel driving circuit of this row on the substrate. The first initial signal line Vinit1 can stabilize the voltage of the sixth sub-active portion 716, thereby improving the problem of leakage to the source and drain of the first transistor T1 caused by the voltage change of the sixth sub-active portion 716.

[0048] As shown in Figures 4, 8, and 12, the first source and drain layer may include a first power line VDD and multiple bridge portions, and the multiple bridge portions may include a fifth bridge portion 35, a sixth bridge portion 36, a seventh bridge portion 37, an eighth bridge portion 38, and a ninth bridge portion 39. The first power line VDD may be used to provide a first power supply terminal in the pixel driving circuit shown in Figure 1. The orthographic projection of the first power line VDD on the substrate may extend along the second direction Y. The first power line VDD may be connected to the second conductive portion 22 through a via H to provide a stable voltage source to the second conductive portion 22. It should be understood that in other exemplary embodiments, a stable voltage source may also be provided to the second conductive portion 22 through other signal lines. For example, a stable voltage source may be provided to the second conductive portion 22 through a first initial signal line Vinit1 and a second initial signal line Vinit2. The first power line VDD may also be connected to the third conductive portion 23 through a via to connect the second electrode of the capacitor and the first power supply terminal. The first power line VDD can form a grid structure with the third conductive portion 23 connected in the first direction X. This arrangement can reduce the voltage drop caused by the resistance of the first power line VDD itself. The first power line VDD can also be connected to the twelfth active portion 712 through a via to connect the first electrode of the fifth transistor T5 and the first power supply terminal. The fifth bridge portion 35 can be connected to the first conductive portion 11 and the eighth active portion 78 through vias to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2. As shown in Figure 7, an opening 231 can be provided on the third conductive portion 23. The orthographic projection of the via connecting the fifth bridge portion 35 and the first conductive portion 11 on the substrate can be located within the orthographic projection of the opening 231 on the substrate to avoid the via being connected to the third conductive portion 23. The sixth bridge portion 36 can be connected to the ninth active portion 79 through a via to connect the first electrode of the fourth transistor T4. The seventh bridge portion 37 can be connected to the thirteenth active portion 713 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode and the second initial signal terminal of the seventh transistor. The eighth bridge portion 38 can be connected to the tenth active portion 710 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode and the first initial signal terminal of the first transistor T1. The ninth bridge portion 39 can be connected to the eleventh active portion 711 through a via, to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0049] As shown in Figures 4 and 9, the second source-drain layer may include a data line Da and a tenth bridge portion 410. The data line Da is used to provide a data signal terminal for the pixel driving circuit shown in Figure 1. Each column of pixel driving circuits is provided with a corresponding data line Da, and the data line connects to the first electrode of the fourth transistor in the pixel driving circuit in the same column. The data line Da can be connected to the sixth bridge portion 36 through a via, thereby connecting the first electrode of the fourth transistor T4 to the data signal terminal.

[0050] It should be noted that, as shown in Figures 4 and 12, the black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate. The black squares merely indicate the locations of the vias; different vias represented by black squares in different locations can penetrate different insulating layers.

[0051] As shown in FIG13 , a partial cross-sectional view of the display panel shown in FIG4 taken along dotted line EE is shown. The display panel may further include a first insulating layer 91, a second insulating layer 92, a dielectric layer 93, a passivation layer 94, and a first planarization layer 95. The substrate 90, the active layer, the first insulating layer 91, the first gate layer, the second insulating layer 92, the second gate layer, the dielectric layer 93, the first source and drain layer, the passivation layer 94, the first planarization layer 95, and the second source and drain layer may be stacked in sequence. The first insulating layer 91 and the second insulating layer 92 may be silicon oxide layers, the dielectric layer 93 may be a silicon nitride layer, the passivation layer 94 may be made of silicon oxide, silicon nitride, or the like, and the first planarization layer 95 may be made of an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or a silicon-glass bonding structure (SOG). The base substrate 90 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer may be an inorganic material. The first gate layer and the second gate layer may be made of one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or other conductive layer. The first source / drain layer and the second source / drain layer may be made of a metal material, such as one of molybdenum, aluminum, copper, titanium, and niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or other conductive layer such as a titanium / aluminum / titanium laminate.

[0052] In this exemplary embodiment, the first power line VDD is located in the first source-drain layer, the data line Da is located in the second source-drain layer of the display area AA, and the second source-drain layer is not wired in the border area BB. Therefore, the display panel is prone to accumulate a large amount of static charge in the border area BB, and the static charge is prone to break down the fourth transistor T4 in Figure 1, thereby causing the gate of the fourth transistor and the data line to be short-circuited. In the light-emitting stage of the pixel driving circuit, the gate of the fourth transistor T4 is often at a high level, and thus the data line Da is often at a high level, so that the data line will drive the sub-pixel where the pixel driving circuit is located to display a low grayscale image, and then a black line C will appear on the display panel.

[0053] Based on this, this exemplary embodiment provides a display panel, as shown in Figures 14 and 15. Figure 14 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure, and Figure 15 is a schematic structural diagram of a partial area D of the display panel shown in Figure 14. The display panel includes a display area AA, a frame area BB, and a pixel driving circuit Pix located in the display area AA. The display panel also includes a base substrate and a second source / drain layer. The second source / drain layer is located on one side of the base substrate. The second source / drain layer includes a data line da and at least one electrostatic transmission line LE. The data line Da is used to provide a data signal to the pixel driving circuit Pix. The data line Da is located in the display area AA. The electrostatic transmission line LE is used to transmit electrostatic charge on the display panel. The electrostatic transmission line LE is located in the frame area BB.

[0054] In this exemplary embodiment, an electrostatic transmission line LE is added to the border area BB. The electrostatic transmission line LE can disperse the static charge in the border area BB. The dispersed static charge is not easy to break down the transistors in the pixel driving circuit, so this setting can improve the safety and stability of the display panel.

[0055] It should be noted that the pixel driving circuit of the display area of ​​the display panel shown in Figure 14 may be as shown in Figure 4. It should be understood that in other exemplary embodiments, the pixel driving circuit may also have other structures, and this exemplary embodiment can release or disperse static electricity through the static electricity transmission line LE.

[0056] In this exemplary embodiment, as shown in Figure 15, the border area BB also includes a power line integration area B1, and the display panel also includes: a first source and drain layer, the first source and drain layer is located between the base substrate and the second source and drain layer, the first source and drain layer includes: a plurality of first power lines VDD, the first power line VDD is located in the display area, and the first power line VDD is used to provide a high-level signal to the pixel driving circuit Pix. For example, the first power line VDD is used to provide the first power terminal in Figure 1. The orthographic projections of the first power lines VDD on the substrate extend along the second direction Y and are spaced apart along the first direction X. The first direction X and the second direction Y intersect. For example, the first direction may be a row direction, and the second direction may be a column direction. The power access line LVDD is located in the power line integration area B1. The orthographic projections of the power access line LVDD on the substrate extend along the first direction X. The power access line LVDD connects to multiple first power lines VDD. The at least one electrostatic transmission line LE includes a first electrostatic transmission line LE1. The orthographic projections of the first electrostatic transmission line LE1 on the substrate at least partially overlap with the orthographic projections of the power access line LVDD on the substrate. The first electrostatic transmission line LE1 is connected to the power access line LVDD via a via. In this exemplary embodiment, the first electrostatic transmission line LE1 can release static charge through the power access line LVDD, thereby further preventing static charge accumulation in the border area BB.

[0057] It should be noted that in other exemplary embodiments, the power line integrated area B1 may also overlap with the area where a row of pixel driving circuits closest to the border area of ​​the display area is located. Accordingly, the pixel driving circuits in this row may not drive the light-emitting units to emit light.

[0058] In this exemplary embodiment, as shown in FIG15 , the display panel further includes a dummy pixel driving circuit DPix, and the border area BB further includes a dummy pixel area B2. The dummy pixel driving circuit DPix is ​​located in the dummy pixel area B2. The dummy pixel driving circuit Dpix can improve the edge effect of the active layer. The sub-pixel unit where the dummy pixel driving circuit Dpix is ​​located does not emit light. The at least one electrostatic transmission line LE further includes at least one second electrostatic transmission line LE2, and the second electrostatic transmission line LE2 is located in the dummy pixel area B2. The second electrostatic transmission line LE2 located in the dummy pixel area B2 can disperse the static charge in the dummy pixel area B2, thereby preventing static electricity accumulation.

[0059] In this exemplary embodiment, as shown in FIG15 , the first source / drain layer may further include: a plurality of virtual power lines DVDD, located in the virtual pixel area B2, with the orthographic projections of the virtual power lines DVDD on the substrate extending along the second direction Y and spaced apart along the first direction X; and second electrostatic transmission lines LE2 connected to the virtual power lines DVDD via vias. Electrostatic charge on the second electrostatic transmission lines LE2 can be transferred to the virtual power lines DVDD, thereby further dissipating the electrostatic charge. The second electrostatic transmission lines LE2 may be directly connected to the virtual power lines DVDD via vias, meaning that the vias connected to the second electrostatic transmission lines LE2 are also connected to the virtual power lines DVDD. Alternatively, the second electrostatic transmission lines LE2 may be indirectly connected to the virtual power lines DVDD via vias, meaning that the vias connected to the second electrostatic transmission lines LE2 are connected to the virtual power lines DVDD via other structures.

[0060] In this exemplary embodiment, as shown in FIG15 , the first source / drain layer further includes: a virtual power connection line VDDx, located in the virtual pixel area B2; an orthographic projection of the virtual power connection line VDDx on the base substrate extending along a first direction X and intersecting with an orthographic projection of the virtual power line DVDD on the base substrate; and an orthographic projection of a second electrostatic transmission line LE2 on the base substrate intersecting with the orthographic projection of the virtual power connection line VDDx on the base substrate. The second electrostatic transmission line LE2 is directly connected to the virtual power connection line VDDx via a via. The virtual power connection line VDDx can form a grid structure around the virtual power line DVDD, and the grid structure of the virtual power line DVDD can more evenly distribute static charge.

[0061] In this exemplary embodiment, as shown in FIG15 , the first source-drain layer further includes: a plurality of bridges 3, each of which is connected to a transistor in the pixel driving circuit via a via. The bridges 3 can be used to connect the source, drain, or gate of the transistor vias, thereby achieving connections between the transistors and between the transistors and the signal terminals. At least some of the bridges 3 are connected to a virtual power line DVDD. This arrangement can disperse static charge through the bridges 3 and the transistors and signal lines connected to the bridges 3, thereby further preventing static charge accumulation.

[0062] In this exemplary embodiment, the virtual power line DVDD and the conductive structure connected to the virtual power line DVDD can be suspended, that is, the virtual power line DVDD and the conductive structure connected to the virtual power line DVDD are not connected to the signal terminal or power terminal outside the display panel. Static electricity in the border area BB can be dispersed on the virtual power line DVDD and the conductive structure connected to the virtual power line DVDD. It should be understood that in other exemplary embodiments, the virtual power line DVDD and the conductive structure connected to the virtual power line DVDD can also be connected to an external circuit, and static electricity in the border area BB can be discharged to the outside through the virtual power line DVDD and the conductive structure connected to the virtual power line DVDD.

[0063] In this exemplary embodiment, as shown in FIG16 , which is a schematic structural diagram of another exemplary embodiment of the display panel disclosed herein, the at least one second electrostatic transmission line may further include: a plurality of first sub-electrostatic transmission lines LE21 , wherein the orthographic projections of the first sub-electrostatic transmission lines LE21 on the base substrate extend along the second direction Y and are spaced apart along the first direction X.

[0064] In this exemplary embodiment, as shown in FIG16 , the at least one second electrostatic transmission line may further include: at least one second sub-electrostatic transmission line LE22, the orthographic projection of the at least one second sub-electrostatic transmission line LE22 on the substrate extending along the first direction X and spaced apart along the second direction Y; the orthographic projection of the second sub-electrostatic transmission line LE22 on the substrate intersecting with the orthographic projection of the first sub-electrostatic transmission line LE21 on the substrate. The second sub-electrostatic transmission lines LE22 and the first sub-electrostatic transmission lines LE21 may form a grid structure. The grid structure of the second sub-electrostatic transmission lines LE22 and the first sub-electrostatic transmission lines LE21 can more evenly disperse static charge, thereby preventing static charge accumulation.

[0065] In this exemplary embodiment, the electrostatic transmission line LE includes a plurality of second electrostatic transmission lines LE2. The plurality of second electrostatic transmission lines LE2 may form a grid structure. The hollowed-out shape of the grid structure may include one or more of a circle, a polygon, and an irregular shape. The polygon may be a triangle, a rectangle, a rhombus, a pentagon, a hexagon, or the like.

[0066] In this exemplary embodiment, as shown in Figures 14-16, the display area AA and the border area BB are distributed in the second direction Y. The display panel may further include a bonding area PAD, which can be used to bond driver chips such as source driver circuits, driver ICs, and touch control ICs. The bonding area PAD can be bent to the back of the display panel. Before the bonding area PAD is bent, the border area BB can be located on the side of the display area AA that is away from the bonding area PAD.

[0067] In this exemplary embodiment, as shown in FIG. 4 to FIG. 6 , the power line integration area B1 is located between the dummy pixel area B2 and the display area AA.

[0068] In this exemplary embodiment, the display panel further includes: a signal line, the signal line being located between the base substrate and the second source / drain layer, and the electrostatic transmission line being connected to the signal line through a via. The electrostatic transmission line can release static charge through the signal line. The signal line may include at least one of a power line and an initial signal line. The power line is used to provide a power signal to the pixel driving circuit, for example, the power line can be used to provide a high-level or low-level power signal to the pixel driving circuit; the initial signal line is used to provide an initial signal to the pixel driving circuit, for example, the initial signal line can be used to provide a first initial signal, a second initial signal, etc. to the pixel driving circuit.

[0069] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0070] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0071] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0072] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0073] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a display area, a frame area, and a pixel driving circuit located in the display area. The display panel also includes: substrate; A second source and drain layer is located on one side of the base substrate, and the second source and drain layer includes a data line and at least one electrostatic transmission line. The data line is used to provide a data signal to the pixel driving circuit, and the data line is located in the display area. The electrostatic transmission line is used to transmit static charge on the display panel, and the electrostatic transmission line is located in the frame area.

2. The display panel according to claim 1, wherein: The display panel further includes: A signal line is located between the base substrate and the second source / drain layer, and the electrostatic transmission line is connected to the signal line through a via hole.

3. The display panel according to claim 2, wherein: The signal line includes at least one of a power line and an initial signal line; The power line is used to provide a power signal to the pixel driving circuit, and the initial signal line is used to provide an initial signal to the pixel driving circuit.

4. The display panel according to claim 1, wherein: The frame area includes a power line integration area, and the display panel further includes: A first source-drain layer is located between the base substrate and the second source-drain layer, and the first source-drain layer includes: a plurality of first power lines located in the display area, the first power lines being configured to provide high-level signals to the pixel driving circuit, the orthographic projections of the first power lines on the substrate extending along a second direction and spaced apart along the first direction, the first direction and the second direction intersecting; a power access line, located in the power line integrated area, wherein an orthographic projection of the power access line on the substrate extends along the first direction, and the power access line connects a plurality of the first power lines; At least one of the electrostatic transmission lines includes a first electrostatic transmission line, the orthographic projection of the first electrostatic transmission line on the base substrate and the orthographic projection of the power access line on the base substrate at least partially overlap, and the first electrostatic transmission line is connected to the power access line through a via.

5. The display panel according to claim 1, wherein: The display panel further includes a virtual pixel driving circuit, the frame area includes a virtual pixel area, and the virtual pixel driving circuit is located in the virtual pixel area; The at least one static electricity transmission line includes at least one second static electricity transmission line, and the second static electricity transmission line is located in the dummy pixel area. The display panel according to claim 5 , wherein: The display panel further includes: A first source-drain layer is located between the base substrate and the second source-drain layer, and the first source-drain layer includes: a plurality of virtual power lines located in the virtual pixel area, wherein the orthographic projections of the virtual power lines on the substrate extend along a second direction and are spaced apart along a first direction, and the first direction and the second direction intersect; The second electrostatic transmission line is connected to the virtual power line through a via.

7. The display panel according to claim 6, wherein: The first source and drain layer further includes: a virtual power connection line, located in the virtual pixel area, wherein an orthographic projection of the virtual power connection line on the base substrate extends along the first direction and intersects with an orthographic projection of the virtual power line on the base substrate; The orthographic projection of the second electrostatic transmission line on the base substrate intersects with the orthographic projection of the virtual power connection line on the base substrate, and the second electrostatic transmission line is directly connected to the virtual power connection line through a via.

8. The display panel according to claim 6, wherein: The pixel driving circuit includes a plurality of transistors, and the first source-drain layer further includes: One or more bridge portions, wherein the bridge portions are connected to the transistors through vias; Wherein, at least a portion of the bridge portion is connected to the virtual power line.

9. The display panel according to claim 5, wherein: At least one of the second electrostatic transmission lines comprises: A plurality of first sub-electrostatic transmission lines are provided, wherein the orthographic projections of the first sub-electrostatic transmission lines on the base substrate extend along the second direction and are spaced apart along the first direction, and the first direction and the second direction intersect.

10. The display panel according to claim 9, wherein: At least one of the second electrostatic transmission lines further includes: At least one second sub-electrostatic transmission line, wherein the orthographic projection of the at least one second sub-electrostatic transmission line on the substrate extends along the first direction and is spaced apart along the second direction; The orthographic projection of the second sub-electrostatic transmission line on the base substrate intersects with the orthographic projection of the first sub-electrostatic transmission line on the base substrate.

11. The display panel according to claim 5, wherein: At least one of the electrostatic transmission lines includes a plurality of the second electrostatic transmission lines, and the plurality of the second electrostatic transmission lines form a grid structure, and the hollow shape of the grid structure includes one or more of a circle, a polygon, and an irregular shape.

12. The display panel according to claim 1, wherein: The orthographic projection of the data line on the base substrate extends along a second direction. The display panel further includes a binding area. The binding area, the display area, and the frame area are distributed in the second direction, and the display area is located between the binding area and the frame area.

13. The display panel according to claim 12, wherein: The frame area includes a power line integration area and a virtual pixel area, and the power line integration area is located between the virtual pixel area and the display area.

14. The display panel according to claim 1, wherein: The pixel driving circuit includes: a driving transistor and a fourth transistor. A first electrode of the fourth transistor is connected to a data line, and a second electrode is connected to the first electrode of the driving transistor.

15. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 14.

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