Display panel and display system comprising same

Abstract

This display panel comprises: a first sub-pixel; a second sub-pixel; a second-a power line; and a second-b power line. The first sub-pixel is configured to emit light of a first wavelength band. The second sub-pixel is positioned in a first direction from the first sub-pixel. The second sub-pixel is configured to emit light of a second wavelength band different from the first wavelength band. The second-a power line extends in the first direction and overlaps the first and second sub-pixels in a third direction intersecting the first direction. The second-a power line includes a bridge pattern branching in a second direction intersecting the first direction and the third direction. The second-a power line is electrically connected to the first sub-pixel via a bridge pattern. The second-b power line bypasses the bridge pattern and extends in the first direction. The second-b power line overlaps the first and second sub-pixels in the third direction. The second-b power line is electrically connected to the second sub-pixel.

Description

Display panel and display system including the same

[0001] Embodiments of the present disclosure generally relate to a display panel and a display system including the same.

[0002] As information technology advances, the importance of display devices, which serve as a link between users and information, is growing. In response, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), and inorganic light-emitting displays (ILDs), is increasing.

[0003] Some display devices are becoming increasingly smaller. Consequently, the size of pixels (or sub-pixels) in display devices (or display panels) is also decreasing. To reduce pixel (or sub-pixel) size, a method is being used in which the circuit elements of the sub-pixel circuits that constitute a pixel and the power lines that supply power to the sub-pixel circuits are stacked vertically.

[0004] However, multiple masks are typically used to vertically stack circuit elements and power lines, which can increase the time required to manufacture the display panel. Therefore, a method for providing a display panel with spatially efficient arrangement of sub-pixels and power lines is needed.

[0005] The background provided herein is generally intended to provide context for the disclosure. The work of the currently named inventors is described in this background, and aspects of the description that may not have qualified as prior art at the time of filing are not explicitly or implicitly recognized as prior art for the disclosure.

[0006] The technical challenge to be solved is to provide a display panel in which power lines and sub-pixels are efficiently arranged.

[0007] The technical challenge to be solved is to provide a display system including a display panel in which power lines and sub-pixels are efficiently arranged.

[0008] Additional aspects will be set forth in the detailed description which follows, and in part will be obvious from the disclosure or may be learned by practicing the disclosed embodiments and / or claimed subject matter.

[0009] A display panel according to embodiments of the present disclosure includes a first sub-pixel, a second sub-pixel, a 2a power line, and a 2b power line. The first sub-pixel is configured to emit light of a first wavelength band. The second sub-pixel is positioned in a first direction from the first sub-pixel. The second sub-pixel is configured to emit light of a second wavelength band different from the first wavelength band. The 2a power line extends in the first direction and is positioned to overlap the first and second sub-pixels in a third direction intersecting the first direction. The 2a power line includes a bridge pattern branching in a second direction intersecting the first and third directions. The 2a power line is electrically connected to the first sub-pixel through the bridge pattern. The 2b power line extends in the first direction bypassing the bridge pattern. The 2b power line is positioned to overlap the first and second sub-pixels in the third direction. The 2b power line is electrically connected to the second sub-pixel.

[0010] In one embodiment, the seconda power line and the secondb power line may be adjacent to each other in the second direction.

[0011] In one embodiment, the 2a power line and the 2b power line can be configured to apply different levels of power voltage to the first sub-pixel and the second sub-pixel, respectively.

[0012] In one embodiment, the display panel may further include a gate line extending in a first direction. The gate line may be electrically connected to both the first and second sub-pixels. The gate line may be positioned between the seconda power line and the secondb power line in the second direction.

[0013] In one embodiment, the bridge pattern may be positioned to overlap at least a portion of the gate line in a third direction.

[0014] In one embodiment, the seconda power line may not be electrically connected to the second sub-pixel, and the secondb power line may not be electrically connected to the first sub-pixel.

[0015] In one embodiment, each of the first and second sub-pixels may include a pulse width modulation circuit, a connecting electrode, a pixel driving circuit, and a light-emitting element. The pulse width modulation circuit may be configured to generate a light-emitting control signal having a pulse width corresponding to a data signal. The connecting electrode may be electrically connected to the pulse width modulation circuit. The connecting electrode may be configured to receive the light-emitting control signal. The pixel driving circuit may be electrically connected to the connecting electrode. The pixel driving circuit may be configured to generate a driving current for a period corresponding to a pulse width of the light-emitting control signal. The light-emitting element may be electrically connected between the pixel driving circuit and a fourth power line, wherein the fourth power line is different from the seconda power line and the secondb power line. The light-emitting element may be configured to emit light in response to the driving current. The seconda power line may be electrically connected to the pulse width modulation circuit of the first sub-pixel. The secondb power line may be electrically connected to the pulse width modulation circuit of the second sub-pixel.

[0016] In one embodiment, a pulse width modulation circuit may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first transistor may include a gate electrode electrically connected to a first node. The first transistor may be electrically connected between a second node and a third node. The second transistor may be electrically connected to a first gate line. The second transistor may be configured to switch an electrical connection between the third node and a data line. The third transistor may include a gate electrode electrically connected to the first gate line. The third transistor may be configured to switch an electrical connection between the first node and the second node. The fourth transistor may include a gate electrode electrically connected to a light emission control line. The fourth transistor may be configured to switch an electrical connection between a first power line and the third node. The first power line may be different from the seconda power line, the secondb power line, and the fourth power line. The fifth transistor may include a gate electrode electrically connected to the emission control line. The fifth transistor may be configured to switch an electrical connection between the second node and the fourth node. The sixth transistor may include a gate electrode electrically connected to a second gate line different from the first gate line. The sixth transistor may be configured to switch an electrical connection between the first node and the fifth node. The seconda power line may be electrically connected to the fifth node of the first sub-pixel. The secondb power line may be electrically connected to the fifth node of the second sub-pixel.

[0017] In one embodiment, each of the first transistor, the fourth transistor, and the fifth transistor may include a semiconductor layer formed of a corresponding region of the first active pattern layer. Each of the second transistor, the third transistor, and the sixth transistor may include a semiconductor layer formed of a corresponding region of the second active pattern layer that is different from the first active pattern layer. The first active pattern layer may be a P-type semiconductor layer, and the second active pattern layer may be an N-type semiconductor layer.

[0018] In one embodiment, the connecting electrode may be electrically connected to a fourth node.

[0019] In one embodiment, the pulse width modulation circuit may include a first capacitor. The first capacitor may include a first electrode electrically connected to a first node and a second electrode electrically connected to a sweep line.

[0020] In one embodiment, the pixel driver circuit may further include a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, a second capacitor, and a third capacitor. The seventh transistor may include a gate electrode electrically connected to a fourth node. The seventh transistor may be electrically connected to a sixth node. The eighth transistor may include a gate electrode electrically connected to an emission control line. The eighth transistor may be configured to switch an electrical connection between a third power line and the seventh transistor. The third power line may be different from the first power line, the seconda power line, the secondb power line, and the fourth power line. The ninth transistor may include a gate electrode electrically connected to a third gate line, wherein the third gate line is different from the first gate line and the second gate line. The ninth transistor may be configured to switch an electrical connection between the fourth node and the fifth node. The tenth transistor may include a gate electrode electrically connected to the fourth gate line. The tenth transistor may be configured to switch an electrical connection between a fifth power line and a sixth node. The fifth power line may be different from the first power line, the seconda power line, the secondb power line, the third power line, and the fourth power line. The second capacitor may include a first electrode electrically connected to the third power line and a second electrode electrically connected to the fourth node. The third capacitor may include a first electrode electrically connected to the fourth node and a second electrode electrically connected to the sixth node.

[0021] In one embodiment, each of the seventh transistor, the eighth transistor, and the tenth transistor may include a semiconductor layer formed of a corresponding region of the first active pattern layer. The ninth transistor may include a semiconductor layer formed of a corresponding region of the second active pattern layer.

[0022] In one embodiment, each of the first gate line, the second gate line, and the third gate line may include a corresponding region of the gate electrode layer. The fourth gate line, the first power line, the seconda power line, the secondb power line, the secondc power line, the sweep line, and the emission control line may include a corresponding region of the first source-drain electrode layer disposed on the gate electrode layer. The data line, the fourth power line, and the fifth power line may include a corresponding region of the second source-drain electrode layer disposed on the first source-drain electrode layer.

[0023] In one embodiment, the pulse width modulation circuit and the pixel driver circuit may be adjacent in a second direction. The connecting electrode may extend in the second direction and overlap with each of the seconda power line and the secondb power line in a third direction.

[0024] In one embodiment, the light emitting element may be a flip chip type light emitting element.

[0025] In one embodiment, the bridge pattern extended from the second a power line may include a first bridge pattern. A display panel according to embodiments of the present disclosure may further include a third sub-pixel and a third a power line. The third sub-pixel may be positioned in a first direction from the second sub-pixel. The third sub-pixel may be configured to emit light of a third wavelength band different from the first wavelength band and the second wavelength band. The third a power line may extend in the first direction and overlap the first sub-pixel, the second sub-pixel, and the third sub-pixel in the third direction. The third a power line may include a second bridge pattern branching in the second direction and may be electrically connected to the third sub-pixel through the second bridge pattern. The third a power line may be different from the second a power line and the second b power line. The second b power line may extend in the first direction and may bypass the first and second bridge patterns.

[0026] In one embodiment, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be sequentially adjacent in the first direction.

[0027] The first sub-pixel, the third sub-pixel, and the second sub-pixel may be sequentially adjacent in the first direction.

[0028] A display system according to embodiments of the present disclosure may include a processor and a display device. The processor may provide image data and a control signal. The display device may include a display panel, and the display device may be configured to receive the image data and the control signal, and display an image corresponding to the image data in response to the control signal. The display panel may include a first sub-pixel, a second sub-pixel, a seconda power line, and a secondb power line. The first sub-pixel may be configured to emit light of a first wavelength band. The second sub-pixel may be positioned in a first direction from the first sub-pixel. The second sub-pixel may be configured to emit light of a second wavelength band different from the first wavelength band. The seconda power line may extend in the first direction and overlap the first sub-pixel and the second sub-pixel in a third direction, the third direction intersecting the first direction. The seconda power line may include a bridge pattern branching in a second direction intersecting the first direction and the third direction. The second power line may be electrically connected to the first sub-pixel through the bridge pattern. The second power line may extend in the first direction by bypassing the bridge pattern. The second power line may overlap each of the first and second sub-pixels in the third direction. The second power line may be electrically connected to the second sub-pixel.

[0029] The foregoing general description and the following detailed description are explanatory and exemplary and are intended to provide further explanation of the subject matter claimed.

[0030] According to the embodiments of the present disclosure, the display panel and the display system including the same enable efficient arrangement of power lines and sub-pixels. This allows for increased pixel density, thereby improving the resolution of the display panel and the display system including the display panel.

[0031] Various embodiments disclosed herein are illustrated by way of example, and not limitation, in the accompanying drawings, in which like reference numbers and / or letters represent similar components.

[0032] FIG. 1 is a block diagram showing a display device according to embodiments.

[0033] Fig. 2 is an orthogonal projection showing an embodiment of a display panel of the display device of Fig. 1.

[0034] FIG. 3 is a block diagram showing an embodiment of a sub-pixel of the display device of FIG. 1.

[0035] FIG. 4 is an embodiment of a sub-pixel circuit according to embodiments.

[0036] FIG. 5 is an example of an equivalent circuit diagram of a pulse width modulation circuit and a pixel driving circuit according to embodiments.

[0037] FIG. 6 is a first (e.g., lower) layout drawing of sub-pixels according to embodiments.

[0038] FIG. 7 is a second (e.g., upper) layout drawing of sub-pixels according to embodiments.

[0039] FIG. 8A is an example of bridge patterns according to one embodiment of a display panel according to the embodiments of FIG. 2.

[0040] FIG. 8b is an example of bridge patterns according to another embodiment of the display panel according to the embodiments of FIG. 2.

[0041] FIG. 9 is a cross-sectional view showing an embodiment of a display panel according to the embodiments of FIG. 2.

[0042] FIG. 10 is a cross-sectional view showing another embodiment of a display panel according to the embodiments of FIG. 2.

[0043] FIG. 11 is an orthogonal projection showing an embodiment of one of the pixels of FIG. 2.

[0044] Figure 12 is a cross-sectional view taken along line II' of the pixel of Figure 11.

[0045] Figure 13 is a cross-sectional view taken along line II-II' of the pixel of Figure 11.

[0046] Figure 14 is a block diagram showing an embodiment of a display system.

[0047] Figures 15, 16, 17, and 18 are perspective views showing application examples of the display system of Figure 14.

[0048] In the following description, specific details are set forth for purposes of explanation and to provide an understanding of various embodiments or implementations. The terms "embodiment" and "implementation" may be used interchangeably to describe one or more non-limiting examples of the systems, devices, methods, etc. described herein. However, it will be apparent that various embodiments may be practiced without the specific details or in one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily limiting the various embodiments. Furthermore, the various embodiments may vary, but are not necessarily exclusive. For example, specific features, configurations, and characteristics of an embodiment may be used or implemented in other embodiments without departing from the scope of the present disclosure.

[0049] Unless otherwise specified, the described embodiments should be understood to provide exemplary features of various details of some embodiments. Accordingly, unless otherwise specified, the features, components, modules, layers, films, regions, aspects, structures, etc. (hereinafter individually or collectively referred to as "elements" or "elements") of the various drawings may be otherwise combined, separated, exchanged, and / or rearranged without departing from the scope of the present disclosure.

[0050] The use of crosshatching and / or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. Therefore, the presence or absence of crosshatching or shading is not intended to convey or indicate any preference or requirement for any particular material, material property, dimension, proportion, commonality between drawing elements, and / or any other characteristic, property, or property of the elements, unless expressly stated otherwise. Furthermore, the sizes and relative sizes of elements in the accompanying drawings may be exaggerated for clarity and / or illustrative purposes. Accordingly, the sizes and relative sizes of each element are not necessarily limited to those shown in the drawings. Where the embodiments may be implemented differently, certain process sequences may be performed differently from the illustrated sequence. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order described. Furthermore, like reference numbers and / or reference letters indicate like elements.

[0051] When an element, such as a layer, is referred to as being "over," "on," "connected to," or "joined to" another element, it may be directly over, directly on, directly connected to, or directly coupled to the other element, or there may be at least one intermediate element present. However, when a component is referred to as being "directly over," "directly on," "directly connected to," or "directly coupled to" another component, there are no intermediate elements present. When other terms and / or phrases are used herein to describe the relationship between components, they should be interpreted in the same manner, such as "between" and "directly between," "adjacent" and "directly adjacent," "over" and "directly above," "connected" and "directly connected," "contacting" and "directly contacting," etc. Furthermore, the term "connected" may refer to a physical, electrical, and / or fluid connection. To this end, the phrase "fluidically connected" in this disclosure may be used with respect to volumes, plenums, holes, openings, etc., that can be directly connected to one another through one or more intervening components or volumes to form a fluid connection, similar to the way the phrase "electrically connected" is used with respect to components that are connected to form an electrical connection.

[0052] For the purposes of this disclosure, the first axis extending along the first direction (DR1), the second axis extending along the second direction (DR2), and the third axis extending along the third direction (DR3) are not limited to three axes of an orthogonal coordinate system, such as the x, y, and z axes of an orthogonal coordinate system, and may be interpreted in a broader sense. For example, the first axis, the second axis, and the third axis may be perpendicular to each other, or may represent other directions that are not perpendicular to each other. Furthermore, when used in this disclosure, the phrases “at least one of X, Y, ..., and Z” and “at least one selected from the group consisting of X, Y, ..., and Z” may be interpreted as X only, Y only, ..., Z only, or any combination of two or more of X, Y, Z, for example, XYZ, XYY, YZ, and ZZ. Furthermore, when used herein, the term “and / or” includes any combination of one or more of the associated listed items.

[0053] While the terms "first," "second," "third," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Accordingly, a first element discussed below may be referred to as a second element without departing from the scope of this disclosure. To this end, the use of such identifiers, e.g., "first element," should not be construed as implicitly or inherently implying that there are other instances, such as "second element."

[0054] Spatially relative terms such as "underneath," "beneath," "lower," "above," "on," "over," "higher," and "to the side" (e.g., a "side wall") may be used herein for descriptive purposes to describe the spatial relationship of one element to at least one other element, as depicted in the drawings. The spatially relative terms are intended to encompass various orientations of the device during use, operation, and / or manufacture, in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as "underneath" or "beneath" another element or feature is oriented "above" or "on" the other element or feature. Thus, the term "underneath" can encompass both the above and below orientations. Moreover, the device can be oriented in other orientations (e.g., rotated 90 degrees (°) or in other directions), and the spatially relative descriptors used herein are to be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing some embodiments and is not intended to be limiting. The singular forms used herein are intended to include the plural forms as well, unless the context clearly indicates otherwise. The phrases "for each <item> of one or more <items>," "each <item> of one or more <items>," and / or similar phrases, when used herein, should be understood to encompass both single-item groups and multiple-item groups. That is, the phrase "for each..." is used in the sense that it refers to each item of all items referenced in a programming language. For example, if the collection of items being referenced is a single item, "each" refers only to that single item (although dictionaries often define "each" to mean "any of two or more") and does not imply that there must be at least two of those items. Similarly, the terms "set" or "subset" should not be construed as necessarily encompassing a plurality of items. A set or subset may (unless the context clearly indicates otherwise) include just one member or multiple members.

[0056] As used herein, the terms "comprises," "comprising," "has," and / or "having" specify the presence of stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should also be noted that the terms "substantially," "about," "approximately," and other similar terms as used herein are used as terms of approximation rather than degrees, and thus are used to account for the inherent variation in measurements, calculations, and / or provided values ​​that will be recognized by those skilled in the art. Thus, as used herein, the term "substantially" can mean within 5% of a referenced value, unless otherwise specified. For example, substantially perpendicular can mean within ±5% of parallel. Furthermore, the term "between" as used herein in connection with a range of values ​​should be understood to include the start and end values ​​of the range, unless otherwise specified. For example, the numbers between 1 and 5 should be understood to include not only the numbers 2, 3, and 4, but also the numbers 1, 2, 3, 4, and 5.

[0057] Various embodiments are described herein with reference to cross-sections, isometric views, perspective views, orthographic views, and / or exploded views, which are schematic depictions of idealized embodiments and / or intermediate structures. Therefore, variations in the shapes of the figures may occur, for example, due to manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as being limited to the specific shapes of the regions depicted, but should encompass, for example, variations in shape resulting from manufacturing. For this purpose, the regions depicted in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the device regions and are therefore not intended to be limiting.

[0058] As is customary in the art, some embodiments may be illustrated and described in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. When the blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Furthermore, each block, unit, and / or module may be implemented by dedicated hardware, or a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) that perform other functions. Additionally, each block, unit, and / or module of some embodiments may be physically separated into two or more interacting and individual blocks, units, and / or modules without departing from the scope of the disclosure. Furthermore, the blocks, units, and / or modules of some embodiments may be physically combined into more complex blocks, units, and / or modules without departing from the scope of the disclosure.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries, for example, should be interpreted as having a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0060] Hereinafter, various embodiments will be described in detail with reference to the attached drawings.

[0061] FIG. 1 is a block diagram showing a display device (DD) according to embodiments of the present disclosure.

[0062] Referring to FIG. 1, the display device (DD) may include a display panel (DP), a gate driver (120), a data driver (130), a voltage generator (140), a sweep providing circuit (160), and a controller (150).

[0063] A display panel (DP) may include sub-pixels (SP). The sub-pixels (SP) may be electrically connected to a gate driver (120) via first to m-th gate lines (GL1 to GLm; m is an integer greater than or equal to 1). The sub-pixels (SP) may be electrically connected to a data driver (130) via first to n-th data lines (DL1 to DLn; n is an integer greater than or equal to 1).

[0064] The sub-pixels (SP) can generate light of two or more colors. For example, each of the sub-pixels (SP) can generate light of red, green, blue, cyan, magenta, yellow, etc. However, embodiments are not limited thereto. For example, at least one of the sub-pixels (SP) can generate white light or light of another suitable color.

[0065] Two or more sub-pixels (SP) among the sub-pixels (SP) can constitute one pixel (PXL). For example, the pixel (PXL) can include three sub-pixels (SP) as illustrated in FIG. 1. In this way, the pixel (PXL) can emit light of various colors and various luminances depending on the combination of light emitted from the sub-pixels (SP) included in it.

[0066] The gate driver (120) is electrically connected to the sub-pixels (SP) arranged in the first (e.g., row) direction (DR1) via the first to m-th gate lines (GL1 to GLm). The gate driver (120) can output gate signals to the first to m-th gate lines (GL1 to GLm) in response to a gate control signal (GCS). In embodiments, the gate control signal (GCS) can include a start signal indicating the start of each frame, a horizontal synchronization signal, and the like.

[0067] The gate driver (120) may be arranged on one side of the display panel (DP). However, the embodiments of the present disclosure are not limited thereto. For example, the gate driver (120) may be divided into two or more drivers that are physically and / or logically separated, and such drivers may be arranged on one side of the display panel (DP) and on the other side of the display panel (DP) opposite to the one side, for example, on the side opposite to the first direction (DR1). In this way, the gate driver (120) may be arranged around the display panel (DP) in various forms depending on the display panel (DP).

[0068] The data driver (130) is electrically connected to the sub-pixels (SP) arranged in a second (e.g., column) direction (DR2) via the first to nth data lines (DL1 to DLn). In one embodiment, the second direction (DR2) may be a direction intersecting (e.g., perpendicular) to the first direction (DR1). The data driver (130) receives image data (DATA) and a data control signal (DCS) from the controller (150). The data driver (130) operates in response to the data control signal (DCS). In embodiments, the data control signal (DCS) may include a source start signal, a source shift clock signal, a source output enable signal, etc.

[0069] The data driver (130) can receive voltages from the voltage generator (140). The data driver (130) can use the received voltages to apply data signals having grayscale voltages corresponding to image data (DATA) to the first to n-th data lines (DL1 to DLn). In response to a gate signal applied to each of the first to m-th gate lines (GL1 to GLm), data signals corresponding to the image data (DATA) can be applied to the data lines (DL1 to DLn). The sub-pixels (SP) can generate light corresponding to the data signals, and the display panel (DP) can display an image.

[0070] In embodiments, the gate driver (120) and the data driver (130) may include complementary metal-oxide semiconductor (CMOS) circuit elements. However, embodiments of the present disclosure are not limited thereto.

[0071] The voltage generator (140) can operate in response to a voltage control signal (VCS) from the controller (150). The voltage generator (140) is configured to generate a plurality of voltages and provide the generated voltages to components of the display device (DD), such as the gate driver (120), the data driver (130), and the controller (150). The voltage generator (140) can generate a plurality of voltages by receiving an input voltage from a device (e.g., a device external to the display device (DD)) and regulating the received input voltage.

[0072] The voltage generator (140) can generate two or more voltages, for example, power voltages. The generated power voltages can be provided to the sub-pixels (SP) via power lines (PL), one of which is illustrated in FIG. 1. In other embodiments, at least one of the power voltages can be provided from outside the display device (DD).

[0073] In addition, the voltage generator (140) can provide various voltages and / or signals. For example, the voltage generator (140) can provide one or more initialization voltages applied to the sub-pixels (SP). For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels (SP), a predetermined reference voltage can be applied to the first to n-th data lines (DL1 to DLn), and the voltage generator (140) can generate the reference voltage and transmit it to the data driver (130). For example, during a display operation for displaying an image on the display panel (DP), pixel control signals can be applied to the sub-pixels (SP), and the voltage generator (140) can generate at least some of the pixel control signals. In embodiments, the voltage generator (140) may provide one or more pixel control signals to the sub-pixels (SP) via pixel control lines (PXCL), which are illustrated as a single dotted line in FIG. 1. Although FIG. 1 illustrates that the pixel control lines (PXCL) are electrically connected between the voltage generator (140) and the display panel (DP), embodiments are not limited thereto. For example, at least one of the pixel control lines (PXCL) may be electrically connected between the gate driver (120) and the display panel (DP). The pixel control signals may be transmitted from the voltage generator (140) to the pixel control lines (PXCL) via the gate driver (120).

[0074] The sweep providing circuit (160) can provide a sweep signal to the display panel (DP). The sweep signal can be, for example, a signal whose voltage increases over time (e.g., sequentially increases). However, embodiments are not limited thereto. The sweep signal can be, for example, a signal whose voltage decreases over time (e.g., sequentially decreases). The sweep signal can be provided as a triangle wave. The sweep providing circuit (160) can provide the sweep signal to the sweep line (SWL). The sweep line (SWL) can be electrically connected to a plurality of sub-pixels (SP). The sweep providing circuit (160) can provide the sweep signal to the sweep line (SWL) in response to the sweep control signal (SCS).

[0075] According to an embodiment, a sweep line (SWL) (e.g., one sweep line (SWL)) may be connected to a plurality of sub-pixels (SP) located in a single row (or a single pixel row). According to an embodiment, a sweep line (SWL) (e.g., one sweep line (SWL)) may be electrically connected to a plurality of sub-pixels (SP) located in a plurality of rows (or a plurality of pixel rows).

[0076] The controller (150) can control all operations of the display device (DD). The controller (150) can receive input image data (IMG) and a corresponding control signal (CTRL) from a device (e.g., a device external to the display device (DD). In response to the control signal (CTRL), the controller (150) can provide a gate control signal (GCS), a data control signal (DCS), a voltage control signal (VCS), and a sweep control signal (SCS).

[0077] The controller (150) can convert input image data (IMG) to be suitable for a display device (DD) or a display panel (DP) and output the image data (DATA). In embodiments, the controller (150) can align the input image data (IMG) to be suitable for sub-pixels (SP) in a row unit and output the image data (DATA).

[0078] Two or more components of the data driver (130), the voltage generator (140), and the controller (150) may be mounted on a single integrated circuit. As illustrated in FIG. 1, the data driver (130), the voltage generator (140), and the controller (150) may be included in a driver integrated circuit (DIC). In this case, the data driver (130), the voltage generator (140), and the controller (150) may be functionally separate components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver (130), the voltage generator (140), and the controller (150) may be provided as a separate (or distinct) component from the driver integrated circuit (DIC) including the remaining components of the data driver (130), the voltage generator (140), and the controller (150).

[0079] FIG. 2 is an orthogonal projection diagram showing an embodiment of a display panel (DP) of the display device (DD) of FIG. 1. For example, FIG. 2 illustrates the display panel (DP) when viewed from a third direction (DR3), which may be a transverse direction (e.g., an orthogonal direction) with respect to both the first direction (DR1) and the second direction (DR2).

[0080] Referring to FIG. 2, a display panel (DP) may include a display area (DA) and a non-display area (NDA). The display panel (DP) may display an image through (or in connection with) the display area (DA). The non-display area (NDA) may be positioned around (e.g., adjacent to, around, and / or similar to) the display area (DA).

[0081] A plurality of sub-pixels (SP) may be positioned in the display area (DA). The plurality of sub-pixels (SP) may be arranged along a first direction (DR1) and a second direction (DR2) intersecting the first direction (DR1). In one embodiment, the plurality of sub-pixels (SP) may be arranged in a matrix form along the first direction (DR1) and the second direction (DR2). As another example, the plurality of sub-pixels (SP) may be arranged in a zigzag form along the first direction (DR1) and the second direction (DR2). In one embodiment, the sub-pixels (SP) may be arranged in a pentile form. TM ) can be arranged in the form of a plurality of sub-pixels (SP). However, the arrangement of the plurality of sub-pixels (SP) may vary depending on the configuration of the display panel (DP) according to embodiments. For example, the first direction (DR1) may be a row direction, and the second direction (DR2) may be a column direction or the opposite. However, the embodiments of the present disclosure are not limited thereto.

[0082] Two or more sub-pixels among a plurality of sub-pixels (SP) can constitute one pixel (PXL). Referring to FIG. 2, the pixel (PXL) is illustrated as including three sub-pixels, for example, first to third sub-pixels (SP1, SP2, and SP3), but the embodiments of the present disclosure are not limited thereto. For example, the pixel (PXL) may include two sub-pixels, or four or more sub-pixels. Hereinafter, for convenience, it is assumed that the pixel (PXL) includes first to third sub-pixels (SP1 to SP3).

[0083] Each of the first to third sub-pixels (SP1 to SP3) can generate light of one of various colors such as red, green, blue, cyan, magenta, yellow, etc., but the embodiments are not limited thereto. Hereinafter, for the sake of clarity and concise description, it is assumed and described that the first sub-pixel (SP1) is configured to generate red color light, the second sub-pixel (SP2) is configured to generate green color light, and the third sub-pixel (SP3) generates blue color light.

[0084] Each of the first to third sub-pixels (SP1 to SP3) may include at least one light-emitting element configured to generate light. In embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of the same color. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate blue light, for example, light in a wavelength band of 450 nm to 495 nm. In other embodiments, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate light of different colors. For example, the light-emitting elements of the first to third sub-pixels (SP1 to SP3) may generate red light (for example, light in a wavelength band of 620 nm to 750 nm), green light (for example, light in a wavelength band of 500 nm to 600 nm), and blue light, respectively.

[0085] As a display panel (DP), a self-luminous display panel such as a light emitting diode display panel (LED display panel) that uses micro-scale or nano-scale light emitting diodes as light emitting elements, and / or an organic light emitting diode display panel (OLED panel) that uses organic light emitting diodes as light emitting elements may be used. However, the embodiments are not limited thereto.

[0086] Components for controlling a plurality of sub-pixels (SP) may be arranged in the non-display area (NDA), but embodiments are not limited thereto. Wires electrically connected to a plurality of sub-pixels (SP), for example, the first to m-th gate lines (GL1 to GLm), the first to n-th data lines (DL1 to DLn), the power lines (PL), and the pixel control lines (PXCL) described in connection with FIG. 1, may be arranged in the non-display area (NDA).

[0087] At least one of the gate driver (120), the data driver (130), the voltage generator (140), the controller (150), and the sweep providing circuit (160) described in connection with FIG. 1 may be disposed in a non-display area (NDA) of the display panel (DP). In embodiments, the gate driver (120) and the sweep providing circuit (160) may be disposed in the non-display area (NDA). The data driver (130), the voltage generator (140), and the controller (150) may be implemented as a driver integrated circuit (DIC) described in connection with FIG. 1 that is separate (or distinct) from, but electrically connected to, the display panel (DP), and the driver integrated circuit (DIC) may be electrically connected to wires disposed in the non-display area (NDA). In other embodiments, the gate driver (120) may be implemented as a single integrated circuit separate from (or distinct from) the display panel (DP) together with the data driver (130), voltage generator (140), and controller (150). However, the embodiments of the present disclosure are not limited thereto.

[0088] In embodiments, the display area (DA) may have various shapes when viewed from a third direction (DR3). The display area (DA) may have a closed loop shape including straight and / or curved edges. For example, the display area (DA) may have shapes such as a polygon, a circle, a semicircle, or an ellipse when viewed from the third direction (DR3).

[0089] In embodiments, the display panel (DP) may have a flat display surface. In other embodiments, the display panel (DP) may have a display surface that is at least partially rounded or curved in an imaginary plane that is parallel (or substantially parallel) to the first direction (DR1)-second direction (DR2) plane. In embodiments, the display panel (DP) may be bendable, foldable, flexible, twistable, and / or rollable. In such cases, the display panel (DP) and / or the substrate of the display panel (DP) may include one or more materials having flexible properties.

[0090] FIG. 3 is a block diagram showing an embodiment of a sub-pixel (SP) of the display device (DD) of FIG. 1.

[0091] In Fig. 3, among the sub-pixels (SP) described in connection with Fig. 1, sub-pixels (SPij) arranged in the ith row (i is an integer greater than or equal to 1 and less than or equal to m) and the jth column (j is an integer greater than or equal to 1 and less than or equal to n) are exemplarily illustrated.

[0092] Referring to FIG. 3, a sub-pixel (SPij) may include a sub-pixel circuit (SPC) and a light-emitting element (LD).

[0093] A light emitting element (LD) can be electrically connected between a first power supply voltage node (VDDN) and a second power supply voltage node (VSSN). The first power supply voltage node (VDDN) can be electrically connected to one of the power lines (PL) described in connection with Fig. 1 and can receive the first power supply voltage. The second power supply voltage node (VSSN) can be electrically connected to another of the power lines (PL) described in connection with Fig. 1 and can receive a second power supply voltage different from the first power supply voltage. A voltage level of the first power supply voltage can be higher than a voltage level of the second power supply voltage.

[0094] A light emitting element (LD) may be electrically connected between an anode electrode and a cathode electrode. The anode electrode may be electrically connected to a first power voltage node (VDDN) via a sub-pixel circuit (SPC). For example, the anode electrode may be electrically connected to the first power voltage node (VDDN) via one or more transistors included in (or part of) the sub-pixel circuit (SPC). The cathode electrode may be connected to a second power voltage node (VSSN). The light emitting element (LD) may be configured to emit light in response to a current flowing from the anode electrode to the cathode electrode.

[0095] The sub-pixel circuit (SPC) may be electrically connected to an i-th gate line (GLi) among the first to m-th gate lines (GL1 to GLm) described in connection with FIG. 1, and to a j-th data line (DLj) among the first to n-th data lines (DL1 to DLn) described in connection with FIG. 1. In response to a gate signal received through the i-th gate line (GLi), the sub-pixel circuit (SPC) may control a light-emitting element (LD) to emit light according to a data signal received through the j-th data line (DLj). In embodiments, the sub-pixel circuit (SPC) may be electrically connected to a sweep line (SWL) described in connection with FIG. 1.

[0096] A sub-pixel circuit (SPC) may include circuit elements, such as transistors and one or more capacitors.

[0097] The transistors of the sub-pixel circuit (SPC) may include P-type transistors and / or N-type transistors. In embodiments, the transistors of the sub-pixel circuit (SPC) may include MOSFETs (Metal Oxide Silicon Field Effect Transistors). In embodiments, the transistors of the sub-pixel circuit (SPC) may include amorphous silicon semiconductors, monocrystalline silicon semiconductors, polycrystalline silicon semiconductors, oxide semiconductors, and the like.

[0098] FIG. 4 is an embodiment of a sub-pixel circuit (SPC) according to embodiments.

[0099] Referring to FIG. 4, a sub-pixel circuit (SPC) according to embodiments of the present disclosure may be a sub-pixel (SPij) located in an i-th row and a j-th column. The sub-pixel circuit (SPC) of the sub-pixel (SPij) located in an i-th row and a j-th column may include a pulse width modulation circuit (PWMC) and a pixel driving circuit (PDC).

[0100] A pulse width modulation circuit (PWMC) can be connected to a first power line (PL1) and a second power line (PL2).

[0101] A first power supply voltage (VDD1) may be applied to a first power supply line (PL1). The first power supply voltage may be a relatively high voltage. A second power supply voltage (VINT) may be applied to a second power supply line (PL2).

[0102] A pulse width modulation circuit (PWMC) may be electrically connected to an ith gate line (GLi). The ith gate line (GLi) may include a first gate line (SCL1i), a second gate line (SCL2), a third gate line (SCL3), and an emission control line (EML). In one embodiment, the ith gate line (GLi) may include a sweep line (SWL).

[0103] The first gate line (SCL1i) may be arranged in rows (e.g., pixel row units). The first gate line (SCL1i) may correspond to the first gate line (SCL1i) located in the i-th row. A first scan signal (GW[i]) may be written to the first gate line (SCL1i).

[0104] The second gate line (SCL2) may be electrically connected in common to a plurality of rows (or a plurality of pixel rows). Depending on the embodiment, the second gate line (SCL2) may be arranged in units of rows (or units of pixel rows). For convenience of explanation, an embodiment in which the second gate line (SCL2) is electrically connected in common to a plurality of rows is described below as an example. A second scan signal (GI1) may be written to the second gate line (SCL2).

[0105] The third gate line (SCL3) may be electrically connected in common to a plurality of rows (or a plurality of pixel rows). Depending on the embodiment, the third gate line (SCL3) may be arranged in units of rows (or units of pixel rows). For convenience of explanation, an embodiment in which the third gate line (SCL3) is electrically connected in common to a plurality of rows is described below as an example. A third scan signal (GI2) may be written to the third gate line (SCL3).

[0106] The light emission control line (EML) may be electrically connected in common to a plurality of rows (or a plurality of pixel rows). In some embodiments, the light emission control line (EML) may be arranged in units of rows (or units of pixel rows). For convenience of explanation, an embodiment in which the light emission control line (EML) is electrically connected in common to a plurality of rows is described below as an example. A first light emission control signal (EM1) may be written to the light emission control line (EML).

[0107] A sweep line (SWL) may be electrically connected to a plurality of rows (or a plurality of pixel rows). In some embodiments, the sweep line (SWL) may be arranged in units of rows (or units of pixel rows). For convenience of explanation, an embodiment in which the sweep line (SWL) is electrically connected to a plurality of rows is described below as an example. A sweep signal (SWEEP) may be written to the sweep line (SWL).

[0108] A pulse width modulation circuit (PWMC) may be electrically connected to a j-th data line (DLj). The j-th data line (DLj) may correspond to a j-th data line (DLj) located in a j-th column (or a j-th sub-pixel column). A data voltage (DATA_PWM) may be written to the j-th data line (DLj) located in the j-th column.

[0109] A pulse width modulation circuit (PWMC) can be electrically connected to a pixel driver circuit (PDC) via a connecting electrode (CNE).

[0110] A second emission control signal (EM2) can be written to the connecting electrode (CNE). The width (e.g., pulse width) of the second emission control signal (EM2) can correspond to the voltage value of the data voltage (DATA_PWM).

[0111] A pixel driving circuit (PDC) may be electrically connected to a light emitting element (LD). The pixel driving circuit (PDC) may be electrically connected to a third power line (PL3) and a fifth power line (PL5).

[0112] A second power supply voltage (VDD2) may be applied to the third power supply line (PL3). The second power supply voltage (VDD2) may be a relatively high-potential voltage. A fifth power supply voltage (VAINT) may be applied to the fifth power supply line (PL5). The fifth power supply voltage (VAINT) may be a relatively low-potential voltage.

[0113] The pixel driver circuit (PDC) can be electrically connected to the emission control line (EML) and the fourth gate line (SCL4).

[0114] The fourth gate line (SCL4) may be electrically connected in common to a plurality of rows (or a plurality of pixel rows). Depending on the embodiment, the fourth gate line (SCL4) may be arranged in units of rows (or units of pixel rows). For convenience of explanation, an embodiment in which the fourth gate line (SCL4) is electrically connected in common to a plurality of rows is described below as an example. A fourth scan signal (BCB) may be written to the fourth gate line (SCL4).

[0115] The light emitting element (LD) can be electrically connected between the pixel driving circuit (PDC) and the fourth power line (PL4).

[0116] A fourth power supply voltage (VSS) can be applied to the fourth power line (PL4). The fourth power supply voltage (VSS) can be a relatively low voltage.

[0117] The aforementioned ith gate line (GLi) may include a light emission control line (EML), a first gate line (SCL1i), a second gate line (SCL2), a third gate line (SCL3), and a fourth gate line (SCL4).

[0118] FIG. 5 is an example of an equivalent circuit diagram of a pulse width modulation circuit (PWMC) and a pixel driving circuit (PDC) according to embodiments.

[0119] A pulse width modulation circuit (PWMC) according to embodiments of the present disclosure may include a plurality of transistors and at least one capacitor. Referring to FIG. 5, a pulse width modulation circuit (PWMC) according to embodiments of the present disclosure may include first to sixth transistors (TR1 to TR6) and a first capacitor (Cap1). However, embodiments of the present disclosure are not limited thereto.

[0120] A pixel driving circuit (PDC) according to embodiments of the present disclosure may include a plurality of transistors and at least one capacitor. Referring to FIG. 5, a pixel driving circuit (PDC) according to embodiments of the present disclosure may include seventh to tenth transistors (TR7 to TR10) and second and third capacitors (Cap2, Cap3).

[0121] A first transistor (TR1) may include a gate electrode electrically connected to a first node (N1). The first transistor (TR1) may include a first electrode (e.g., one of a source electrode and a drain electrode) electrically connected to a second node (N2) and a second electrode (e.g., the other of the source electrode and the drain electrode) electrically connected to a third node (N3). The first electrode may be, for example, a source electrode. The second electrode may be, for example, a drain electrode. A body electrode of the first transistor (TR1) may be electrically connected to a first power line (PL1). The first transistor (TR1) may be configured to electrically connect between the second node (N2) and the third node (N3) during a period in which a voltage of a first logic level (e.g., a turn-on level) is applied to the first node (N1). Depending on the length of the period in which the first transistor (TR1) is turned on, the width of the second light emission control signal (EM2) output through the connection electrode (CNE) can adaptively vary.

[0122] The second transistor (TR2) may be configured to switch an electrical connection between the j-th data line (DLj) and the third node (N3). The second transistor (TR2) may electrically connect the j-th data line (DLj) and the third node (N3) in response to a first scan signal (GW[i]) of a first logic level (e.g., a turn-on level). The second transistor (TR2) may include a gate electrode electrically connected to the first gate line (SCL1i). The second transistor (TR2) may include a body electrode electrically connected to the first gate line (SCL1i). In response to the second transistor (TR2) being turned on, a data voltage (DATA_PWM) or a voltage corresponding to the data voltage (DATA_PWM) may be applied to the third node (N3).

[0123] A third transistor (TR3) may be configured to switch an electrical connection between a first node (N1) and a second node (N2). The third transistor (TR3) may electrically connect the second node (N2) and the third node (N3) in response to a first scan signal (GW[i]) of a first logic level (e.g., a turn-on level). The third transistor (TR3) may include a gate electrode electrically connected to the first gate line (SCL1i). The third transistor (TR3) may include a body electrode electrically connected to the first gate line (SCL1i). In response to the third transistor (TR3) being turned on, the first transistor (TR1) may be connected in a diode form. As a result, a voltage corresponding to the data voltage (DATA_PWM) applied to the third node (N3) may be stored in the first node (N1). The third transistor (TR3) can perform a function of compensating for changes in the characteristics of the first transistor (TR1) (e.g., changes in threshold voltage, etc.).

[0124] A first capacitor (Cap1) may include a first electrode (E11) electrically connected to a first node (N1) and a second electrode (E12) electrically connected to a sweep line (SWL). A sweep signal (SWEEP) may be applied to the second electrode (E12). When the voltage of the second electrode (E12) changes in response to the sweep signal (SWEEP) applied to the second electrode (E12), the voltage change of the first electrode (E11) may change due to the effect of maintaining the amount of charge stored in the first capacitor (Cap1). Accordingly, the voltage of the first node (N1) may change (e.g., change sequentially) in response to the sweep signal (SWEEP).

[0125] A fourth transistor (TR4) may be configured to switch an electrical connection between a first power line (PL1) and a third node (N3). The fourth transistor (TR4) may electrically connect the first power line (PL1) and the third node (N3) in response to a first emission control signal (EM1) of a first logic level (e.g., a turn-on level). The fourth transistor (TR4) may include a gate electrode electrically connected to the emission control line (EML). In response to the fourth transistor (TR4) being turned on, a first power voltage (VDD1) or a voltage corresponding to the first power voltage (VDD1) may be applied to the third node (N3). As a result, current may flow from the first power line (PL1) in the direction of the first transistor (TR1).

[0126] The fifth transistor (TR5) may be configured to switch an electrical connection between the second node (N2) and the fourth node (N4). The fifth transistor (TR5) may electrically connect the second node (N2) and the fourth node (N4) in response to a first emission control signal (EM1) of a first logic level (e.g., a turn-on level). The fifth transistor (TR5) may include a gate electrode electrically connected to an emission control line (EML). In response to the fifth transistor (TR5) being turned on, current may flow from the first power line (PL1) toward the fourth node (N4). Accordingly, the second emission control signal (EM2) may be applied to the connection electrode (CNE), so that the connection electrode (CNE) may be electrically connected to the fourth node (N4).

[0127] The sixth transistor (TR6) may be configured to switch an electrical connection between the first node (N1) and the fifth node (N5). The sixth transistor (TR6) may electrically connect the first node (N1) and the fifth node (N5) in response to a second scan signal (GI1) of a first logic level (turn-on level). The sixth transistor (TR6) may include a gate electrode electrically connected to the second gate line (SCL2). The fifth node (N5) may be electrically connected to the second power line (PL2). The sixth transistor (TR6) may include a body electrode electrically connected to the second gate line (SCL2). In response to the sixth transistor (TR6) being turned on, a second power voltage (VINT) may be applied to the first node (N1). As a result, the voltage of the first node (N1) may be initialized to the second power voltage (VINT).

[0128] The pixel driver circuit (PDC) may include seventh to tenth transistors (TR7 to TR10) and second and third capacitors (Cap2, Cap3).

[0129] The seventh transistor (TR7) may include a gate electrode electrically connected to the connection electrode (CNE). The seventh transistor (TR7) may include a first electrode (e.g., one of the source electrode and the drain electrode) electrically connected to the eighth transistor (TR8) and a second electrode (e.g., the other of the source electrode and the drain electrode) electrically connected to the sixth node (N6). For example, the first electrode may be the source electrode and the second electrode may be the drain electrode. The seventh transistor (TR7) may include a body electrode electrically connected to the third power line (PL3). In response to the seventh transistor (TR7) being turned on, the eighth transistor (TR8) and the sixth node (N6) may be electrically connected.

[0130] The eighth transistor (TR8) may be configured to switch an electrical connection between a third power line (PL3) and the seventh transistor (TR7). The eighth transistor (TR8) may electrically connect the third power line (PL3) and the seventh transistor (TR7) in response to a first emission control signal (EM1) of a first logic level (e.g., a turn-on level). The eighth transistor (TR8) may include a gate electrode electrically connected to the emission control line (EML). In response to the eighth transistor (TR8) being turned on, current may flow from the third power line (PL3) toward the seventh transistor (TR7).

[0131] The ninth transistor (TR9) may be configured to switch an electrical connection between a second power line (PL2) and a fourth node (N4). The ninth transistor (TR9) may electrically connect the second power line (PL2) and the fourth node (N4) in response to a third scan signal (GI2) of a first logic level (e.g., a turn-on level). The ninth transistor (TR9) may include a gate electrode electrically connected to a third gate line (SCL3). The ninth transistor (TR9) may include a body electrode electrically connected to the third gate line (SCL3). In response to the ninth transistor (TR9) being turned on, a second power voltage (VINT) may be applied to the fourth node (N4). The voltage of the fourth node (N4) may be initialized to the second power voltage (VINT).

[0132] The tenth transistor (TR10) may be configured to switch an electrical connection between a fifth power line (PL5) and a sixth node (N6). The tenth transistor (TR10) may electrically connect the fifth power line (PL5) and the sixth node (N6) in response to a fourth scan signal (BCB) of a first logic level (e.g., a turn-on level). The tenth transistor (TR10) may include a gate electrode electrically connected to a fourth gate line (SCL4). In response to the tenth transistor (TR10) being turned on, a fifth power voltage (VAINT) may be applied to the sixth node (N6). The voltage of the sixth node (N6) may be initialized to the fifth power voltage (VAINT).

[0133] The second capacitor (Cap2) may include a first electrode (E21) electrically connected to a third power line (PL3) and a second electrode (E22) electrically connected to a fourth node (N4). The second capacitor (Cap2) may be configured to maintain a voltage difference between the third power line (PL3) and the fourth node (N4).

[0134] The third capacitor (Cap3) may include a first electrode (E31) electrically connected to a fourth node (N4) and a second electrode (E32) electrically connected to a sixth node (N6). The third capacitor (Cap3) may be configured to maintain a voltage difference between the fourth node (N4) and the sixth node (N6).

[0135] The light emitting element (LD) may be electrically connected between the sixth node (N6) and the fourth power line (PL4). The light emitting element (LD) may include a first electrode (e.g., an anode electrode) electrically connected to the sixth node (N6) and a second electrode (e.g., a cathode electrode) electrically connected to the fourth power line (PL4). In response to the seventh transistor (TR7) and the eighth transistor (TR8) being turned on, a current may flow from the third power line (PL3) to the fourth power line (PL4) in the light emitting element (LD).

[0136] Each of the first to tenth transistors (TR1 to TR10) according to the embodiments may be configured as a transistor including a P-type semiconductor layer or a transistor including an N-type semiconductor layer. Referring to FIG. 5, the first, fourth, fifth, seventh, eighth, and tenth transistors (TR1, TR4, TR5, TR7, TR8, TR10) may be configured as transistors including a P-type semiconductor layer. The second, third, sixth, and ninth transistors (TR2, TR3, TR6, TR9) may be configured as transistors including an N-type semiconductor layer. However, the embodiments are not limited thereto.

[0137] A transistor including a P-type semiconductor layer may include, for example, a silicon semiconductor (e.g., a polycrystalline silicon semiconductor). A transistor including an N-type semiconductor layer may include, for example, a metal oxide semiconductor. However, the embodiments are not limited thereto.

[0138] The metal oxide semiconductor may include, for example, indium gallium zinc oxide (IGZO), but embodiments are not limited thereto.

[0139] Meanwhile, the second power supply voltage (VINT) can be applied with voltages of different magnitudes depending on the sub-pixel (SP) within one pixel (PXL). Accordingly, the widths of the second emission control signal (EM2) can be controlled differently in the red sub-pixel (e.g., the first sub-pixel (SP1)), the green sub-pixel (e.g., the second sub-pixel (SP2)), and the blue sub-pixel (e.g., the third sub-pixel (SP3)).

[0140] Since the widths of the second emission control signals (EM2) are controlled differently in the red sub-pixel, the green sub-pixel, and the blue sub-pixel, the widths of the second emission control signals (EM2) may be different even for data voltages (DATA_PWM) of the same size (or the same voltage level). Accordingly, the emission times of the red sub-pixel, the green sub-pixel, and the blue sub-pixel of the corresponding pixel (PXL) may be controlled differently, which may have the same effect as performing gamma correction with different gamma values ​​depending on the sub-pixels.

[0141] However, in the above embodiment, it is required to arrange multiple second power lines (PL2) to apply different magnitudes of second power voltages (VINT) to each sub-pixel. As will be more clearly seen below, the multiple second power lines (PL2) can be arranged more efficiently.

[0142] Fig. 6 is a first (e.g., lower) layout drawing of sub-pixels (SP1, SP2, SP3) according to embodiments. Fig. 7 is a second (e.g., upper) layout drawing of sub-pixels (SP1, SP2, SP3) according to embodiments of the present disclosure.

[0143] In the layout drawings of FIGS. 6 and 7, each of the first sub-pixel (SP1), the second sub-pixel (SP2), and the third sub-pixel (SP3) may include a pulse width modulation circuit (PWMC), a pixel driving circuit (PDC), and a connection electrode (CNE) as illustrated in the equivalent circuit diagram of FIG. 5.

[0144] Referring to FIG. 6, a pixel driving circuit (PDC) and a pulse width modulation circuit (PWMC) may be positioned adjacent to each other in a second direction (DR2). A connection electrode (CNE) may be configured to extend in the second direction (DR2) to electrically connect the pixel driving circuit (PDC) and the pulse width modulation circuit (PWMC) to each other.

[0145] The first sub-pixel (SP1) may correspond to a red sub-pixel. The second sub-pixel (SP2) may correspond to a green sub-pixel. The third sub-pixel (SP3) may correspond to a blue sub-pixel. The first to third sub-pixels (SP1 to SP3) may be adjacent in the first direction (DR1).

[0146] Referring to FIGS. 6 and 7, a first active pattern layer (ACT1), a first gate electrode layer (GAT1), a second gate electrode layer (GAT2), a second active pattern layer (ACT2), a third gate electrode layer (GAT3), a first source-drain electrode layer (SD1), and a second source-drain electrode layer (SD2) can be sequentially stacked on each other.

[0147] The first active pattern layer (ACT1) may be composed of a silicon semiconductor (e.g., a polycrystalline silicon semiconductor). The first active pattern layer (ACT1) may include a channel region. The source region and the drain region of the first active pattern layer may be spaced apart from each other with the channel region interposed therebetween.

[0148] The first gate electrode layer (GAT1) may be positioned to overlap with the channel region of the first active pattern layer (ACT1), for example, may overlap with the channel region of the first active pattern layer (ACT1) in the third direction (DR3). The first gate electrode layer (GAT1) may include at least one metal material. For example, the first gate electrode layer (GAT1) may be formed of at least one metal such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), tungsten (W), or an alloy of the aforementioned metal materials. According to an embodiment, the first gate electrode layer (GAT1) may be formed as a single layer, or may be formed as a multilayer in which two or more materials of the metals and alloys are stacked.

[0149] A first gate insulating layer (not shown) may be disposed between the first gate electrode layer (GAT1) and the first active pattern layer (ACT1) (e.g., stacked in the third direction). The first gate insulating layer may include at least one inorganic insulating layer including at least one inorganic material. The first gate insulating layer may include silicon oxide (SiO2), silicon nitride (SiN x ) (x is a positive number), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO x ) may include inorganic insulators such as zinc oxide. The zinc oxide may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2). However, the embodiments are not limited thereto.

[0150] A second gate electrode layer (GAT2) may be positioned on a first gate electrode layer (GAT1). The first gate electrode layer (GAT1) and the second gate electrode layer (GAT2) may constitute a first electrode and a second electrode of a capacitor, respectively. The second gate electrode layer (GAT2) may include a metal. For example, the second gate electrode layer (GAT2) may be formed of at least one metal, such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and tungsten (W), or an alloy of at least one of the aforementioned metals. According to an embodiment, the second gate electrode layer (GAT2) may be formed as a single layer, or may be formed as a multilayer in which two or more materials of the metals and alloys are stacked on each other.

[0151] A second gate insulating layer (not shown) may be disposed between the first gate electrode layer (GAT1) and the second gate electrode layer (GAT2) (e.g., stacked in the third direction). The second gate insulating layer may include at least one inorganic insulating layer including one or more inorganic materials. The second gate insulating layer may include silicon oxide (SiO2), silicon nitride (SiN x ) (x is a positive number), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and / or zinc oxide (ZnO x ) may include inorganic insulators such as zinc oxide. The zinc oxide may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2). However, the embodiments are not limited thereto.

[0152] A first interlayer insulating layer (not shown) may be provided on the second gate electrode layer (GAT2). The first interlayer insulating layer may be an inorganic insulating layer comprising at least one inorganic material. The at least one inorganic material may include polysiloxane, silicon nitride, silicon oxide, and / or silicon oxynitride. However, the embodiments are not limited thereto.

[0153] A second active pattern layer (ACT2) may be positioned on the first interlayer insulating layer. In one embodiment, the second active pattern layer (ACT2) may be formed of an oxide semiconductor. The second active pattern layer (ACT2) may include a metal oxide semiconductor. For example, the second active pattern layer (ACT2) may include indium gallium zinc oxide (IGZO), but embodiments are not limited thereto. The second active pattern layer (ACT2) may be doped with an N-type impurity. Examples of the N-type impurity may include phosphorus (P), arsenic (As), antimony (Sb), etc. For example, the second active pattern layer (ACT2) may be formed by depositing a metal oxide using a sputtering method and etching (e.g., dry etching). However, embodiments are not limited thereto. The second active pattern layer (ACT2) may include a channel region. The source region and drain region of the second active pattern layer (ACT2) can be spaced apart from each other with a channel region therebetween.

[0154] The third gate electrode layer (GAT3) may overlap with the channel region of the second active pattern layer (ACT2), for example, the third gate electrode layer (GAT3) may overlap with the channel region of the second active pattern layer (ACT2) in the third direction. The third gate electrode layer (GAT3) may include at least one metal. For example, the third gate electrode layer (GAT3) may be formed of at least one metal selected from the group consisting of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and tungsten (W), or an alloy of at least one of the aforementioned metals. According to an embodiment, the third gate electrode layer (GAT3) may be formed as a single layer, or may be formed as a multilayer in which two or more materials of the metals and alloys are stacked on each other.

[0155] A second interlayer insulating layer (not shown) may be provided on the third gate electrode layer (GAT3). The second interlayer insulating layer may be an inorganic insulating layer comprising at least one inorganic material. The at least one inorganic material may include polysiloxane, silicon nitride, silicon oxide, and / or silicon oxynitride. However, the embodiments are not limited thereto.

[0156] A first source-drain electrode layer (SD1) may be provided on the second interlayer insulating layer. The source electrode and the drain electrode of the first source-drain electrode layer (SD1) may be electrically connected to the corresponding first active pattern layer (ACT1) or the second active pattern layer (ACT2). For example, the electrode of the first source-drain electrode layer (SD1) may be electrically connected to the source region of the first active pattern layer (ACT1) or the drain region of the first active pattern layer (ACT1). In embodiments, the electrode of the first source-drain electrode layer (SD1) may be electrically connected to the source region of the second active pattern layer (ACT2) or the drain region of the second active pattern layer (ACT2).

[0157] The first source-drain electrode layer (SD1) may include a metal. The first source-drain electrode layer (SD1) may include a material having relatively excellent conductivity. For example, the first source-drain electrode layer (SD1) may include a conductive material, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The first source-drain electrode layer (SD1) may be formed as a multilayer structure or a single-layer structure including at least one of the above materials. For example, the first source-drain electrode layer (SD1) may have a multilayer structure of Ti / Al / Ti.

[0158] A first via layer (not shown) may be provided on the first source-drain electrode layer (SD1). For example, the first via layer may be an organic insulating layer including at least one organic material. The at least one organic material may include, for example, at least one of a general-purpose polymer such as polymethylmethacrylate or polystyrene, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, and a vinyl alcohol polymer. The first via layer may perform a function of planarizing an area on the first source-drain electrode layer (SD1).

[0159] A second source-drain electrode layer (SD2) may be provided on the first via layer. The source electrode or the drain electrode of the second source-drain electrode layer (SD2) may be electrically connected to the corresponding source electrode or the drain electrode of the first source-drain electrode layer (SD1). For example, the second source-drain electrode layer (SD2) may be configured to electrically connect the first source electrode or the first drain electrode of the first source-drain electrode layer (SD1) which are positioned to be spaced apart from each other, or to connect the corresponding source electrode or the drain electrode of the first source-drain electrode layer (SD1) with an electrode (e.g., an anode electrode, etc.) of another layer, for example, an upper layer (or, overlying) electrode.

[0160] The second source-drain electrode layer (SD2) may include a metal. The second source-drain electrode layer (SD2) may include a material having relatively excellent conductivity. For example, the second source-drain electrode layer (SD2) may include at least one conductive material, and the conductive material may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. The second source-drain electrode layer (SD2) may be formed as a multilayer structure or a single-layer structure including at least one of the above materials. For example, the second source-drain electrode layer (SD2) may have a multilayer structure of Ti / Al / Ti.

[0161] A second via layer (not shown) may be provided on the second source / drain electrode layer (SD2). For example, the second via layer may be an organic insulating layer including one or more organic materials. The second via layer may include at least one organic insulating material, and the at least one organic insulating material may include at least one of organic insulating materials, such as, for example, general-purpose polymers such as polymethylmethacrylate and polystyrene, polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene polymers, and vinyl alcohol-based polymers. The second via layer may perform a function of planarizing an area on the second source / drain electrode layer (SD2).

[0162] The semiconductor layers of the first, fourth, fifth, seventh, eighth, and tenth transistors (TR1, TR4, TR5, TR7, TR8, TR10) may be formed of respective regions of the first active pattern layer (ACT1). The gate electrodes of the first, fourth, fifth, seventh, eighth, and tenth transistors (TR1, TR4, TR5, TR7, TR8, TR10) may be formed of respective regions of the first gate electrode layer (GAT1).

[0163] The semiconductor layers of the second, third, sixth, and ninth transistors (TR2, TR3, TR6, TR9) may be formed from respective regions of the second active pattern layer (ACT2). The gate electrodes of the second, third, sixth, and ninth transistors (TR2, TR3, TR6, TR9) may be formed from respective regions of the third gate electrode layer (GAT3).

[0164] The first capacitor (Cap1) may be formed of, for example, regions of the first gate electrode layer (GAT1) and the second gate electrode layer (GAT2) that overlap and face each other in the third direction (DR3). Referring further to FIG. 5, the first capacitor (Cap1) may include a first electrode (E11) formed of a region of the first gate electrode layer (GAT1) and a second electrode (E12) formed of a region of the second gate electrode layer (GAT2).

[0165] The second capacitor (Cap2) may be composed of, for example, a first gate electrode layer (GAT1) and a second gate electrode layer (GAT2) that overlap and face each other in the third direction (DR3). Referring further to FIG. 5, the second capacitor (Cap2) may include a first electrode (E21) composed of an area of ​​the second gate electrode layer (GAT2) and a second electrode (E22) composed of an area of ​​the first gate electrode layer (GAT1).

[0166] The third capacitor (Cap3) may be composed of, for example, a first gate electrode layer (GAT1) and a second gate electrode layer (GAT2) that overlap and face each other in the third direction (DR3). Referring further to FIG. 5, the third capacitor (Cap3) may include a first electrode (E31) composed of an area of ​​the first gate electrode layer (GAT1) and a second electrode (E32) composed of an area of ​​the second gate electrode layer (GAT2).

[0167] A first transistor (TR1) may include a semiconductor layer formed of a region of a first active pattern layer (ACT1). The first transistor (TR1) may include a gate electrode formed of a corresponding region of a first gate electrode layer (GAT1). The first active pattern layer (ACT1) of the first transistor (TR1) may include a channel region overlapping the first gate electrode layer (GAT1), for example, overlapping in a third direction (DR3). The first active pattern layer (ACT1) of the first transistor (TR1) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. Each region of the first active pattern layer (ACT1) of the first transistor (TR1) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a second node (N2) and a third node (N3).

[0168] The second transistor (TR2) may include a semiconductor layer formed of a region of a second active pattern layer (ACT2). The second transistor (TR2) may include a gate electrode formed of a region of a third gate electrode layer (GAT3). The second active pattern layer (ACT2) of the second transistor (TR2) may include a channel region that overlaps the third gate electrode layer (GAT3), for example, overlaps in a third direction (DR3). The second active pattern layer (ACT2) of the second transistor (TR2) may include a source region and a channel region, and the source region and the channel region may be spaced apart from each other with the channel region therebetween. Each region of the second active pattern layer (ACT2) of the second transistor (TR2) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a data voltage supply node (Nvdata) and a third node (N3).

[0169] The third transistor (TR3) may include a semiconductor layer formed of a region of the second active pattern layer (ACT2). The third transistor (TR3) may include a gate electrode formed of a corresponding region of the third gate electrode layer (GAT3). The second active pattern layer (ACT2) of the third transistor (TR3) may include a channel region that overlaps the third gate electrode layer (GAT3), for example, overlaps in a third direction (DR3). The second active pattern layer (ACT2) of the third transistor (TR3) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. Each region of the second active pattern layer (ACT2) of the third transistor (TR3) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a first node (N1) and a second node (N2).

[0170] The fourth transistor (TR4) may include a semiconductor layer formed of a region of the first active pattern layer (ACT1). The fourth transistor (TR4) may include a gate electrode formed of a region of the first gate electrode layer (GAT1). The first active pattern layer (ACT1) of the fourth transistor (TR4) may include a channel region overlapping the first gate electrode layer (GAT1), for example, overlapping in a third direction (DR3). The first active pattern layer (ACT1) of the fourth transistor (TR4) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. The first region of the first active pattern layer (ACT1) of the fourth transistor (TR4) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a third node (N3). A second region of the first active pattern layer (ACT1) of the fourth transistor (TR4) can be electrically connected to a first power line (PL1) formed by a region of the first source-drain electrode layer (SD1).

[0171] The fifth transistor (TR5) may include a semiconductor layer formed of a region of the first active pattern layer (ACT1). The fifth transistor (TR5) may include a gate electrode formed of a region of the first gate electrode layer (GAT1). The first active pattern layer (ACT1) of the fifth transistor (TR5) may include a channel region overlapping the first gate electrode layer (GAT1), for example, overlapping in a third direction (DR3). The first active pattern layer (ACT1) of the fifth transistor (TR5) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. Each region of the first active pattern layer (ACT1) of the fifth transistor (TR5) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a second node (N2) and a fourth node (N4).

[0172] The sixth transistor (TR6) may include a semiconductor layer formed of a region of the second active pattern layer (ACT2). The sixth transistor (TR6) may include a gate electrode formed of a region of the third gate electrode layer (GAT3). The second active pattern layer (ACT2) of the sixth transistor (TR6) may include a channel region that overlaps the third gate electrode layer (GAT3), for example, overlaps in a third direction (DR3). The second active pattern layer (ACT2) of the sixth transistor (TR6) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. Each region of the second active pattern layer (ACT2) of the sixth transistor (TR6) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a first node (N1) and a fourth node (N4).

[0173] The seventh transistor (TR7) may include a semiconductor layer formed of a region of a first active pattern layer (ACT1). The seventh transistor (TR7) may include a gate electrode formed of a region of a first gate electrode layer (GAT1). The first active pattern layer (ACT1) of the seventh transistor (TR7) may include a channel region overlapping the first gate electrode layer (GAT1), for example, overlapping in a third direction (DR3). The first active pattern layer (ACT1) of the seventh transistor (TR7) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. The first region of the first active pattern layer (ACT1) of the seventh transistor (TR7) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with the sixth node (N6). The second region of the first active pattern layer (ACT1) of the seventh transistor (TR7) may extend from a corresponding region formed in association with the first active pattern layer (ACT1) of the eighth transistor (TR8). However, according to an embodiment, the second region of the first active pattern layer (ACT1) of the seventh transistor (TR7) may also be electrically connected to a corresponding region of the first active pattern layer (ACT1) of the eighth transistor (TR8) through another region of the first source-drain electrode layer (SD1).

[0174] The eighth transistor (TR8) may include a semiconductor layer formed of a region of a first active pattern layer (ACT1). The eighth transistor (TR8) may include a gate electrode formed of a region of a first gate electrode layer (GAT1). The first active pattern layer (ACT1) of the eighth transistor (TR8) may include a channel region overlapping the first gate electrode layer (GAT1), for example, overlapping with a third region (DR3). The first active pattern layer (ACT1) of the eighth transistor (TR8) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. The first region of the first active pattern layer (ACT1) of the eighth transistor (TR8) may be electrically connected to a corresponding region of the first source-drain electrode layer in association with a power voltage supply node (Nvdd2). A first region of the first active pattern layer (ACT1) of the eighth transistor (TR8) may extend from a corresponding region of the first active pattern layer (ACT1) of the seventh transistor (TR7). However, according to an embodiment, the first region of the first active pattern layer (ACT1) of the eighth transistor (TR8) may be connected to a corresponding region of the first active pattern layer (ACT1) of the seventh transistor (TR7) through another region of the first source-drain electrode layer (SD1).

[0175] The ninth transistor (TR9) may include a semiconductor layer formed of a region of the second active pattern layer (ACT2). The ninth transistor (TR9) may include a gate electrode formed of a region of the third gate electrode layer (GAT3). The second active pattern layer (ACT2) of the ninth transistor (TR9) may include a channel region that overlaps the third gate electrode layer (GAT3), for example, overlaps in a third direction (DR3). The second active pattern layer (ACT2) of the ninth transistor (TR9) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. Each region of the second active pattern layer (ACT2) of the ninth transistor (TR9) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a fourth node (N4) and a fifth node (N5).

[0176] The tenth transistor (TR10) may include a semiconductor layer formed of a region of a first active pattern layer (ACT1). The tenth transistor (TR10) may include a gate electrode formed of a region of a first gate electrode layer (GAT1). The first active pattern layer (ACT1) of the tenth transistor (TR10) may include a channel region overlapping the first gate electrode layer (GAT1), for example, overlapping in a third direction (DR3). The first active pattern layer (ACT1) of the tenth transistor (TR10) may include a source region and a drain region, and the source region and the drain region may be spaced apart from each other with the channel region therebetween. Each region of the first active pattern layer (ACT1) of the tenth transistor (TR10) may be electrically connected to a corresponding region of the first source-drain electrode layer (SD1) in association with a sixth node (N6) and an anode initialization voltage supply node (Nvaint).

[0177] The first gate line (SCL1i), the second gate line (SCL2), and the third gate line (SCL3) may include an area of ​​the third gate electrode layer (GAT3). The first gate line (SCL1i), the second gate line (SCL2), and the third gate line (SCL3) may extend overall in the first direction (DR1).

[0178] The fourth gate line (SCL4), the emission control line (EML), the first power line (PL1), and the sweep line (SWL) may include an area of ​​the first source-drain electrode layer (SD1).

[0179] A second power voltage (VINT_R) supplied to a first sub-pixel (SP1) (e.g., a red sub-pixel) may be applied to a second power line (PL2a). A second power voltage (VINT_G) supplied to a second sub-pixel (SP2) (e.g., a green sub-pixel) may be applied to a second power line (PL2b). A second power voltage (VINT_B) supplied to a third sub-pixel (SP3) (e.g., a blue sub-pixel) may be applied to a second power line (PL2c).

[0180] The second a, second b, and second c power lines (PL2a, PL2b, PL2c) may each include an area of ​​the third gate electrode layer (GAT3). The second a, second b, and second c power lines (PL2a, PL2b, PL2c) may each extend overall in the first direction (DR1).

[0181] The second power line (PL2a) may include a first bridge pattern (610a). The first bridge pattern (610a) may branch from the second power line (PL2a) and extend in the second direction (DR2) as a whole. Referring to FIG. 6, the first bridge pattern (610a) may be positioned to overlap the third gate line (SCL3), for example, to overlap in the third direction (DR3). The first bridge pattern (610a) may be electrically connected to the fifth node (N5) of the first sub-pixel (SP1).

[0182] The second c power line (PL2c) may include a second bridge pattern (610b). The second bridge pattern (610b) may branch from the second c power line (PL2c) and extend in the second direction (DR2) as a whole. Referring to FIG. 6, the second bridge pattern (610b) may be positioned to overlap the second gate line (SCL2), for example, to overlap in the third direction (DR3). The second bridge pattern (610b) may be electrically connected to the fifth node (N5) of the third sub-pixel (SP3).

[0183] The second power line (PL2b) may be bent around the first bridge pattern (610a) when viewed from the third direction (DR3) and may extend entirely in the first direction (DR1) bypassing the first bridge pattern (610a). The second power line (PL2b) may be bent around the second bridge pattern (610b) when viewed from the third direction (DR3) and may extend entirely in the first direction (DR1) bypassing the second bridge pattern (610b). The second power line (PL2b) may be electrically connected to the fifth node (N5) of the second sub-pixel (SP2).

[0184] Referring to FIGS. 6 and 7, the third a power line (PL3a) may be formed by an area of ​​the first source-drain electrode layer (SD1) and may extend entirely in the first direction (DR1). The third b power line (PL3b) may be formed by an area of ​​the second source-drain electrode layer (SD2) and may extend entirely in the second direction (DR2). The third a power line (PL3a) and the third b power line may be electrically connected at a power voltage supply node (Nvdd2). A third power voltage (VDD2) may be commonly applied to the third a power line (PL3a) and the third b power line (PL3b).

[0185] Referring to FIG. 7, each of the plurality of data lines (DLj, DL(j+1), DL(j+2)) may include a corresponding area of ​​the second source-drain electrode layer (SD2). The plurality of data lines (DLj, DL(j+1), DL(j+2)) may extend overall in the second direction (DR2). A data voltage (DATA_PWM) to be supplied to a sub-pixel electrically connected to the corresponding data line may be applied to each of the plurality of data lines (DLj, DL(j+1), DL(j+2)).

[0186] The jth data line (DLj) may extend overall in the second direction (DR2) and be electrically connected to the second transistor (TR2) of the first sub-pixel (SP1) through the data voltage supply node (Nvdata). The (j+1)th data line (DL(j+1)) may extend overall in the second direction (DR2) and be electrically connected to the second transistor (TR2) of the second sub-pixel (SP2) through the data voltage supply node (Nvdata). The (j+2)th data line (DL(j+2)) may extend overall in the second direction (DR2) and be electrically connected to the second transistor (TR2) of the third sub-pixel (SP3) through the data voltage supply node (Nvdata).

[0187] The fourth power line (PL4) may be formed by an area of ​​the second source-drain electrode layer (SD2) and may extend entirely in the second direction (DR2). A fourth power voltage (VSS) may be applied to the fourth power line (PL4). The fourth power line (PL4) may be electrically connected to (for example, one) electrode (for example, a cathode electrode) of the light-emitting element (LD), which may form a part of the second source-drain electrode layer (SD2).

[0188] The fifth power line (PL5) may be formed by an area of ​​the second source-drain electrode layer (SD2) and may extend entirely in the second direction (DR2). A fifth power voltage (VAINT) may be applied to the fifth power line (PL5). The fifth power line (PL5) may be electrically connected to the tenth transistor (TR10) via an anode initialization voltage supply node (Nvaint).

[0189] In one embodiment, (e.g., one) fifth power line (PL5) may be commonly electrically connected to tenth transistors (TR10) of different sub-pixels that are positioned adjacent to each other, for example, adjacent to each other in the first direction (DR1). For example, referring to FIGS. 6 and 7, the same fifth power line (PL5) may be commonly electrically connected to the tenth transistor (TR10) of the first sub-pixel (SP1) and the tenth transistor (TR10) of the second sub-pixel (SP2) via the anode initialization voltage supply node (Nvaint). However, embodiments are not limited thereto, and the first to third sub-pixels (SP1 to SP3) may be electrically connected to different fifth power lines (PL5), respectively.

[0190] Between the fourth power line (PL4) and the fifth power line (PL5), for example, in the first direction (DR1), an area of ​​the second source-drain electrode layer (SD2) constituting the sixth node (N6) may be located. Referring further to FIG. 5, a part of the second source-drain electrode layer (SD2) constituting the sixth node (N6) may be electrically connected to (for example, one) electrode (for example, an anode electrode) of the light-emitting element (LD), which may constitute a part of the second source-drain electrode layer (SD2).

[0191] According to embodiments, since the seconda power line (PL2a), the secondb power line (PL2b), and the secondc power line (PL2c) can be configured as part of the first source-drain electrode layer (SD1), the resistance of the wires configured as part of the second source-drain electrode layer (SD2) can be reduced. In addition, by electrically connecting the first, second, and third sub-pixels (SP1, SP2, SP3) to the seconda power line (PL2a), the secondb power line (PL2b), and the secondc power line (PL2c), respectively, an effect similar to compensating sub-pixels having different gamma values ​​can be obtained or realized. As a result, display quality can be improved.

[0192] FIG. 8a is an example of bridge patterns (610a, 610b) according to one embodiment of the display panel (DP) according to the embodiments of FIG. 2.

[0193] Referring to FIG. 8A, a first pixel (PXL1), a second pixel (PXL2), a third pixel (PXL3), and a fourth pixel (PXL4) are illustrated. The first pixel (PXL1) and the second pixel (PXL2) may be adjacent to each other in a first direction (DR1). The third pixel (PXL3) and the fourth pixel (PXL4) may be adjacent to each other in the first direction (DR1). The first pixel (PXL1) and the third pixel (PXL3) may be adjacent to each other in a second direction (DR2). The second pixel (PXL2) and the fourth pixel (PXL4) may be adjacent to each other in the second direction (DR2).

[0194] A first pixel (PXL1) may include an i-th sub-pixel (SPij), an i-th (j+1) sub-pixel (SPi(j+1)), and an i-th (j+2) sub-pixel (SPi(j+2)). The i-th sub-pixel (SPij), the i-th (j+1) sub-pixel (SPi(j+1)), and the i-th (j+2) sub-pixel (SPi(j+2)) may be adjacent to each other in the first direction (DR1).

[0195] The second pixel (PXL1) may include an i(j+3)th sub-pixel (SPi(j+3)), an i(j+4)th sub-pixel (SPi(j+4)), and an i(j+5)th sub-pixel (SPi(j+5)). The i(j+3)th sub-pixel (SPi(j+3)), the i(j+4)th sub-pixel (SPi(j+4)), and the i(j+5)th sub-pixel (SPi(j+5)) may be adjacent to each other in the first direction (DR1).

[0196] The third pixel (PXL3) may include the (i+1)jth sub-pixel (SP(i+1)j), the (i+1)(j+1)th sub-pixel (SP(i+1)(j+1)), and the (i+1)(j+2)th sub-pixel (SP(i+1)(j+2)). The (i+1)jth sub-pixel (SP(i+1)j), the (i+1)(j+1)th sub-pixel (SP(i+1)(j+1)), and the (i+1)(j+2)th sub-pixel (SP(i+1)(j+2)) may each be adjacent in the first direction (DR1).

[0197] The fourth pixel (PXL4) may include the (i+1)(j+3)th sub-pixel (SP(i+1)(j+3)), the (i+1)(j+4)th sub-pixel (SP(i+1)(j+4)), and the (i+1)(j+5)th sub-pixel (SP(i+1)(j+5)). The (i+1)(j+3)th sub-pixel (SP(i+1)(j+3)), the (i+1)(j+4)th sub-pixel (SP(i+1)(j+4)), and the (i+1)(j+5)th sub-pixel (SP(i+1)(j+5)) may be adjacent to each other in the first direction (DR1).

[0198] In the first pixel (PXL1), the i-th sub-pixel (SPij) can receive the second power voltage (VINT_R) supplied to the red sub-pixel through the first bridge pattern (610a). The i(j+1)th sub-pixel (SPi(j+1)) can receive the second power voltage (VINT_G) supplied to the green sub-pixel without the bridge pattern. The i(j+2)th sub-pixel (SPi(j+2)) can receive the second power voltage (VINT_B) supplied to the blue sub-pixel through the second bridge pattern (610b).

[0199] Referring to FIG. 8a, the i-th sub-pixel (SPij) located at the far left in the first pixel (PXL1) receives a second power voltage (e.g., the second power voltage (VINT_R) supplied to the red sub-pixel) through the first bridge pattern (610a), the i-th (j+1) sub-pixel (SPi(j+1)) located in the middle receives (e.g., directly receives) the second power voltage (e.g., the second power voltage (VINT_G) supplied to the green sub-pixel) without the bridge pattern, and the i-th (j+2) sub-pixel (SPi(j+2)) located at the far right receives a second power voltage (e.g., the second power voltage (VINT_B) supplied to the blue sub-pixel) through the second bridge pattern (610b).

[0200] As with the first pixel (PXL1), the corresponding second power supply voltage (VINT) can also be supplied to the second pixel (PXL2), the third pixel (PXL3), and the fourth pixel (PXL4).

[0201] FIG. 8b is an example of bridge patterns (610a, 610b) according to another embodiment of the display panel (DP) according to the embodiments of FIG. 2.

[0202] The description of each of the first to fourth pixels (PXL1 to PXL4) and the description of the sub-pixels included in each of the first to fourth pixels (PXL1 to PXL4) are as described in Fig. 8a. Therefore, the description of these is omitted.

[0203] In the first pixel (PXL1), the i-th sub-pixel (SPij) can receive the second power voltage (VINT_R) supplied to the red sub-pixel through the first bridge pattern (610a). The i(j+1)th sub-pixel (SPi(j+1)) can receive the second power voltage (VINT_B) supplied to the blue sub-pixel through the second bridge pattern (610b). The i(j+22)th sub-pixel (SPi(j+2)) can receive the second power voltage (VINT_G) supplied to the green sub-pixel without the bridge pattern.

[0204] In one embodiment, the i-th sub-pixel (SPij) located at the far left in the first pixel (PXL1) receives a second power voltage (e.g., the second power voltage (VINT_R) supplied to the red sub-pixel) through the first bridge pattern (610a), the i-th (j+1) sub-pixel (SPi(j+1)) located in the middle receives a second power voltage (e.g., the second power voltage (VINT_B) supplied to the blue sub-pixel) through the second bridge pattern (610b), and the i-th (j+2) sub-pixel (SPi(j+2)) located at the far right can directly receive a second power voltage (e.g., the second power voltage (VINT_B) supplied to the green sub-pixel) without the bridge pattern.

[0205] As with the first pixel (PXL1), the corresponding second power supply voltage (VINT) can also be supplied to the second pixel (PXL2), the third pixel (PXL3), and the fourth pixel (PXL4).

[0206] The bridge patterns illustrated in FIGS. 8A and 8B are each only one example, and the embodiments are not limited to those described above.

[0207] FIG. 9 is a cross-sectional view showing an embodiment of a display panel (DP) according to the embodiments of FIG. 2.

[0208] Referring to FIG. 9, the display panel (DP) may include not only a substrate (SUB), but also a pixel circuit layer (PCL), a display element layer (DPL), and a light functional layer (LFL), which are sequentially arranged on the substrate (SUB) in a third direction (DR3).

[0209] The substrate (SUB) may be made of an insulating material, such as glass and / or resin. For example, the substrate (SUB) may include a glass substrate. In another application, the substrate (SUB) may include a polyimide (PI) substrate. In another embodiment, the substrate (SUB) may include a silicon wafer substrate formed using a semiconductor process.

[0210] In embodiments, the substrate (SUB) may be formed of a flexible material that can be bent, folded, twisted, or otherwise flexible. In embodiments, the substrate (SUB) may have a single-layer or multi-layer structure. For example, the flexible material may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. In some applications, at least one of the layers of the multilayer structure forming the substrate (SUB) may be formed of a material different from at least one other layer of the multilayer structure, although the embodiments are not limited thereto.

[0211] A pixel circuit layer (PCL) may be disposed on a substrate (SUB), for example, on an upper surface of the substrate (SUB). The pixel circuit layer (PCL) may include insulating layers and active patterns and conductive patterns disposed between at least two insulating layers. The conductive patterns of the pixel circuit layer (PCL) may function as circuit elements, wirings, etc. The conductive patterns may correspond to the first to third gate electrode layers (GAT1 to GAT3) and the first and second source-drain electrode layers (SD1, SD2) described above with reference to FIGS. 6 and 7.

[0212] The circuit elements of the pixel circuit layer (PCL) may include sub-pixel circuits (SPC; see FIG. 3) of each of the sub-pixels (SP) described in connection with FIG. 2. For example, the circuit elements of the pixel circuit layer (PCL) may include the first to tenth transistors (TR1 to TR10) and the first to third capacitors (Cap1 to Cap3) described in connection with FIG. 5. The first and second active pattern layers (ACT1, ACT2), the first to third gate electrode layers (GAT1 to GAT3), and the first and second source-drain electrode layers (SD1, SD2) described with reference to FIGS. 6 and 7 described above may constitute the circuit elements of the pixel circuit layer (PCL).

[0213] The wiring of the pixel circuit layer (PCL) may include wiring electrically connected to the sub-pixels (SP) described in connection with Fig. 2. The wiring of the pixel circuit layer (PCL) may include the first to fifth power lines (PL1 to PL5), the first to fourth gate lines (SCL1i, SCL2, SCL3, SCL4), the data line (DLj), and the sweep line (SWL) described in connection with Fig. 5.

[0214] A display element layer (DPL) may be arranged on a pixel circuit layer (PCL). The display element layer (DPL) may include a light-emitting element for each of the sub-pixels (SP).

[0215] A light-functional layer (LFL) may be disposed on a display element layer (DPL). The light-functional layer (LFL) may include light-converting patterns having color-converting particles and / or scattering particles. For example, the color-converting particles may include quantum dots, quantum rods, and / or the like. For convenience, it is assumed that the color-converting particles are quantum dots. The quantum dots can change the wavelength (or color) of light emitted from the display element layer (DPL). The light-functional layer (LFL) may further include light-scattering patterns having scattering particles. In embodiments, the light-converting patterns and the light-scattering patterns may be omitted.

[0216] The light function layer (LFL) may further include a color filter layer including color filters. The color filter may selectively transmit light of a specific wavelength band (or, a specific color). In embodiments, the color filter layer may be omitted.

[0217] A window may be provided on a light-functional layer (LFL) to protect an exposed surface (or upper surface) of a display panel (DP). The window may be configured to protect the display panel (DP) from external impact. The window may extend from the light-functional layer (LFL) (e.g., be structurally bonded to the light-functional layer (LFL)) via an optically transparent adhesive (or bonding) member. The window may have a multilayer structure selected from a glass substrate, a plastic film, and / or a plastic substrate. This multilayer structure may be formed through a continuous process or an adhesive process that bonds adjacent layers using an adhesive layer. All or a portion of the window may be flexible. Additionally, the window may have a single-layer structure.

[0218] FIG. 10 is a cross-sectional view showing another embodiment of a display panel (DP') according to the embodiments of FIG. 2.

[0219] Referring to FIG. 10, the display panel (DP') may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), an input sensing layer (ISL), and a light function layer (LFL), which may be sequentially stacked in a third direction (DR3). The substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) may be configured similarly to the substrate (SUB), the pixel circuit layer (PCL), the display element layer (DPL), and the light function layer (LFL) described with reference to FIG. 9, respectively. Hereinafter, overlapping descriptions are omitted.

[0220] An input sensing layer (ISL) can detect user input on, adjacent to, or approaching the top surface (or display surface) of a display panel (DP'). The input sensing layer (ISL) may include configurations suitable for detecting external objects, such as a user's hand, a pen, etc. For example, the input sensing layer (ISL) may include touch electrodes.

[0221] FIG. 11 is an orthogonal projection showing an embodiment of one of the pixels (PXL) of FIG. 2.

[0222] Referring to FIG. 11, a pixel (PXL) may include first to third sub-pixels (SP1 to SP3). The first to third sub-pixels (SP1 to SP3) may be arranged in a first direction (DR1). However, the arrangement of the pixels (PXL) is not limited thereto. For example, the arrangement of the pixels (PXL) may vary depending on the configuration of the display panel (DP). For example, the first to third sub-pixels (SP1 to SP3) may be arranged in a zigzag pattern or a pentile pattern. TM ) can be arranged in patterns, etc.

[0223] First to third anode electrodes (AE1 to AE3) may be disposed in the first to third sub-pixels (SP1 to SP3), respectively. The first anode electrode (AE1) may be provided as an electrode electrically connected to a sub-pixel circuit (SPC; for example, see FIG. 3) of the first sub-pixel (SP1). The second anode electrode (AE2) may be provided as an electrode electrically connected to the sub-pixel circuit (SPC) of the second sub-pixel (SP2). The third anode electrode (AE3) may be provided as an electrode electrically connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0224] The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3). The cathode electrode (CE) may be arranged at the same height as the first to third anode electrodes (AE1 to AE3) on the substrate (SUB) described in connection with FIGS. 9 and 10. The cathode electrode (CE) may be spaced apart from the first to third anode electrodes (AE1 to AE3) in a second direction (DR2). In embodiments, the cathode electrode (CE) may extend in the first direction (DR1) and be used as a common electrode for the pixel (PXL) and one or more other pixels adjacent to the pixel (PXL). Although not shown, depending on the embodiment, the cathode electrode (CE) may extend not only in the first direction (DR1) but also in the second direction (DR2), and may be used as a common electrode for all (or at least some) of the adjacent sub-pixels (SP) in the first direction (DR1) and the second direction (DR2) described in connection with FIG. 2. In this way, the cathode electrode (CE) may have various shapes.

[0225] First to third light-emitting elements (LD1 to LD3) may be disposed on first to third anode electrodes (AE1 to AE3) and a cathode electrode (CE). The first light-emitting element (LD1) may be electrically connected to the first anode electrode (AE1) and the cathode electrode (CE). The first light-emitting element (LD1) may be provided as a light-emitting element (LD) electrically connected to a sub-pixel circuit (SPC) of a first sub-pixel (SP1). The second light-emitting element (LD2) may be electrically connected to the second anode electrode (AE2) and the cathode electrode (CE). The second light-emitting element (LD2) may be provided as a light-emitting element (LD) electrically connected to a sub-pixel circuit (SPC) of a second sub-pixel (SP2). The third light-emitting element (LD3) may be electrically connected to the third anode electrode (AE3) and the cathode electrode (CE). The third light-emitting element (LD3) may be provided as a light-emitting element (LD) electrically connected to the sub-pixel circuit (SPC) of the third sub-pixel (SP3).

[0226] The first light-emitting element (LD1), the second light-emitting element (LD2), and the third light-emitting element (LD3) may be inorganic light-emitting diodes including inorganic light-emitting materials. However, the embodiments are not limited thereto. For example, the first to third light-emitting elements (LD1 to LD3) may be organic light-emitting diodes.

[0227] Figure 12 is a cross-sectional view taken along line II' of the pixel of Figure 11.

[0228] Referring to FIGS. 11 and 12, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially arranged in a third direction (DR3) on a substrate (SUB).

[0229] A pixel circuit layer (PCL) may include insulating layers, active pattern layers, and conductive patterns stacked in a third direction (DR3) on a substrate (SUB). The insulating layers may include a buffer layer (BFL), a gate insulating layer (GI), one or more interlayer insulating layers (ILD), and one or more via layers (e.g., first and second via layers PSV1, PSV2). The active pattern layers and the conductive patterns may be positioned between at least two insulating layers. The conductive patterns may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0230] As described with reference to FIG. 5, the sub-pixel circuit (SPC) may include one or more transistors and one or more capacitors. The active pattern layers and conductive patterns of the pixel circuit layer (PCL) may function as transistors and capacitors of the sub-pixel circuit (SPC). Additionally, the conductive patterns of the pixel circuit layer (PCL) may further function as wirings (e.g., transmission lines).

[0231] A buffer layer (BFL) may be disposed on a substrate (SUB) (e.g., on one side), on an upper surface of the substrate (SUB). The buffer layer (BFL) may be disposed on the substrate (SUB) to prevent diffusion of impurities into circuit elements and wirings included in the pixel circuit layer (PCL). The buffer layer (BFL) may include an inorganic insulating layer including at least one inorganic material. In embodiments, the buffer layer (BFL) may include silicon nitride (SiN). x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x) may include at least one of the metal oxides. Here, x and y are natural numbers. The buffer layer (BFL) may be provided as a single layer or multiple layers. When the buffer layer (BFL) is provided as multiple layers, each layer may be formed of the same material or at least one of the multiple layers may be formed of a material different from the other layers.

[0232] In embodiments, one or more barrier layers may be disposed between the substrate (SUB) and the buffer layer (BFL). For example, each of the barrier layers may comprise polyimide.

[0233] A transistor (T_SP1) may be placed on the buffer layer (BFL). The transistor (T_SP1) may be any one of the transistors included in the sub-pixel circuit (SPC) of the first sub-pixel (SP1). For example, the transistor (T_SP1) may correspond to the tenth transistor (TR10) described with reference to FIG. 5.

[0234] The transistor (T_SP1) may include a semiconductor layer (SCP), a gate electrode (GE), a first terminal (ET1), and a second terminal (ET2). The first terminal (ET1) may be either a source electrode or a drain electrode, and the second terminal (ET2) may be the other of the source electrode and the drain electrode. For example, the first terminal (ET1) may be a source electrode, and the second terminal (ET2) may be a drain electrode.

[0235] A semiconductor layer (SCP) may be disposed on a buffer layer (BFL). The semiconductor layer (SCP) may include a first contact region electrically connected to a first terminal (ET1) and a second contact region electrically connected to a second terminal (ET2). A region between the first contact region and the second contact region may be a channel region. The channel region may overlap (e.g., overlap in the third direction (DR3)) with a gate electrode (GE) of the transistor (T_SP1). The channel region may be a semiconductor pattern that is not doped with impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities. As the impurity, for example, a p-type impurity may be used, but embodiments are not limited thereto. For example, an n-type impurity may be used.

[0236] The semiconductor layer (SCP) may include any one of various types of semiconductors, for example, an amorphous silicon semiconductor, a monocrystalline silicon semiconductor, a polycrystalline silicon semiconductor, a low temperature polycrystalline silicon semiconductor, or an oxide semiconductor.

[0237] Interlayer insulating layers (ILDs) may be sequentially stacked on a semiconductor layer (SCP). The interlayer insulating layers (ILDs) may be inorganic insulating layers containing at least one inorganic material. For example, each of the interlayer insulating layers (ILDs) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x) may include at least one of metal oxides, such as x and y. Here, x and y may be natural numbers. However, the interlayer insulating layers (ILDs) are not limited thereto. For example, any one of the interlayer insulating layers (ILDs) may include an organic insulating layer including at least one organic material. In some applications, at least one interlayer insulating layer (ILD) may be formed of a different material from another interlayer insulating layer (ILD).

[0238] Interlayer insulating layers (ILDs) can electrically isolate conductive patterns and / or active pattern layers disposed between the interlayer insulating layers (ILDs). For example, the interlayer insulating layers (ILDs) can include a gate insulating layer (GI) disposed on a semiconductor layer (SCP). The gate insulating layer (GI) can be disposed between the semiconductor layer (SCP) and the gate electrode (GE) such that the gate electrode (GE) is spaced apart from the semiconductor layer (SCP). In embodiments, the gate insulating layer (GI) can be provided over the entire surface of the semiconductor layer (SCP) and the buffer layer (BFL) to cover the semiconductor layer (SCP) and the buffer layer (BFL). As the number of layers used for the conductive patterns and / or semiconductor patterns increases, the number of interlayer insulating layers (ILDs) can increase.

[0239] A gate electrode (GE) may be disposed on a gate insulating layer (GI). The gate electrode (GE) may overlap (e.g., overlap in a third direction (DR3)) a channel region of a semiconductor layer (SCP). In embodiments, the gate electrode (GE) may be provided as a single layer including at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag). In embodiments, the gate electrode (GE) may be provided as a multilayer including at least one material selected from the group consisting of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and silver (Ag), which are relatively low-resistivity materials.

[0240] The first and second terminals (ET1, ET2) may be disposed on interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may be electrically connected to a semiconductor layer (SCP) through contact holes penetrating the interlayer insulating layers (ILD). The first and second terminals (ET1, ET2) may be electrically connected to a source region and a drain region of the semiconductor layer (SCP), respectively. Each of the first and second terminals (ET1, ET2) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0241] In embodiments, the transistor (T_SP1) may be configured as a transistor including a relatively low-temperature polycrystalline silicon semiconductor. However, the embodiments are not limited thereto. For example, the transistor (T_SP1) may also be configured as a transistor including an oxide semiconductor.

[0242] In the embodiments, the transistor (T_SP1) is described as a transistor having a top gate structure, but the embodiments are not limited thereto. For example, the transistor (T_SP1) may be a transistor having a bottom gate structure or a dual gate structure. In the embodiments, the structure of the transistor (T_SP1) may be changed in various ways.

[0243] At least some of the various wirings of the display panel (DP) and / or display device (DD) may be further arranged on the interlayer insulating layers (ILD).

[0244] A first via layer (PSV1) may be arranged on the first and second terminals (ET1, ET2). The via layer may also be referred to as a protective layer or a via layer. The first via layer (PSV1) may protect components arranged under the first via layer (PSV1) and may be configured to provide a uniform (or flat) upper surface.

[0245] A connection pattern (CP) may be arranged on a first via layer (PSV1). The connection pattern (CP1) may be electrically connected to a first terminal (ET1) of a transistor (T_SP1) by penetrating the first via layer (PSV1). The connection pattern (CP) may correspond to an area of ​​a second source-drain electrode layer (SD2) constituting a sixth node (N6) described with reference to FIG. 6. The connection pattern (CP) may include at least one material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), and silver (Ag).

[0246] At least some of the various wirings of the display panel (DP) and / or the display device (DD) may be further arranged on the first via layer (PSV1).

[0247] A second via layer (PSV2) may be disposed on both the connection pattern (CP) and the first via layer (PSV1). The second via layer (PSV2) may be configured to protect components disposed underneath the second via layer (PSV2) and provide a uniform (e.g., flat) upper surface.

[0248] Each of the first and second via layers (PSV1, PSV2) may include an inorganic insulating layer including at least one inorganic material and / or an organic insulating layer including at least one organic material. The inorganic insulating layer may be, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlOx ) may include at least one of metal oxides such as, for example, x and y. Here, x and y may be natural numbers. The organic insulating layer may include at least one of, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0249] In some embodiments, the first and second via layers (PSV1, PSV2) may each include the same material as one of the interlayer insulating layers (ILD). However, embodiments of the present disclosure are not limited thereto. Each of the first and second via layers (PSV1, PSV2) may be provided as a single layer, and may also be provided as multiple layers according to some embodiments. In one embodiment, at least one of the first and second via layers (PSV1, PSV2) may be provided as a single layer, and the remainder of the first and second via layers (PSV1, PSV2) may be provided as multiple layers.

[0250] A display element layer (DPL) may be disposed on the second via layer (PSV2). The display element layer (DPL) may include a first anode electrode (AE1), a cathode electrode (CE), a first bank (BNK1), first and second reflective electrodes (RFE1, RFE2), a first light-emitting element (LD1), an overcoat layer (OCL), a third via layer (PSV3), and a capping layer (CPL). In one embodiment, the display element layer (DPL) may include one or more additional layers.

[0251] A first anode electrode (AE1) and a cathode electrode (CE) can be arranged on the pixel circuit layer (PCL).

[0252] The first anode electrode (AE1) can be electrically connected to the connection pattern (CP) through a contact hole penetrating the second via layer (PSV2). In this way, the first anode electrode (AE1) can be electrically connected to the first transistor (T_SP1).

[0253] The cathode electrode (CE) may be spaced apart from the first anode electrode (AE1) in the second direction (DR2). The cathode electrode (CE) may be electrically connected to the second power voltage node (VSSN) described in connection with FIG. 3. Accordingly, the fourth power voltage (VSS; see FIG. 4) applied to the second power voltage node (VSSN) may be transmitted to the cathode electrode (CE).

[0254] A first bank (BNK1) may be disposed on a first anode electrode (AE1) and a cathode electrode (CE). The first bank (BNK1) may include a first opening (OP1) exposing at least portions of the first anode electrode (AE1) and the cathode electrode (CE). A first light-emitting element (LD1) may be disposed in the first opening (OP1) of the first bank (BNK1). In this way, the first bank (BNK1) may be provided as a pixel definition film defining (or, at least, surrounding) an area in which the first light-emitting element (LD1) is positioned.

[0255] The first bank (BNK1) is configured to include a light-shielding material to prevent (or at least mitigate) light mixing between adjacent sub-pixels. In embodiments, the first bank (BNK1) may include at least one organic material. For example, the first bank (BNK1) may include at least one organic insulating material selected from the group consisting of an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

[0256] A first reflective electrode (RFE1) may be disposed on an exposed portion of the first anode electrode (AE1) and a side surface of the first bank (BNK1) adjacent to the first anode electrode (AE1). A second reflective electrode (RFE2) may be disposed on an exposed portion of the cathode electrode (CE) and a side surface of the first bank (BNK1) adjacent to the cathode electrode (CE). The first and second reflective electrodes (RFE1, RFE2) may include conductive material(s) suitable for reflecting light. Accordingly, the light emission efficiency of the first light-emitting element (LD1) may be improved. In embodiments, the first and second reflective electrodes (RFE1, RFE2) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), and an alloy of two or more materials selected therefrom. However, the embodiments are not limited thereto.

[0257] The first light-emitting element (LD1) is electrically connected to the first anode electrode (AE1) through the first reflective electrode (RFE1). The first light-emitting element (LD1) is electrically connected to the cathode electrode (CE) through the second reflective electrode (RFE2). The first light-emitting element (LD1) may be coupled (or bonded) to the first and second reflective electrodes (RFE1, RFE2). In one embodiment, the first light-emitting element (LD1) may be supported on (or by) the first and second reflective electrodes (RFE1, RFE2), and at least one other layer (e.g., an overcoat layer (OCL)) may fix the position of the first light-emitting element (LD1) relative to the first and second reflective electrodes (RFE1, RFE2).

[0258] The first light-emitting element (LD1) may include a first semiconductor layer (1210), an active layer (1220), a second semiconductor layer (1230), and an auxiliary layer (1250). The first light-emitting element (LD1) may include a light-emitting laminate in which the auxiliary layer (1250), the first semiconductor layer (1210), the active layer (1220), and the second semiconductor layer (1230) are sequentially stacked on each other (e.g., stacked in a third direction (DR3)).

[0259] The first light-emitting element (LD1) may include first and second bonding electrodes (BDE1, BDE2) facing the same direction (e.g., opposite to the third direction (DR3)). The first bonding electrode (BDE1) may be electrically connected to the second semiconductor layer (1230). The second bonding electrode (BDE2) may be electrically connected to the first semiconductor layer (1210) in which corresponding regions of the second semiconductor layer (1230) and the active layer (1220) are etched (or otherwise removed) to expose them. The first light-emitting element (LD1) may be a flip chip type light-emitting element, but embodiments are not limited thereto.

[0260] The first semiconductor layer (1210) is configured to provide electrons to the active layer (1220). The first semiconductor layer (1210) may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer (1210) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge), or tin (Sn). However, the material constituting the first semiconductor layer (1210) is not limited thereto, and various additional materials may also constitute the first semiconductor layer (1210). In one embodiment, the first semiconductor layer (1210) may include a gallium nitride (GaN) semiconductor material doped with a first conductive dopant (or n-type dopant). In some embodiments, the first semiconductor layer (1210) may form an n-type semiconductor layer together with the auxiliary layer (1250).

[0261] The active layer (1220) is disposed on the first semiconductor layer (1210) and can provide a region where electrons and holes recombine. As electrons and holes recombine in the active layer (1220), they transition to a relatively low energy level, and light having a corresponding wavelength can be generated or emitted. The active layer (1220) can be formed in a single or multiple quantum well structure. In an embodiment in which the active layer (1220) is formed in a multiple quantum well structure, portions including a barrier layer, a strain reinforcing layer, and a well layer can be repeatedly stacked to form the active layer (1220). However, embodiments of the active layer (1220) are not limited to those described above.

[0262] The second semiconductor layer (1230) is disposed on the active layer (1220) and can provide holes to the active layer (1220). The second semiconductor layer (1230) may include a semiconductor layer of a different type from the first semiconductor layer (1210). For example, the second semiconductor layer (1230) may include at least one p-type semiconductor layer. For example, the second semiconductor layer (1230) may include at least one semiconductor material among gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and indium nitride (InN), and may be a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like. However, the material constituting the second semiconductor layer (1230) is not limited thereto, and various additional materials may also constitute the second semiconductor layer (1230). In one embodiment of the present disclosure, the second semiconductor layer (1230) may include a gallium nitride (GaN) semiconductor material doped with a second conductive dopant (or p-type dopant).

[0263] The auxiliary layer (1250) may include, for example, an undoped gallium nitride (GaN) semiconductor material and may form an n-type semiconductor layer together with the first semiconductor layer (1210). A dotted line is provided between the auxiliary layer (1250) and the first semiconductor layer (1210) to illustrate a boundary between the auxiliary layer (1250) and the first semiconductor layer (1210). However, it should be noted that a continuum of variably doped gallium nitride (GaN) semiconductor material may exist between the auxiliary layer (1250) and the first semiconductor layer (1210). In any case, the auxiliary layer (1250) may be characterized by an undoped gallium nitride (GaN) semiconductor material.

[0264] The first bonding electrode (BDE1) may be electrically connected to the second semiconductor layer (1230). The second bonding electrode (BDE2) may be electrically connected to the first semiconductor layer (1210). The first and second bonding electrodes (BDE1, BDE2) may include a eutectic metal.

[0265] The first light-emitting element (LD1) may further include an insulating film (1260) configured to cover an outer circumferential surface of the light-emitting stack. The insulating film (1260) may be configured to prevent (or alleviate) an electrical short circuit that may occur when the active layer (1220) comes into contact with a conductive material other than the first and second semiconductor layers (1210, 1230). The insulating film (1260) may include at least one transparent (or at least light-transmitting) insulating material. The insulating film (1260) may expose the lower surfaces of the first and second bonding electrodes (BDE1, BDE2) and may be configured so that the first and second bonding electrodes (BDE1, BDE2) can form a connection with the first and second semiconductor layers (1210, 1230), respectively.

[0266] A lower surface of the first bonding electrode (BDE1) may be electrically connected to a first reflective electrode (RFE1). Accordingly, the first bonding electrode (BDE1) may be electrically connected to a first anode electrode (AE1) via the first reflective electrode (RFE1). A lower surface of the second bonding electrode (BDE2) may be electrically connected to a second reflective electrode (RFE2). Accordingly, the second bonding electrode (BDE2) may be electrically connected to a cathode electrode (CE) via the second reflective electrode (RFE2).

[0267] An overcoat layer (OCL) may be disposed within a first opening (OP1) in which first and second reflective electrodes (RFE1, RFE2) and a first light-emitting element (LD1) are disposed. The overcoat layer (OCL) may be configured to fix the first light-emitting element (LD1) so as to be electrically connected to the first and second reflective electrodes (RFE1, RFE2) and to prevent (or at least reduce the possibility of) relative movement between the first light-emitting element (LD1) and at least one of the first and second reflective electrodes (RFE1, RFE2). In addition, the overcoat layer (OCL) may protect components disposed below the overcoat layer (OCL) from foreign substances such as dust, moisture, and humidity. For example, the overcoat layer (OCL) may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer (OCL) may include an epoxy resin, but embodiments are not limited thereto.

[0268] A third via layer (PSV3) may be disposed on the first bank (BNK1) and the overcoat layer (OCL). The third via layer (PSV3) may protect components disposed under the third via layer (PSV3) and provide a uniform (or flat) upper surface. The third via layer (PSV3) may include the same material as one of the first and second via layers (PSV1, PSV2). However, embodiments are not limited thereto. For example, the third via layer (PSV3) may be formed of a material different from at least one of the first and second via layers (PSV1, PSV2).

[0269] In embodiments, the third via layer (PSV3) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). The first light-emitting element (LD1) may protrude into the light-functional layer (LFL). The first light-emitting element (LD1) may be at least partially positioned within the second opening (OP2) of the second bank (BNK2). For example, the height of the upper surface (LTS) of the first light-emitting element (LD1) in the third direction (DR3) from the substrate (SUB) may be higher than the lowermost end (RBE) of the reflective layer (RFL). Accordingly, light emitted from the first light-emitting element (LD1) may be provided to the light-functional layer (LFL) at a relatively high rate.

[0270] The capping layer (CPL) may be disposed on the third via layer (PSV3). The capping layer (CPL) may protect components under the capping layer (CPL), such as the first light-emitting element (LD1), from external moisture and / or humidity. In embodiments, the capping layer (CPL) may not be disposed on the upper surface (LTS) of the first light-emitting element (LD1). In one embodiment, the capping layer (CPL) may not cover at least a portion of one or more side surfaces (or, side surfaces) of the first light-emitting element (LD1). In other embodiments, the capping layer (CPL) may entirely cover the first light-emitting element (LD1) and the third via layer (PSV3). The capping layer (CPL) may be formed of silicon nitride (SiN). x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ) may include at least one of the metal oxides, wherein x and y may be natural numbers. However, the embodiment of the capping layer (CPL) is not limited to the above.

[0271] The pixel circuit layer (PCL) and display element layer (DPL) of the first sub-pixel (SP1) have been described above. Each of the second and third sub-pixels (SP2, SP3) illustrated in Fig. 11 may also be configured similarly to the first sub-pixel (SP1), unless otherwise described herein.

[0272] A light functional layer (LFL) may be disposed on the capping layer (CPL). The light functional layer (LFL) may include a second bank (BNK2), a reflective layer (RFL), a fourth via layer (PSV4), a first light conversion pattern (CCP1), a low-refractive-index layer (LRL), and / or a color filter layer (CFL).

[0273] A second bank (BNK2) may be disposed on the capping layer (CPL). The second bank (BNK2) may overlap the first bank (BNK1) (e.g., overlap in the third direction (DR3)). The second bank (BNK2) may have a second opening (OP2) that overlaps the first opening (OP1) (e.g., overlaps in the third direction (DR3)). In one embodiment, the center axes of the first and second openings (OP1, OP2) may be aligned with each other in the third direction (DR3). It should be noted that in one embodiment, the first and second openings (OP1, OP2) may be concentrically aligned with each other when viewed in the third direction (DR3). To this end, the cross-sectional area of ​​the second opening (OP2) in the first plane parallel to the first direction (DR1) - second direction (DR2) plane may be larger than the cross-sectional area of ​​the first opening (OP1) in the second plane parallel to the first direction (DR1) - second direction (DR2) plane.

[0274] The second bank (BNK2) is configured to include at least one light-shielding material to prevent (or at least mitigate) light mixing between adjacent sub-pixels. In embodiments, the second bank (BNK2) may include at least one organic material. For example, the second bank (BNK2) may include at least one organic insulating material selected from the group consisting of acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0275] A reflective layer (RFL) may be disposed on side surfaces of the second bank (BNK2) adjacent to (e.g., at least partially surrounding) the second opening (OP2). The reflective layer (RFL) is configured to reflect incident light, thereby improving the light emission efficiency of the display panel (DP). The reflective layer (RFL) may include a material suitable for reflecting light. The reflective layer (RFL) may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), or an alloy of two or more of these materials. However, the embodiments are not limited thereto.

[0276] On the capping layer (CPL), a fourth via layer (PSV4) may be arranged within the second opening (OP2). The fourth via layer (PSV4) may protect components arranged under the fourth via layer (PSV4) and provide a uniform (or flat) upper surface. The fourth via layer (PSV4) may include the same material as any one of the first to third via layers (PSV1 to PSV3). However, embodiments of the present disclosure are not limited thereto. For example, the material of the fourth via layer (PSV4) may be different from the material of at least one of the first to third via layers (PSV1 to PSV3).

[0277] On the fourth via layer (PSV4), a first photo-conversion pattern (CCP1) can be arranged within a second opening (OP2).

[0278] The first light conversion pattern (CCP1) may include color conversion particles and / or scattering particles. The color conversion particles may change the wavelength of incident light to convert the incident light into light of a different color. Additionally, the color conversion particles may scatter the incident light. In embodiments, the color conversion particles may be quantum dots, quantum rods, or the like. The scattering particles may scatter the incident light.

[0279] The first sub-pixel (SP1) may be a red sub-pixel. In an application example in which the first light-emitting element (LD1) emits blue light, the first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. In an application example in which the first light-emitting element (LD1) emits red light, the first light conversion pattern (CCP1) may include scattering particles and not include color conversion particles. In this way, the particles included in the first light conversion pattern (CCP1) may be variously changed depending on the first light-emitting element (LD1).

[0280] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), and the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) may have a lower refractive index than the refractive index of the first light conversion pattern (CCP1). The low-refractive-index layer (LRL) is configured to refract or totally reflect incident light depending on the incident angle of the light. For example, the low-refractive-index layer (LRL) may provide light that has passed through the first light conversion pattern (CCP1) back to the first light conversion pattern (CCP1). Accordingly, the light conversion efficiency of the first light conversion pattern (CCP1) may be improved.

[0281] A color filter layer (CFL) may be disposed on a low refractive index layer (LRL). The color filter layer (CFL) may include a first color filter (CF1) and light-blocking patterns (LBP). The first color filter (CF1) may overlap (e.g., overlap in a third direction (DR3)) the first light conversion pattern (CCP1). The first color filter (CF1) may selectively transmit light of a predetermined wavelength range through the first color filter (CF1). In an application example where the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. The light-blocking patterns (LBP) may include at least one of various types of light-blocking materials. Although described as light blocking patterns (LBP), the light blocking patterns (LBP) may form part of the same light blocking pattern, and the first color filter (CF1) may be disposed in an opening of the light blocking pattern that includes the light blocking patterns (LBP).

[0282] Figure 13 is a cross-sectional view taken along line II-II' of the pixel of Figure 11.

[0283] Referring to FIGS. 11 and 13, a pixel circuit layer (PCL), a display element layer (DPL), and a light function layer (LFL) can be sequentially provided in a third direction (DR3) on a substrate (SUB).

[0284] The pixel circuit layer (PCL) and the display element layer (DPL) can be configured similarly to the pixel circuit layer (PCL) and the display element layer (DP) with reference to FIG. 12. In the pixel circuit layer (PCL), sub-pixel circuits corresponding to the first to third sub-pixels (SP1 to SP3) are provided, respectively. In the display element layer (DPL), first to third light-emitting elements (LD1 to LD3) corresponding to the first to third sub-pixels (SP1 to SP3) are provided, respectively. The first to third light-emitting elements (LD1 to LD3) can overlap (for example, overlap in the third direction (DR3)) the first openings (OP1) of the first bank (BNK1). The first light-emitting element (LD1) may be electrically connected between a cathode electrode (CE; see FIG. 12) and a transistor (T_SP1; see FIG. 12) included in a sub-pixel circuit (SPC) of a first sub-pixel (SP1). The second light-emitting element (LD2) may be electrically connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit (SPC) of a second sub-pixel (SP2). The third light-emitting element (LD3) may be electrically connected between the cathode electrode (CE) and a transistor included in a sub-pixel circuit (SPC) of a third sub-pixel (SP3). Hereinafter, overlapping descriptions are omitted.

[0285] A light functional layer (LFL) may be provided on the display element layer (DPL). The light functional layer (LFL) may be configured similarly to the light functional layer (LFL) of FIG. 12. Hereinafter, redundant descriptions are omitted.

[0286] The second bank (BNK2) may have second openings (OP2). In this way, the second openings (OP2) of the second bank (BNK2) may partially surround the emission areas (EMA) of each of the first to third sub-pixels (SP1 to SP3). The non-emission areas (NEMA) for each (or between) the first to third sub-pixels (SP1 to SP3) may be formed in association with the areas corresponding to the second bank (BNK2). The areas overlapping the second bank (BNK2) in the third direction (DR3) may correspond to the non-emission areas (NEMA). The areas overlapping the second openings (OP2) of the second bank (BNK2) may correspond to the emission areas (EMA) of the first to third sub-pixels (SP1 to SP3).

[0287] On the capping layer (CPL), a fourth via layer (PSV4) may be disposed within the second openings (OP2). On the fourth via layer (PSV4), first and second light conversion patterns (CCP1, CCP2) and a light scattering pattern (LSP) may be disposed within the second openings (OP2).

[0288] In embodiments, the first to third light-emitting elements (LD1 to LD3) may be configured to emit blue light. The first light conversion pattern (CCP1) may include first color conversion particles (QD1) configured to convert blue light into red light. The second light conversion pattern (CCP2) may include second color conversion particles (QD2) configured to convert blue light into green light. The light scattering pattern (LSP) may include scattering particles (SCT) that scatter blue light to improve the light output efficiency of the display panel (DP). Accordingly, the first to third sub-pixels (SP1 to SP3) may be provided as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. In embodiments, at least one of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may further include color conversion particles that convert blue color light into white color light.

[0289] In embodiments, the first to third light-emitting elements (LD1 to LD3) may be configured to emit red, green, and blue light, respectively. In this case, each of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may include scattering particles (SCT). In this way, the particles included in the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be variously changed depending on the first to third light-emitting elements (LD1 to LD3).

[0290] In embodiments, the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP) may be omitted.

[0291] A low-refractive-index layer (LRL) may be disposed on the second bank (BNK2), the reflective layer (RFL), the first light conversion pattern (CCP1), the second light conversion pattern (CCP2), and the light scattering pattern (LSP). The low-refractive-index layer (LRL) may have a lower refractive index than the refractive indices of the first and second light conversion patterns (CCP1, CCP2) and the light scattering pattern (LSP). In embodiments, the low-refractive-index layer (LRL) may be omitted in an area corresponding to the third sub-pixel (SP3) or may be omitted in an area overlapping with the second opening (OP2) formed in association with the third sub-pixel (SP3) in the third direction (DR3).

[0292] A color filter layer (CFL) may be disposed on the low refractive index layer (LRL). The color filter layer (CFL) may include first to third color filters (CF1 to CF3) and light blocking patterns (LBP).

[0293] Each of the first to third color filters (CF1 to CF3) can selectively transmit light of a predetermined wavelength range through the first to third color filters (CF1 to CF3). In an embodiment in which the first sub-pixel (SP1) is a red sub-pixel, the first color filter (CF1) may include a red color filter. In an embodiment in which the second sub-pixel (SP2) is a green sub-pixel, the second color filter (CF2) may include a green color filter. In an embodiment in which the third sub-pixel (SP3) is a blue sub-pixel, the third color filter (CF3) may include a blue color filter. The refractive index of the first to third color filters (CF1 to CF3) may have a refractive index higher than that of the low-refractive-index layer (LRL). However, the embodiments are not limited thereto. For example, the refractive index of at least one of the first to third color filters (CF1 to CF3) may be lower than or equal to that of the low-refractive-index layer (LRL).

[0294] Light blocking patterns (LBP) may be arranged between the first to third color filters (CF1 to CF3). It may be understood that the light emitting area (or light emitting area) (EMA) and the non-light emitting area (NEMA) for the first to third sub-pixels (SP1 to SP3) are at least partially surrounded by the light blocking patterns (LBP). An area overlapping the light blocking patterns (LBP) in the third direction (DR3) may correspond to the non-light emitting area (NEMA). An area not overlapping the light blocking patterns (LBP) may correspond to the light emitting area (EMA).

[0295] In embodiments, the light blocking patterns (LBP) may include at least one of various types of light-blocking materials. In embodiments, each of the light blocking patterns (LBP) may be provided in the form of a multilayer in which at least two color filters among the first to third color filters (CF1 to CF3) overlap in a third direction (DR3). For example, each of the light blocking patterns (LBP) may be formed in such a way that portions of each of the first to third color filters (CF1 to CF3) overlap in the third direction (DR3). As an application example, the light blocking pattern between the first and second color filters (CF1, CF2) among the light blocking patterns (LBP) may be formed in a multilayer in which portions of each of the first and second color filters (CF1, CF2) overlap in the third direction (DR3). Among the light blocking patterns (LBP), the light blocking pattern between the second and third color filters (CF2, CF3) may be formed as a multilayer in which portions of each of the second and third color filters (CF2, CF3) overlap in a third direction (DR3). The light blocking pattern between the first color filter (CF1) and the third color filter (CF3) of an adjacent pixel may be formed as a multilayer in which portions of each of the first and third color filters (CF1, CF3) overlap in a third direction (DR3). In this way, each of the first to third color filters (CF1 to CF3) may extend to the non-emitting area (NEMA) to form the light blocking patterns (LBP).

[0296] Figure 14 is a block diagram showing an embodiment of a display system (1400).

[0297] Referring to FIG. 14, the display system (1400) may include a processor (1410) and a display device (1420). Although only one processor (1410) and one display device (1420) are illustrated, the embodiment is not limited thereto. For example, the display system (1400) may include multiple processors (1410) and / or multiple display devices (1420). The multiple processors (1410) and / or the multiple display devices (1420) may function as part of a whole and / or may function individually. For convenience, it is assumed that the display system (1400) includes one processor (1410) and one display device (1420).

[0298] The processor (1410) can perform various tasks and calculations. In embodiments, the processor (1410) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1410) is communicatively connected to other components of the display system (1400) via a bus system, so that the processor (1410) can control other components.

[0299] The processor (1410) can transmit image data (IMG) and a control signal (CTRL) to the display device (1420). The display device (1420) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1420) can be configured similarly to the display device (DD) described with reference to FIG. 1. In this case, the image data (IMG) and the control signal (CTRL) can be provided as the input image data (IMG) and the control signal (CTRL), respectively, described with reference to FIG. 1.

[0300] The display system (1400) may include a computing system that provides an image display function, such as at least one of a smart watch, a mobile phone, a smart phone, a portable computer, a tablet personal computer, a watch phone, an automotive display, a bulletin board, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra-mobile personal computer (UMPC), etc. In addition, the display system (1400) may include at least one of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0301] FIGS. 15, 16, 17, and 18 are perspective views showing application examples of the display system (1400) of FIG. 14.

[0302] Referring to FIG. 15, the display system (1400) described with reference to FIG. 14 can be applied to (or incorporated into) a smart watch (1500) including a display portion (1510) and a strap portion (1520).

[0303] The smartwatch (1500) may be a wearable electronic device. For example, the smartwatch (1500) may have a structure in which a strap portion (1520) is attached to the user's wrist. Here, a display system (1400) and / or a display device (1420) may be applied to the display portion (1510), so that image data including time information may be provided to the user.

[0304] Referring to FIG. 16, the display system (1400) described with reference to FIG. 14 may be applied to (or incorporated into) an automotive display system (1600). Here, the automotive display system (1600) may include a computing system provided inside and / or outside a vehicle to provide image data.

[0305] For example, the display system (1400) and / or the display device (1420) may be applied to at least one of an infotainment panel (1610), a cluster (1620), a co-driver display (1630), a head-up display (1640), a side mirror display (1650), and a rear seat display (1660), which may be provided inside the vehicle, provided on the vehicle, or projected from the vehicle.

[0306] Referring to FIG. 17, the display system (1400) described with reference to FIG. 14 can be applied to smart glasses (1700). The smart glasses (1700) may be a wearable electronic device that can be worn on a user's head. For example, the smart glasses (1700) may be a wearable device for augmented reality.

[0307] Smart glasses (1700) may include a frame (1710) and a lens unit (1720). The frame (1710) may include a housing (1711) that supports the lens unit (1720) and a leg unit (1712) for a user to wear. The leg unit (1712) may be extended (e.g., movably connected) from the housing (1711) via a hinge, and may be folded or unfolded relative to the housing (1711).

[0308] The frame (1710) may include a battery, a touch pad, a microphone, a camera, etc. In addition, the frame (1710) may include a projector that outputs light, a processor that controls light signals, etc.

[0309] The lens unit (1720) may include an optical member that transmits or reflects light. For example, the lens unit (1720) may include glass, transparent (or light-transmitting) synthetic resin, etc.

[0310] In order for the user's eyes to recognize visual information, the lens unit (1720) can reflect an image by an optical signal transmitted from the projector of the frame (1710) through the rear surface of the lens unit (1720) (e.g., the surface facing the user's eyes). For example, as illustrated in FIG. 17, the user can recognize visual information such as the time and date displayed on the lens unit (1720). At this time, the projector and / or the lens unit (1720) may be a type of display device. The display device (1420; see FIG. 14) may be applied to the projector and / or the lens unit (1720).

[0311] Referring to FIG. 18, the display system (1400) described with reference to FIG. 14 can be applied to a head-mounted display device (1800).

[0312] The head-mounted display device (1800) may be a wearable electronic device that can be worn on a user's head. For example, the head-mounted display device (1800) may be a wearable device for virtual reality or mixed reality.

[0313] A head-mounted display device (1800) may include a head-mounted band (1810) and a display device storage case (1820). The head-mounted band (1810) may extend from the display device storage case (1820) (e.g., be structurally connected to the display device storage case (1820). The head-mounted band (1810) may include horizontal bands and / or vertical bands for securing the head-mounted display device (1800) to a user's head. The horizontal bands may be configured to surround the sides of the user's head, and the vertical bands may be configured to surround the top of the user's head. However, embodiments are not limited thereto. For example, the head-mounted band (1810) may be implemented in the form of eyeglass frames, helmets, etc.

[0314] The display device storage case (1820) can store the display system (1400) and / or the display device (1420).

[0315] While the aforementioned embodiments have been described in some detail for clarity of understanding, it is clear that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems, and devices of the disclosed embodiments. Therefore, the embodiments should be considered illustrative rather than restrictive, and the embodiments should not be limited to the details provided herein.

Claims

1. A first sub-pixel configured to emit light of a first wavelength band; A second sub-pixel positioned in a first direction from the first sub-pixel and configured to emit light of a second wavelength band different from the first wavelength band; A second power line including a bridge pattern extending in the first direction, overlapping the first and second sub-pixels in a third direction intersecting the first direction, and branching in a second direction intersecting the first direction and the third direction, and electrically connected to the first sub-pixel through the bridge pattern; and A display panel including a secondb power line extending in the first direction by bypassing the bridge pattern, positioned to overlap the first and second sub-pixels in the third direction, and electrically connected to the second sub-pixel.

2. In paragraph 1, A display panel in which the second a power line and the second b power line are adjacent to each other in the second direction.

3. In paragraph 1, A display panel in which the above 2a power line and the above 2b power line are configured to apply different levels of power voltage to the first sub-pixel and the second sub-pixel, respectively.

4. In paragraph 1, further comprising a gate line extending in the first direction and electrically connected to both the first and second sub-pixels, A display panel in which the gate line is located between the second a power line and the second b power line in the second direction.

5. In paragraph 4, A display panel in which the bridge pattern is positioned to overlap at least a portion of the gate line in the third direction.

6. In paragraph 1, A display panel in which the second a power line is not electrically connected to the second sub-pixel, and the second b power line is not electrically connected to the first sub-pixel.

7. In paragraph 1, Each of the first and second sub-pixels, A pulse width modulation circuit configured to generate a light emission control signal having a pulse width corresponding to a data signal; A connecting electrode electrically connected to the pulse width modulation circuit and configured to receive the light emission control signal; A pixel driving circuit electrically connected to the above connecting electrode and configured to generate a driving current for a period corresponding to the pulse width of the light emission control signal; and A light-emitting element electrically connected between the pixel driving circuit and the fourth power line, the fourth power line being different from the second a power line and the second b power line, and configured to emit light in response to the driving current, The above 2a power line is electrically connected to the pulse width modulation circuit of the first sub-pixel, A display panel in which the secondb power line is electrically connected to the pulse width modulation circuit of the second sub-pixel.

8. In paragraph 7, The above pulse width modulation circuit, A first transistor comprising a gate electrode electrically connected to a first node and electrically connected between a second node and a third node; A second transistor comprising a gate electrode electrically connected to the first gate line and configured to switch an electrical connection between the third node and the data line; A third transistor comprising a gate electrode electrically connected to the first gate line and configured to switch an electrical connection between the first node and the second node; A fourth transistor comprising a gate electrode electrically connected to a light emitting control line and configured to switch an electrical connection between a first power line and the third node, wherein the first power line is different from the second a power line, the second b power line, and the fourth power line; A fifth transistor comprising a gate electrode electrically connected to the light emission control line and configured to switch an electrical connection between the second node and the fourth node; and A sixth transistor comprising a gate electrode electrically connected to a second gate line different from the first gate line, and configured to switch an electrical connection between the first node and the fifth node, The above 2a power line is electrically connected to the fifth node of the first sub-pixel, A display panel in which the secondb power line is electrically connected to the fifth node of the second sub-pixel.

9. In paragraph 8, Each of the first transistor, the fourth transistor, and the fifth transistor includes a semiconductor layer comprising a corresponding region of the first active pattern layer, Each of the second transistor, the third transistor, and the sixth transistor includes a semiconductor layer composed of a corresponding region of the first active pattern layer and a second active pattern layer that is different from each other, The above first active pattern layer is a P-type semiconductor layer, A display panel in which the second active pattern layer is an N-type semiconductor layer.

10. In paragraph 8, The above connecting electrode is a display panel electrically connected to the fourth node.

11. In paragraph 9, The pulse width modulation circuit includes a first capacitor, A display panel wherein the first capacitor includes a first electrode connected to the first node and a second electrode connected to a sweep line.

12. In paragraph 11, The above pixel driving circuit, A seventh transistor comprising a gate electrode electrically connected to the fourth node and electrically connected to the sixth node; An eighth transistor comprising a gate electrode electrically connected to the light emission control line and configured to switch an electrical connection between a third power line and the seventh transistor, wherein the third power line is different from the first power line, the second a power line, the second b power line, and the fourth power line; A ninth transistor comprising a gate electrode electrically connected to a third gate line, the third gate line being different from both the first gate line and the second gate line, and configured to switch an electrical connection between the fourth node and the fifth node; A gate electrode electrically connected to a fourth gate line, and configured to switch an electrical connection between a fifth power line and the sixth node, wherein the fifth power line comprises a tenth transistor different from the first power line, the second a power line, the second b power line, the third power line, and the fourth power line; A second capacitor comprising a first electrode electrically connected to the third power line and a second electrode electrically connected to the fourth node; and A display panel comprising a third capacitor including a first electrode electrically connected to the fourth node and a second electrode electrically connected to the sixth node.

13. In paragraph 12, Each of the seventh transistor, the eighth transistor, and the tenth transistor includes a semiconductor layer formed of a corresponding region of the first active pattern layer, A display panel including a semiconductor layer comprising the ninth transistor and a corresponding region of the second active pattern layer.

14. In paragraph 12, Each of the first gate line, the second gate line, and the third gate line includes a corresponding area of the gate electrode layer, The fourth gate line, the first power line, the second a power line, the second b power line, the second c power line, the sweep line, and the light emission control line include corresponding areas of the first source drain electrode layer disposed on the gate electrode layer, A display panel in which the data line, the fourth power line, and the fifth power line include corresponding areas of the second source-drain electrode layer disposed on the first source-drain electrode layer.

15. In paragraph 7, The pulse width modulation circuit and the pixel driving circuit are adjacent in the second direction, A display panel in which the above connecting electrode extends in the second direction and overlaps with each of the second a power line and the second b power line in the third direction.

16. In paragraph 7, The above light-emitting element is a display panel of a flip-chip type light-emitting element.

17. In paragraph 1, The bridge pattern extending from the second a power line includes a first bridge pattern, The above display panel, A third sub-pixel positioned in the first direction from the second sub-pixel and configured to emit light of a third wavelength band different from the first wavelength band and the second wavelength band; and A second bridge pattern extending in the first direction, overlapping the first sub-pixel, the second sub-pixel, and the third sub-pixel in the third direction, and branching in the second direction, further comprising a thirda power line connected to the third sub-pixel through the second bridge pattern, The above 3a power line is different from the above 2a power line and the above 2b power line, A display panel in which the second b power line extends in the first direction and bypasses the first bridge pattern and the second bridge pattern.

18. In paragraph 17, A display panel in which the first sub-pixel, the second sub-pixel, and the third sub-pixel are sequentially adjacent in the first direction.

19. In paragraph 17, A display panel in which the first sub-pixel, the third sub-pixel, and the second sub-pixel are sequentially adjacent in the first direction.

20. A processor providing image data and control signals; and A display device including a display panel, The above display device, configured to receive the above image data and the above control signal, It is configured to display an image corresponding to the image data in response to the above control signal, The above display panel, A first sub-pixel configured to emit light of a first wavelength band; A second sub-pixel positioned in a first direction from the first sub-pixel and configured to emit light of a second wavelength band different from the first wavelength band; A second power line including a bridge pattern extending in the first direction, overlapping the first sub-pixel and the second sub-pixel in a third direction intersecting the first direction, and branching in a second direction intersecting the first direction, and electrically connected to the first sub-pixel through the bridge pattern; and A display system including a secondb power line extending in the first direction, bypassing the bridge pattern, overlapping both the first sub-pixel and the second sub-pixel in the third direction, and electrically connected to the second sub-pixel.

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