Display panel and operating method thereof

Abstract

Provided is a display panel comprising: a light-emitting element; a first transistor that controls a current flowing in the light-emitting element; a storage capacitor connected to a gate of the first transistor; a second transistor connected to a first terminal of the first transistor to apply a data signal; a third transistor connected to the gate and a second terminal of the first transistor; a fourth transistor connected to the second terminal of the first transistor to apply an initialization voltage; a fifth transistor connected to the first terminal of the first transistor to apply a first voltage; a sixth transistor connected to the second terminal of the first transistor and the light-emitting element; a seventh transistor connected to a first terminal of the storage capacitor to apply a reference voltage; and an eighth transistor connected to the first terminal of the storage capacitor to apply the first voltage.

Description

Display panel and method of operation thereof

[0001] The present disclosure relates to a display panel and a method of operating the same.

[0002] Display panels that use self-luminous elements, such as micro light emitting diodes (LEDs) or organic light emitting diodes (OLEDs), may include pixel circuitry that controls the current flowing to the light emitting elements.

[0003] A pixel circuit may include a light-emitting element and a driving transistor that controls current flowing to the light-emitting element. The current of the driving transistor is controlled by a gate-source voltage (V) of the driving transistor. GS ) and threshold voltage (Vth).

[0004] However, the threshold voltages of multiple driving transistors included in the display panel may differ due to the non-uniformity of the manufacturing process (e.g., Excimer Laser Annealing (ELA), etching, etc.). In addition, when the current of the light-emitting element flows through the power wiring, a voltage drop (IR-Drop) may occur due to the resistance component of the power wiring, and due to the voltage drop, the voltage applied to the source node of the driving transistor may differ depending on the location within the display panel.

[0005] Therefore, even if the same data voltage is input, the current flowing to the light-emitting element may vary depending on the location within the display panel, which may result in problems such as uneven brightness of the display panel, afterimages, and reduced lifespan.

[0006] A display panel according to one embodiment of the present disclosure may include a light-emitting element, a first transistor for controlling current flowing in the light-emitting element, a storage capacitor connected to a gate of the first transistor, a second transistor connected to a first terminal of the first transistor and applying a data signal, a third transistor connected to the gate of the first transistor and a second terminal of the first transistor, a fourth transistor connected to the second terminal of the first transistor and applying an initialization voltage, a fifth transistor connected to the first terminal of the first transistor and applying a first voltage, a sixth transistor connected to the second terminal of the first transistor and the light-emitting element, a seventh transistor connected to the first terminal of the storage capacitor and applying a reference voltage, and an eighth transistor connected to the first terminal of the storage capacitor and applying a first voltage.

[0007] A display device according to one embodiment of the present disclosure may include an active area including a plurality of pixels arranged in rows and columns, a scan driver (SCAN driver) that applies a plurality of scan signals to the active area, an emission driver (Emission driver) that applies a plurality of emission signals to the active area, a display driver IC (Display Driver Integrated Circuit) that acquires image data, generates a plurality of data signals based on the image data, and applies the plurality of data signals to the active area, and a power supply that supplies a first voltage, a second voltage, an initialization voltage, and a reference voltage to the active area.

[0008] In one embodiment, each of the plurality of pixels may include a light-emitting element, a first transistor for controlling current flowing in the light-emitting element, a storage capacitor connected to a gate of the first transistor, a second transistor connected to a first terminal of the first transistor and applying a corresponding data signal, a third transistor connected to the gate of the first transistor and a second terminal of the first transistor, a fourth transistor connected to the second terminal of the first transistor and applying an initialization voltage, a fifth transistor connected to the first terminal of the first transistor and applying a first voltage, a sixth transistor connected to the second terminal of the first transistor and the light-emitting element, a seventh transistor connected to the first terminal of the storage capacitor and applying a reference voltage, and an eighth transistor connected to the first terminal of the storage capacitor and applying a first voltage.

[0009] FIG. 1 schematically illustrates the configuration of a display panel according to one embodiment of the present disclosure.

[0010] FIG. 2 illustrates a pixel circuit according to one embodiment of the present disclosure.

[0011] FIG. 3 illustrates the operation timing of a pixel circuit according to one embodiment of the present disclosure.

[0012] FIG. 4 illustrates a state of a pixel circuit in an initialization period according to one embodiment of the present disclosure.

[0013] FIG. 5 illustrates a state of a pixel circuit in a sampling interval according to one embodiment of the present disclosure.

[0014] FIG. 6 illustrates a state of a pixel circuit in a light-emitting section according to one embodiment of the present disclosure.

[0015] FIG. 7a illustrates a pixel circuit according to one embodiment of the present disclosure.

[0016] FIG. 7b illustrates the operation timing of a pixel circuit according to one embodiment of the present disclosure.

[0017] FIG. 8A illustrates a pixel circuit according to one embodiment of the present disclosure.

[0018] FIG. 8b illustrates the operation timing of a pixel circuit according to one embodiment of the present disclosure.

[0019] FIG. 9a illustrates a pixel circuit according to one embodiment of the present disclosure.

[0020] FIG. 9b illustrates the operation timing of a pixel circuit according to one embodiment of the present disclosure.

[0021] FIG. 10A illustrates a pixel circuit according to one embodiment of the present disclosure.

[0022] FIG. 10b illustrates the operation timing of a pixel circuit according to one embodiment of the present disclosure.

[0023] In this disclosure, the expression “at least one of a, b, and c” may refer to “a,” “b,” “c,” “a and b,” “a and c,” “b and c,” “all of a, b, and c,” or variations thereof.

[0024] The terms used in this disclosure are selected from widely used, current terms, taking into account the functions of the embodiments. However, these terms may vary depending on the intentions of those skilled in the art, precedents, the emergence of new technologies, etc. Furthermore, in certain cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this disclosure should not be understood simply as names, but rather based on their inherent meanings and the overall content of this disclosure.

[0025] While terms like "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component could be referred to as a "second component," and similarly, a second component could also be referred to as a "first component."

[0026] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0027] Singular expressions may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art described herein.

[0028] In this disclosure, it should be understood that terms such as “include” or “have” are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in this disclosure, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0029] In this disclosure, components expressed as "units", "modules", etc. may be two or more components combined into one component, or one component may be divided into two or more components with more detailed functions. In addition, each component described below may additionally perform some or all of the functions performed by other components in addition to its own main function, and of course, some of the main functions performed by each component may be exclusively performed by other components.

[0030] In the present disclosure, a device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, the term "non-transitory storage medium" simply means a tangible device that does not contain signals (e.g., electromagnetic waves). This term does not distinguish between cases where data is permanently stored in the storage medium and cases where data is temporarily stored. For example, a "non-transitory storage medium" may include a buffer in which data is temporarily stored.

[0031] According to one embodiment, a method according to various aspects described in the present disclosure may be provided as a computer program product. The computer program product may be traded as a commodity between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an application store or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product (e.g., a downloadable app) may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0032] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present disclosure. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0033] FIG. 1 schematically illustrates the configuration of a display panel (100) according to one embodiment of the present disclosure.

[0034] Referring to FIG. 1, a display panel (100) according to one embodiment of the present disclosure may include a display driver integrated circuit (DDI) (110), a scan driver (SCAN driver) (120), an emission driver (130), a power supply (140), and an active area (150). However, the configuration of the display panel (100) is not limited thereto. For example, the display panel (100) may further include a timing controller for synchronizing an operation timing of the display panel (100) with a signal received from the outside, or a digital-to-analog converter for converting a digital signal into an analog signal.

[0035] A display device according to one embodiment of the present disclosure may include a display panel (100).

[0036] A display device according to one embodiment of the present disclosure may include a display driver integrated circuit (DDI) (110), a scan driver (SCAN driver) (120), an emission driver (130), a power supply (140), and an active area (150). However, the configuration of the display device is not limited thereto. For example, the display device may further include a timing controller for synchronizing an operation timing of a display panel (100) with a signal received from the outside, or a digital-to-analog converter for converting a digital signal into an analog signal.

[0037] In one embodiment of the present disclosure, the display driver IC (110) may generate a plurality of data signals (Data[1] to Data[H]) based on image data acquired from an external processor (e.g., an Application Processor (AP), a Graphic Processing Unit (GPU), etc.), and apply the generated plurality of data signals (Data[1] to Data[H]) to a plurality of data lines included in a display area (150). In one embodiment, the plurality of data signals (Data[1] to Data[H]) may be voltages corresponding to the brightness of each pixel (151) included in the display area (150).

[0038] In one embodiment of the present disclosure, the scan driver (120) can apply scan signals (SC[1] to SC[V]) to a plurality of scan lines (SC Lines) included in the display area (150). In one embodiment of the present disclosure, the scan signals (SC[1] to SC[V]) can be voltages for turning on or off corresponding transistors included in each pixel (151). The operation of the pixel (151) according to the scan signals (SC[1] to SC[V]) will be described later with reference to FIGS. 2 to 6.

[0039] In one embodiment of the present disclosure, the light emitting driver (130) can apply light emitting signals (EM[1] to EM[V]) to cause a plurality of pixels (151) included in a display area (150) to emit light. In one embodiment of the present disclosure, the light emitting signals (EM[1] to EM[V]) can be voltages for turning on or off a corresponding transistor included in each pixel (151). The operation of the pixel (151) according to the light emitting signals (EM[1] to EM[V]) will be described later with reference to FIGS. 2 to 6.

[0040] In one embodiment of the present disclosure, the power supply unit (140) can supply a first voltage (VDD), a second voltage (VSS), an initialization voltage (Vini), and a reference voltage (Vref) to the display area (150). In one embodiment of the present disclosure, the first voltage (VDD) can be a voltage of a higher potential than the second voltage (VSS). The operation of the pixel (151) according to the first voltage (VDD), the second voltage (VSS), the initialization voltage (Vini), and the reference voltage (Vref) will be described later with reference to FIGS. 2 to 6.

[0041] In one embodiment of the present disclosure, the display area (150) may include a plurality of pixels (151), a plurality of scan lines (SC Lines, single-dotted and dashed lines in FIG. 1), and a plurality of data lines (Data Lines, double-dotted and dashed lines in FIG. 1). However, the configuration of the display area (150) is not limited thereto. For example, the display area (150) may further include a plurality of power lines for applying a first voltage (VDD), a second voltage (VSS), an initialization voltage (Vini), and a reference voltage (Vref) supplied from a power supply unit (140) to the pixels (151).

[0042] In one embodiment of the present disclosure, scan lines (SC Lines) may be arranged for each row. The scan lines (SC Lines) are lines for applying scan signals (SC[1] to SC[V]) to pixels (151). For example, a number of scan lines (SC Lines) equal to the vertical resolution may be arranged in the display area (150).

[0043] In one embodiment of the present disclosure, data lines may be arranged for each column. The data lines are lines for applying data signals (Data[1] to Data[H]) to pixels (151). For example, a number of data lines equal to the horizontal resolution may be arranged in the display area (150). Alternatively, if each pixel includes three sub-pixels, three data lines equal to the horizontal resolution may be arranged in the display area (150). When a multiplexer (MUX) that selects some of a plurality of data signals is used, a smaller number of data lines may be arranged in the display area (150).

[0044] In one embodiment of the present disclosure, a pixel (151) may be placed in an area where a scan line (SC Line) and a data line (Data Line) intersect.

[0045] In one embodiment of the present disclosure, a pixel (151) may include a light-emitting element that emits light by itself when current flows and a driving transistor that controls the current flowing to the light-emitting element. The driving transistor may control the current flowing to the light-emitting element by turning on or off in response to a corresponding data signal.

[0046] In one embodiment of the present disclosure, a pixel (151) may include a plurality of sub-pixels (not shown). For example, a pixel (151) may include three sub-pixels, each corresponding to red (R), green (G), and blue (B).

[0047] FIG. 2 illustrates a pixel circuit (200) according to one embodiment of the present disclosure.

[0048] The pixel circuit (200) illustrated in FIG. 2 may be included in a pixel (151 in FIG. 1) corresponding to the nth row and mth column of the display area (150 in FIG. 1). Here, n is any natural number between 1 and the vertical resolution (V), and m is any natural number between 1 and the horizontal resolution (H).

[0049] In one embodiment of the present disclosure, the pixel circuit (200) may include a light emitting element (D1), first to eighth transistors (T1 to T8), and a storage capacitor (C1).

[0050] In one embodiment of the present disclosure, the light-emitting element (D1) can emit light proportional to the magnitude of the current when current flows. For example, the light-emitting element (D1) can be a self-luminous element such as a micro light-emitting diode (micro LED) or an organic light-emitting diode (OLED).

[0051] In one embodiment of the present disclosure, the first to eighth transistors (T1 to T8) can be turned on or off in response to a first scan signal (SC[n-2]), a second scan signal (SC[n-1]), a third scan signal (SC[n]), and an emission signal (EM[n]). In one embodiment, the first scan signal (SC[n-2]) can be a scan signal applied to the (n-2)th scan wire, the second scan signal (SC[n-1]) can be a scan signal applied to the (n-1)th scan wire, and the third scan signal (SC[n]) can be a scan signal applied to the (n)th scan wire. In one embodiment, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) can be generated by a scan driver (120 of FIG. 1). As described below, the voltage of each node in the pixel circuit (200) may change and the current of the light-emitting element (D1) may change depending on the state (i.e., on or off) of the first to eighth transistors (T1 to T8).

[0052] In one embodiment of the present disclosure, the first to eighth transistors (T1 to T8) may be low-temperature polycrystalline silicon thin film transistors (LTPS TFTs), oxide thin film transistors (Oxide TFTs), low-temperature polycrystalline silicon oxide (LTPO), or silicon-based switching elements.

[0053] In FIGS. 2 to 6, the first to eighth transistors (T1 to T8) are illustrated as being P-type transistors, but this is merely an example, and the first to eighth transistors (T1 to T8) may also be N-type transistors. In the following description, the first terminal of the first to eighth transistors (T1 to T8) may be a source, and the second terminal may be a drain, but is not limited thereto, and if the types of the first to eighth transistors (T1 to T8) change, the first terminal and the second terminal may also change.

[0054] In one embodiment of the present disclosure, the gate of the first transistor (T1) can be connected to the second terminal of the storage capacitor (C1) and the first terminal of the third transistor (T3).

[0055] In one embodiment of the present disclosure, a first terminal (N1 node) of a first transistor (T1) may be connected to a second terminal of a second transistor (T2) and a second terminal of a fifth transistor (T5), and a second terminal (N3 node) of the first transistor (T1) may be connected to a second terminal of a third transistor (T3), a first terminal of a fourth transistor (T4), and a first terminal of a sixth transistor (T6).

[0056] In one embodiment of the present disclosure, the first transistor (T1) may be a driving transistor. When the fifth transistor (T5), the first transistor (T1), and the sixth transistor (T6) are turned on, a current (I) is supplied through a path including the first voltage (VDD), the fifth transistor (T5), the first transistor (T1), the sixth transistor (T6), the light-emitting element (D1), and the second voltage (VSS). D1 ) can flow. At this time, current (I D1 ) is the gate-source voltage (V) of the first transistor (T1) as in mathematical expression 1. GS ) and threshold voltage (Vth).

[0057]

[0058] When the fifth transistor (T5) is turned on, the first voltage (VDD) is applied to the source of the first transistor (T1), so the current (I D1 ) can be expressed as in mathematical expression 2.

[0059]

[0060] In mathematical expressions 1 and 2, μ is the mobility of the carrier, and C ox is the capacitance of the oxide film of the first transistor (T1), and W and L are the width and length of the channel formed in the first transistor (T1), respectively.

[0061] Referring to mathematical expression 2, the current (I D1 ) can vary depending on the first voltage (VDD) and the threshold voltage (Vth) of the first transistor (T1).

[0062] However, the current (I D1) may cause a voltage drop due to the resistance component of the power wiring when current flows, and the voltage drop may cause the first voltage (VDD) applied to the source of the first transistor (T1) to vary depending on the location within the display panel (100). In addition, the threshold voltage (Vth) of the first transistor (T1) may vary depending on the pixel (151 in FIG. 1) due to the non-uniformity of the process. As a result, the brightness may become non-uniform depending on the location within the display panel due to the voltage drop and the deviation in the threshold voltage.

[0063] According to one embodiment of the present disclosure, the pixel circuit (200) generates a current (I) by the operation described below. D1 ) and the threshold voltage (Vth) of the first transistor (T1) per pixel (151) are simultaneously compensated for by the current (I D1 ) can eliminate the influence of the first voltage (VDD) and threshold voltage (Vth).

[0064] In one embodiment of the present disclosure, the gate of the second transistor (T2) may be connected to the nth scan wiring. A third scan signal (SC[n]) may be applied to the gate of the second transistor (T2), and the second transistor (T2) may be turned on or off in response to the third scan signal (SC[n]). For example, the second transistor (T2) may be turned on when the third scan signal (SC[n]) is low, and may be turned off when the third scan signal (SC[n]) is high.

[0065] In one embodiment of the present disclosure, a first terminal of a second transistor (T2) may be connected to a data line, and a second terminal of the second transistor (T2) may be connected to a first terminal of a first transistor (T1) and a second terminal of a fifth transistor (T5). When the second transistor (T2) is turned on, a data signal may be applied to the N1 node. The second transistor (T2) may be referred to as a switching transistor that applies a data signal to a driving transistor.

[0066] In one embodiment of the present disclosure, the gate of the third transistor (T3) may be connected to the (n-1)th scan wiring. A second scan signal (SC[n-1]) may be applied to the gate of the third transistor (T3), and the third transistor (T3) may be turned on or off in response to the second scan signal (SC[n-1]). For example, the third transistor (T3) may be turned on when the second scan signal (SC[n-1]) is low, and may be turned off when the second scan signal (SC[n-1]) is high.

[0067] In one embodiment of the present disclosure, a first terminal of a third transistor (T3) may be connected to a gate of a first transistor (T1) and a second terminal of a storage capacitor (C1), and a second terminal of the third transistor (T3) may be connected to a second terminal of the first transistor (T1), a first terminal of a fourth transistor (T4), and a first terminal of a sixth transistor (T6). When the third transistor (T3) and the fourth transistor (T4) are turned on, an initialization voltage (Vini) may be applied to the gate of the first transistor (T1).

[0068] In one embodiment of the present disclosure, the gate of the fourth transistor (T4) may be connected to the (n-2)th scan line. A first scan signal (SC[n-2]) may be applied to the gate of the fourth transistor (T4), and the fourth transistor (T4) may be turned on or off in response to the first scan signal (SC[n-2]). For example, the fourth transistor (T4) may be turned on when the first scan signal (SC[n-2]) is low, and may be turned off when the first scan signal (SC[n-2]) is high.

[0069] In one embodiment of the present disclosure, a first terminal of a fourth transistor (T4) may be connected to a second terminal of a first transistor (T1), a second terminal of a third transistor (T3), and a first terminal of a sixth transistor (T6), and a second terminal of the fourth transistor (T4) may be connected to a power line that supplies an initialization voltage (Vini). When the third transistor (T3) and the fourth transistor (T4) are turned on, the initialization voltage (Vini) may be applied to the gate of the first transistor (T1).

[0070] In one embodiment of the present disclosure, the gate of the fifth transistor (T5) may be connected to a wiring that applies a light-emitting signal (EM[n]). The light-emitting signal (EM[n]) may be applied to the gate of the fifth transistor (T5), and the fifth transistor (T5) may be turned on or off in response to the light-emitting signal (EM[n]). For example, the fifth transistor (T5) may be turned on when the light-emitting signal (EM[n]) is low, and may be turned off when the light-emitting signal (EM[n]) is high.

[0071] In one embodiment of the present disclosure, a first terminal of the fifth transistor (T5) may be connected to a power line supplying a first voltage (VDD), and a second terminal of the fifth transistor (T5) may be connected to a first terminal of the first transistor (T1) and a second terminal of the second transistor (T2). When the fifth transistor (T5) is turned off, a current (I D1 ) will not flow.

[0072] In one embodiment of the present disclosure, the gate of the sixth transistor (T6) may be connected to a wiring that applies a light-emitting signal (EM[n]). The light-emitting signal (EM[n]) may be applied to the gate of the sixth transistor (T6), and the sixth transistor (T6) may be turned on or off in response to the light-emitting signal (EM[n]). For example, the sixth transistor (T6) may be turned on when the light-emitting signal (EM[n]) is low, and may be turned off when the light-emitting signal (EM[n]) is high.

[0073] In one embodiment of the present disclosure, the first terminal of the sixth transistor (T6) can be connected to the second terminal of the first transistor (T1), the second terminal of the third transistor (T3), and the first terminal of the fourth transistor (T4), and the second terminal (N4 node) of the sixth transistor (T6) can be connected to the anode of the light-emitting element (D1). When the sixth transistor (T6) is turned off, the current (I D1 ) will not flow.

[0074] In one embodiment of the present disclosure, the gate of the seventh transistor (T7) may be connected to the (n-1)th scan wiring. A second scan signal (SC[n-1]) may be applied to the gate of the seventh transistor (T7), and the seventh transistor (T7) may be turned on or off in response to the second scan signal (SC[n-1]). For example, the seventh transistor (T7) may be turned on when the second scan signal (SC[n-1]) is low, and may be turned off when the second scan signal (SC[n-1]) is high.

[0075] In one embodiment of the present disclosure, a first terminal of the seventh transistor (T7) may be connected to a power wiring supplying a reference voltage (Vref), and a second terminal of the seventh transistor (T7) may be connected to a first terminal (N5 node) of a storage capacitor (C1) and a second terminal of an eighth transistor (T8). When the seventh transistor (T7) is turned on, the reference voltage (Vref) is applied to the first terminal (N5 node) of the storage capacitor (C1).

[0076] In one embodiment of the present disclosure, the gate of the eighth transistor (T8) may be connected to a wiring that applies a light-emitting signal (EM[n]). The light-emitting signal (EM[n]) may be applied to the gate of the eighth transistor (T8), and the eighth transistor (T8) may be turned on or off in response to the light-emitting signal (EM[n]). For example, the eighth transistor (T8) may be turned on when the light-emitting signal (EM[n]) is low, and may be turned off when the light-emitting signal (EM[n]) is high.

[0077] In one embodiment of the present disclosure, a first terminal of the eighth transistor (T8) may be connected to a power line supplying a first power source (VDD), and a second terminal of the eighth transistor (T8) may be connected to a first terminal (N5 node) of a storage capacitor (C1) and a second terminal of a seventh transistor (T7). When the eighth transistor (T8) is turned on, the first power source (VDD) may be applied to the first terminal (N5 node) of the storage capacitor (C1).

[0078] Referring to FIG. 1, a display panel (100) according to an embodiment of the present disclosure may include two GIP (Gate in Panel) drivers (i.e., a scan driver (120) and a light emitting driver (130)) to control pixels (151). As the display panel (100) includes fewer GIP drivers, the aperture ratio increases, production costs can be reduced, the size of the bezel can be reduced, and power consumption can be reduced. Therefore, the display panel (100) according to an embodiment of the present disclosure may be configured to supply current (I D1 ) can have the aforementioned advantages compared to other display panels that include three or more GIP drivers to simultaneously compensate for the voltage drop that occurs when the GIP driver flows and the threshold voltage (Vth) of the driving transistor.

[0079] In a display panel (100) according to one embodiment of the present disclosure, one transistor (i.e., a third transistor (T3)) is connected to the gate of a first transistor (T1), which is a driving transistor. The more transistors connected to the gate of the driving transistor, the greater the leakage current flowing through the corresponding transistor. In particular, when driving at a low duty cycle (e.g., 1 Hz or 10 Hz) to reduce power consumption, the leakage current becomes greater, and the storage capacitor may be rapidly discharged due to the leakage current, which may cause a flicker phenomenon in the display panel (100). Therefore, the display panel (100) according to one embodiment of the present disclosure can reduce the flicker phenomenon compared to other display panels in which two or more transistors are connected to the gate of the driving transistor.

[0080] FIG. 3 illustrates the operation timing of a pixel circuit (200 in FIG. 2) according to one embodiment of the present disclosure.

[0081] In one embodiment of the present disclosure, the pixel circuit (200 of FIG. 2) can operate in an initial period, a sampling period, and an emission period. In one embodiment of the present disclosure, a holding period can be added between the sampling period and the emission period. In the present disclosure, the initialization period can be referred to as a first operation period. In the present disclosure, the sampling period can be referred to as a second operation period. In the present disclosure, the emission period can be referred to as a third operation period.

[0082] Each operation section can be distinguished by the first to third scan signals (SC[n-2], SC[n-1], SC[n]) or the emission signal (EM[n]). In one embodiment of the present disclosure, in the initialization section, the first scan signal (SC[n-2]) and the second scan signal (SC[n-1]) can be first values ​​for turning on the transistor. In one embodiment of the present disclosure, in the sampling section, the second scan signal (SC[n-1]) and the third scan signal (SC[n]) can be first values ​​for turning on the transistor. In one embodiment of the present disclosure, in the emission section, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) can be second values ​​for turning off the transistor, and the emission signal (EM[n]) can be the first value for turning on the transistor. Here, the first value can be low, and the second value can be high.

[0083] As illustrated in FIG. 3, in one embodiment of the present disclosure, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) may be a first value for turning on the transistor for at least 2H (Horizontal time) during the entire operation period. For example, the first scan signal (SC[n-2]) and the second scan signal (SC[n-1]) may change from the second value to the first value with a time difference of 1H, and may each maintain the first value for 2H. In addition, the second scan signal (SC[n-1]) and the third scan signal (SC[n]) may change from the second value to the first value with a time difference of 1H, and may each maintain the first value for 2H. Therefore, the initialization period and the sampling period may be maintained for at least 1H.

[0084] Here, 1H may include the input time of data allocated to one pixel line to represent one frame. In one embodiment of the present disclosure, 1H may be determined based on the refresh rate and vertical resolution of the display. For example, 1H may be determined by dividing the time of one frame (i.e., 1 / refresh rate) by the vertical resolution of the display.

[0085] Below, the state and operation of the pixel circuit (200) in each operation section are described with reference to FIGS. 4 to 6.

[0086] FIG. 4 illustrates the state of a pixel circuit (200) in an initialization period according to one embodiment of the present disclosure.

[0087] In one embodiment of the present disclosure, the initialization period is a period for initializing the gate voltage of the driving transistor (i.e., the first transistor (T1)). In the initialization period, the first scan signal (SC[n-2]) and the second scan signal (SC[n-1]) may be first values ​​for turning on the transistor.

[0088] Referring to FIG. 4, in the initialization section, the fourth transistor (T4) may be turned on in response to the first scan signal (SC[n-2]) being a first value (e.g., low), and the third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being a first value (e.g., low).

[0089] When the third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7) are turned on, the gate (N2 node) voltage of the first transistor (T1) can be initialized to the initialization voltage (Vini) through the third transistor (T3) and the fourth transistor, and the source (N1 node) voltage of the first transistor (T1) can become the third voltage. In one embodiment, the third voltage can be determined based on the initialization voltage and the threshold voltage. For example, the third voltage can be a voltage that is higher than the initialization voltage (Vini) by the absolute value of the threshold voltage (i.e., Vini + |Vth|). In addition, a reference voltage (Vref) can be applied to the first terminal (N5 node) of the storage capacitor (C1).

[0090] In a display panel (100) according to one embodiment of the present disclosure, since the source of the driving transistor (i.e., the first transistor (T1)) is not floated in the initialization section and a specific voltage (i.e., Vini + |Vth|) is applied, the influence of the previous frame on the current frame can be minimized, thereby improving motion blur caused by the hysteresis of the driving transistor.

[0091] FIG. 5 illustrates a state of a pixel circuit (200) in a sampling interval according to one embodiment of the present disclosure.

[0092] In one embodiment, the sampling period is a period in which a data signal is applied to the pixel circuit (200) and the threshold voltage (Vth) of the driving transistor is sampled. In the sampling period, the second scan signal (SC[n-1]) and the third scan signal (SC[n]) may be the first values ​​for turning on the transistor.

[0093] Referring to FIG. 5, in the sampling interval, the third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being a first value (e.g., low), and the second transistor (T2) may be turned on in response to the third scan signal (SC[n]) being a first value (e.g., low).

[0094] When the second transistor (T2), the third transistor (T3), and the seventh transistor (T7) are turned on, a data signal (Vdata) can be applied to the source of the first transistor (T1), and the gate voltage of the first transistor (T1) can be a fourth voltage. In one embodiment, the fourth voltage can be determined based on the data signal (Vdata) and a threshold voltage. For example, the fourth voltage can be a voltage that is lower than the data signal (Vdata) by an absolute value of the threshold voltage (i.e., Vdata - |Vth|). In addition, the voltage of the first terminal (N5 node) of the storage capacitor (C1) can be maintained at the reference voltage (Vref).

[0095] The gate voltage (V) of the driving transistor during the sampling period G ) may include a threshold voltage (Vth) component. Therefore, as described below, the current (I) in the light-emitting section D1 ) the threshold voltage component can be offset.

[0096] FIG. 6 illustrates a state of a pixel circuit (200) in a light-emitting section according to one embodiment of the present disclosure.

[0097] In one embodiment, the light emitting section is configured to apply current (I) to the light emitting element (D1). D1 ) flows, and the light-emitting element (D1) emits light. In the light-emitting section, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) may be the second value for turning off the transistor, and the light-emitting signal (EM[n]) may be the first value for turning on the transistor.

[0098] Referring to FIG. 6, in the light emission section, the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) can be turned on in response to the light emission signal (EM[n]) being a first value (e.g., low).

[0099] When the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned on, the voltage of the first terminal (N5 node) of the storage capacitor (C1) can change from the reference voltage (Vref) to the first voltage (VDD), and the source voltage of the first transistor (T1) can become the first voltage (VDD).

[0100] When the voltage of the first terminal (N5 node) of the storage capacitor (C1) changes instantaneously, the voltage of the second terminal of the storage capacitor (C1) (i.e., the gate of the first transistor (T1)) changes in proportion to the amount of change in the voltage of the first terminal (i.e., VDD-Vref) due to the coupling phenomenon. As a result, in the light-emitting section, the gate voltage (V of the first transistor (T1) G ) can be expressed as in mathematical formula 3.

[0101]

[0102] In mathematical expression 3, α is C1 / (C1 + Cpara), and Cpara is a parasitic capacitance generated at the first terminal of the storage capacitor (C1). The parasitic capacitance may be caused by the layout of the pixel circuit (200). Since Cpara is very small compared to C1, α can be approximated as 1. In the present disclosure, α(VDD-Vref) may be referred to as a fifth voltage.

[0103] If we substitute mathematical expression 3 into mathematical expression 2, we get the current (I) as in mathematical expression 4. D1 ) flows to the light emitting element (D1).

[0104]

[0105] If α is approximated to 1 in mathematical expression 4, the current (ID1 ) can be expressed as in mathematical expression 5.

[0106]

[0107] Referring to mathematical expression 5, the current (I) of the light-emitting element (D1) D1 ) does not include the first voltage (VDD) and threshold voltage (Vth) components, so the display panel (100) according to one embodiment of the present disclosure does not include the current (I D1 ) can simultaneously compensate for the voltage drop (IR-Drop) that occurs when the current flows, and the threshold voltage (Vth) of the first transistor (T1) per pixel (151 in Fig. 1).

[0108] Meanwhile, during the display manufacturing process, the storage capacitor (C1) may be short-circuited by foreign matter. When the storage capacitor (C1) is short-circuited, the display's failure rate may vary depending on the state of the driving transistor (i.e., on or off). When the driving transistor is on, the corresponding pixel becomes a bright spot, and when the driving transistor is off, the corresponding pixel becomes a black spot. To reduce the display's failure rate, the driving transistor needs to be turned off so that the corresponding pixel becomes a dark spot even when the storage capacitor (C1) is short-circuited.

[0109] As described above, in the display panel (100) according to one embodiment of the present disclosure, the voltage of the first terminal (N5 node) of the storage capacitor (C1) may be VDD during the light-emitting period, and the source voltage of the driving transistor (i.e., the first transistor (T1)) may be VDD. Therefore, even if the storage capacitor (C1) is short-circuited, the gate voltage of the first transistor (T1) becomes VDD, so the first transistor (T1) may remain in an off state, and the corresponding pixel may become a dark spot. Consequently, in the display panel (100) according to one embodiment of the present disclosure, even if the storage capacitor (C1) is short-circuited by a foreign substance or the like during the manufacturing process, the defect rate may be reduced.

[0110] The pixel circuit (200) according to one embodiment of the present disclosure described above operates using only two GIP drivers (i.e., a scan driver and a light emitting driver) and supplies current (I D1 ) can simultaneously compensate for the voltage drop (IR-Drop) that occurs when the current flows, and the threshold voltage (Vth) of the first transistor (T1) for each pixel (151 in Fig. 1). Hereinafter, a pixel circuit that can simultaneously compensate for the voltage drop and the threshold voltage using only two GIP drivers, similar to the pixel circuit (200), will be described.

[0111] FIG. 7a illustrates a pixel circuit (700) according to one embodiment of the present disclosure, and FIG. 7b illustrates the operation timing of the pixel circuit (700) according to one embodiment of the present disclosure.

[0112] Referring to FIG. 7A, in one embodiment of the present disclosure, the pixel circuit (700) may include a light-emitting element (D1), first to eighth transistors (T1 to T8), and a storage capacitor (C1). In one embodiment of the present disclosure, the first to eighth transistors (T1 to T8) may be turned on or off in response to a first scan signal (SC[n-2]), a second scan signal (SC[n-1]), a third scan signal (SC[n]), a first light-emitting signal (EM[n-1]), and a second light-emitting signal (EM[n]).

[0113] The connection state between the light-emitting element (D1), the first to eighth transistors (T1 to T8), and the storage capacitor (C1) included in the pixel circuit (700) is the same as that of the pixel circuit (200) of FIG. 2. However, in the pixel circuit (700), the fifth transistor (T5) and the eighth transistor (T8) can be turned on or off in response to the first light-emitting signal (EM[n-1]), and the sixth transistor (T6) can be turned on or off in response to the second light-emitting signal (EM[n]).

[0114] Referring to FIG. 7B, in one embodiment of the present disclosure, the pixel circuit (700) may operate in an initialization period, a sampling period, and a light emission period. In one embodiment of the present disclosure, a holding period may be added between the sampling period and the light emission period.

[0115] Each operation section can be distinguished by the first to third scan signals (SC[n-2], SC[n-1], SC[n]) or the first to second emission signals (EM[n-1], EM[n]).

[0116] In one embodiment, in the initialization period, the first scan signal (SC[n-2]) and the second scan signal (SC[n-1]) may be first values ​​for turning on the transistors. The fourth transistor (T4) may be turned on in response to the first scan signal (SC[n-2]) being the first value, and the third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being the first value.

[0117] In one embodiment of the present disclosure, in the sampling interval, the second scan signal (SC[n-1]) and the third scan signal (SC[n]) may be first values ​​for turning on the transistors. The third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being the first value, and the second transistor (T2) may be turned on in response to the third scan signal (SC[n]) being the first value.

[0118] In one embodiment of the present disclosure, in the light emission section, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) may be second values ​​for turning off the transistors, and the first to second light emission signals (EM[n-1], EM[n]) may be first values ​​for turning on the transistors. In response to the first light emission signal (EM[n-1]) being the first value, the fifth transistor (T5) and the eighth transistor (T8) may be turned on, and in response to the second light emission signal (EM[n]) being the first value, the sixth transistor (T6) may be turned on.

[0119] FIG. 8a illustrates a pixel circuit (800) according to one embodiment of the present disclosure, and FIG. 8b illustrates the operation timing of the pixel circuit (800) according to one embodiment of the present disclosure.

[0120] Referring to FIG. 8A, in one embodiment of the present disclosure, a pixel circuit (800) may include a light-emitting element (D1), first to eighth transistors (T1 to T8), and a storage capacitor (C1). In one embodiment of the present disclosure, the first to eighth transistors (T1 to T8) may be turned on or off in response to a first scan signal (SC[n-2]), a second scan signal (SC[n-1]), a third scan signal (SC[n]), and a light-emitting signal (EM[n]). The first to eighth transistors (T1 to T8) included in the pixel circuit (800) may be N-type transistors.

[0121] Referring to FIG. 8B, in one embodiment of the present disclosure, the pixel circuit (800) may operate in an initialization period, a sampling period, and a light emission period. In one embodiment of the present disclosure, a holding period may be added between the sampling period and the light emission period.

[0122] Each operation section can be distinguished by the first to third scan signals (SC[n-2], SC[n-1], SC[n]) or the emission signal (EM[n]).

[0123] In one embodiment of the present disclosure, in the initialization period, the first scan signal (SC[n-2]) and the second scan signal (SC[n-1]) may be first values ​​for turning on the transistors. The fourth transistor (T4) may be turned on in response to the first scan signal (SC[n-2]) being the first value, and the third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being the first value.

[0124] In one embodiment of the present disclosure, in the sampling interval, the second scan signal (SC[n-1]) and the third scan signal (SC[n]) may be first values ​​for turning on the transistors. The third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being the first value, and the second transistor (T2) may be turned on in response to the third scan signal (SC[n]) being the first value.

[0125] In one embodiment of the present disclosure, in the light emission section, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) may be second values ​​for turning off the transistors, and the light emission signal (EM[n]) may be first values ​​for turning on the transistors. In response to the light emission signal (EM[n]) being the first value, the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) may be turned on.

[0126] FIG. 9a illustrates a pixel circuit (900) according to one embodiment of the present disclosure, and FIG. 9b illustrates the operation timing of the pixel circuit (900) according to one embodiment of the present disclosure.

[0127] Referring to FIG. 9A, in one embodiment of the present disclosure, a pixel circuit (900) may include a light-emitting element (D1), first to ninth transistors (T1 to T9), and a storage capacitor (C1). In one embodiment of the present disclosure, the first to ninth transistors (T1 to T9) may be turned on or off in response to a first scan signal ([n-2]), a second scan signal ([n-1]), a third scan signal ([n]), and a light-emitting signal (EM[n]).

[0128] Referring to FIG. 9B, in one embodiment of the present disclosure, the pixel circuit (900) may operate in an initialization period, a sampling period, and a light emission period. In one embodiment of the present disclosure, a holding period may be added between the sampling period and the light emission period.

[0129] Each operation section can be distinguished by the first to third scan signals (SC[n-2], SC[n-1], SC[n]) or the emission signal (EM[n]).

[0130] In one embodiment of the present disclosure, in the initialization section, the first scan signal (SC[n-2]) and the second scan signal (SC[n-1]) may be first values ​​for turning on the transistors. In response to the first scan signal (SC[n-2]) being the first value, the fourth transistor (T4) and the ninth transistor (T9) may be turned on, and in response to the second scan signal (SC[n-1]) being the first value, the third transistor (T3) and the seventh transistor (T7) may be turned on.

[0131] In one embodiment of the present disclosure, in the sampling interval, the second scan signal (SC[n-1]) and the third scan signal (SC[n]) may be first values ​​for turning on the transistors. The third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being the first value, and the second transistor (T2) may be turned on in response to the third scan signal (SC[n]) being the first value.

[0132] In one embodiment of the present disclosure, in the light emission section, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) may be second values ​​for turning off the transistors, and the light emission signal (EM[n]) may be first values ​​for turning on the transistors. In response to the light emission signal (EM[n]) being the first value, the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) may be turned on.

[0133] FIG. 10A illustrates a pixel circuit (1000) according to one embodiment of the present disclosure, and FIG. 10B illustrates the operation timing of the pixel circuit (1000) according to one embodiment of the present disclosure.

[0134] Referring to FIG. 10A, in one embodiment of the present disclosure, a pixel circuit (1000) may include a light-emitting element (D1), first to ninth transistors (T1 to T9), and a storage capacitor (C1). In one embodiment of the present disclosure, the first to ninth transistors (T1 to T9) may be turned on or off in response to a first scan signal ([n-2]), a second scan signal ([n-1]), a third scan signal ([n]), and a light-emitting signal (EM[n]).

[0135] Referring to FIG. 10B, in one embodiment of the present disclosure, the pixel circuit (1000) may operate in an initialization period, a sampling period, and a light emission period. In one embodiment of the present disclosure, a holding period may be added between the sampling period and the light emission period.

[0136] Each operation section can be distinguished by the first to third scan signals (SC[n-2], SC[n-1], SC[n]) or the emission signal (EM[n]).

[0137] In one embodiment of the present disclosure, in the initialization section, the first scan signal (SC[n-2]) and the second scan signal (SC[n-1]) may be first values ​​for turning on the transistors. In response to the first scan signal (SC[n-2]) being the first value, the fourth transistor (T4) and the ninth transistor (T9) may be turned on, and in response to the second scan signal (SC[n-1]) being the first value, the third transistor (T3) and the seventh transistor (T7) may be turned on.

[0138] In one embodiment of the present disclosure, in the sampling interval, the second scan signal (SC[n-1]) and the third scan signal (SC[n]) may be first values ​​for turning on the transistors. The third transistor (T3) and the seventh transistor (T7) may be turned on in response to the second scan signal (SC[n-1]) being the first value, and the second transistor (T2) may be turned on in response to the third scan signal (SC[n]) being the first value.

[0139] In one embodiment of the present disclosure, in the light emission section, the first to third scan signals (SC[n-2], SC[n-1], SC[n]) may be second values ​​for turning off the transistors, and the light emission signal (EM[n]) may be first values ​​for turning on the transistors. In response to the light emission signal (EM[n]) being the first value, the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) may be turned on.

[0140] A display panel according to one embodiment of the present disclosure may include a light-emitting element, a first transistor for controlling current flowing in the light-emitting element, a storage capacitor connected to a gate of the first transistor, a second transistor connected to a first terminal of the first transistor and applying a data signal, a third transistor connected to the gate of the first transistor and a second terminal of the first transistor, a fourth transistor connected to the second terminal of the first transistor and applying an initialization voltage, a fifth transistor connected to the first terminal of the first transistor and applying a first voltage, a sixth transistor connected to the second terminal of the first transistor and the light-emitting element, a seventh transistor connected to the first terminal of the storage capacitor and applying a reference voltage, and an eighth transistor connected to the first terminal of the storage capacitor and applying the first voltage.

[0141] In one embodiment of the present disclosure, the display panel may further include a scan driver (SCAN driver) that generates a first scan signal for turning on or off the fourth transistor, a second scan signal for turning on or off the third transistor and the seventh transistor, and a third scan signal for turning on or off the second transistor.

[0142] In one embodiment of the present disclosure, each of the first to third scan signals may be a first value for turning on a corresponding transistor for at least 2H (Horizontal time).

[0143] In one embodiment of the present disclosure, the display panel may further include an emission driver that generates an emission signal for turning on or off the fifth transistor, the sixth transistor, and the eighth transistor.

[0144] In one embodiment of the present disclosure, the display panel may further include an emission driver that generates a first emission signal for turning on or off the fifth transistor and the eighth transistor, and a second emission signal for turning on or off the sixth transistor.

[0145] In one embodiment of the present disclosure, in the first operation section, the third transistor, the fourth transistor, and the seventh transistor may be turned on, the initialization voltage may be applied to the gate of the first transistor, the reference voltage may be applied to the first terminal of the storage capacitor, and a third voltage determined based on the initialization voltage and the threshold voltage of the first transistor may be applied to the first terminal of the first transistor.

[0146] In one embodiment of the present disclosure, in the second operating section, the second transistor, the third transistor, and the seventh transistor may be turned on, the data signal may be applied to the first terminal of the first transistor, and a fourth voltage determined based on the data signal and a threshold voltage of the first transistor may be applied to the gate of the first transistor.

[0147] In one embodiment of the present disclosure, in the third operating section, the fifth transistor, the sixth transistor, and the eighth transistor may be turned on, the first voltage may be applied to the first terminal of the storage capacitor, and a fifth voltage proportional to the amount of change in the voltage of the first terminal of the storage capacitor may be additionally applied to the gate of the first transistor.

[0148] In one embodiment of the present disclosure, the first operation section and the second operation section can be maintained for at least 1H (Horizontal time).

[0149] In one embodiment of the present disclosure, the first to eighth transistors may be any one of a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), an oxide thin film transistor (Oxide TFT), a low-temperature polycrystalline silicon oxide (LTPO), or a silicon-based switching element.

[0150] A display device according to one embodiment of the present disclosure may include an active area including a plurality of pixels arranged in rows and columns, a scan driver (SCAN driver) that applies a plurality of scan signals to the active area, an emission driver (Emission driver) that applies a plurality of emission signals to the active area, a display driver IC (Display Driver Integrated Circuit) that acquires image data, generates a plurality of data signals based on the image data, and applies the plurality of data signals to the active area, and a power supply that supplies a first voltage, a second voltage, an initialization voltage, and a reference voltage to the active area.

[0151] In one embodiment of the present disclosure, each of the plurality of pixels may include a light-emitting element, a first transistor for controlling current flowing in the light-emitting element, a storage capacitor connected to a gate of the first transistor, a second transistor connected to a first terminal of the first transistor for applying a corresponding data signal, a third transistor connected to the gate of the first transistor and a second terminal of the first transistor, a fourth transistor connected to the second terminal of the first transistor for applying the initialization voltage, a fifth transistor connected to the first terminal of the first transistor for applying the first voltage, a sixth transistor connected to the second terminal of the first transistor and the light-emitting element, a seventh transistor connected to the first terminal of the storage capacitor for applying the reference voltage, and an eighth transistor connected to the first terminal of the storage capacitor for applying the first voltage.

[0152] In one embodiment of the present disclosure, the plurality of scan signals may include a first scan signal for turning on or off the fourth transistor, a second scan signal for turning on or off the third transistor and the seventh transistor, and a third scan signal for turning on or off the second transistor.

[0153] In one embodiment of the present disclosure, each of the first to third scan signals may be a first value for turning on a corresponding transistor for at least 2H (Horizontal time).

[0154] In one embodiment of the present disclosure, in the first operation section, the third transistor, the fourth transistor, and the seventh transistor may be turned on, the initialization voltage may be applied to the gate of the first transistor, the reference voltage may be applied to the first terminal of the storage capacitor, and a third voltage determined based on the initialization voltage and the threshold voltage of the first transistor may be applied to the first terminal of the first transistor.

[0155] In one embodiment of the present disclosure, in the second operating section, the second transistor, the third transistor, and the seventh transistor may be turned on, the corresponding data signal may be applied to the first terminal of the first transistor, and a fourth voltage determined based on the corresponding data signal and a threshold voltage of the first transistor may be applied to the gate of the first transistor.

[0156] In one embodiment of the present disclosure, in the third operating section, the fifth transistor, the sixth transistor, and the eighth transistor may be turned on, the first voltage may be applied to the first terminal of the storage capacitor, and a fifth voltage proportional to the amount of change in the voltage of the first terminal of the storage capacitor may be additionally applied to the gate of the first transistor.

Claims

1. Light-emitting element (D1); A first transistor (T1) that controls the current flowing to the light-emitting element (D1); A storage capacitor (C1) connected to the gate of the first transistor (T1); A second transistor (T2) connected to the first terminal of the first transistor (T1) and applying a data signal (Vdata); A third transistor (T3) connected to the gate of the first transistor (T1) and the second terminal of the first transistor (T1); A fourth transistor (T4) connected to the second terminal of the first transistor (T1) and applying an initialization voltage (Vini); A fifth transistor (T5) connected to the first terminal of the first transistor (T1) and applying a first voltage (VDD); A sixth transistor (T6) connected to the second terminal of the first transistor (T1) and the light-emitting element (D1); A seventh transistor (T7) connected to the first terminal of the storage capacitor (C1) and applying a reference voltage (Vref); and An eighth transistor (T8) connected to the first terminal of the storage capacitor (C1) and applying the first voltage (VDD); A display panel (100) including:

2. In paragraph 1, A first scan signal (SC[n-2]) for turning on or off the fourth transistor (T4), A second scan signal (SC[n-1]) for turning on or off the third transistor (T3) and the seventh transistor (T7), and A display panel (100) further comprising a scan driver (SCAN driver) (120) that generates a third scan signal (SC[n]) for turning on or off the second transistor (T2).

3. In paragraph 1 or 2, A display panel, wherein the first to third scan signals (SC[n-2], SC[n-1], SC[n]) are each a first value for turning on a corresponding transistor for at least 2H (Horizontal time).

4. In any one of paragraphs 1 to 3, A display panel (100) further comprising an emission driver (130) that generates an emission signal (EM[n]) for turning on or off the fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8).

5. In any one of paragraphs 1 to 3, A first light emitting signal (EM[n-1]) for turning on or off the fifth transistor (T5) and the eighth transistor (T8), and A display panel (100) further comprising an emission driver (130) that generates a second emission signal (EM[n]) for turning on or off the sixth transistor (T6).

6. In any one of paragraphs 1 to 5, In the first movement section, The third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7) are turned on, The initialization voltage (Vini) is applied to the gate of the first transistor (T1), The reference voltage (Vref) is applied to the first terminal of the storage capacitor (C1), A display panel (100) in which a third voltage determined based on the initialization voltage (Vini) and the threshold voltage of the first transistor (T1) is applied to the first terminal of the first transistor (T1).

7. In any one of paragraphs 1 to 6, In the second movement section, The second transistor (T2), the third transistor (T3), and the seventh transistor (T7) are turned on, The data signal (Vdata) is applied to the first terminal of the first transistor (T1), A display panel (100) in which a fourth voltage determined based on the data signal (Vdata) and the threshold voltage of the first transistor (T1) is applied to the gate of the first transistor (T1).

8. In any one of paragraphs 1 to 7, In the third movement section, The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned on, The first voltage (VDD) is applied to the first terminal of the storage capacitor (C1), A display panel (100) in which a fifth voltage proportional to the amount of change in voltage of the first terminal of the storage capacitor (C1) is additionally applied to the gate of the first transistor (T1).

9. In any one of paragraphs 1 to 8, A display panel (100) in which the first operation section and the second operation section are maintained for at least 1H (Horizontal time).

10. In any one of paragraphs 1 to 9, The first to eighth transistors (T1 to T8) are any one of a low-temperature polycrystalline silicon thin film transistor (LTPS TFT), an oxide thin film transistor (Oxide TFT), a low-temperature polycrystalline silicon oxide (LTPO), or a silicon-based switching element, in a display panel (100).

11. Active area (150) including a plurality of pixels (151) arranged in rows and columns; A scan driver (SCAN driver) (120) that applies multiple scan signals to the display area (150); An emission driver (130) that applies multiple emission signals to the display area (150); A display driver IC (Display Driver Integrated Circuit) (110) that acquires image data, generates a plurality of data signals based on the image data, and applies the plurality of data signals to the display area (150); and A power supply (140) that supplies a first voltage (VDD), a second voltage (VSS), an initialization voltage (Vini), and a reference voltage (Vref) to the display area (150); Including, Each of the above plurality of pixels (151) is Light-emitting element (D1), A first transistor (T1) that controls the current flowing to the light-emitting element (D1), A storage capacitor (C1) connected to the gate of the first transistor (T1), A second transistor (T2) connected to the first terminal of the first transistor (T1) and applying a corresponding data signal (Vdata), A third transistor (T3) connected to the gate of the first transistor (T1) and the second terminal of the first transistor (T1), A fourth transistor (T4) connected to the second terminal of the first transistor (T1) and applying the initialization voltage (Vini), A fifth transistor (T5) connected to the first terminal of the first transistor (T1) and applying the first voltage (VDD), A sixth transistor (T6) connected to the second terminal of the first transistor (T1) and the light-emitting element (D1), A seventh transistor (T7) connected to the first terminal of the storage capacitor (C1) and applying the reference voltage (Vref), and A display device comprising an eighth transistor (T8) connected to a first terminal of the storage capacitor (C1) and applying the first voltage (VDD).

12. In paragraph 11, The above multiple scan signals are, A first scan signal (SC[n-2]) for turning on or off the fourth transistor (T4), A second scan signal (SC[n-1]) for turning on or off the third transistor (T3) and the seventh transistor (T7), and Includes a third scan signal (SC[n]) for turning on or off the second transistor (T2), A display device, wherein the first to third scan signals (SC[n-2], SC[n-1], SC[n]) are each a first value for turning on a corresponding transistor for at least 2H (Horizontal time).

13. In paragraph 11 or 12, In the first movement section, The third transistor (T3), the fourth transistor (T4), and the seventh transistor (T7) are turned on, The initialization voltage (Vini) is applied to the gate of the first transistor (T1), The reference voltage (Vref) is applied to the first terminal of the storage capacitor (C1), A display device, wherein a third voltage determined based on the initialization voltage (Vini) and the threshold voltage of the first transistor (T1) is applied to the first terminal of the first transistor (T1).

14. In any one of paragraphs 11 to 13, In the second movement section, The second transistor (T2), the third transistor (T3), and the seventh transistor (T7) are turned on, The corresponding data signal (Vdata) is applied to the first terminal of the first transistor (T1), A display device, wherein a fourth voltage determined based on the corresponding data signal (Vdata) and the threshold voltage of the first transistor (T1) is applied to the gate of the first transistor (T1).

15. In any one of paragraphs 11 to 14, In the third movement section, The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are turned on, The first voltage (VDD) is applied to the first terminal of the storage capacitor (C1), A display device, wherein a fifth voltage proportional to the amount of change in voltage of the first terminal of the storage capacitor (C1) is additionally applied to the gate of the first transistor (T1).

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