Single phase ac DC power converter with harmonically partitioned power electronics

Abstract

A harmonically partitioned power converter (HPPC) includes a modulation network that synthesizes an AC signal having two voltages at different frequencies and a power electronic network communicatively coupled to the modulation network and having an orthogonal load and a direct load. The power electronic network includes at least one branch communicatively coupled to the modulation network in parallel. Each branch includes an orthogonal branch element, and a direct branch element communicatively coupled to a DC port and to the orthogonal branch element in series. The power electronic network is harmonically partitioned such that each branch draws a branch current at one of the two frequencies. The direct branch element inserts the voltage whose frequency is equal to the branch current frequency, and the orthogonal branch element inserts the other voltage. The orthogonal load absorbs second-line harmonic power such that the HPPC automatically achieves unity displacement factor.

Description

SINGLE PHASE AC DC POWER CONVERTER WITH HARMONICALLY PARTITIONED POWER ELECTRONICSRELATED APPLICATIONS

[0001] This application claims the benefit of U.S. provisional patent application 63 / 626,447, filed January 29, 2024 titled “Single Phase AC / DC Power Converter with Harmonically Partitioned Power Electronics,” the entirety of the disclosure of which is hereby incorporated by this reference.TECHNICAL FIELD

[0002] Aspects of this document relate generally to single phase AC / DC power converters.BACKGROUND

[0003] Single-phase AC / DC power conversion devices are essential for applications such as datacenters, electric vehicle chargers, and consumer device chargers. Traditional power converters typically employ a multistage process, including rectification, power factor correction (PFC), and DC-to-DC conversion, to transform AC input into stable DC output.

[0004] A standard converter architecture involves a diode-bridge rectifier, an electromagnetic interference (EMI) filter, a front-end PFC converter, and an isolated DC / DC converter. The rectifier converts AC to DC, while the EMI filter suppresses high-frequency noise. In many applications, the PFC converter ensures a sinusoidal input current to enable a power factor close to unity, while an energy buffer minimizes voltage ripple by sinking the second harmonic power drawn from the input source. The isolated DC / DC converter regulates the output voltage and provides electrical isolation. Note that power factor can be described as the product of a distortion factor KD which indicates harmonic content in the current waveform through the AC port and a displacement factor K< which indicates the relative phase shift between the voltage and current waveforms. PFC converters regulate the displacement factor K,p to a desired value, typically unity, while EMI filters are used to suppress distortion (i.e., to set KDto unity).

[0005] One significant limitation is that efficiency losses compound across these stages. Even with highly efficient components, the overall efficiency is reduced due to sequential power processing. Additionally, the PFC stage must handle increased RMS currents because of second-line frequency power, further reducing system efficiency.

[0006] Alternative designs, such as bridgeless PFC converters and active energy buffers, address some drawbacks. Bridgeless PFC designs integrate rectification and PFC, reducing component count and improving efficiency. Active energy buffers replace large capacitors with converters capable of high-voltage ripple operation, enabling miniaturization. Despite these advancements, the reliance on multistage architectures still results in increased system size, complexity, and maintenance costs.

[0007] Furthermore, these systems require complex control strategies, with each stage typically needing independent feedback and control loops. The use of bulky capacitors and reactive elements further adds to the system’s size, cost, and weight, while also limiting lifespan.SUMMARY

[0008] According to one aspect, a harmonically partitioned power converter includes a modulation network communicatively coupled to an AC port through which an AC signal is interfaced. The modulation network is configured to modulate a carrier signal with the AC signal and synthesize a modulation signal that is a composite signal having a first voltage at a first frequency and a second voltage at a second frequency. The harmonically partitioned power converter includes a power electronic network communicatively coupled to the modulation network and having an orthogonal load and a direct load. The power electronic network includes at least one branch communicatively coupled to the modulation network in parallel. Each branch of the at least one branch includes an orthogonal branch element having an energy storage element and a direct branch element communicatively coupled to at least one DC port and communicatively coupled to the orthogonal branch element in series. The power electronic network is harmonically partitioned such that each branch draws a branch current at one of the first frequency and the second frequency and inserts both the first voltage and the second voltage. For each branch of the at least one branch, the direct branch element of the branch inserts one of the first voltage and the second voltage whose frequency is equal to the frequency of the branch current in that branch, and the orthogonal branch element of the branch inserts the other of the first voltage and the second voltage. The orthogonal load is implemented by the orthogonal branch elements of the at least one branch, and absorbs second-line harmonic power such that the harmonically partitioned power converter automatically achieves unity displacement factor. The direct load is communicatively coupled to the at least one DC port and processes DC power through the at least one DC port, the direct load being implemented by the direct branch elements of the at least one branch.

[0009] In some embodiments, the energy storage elements of the orthogonal load include buffer capacitors. In some embodiments, an instanteous power processed by the buffer capacitors is equal to the second-line harmonic power drawn from the AC port. In some embodiments, the carrier signal has a carrier frequency that is at least two orders of magnitude greater than the frequency of the AC signal. In some embodiments, the harmonically partitioned power converter also includes an EMI filter communicatively coupled to the AC port and the modulation network. In some embodiments, the modulation network includes a BDS inverter having four bidirectional switches. In some embodiments, the bidirectional switches are monolithic. In some embodiments, the modulation network includes a diode bridge rectifier communicatively coupled with a full-bridge inverter. In some embodiments, the modulation network includes an emulated BDS inverter having four pairs of unidirectionaltransistors, each pair being communicatively coupled in an anti-series back-to-back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs. In some embodiments, the modulation network includes a BDS inverter having two bidirectional switches forming a half-bridge. In some embodiments, the modulation network includes a multi-level inverter.

[0010] In some embodiments, the power electronic network includes two branches interfacing the modulation network to the at least one DC port. In some embodiments, the power electronic network consists of one branch interfacing the modulation network to the at least one DC port. In some embodiments, each orthogonal branch element includes a buffer inverter coupled to the energy storage element. In some embodiments, the buffer inverter includes a BDS inverter having four bidirectional switches. In some embodiments, the bidirectional switches are monolithic. In some embodiments, the buffer inverter includes a diode bridge rectifier communicatively coupled with a full-bridge inverter. In some embodiments, the buffer inverter includes an emulated BDS inverter having four pairs of unidirectional transistors, each pair being communicatively coupled in an anti-series back-to- back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs. In some embodiments, the buffer inverter includes a BDS inverter having two bidirectional switches forming a half-bridge. In some embodiments, the buffer inverter comprises a multilevel inverter.

[0011] In some embodiments, each orthogonal branch element includes a buffer inverter coupled to the buffer capacitor. In some embodiments, the buffer capacitor has variable capacitance. In some embodiments, for each branch carrying a branch current, the orthogonal branch element also includes one of an orthogonal inductor and an orthogonal capacitor selected such that when the one of an orthogonal inductor and an orthogonal capacitor carries the branch current at one of the first frequency and the second frequency, the orthogonal branch element inserts the voltage at the other of the first frequency and the second frequency. In some embodiments, the orthogonal inductor has variable inductance. In some embodiments, the orthogonal capacitor has variable capacitance.

[0012] In some embodiments, for each branch, the direct branch element includes a full wave rectifier communicatively coupled to at least one DC port. In some embodiments, the full wave rectifier is a diode bridge rectifier. In some embodiments, the full wave rectifier employs synchronous rectifiers. In some embodiments, for each branch, the direct branch element includes a full bridge inverter communicatively coupled to the at least one DC port. In some embodiments, for each branch, the direct branch element includes a multi-level inverter.In some embodiments, for each branch, the direct branch element includes a transformer communicatively coupled to the multi-level inverter.

[0013] In some embodiments, for each branch, the direct branch element includes a half-bridge inverter. In some embodiments, the direct branch element includes a transformer communicatively coupled to the half-bridge inverter. In some embodiments, for each branch, the direct branch element also includes a transformer communicatively coupled to the full bridge inverter. In some embodiments, the direct branch element also includes a transformer communicatively coupled to the full wave rectifier. In some embodiments, the modulation network also includes a series resonant filter having a resonant inductor in series with a resonant capacitor. In some embodiments, at least one of the modulation network, orthogonal load, or direct load are controlled to enact variable voltage gain between the AC port and the DC port.

[0014] According to another aspect, a method for AC / DC power conversion through harmonic partitioning includes modulating a carrier signal with an AC signal interfaced through an AC port to synthesize a modulation signal that is a composite signal having a first voltage at a first frequency and a second voltage at a second frequency. The method includes partitioning the composite signal using a power electronic network having at least one branch communicatively coupled to the modulation network. The power electronic network is harmonically partitioned such that each branch draws a branch current at one of the first frequency and the second frequency and inserts both the first voltage and the second voltage. The composite signal is partitioned such that, for each branch of the at least one branch, the branch includes an orthogonal branch element and a direct branch element communicatively coupled to the orthogonal branch element in series, with the orthogonal branch element having an energy storage element; the branch draws current at one of the first frequency and the second frequency; the direct branch element of the branch inserts one of the first voltage and the second voltage whose frequency is equal to the frequency of the branch current in that branch; and the orthogonal branch element of the branch inserts the other of the first voltage and the second voltage. The method also includes achieving a unity displacement factor at the AC port by absorbing second-line harmonic power with an orthogonal load, with the orthogonal load belonging to the power electronic network and being implemented by the orthogonal branch elements of the at least one branch. The method also includes processing DC power with the direct load to exchange power with at least one DC port, the direct load also belonging to the power electronic network and being implemented by the direct branch elements of the at least one branch.

[0015] In some embodiments, the energy storage elements of the orthogonal load are implemented by buffer capacitors. In some embodiments, an instaneous power processed by the buffer capacitors is equal to the second-line harmonic power drawn from the AC port. In some embodiments, the carrier signal has a carrier frequency that is at least two orders of magnitude greater than the frequency of the AC signal. In some embodiments, the modulating is performed using a BDS inverter having four bidirectional switches. In some embodiments, the bidirectional switches are monolithic. In some embodiments, the modulating is performed using a diode bridge rectifier communicatively coupled with a full-bridge inverter. In some embodiments, the modulating is performed using an emulated BDS inverter having four pairs of unidirectional transistors, each pair being communicatively coupled in an anti-series back- to-back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs. In some embodiments, the modulating is performed using a BDS inverter having two bidirectional switches forming a half-bridge. In some embodiments, the modulating is performed using a multi-level inverter.

[0016] In some embodiments, the power electronic network includes two branches. In some embodiments, the power electronic network consists of one branch. In some embodiments, each orthogonal branch element includes a buffer inverter coupled to the energy storage element. In some embodiments, the buffer inverter is a full-bridge inverter. In some embodiments, the buffer inverter employs bidirectional switches. In some embodiments, the bidirectional switches are monolithic. In some embodiments, the buffer inverter includes a diode bridge rectifier communicatively coupled with a full-bridge inverter. In some embodiments, the buffer inverter includes an emulated BDS inverter having four pairs of unidirectional transistors, each pair being communicatively coupled in an anti-series back-to- back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs. In some embodiments, the buffer inverter includes a BDS inverter having two bidirectional switches forming a half-bridge. In some embodiments, the buffer inverter includes a multilevel inverter.

[0017] In some embodiments, each orthogonal branch element includes a buffer inverter coupled to the buffer capacitor. In some embodiments, the buffer capacitor has variable capacitance. In some embodiments, for each branch carrying a branch current, the orthogonal branch element also includes one of an orthogonal inductor an an orthogonal capacitor selected such that when the one of the orthogonal inductor and the orthogonal capacitor carries the branch current at one of the first frequency and the second frequency, the orthogonal branch element inserts the voltage at the other of the first frequency and the second frequency. Insome embodiments, the orthogonal inductor has variable inductance. In some embodiments, the orthogonal capacitor has variable capacitance. In some embodiments, each direct branch element includes a transformer coupled with a full wave rectifier. In some embodiments, the full wave rectifier is a diode bridge rectifier. In some embodiments, the full wave rectifier employs synchronous rectifiers.

[0018] In some embodiments, each direct branch elements includes a full bridge inverter communicatively coupled to the at least one DC port. In some embodiments, the direct branch element includes a multi-level inverter. In some embodiments, the direct branch element comprises a half-bridge inverter. In some embodiments, the direct branch element includes a transformer communicatively coupled to the multi-level inverter. In some embodiments, the direct branch element includes a transformer communicatively coupled to the half-bridge inverter. In some embodiments, at least one of the modulation network, orthogonal load, or direct load are controlled to enact variable voltage gain between the AC port and the DC port.

[0019] According to another aspect, a harmonically partitioned power converter includes a modulation network communicatively coupled to an AC port through which an AC signal is received. The modulation network includes a BDS inverter that is configured to modulate a carrier signal using the AC signal and a high frequency filter to produce a modulation output that is a composite signal having a first voltage at a first frequency and a second voltage at a second frequency. The harmonically partitioned power converter includes a power electronic network communicatively coupled to the modulation network and having an orthogonal load and a direct load. The power electronic network includes a branch communicatively coupled to the modulation network. The branch includes an orthogonal branch element having a buffer inverter and a buffer capacitor sized to process instanteous power equal to a second-line harmonic power drawn from the AC port and a direct branch element having a full bridge switching network communicatively coupled to a DC port. The direct branch element is communicatively coupled to the orthogonal branch element in series. The power electronic network is harmonically partitioned such that the branch draws a branch current at one of the first frequency and the second frequency and inserts both the first voltage and the second voltage. The direct branch element of the branch inserts one of the first voltage and the second voltage, whose frequency is equal to the frequency of the branch current in the branch. The orthogonal branch element of the branch inserts the other of the first voltage and the second voltage. The orthogonal load is implemented by the orthogonal branch elements of the branch, and absorbs second-line harmonic power such that the harmonically partitionedpower converter achieves unity displacement factor. The direct load is communicatively coupled to the DC port and exchanges DC power with that port, the direct load being implemented by the direct branch elements of the branch. The BDS inverter includes four bidirectional switches that are monolithic.

[0020] In some embodiments, the carrier signal has a carrier frequency that is at least two orders of magnitude greater than an input frequency of the AC signal. In some embodiments, the harmonically partitioned power converter also includes an EMI filter communicatively coupled to the AC port and the modulation network. In some embodiments, the buffer inverter is a full-bridge inverter. In some embodiments, the buffer inverter employs BDS devices. In some embodiments, the buffer capacitor has variable capacitance. In some embodiments, the orthogonal branch element also includes one of an orthogonal inductor and an orthogonal capacitor selected such that when the one of the orthogonal inductor and the orthogonal capacitor carries the branch current at one of the first frequency and the second frequency, the orthogonal branch element inserts the voltage at the other of the first frequency and the second frequency. In some embodiments, the orthogonal inductor has variable inductance. In some embodiments, the orthogonal capacitor has variable capacitance. In some embodiments, the direct branch element also includes a transformer communicatively coupled with a full wave rectifier. In some embodiments, the full wave rectifier is a diode bridge rectifier. In some embodiments, the modulation network also includes a series resonant filter comprising a resonant inductor in series with a resonant capacitor.

[0021] According to another aspect, a harmonically partitioned power converter includes a modulation network communicatively coupled to an AC port through which an AC signal having an input frequency is interfaced. The modulation network is configured to modulate a carrier signal with the AC signal and synthesize a modulation signal that is a composite signal having 2N harmonic voltages forming N pairs. Each pair includes a first voltage at a first frequency and a second voltage at a second frequency, the first frequency and the second frequency of each pair being separated by twice the input frequency of the AC signal. The harmonicall partitioned power converter includes a power electronic network communicatively coupled to the modulation network and having an orthogonal load and a direct load. The power electronic network includes at least one branch communicatively coupled to the modulation network in parallel, each branch of the at least one branch including an orthogonal branch element having an energy storage element and a direct branch element communicatively coupled to at least one DC port and communicatively coupled to the orthogonal branch element in series. The power electronic network is harmonically partitionedsuch that each branch draws a branch current at a frequency of one of the 2N harmonic voltages produced by the modulation network and inserts a net voltage equal to the 2N harmonic voltages produced by the modulation network. For each branch of the at least one branch, the direct branch element of the branch inserts the harmonic voltage produced by the modulation network whose frequency is equal to the frequency of the branch current in that branch and the orthogonal branch element of the branch inserts the harmonic voltages synthesized by the modulation network whose frequency is not equal to the frequency of the branch current in that branch. The orthogonal load is implemented by the orthogonal branch elements of the at least one branch, and absorbs second-line harmonic power such that the harmonically partitioned power converter achieves unity displacement factor. The direct load is communicatively coupled to the at least one DC port and processes DC power through these ports, the direct load being implemented by the direct branch elements of the at least one branch.

[0022] Aspects and applications of the disclosure presented here are described below in the drawings and detailed description. Unless specifically noted, it is intended that the words and phrases in the specification and the claims be given their plain, ordinary, and accustomed meaning to those of ordinary skill in the applicable arts. The inventors are fully aware that they can be their own lexicographers if desired. The inventors expressly elect, as their own lexicographers, to use only the plain and ordinary meaning of terms in the specification and claims unless they clearly state otherwise and then further, expressly set forth the “special” definition of that term and explain how it differs from the plain and ordinary meaning. Absent such clear statements of intent to apply a “special” definition, it is the inventors’ intent and desire that the simple, plain and ordinary meaning to the terms be applied to the interpretation of the specification and claims.

[0023] The inventors are also aware of the normal precepts of English grammar. Thus, if a noun, term, or phrase is intended to be further characterized, specified, or narrowed in some way, then such noun, term, or phrase will expressly include additional adjectives, descriptive terms, or other modifiers in accordance with the normal precepts of English grammar. Absent the use of such adjectives, descriptive terms, or modifiers, it is the intent that such nouns, terms, or phrases be given their plain, and ordinary English meaning to those skilled in the applicable arts as set forth above.

[0024] Further, the inventors are fully informed of the standards and application of the special provisions of 35 U.S.C. § 112(f). Thus, the use of the words “function,” “means” or “step” in the Detailed Description or Description of the Drawings or claims is not intended to somehow indicate a desire to invoke the special provisions of 35 U.S.C. § 112(f), to definethe invention. To the contrary, if the provisions of 35 U.S. C. § 112(f) are sought to be invoked to define the inventions, the claims will specifically and expressly state the exact phrases “means for” or “step for”, and will also recite the word “function” (i.e., will state “means for performing the function of [insert function]”), without also reciting in such phrases any structure, material or act in support of the function. Thus, even when the claims recite a “means for performing the function of . . . “ or “step for performing the function of . . . ,” if the claims also recite any structure, material or acts in support of that means or step, or that perform the recited function, then it is the clear intention of the inventors not to invoke the provisions of 35 U.S.C. § 112(f). Moreover, even if the provisions of 35 U.S.C. § 112(f) are invoked to define the claimed aspects, it is intended that these aspects not be limited only to the specific structure, material or acts that are described in the preferred embodiments, but in addition, include any and all structures, materials or acts that perform the claimed function as described in alternative embodiments or forms of the disclosure, or that are well known present or later-developed, equivalent structures, material or acts for performing the claimed function.

[0025] The foregoing and other aspects, features, and advantages will be apparent to those artisans of ordinary skill in the art from the DESCRIPTION and DRAWINGS, and from the CLAIMS.BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The disclosure will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:

[0027] FIGs. 1A, IB, and 1C are block diagrams of conventional AC / DC power converters;

[0028] FIG. 2 is a schematic view of a harmonically partitioned power converter (HPPC) architecture;

[0029] FIG. 3 is a schematic view of an HPPC having two branches;

[0030] FIG. 4 shows the spectrum of two signals before and after multiplication;

[0031] FIGs. 5-7 are schematic views of HPPCs having modulation networks that are BDS-, emulated BDS-, and non-BDS based, respectively;

[0032] FIG. 8 shows observed waveforms of a specific embodiment of an HPPC.

[0015] FIG. 9 is a schematic view of another HPPC having two branches.DETAILED DESCRIPTION

[0033] This disclosure, its aspects and implementations, are not limited to the specific material types, components, methods, or other examples disclosed herein. Many additional material types, components, methods, and procedures known in the art are contemplated for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any components, models, types, materials, versions, quantities, and / or the like as is known in the art for such systems and implementing components, consistent with the intended operation.

[0034] The word "exemplary," "example," or various forms thereof are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" or as an “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Furthermore, examples are provided solely for purposes of clarity and understanding and are not meant to limit or restrict the disclosed subject matter or relevant portions of this disclosure in any manner. It is to be appreciated that a myriad of additional or alternate examples of varying scope could have been presented, but have been omitted for purposes of brevity.

[0035] While this disclosure includes a number of embodiments in many different forms, there is shown in the drawings and will herein be described in detail particular embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the disclosed methods and systems, and is not intended to limit the broad aspect of the disclosed concepts to the embodiments illustrated.

[0036] Single-phase AC / DC power conversion devices are essential for a wide range of applications, including datacenters, electric vehicle on-board chargers, renewable energy systems, and consumer devices chargers. Traditional power conversion devices, integral to supplying stable DC power from AC sources, often encompass a multistage process involving rectification, power factor correction, and DC-to-DC conversion. These stages collectively transform the input AC into a regulated DC output suitable for electronic devices and systems.

[0037] See, for example, FIGs. 1A-1C. FIG. 1A is a block diagram of a conventional single-phase AC / DC power converter with power factor requirements. As shown, the conversion is a multi-stage process that includes a diode-bridge rectifier (e.g., four diodes which rectify the sinusoidal AC input voltage) and an electromagnetic interference (EMI) filter (e.g., to filter the high frequency switching content of the power converter, preventing it frompropagating to the AC input). Also included is a front-end power factor correction (PFC) converter which, in the typical case of unity power factor operation, regulates the input current to be a sinusoid that is proportional to the AC input voltage plus higher order switching frequency harmonics. These harmonics are attenuated by the EMI filter such that the current drawn from the AC input voltage results in a unity power factor. The resulting power drawn from the source has an average component Pdc and a second line-harmonic sinusoidal component having a peak value of Pdc.

[0038] Because only the average power is transferred to the DC output, a typical AC / DC power converter also includes an energy buffer, which decouples the front-end converter and the isolated DC / DC converter. The front-end converter, which is typically a boost converter, works to regulate the voltage around some nominal value, and the capacitor is sized to minimize voltage ripple and to have a nominally DC voltage. This buffer sinks the instantaneous second line-frequency harmonic power being pulled from the input source (e.g., by sinking a line-frequency current).

[0039] Finally, the conventional architecture for a single-phase AC / DC power converter includes an isolated DC / DC converter which enables regulation of the output voltage and provides requisite system isolation. One of the main trade-offs on the size of the capacitive energy buffer is that as its size is reduced, the ripple on this capacitor increases, which requires that the DC / DC converter stage have higher gain variation capability, often resulting in higher loss and volume of this converter.

[0040] The efficiency of this converter is multiplicative. If the diode rectifier has efficiency Trect, the front-end converter has efficiency r / pFC, and the isolated DC / DC converter has efficiency r / dc, then the net efficiency of the converter is ? ^Irect PFc dc

[0041] This inhibits very high efficiencies. For example, if T]rect= 0.995 and the two switching converters have an extremely high efficiency of 0.985, the net efficiency of the converter is only 96.5%. A substantial efficiency penalty is suffered for each of these converters processing power sequentially. It should be noted that the front-end PFC also processes second-line-frequency instantaneous power, which means that it carries increased rms currents than if it just processed DC power.

[0042] A popular modification of this architecture is to use a “bridgeless PFC” converter, as illustrated in FIG. IB. The bridgeless PFC converter integrates the front-end converter with the line-rectifier. As shown, the inductor is placed on the AC-side of the bridge,and two rectifier devices are replaced by controllable switches (e.g. MOSFETs). This integration enables fewer switching devices to be used, which can help improve efficiency and reduce cost.

[0043] A further modification is to use “active energy buffers” (AEB) in which the energy buffer is replaced by another power converter, as illustrated in FIG. 1C. Active energy buffers enable strong miniaturization of the buffer capacitor by moving it to a port of the converter which can swing over a wider voltage range. The active buffer decouples the low- voltage-ripple requirement of the DC / DC converter stage from the high-voltage-ripple operation that enables miniaturization of the buffer capacitor.

[0044] However, despite these modifications, these conventional multi-stage converters come with drawbacks. The separation of functions into distinct stages often results in a larger overall system footprint due to the need for multiple sets of power electronic components. The cumulative effect of losses in each stage can also significantly decrease the overall conversion efficiency. Furthermore, the use of large capacitors for energy buffering in the PFC stage adds to the bulk of the converter and can have a limited lifespan, which can degrade performance over time and increase maintenance costs.

[0045] Another limitation of conventional power converter architectures is the complexity of control strategies required. Each stage typically operates independently, necessitating individual feedback and control loops. This not only increases the complexity of the power conversion device but also requires more sophisticated and expensive control circuitry. Moreover, the reactive elements, such as the inductors and capacitors used in these stages, occupy substantial space and contribute to the weight and cost of the power converter.

[0046] Contemplated herein is a single-phase AC / DC power converter that uses harmonically partitioned power electronics to consolidate the conventional rectification, PFC, and DC / DC conversion stages into a smaller, more integrated solution.

[0047] According to various embodiments, this architecture reduces component count, converter volume, and potential points of failure, as well as simplifying control schemes and improving overall efficiency. This consolidation is accomplished through the use of a power electronic network that efficiently partitions the power into streams running in one or more parallel branches. The AC input is modulated with a high frequency carrier wave to produce known voltage harmonics that are then processed by the harmonically partitioned power electronic network. Each branch of the power electronic network is made up of segments connected in series, one segment optimized for delivering DC power, the other(s) optimized for harmonic buffering. While each branch inserts several harmonics, each branchideally only carries one current harmonic of the composite modulated signal. This architecture not only simplifies the overall power conversion process, but also minimizes the need for large passive components, offering a more compact, efficient, and reliable solution compared to conventional power conversion devices.

[0048] The integrated architecture contemplated herein could address the need for large, failure-prone components and result in a smaller, more cost-effective, and energyefficient power conversion device that is able to greatly reduce energy storage in the buffer capacitor, according to various embodiments. The contemplated architecture makes better use of the passive components in the system, a boon to miniaturization efforts as these components represent the dominant bottleneck on volume and weight in traditional single-phase AC / DC power converters. Instead of relying on distinct front-end and back-end conversion stages and a discrete energy buffering port between them, the architecture synergistically combines these functions into a single effective architecture.

[0049] As will be discussed below, the contemplated harmonically partitioned power converter (hereinafter HPPC) architecture is centered upon the single or multi-branch power electronic network loading an inverter such that each branch supports a single harmonic current carried by the output of the modulation network. Each branch comprises at least two series-connected power electronic elements, where each element inserts a voltage equal to one or more of the harmonic voltages at the output of the modulation network, such that a DC element (which processes DC power) and a buffer element (which processes second line harmonic power) can be discretely identified in each branch. This means that the branch element which processes the DC power need not be concerned with harmonic power buffering, and the branch element which provides buffering need not be concerned with any DC power processing. This partitioning is highly advantageous since the power electronic elements in the architecture can be optimized around these single functions. Additionally, while these elements also process higher-order frequency power, these very high frequency components can be easily mitigated by relatively small L and C filter elements in these networks, according to various embodiments.

[0050] In addition to enabling the discrete partitioning between the buffering components and the DC output components, the contemplated HPPC architecture also automatically achieves unity displacement factor at the input without requiring a separate stage for that purpose, as is ubiquitous to traditional power converters. None of the elements in the network is assigned directly to the task of regulating unity power factor. The buffer elements simply absorb 2nd harmonic power, and the DC elements simply absorb DC power. Byperforming these actions in the architecture, unity displacement factor can be automatically achieved, thereby reducing the number of conversion stages.

[0051] The contemplated HPPC architecture is especially well-suited to leveraging a strong miniaturization benefit from emerging monolithic Bidirectional Switch (BDS) semiconductor devices, according to various embodiments. Monolithic wide band gap power semiconductors capable of four quadrant operation (i.e., blocking bidirectional voltage and carrying bidirectional current) are emerging and becoming commercially available. A four- quadrant device such as this will hereinafter be called a “Bidirectional Switch” (BDS). Historically, BDSs have been implemented using two discrete unipolar power semiconductor devices. This has impeded strong interest in power electronic architectures that require BDS devices.

[0052] The contemplated harmonically partitioned power converter architecture is well suited to leverage the advent of new monolithic BDSs capable of high switching frequencies. Embodiments comprising BDS devices, particularly monolithic BDS devices, may provide a number of additional advantages over conventional power conversion solutions. The ability to directly use BDS devices to interface a buffer capacitor to the buffer element in a branch facilitates the maximum usage of the energy storage capability of the capacitor, thus driving its miniaturization. Additionally, control over the modulation signal in the BDS inverter can be used to change the voltage on the DC elements. Thus, in some embodiments, it is possible for the HPPC to function as a DC / DC converter without requiring a separate DC / DC converter stage, also facilitating miniaturization. Furthermore, because the two-branch network loads the BDS inverter as an effective resistor, a small degree of inductance can be added to the output of the inverter to guarantee zero-voltage switching of the BDS inverter switches. This enables the architecture to be operated at high switching frequencies, again providing further miniaturization.

[0053] According to various embodiments, the HPPC architecture specially loads an inverter to enable discrete partitioning between the buffering components and the DC output components while also automatically achieving unity displacement factor at the input. The ability for a BDS switch to block bidirectional voltage naturally encourages its use for direct AC-to-AC conversion, and enables highly miniaturized elements in this power conversion architecture. However, it should be noted that some embodiments of the HPPC architecture do not require BDS device, as will be discussed below.

[0054] FIG. 2 is a schematic view of a non-limiting example of a harmonically partitioned power converter 200 (HPPC) architecture. As shown, the HPPC 200 comprisestwo main parts: a modulation network 202, and a power electronic network 204. Each will be discussed in turn. Although not shown in FIG. 2, HPPC 200 also comprises an EMI filter before modulation network 202, according to various embodiments (see FIG. 3).

[0055] According to various embodiments, the modulation network 202 is communicatively coupled to an AC input port 212 through which an AC input signal 216 is received. The modulation network 202 is responsible for modulating and filtering the incoming AC input signal 216 such that it becomes a composite signal 220 made up of understood and predictable voltage harmonics that can be efficiently processed or absorbed by the power electronic network 204, which is harmonically partitioned. Although the AC port 212 is described as an input port, HPPC 200 may be bidirectional such that AC port 212 acts as an output port in some instances and outputs an AC signal. In this situation, the DC output port 214 discussed below would be an input port.

[0056] Those with skill in art will recognize that there are a number of ways to modulate a signal. While this and other non-limiting examples of an HPPC 200 are done in the context of a modulation network 202 that includes switches that perform amplitude modulation using the AC input signal 216, in other embodiments different forms of modulation may be employed. Amplitude modulation, particularly modulating a high frequency carrier using the AC input signal 216 results in a composite signal 220 made up of signals having much higher frequencies than the AC input signal 216. Higher frequencies are easier to attenuate, and can be dealt with using circuitry that is smaller and more efficient in comparison to what is required to deal with second-line harmonics and comparable lower frequencies. Similarly, the modulation network 202 may also incorporate high frequency filtering which permits certain desired high frequency content in the composite signal 220. For example, in an example embodiment the modulation network 202 incorporates an LC filter which results in the composite signal 220 primarily comprising two harmonics, whereas amplitude modulation applied in this example embodiment without the filter would produce many more harmonics at multiples of the switching frequency.

[0057] The HPPC 200 further comprises a power electronic network 204 communicatively coupled to the modulation network 202. According to various embodiments, the power electronic network 204 is used to load the modulation network 202 with harmonically partitioned pathways that, combined, load the modulation network 202 with an orthogonal load 222 and a direct load 224. These loads serve very specific purposes. The fact that they are able to be partitioned, as discussed below, is the source of many of the advantages the contemplated HPPC 200 architecture offers over conventional converters.

[0058] According to various embodiments, the orthogonal load 222, which could also be referred to as the buffer load, the quadrature load, or the reactive load, is communicatively coupled to the modulation network 202, as shown. The orthogonal load 222 absorbs second-line harmonic power 228 and the direct load 224 absorbs DC power 226 such that HPPC 200 appears to the AC input signal 216 as a resistive load, thereby automatically achieving unity displacement factor.

[0059] In the context of the present description and the claims that follow, a unity power factor, and a unity displacement factor, is greater than 0.96, and ideally equal to 1.

[0060] According to various embodiments, the direct load 224 (or DC load), is communicatively coupled to at least one DC output port 214. The direct load 224 processes DC power 226 and interfaces with a DC output port 214.

[0061] According to various embodiments, the power electronic network 204 effectively applies these two loads to the modulation network 202, each tuned to accomplish one of the two main tasks of a single-phase AC / DC power converter. Specifically, absorb the power of the harmonics inherent to single-phase power conversion (e.g., the second-line harmonics, etc.) to achieve unity power factor, and produce a DC output.

[0062] Structurally, the power electronic network 204 is made up of one, two, or more branches 206. These branches 206 are communicatively coupled in parallel across the output of the modulation network 202. Each branch 206 of the power electronic network 204 is made up of at least one orthogonal branch element 208 and a direct branch element 210, with all elements in a branch 206 communicatively coupled in series.

[0063] According to various embodiments, each branch element (e.g., orthogonal branch element 208, direct branch element 210) is configured to insert a voltage such that the sum of voltages within any branch 206 is equal to the voltage of the composite signal 220. Additionally, the sum of the currents of each branch 206 equals the current flowing through the output of the modulation network.

[0064] As previously discussed, the modulation network 202 takes the AC input signal 216 and produces a composite signal 220 made up of known harmonics. Each branch element is tuned to address an aspect (e.g., absorbing harmonic power, processing DC power) for one of those harmonics. This harmonic partitioning of the power electronic network 204 gives the HPPC 200 a number of advantages over conventional power converters including, but not limited to, better efficiency in a smaller size as well as automatic unity power factor. Other aspects of the HPPC 200 architecture provide additional benefits, as will be discussed below.

[0065] The direct load 224 is implemented by the direct branch elements 210 of the branch 206 or branches 206 of the power electronic network 204. Additionally, the orthogonal load 222 is implemented by the orthogonal branch elements 208 of the branch 206 or branches 206.

[0066] It should be noted that while the following discussion will focus on embodiments of the contemplated HPPC 200 whose power electronic network 204 has one or two branches 206, in other embodiments of the HPPC 200 there may be additional branches 206 to accommodate higher frequency harmonics in the composite signal 220. In the nonlimiting examples discussed below, the AC input signal 216 is modulated and filtered to produce a composite signal 220 having two voltage harmonics.

[0067] According to various embodiments, each branch 206 has a branch element for each voltage harmonic that makes up the composite signal 220. Specifically, each branch 206 has at least one direct branch element 210 and at least one orthogonal branch elements 208, the net voltages associated with these elements totaling up to the voltage of the composite signal 220.

[0068] According to various embodiments, an HPPC 200 whose modulation network 202 generates N pairs 400 of voltage harmonics always has at least one direct branch element 210 in series with at least one orthogonal branch element 208, such that in sum they insert a voltage equal to the 2N voltage harmonics of the composite signal 220. The HPPC 200 will employ at least one branch 206 to carry at least one harmonic current, though more than this number of branches can be used. See, for example, the non-limiting example of an HPPC 200 with two harmonics and two branches 206 shown in FIG. 3 and the non-limiting example of a two branch Power Electronic Network 204 shown in FIG. 9. In other embodiments, an HPPC 200 having 2N voltage harmonics may only use one branch 206 and may carry a single harmonic current. See, for example, the non-limiting example of an HPPC 200 with two voltage harmonics and a single branch 206 shown in FIG. 5.

[0069] In other embodiments, high frequency filtering may be incorporated into each branch instead of only being deployed within the modulation network 202. This permits high-frequency filtering elements to be installed having lower current processing requirements of the branch. In these cases, such filtering elements still result in the desired composite signal 220 being applied to each branch of the power electronic network.

[0070] FIG. 3 is a schematic view of a non-limiting example of a harmonically partitioned power converter 200 whose power electronic network 204 has two branches 206. According to various embodiments, the modulation network 202 comprises a full-bridgeinverter 322 which connects to an AC input voltage 216 on its low-frequency AC terminal and can produce an “amplitude modulated” voltage signal, and an optional high frequency filter 303 which filters this voltage signal to produce the composite voltage signal 220, hereinafter denoted VHF. This allows clear identification / specification of the harmonics in VHF.

[0071] As discussed above, the power electronic network 204 comprising multiple parallel branches 206 loads the modulation network 202 such that each branch 206 supports the full composite voltage 220 VHF but only carries current at a particular harmonic of VHF. The result is that the elements in each branch 206 can be decomposed into those which carry DC power 226, and those that carry 2nd line harmonic power 228, thus creating a clean partition between elements which support buffering the twice-line power and elements which process the desired DC power 226. Furthermore, the power electronic network 204 can be designed such that the current drawn from the inverter 300, IHF, yields unity power factor on the AC input port 212, according to various embodiments.

[0072] According to various embodiments, the contemplated architecture can achieve DC / DC conversion, twice-line frequency AC power buffering, and input power factor correction using a single effective converter stage. The result is a high efficiency conversion architecture which can enable dramatic miniaturization compared to traditional approaches. In some embodiments, BDS devices enable optimal implementations of the branch elements which load the inverter 300, but in other embodiments a BDS inverter 300 is not necessarily required for the modulation network 202 stage, as will be discussed in the context of FIG. 7, below.

[0073] The modulation network 202 is configured to modulate a high frequency carrier signal 304 using the AC input signal 216 to produce a modulation output 306 that is a composite signal that can be decomposed into known harmonics. After optional filtering (e.g., high frequency filter 303, etc.), the composite signal 220 is produced. The non-limiting example of an HPPC 200 shown in FIG. 3 is configured to handle a composite signal 220 having two high frequency components, hereinafter referred to as the first voltage 310a and the second voltage 310b, with the first voltage 310a oscillating at a first frequency 314a, and the second voltage 310b oscillating at a second frequency 314b. Branch currents 308 flow in the branches, the first current 312a oscillating at the first frequency 314a and the second current 312b oscillating at the second frequency 314b. In other embodiments, the power electronic network 204 may comprise additional branches 206 to support branch currents 308 at the frequencies of the composite signal 220.

[0074] The non-limiting example of an HPPC 200 shown in FIG. 3 makes use of a full-bridge inverter 322 performing amplitude modulation. However, there are numerous ways to implement an inverter 300 or to modulate a signal such that the desired composite voltage VHF is generated including, but not limited to, half-bridge inverters, multi-level inverters, square-wave and zero-state modulation, sinusoidal pulse width modulation, and the like. For example, one particular non-limiting example makes use of four bidirectional switches 302, square wave modulation 304, and an LC filtering element 303 tuned to allow only harmonics close to the carrier frequency 316 of the carrier signal 304 to pass through to the composite signal 306 (greatly mitigating higher frequency content). Another non-limiting example makes use of four bidirectional switches 302, sinusoidal pulse width modulation, and no high frequency LC filtering element 303.

[0075] In some embodiments, the BDS inverter 300 may employ monolithic bidirectional switches 302. Emerging monolithic wide-bandgap (WBG) BDS devices aim to replace the current "emulated" approach consisting of anti-series "back-to-back" transistors. Monolithic bidirectional switches 302 may further reduce losses and cost and enhance efficiency by directly integrating bidirectional voltage blocking into a single device.

[0076] It should be noted that while much of the discussion herein is in the context of embodiments comprising monolithic bidirectional switches 302, the advantages of the contemplated harmonically partitioned power converter 200 over conventional power converter architectures are not entirely dependent on the use of monolithic bidirectional switches 302. Embodiments having a modulation network 202 where the bidirectional switches 302 of a BDS inverter 300 are emulated and where they are omitted all together will be discussed in the context of FIGs. 6 and 7, respectively.

[0077] The HPPC 200 further comprises an Electromagnetic Interference (EMI) filter 320 communicatively coupled to the AC input port 212 and the modulation network 202. The HPPC's switching elements, such as the BDS inverter 300, generate high frequency noise (at the harmonics of the switching frequency) which must be mitigated to meet interconnection standards (e.g., IEC 61000). The EMI filter 320 attenuates these high frequency components to prevent them from propagating back to the AC source, according to various embodiments.

[0078] Consider the control of this four-switch network as a full-bridge inverter, such that SI and S4 switch on and off at the same time, and switches S2 and S3 switch on and off at the same time. SI and S2 switch in a complementary manner (excepting the normal requirement for a short deadtime between their on / off states where they are both off, to avoid shoot-through - this deadtime may also be used to achieve zero voltage switching of the BDSdevices). The inverter 300 receives a modulation command m(t) and produces a modulation output:

[0079] According to various embodiments, m(t) is a periodic signal which commands the four switching devices on and off. For the purposes of clarity, the following discussion will be done in the context of the BDS inverter 300 operating as a full-bridge inverter with no deadtime. In such a case, m(t) takes on values of “1” and “-1”. When m(t)=l, S2 and S3 are on, and when m(t)=-l, SI and S4 are on. The AC input voltage 216 is sinusoidal at a radial frequency mg, corresponding to a frequency of fo=cog / 27t. The modulation command is periodic at HF, which is larger than fo.

[0080] The specification of m(t) for an inverter 300 is well-explored. One popular example is sinusoidal pulse width modulation, mspwM(t), where mspwn(H =ma si (.2nfspWMt) + HF Harmoncis a»HF

[0081] Where / SPWM « HF, such that the unwanted harmonics can be filtered out using relatively simple filters having relatively low corner frequencies, and mais a “modulation index” between 0 and 1.

[0082] In general, m(t) is a periodic signal that obeys the Dirichlet conditions and can be described by its Fourier series. So, m(t) can also be thought of as the sum of sinusoids each having a frequency equal to HF or an integer multiple of HF. The amplitude and phase of these Fourier components are called the “spectrum” of the signal. Because m(t) can always be described by sinusoidal components using the Fourier series, the function of the BDS inverter 300 may be interpreted as an amplitude modulator (similar to the amplitude modulation used in AM radio). A result of amplitude modulation is that the output spectrum follows a simple “sideband production” rule, where multiplication in the time domain corresponds to convolution in the Fourier (or “frequency”) domain. This property is illustrated in FIG. 4.

[0083] In amplitude modulation, fuF is often called the “carrier”. As shown, the input frequency 318 of the AC input signal 216 is much lower than the carrier frequency 316 of the signal 304 used by the inverter 300 to produce the composite signal 220. The spectrum of the composite signal 220 shows the two sidebands, which are being referred to as the first frequency 314a (of the first voltage 310a) and the second frequency 314b (of the second voltage 310b). These frequencies are much higher than the AC input signal 216, which facilitates a number of goals of the HPPC 200 such as miniaturization and efficiency, as will be discussed below. In some embodiments, the carrier signal 304 may have a carrier frequency 316 that isat least two orders of magnitude greater than the input frequency 318 of the AC input signal 216.

[0084] Another popular example is square-wave modulation, msQ (t) where

[0085] The BDS full-bridge inverter can be viewed as a square wave amplitude modulator, which performs this kind of frequency mixing yielding “sideband” harmonic content around the high frequency “carrier”. Because m(t) can be described as the sum of sinusoids, and because this frequency mixing property is linear, the possible frequency content that can be developed by this modulation is also simple to compute. As a specific, non-limiting example, consider an embodiment where m(t) is a single frequency sinusoid m(t) = M sm 2nfHPt)

[0086] M is some real number, for generality. Note that this could be derived from SPWM, where the high frequency content that is produced is easily filtered, and thus reasonably described as a pure tone. In this case, M would be the carrier amplitude. This singlefrequency description could also represent various embodiments using square-wave modulation with a high-quality filter 303 included in the modulation network that filters the non-fundamental harmonics produced by the output (e.g., as is done in the common LLC converter). The output of the modulation network in this non-limiting example is

[0087] Which can be expanded toIgM ZzzVHF = — [cos \ )HP- a)g)t) - cos( a>HP+ jg)t)]

[0088] This is representative of the familiar result found in AM radio, where the modulation (multiplication) of a low frequency “message" signal and a high frequency “carrier" signal results in sideband harmonic generation around the high frequency carrier. The modulation network 202, here comprising the BDS inverter 300 and the high frequency filter 303, can therefore be thought of as having inserted two voltage components (i.e., sideband harmonics) to the rest of the system, hereinafter referred to as v+ and V-. vHP= v++ v_

[0089] where the - and + subscripts denote the negative and positive sideband, respectively.

[0090] According to various embodiments, the HPPC 200 architecture is operated such that unity displacement factor is drawn from the AC input port 212. Thus, the HPPC 200 appears after EMI filtering as a resistor Racto the input source. This means that the input powerPin I®

[0091] For simplicity, this discussion will proceed under the assumption that the BDS inverter 300 and high frequency filter 303 are lossless such that this power is passed through to the output of the modulation network. Consider drawing a current IHF that is in- phase with VHF (i.e. that the composite signal is effectively loaded by a resistance Re).VHF lHF — t_ + i+

[0092] To ensure the converter will draw current that allows unity power factor operation (e.g., 60Hz plus higher frequency switching harmonics), the modulation network 202 must be loaded with an effective resistance Re. For this case, the current IHF (t) is found as10093] This current has the same sideband harmonics as the composite signal 220 inserted by the BDS inverter 300. If the orthogonal load elements 208 and the direct load elements 210 maintain the voltages shown in FIG. 3 and the current inp(t) splits such that i-(t) flows in one branch 206 while i+(t) flows in the other (in this non-limiting example of a two branch power electronic network 204), the HPPC 200 will draw unity displacement factor current while completely decoupling the de and 2coginstantaneous power in the system, according to various embodiments.

[0094] Since VHF and IHF each contain two harmonics at the same frequencies, four harmonics and a DC value are anticipated in their product (0, 2nd, 2COHF, 2(COHF ± mg)), per the sideband modulation principle. Specifically:

[0095] Thus, pHF(t) can be expressed as the sum of pin(t) plus three additional high- frequency power components. According to various embodiments, these high frequency harmonics can be accommodated by an input EMI filter 320. The central difficulty of the second line-harmonic power 228 is that it is at a relatively low frequency, and thus classically requires relatively large capacitance to buffer without experiencing large voltage ripple.

[0096] According to various embodiments of the harmonically partitioned power converter 200 contemplated herein, a power electronic network 204 is connected to the output of the modulation network 202 and is configured to operate on the principle of decomposing the harmonics of the modulation output 306 into their constituent parts. For example, in the non-limiting example of HPPC 200 architecture shown in FIG. 3, two branches 206 are used, each comprising power electronic elements that insert one of the two harmonics of VHF. Similarly, the branches 206 each carry one of the two harmonics of IHF.

[0097] The result is that these network elements clearly partition the DC and harmonic power being output by the inverter. For example, in the branch 206 carrying i-, hereinafter referred to as the “minus” branch 206, the power absorbed by the branch 206 isP- P-,buff d” P-tdc

[0098] The first term is the result of the branch current i- flowing through an orthogonal load element that inserts v+. This is the product of a voltage and current at different frequencies (i.e., these are “orthogonal” signals), resulting in instantaneous power absorption only at the 2nd and 2COHF harmonics. This power will hereinafter be referred to as the buffer power in the minus branch 206 (p-,buff)

[0099] Thus, the orthogonal load element 208 that inserts v+ 310b in this branch 206 absorbs half of the 2nd harmonic power and half of the 2COHF power present in PHF.

[0100] The other series element in this branch 206 inserts V-, which is at the same frequency as i-, and absorbs an instantaneous power of:

[0101] This will be referred to as the DC power 226 in the minus branch 206, p.,dc. Thus, the direct load element 210 that inserts v- 310a in this branch 206 absorbs half of the DC power and all the 2(COHF - mg) power present in PHF.

[0102] This clear partitioning provides an advantage over conventional systems: one element in this branch 206 is responsible for absorbing second line harmonic power 228, and the other element is responsible for absorbing DC power 226, allowing each series element to be designed and optimized for their particular task.

[0103] Similarly, in the branch 206 carrying i+, hereinafter referred to as the “plus” branch 206, the power absorbed isP+ = p+ibuff + p+idc

[0104] where ]

[0105] Putting this in more general terms, if each branch 206 draws a different one of the first current 312a (e.g., i-) and the second current 312b (e.g., i+) and inserts both the first voltage 310a (e.g., v-) and the second voltage 310b (e.g., v+) then, in a branch 206 carrying the first current 312a oscillating at the first frequency 314a, the direct branch element 210 of that branch 206 inserts the first voltage 310a (also oscillating at the first frequency 314a), and the orthogonal branch element 208 of that branch 206 inserts the second voltage 310b (oscillating at the second frequency 314b), according to various embodiments. Similarly, in a branch 206 carrying the second current 312b oscillating at the second frequency, the direct branch element 210 of that branch 206 inserts the second voltage 310b (also oscillating at the second frequency 314b), and the orthogonal branch element 208 of that branch 206 inserts the first voltage 310a (oscillating at the first frequency 314a), according to various embodiments.

[0106] Table 1 shows how this non-limiting example of a power electronic network 204 partitions the various power components, expressed in terms of the harmonic content of Vg M2the instantaneous power normalized byTable 1

[0107] Thus, this non-limiting example of a two-branch HPPC 200 architecture comprises power electronic elements that clearly partition the DC 226 and 2nd harmonic 228 power output by the modulation network 202. As previously discussed, this may provide advantages in efficiency as well as miniaturization, according to various embodiments.

[0108] It is noted that the DC power processed by each DC load element can be delivered to a single DC output, as in conventional single-phase AC / DC power conversion, or to multiple DC outputs if such functionality is desired (e.g., to interface two DC loads to the sinusoidal input voltage). If a single output is desired, then an additional high frequency filter element may be optionally employed for the two DC load elements to be AC decoupled but DC coupled. In some embodiments, this can be achieved by using additional inductors, while in other embodiments this can be achieved by leveraging a Coupled Electronic and Magnetic System structure.

[0109] In some embodiments, it is possible to omit one of the two branches 206 for each harmonic (e.g., going from two branches 206 to one branch 206 in the non-limiting example of FIG. 3) without losing all of the benefits provided by the two branch 206 architecture. For clarity, this is named a “single branch” implementation. For example, if only the plus branch 206 is employed, and current i+ is drawn which equals v+IRe, the power VgM2distribution shown in Table 2 results (again normalized by — — ): 4ReTable 2

[0110] It should be noted that this is still a power flow that respects unity power factor, since only DC, second, and high-frequency harmonic power is drawn from the input. According to various embodiments, a single branch 206 construction involves fewer devices, without sacrificing the benefits of automatic unity power factor, true minimum energy storage, power decoupling between the orthogonal and direct loads, and galvanic isolation. However, this also increases the current (e.g., first current 312a, second current 312b, etc.) in the branch 206 for the same power throughput as in the two-branch 206 architecture. Furthermore, because the BDS inverter 300 is no longer loaded by an effective resistance (i.e., it is a non-linear load, since it only draws current at one of the two harmonic frequencies of the inverter voltage), ZVS may not be guaranteed in all operating conditions. Nevertheless, some single branch embodiments may be more attractive in cases where minimizing component count is a priority.[OHl] FIGs. 5-7 are schematic views of non-limiting examples of a single branch HPPC 200 having a modulation network 202 that is BDS-, emulated BDS-, and non-BDS based, respectively. Each will be discussed in turn.

[0112] As shown in FIG. 5, the single branch 206 comprises a direct branch element 210 and an orthogonal branch element 208. In some embodiments, the direct branch element 210 may be implemented using a full wave rectifier 506 connected to the DC output port 214. For example, in some embodiments full wave rectifier 506 may be a diode bridge rectifier 700, while other embodiments may employ synchronous rectifiers. In some embodiments, where the DC port functions as the input, a full-bridge inverter 322 or other switching networks including, but not limited to, half-bridge inverters, multi-level inverters, square-wave and zerostate modulation, sinusoidal pulse width modulation, and the like, may be employed. As shown, the full wave rectifier 506 connects to a high-frequency filter capacitor Co and to a resistor RL, which models the (DC) system load. In some embodiments, the direct branch element 210 may also include a transformer 508 connected to the full wave rectifier 506 to provide galvanic isolation.

[0113] According to various embodiments, the orthogonal branch element 208 may comprise an energy storage element 501 that is used for buffering (i.e., able to process second- line harmonic power). Examples include, but are not limited to, capacitors, inductors, piezoelectrics, flywheels, batteries, and any other forms of energy storage known in the art. In some embodiments, including the non-limiting example shown in FIG. 5, the energy storage element 501 is a buffer capacitor 500 CB, that is connected to the rest of the power electronic network 204 through an inverter, hereinafter referred to as the buffer inverter 502 to distinguish it from the inverter belonging to the modulation network 202 in some embodiments. The buffer capacitor 500 may be any form of capacitor (e.g., film, electrolytic, etc.). Unlike buffer capacitors in conventional power converters, the buffer capacitors 500 of an HPPC 200 do not have to regulate a DC voltage due to the harmonic partitioning of the power electronic network 204. This reduced demand greatly improves miniaturization, and opens up types of capacitors that would otherwise be inappropriate if used to buffer a conventional power converter.

[0114] In some embodiments, including the non-limiting example shown in FIG. 5, the buffer inverter 502 is a BDS inverter 300 comprising four monolithic bidirectional switches 302. In other embodiments the buffer inverter 502 may be a full-bridge inverter 322 of some other form, or other switching networks including, but not limited to, half-bridge inverters, multi-level inverters, square-wave and zero-state modulation, sinusoidal pulse width modulation, and the like.

[0115] The orthogonal branch element 208 may also comprise an “orthogonal” inductance, Lo, which ensures the orthogonal branch element 208 takes on the requisite V- voltage, as shown. More specifically, according to various embodiments, the orthogonal inductor 504 is selected such that when the orthogonal inductor 504 carries the second current 312b (e.g., i+) at the second frequency 314b (e.g., f+), the orthogonal branch element 208 inserts the first voltage 310a (e.g., v-) at the first frequency 314a (e.g., f-). In the example shown in FIG. 5, the orthogonal inductor 504 carries the single branch current at frequency f+ such that the orthogonal branch element 208 inserts v_. Note that, according to various embodiments, such as the non-limiting example shown in FIG. 9, an orthogonal capacitor 900 may be used in place of an orthogonal inductor such that when the orthogonal capacitor carries the first current 312a (e.g., i-) at the first frequency 314a (e.g., f-), the orthogonal branch element inserts the second voltage 310b (e.g., v+) at the second frequency 314b (e.g., f+).

[0116] According to some embodiments, the buffer inverter 502 (e.g., a BDS inverter 300) may be operated with square wave modulation mbuir (t):

[0117] Where permits a possible time delay between the modulation of the buffer inverter 502 and the modulation of the main BDS inverter 300. The contemplated single branch architecture may also include a series resonant filter 510 to realize the modulation network 202, comprising resonant inductor 512 Lrin series with a resonant capacitor 514 Cr, which are selected such that = fHF. This filter operates in a similar fashion as in a conventionalLLC converter, performing AC harmonic filtering such that the current flowing through the converter, IHF, is primarily sinusoidal at HF + fo.

[0118] This series resonant filter 510 allows an analytical assessment of this nonlimiting example architecture using the fundamental harmonic approximation. Under this approximation, VHF, V+, and V- are considered to be sinusoidal at the fundamental frequency, thus producing:4 M = -7T

[0119] Where mgis the angular line frequency (e.g., 2TT(50) or 2TT(60) rad / s). According to various embodiments, the system is operated such that i+ flows through the branch 206:

[0120] In this exemplary embodiment, the direct load is implemented by an NP:Ns transformer 508 connected through a full-bridge diode rectifier to a load RL in parallel with a filter capacitor Co. As in a conventional LLC converter with a full-bridge rectifier connected to the secondary of an NP:Ns transformer 508 and operating with a sinusoidal input current and a DC output voltage, the load resistance RL can be mapped to the primary side of the transformer 508 as an effective resistance as

[0121] According to various embodiments, the buffer power processed by the orthogonal branch element 208 of this non-limiting example of a single-branch 206 HPPC 200 is

[0122] The buffer capacitor 500 will process only second-harmonic power 228 if it has a sinusoidal or full-wave-rectified sinusoidal voltage. For example, a sinusoidal voltage on the buffer capacitor 500 of vcbuff= VA sin(m5t - 45°)

[0123] will result in an instantaneous power of

[0124] For this to equal the buffer power requirement, VA must be

[0125] The voltage inserted through the buffer inverter 502 depends on the square wave modulation of that inverter, which can be expressed using the fundamental harmonic approximation to be

[0126] Choosing p=-45° shows the voltage inserted by the buffer inverter 502 to be

[0127] This is close to the desired voltage to be inserted, V-, namely ifVA / i = VQCJ

[0128] then Vbuff inserts v- and an additional undesired quadrature (sine) voltage component. Note that this relationship can be ensured in the buffer capacitor 500 by choosing its value to be

[0129] The orthogonal inductor 504 Lo compensates for the quadrature part of Vbuir (which is not in V-). Namely, if this inductor 504 carries i+, then its voltage drop is

[0130] Thus, if Lo is selected such that

[0131] the result is

[0132] and the net voltage drop across the orthogonal branch element 208 is

[0133] as desired. It should be noted that in other embodiments, this branch 206 could have been selected to carry i-, in which case the orthogonal branch element 208 inserts v+ and the power factor correcting element may be a capacitor instead of an inductor.

[0134] According to various embodiments, this single branch architecture for the contemplated HPPC 200 provides several efficiency benefits. The BDS buffer inverter 502 can achieve ZVS, minimizing its loss. The input BDS inverter 300 achieves ZVS over half of the line cycle, which helps to minimize loss. ZVS is not achieved over the full line-cycle because of the choice to employ only a single branch 206 carrying i+. Full ZVS is achievable in embodiments where a two-branch architecture or higher is used.

[0135] Although this embodiment employs eight bidirectional switches 302, it is important to note that the DC / DC and PFC functions are also automatically achievable without additional switching stages. A high performing DC / DC converter may itself be an LLC converter which comprises 4 inverter and 4 rectifiers switches. One perspective of the architecture is that by tightly integrating these functions, conversion redundancies are removed, and overall efficiency and miniaturization can be maximized, according to various embodiments.

[0136] Furthermore, by processing second-line harmonic power 228 in a buffer capacitor 500 which has a 60Hz sinusoidal voltage across it, this capacitor 500 can be rated for the exact energy storage required for 2nd harmonic power buffering, greatly aiding miniaturization.

[0137] It should be noted that the values of CB and Lo in the above discussion are load dependent. In some embodiments, a mechanism exists for varying them in proportion to the load. For example, a specific, non-limiting embodiment may operate with a fixed voltage gain, such that v+ across the direct branch element 210 is fixed. The buffer capacitor’s value is:

[0138] So, as the load power reduces (i.e., RL increases for the same output voltage), the buffer capacitance also reduces. In other words, as the DC power of the load is decreasing, the power buffering requirement is reducing in the same proportion. If square-wave modulation is employed for the buffer, then the buffer capacitor voltage is fixed by the peak of VHF, thus the value of CB would be reduced so that it processes lower second line harmonic power. In other words, the system must have enough capacitance installed for the full load buffering condition, but as the load decreases the reduced buffering requirement is handled by directly removing energy storage capacitors. This is a highly efficient action.

[0139] In some embodiments, the buffer capacitor 500 may have variable capacitance. This variable capacitance may be implemented in a variety of ways, according to various embodiments. In some embodiments, a discrete number of switchable capacitor banks may be used. The capacitors are switched in as needed, and if they are sufficiently discrete then the mismatch associated with operating at a non-optimal capacitance (i.e., the capacitance that satisfies the CB equation, above) can be minimized. Note that these switching-bank switches can be low-cost, slow-switching devices, but they should be able to block the highest buffer voltage.

[0140] In other embodiments, the capacitors may use ferroelectric dielectrics with a temperature or DC voltage dependence. A biasing circuit can impose the requisite biasing conditions to modulate the capacitor. It should be noted that while this circuitry may induce loss, the loss is incurred specifically in conditions where less power must be buffered - thus, less loss is incurred in other parts of the circuit. This can help to keep efficiency high.

[0141] In still other embodiments, a different buffer inverter modulation scheme may be employed, which changes the voltage across the buffer capacitor 500 instead of changing the value of the buffer capacitor 500. Some of these embodiments may also be combined to maximize the capacitance variation capability.

[0142] Similarly, the PFC-correction inductor’s value is

[0143] In this case, Lo must increase with increasing load. This may be achieved using switchable inductors, or by inductors having electronically controlled inductance (e.g., by saturation control), according to various embodiments.

[0144] It should be noted that this variation capability is not needed over the full load range (e.g. 0-100% of load). According to various embodiments, other common low- power-processing modes, such as burst-mode operation, may be leveraged to accommodate very light loads.

[0145] Various embodiments of the contemplated HPPC 200 architecture offer significant flexibility for achieving gain variation. For example, the modulation of the BDS inverter 300 m(t) can be changed to reduce the amplitude of its fundamental. The well- established use of “zero states” can be included in the BDS inverter 300. The trade-off of this operation is a change in the ZVS operation of the BDS inverter 300, with a tendency to improve ZVS switching in one leg and worsen ZVS switching in the other leg. Such operating tradeoffs may be worthwhile depending on a specific design.

[0146] In some embodiments, an active switching stage can be employed which changes the relationship between Vo and the voltage on the direct branch element 210, v+. As a specific example, in one embodiment, a Coupled Electronic and Magnetic System may be employed. In other embodiments, a half-bridge, full-bridge, multi-level inverter, and the like may be employed.

[0147] Frequency-based gain control can also be leveraged in a manner similar to classical resonant converter architectures, according to various embodiments. Namely, as the frequency is changed from the resonant frequency associated with the high frequency LC filter, the fundamental voltage synthesized by the modulation network 202 is attenuated, reducing the voltage across the output resistor.

[0148] As previously discussed, one of the major benefits of the contemplated HPPC 200 architecture is that it greatly reduces the size of the bulky passive components usedin a traditional AC / DC converter (e.g., a 3x reduction in capacitive energy storage, and lOx reduction in inductive energy storage). It also imposes consistent current waveforms on them, enabling them to be highly optimized and enabling lower losses. A key trade-off is the use for BDS devices, and the higher currents these devices are required to carry in the main BDS inverter 300. However, it is expected that the net losses of the BDS inverter 300 devices can be similar to the boost PFC devices, and in this case the proposed architecture offers a dramatic improvement in power density without compromising loss.

[0149] If hard switching the BDS inverter 300 is not viable in a given design, then a two-branch architecture can be employed as this enables full ZVS across the full line cycle, according to various embodiments. Furthermore, the removal of the boost PFC inductors also reduces the loss of the converter, and may mitigate any possibility of increased losses in the BDS inverter 300 stage.

[0150] Different modulation schemes can be used for the BDS inverter 300 or the buffer inverter 502. For example, they can be controlled using sine wave modulation. This removes the need for a resonant filter at the switching frequency, at the expense of lowering the operating frequency of the architecture (i.e., the modulated sine wave has a frequency that is typically significantly lower than the switching frequency of the inverters). In a non-limiting example of the contemplated architecture making use of sine wave modulation (with radial frequency mSPWM), the output of the BDS inverter 300 modulation isM = ma

[0151] Where mgis the angular line frequency (e.g. 2TT50 or 2TT60 rad / s). In an embodiment employing a single-branch architecture with i+ flowing through the branch 206

[0152] Where, in a full wave rectifier 506 connected to an NP:Ns transformer 508 operating with a sinusoidal input current and a DC output voltage,

[0153] In this specific example, the buffer power processed by the orthogonal branch element 208 is

[0154] For the buffer to process the desired second-line-harmonic power 228, the buffer capacitor 500 needs to support the following voltage, according to various embodiments vcbuff=VA sin(< - 45°)

[0155] Resulting in an instantaneous power of

[0156] For this to equal the buffer power requirement, VA must be

[0157] The voltage inserted through the buffer inverter 502 depends on its sinusoidal modulation, which can be expressed as

[0159] This is close to the desired voltage to be inserted, V-, namely if^A^-a,buff Vgma

[0160] then Vbuff inserts V- and an additional undesired quadrature voltage component. Note that this relationship can be ensured in the buffer capacitor 500 by choosing its value to be

[0161] Thus

[0162] Which is expressed in terms of the load resistance as

[0163] The orthogonal inductor 504 Lo compensates for the part of Vbuir which is different from V-. Namely, if this inductor 504 carries i+, then its voltage drop is

[0164] Thus, in order for VL to insert

[0165] ThusReLj o — ~ _ _ _ .MsPWM ■+■ Mg

[0166] In terms of the load resistance

[0167] According to various embodiments, introducing sinusoidal PWM control over the BDS inverter 300 of the modulation network 202 and the buffer inverter 502 enables a degree of freedom for keeping CB constant with load

[0168] Now, as RL increases, ma, buff can be increased to compensate. As a specific example, for a 3.3x increase in RL, ma,butf can be increased by 1.7 times (e.g. from 0.57 to 1)such that CB is a constant. Note that the system still requires the orthogonal inductor 504 to be variable with load.

[0169] FIG. 6 is a schematic view of a non-limiting example of an HPPC 200 with a modulation network 202 and a single branch power electronic network 204 which both employ emulated BDS inverters 600. While waiting for monolithic bidirectional switches 302 to become commercially available, the bidirectional switch 302 can be implemented through an emulated bidirectional switch 602, which replaces the monolithic bidirectional switches 302 with devices that are more readily available - pairs of unidirectional transistors 604, like MOSFETs, HEMTs, and Gate Injection Transistors (GITs) (e g., GaN-based HEMTs, GaN- based GITs, etc.).

[0170] According to various embodiments, an emulated bidirectional switch 602 may be created using two unidirectional transistors 604, the pair being communicatively coupled in an anti-series "back-to-back" configuration. Each unidirectional transistor 604 has its source terminal connected to the other's source terminal. Alternatively, they may be implemented in a “drain-to-drain” series connection, where each transistor has its drain terminal connected to the other’s drain terminal.

[0171] This configuration ensures that when both unidirectional transistors 604 are off, the emulated bidirectional switch 602 can block voltage in either direction. When on, the unidirectional transistors 604 conduct current freely in either direction. An emulated BDS inverter 600 would be composed of four emulated bidirectional switches 602, as shown in the modulation network 202 and orthogonal branch element 208 of FIG. 6.

[0172] An emulated bidirectional switch 602 is at a disadvantage against a monolithic bidirectional switch 302, which is monolithically integrated on a single wafer, providing miniaturization and performance advantages. Emulated bidirectional switches 602, on the other hand, will be bigger, lossier, and slower, than "true" monolithically-integrated BDS devices. However, even emulated BDS switches provide advantages over conventional approaches owing to the salient benefits of the HPPC converter described herein. Specifically, an HPPC using emulated bidirectional switches 602 can outperform conventional AC / DC power converters in terms of efficiency and miniaturization, because they make greater reductions to the size of the buffer capacitor 500 possible and they also eliminate the need for a front-end PFC stage common in conventional single-phase power converters.

[0173] FIG. 7 is a schematic view of a non-limiting example of an HPPC 200 with a single branch power electronic network 204 and a modulation network 202 that does not use BDS devices, monolithic or otherwise. Of the three variants of the switching element withinthe modulation network 202 contemplated herein (i.e., monolithic BDS, emulated BDS, and non-BDS), the BDS-free device exhibits the worst performance, according to various embodiments.

[0174] The advantage of using BDS devices is that four high frequency devices are responsible for interfacing the line frequency AC to the high frequency DC / DC converter stage. However, it is also possible to leverage non-BDS devices on the inverter and still achieve the benefits of automatic unity power factor, the dual use of devices for DC / DC conversion, and the ability to use the smallest possible energy buffer. For example, the BDS inverter 300 can be replaced by a conventional diode bridge rectifier 700 communicatively coupled with a fullbridge inverter 322, as shown.

[0175] According to various embodiments, the non-limiting example of HPPC 200 architecture shown in FIG. 5 behaves identically to the previously described embodiments, with the change that m(t) must be inverted every half of a line cycle to ensure the same value of VHF is imposed. The key difference is that the main inverter no longer requires bi-directional voltage blocking capability in each switch. Similarly, the buffer inverter can be implemented in the same manner and mbuy(t) would be adjusted in a similar manner.

[0176] One of the benefits of the contemplated HPPC 200 architecture is the ability to automatically achieve unity power factor while using switching elements that actively participate in DC / DC conversion and while enabling an orthogonal branch element 208 that allows the minimum required second-line harmonic buffer power 228 to be processed. In net, these allow for a dramatic miniaturization of the bulky passive components in the converter 200.

[0177] In some embodiments, the BDS-based buffer inverter 502 may be replaced by a buffer inverter structure that imposes a “full-wave rectified sinusoidal” type voltage on the buffer capacitance having the same voltage magnitude. In such embodiments, the buffer capacitor 500 can still be sized for its minimum value to support the 2ndharmonic buffer power. Namely, if

[0178] The instantaneous power is the same as if thevcbuff =VA sin(m5t - 45°). That is:

[0179] Thus, a full wave rectified sinusoidal waveshape yields the same optimal capacitance. Note that this voltage can be described by its Fourier components as vCbuff=^(0-6366 — 0.4244 cos(2mpt) — 0.0849 cos(4mpt) — 0.0364 cos(6mpt) — 0.0202 cos(8mpt) + •••

[0180] An appropriate inverter modulation and structure can allow such a buffer voltage to still yield the correct inserted voltage, according to various embodiments. The tradeoff is a more complex inverter structure and / or modulation for the benefit of using non-BDS devices and a unipolar capacitor voltage.

[0181] As discussed above, even when implemented with less sophisticated devices, the contemplated HPPC 200 architecture offers advantages over conventional power converter designs. For example, in a specific embodiment, a single branch HPPC 200 was constructed and characterized according to the embodiment illustrated in Fig. 6.

[0182] Additionally, this particular non-limiting example uses wire-wound magnetics that are not integrated into the PCB. The buffer capacitor 500 being used is larger than needed, and the device itself is spread across multiple boards. This modularity allows flexibility while testing aspects like modulation strategies and multi-branch topologies but is not meant for achieving peak performance.

[0183] This specific embodiment is designed to modulate a fo = 60Hz grid frequency voltage at fHF=35OO-fo=21OkHz. This prototype was targeted at a common application for such a device - charging the battery of an electric vehicle, with a Vin of 120.2 RMS (i.e., a grid voltage) and Vout of 250 volts.

[0184] The operating waveforms from this experimental prototype are shown in Fig. 8. The converter is operated in open-loop and seen to automatically regulate the buffer capacitor voltage to be a 45.1° phase shifted version of the input voltage with VA=0.93 Vg=l 11.8Vrms, as expected from the analysis provided above. The input current demonstrates the inherent unity power factor regulation of this converter: current is perfectly in phase with the input voltage. Additional high frequency noise is seen on this current as the example experimental implementation does not include an input EMI filter. Recalling that the power factor at any port can be determined as the product of a distortion factor KD which indicates harmonic content in the current waveform and a displacement factor K<|> which indicates the relative phase shift between the voltage and current waveform, the distortionfactor associated with switching frequency harmonic currents would be mitigated by an EMI filter 320, but the displacement factor is what is regulated by a conventional PFC stage in the traditional AC / DC architecture of FIG. 1A.

[0185] The phase shift between the input voltage and current is observed to be 0.00568°, which results in a displacement factor of K<|>=cos(0.00568)=0.999. After EMI filtering this means a power factor of 0.999 is achievable. Thus, automatic unity power factor capability of the architecture is clearly demonstrated.

[0186] The output voltage is observed to have an average value of VO=246.4 and represents a 1.46% error to that predicted, where the small discrepancy is likely attributable to the active and passive losses as well as diode voltage drops not included in the simplified modeling presented here. The output voltage is observed to have a peak-to-average ripple ratio of R=15.6%. The single-branch HPPC 200 architecture is significantly more susceptible to errors introduced by passive component tolerances as a result of stricter filtering and cancellation requirements.

[0187] FIG. 9 shows an example power electronic network implementation of an HPPC having two branches and one DC port. It should be noted that the modulation network has been reduced to a block representation, but comprises the same functionality as the other embodiments discussed above. According to various embodiments, each direct branch element 210 is communicatively coupled to at least one DC port 214. In some embodiments, including the non-limiting example shown in FIG. 9, multiple direct branch elements 210 may be coupled to a shared DC port 214. FIG. 9 also shows the use of an orthogonal capacitor 900, the counterpart to the orthogonal inductor 504 in the other branch. Both ensure that the orthogonal branch element 208 they each belong to inserts the correct voltage into that branch 206, as discussed above.

[0188] According to various embodiments, a method for AC / DC power conversion through harmonic partitioning includes a modulation network 202 modulating a carrier signal 304 using an AC input signal 216 and an optional filter 303 to produce a modulation output 306 that is a composite signal 220 comprising a first voltage 310a and a second voltage 310b, with the first voltage 310a oscillating at a first frequency 314a, and the second voltage 310b oscillating at a second frequency 314b. A first current 312a oscillating at the first frequency 314a and a second current 312b oscillating at the second frequency 314b may flow through the modulation output. The method continues with partitioning the composite signal 220 using a power electronic network 204 comprising at least one branch 206 communicatively coupled in parallel to the modulation network 202. The power electronic network 204 is harmonicallypartitioned such that each branch 206 draws a current at one of the first frequency 314a or the second frequency 314b and inserts both the first voltage 310a and the second voltage 310b. The composite signal 220 is partitioned such that for each branch 206 of the at least one branch 206, the branch 206 has an orthogonal branch element 208 and a direct branch element 210 in series, with the orthogonal branch element 208 comprising at least one energy storage element 501. The branch 206 carries a current at the first frequency 314a or the second frequency 314b, the direct branch element 210 inserts the first voltage 310a or second voltage 310b whose frequency matches the branch current, and the orthogonal branch element 208 inserts the other voltage.

[0189] The method also includes achieving a unity displacement factor automatically by absorbing second-line harmonic power 228 with an orthogonal load 222, with the orthogonal load 222 belonging to the power electronic network 204 and being implemented by the orthogonal branch elements 208 of the at least one branch 206.

[0190] Finally, the method includes processing DC power with the direct load 224 to interface the at least one DC port 214, the direct load 224 also belonging to the power electronic network 204 and being implemented by the direct branch elements 210 of the at least one branch 206.

[0191] It will be understood that implementations are not limited to the specific components disclosed herein, as virtually any components consistent with the intended operation of a method and / or device implementation for a single-phase AC / DC power converter with harmonically partitioned power electronics may be utilized. Accordingly, for example, although particular HPPC architectures may be disclosed, such components may comprise any shape, size, style, type, model, version, class, grade, measurement, concentration, material, weight, quantity, and / or the like consistent with the intended operation of a method and / or device implementation for a single-phase AC / DC power converter with harmonically partitioned power electronics may be used. In places where the description above refers to particular implementations of a harmonically partitioned power converter, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations may be applied to other device architectures.

Claims

CLAIMSWhat is claimed is:

1. A harmonically partitioned power converter, comprising: a modulation network communicatively coupled to an AC port through which an AC signal is interfaced, the modulation network configured to modulate a carrier signal with the AC signal and synthesize a modulation signal that is a composite signal comprising a first voltage at a first frequency and a second voltage at a second frequency; a power electronic network communicatively coupled to the modulation network and having an orthogonal load and a direct load, the power electronic network comprising at least one branch communicatively coupled to the modulation network in parallel, each branch of the at least one branch comprising: an orthogonal branch element comprising an energy storage element, and a direct branch element communicatively coupled to at least one DC port and communicatively coupled to the orthogonal branch element in series; wherein the power electronic network is harmonically partitioned such that each branch draws a branch current at one of the first frequency and the second frequency and inserts both the first voltage and the second voltage; wherein, for each branch of the at least one branch: the direct branch element of the branch inserts one of the first voltage and the second voltage whose frequency is equal to the frequency of the branch current in that branch; and the orthogonal branch element of the branch inserts the other of the first voltage and the second voltage; wherein the orthogonal load is implemented by the orthogonal branch elements of the at least one branch, and absorbs second-line harmonic power such that the harmonically partitioned power converter automatically achieves unity displacement factor; wherein the direct load is communicatively coupled to the at least one DC port and processes DC power through the at least one DC port, the direct load being implemented by the direct branch elements of the at least one branch.

2. The harmonically partitioned power converter of claim 1, wherein the energy storage elements of the orthogonal load comprise buffer capacitors.

3. The harmonically partitioned power converter of claim 2, wherein an instantaneous power processed by the buffer capacitors is equal to the second-line harmonic power drawn from the AC port.

4. The harmonically partitioned power converter of claim 1, wherein the carrier signal has a carrier frequency that is at least two orders of magnitude greater than the frequency of the AC signal.

5. The harmonically partitioned power converter of claim 1, further comprising an EMI filter communicatively coupled to the AC port and the modulation network.

6. The harmonically partitioned power converter of claim 1, wherein the modulation network comprises a BDS inverter comprising four bidirectional switches.

7. The harmonically partitioned power converter of claim 6, wherein the bidirectional switches are monolithic.

8. The harmonically partitioned power converter of claim 1, wherein the modulation network comprises a diode bridge rectifier communicatively coupled with a full-bridge inverter.

9. The harmonically partitioned power converter of claim 1, wherein the modulation network comprises an emulated BDS inverter comprising four pairs of unidirectional transistors, each pair being communicatively coupled in an anti-series back-to-back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs.

10. The harmonically partitioned power converter of claim 1, wherein the modulation network comprises a BDS inverter comprising two bidirectional switches forming a halfbridge.

11. The harmonically partitioned power converter of claim 1, wherein the modulation network comprises a multi-level inverter.

12. The harmonically partitioned power converter of claim 1, wherein the power electronic network comprises two branches interfacing the modulation network to the at least one DC port.

13. The harmonically partitioned power converter of claim 1, wherein the power electronic network consists of one branch interfacing the modulation network to the at least one DC port.

14. The harmonically partitioned power converter of claim 1, wherein each orthogonal branch element comprises a buffer inverter coupled to the energy storage element.

15. The harmonically partitioned power converter of claim 14, wherein the buffer inverter comprises a BDS inverter comprising four bidirectional switches.

16. The harmonically partitioned power converter of claim 15, wherein the bidirectional switches are monolithic.

17. The harmonically partitioned power converter of claim 14, wherein the buffer inverter comprises a diode bridge rectifier communicatively coupled with a full-bridge inverter.

18. The harmonically partitioned power converter of claim 14, wherein the buffer inverter comprises an emulated BDS inverter comprising four pairs of unidirectional transistors, each pair being communicatively coupled in an anti-series back-to-back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs.

19. The harmonically partitioned power converter of claim 14, wherein the buffer inverter comprises a BDS inverter comprising two bidirectional switches forming a half-bridge.

20. The harmonically partitioned power converter of claim 14, wherein the buffer inverter comprises a multi-level inverter.

21. The harmonically partitioned power converter of claim 2, wherein each orthogonal branch element comprises a buffer inverter coupled to the buffer capacitor.

22. The harmonically partitioned power converter of claim 21, wherein the buffer capacitor has variable capacitance.

23. The harmonically partitioned power converter of claim 21, wherein, for each branch carrying a branch current, the orthogonal branch element further comprises one of an orthogonal inductor and an orthogonal capacitor selected such that when the one of an orthogonal inductor and an orthogonal capacitor carries the branch current at one of the first frequency and the second frequency, the orthogonal branch element inserts the voltage at the other of the first frequency and the second frequency.

24. The harmonically partitioned power converter of claim 23, wherein the orthogonal inductor has variable inductance.

25. The harmonically partitioned power converter of claim 23, wherein the orthogonal capacitor has variable capacitance.

26. The harmonically partitioned power converter of claim 1, wherein, for each branch, the direct branch element comprises a full wave rectifier communicatively coupled to at least one DC port.

27. The harmonically partitioned power converter of claim 26, wherein the full wave rectifier is a diode bridge rectifier.

28. The harmonically partitioned power converter of claim 26, wherein the full wave rectifier employs synchronous rectifiers.

29. The harmonically partitioned power converter of claim 1, wherein, for each branch, the direct branch element comprises a full bridge inverter communicatively coupled to the at least one DC port.

30. The harmonically partitioned power converter of claim 1, wherein, for each branch, the direct branch element comprises a multi-level inverter.

31. The harmonically partitioned power converter of claim 30, wherein, for each branch, the direct branch element comprises a transformer communicatively coupled to the multilevel inverter.

32. The harmonically partitioned power converter of claim 1, wherein, for each branch, the direct branch element comprises a half-bridge inverter.

33. The harmonically partitioned power converter of claim 32, wherein the direct branch element comprises a transformer communicatively coupled to the half-bridge inverter.

34. The harmonically partitioned power converter of claim 29, wherein, for each branch, the direct branch element further comprises a transformer communicatively coupled to the full bridge inverter.

35. The harmonically partitioned power converter of claim 26, wherein the direct branch element further comprises a transformer communicatively coupled to the full wave rectifier.

36. The harmonically partitioned power converter of claim 1, wherein the modulation network further comprises a series resonant filter comprising a resonant inductor in series with a resonant capacitor.

37. The harmonically partitioned power converter of claim 1, wherein at least one of the modulation network, orthogonal load, or direct load are controlled to enact variable voltage gain between the AC port and the DC port.

38. A method for AC / DC power conversion through harmonic partitioning, comprising: modulating a carrier signal with an AC signal interfaced through an AC port to synthesize a modulation signal that is a composite signal comprising a first voltage at a first frequency and a second voltage at a second frequency; partitioning the composite signal using a power electronic network comprising at least one branch communicatively coupled to the modulation network, the power electronic network being harmonically partitioned such that each branch draws a branch currentat one of the first frequency and the second frequency and inserts both the first voltage and the second voltage, the composite signal being partitioned such that, for each branch of the at least one branch: the branch comprises an orthogonal branch element and a direct branch element communicatively coupled to the orthogonal branch element in series, with the orthogonal branch element comprising an energy storage element; the branch draws current at one of the first frequency and the second frequency; the direct branch element of the branch inserts one of the first voltage and the second voltage whose frequency is equal to the frequency of the branch current in that branch; and the orthogonal branch element of the branch inserts the other of the first voltage and the second voltage; achieving a unity displacement factor at the AC port by absorbing second-line harmonic power with an orthogonal load, with the orthogonal load belonging to the power electronic network and being implemented by the orthogonal branch elements of the at least one branch; and processing DC power with the direct load to exchange power with at least one DC port, the direct load also belonging to the power electronic network and being implemented by the direct branch elements of the at least one branch.

39. The method of claim 38, wherein the energy storage elements of the orthogonal load are implemented by buffer capacitors.

40. The method of claim 39, wherein an instantaneous power processed by the buffer capacitors is equal to the second-line harmonic power drawn from the AC port.

41. The method of claim 38, wherein the carrier signal has a carrier frequency that is at least two orders of magnitude greater than the frequency of the AC signal.

42. The method of claim 38, wherein the modulating is performed using a BDS inverter comprising four bidirectional switches.

43. The method of claim 42, wherein the bidirectional switches are monolithic.

44. The method of claim 38, wherein the modulating is performed using a diode bridge rectifier communicatively coupled with a full-bridge inverter.

45. The method of claim 38, wherein the modulating is performed using an emulated BDS inverter comprising four pairs of unidirectional transistors, each pair being communicatively coupled in an anti-series back-to-back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs.

46. The method of claim 38, wherein the modulating is performed using a BDS inverter comprising two bidirectional switches forming a half-bridge.

47. The method of claim 38, wherein the modulating is performed using a multi-level inverter.

48. The method of claim 38, wherein the power electronic network comprises two branches.

49. The method of claim 38, wherein the power electronic network consists of one branch.

50. The method of claim 38, wherein each orthogonal branch element comprises a buffer inverter coupled to the energy storage element.

51. The method of claim 50, wherein the buffer inverter is a full-bridge inverter.

52. The method of claim 50, wherein the buffer inverter employs bidirectional switches.

53. The method of claim 52, wherein the bidirectional switches are monolithic.

54. The method of claim 50, wherein the buffer inverter comprises a diode bridge rectifier communicatively coupled with a full-bridge inverter.

55. The method of claim 50, wherein the buffer inverter comprises an emulated BDS inverter comprising four pairs of unidirectional transistors, each pair being communicatively coupled in an anti-series back-to-back configuration, the unidirectional transistors being one of MOSFETs, HEMTs, and GITs.

56. The method of claim 50, wherein the buffer inverter comprises a BDS inverter comprising two bidirectional switches forming a half-bridge.

57. The method of claim 50, wherein the buffer inverter comprises a multi-level inverter.

58. The method of claim 39, wherein each orthogonal branch element comprises a buffer inverter coupled to the buffer capacitor.

59. The method of claim 58, wherein the buffer capacitor has variable capacitance.

60. The method of claim 58, wherein, for each branch carrying a branch current, the orthogonal branch element further comprises one of an orthogonal inductor an orthogonal capacitor selected such that when the one of the orthogonal inductor and the orthogonal capacitor carries the branch current at one of the first frequency and the second frequency, the orthogonal branch element inserts the voltage at the other of the first frequency and the second frequency.

61. The method of claim 60, wherein the orthogonal inductor has variable inductance.

62. The method of claim 60, wherein the orthogonal capacitor has variable capacitance.

63. The method of claim 38, wherein each direct branch element comprises a transformer coupled with a full wave rectifier.

64. The method of claim 63, wherein the full wave rectifier is a diode bridge rectifier.

65. The method of claim 63, wherein the full wave rectifier employs synchronous rectifiers.

66. The method of claim 38, wherein each direct branch elements comprises a full bridge inverter communicatively coupled to the at least one DC port.

67. The method of claim 38, wherein the direct branch element comprises a multi-level inverter.

68. The method of claim 38, wherein the direct branch element comprises a half-bridge inverter.

69. The method of claim 67, wherein the direct branch element comprises a transformer communicatively coupled to the multi-level inverter.

70. The method of claim 68, wherein the direct branch element comprises a transformer communicatively coupled to the half-bridge inverter.

71. The method of claim 38, wherein at least one of the modulation network, orthogonal load, or direct load are controlled to enact variable voltage gain between the AC port and the DC port.

72. A harmonically partitioned power converter, comprising: a modulation network communicatively coupled to an AC port through which an AC signal is received, the modulation network comprising a BDS inverter configured to modulate a carrier signal using the AC signal and a high frequency filter to produce a modulation output that is a composite signal comprising a first voltage at a first frequency and a second voltage at a second frequency; a power electronic network communicatively coupled to the modulation network and having an orthogonal load and a direct load, the power electronic network comprising a branch communicatively coupled to the modulation network and comprising: an orthogonal branch element comprising a buffer inverter and a buffer capacitor sized to process instantaneous power equal to a second-line harmonic power drawn from the AC port, and a direct branch element comprising a full bridge switching network communicatively coupled to a DC port, the direct branch element communicatively coupled to the orthogonal branch element in series; wherein the power electronic network is harmonically partitioned such that the branch draws a branch current at one of the first frequency and the second frequency and inserts both the first voltage and the second voltage;wherein the direct branch element of the branch inserts one of the first voltage and the second voltage, whose frequency is equal to the frequency of the branch current in the branch; and wherein the orthogonal branch element of the branch inserts the other of the first voltage and the second voltage; wherein the orthogonal load is implemented by the orthogonal branch elements of the branch, and absorbs second-line harmonic power such that the harmonically partitioned power converter achieves unity displacement factor; wherein the direct load is communicatively coupled to the DC port and exchanges DC power with that port, the direct load being implemented by the direct branch elements of the branch; wherein the BDS inverter comprises four bidirectional switches that are monolithic.

73. The harmonically partitioned power converter of claim 72, wherein the carrier signal has a carrier frequency that is at least two orders of magnitude greater than an input frequency of the AC signal.

74. The harmonically partitioned power converter of claim 72, further comprising an EMI filter communicatively coupled to the AC port and the modulation network.

75. The harmonically partitioned power converter of claim 72, wherein the buffer inverter is a full-bridge inverter.

76. The harmonically partitioned power converter of claim 72, wherein the buffer inverter employs BDS devices.

77. The harmonically partitioned power converter of claim 72, wherein the buffer capacitor has variable capacitance.

78. The harmonically partitioned power converter of claim 72, wherein the orthogonal branch element further comprises one of an orthogonal inductor and an orthogonal capacitor selected such that when the one of the orthogonal inductor and the orthogonal capacitor carries the branch current at one of the first frequency and the secondfrequency, the orthogonal branch element inserts the voltage at the other of the first frequency and the second frequency.

79. The harmonically partitioned power converter of claim 78, wherein the orthogonal inductor has variable inductance.

80. The harmonically partitioned power converter of claim 78, wherein the orthogonal capacitor has variable capacitance.

81. The harmonically partitioned power converter of claim 72, wherein the direct branch element further comprises a transformer communicatively coupled with a full wave rectifier.

82. The harmonically partitioned power converter of claim 81, wherein the full wave rectifier is a diode bridge rectifier.

83. The harmonically partitioned power converter of claim 72, wherein the modulation network further comprises a series resonant filter comprising a resonant inductor in series with a resonant capacitor.

84. A harmonically partitioned power converter, comprising: a modulation network communicatively coupled to an AC port through which an AC signal having an input frequency is interfaced, the modulation network configured to modulate a carrier signal with the AC signal and synthesize a modulation signal that is a composite signal comprising 2N harmonic voltages forming A pairs, each pair comprising a first voltage at a first frequency and a second voltage at a second frequency, the first frequency and the second frequency of each pair being separated by twice the input frequency of the AC signal; a power electronic network communicatively coupled to the modulation network and having an orthogonal load and a direct load, the power electronic network comprising at least one branch communicatively coupled to the modulation network in parallel, each branch of the at least one branch comprising: an orthogonal branch element comprising an energy storage element, anda direct branch element communicatively coupled to at least one DC port and communicatively coupled to the orthogonal branch element in series; wherein the power electronic network is harmonically partitioned such that each branch draws a branch current at a frequency of one of the IN harmonic voltages produced by the modulation network and inserts a net voltage equal to the 2N harmonic voltages produced by the modulation network; wherein, for each branch of the at least one branch: the direct branch element of the branch inserts the harmonic voltage produced by the modulation network whose frequency is equal to the frequency of the branch current in that branch; and the orthogonal branch element of the branch inserts the harmonic voltages synthesized by the modulation network whose frequency is not equal to the frequency of the branch current in that branch; wherein the orthogonal load is implemented by the orthogonal branch elements of the at least one branch, and absorbs second-line harmonic power such that the harmonically partitioned power converter achieves unity displacement factor; wherein the direct load is communicatively coupled to the at least one DC port and processes DC power through these ports, the direct load being implemented by the direct branch elements of the at least one branch.

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