Display panel

Abstract

A display panel. A second connection end (132) of a first input signal line (13) is electrically connected to one of the binding terminals (12), and part of the first input signal line (13) is located in a fan-out routing area (103); a fourth connection end (142) of a second input signal line (14) is electrically connected to one of the binding terminals (12), and part of the second input signal line (14) is located in the fan-out routing area (103); and the voltage applied to the binding terminal (12) electrically connected to the first input signal line (13) is the same as the voltage applied to the binding terminal (12) electrically connected to the second input signal line (14).

Description

Display panel Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] In a display panel, the Gate Driver On Array (GOA) technology generates a scan signal through a GOA circuit and transmits the scan signal to the pixel drive circuit within the surface to enable the pixels within the surface to emit light.

[0003] Among them, the GOA circuit scans row by row to transmit scanning signals to the pixel driving circuit of the corresponding row; for example, multiple rows of GOA units in the GOA circuit all input high-potential signals through the high-potential scanning signal line. When the pixel driving circuit of this row adopts the high-potential signal for charging, and the pixel driving circuits of other rows also adopt the high-potential scanning signal for charging, the load of the high-potential scanning signal line will increase, and the potential in the high-potential scanning signal line will decrease, thereby affecting the signal stability in the pixel driving circuit, causing the display panel to have uneven display. SUMMARY OF THE INVENTION

[0004] The embodiments of the present application provide a display panel that can improve the transmission stability of signals in the first input signal line and the second input signal line, thereby improving the display uniformity of the display panel.

[0005] An embodiment of the present application provides a display panel, comprising a display area, a first driving circuit area located on a first side of the display area, and a fan-out wiring area located on a second side of the display area;

[0006] The display panel further includes:

[0007] The panel body includes a first gate driving circuit arranged in the first driving circuit area, at least one binding terminal arranged on a side of the fan-out wiring area away from the display area, a first input signal line, and a second input signal line;

[0008] The first input signal line includes a first connection end and a second connection end opposite to each other, the first connection end is electrically connected to the first gate driving circuit, and the second connection end is electrically connected to one of the binding terminals, and a portion of the first input signal line is located in the fan-out routing area;

[0009] The second input signal line includes a third connection end and a fourth connection end opposite to each other, the third connection end is electrically connected to the first gate driving circuit, and the fourth connection end is electrically connected to one of the binding terminals, and a portion of the second input signal line is located in the fan-out routing area;

[0010] The voltage loaded on the binding terminal electrically connected to the first input signal line is the same as the voltage loaded on the binding terminal electrically connected to the second input signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic diagram of a distribution of display panels provided by related art;

[0012] FIG2 is a waveform diagram of an output voltage signal of a gate drive circuit provided by the related art;

[0013] FIG3 is a brightness curve diagram of different rows of a display panel provided by the related art;

[0014] FIG4 is a schematic diagram of a planar distribution of a display panel provided in an embodiment of the present application;

[0015] FIG5 is a schematic diagram of a circuit connection of a display panel provided in an embodiment of the present application;

[0016] FIG6 is a schematic diagram of the structure of a first signal input line and a second signal input line provided in an embodiment of the present application;

[0017] FIG7 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0018] 8 and 9 are schematic structural diagrams of a first gate control circuit provided in an embodiment of the present application;

[0019] 10 and 11 are waveform diagrams of output signals of a first gate control circuit provided in an embodiment of the present application;

[0020] FIG12 is another circuit connection diagram of a display panel provided in an embodiment of the present application;

[0021] FIG13 is another schematic diagram of the structure of the first signal input line and the second signal input line provided in an embodiment of the present application;

[0022] FIG14 is another circuit connection diagram of a display panel provided in an embodiment of the present application;

[0023] FIG15 is another schematic diagram of the structure of the first signal input line and the second signal input line provided in an embodiment of the present application;

[0024] FIG16 is another circuit connection diagram of a display panel provided in an embodiment of the present application;

[0025] FIG17 is another schematic diagram of the structure of the first signal input line and the second signal input line provided in an embodiment of the present application;

[0026] FIG18 is another circuit connection diagram of a display panel provided in an embodiment of the present application;

[0027] FIG19 is another schematic diagram of the structure of the first signal input line and the second signal input line provided in an embodiment of the present application;

[0028] FIG20 is another circuit connection diagram of a display panel provided in an embodiment of the present application;

[0029] FIG21 is another structural schematic diagram of the first signal input line and the second signal input line provided in an embodiment of the present application. Modes for Carrying Out the Invention

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0031] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0032] Please refer to Figures 1, 2 and 3. In the related art, the display panel includes multiple row gate control circuits, for example, it may include a first row gate control circuit 1, a second row gate control circuit 2, a third row gate control circuit 3 and a fourth row gate control circuit 4. The signal input terminal 5 transmits the scanning signal to the multiple row gate control circuits through the transmission signal line 6, and the row gate control circuit transmits the voltage to the pixel circuit 8 in the display area through the output signal line 7; wherein the first row gate control circuit 1 and the third row gate control circuit 3 are directly connected and connected to the transmission signal line 6, and the second row gate control circuit 2 and the fourth row gate control circuit 4 are directly connected and connected to the transmission signal line 6; during the driving process of the display panel, the multiple gate control circuits perform row-by-row scanning. When the second row gate control circuit 2 and the fourth row gate control circuit 4 charge the pixel circuit 8, the load of the transmission signal line 6 will increase, thereby The voltage in the transmission signal line 6 decreases, causing the voltage transmitted to the first-row gate control circuit 1 to decrease, resulting in a sharp corner A as shown in Figure 2. When the third-row gate control circuit 3 charges the pixel circuit 8, the load on the transmission signal line 6 will increase, and the voltage in the transmission signal line 6 will decrease, causing the voltage transmitted to the first-row gate control circuit 1 to decrease, resulting in a sharp corner B as shown in Figure 2. Since the third-row gate control circuit 3 is directly connected to the first-row gate control circuit 1, the third-row gate control circuit 3 has a greater impact on the voltage in the first-row gate control circuit 1 when charging. Therefore, the degree of decrease in sharp corner B is greater than the degree of decrease in sharp corner A. Since the potentials in other row gate control circuits will also be affected by the first-row gate control circuit 1 as described above, the brightness of different rows in the display panel will fluctuate as shown in Figure 3, resulting in the display panel showing fine horizontal stripes and uneven display.

[0033] In conjunction with Figures 4 and 5, an embodiment of the present application provides a display panel, which includes a display area 101, a first driving circuit area 1021 located on a first side of the display area 101, and a fan-out wiring area 103 located on a second side of the display area 101; the display panel also includes a panel body 10; wherein the panel body 10 includes a first gate driving circuit 11 arranged in the first driving circuit area 1021, at least one binding terminal 12 arranged on a side of the fan-out wiring area 103 away from the display area 101, a first input signal line 13, and a second input signal line 14.

[0034] The first input signal line 13 includes a first connection end 131 and a second connection end 132 opposite to each other. The first connection end 131 is electrically connected to the first gate driving circuit 11 , and the second connection end 132 is electrically connected to one of the binding terminals 12 . Part of the first input signal line 13 is located in the fan-out routing area 103 .

[0035] The second input signal line 14 includes a third connection end 141 and a fourth connection end 142 opposite to each other. The third connection end 141 is electrically connected to the first gate driving circuit 11 , and the fourth connection end 142 is electrically connected to one of the binding terminals 12 . Part of the second input signal line 14 is located in the fan-out routing area 103 .

[0036] Furthermore, the voltage applied to the binding terminal 12 electrically connected to the first input signal line 13 is the same as the voltage applied to the binding terminal 12 electrically connected to the second input signal line 14 .

[0037] During the implementation process, the embodiment of the present application sets the connection point of the first input signal line 13 and the second input signal line 14 in the fan-out routing area 103 or on the side farther away from the first gate drive circuit 11, thereby making the connection point between the first input signal line 13 and the first gate drive circuit 11 and the connection point between the second input signal line 14 and the first gate drive circuit 11 farther, reducing the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14, and can improve the transmission stability of the signals in the first input signal line 13 and the second input signal line 14, thereby improving the display uniformity of the display panel.

[0038] In an embodiment of the present application, the first input signal line and the second input signal line are electrically connected to the same binding terminal.

[0039] In one embodiment of the present application, the panel body further includes a transfer signal line, one end of the transfer signal line is connected to the binding terminal, and the other end of the transfer signal line is connected to the second connection end and the fourth connection end.

[0040] In an embodiment of the present application, the second connection end and the fourth connection end are both located in the fan-out wiring area.

[0041] In one embodiment of the present application, the display panel further includes a bending area arranged on a side of the fan-out wiring area away from the display area, and the second connection end, the fourth connection end and part of the transfer signal line are all located in the bending area.

[0042] In one embodiment of the present application, the display panel also includes a bending area arranged on the side of the fan-out wiring area away from the display area, and the second connection end, the fourth connection end and the transfer signal line are all located on the side of the bending area away from the fan-out wiring area.

[0043] In an embodiment of the present application, the transfer signal line extends along a first direction, and the first direction is a direction in which the bending area approaches the fan-out routing area.

[0044] In one embodiment of the present application, the first input signal line extends in a direction deviated from the first direction in the fan-out routing area, the first input signal line extends in the first direction in the bending area, and the first input signal line extends in a direction deviated from the first direction between the bending area and the transfer signal line;

[0045] The second input signal line extends in a direction oblique to the first direction in the fan-out routing area, the second input signal line extends in the first direction in the bending area, and the second input signal line extends in a direction oblique to the first direction between the bending area and the transfer signal line.

[0046] In one embodiment of the present application, the panel body includes a source / drain layer and a gate layer;

[0047] The source-drain electrode layer includes the transfer signal line, and the length of the transfer signal line along the first direction is greater than or equal to 100 microns;

[0048] Alternatively, the gate layer includes the transfer signal line, and the length of the transfer signal line along the first direction is greater than or equal to 20 micrometers.

[0049] In one embodiment of the present application, the first input signal line includes multiple first line segments, and the multiple first line segments are each independently located in the source and drain layer or the gate layer, and the second input signal line includes multiple second line segments, and the multiple second line segments are each independently located in the source and drain layer or the gate layer.

[0050] In one embodiment of the present application, the binding terminal electrically connected to the first input signal line and the binding terminal electrically connected to the second input signal line are different binding terminals.

[0051] In one embodiment of the present application, the panel body includes a plurality of pixel driving circuits disposed in the display area and arranged along a second direction and a third direction, the second direction intersecting the third direction, and the first gate driving circuit includes a plurality of first gate control circuits disposed in the first driving circuit area and arranged along the third direction;

[0052] The panel body also includes multiple first output signal lines, one end of each first output signal line is connected to a first gate control circuit, and the other end of each first output signal line is connected to a plurality of pixel driving circuits arranged along the second direction, and the first output signal line is used to transmit the voltage signals in the first input signal line and the second input signal line to the pixel driving circuit.

[0053] In one embodiment of the present application, the first input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, the second input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, and the plurality of the first gate control circuits connected to the first input signal line and the plurality of the first gate control circuits connected to the second input signal line are alternately arranged along the third direction.

[0054] In one embodiment of the present application, the first gate driving circuit further includes a plurality of second gate control circuits disposed in the first driving circuit area and arranged along the third direction, the panel body further includes a plurality of second output signal lines, and the plurality of second gate control circuits are located on a side of the plurality of first gate control circuits that is away from or close to the display area;

[0055] One end of a second output signal line is connected to a second gate control circuit, and the other end of a second output signal line is connected to a plurality of the pixel driving circuits arranged along the second direction.

[0056] In one embodiment of the present application, the panel body further includes a first sub-line and a second sub-line connected to the first connection end, the first sub-line being connected to a plurality of the first gate control circuits arranged along the third direction, the second sub-line being connected to a plurality of the first gate control circuits arranged along the third direction, and the plurality of the first gate control circuits connected to the first sub-line and the plurality of the first gate control circuits connected to the second sub-line being alternately arranged along the third direction;

[0057] The panel body also includes a third sub-line and a fourth sub-line connected to the third connection end, the third sub-line is connected to a plurality of second gate control circuits arranged along the third direction, the fourth sub-line is connected to a plurality of second gate control circuits arranged along the third direction, and the plurality of second gate control circuits connected to the third sub-line and the plurality of second gate control circuits connected to the fourth sub-line are alternately arranged along the third direction.

[0058] In one embodiment of the present application, the first input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, the second input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, and the plurality of the first gate control circuits connected to the first input signal line and the plurality of the first gate control circuits connected to the second input signal line are alternately arranged along the third direction;

[0059] The panel body also includes a third input signal line, the fifth connection end of the third input signal line is electrically connected to the second gate control circuit, the sixth connection end of the third input signal line passes through at least a portion of the fan-out routing area and is electrically connected to one of the binding terminals, and the voltage loaded on the binding terminal electrically connected to the first input signal line is the same as the voltage loaded on the binding terminal electrically connected to the third input signal line.

[0060] In one embodiment of the present application, the panel body further includes a fourth input signal line, a seventh connection end of the fourth input signal line is electrically connected to the second gate control circuit, an eighth connection end of the fourth input signal line passes through at least a portion of the fan-out routing area and is electrically connected to one of the binding terminals, and a voltage applied to the binding terminal electrically connected to the first input signal line is the same as a voltage applied to the binding terminal electrically connected to the fourth input signal line;

[0061] The third input signal line is connected to a plurality of second gate control circuits arranged along the third direction, the fourth input signal line is connected to a plurality of second gate control circuits arranged along the third direction, and the plurality of second gate control circuits connected to the third input signal line and the plurality of second gate control circuits connected to the fourth input signal line are alternately arranged along the third direction.

[0062] In one embodiment of the present application, the panel body also includes a fifth sub-line and a sixth sub-line connected to the fifth connection end, the fifth sub-line is connected to a plurality of second gate control circuits arranged along the third direction, the sixth sub-line is connected to a plurality of second gate control circuits arranged along the third direction, and the plurality of second gate control circuits connected to the fifth sub-line and the plurality of second gate control circuits connected to the sixth sub-line are alternately arranged along the third direction.

[0063] In one embodiment of the present application, the pixel driving circuit includes a driving transistor and a compensation transistor, the first electrode of the driving transistor and the first electrode of the compensation transistor are both connected to a first node, the gate of the driving transistor and the second electrode of the compensation transistor are both connected to a second node, and the first output signal line is connected to the gate of the compensation transistor.

[0064] In one embodiment of the present application, the compensation transistor is an N-type thin film transistor, and the voltage loaded on the binding terminal electrically connected to the first input signal line and the voltage loaded on the binding terminal electrically connected to the second input signal line are both high levels.

[0065] Specifically, please continue to combine Figures 4 and 5. The display panel provided in the embodiment of the present application includes a display area 101 and a non-display area adjacent to the display area 101, and the non-display area includes a first driving circuit area 1021 located on the first side of the display area 101, a fan-out routing area 103 located on the second side of the display area 101, and a second driving circuit area 1022 located on the third side of the display area 101; wherein the first side and the third side are opposite sides of the display area 101, and the second side is located between the first side and the third side.

[0066] The display panel also includes a panel body 10, a flexible circuit board 20 and a circuit board 30, and one end of the flexible circuit board 20 is connected to a side of the panel body 10 away from the fan-out wiring area 103, and the other end of the flexible circuit board 20 is connected to the circuit board 30; wherein, the circuit board 30 transmits signals to the panel body 10 through the flexible circuit board 20 to realize the display function of the display panel.

[0067] In one embodiment, a driving chip 31 is disposed on the circuit board 30 to provide display signals to the panel body 10 .

[0068] Furthermore, the panel body 10 includes a first gate driving circuit 11 arranged in the first driving circuit area 1021, a second gate driving circuit 15 arranged in the second driving circuit area 1022, and a plurality of pixel driving circuits 16 arranged in the display area 101, and the plurality of pixel driving circuits 16 are arranged in an array along the second direction M and the third direction N, wherein the second direction M and the third direction N intersect.

[0069] In one embodiment, the second direction M is perpendicular to the third direction N, and the third direction N is the direction in which the fan-out wiring area 103 approaches the display area 101; it can be understood that in other embodiments of the present application, the third direction N can also be other directions, which is not limited here.

[0070] A first gate driving circuit 11 and a second gate driving circuit 15 jointly drive a plurality of pixel driving circuits 16 arranged along the second direction M.

[0071] The panel body 10 also includes at least one binding terminal 12 arranged on the side of the fan-out wiring area 103 away from the display area 101, and the flexible circuit board 20 is bound and connected to the binding terminal 12. Then, the circuit board 30 can transmit signals to the first gate driving circuit 11 and the second gate driving circuit 15 through the flexible circuit board 20 to perform row-by-row scanning on multiple pixel driving circuits 16.

[0072] It should be noted that in the embodiment of the present application, the first gate drive circuit 11 and the second gate drive circuit 15 are symmetrically arranged relative to the display area 101, and the connection and signal transmission between the first gate drive circuit 11 and the flexible circuit board 20 and the circuit board 30 are the same as the connection and signal transmission between the second gate drive circuit 15 and the flexible circuit board 20 and the circuit board 30. Therefore, in the embodiment of the present application, the connection and signal transmission between the first gate drive circuit 11 and the flexible circuit board 20 and the circuit board 30 are described as an example, and the connection structure between the second gate drive circuit 15 and the flexible circuit board 20 and the circuit board 30 can be changed symmetrically relative to the display area 101, and the signal transmission is the same.

[0073] The panel body 10 includes a first input signal line 13 and a second input signal line 14. The first input signal line 13 includes a first connection end 131 and a second connection end 132 relative to each other. The first connection end 131 is electrically connected to the first gate driver circuit 11, and the second connection end 132 passes through at least a portion of the fan-out wiring area 103 and is electrically connected to a binding terminal 12; the second input signal line 14 includes a third connection end 141 and a fourth connection end 142 relative to each other. The third connection end 141 is electrically connected to the first gate driver circuit 11, and the fourth connection end 142 passes through at least a portion of the fan-out wiring area 103 and is electrically connected to a binding terminal 12.

[0074] Furthermore, the voltage applied to the binding terminal 12 electrically connected to the first input signal line 13 is the same as the voltage applied to the binding terminal 12 electrically connected to the second input signal line 14. In the embodiment of the present application, the connection point between the first input signal line 13 and the second input signal line 14 is arranged in the fan-out routing area 103 or on a side further away from the first gate driver circuit 11, thereby making the connection point between the first input signal line 13 and the first gate driver circuit 11 and the connection point between the second input signal line 14 and the first gate driver circuit 11 farther apart, thereby reducing the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14, thereby improving the transmission stability of the signals in the first input signal line 13 and the second input signal line 14, and improving the display uniformity of the display panel.

[0075] In one embodiment, the first input signal line 13 and the second input signal line 14 are electrically connected to the same binding terminal 12, and the panel body 10 also includes a transfer signal line 19, one end of the transfer signal line 19 is connected to the binding terminal 12, and the other end of the transfer signal line 19 is connected to the second connection end 132 and the fourth connection end 142.

[0076] Furthermore, the display panel further includes a bending region 104 disposed on a side of the fan-out wiring region 103 away from the display region 101 .

[0077] In one embodiment, the second connection end 132 , the fourth connection end 142 and part of the transfer signal line 19 are all located in the fan-out routing area 103 , and the transfer signal line 19 is connected to the second connection end 132 and the fourth connection end 142 in the fan-out routing area 103 .

[0078] In one embodiment, the display panel also includes a bending area 104 arranged on the side of the fan-out routing area 103 away from the display area 101, the second connection end 132, the fourth connection end 142 and part of the transfer signal line 19 are all located in the bending area 104, and the transfer signal line 19 is connected to the second connection end 132 and the fourth connection end 142 in the bending area 104.

[0079] In one embodiment, the second connection end 132, the fourth connection end 142 and the transfer signal line 19 are all located on the side of the bending area 104 away from the fan-out routing area 103, and the transfer signal line 19 is connected to the second connection end 132 and the fourth connection end 142 on the side of the bending area 104 away from the fan-out routing area 103.

[0080] In addition, in other embodiments of the present application, the first input signal line 13 and the second input signal line 14 may also be connected to different binding terminals 12 .

[0081] Among them, the farther the connection point between the first input signal line 13 and the second input signal line 14 is set from the first gate drive circuit 11, the smaller the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14. Therefore, in the embodiment of the present application, the embodiment in which the transfer signal line 19 is connected to the second connection end 132 and the fourth connection end 142 on the side of the bending area 104 away from the fan-out routing area 103 is described as an example.

[0082] The connection method of the first input signal line 13 and the second input signal line 14 in the embodiment of the present application will be described in detail below with reference to specific embodiments.

[0083] In one embodiment of the present application, please continue to refer to FIG. 4 , FIG. 5 and FIG. 6 . In the embodiment of the present application, the first input signal line 13 and the second input signal line 14 are connected to the same binding terminal 12 .

[0084] Among them, the first gate driving circuit 11 includes multiple first gate control circuits 111 arranged along the third direction N, the second gate driving circuit 15 includes multiple third gate control circuits 151 arranged along the third direction N, and one first gate control circuit 111 and one third gate control circuit 151 jointly transmit signals to multiple pixel driving circuits 16 arranged along the first direction X; it should be noted that since the connection method between the first gate control circuit 111 and the binding terminal 12 is the same as the connection method between the third gate control circuit 151 and the binding terminal 12, and are symmetrically arranged relative to the display area 101, in the embodiment of the present application, only the connection method between the first gate control circuit 111 and the binding terminal 12 is described for illustration.

[0085] In one embodiment, the panel body 10 further includes a plurality of first output signal lines 113, one end of a first output signal line 113 is connected to a first gate control circuit 111, and the other end of a first output signal line 113 is connected to a plurality of pixel driving circuits 16 arranged along a second direction M. The first output signal line 113 is used to transmit the voltage signals in the first input signal line 13 and the second input signal line 14 to the pixel driving circuit 16.

[0086] In the embodiment of the present application, the driving chip 31 on the circuit board 30 transmits the signal to the flexible circuit board 20, and the flexible circuit board 20 transmits the signal to the first input signal line 13 and the second input signal line 14 through the binding terminal 12 of the binding connection. The first input signal line 13 and the second input signal line 14 transmit the signal to the first gate control circuit 111, and then transmit the signal to the pixel driving circuit 16 through the first output signal line 113 to scan and drive each pixel driving circuit 16.

[0087] In one embodiment, as shown in FIG7 , the pixel driving circuit 16 includes a light-emitting device, a driving transistor T01, a switching transistor T02, a compensation transistor T03, a first reset transistor T04, a first light-emitting control transistor T05, a second light-emitting control transistor T06, a second reset transistor T07, a third reset transistor T08, a first capacitor Cst, and a second capacitor Cboost.

[0088] A first electrode of the driving transistor T01 is connected to the first node B, a gate of the driving transistor T01 is connected to the second node Q, and a second electrode of the driving transistor T01 is connected to the third node A.

[0089] A first electrode of the first switch transistor T02 is connected to the data signal Data, a gate of the first switch transistor T02 is connected to the first scan signal Pscan, and a second electrode of the first switch transistor T02 is connected to the third node A.

[0090] A first electrode of the compensation transistor T03 is connected to the first node B, a gate of the compensation transistor T03 is connected to the second scan signal NscanT3, and a second electrode of the compensation transistor T03 is connected to the second node Q.

[0091] A first electrode of the first reset transistor T04 is connected to the first reset signal Vi_G, a gate of the first reset transistor T04 is connected to the third scan signal NscanT4, and a second electrode of the first reset transistor T04 is connected to the second node Q.

[0092] A first electrode of the first light emitting control transistor T05 is connected to the first power supply signal VDD, a gate of the first light emitting control transistor T05 is connected to the light emitting control signal EM, and a second electrode of the first light emitting control transistor T05 is connected to the third node A.

[0093] A first electrode of the second light emitting control transistor T06 is connected to the first node B, a gate of the second light emitting control transistor T06 is connected to the light emitting control signal EM, and a second electrode of the second light emitting control transistor T06 is connected to the fourth node C.

[0094] A first electrode of the second reset transistor T07 is connected to the second reset signal Vi_ANo, a gate of the second reset transistor T07 is connected to the fourth scan signal PScan2, and a second electrode of the second reset transistor T07 is connected to the fourth node C.

[0095] A first electrode of the third reset transistor T08 is connected to the third reset signal Vi_T8 , a gate of the third reset transistor T08 is connected to the fourth scan signal PScan2 , and a second electrode of the third reset transistor T08 is connected to the third node A.

[0096] A first electrode of the light emitting device is connected to the fourth node C, and a second electrode of the light emitting device is connected to the second power signal VSS.

[0097] The first capacitor Cst is connected between the second node Q and the third node A, and the second capacitor Cboost is connected between the second node Q and the first scan signal PScan.

[0098] Further, please combine Figures 5 and 7. In the embodiment of the present application, the first output signal line 113 is connected to the gate of the compensation transistor T03, that is, the output signal of the first output signal line 113 is the second scanning signal NscanT3; in one embodiment, the compensation transistor T03 is an N-type thin film transistor, then the voltage loaded on the binding terminal 12 electrically connected to the first input signal line 13 and the voltage loaded on the binding terminal 12 electrically connected to the second input signal line 14 are both high levels.

[0099] It can be understood that the compensation transistor T03 is connected to the first electrode and the gate of the driving transistor T01. Therefore, if the signal transmitted in the first input signal line 13 and the second input signal line 14 is unstable, the voltage loaded on the gate of the compensation transistor T03 will also be unstable. Since there is a parasitic capacitance between the gate of the compensation transistor T03 and the gate of the driving transistor T01, the voltage fluctuation on the gate of the compensation transistor T03 will cause the gate of the driving transistor T01 to fluctuate, thereby affecting the stability of the signal transmission in the driving transistor T01, making the electrical signal transmitted to the light-emitting device unstable, resulting in the display unevenness of fine horizontal stripes on the display panel.

[0100] Further, as shown in Figure 8, the first gate control circuit 111 provided in the present application includes a signal control unit 41 and a signal generating unit 42, wherein the signal generating unit 42 can be connected to the high-level signal NVGH_T3 and the low-level signal NVGL_T3, and output the high-level signal NVGH_T3 to the signal output terminal NscanT3_out under the control of the high-level transistor TH, or output the high-level signal NVGL_T3 to the signal output terminal NscanT3_out under the control of the low-level transistor TL, and the signal output terminal NscanT3_out can be connected to the gate of the compensation transistor T03 through the first output signal line 113; and the signal control unit 41 is connected to the gate of the high-level transistor TH and the gate of the low-level transistor TL to turn on the high-level transistor TH or the low-level transistor TL according to the control of multiple clock signals.

[0101] In one embodiment, as shown in Figure 9, an embodiment of the present application provides a first gate control circuit 111 of a 16T3C architecture, wherein the first gate control circuit 111 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0102] The first electrode of the first transistor T1 is connected to the low-level signal VGL, the gate of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the signal output terminal OUT.

[0103] A first electrode of the second transistor T2 is connected to the high level signal VGH, a gate of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the signal output terminal OUT.

[0104] A first electrode of the third transistor T3 is connected to the first node N1 , a gate of the third transistor T3 is connected to the low-level signal VGL, and a second electrode of the third transistor T3 is connected to the third node N3 .

[0105] A first electrode of the fourth transistor T4 is connected to the first node N1 , a gate of the fourth transistor T4 is connected to the first capacitor C1 , and a second electrode of the fourth transistor T4 is connected to the fourth node N4 .

[0106] A first electrode of the fifth transistor T5 is connected to the fourth node N4 , a gate of the fifth transistor T5 is connected to the low-level signal VGL, and a second electrode of the fifth transistor T5 is connected to the fifth node N5 .

[0107] A first electrode of the sixth transistor T6 is connected to the control signal IN, a gate of the sixth transistor T6 is connected to the first clock signal CK, and a second electrode of the sixth transistor T6 is connected to the fifth node N5.

[0108] A first electrode of the seventh transistor T7 is connected to the control signal IN, a gate of the seventh transistor T7 is connected to the first clock signal CK, and a second electrode of the seventh transistor T7 is connected to the third node N3.

[0109] A first electrode of the eighth transistor T8 is connected to the low-level signal VGL, a gate of the eighth transistor T8 is connected to the first clock signal CK, and a second electrode of the eighth transistor T8 is connected to the sixth node N6.

[0110] A first electrode of the ninth transistor T9 is connected to the second clock signal XCK, a gate of the ninth transistor T9 is connected to the fourth node N4, and a second electrode of the ninth transistor T9 is connected to the seventh node N7.

[0111] A first electrode of the tenth transistor T10 is connected to the first clock signal CK, a gate of the tenth transistor T10 is connected to the third node N3, and a second electrode of the tenth transistor T10 is connected to the sixth node N6; and the tenth transistor T10 may be a dual-gate transistor.

[0112] A first electrode of the eleventh transistor T11 is connected to the high-level signal VGH, a gate of the eleventh transistor T11 is connected to the sixth node N6, and a second electrode of the eleventh transistor T11 is connected to the seventh node N7.

[0113] A first electrode of the twelfth transistor T12 is connected to the high level signal VGH, a gate of the twelfth transistor T12 is connected to the third node N3, and a second electrode of the twelfth transistor T12 is connected to the second node N2.

[0114] A first electrode of the thirteenth transistor T13 is connected to the high level signal VGH, a gate of the thirteenth transistor T13 is connected to the control signal RST, and a second electrode of the thirteenth transistor T13 is connected to the third node N3.

[0115] A first electrode of the fourteenth transistor T14 is connected to the sixth node N6 , a gate of the fourteenth transistor T14 is connected to the low-level signal VGL, and a second electrode of the fourteenth transistor T14 is connected to the eighth node N8 .

[0116] A first electrode of the fifteenth transistor T15 is connected to the ninth node N9 , a gate of the fifteenth transistor T15 is connected to the second clock signal XCK, and a second electrode of the fifteenth transistor T15 is connected to the second node N2 .

[0117] A first electrode of the sixteenth transistor T16 is connected to the second clock signal XCK, a gate of the sixteenth transistor T16 is connected to the eighth node N8, and a second electrode of the sixteenth transistor T16 is connected to the ninth node N9.

[0118] The first capacitor C1 is connected between the gate of the fourth transistor T4 and the seventh node N7, the second capacitor C2 is connected between the high level signal VGH and the second node N2, and the third capacitor C3 is connected between the eighth node N8 and the ninth node N9.

[0119] Continuing from the above, under the control of the second node N2, the second transistor T2 transmits the high-level signal transmitted in the first input signal line 13 or the first output signal line 13 to the signal output terminal OUT, and then transmits it to the gate of the compensation transistor T03 in the pixel driving circuit 16 through the first output signal line 113.

[0120] Furthermore, the first connection end 131 of the first input signal line 13 is connected to a plurality of first gate control circuits 111 arranged along a third direction N, the third connection end 141 of the second input signal line 14 is connected to a plurality of first gate control circuits 111 arranged along a third direction N, and the plurality of first gate control circuits 111 connected to the first input signal line 13 and the plurality of first gate control circuits 111 connected to the second input signal line 14 are alternately arranged along the third direction N.

[0121] It can be understood that the first gate control circuit 111 connected to the first input signal line 13 and the first gate control circuit 111 connected to the second input signal line 14 are different first gate control circuits 111 .

[0122] Furthermore, the second connection end 132 of the first input signal line 13 and the fourth connection end 142 of the second input signal line 14 are connected to the transfer signal line 19 , and the transfer signal line 19 is connected to the second connection end 132 and the fourth connection end 142 on the side of the bending area 104 away from the fan-out routing area 103 .

[0123] In one embodiment, the transfer signal line 19 extends along a first direction X, and the first direction X can be the direction in which the bending area 104 approaches the fan-out wiring area 103; it should be noted that when the third direction N is the direction in which the fan-out wiring area 103 approaches the display area 101, the first direction X is parallel to the third direction N.

[0124] Among them, the first input signal line 13 extends in a direction oblique to the first direction X in the fan-out routing area 103, the first input signal line 13 extends in the first direction X in the bending area 104, and the first input signal line 13 extends in a direction oblique to the first direction X between the bending area 104 and the transfer signal line 19.

[0125] The second input signal line 14 extends in a direction oblique to the first direction X in the fan-out routing area 103 , extends in the first direction X in the bending area 104 , and extends in a direction oblique to the first direction X between the bending area 104 and the transfer signal line 19 .

[0126] It should be noted that, since the portion of the display panel located in the bending area 104 needs to be bent, the portion of the display panel located in the bending area 104 away from the fan-out wiring area 103 is bent to the back side, so that the flexible circuit board 20 and the circuit board 30 can be located on the back side of the display panel to reduce the border width of the display panel close to the fan-out wiring area 103. Therefore, in the embodiment of the present application, the first input signal line 13 and the second input signal line 14 are extended along the first direction X in the bending area 104, which can reduce the bending stress exerted on the first input signal line 13 and the second input signal line 14. In addition, the binding terminal 12 and the first gate drive circuit 11 are not aligned. Therefore, in the embodiment of the present application, the first input signal line 13 and the second input signal line 14 are extended in a direction oblique to the first direction X in the area within the fan-out wiring area 103 and between the bending area 104 and the transfer signal line 19, so that the first input signal line 13 and the second input signal line 14 can be connected to the first gate drive circuit 11.

[0127] In one embodiment, through holes may be provided in the bending region 104 of the first input signal line 13 and the second input signal line 14 to improve the bending ability of the first input signal line 13 and the second input signal line 14 , and the arrangement of the through holes is not limited in the embodiment of the present application.

[0128] Furthermore, the panel body 10 includes a substrate and a source / drain layer and a gate layer provided on the substrate, and the first input signal line 13 , the second input signal line 14 and the transfer signal line 19 can be independently selected to be located in the source / drain layer or the gate layer.

[0129] In one embodiment, the source-drain layer includes a transfer signal line 19. According to the process precision limitation of the source-drain layer, the length of the transfer signal line 19 along the first direction X is greater than or equal to 100 microns to avoid short circuits between the first input signal line 13, the second input signal line 14 and the transfer signal line 19 and the adjacent binding terminals 12 during the connection process.

[0130] In one embodiment, the gate layer includes a transfer signal line 19. According to the process precision limitation of the gate layer, the length of the transfer signal line 19 along the first direction X is greater than or equal to 20 microns to avoid short circuits between the first input signal line 13, the second input signal line 14 and the transfer signal line 19 and the adjacent binding terminals 12 during the connection process.

[0131] Furthermore, the first input signal line 13 includes multiple first line segments, and the multiple first line segments are independently located in the source and drain layer or the gate layer, that is, each first line segment can be selected to be located in the source and drain layer or the gate layer according to actual needs; for example, the first line segment of the first input signal line 13 located between the transfer signal line 19 and the bending area 104 can be located in the source and drain layer, the first line segment of the first input signal line 13 located in the bending area 104 can be located in the source and drain layer, and the first line segment of the first input signal line 13 located in the fan-out routing area 103 can be located in the gate layer.

[0132] The second input signal line 14 includes multiple second line segments, and the multiple second line segments are independently located in the source and drain layer or the gate layer, that is, each second line segment can be selected to be located in the source and drain layer or the gate layer according to actual needs; for example, the second line segment of the second input signal line 14 located between the transfer signal line 19 and the bending area 104 can be located in the source and drain layer, the second line segment of the second input signal line 14 located in the bending area 104 can be located in the source and drain layer, and the second line segment of the second input signal line 14 located in the fan-out routing area 103 can be located in the gate layer.

[0133] Please refer to Figures 5, 7, 9, 10 and 11. Since the connection points between the first input signal line 13 and the first gate drive circuit 11 and the connection points between the second input signal line 14 and the first gate drive circuit 11 are farther in the embodiment of the present application, the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14 is reduced, so that the sharp angle A appearing in the second scanning signal NscanT3 connected to the gate of the compensation transistor T03 is changed to the sharp angle a, and the degree of decrease in the potential of the second scanning signal NscanT3 at the sharp angle a is less than the degree of decrease at the sharp angle A, that is, the embodiment of the present application can effectively reduce the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14.

[0134] In one embodiment, a plurality of pixel driving circuits 16 are arranged in multiple rows and columns along the third direction N and the second direction M, wherein the first gate control circuit 111 connected to the first input signal line 13 can be connected to the pixel driving circuits 16 in odd rows, and the first gate control circuit 111 connected to the second input signal line 14 can be connected to the pixel driving circuits 16 in even rows; wherein the first scanning signal Pscan charges and turns on the switching transistors T02 in the pixel driving circuits 16 in the odd rows and the second scanning signal NscanT3 The time periods when the sharp corners B appear are staggered, and the time periods when the second scanning signal Pscan charges and turns on the switching transistor T02 in the pixel driving circuit 16 located in the even rows are staggered with the time periods when the sharp corners B appear in the second scanning signal NscanT3; since the second scanning signal NscanT3 will have a large downward fluctuation at the sharp corners B, the stage of data writing in the pixel driving circuit 16 in the embodiment of the present application is staggered with the time period when the sharp corners B appear in the second scanning signal NscanT3, so as to improve the stability of the pixel driving circuit 16 during the driving process.

[0135] Furthermore, one of the time period during which the first scanning signal Pscan charges and turns on the switching transistor T02 in the pixel driving circuit 16 located in the odd rows, and the time period during which the second scanning signal Pscan charges and turns on the switching transistor T02 in the pixel driving circuit 16 located in the even rows can be overlapped with the time period during which the sharp corner a appears in the second scanning signal NscanT3, while the other can be overlapped with the time period during which no sharp corner appears in the second scanning signal NscanT3.

[0136] Specifically, when the switching transistor T02 in the pixel driving circuit 16 located in the preset odd row is turned on, the compensation transistor T03 in the pixel driving circuit 16 located in the odd rows other than the preset odd row is not charged; when the switching transistor T02 in the pixel driving circuit 16 located in the preset even row is turned on, the compensation transistor T03 in the pixel driving circuit 16 located in the even rows other than the preset even row is not charged.

[0137] In addition, when the switching transistor T02 in the pixel driving circuit 16 located in the preset odd row is turned on, the compensation transistor T03 in the pixel driving circuit 16 located in the even row is charged, or when the switching transistor T02 in the pixel driving circuit 16 located in the preset even row is turned on, the compensation transistor T03 in the pixel driving circuit 16 located in the odd row is charged.

[0138] Furthermore, the embodiment of the present application performs brightness simulation verification on the display panels shown in Figures 1 and 5, and provides a pair of proportions and an embodiment. In the comparative example, the connection scheme shown in Figure 1 is adopted, and in the embodiment, the connection scheme shown in Figure 5 is adopted, and the brightness simulation data obtained is shown in Table 1 below.

[0139] Table 1 Brightness simulation data table

[0140] Comparative Example: Nscan T3 has a smaller sharp corner size (mV): 15246; odd-numbered line brightness (nit): 137.8135.7; even-numbered line brightness (nit): 132.3134.4; odd-even line difference: 4.07%0.96%

[0141] It can be seen from Table 1 above that the embodiment of the present application can effectively reduce the size of the smaller sharp corners appearing in the NscanT3 signal, and effectively reduce the luminous brightness of pixels in odd and even rows, thereby improving the display uniformity of the display panel.

[0142] Continuing from the above, the embodiment of the present application sets the connection point of the first input signal line 13 and the second input signal line 14 on the side of the bending area 104 away from the fan-out routing area 103, thereby making the connection point between the first input signal line 13 and the first gate drive circuit 11 and the connection point between the second input signal line 14 and the first gate drive circuit 11 farther, reducing the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14, and can improve the transmission stability of the signals in the first input signal line 13 and the second input signal line 14, improve the stability of the high-level signal output by the first gate control circuit 111, and improve the stability of the gate signals of the compensation transistor T03 and the driving transistor T01, thereby improving the display uniformity of the display panel.

[0143] In another embodiment of the present application, referring to FIG. 4 , FIG. 12 and FIG. 13 , the difference between this embodiment and the embodiment shown in FIG. 5 is that the first input signal line 13 and the second input signal line 14 are connected to different binding terminals 12 .

[0144] Specifically, the display panel includes multiple binding terminals 12, the second connection end 132 of the first input signal line 13 passes through the fan-out routing area 103 and the bending area 104 and is connected to one binding terminal 12, and the fourth end of the second input signal line 14 passes through the fan-out routing area 103 and the bending area 104 and is connected to another binding terminal 12.

[0145] The voltage loaded in the binding terminal 12 connected to the first input signal line 13 and the voltage loaded in the binding terminal 12 connected to the second input signal line 14 are both provided by the driver chip 31 on the circuit board 30, and the voltages loaded in both are the same, which are the same high-level signals.

[0146] Continuing from the above, the embodiment of the present application connects the first input signal line 13 and the second input signal line 14 to two binding terminals 12 respectively, thereby reducing the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14, and can improve the transmission stability of the signals in the first input signal line 13 and the second input signal line 14, improve the stability of the high-level signal output by the first gate control circuit 111, and improve the stability of the gate signals of the compensation transistor T03 and the driving transistor T01, thereby improving the display uniformity of the display panel.

[0147] In another embodiment of the present application, please refer to Figures 4, 14 and 15. The difference between this embodiment and the embodiment shown in Figure 5 is that: the first gate driving circuit 11 also includes a plurality of second gate control circuits 112 arranged in the first driving circuit area 1021 and arranged along the third direction N, the panel body 10 also includes a plurality of second output signal lines 114, and the plurality of second gate control circuits 112 are located on the side of the plurality of first gate control circuits 111 away from or close to the display area 101.

[0148] One end of a second output signal line 114 is connected to a second gate control circuit 112 , and the other end of a second output signal line 114 is connected to a plurality of pixel driving circuits 16 arranged along the second direction M.

[0149] It should be noted that, similarly, the second gate driving circuit 15 also includes a plurality of fourth gate control circuits 152 arranged in the second driving circuit area 1022 and arranged along the third direction N, and the plurality of fourth gate control circuits 152 are located on the side of the third gate control circuit 151 close to or away from the display area 101; and a fourth gate control circuit 152 and a second gate control circuit 112 jointly transmit signals to a plurality of pixel driving circuits 16 arranged along the second direction M through a second output signal line 114.

[0150] In one embodiment, the second gate control circuits 112 are located on a side of the first gate control circuits 111 away from the display area 101 , and the fourth gate control circuits 152 are located on a side of the third gate control circuits 151 away from the display area 101 .

[0151] Among them, the second output signal line 114 is used to transmit the signals in the second gate control circuit 112 and the fourth gate control circuit 152 to the gate of the first reset transistor T04. Since there is a parasitic capacitance between the gate of the first reset transistor T04 and the gate of the driving transistor T01, if the gate potential of the first reset transistor T04 fluctuates, the gate potential of the driving transistor T01 will also fluctuate, causing the display panel to produce uneven display.

[0152] In an embodiment of the present application, the circuit structures of the first gate control circuit 111, the second gate control circuit 112, the third gate control circuit 151 and the fourth gate control circuit 152 can all be arranged with reference to Figure 9, and the signals output by the first gate control circuit 111, the second gate control circuit 112, the third gate control circuit 151 and the fourth gate control circuit 152 to the pixel driving circuit 16 are the same and can all be high levels.

[0153] Since the signal connection method of the fourth gate control circuit 152 is the same as the signal connection method of the second gate control circuit 112 and is symmetrically arranged relative to the display area 101, the embodiment of the present application only describes the signal connection method of the second gate control circuit 112 as an example for illustration.

[0154] The high-level signals in the first gate control circuit 111 and the second gate control circuit 112 may be input through the first input signal line 13 and the second input signal line 14 .

[0155] Specifically, the panel body 10 also includes a first sub-line 1301 and a second sub-line 1302 connected to the first connection end 131, the first sub-line 1301 is connected to a plurality of first gate control circuits 111 arranged along a third direction N, the second sub-line 1302 is connected to a plurality of first gate control circuits 111 arranged along a third direction N, and the plurality of first gate control circuits 111 connected to the first sub-line 1301 and the plurality of first gate control circuits 111 connected to the second sub-line 1302 are alternately arranged along the third direction N.

[0156] The panel body 10 also includes a third sub-line 1401 and a fourth sub-line 1402 connected to the third connection end 141, the third sub-line 1401 is connected to a plurality of second gate control circuits 112 arranged along a third direction N, the fourth sub-line 1402 is connected to a plurality of second gate control circuits 112 arranged along a third direction N, and the plurality of second gate control circuits 112 connected to the third sub-line 1401 and the plurality of second gate control circuits 112 connected to the fourth sub-line 1402 are alternately arranged along the third direction N.

[0157] It can be understood that the first gate control circuit 111 connected to the first sub-line 1301 and the first gate control circuit 111 connected to the second sub-line 1302 are different first gate control circuits 111; the second gate control circuit 112 connected to the third sub-line 1401 and the second gate control circuit 112 connected to the fourth sub-line 1402 are different second gate control circuits 112.

[0158] Furthermore, the second connection end 132 and the fourth connection end 142 are connected to the transfer signal line 19 at a side of the bending area 104 away from the fan-out routing area 103 , so that the first input signal line 13 and the second input signal line 14 are connected to the same binding terminal 12 .

[0159] Continuing from the above, the embodiment of the present application sets the connection point of the first input signal line 13 and the second input signal line 14 on the side of the bending area 104 away from the fan-out routing area 103, thereby making the connection point between the first input signal line 13 and the first gate control circuit 111 and the connection point between the second input signal line 14 and the second gate control circuit 112 farther apart, reducing the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14, and can improve the transmission stability of the signals in the first input signal line 13 and the second input signal line 14, improve the stability of the high-level signal output by the first gate control circuit 111, and improve the stability of the gate signals of the compensation transistor T03, the first reset transistor T04 and the driving transistor T01, thereby improving the display uniformity of the display panel.

[0160] In another embodiment of the present application, please refer to Figures 4, 16 and 17. The difference between this embodiment and the embodiment shown in Figure 14 is that the second connection end 132 of the first input signal line 13 passes through the fan-out routing area 103 and the bending area 104 to be connected to a binding terminal 12, and the fourth connection end 142 of the second input signal line 14 passes through the fan-out routing area 103 and the bending area 104 to be connected to another binding terminal 12.

[0161] Continuing from the above, the embodiment of the present application connects the first input signal line 13 and the second input signal line 14 to two binding terminals 12 respectively, thereby reducing the mutual influence between the signal transmission in the first input signal line 13 and the signal transmission in the second input signal line 14, and can improve the transmission stability of the signals in the first input signal line 13 and the second input signal line 14, improve the stability of the high-level signal output by the first gate control circuit 111, and improve the stability of the gate signals of the compensation transistor T03, the first reset transistor T04 and the driving transistor T01, thereby improving the display uniformity of the display panel.

[0162] In another embodiment of the present application, please refer to Figures 4, 18 and 19. The difference between this embodiment and Figure 14 is that: the panel body 10 also includes a third input signal line 17, the fifth connection end 171 of the third input signal line 17 is electrically connected to the second gate control circuit 112, the sixth connection end 172 of the third input signal line 17 passes through at least a portion of the fan-out routing area 103 and is electrically connected to a binding terminal 12, and the voltage loaded on the binding terminal 12 electrically connected to the first input signal line 13 is the same as the voltage loaded on the binding terminal 12 electrically connected to the third input signal line 17.

[0163] Specifically, the first input signal line 13 is connected to a plurality of first gate control circuits 111 arranged along a third direction N, the second input signal line 14 is connected to a plurality of first gate control circuits 111 arranged along a third direction N, and the plurality of first gate control circuits 111 connected to the first input signal line 13 and the plurality of first gate control circuits 111 connected to the second input signal line 14 are alternately arranged along the third direction N.

[0164] The fifth connection end 171 of the third input signal line 17 is electrically connected to the second gate control circuit 112, the sixth connection end 172 of the third input signal line 17 passes through the fan-out routing area 103 and the bending area 104 and is connected to the transfer signal line 19, the second connection end 132 of the first input signal line 13, the fourth connection end 142 of the second input signal line 14, and the sixth connection end 172 of the third input signal line 17 are connected to the transfer signal line 19 on the side of the bending area 104 away from the fan-out routing area 103.

[0165] The panel body 10 also includes a fifth sub-line 1701 and a sixth sub-line 1702 connected to the fifth connection end 171, the fifth sub-line 1701 is connected to a plurality of second gate control circuits 112 arranged along a third direction N, the sixth sub-line 1702 is connected to a plurality of second gate control circuits 112 arranged along a third direction N, and the plurality of second gate control circuits 112 connected to the fifth sub-line 1701 and the plurality of second gate control circuits 112 connected to the sixth sub-line 1702 are alternately arranged along the third direction N.

[0166] It can be understood that the first gate control circuit 111 connected to the first input signal line 13 and the first gate control circuit 111 connected to the second input signal line 14 are different first gate control circuits 111; the second gate control circuit 112 connected to the fifth sub-line 1701 and the second gate control circuit 112 connected to the sixth sub-line 1702 are different second gate control circuits 112.

[0167] Continuing from the above, the embodiment of the present application arranges the connection points of the first input signal line 13, the second input signal line 14 and the third input signal line 17 on the side of the bending area 104 away from the fan-out routing area 103, thereby making the connection points between the first input signal line 13 and the first gate control circuit 111, the connection points between the second input signal line 14 and the first gate control circuit 111, and the connection points between the third input signal line 17 and the second gate control circuit 112 farther apart, thereby reducing the mutual influence of the signal transmission in the first input signal line 13, the signal transmission in the second input signal line 14, and the signal transmission in the third input signal line 17, and can improve the transmission stability of the signals in the first input signal line 13, the second input signal line 14 and the third input signal line 17, improve the stability of the high-level signal output by the first gate control circuit 111, and improve the stability of the gate signals of the compensation transistor T03, the first reset transistor T04 and the driving transistor T01, thereby improving the display uniformity of the display panel.

[0168] In another embodiment of the present application, please refer to Figures 4, 20 and 21. The difference between this embodiment and the embodiment shown in Figure 18 is that: the panel body 10 also includes a fourth input signal line 18, the seventh connection terminal 181 of the fourth input signal line 18 is electrically connected to the second gate control circuit 112, the eighth connection terminal 182 of the fourth input signal line 18 passes through at least part of the fan-out routing area 103 and is electrically connected to a binding terminal 12, and the voltage loaded on the binding terminal 12 electrically connected to the first input signal line 13 is the same as the voltage loaded on the binding terminal 12 electrically connected to the fourth input signal line 18.

[0169] Specifically, the seventh connection end 181 of the fourth input signal line 18 is connected to the second gate control circuit 112, the eighth connection end 182 of the fourth input signal line 18 passes through the fan-out routing area 103 and the bending area 104 and is connected to the transfer signal line 19, and the second connection end 132 of the first input signal line 13, the fourth connection end 142 of the second input signal line 14, the sixth connection end 172 of the third input signal line 17 and the eighth connection end 182 of the fourth input signal line 18 are connected to the transfer signal line 19 on the side of the bending area 104 away from the fan-out routing area 103.

[0170] The third input signal line 17 is connected to a plurality of second gate control circuits 112 arranged along a third direction N, the fourth input signal line 18 is connected to a plurality of second gate control circuits 112 arranged along a third direction N, and the plurality of second gate control circuits 112 connected to the third input signal line 17 and the plurality of second gate control circuits 112 connected to the fourth input signal line 18 are alternately arranged along the third direction N.

[0171] It can be understood that the first gate control circuit 111 connected to the first input signal line 13 and the first gate control circuit 111 connected to the second input signal line 14 are different first gate control circuits 111; the second gate control circuit 112 connected to the third input signal line 17 and the second gate control circuit 112 connected to the fourth input signal line 18 are different second gate control circuits 112.

[0172] As mentioned above, in the embodiment of the present application, the connection points of the first input signal line 13, the second input signal line 14, the third input signal line 17 and the fourth input signal line 18 are arranged on the side of the bending area 104 away from the fan-out wiring area 103, thereby making the connection points of the first input signal line 13 and the first gate control circuit 111, the connection points of the second input signal line 14 and the first gate control circuit 111, the connection points of the third input signal line 17 and the second gate control circuit 112, and the connection points of the fourth input signal line 18 and the second gate control circuit 112 farther, thereby reducing the first input signal line 13 and the second gate control circuit 111. The mutual influence of the signal transmission in the first input signal line 13, the signal transmission in the second input signal line 14, the signal transmission in the third input signal line 17, and the signal transmission in the fourth input signal line 18 can improve the transmission stability of the signals in the first input signal line 13, the second input signal line 14, the third input signal line 17, and the fourth input signal line 18, improve the stability of the high-level signal output by the first gate control circuit 111, and improve the stability of the gate signals of the compensation transistor T03, the first reset transistor T04, and the driving transistor T01, thereby improving the display uniformity of the display panel.

[0173] In addition, an embodiment of the present application further provides a display device, which includes the display panel as described in the above embodiment.

[0174] Since the display device includes the display panel described in the above embodiment, the display device has the same beneficial effects as the display panel described in the above embodiment, which will not be described in detail here.

[0175] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0176] The above is a detailed introduction to a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, comprising a display area, a first driving circuit area located on a first side of the display area, and a fan-out wiring area located on a second side of the display area; The display panel further includes: The panel body includes a first gate driving circuit arranged in the first driving circuit area, at least one binding terminal arranged on a side of the fan-out wiring area away from the display area, a first input signal line, and a second input signal line; The first input signal line includes a first connection end and a second connection end opposite to each other, the first connection end is electrically connected to the first gate driving circuit, and the second connection end is electrically connected to one of the binding terminals, and a portion of the first input signal line is located in the fan-out routing area; The second input signal line includes a third connection end and a fourth connection end opposite to each other, the third connection end is electrically connected to the first gate driving circuit, and the fourth connection end is electrically connected to one of the binding terminals, and a portion of the second input signal line is located in the fan-out routing area; The voltage loaded on the binding terminal electrically connected to the first input signal line is the same as the voltage loaded on the binding terminal electrically connected to the second input signal line.

2. The display panel according to claim 1, wherein The first input signal line and the second input signal line are electrically connected to the same binding terminal.

3. The display panel according to claim 1, wherein: The panel body further includes a transfer signal line, one end of which is connected to the binding terminal, and the other end of which is connected to the second connection end and the fourth connection end.

4. The display panel according to claim 3, wherein: The second connection end, the fourth connection end, and part of the transfer signal lines are all located in the fan-out routing area.

5. The display panel according to claim 3, wherein: The display panel further includes a bending area disposed on a side of the fan-out wiring area away from the display area, and the second connection end, the fourth connection end, and a portion of the transfer signal line are all located in the bending area. The display panel according to claim 3 , wherein: The display panel further includes a bending area disposed on a side of the fan-out wiring area away from the display area, and the second connection end, the fourth connection end, and the transfer signal line are all located on a side of the bending area away from the fan-out wiring area.

7. The display panel according to claim 6, wherein: The transfer signal line extends along a first direction, which is a direction in which the bending area approaches the fan-out routing area.

8. The display panel according to claim 7, wherein: The first input signal line extends in the fan-out routing area along a direction that is oblique to the first direction, the first input signal line extends in the bending area along the first direction, and the first input signal line extends in the direction that is oblique to the first direction between the bending area and the transfer signal line; The second input signal line extends in a direction oblique to the first direction in the fan-out routing area, the second input signal line extends in the first direction in the bending area, and the second input signal line extends in a direction oblique to the first direction between the bending area and the transfer signal line.

9. The display panel according to claim 7, wherein: The panel body includes a source / drain layer and a gate layer; The source-drain electrode layer includes the transfer signal line, and the length of the transfer signal line along the first direction is greater than or equal to 100 microns; Alternatively, the gate layer includes the transfer signal line, and the length of the transfer signal line along the first direction is greater than or equal to 20 micrometers.

10. The display panel according to claim 9, wherein: The first input signal line includes multiple first line segments, and the multiple first line segments are independently located in the source and drain layer or the gate layer. The second input signal line includes multiple second line segments, and the multiple second line segments are independently located in the source and drain layer or the gate layer.

11. The display panel according to claim 1, wherein: The binding terminal electrically connected to the first input signal line and the binding terminal electrically connected to the second input signal line are different binding terminals.

12. The display panel according to claim 1, wherein: The panel body includes a plurality of pixel driving circuits disposed in the display area and arranged along a second direction and a third direction, wherein the second direction intersects the third direction, and the first gate driving circuit includes a plurality of first gate control circuits disposed in the first driving circuit area and arranged along the third direction; The panel body also includes multiple first output signal lines, one end of each first output signal line is connected to a first gate control circuit, and the other end of each first output signal line is connected to a plurality of pixel driving circuits arranged along the second direction, and the first output signal line is used to transmit the voltage signals in the first input signal line and the second input signal line to the pixel driving circuit.

13. The display panel according to claim 12, wherein: The first input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, the second input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, and the plurality of the first gate control circuits connected to the first input signal line and the plurality of the first gate control circuits connected to the second input signal line are alternately arranged along the third direction.

14. The display panel according to claim 12, wherein: The first gate driving circuit further includes a plurality of second gate control circuits disposed in the first driving circuit area and arranged along the third direction. The panel body further includes a plurality of second output signal lines. The plurality of second gate control circuits are located on a side of the plurality of first gate control circuits that is away from or close to the display area. One end of a second output signal line is connected to a second gate control circuit, and the other end of a second output signal line is connected to a plurality of the pixel driving circuits arranged along the second direction.

15. The display panel according to claim 14, wherein: The panel body further includes a first sub-line and a second sub-line connected to the first connection end, the first sub-line being connected to a plurality of the first gate control circuits arranged along the third direction, the second sub-line being connected to a plurality of the first gate control circuits arranged along the third direction, and the plurality of the first gate control circuits connected to the first sub-line and the plurality of the first gate control circuits connected to the second sub-line being alternately arranged along the third direction; The panel body also includes a third sub-line and a fourth sub-line connected to the third connection end, the third sub-line is connected to a plurality of second gate control circuits arranged along the third direction, the fourth sub-line is connected to a plurality of second gate control circuits arranged along the third direction, and the plurality of second gate control circuits connected to the third sub-line and the plurality of second gate control circuits connected to the fourth sub-line are alternately arranged along the third direction.

16. The display panel according to claim 14, wherein: The first input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, and the second input signal line is connected to a plurality of the first gate control circuits arranged along the third direction, and the plurality of the first gate control circuits connected to the first input signal line and the plurality of the first gate control circuits connected to the second input signal line are alternately arranged along the third direction; The panel body also includes a third input signal line, the fifth connection end of the third input signal line is electrically connected to the second gate control circuit, the sixth connection end of the third input signal line passes through at least a portion of the fan-out routing area and is electrically connected to one of the binding terminals, and the voltage loaded on the binding terminal electrically connected to the first input signal line is the same as the voltage loaded on the binding terminal electrically connected to the third input signal line.

17. The display panel according to claim 16, wherein: The panel body further includes a fourth input signal line, wherein a seventh connection end of the fourth input signal line is electrically connected to the second gate control circuit, and an eighth connection end of the fourth input signal line passes through at least a portion of the fan-out routing area and is electrically connected to one of the binding terminals, wherein a voltage applied to the binding terminal electrically connected to the first input signal line is the same as a voltage applied to the binding terminal electrically connected to the fourth input signal line; The third input signal line is connected to a plurality of second gate control circuits arranged along the third direction, the fourth input signal line is connected to a plurality of second gate control circuits arranged along the third direction, and the plurality of second gate control circuits connected to the third input signal line and the plurality of second gate control circuits connected to the fourth input signal line are alternately arranged along the third direction.

18. The display panel according to claim 16, wherein: The panel body also includes a fifth sub-line and a sixth sub-line connected to the fifth connection end, the fifth sub-line is connected to a plurality of second gate control circuits arranged along the third direction, the sixth sub-line is connected to a plurality of second gate control circuits arranged along the third direction, and the plurality of second gate control circuits connected to the fifth sub-line and the plurality of second gate control circuits connected to the sixth sub-line are alternately arranged along the third direction.

19. The display panel according to claim 12, wherein: The pixel driving circuit includes a driving transistor and a compensation transistor, the first electrode of the driving transistor and the first electrode of the compensation transistor are both connected to a first node, the gate of the driving transistor and the second electrode of the compensation transistor are both connected to a second node, and the first output signal line is connected to the gate of the compensation transistor.

20. The display panel according to claim 19, wherein The compensation transistor is an N-type thin film transistor, and the voltage loaded on the binding terminal electrically connected to the first input signal line and the voltage loaded on the binding terminal electrically connected to the second input signal line are both high level.

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