On-chip voltage prediction circuit based on power delivery network parameters

Abstract

Disclosed is an on-chip voltage prediction circuit based on power delivery network (PDN) parameters, aiming to solve the problem in traditional chips that the voltage monitoring circuit has a delay of several cycles when measuring on-chip voltage, and voltage prediction methods based on historical data have relatively low accuracy. The circuit comprises: an on-chip PDN impedance scanning module, an on-chip voltage monitoring module, an on-chip PDN parameter table storage module, an on-chip predictive digital power meter, and an on-chip voltage prediction calculation module; a physical model from historical voltage and predicted current information to predicted voltage information is established; by quantizing the model and integrating same with the voltage monitoring circuit and the predictive digital power meter, on-chip deployment of the voltage prediction circuit is implemented, and the effect of predicting future on-chip voltage is achieved.

Description

On-chip voltage prediction circuit based on power delivery network parameters Technical Field

[0001] The invention discloses an on-chip voltage prediction circuit based on power transmission network parameters, relates to a low-power design technology for integrated circuits, and belongs to the technical field of calculation, estimation or counting. Background Art

[0002] With the rapid development of integrated circuits, chip technology and integration levels continue to improve, and the rate of change of current on the chip continues to increase, which in turn causes on-chip voltage fluctuations. When the voltage fluctuates sharply, the circuit timing margin is insufficient or even fails to meet the minimum voltage requirement, which in turn causes circuit function errors. The frequency of voltage fluctuations ranges from tens to hundreds of megahertz, and the highest voltage fluctuation frequency depends on the size of the package inductor and on-chip capacitors in the power delivery network (PDN). To cope with voltage fluctuations, low-dropout linear regulators, DC-DC converters, and other means are needed to regulate the on-chip voltage to avoid timing errors. However, voltage regulation first requires real-time acquisition of the on-chip voltage to guide the direction of voltage regulation.

[0003] Due to the influence of synchronous clocks, on-chip voltage monitoring modules contain post-processing and calibration circuits, resulting in a delay in the output code value relative to the on-chip voltage. Although on-chip predictive digital power meters can predict dynamic power consumption in advance, power consumption changes cannot be directly mapped to on-chip voltage fluctuations. Traditional on-chip voltage prediction schemes have several problems. For example, voltage prediction based on pipeline events relies on manual experience to select events, making it difficult to adapt to different application scenarios. Designs based on historical voltage and support vector machines require a large number of multiplication and accumulation units, limiting the circuit size and accuracy of predictions. Schemes based on historical voltage and voltage change rate have limited monitoring windows, making it difficult to accurately predict complex voltage changes.

[0004] Therefore, a voltage prediction circuit based on the physical model of the power transmission network is needed. It combines the historical voltage information and predicted power consumption information on the chip to predict the on-chip voltage, so as to achieve accurate prediction of the complex and changeable on-chip voltage with less hardware overhead.

[0005] Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and propose an on-chip voltage prediction circuit based on power transmission network parameters. Through on-chip voltage monitoring, on-chip power prediction, on-chip voltage prediction calculation and other technologies, the problems of high hardware cost and poor prediction accuracy of the existing voltage prediction circuit are solved.

[0007] To achieve the above object, the technical solution adopted by the present invention is:

[0008] An on-chip voltage prediction circuit based on power transmission network parameters includes: an on-chip PDN impedance scanning module, an on-chip PDN parameter table storage module, an on-chip voltage monitoring module, an on-chip predictive digital power meter, and an on-chip voltage prediction calculation module; the on-chip PDN impedance scanning module obtains a PDN impedance-frequency curve by configuring currents of different frequencies on the chip; the on-chip voltage monitoring module is used to monitor and record the on-chip voltage under currents of different frequencies in real time, obtain the on-chip voltage under periodic current changes, and output historical voltage code values; the on-chip PDN parameter table storage module is used to store on-chip PDN parameters obtained based on the on-chip voltage under currents of different frequencies and the PDN impedance-frequency curve; the on-chip predictive digital power meter is used to monitor the on-chip current in real time and output a predicted current code value; the on-chip voltage prediction calculation module substitutes the historical voltage code value output by the on-chip voltage monitoring module and the predicted current code value output by the on-chip predictive digital power meter into the on-chip voltage prediction formula obtained by quantizing the on-chip PDN parameters: V dp [n] = c1 * I d [n]+c2*I d [n-1]+c3*I d [n-2]-d1*V dn [n-1]-d2*V dn [n-2], calculate the predicted voltage code value of the digital system according to the on-chip voltage prediction formula.

[0009] As a further optimization scheme for the on-chip voltage prediction circuit based on the power transmission network parameters, the on-chip PDN parameters are obtained by the host computer based on the on-chip voltage at different frequency currents and the PDN impedance-frequency curve. Specifically, the host computer infers the effective value of the on-chip voltage at different frequency currents and calculates the impedance of the PDN at different frequencies. It fits the second-order impedance network transfer function formula that conforms to the PDN impedance-frequency curve, and extracts the parameters in the second-order impedance network transfer function formula as the on-chip PDN parameters.

[0010] As a further optimization scheme for the on-chip voltage prediction circuit based on the power transmission network parameters, the host computer calculates the effective value of the on-chip voltage under different frequency currents and calculates the impedance of the PDN at different frequencies. The specific method is as follows: for the on-chip voltage U(f) at frequency f, half of the difference between the maximum and minimum values ​​of the on-chip voltage U(f) at frequency f is divided by the square root of 2 to obtain the effective value of the on-chip voltage at frequency f. The effective value of the on-chip voltage at frequency f is divided by the effective value of the current at frequency f to obtain the impedance of the PDN at frequency f.

[0011] As a further optimization scheme for the on-chip voltage prediction circuit based on the power delivery network parameters, the second-order impedance network transfer function formula that conforms to the PDN impedance-frequency curve is fitted. Specifically, the second-order impedance network transfer function formula that conforms to the PDN impedance-frequency curve is fitted according to the Laplace frequency transform relationship. Perform the transformation to obtain the corresponding formula between impedance and frequency, and then combine the data points on the PDN impedance-frequency curve to use the least squares method to fit the parameters a1, a2, b1, and b2 of the second-order impedance network transfer function formula.

[0012] As a further optimization scheme for the on-chip voltage prediction circuit based on the power delivery network parameters, the on-chip voltage prediction formula obtained by quantizing the on-chip PDN parameters is V dp [n] = c1 * I d [n]+c2*I d [n-1]+ c3*I d [n-2]-d1*V dn [n-1]-d2*V dn [n-2], where V dp [n] is the voltage prediction at time n, I d [n] is the predicted current at time n, I d [n-1] is the predicted current at time n-1, I d [n-2] is the predicted current at time n-2, V dn [n-1] is the on-chip voltage monitoring value at time n-1, V dn [n-2] is the on-chip voltage monitoring value at time n-2, and c1, c2, c3, d1, and d2 are based on the bilinear transformation formula: The parameters of the transfer function obtained by converting the second-order impedance network transfer function formula into the discrete z domain are: T is a system clock cycle, and the corresponding parameters c1, c2, c3, d1, and d2 of the power transmission network are respectively compared with the current prediction value I at time n. d [n], the predicted current value I at time n-1 d The predicted current I at time [n-1] and time n-2 d On-chip voltage monitoring value V at time [n-2] and n-1 dn On-chip voltage monitoring value V at time [n-1] and n-2 dn [n-2] is multiplied by the multiplier, and then passes through the three-stage adder to add and subtract the calculation results to obtain the on-chip voltage prediction value V at the output time n. dpThe delay of the discrete sequence is implemented by clock registering through a D-type flip-flop. Combining the outputs of the on-chip voltage monitoring module and the on-chip predictive digital power meter, the proposed on-chip voltage prediction circuit based on the power transmission network parameters can obtain the predicted voltage code value.

[0013] As a further optimization solution for the on-chip voltage prediction circuit based on power delivery network parameters, the on-chip PDN impedance scanning module includes: a configuration module and an artificial current load module. The configuration module is used to control the activation of each ring oscillator circuit in the artificial current load module. The artificial current load module contains a configurable number of ring oscillator circuits and simulates currents of different frequencies on the load under the control of the configuration module.

[0014] As a further optimization scheme for the on-chip voltage prediction circuit based on power transmission network parameters, the on-chip voltage monitoring module includes: a voltage-controlled oscillator, a code value sampling module and a quantization logic module; the voltage-controlled oscillator is used to map the changes in on-chip voltage under different frequency currents into device delay changes; the code value sampling module is used to sample the position of the signal flip on the voltage-controlled oscillator; the quantization logic module is used to count the position of the signal flip on the voltage-controlled oscillator at the beginning of the sampling period, the position of the signal flip on the voltage-controlled oscillator at the end of the sampling period, and the total number of oscillations within a system clock cycle T, and output the historical voltage code value.

[0015] As a further optimization scheme of the on-chip voltage prediction circuit based on the power transmission network parameters, the on-chip predictive digital power meter includes: a signal flip monitoring module, a current calculation module and a current correction module; the signal flip monitoring module deployed in each processor system is used to monitor the flip of key signals in the processor system to which it belongs, and output the flip monitoring results of the key signals in the processor system to which it belongs to the current calculation module in the processor system to which it belongs; the current calculation module deployed in each processor system is used to multiply the flip monitoring results of the key signals in the processor system to which it belongs and the corresponding weights through a multiplier to obtain the current corresponding to the flip of each key signal, add the current corresponding to the flip of each key signal through an addition tree to obtain the current value corresponding to the flip of the key signal on the processor system to which it belongs; the current correction module is used to add the current value corresponding to the flip of the key signal on each processor system and the current value on the clock tree to obtain the current of each processor, add the current of the processors with valid clocks to obtain the predicted current code value.

[0016] The present invention adopts the above technical solution and has the following advantages:

[0017] (1) The on-chip voltage prediction circuit proposed in this invention uses an on-chip PDN impedance scanning module and cooperates with a host computer to fit PDN parameters. This fully integrated circuit completes current changes and voltage monitoring at different frequencies to obtain the actual power transmission network impedance. This is simple and easy to implement. The on-chip PDN impedance scanning module is run once when the chip leaves the factory to obtain the chip impedance parameters. The PDN impedance scanning module can be turned off during chip operation thereafter, without generating additional power consumption.

[0018] (2) The present invention realizes on-chip voltage prediction based on the power transmission network parameters. Compared with the traditional voltage monitoring scheme, it can predict the on-chip voltage in real time, avoid monitoring lag, and take into account the characteristics of the chip power transmission network. The obtained prediction result is more real and reliable than the prediction based on the voltage monitoring value during operation alone.

[0019] (3) The present invention uses a physical model to derive the real-time on-chip voltage, combines the predicted current and the monitored on-chip voltage, and completes the hardware implementation according to the transmission network formula. Compared with other voltage prediction schemes, it reduces the hardware overhead and improves the accuracy of the model prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a schematic diagram of an on-chip voltage prediction circuit based on power transmission network parameters according to the present invention.

[0021] FIG2 is a schematic diagram of a physical model of an on-chip power transmission network according to the present invention.

[0022] FIG3 is a schematic diagram of an on-chip PDN impedance scanning module of the present invention.

[0023] FIG4 is a schematic diagram of an on-chip voltage monitoring module of the present invention.

[0024] FIG5 is a schematic diagram of an on-chip predictive digital power meter according to the present invention.

[0025] FIG6 is a circuit diagram of the on-chip voltage prediction and calculation module of the present invention.

[0026] FIG7 is a diagram showing the simulation effect of on-chip voltage prediction according to the present invention. DETAILED DESCRIPTION

[0027] In order to better understand the purpose, structure and function of the present invention, the on-chip voltage prediction circuit based on power transmission network parameters of the present invention is further described in detail below with reference to the accompanying drawings.

[0028] Figure 1 shows an on-chip voltage prediction circuit based on power transmission network parameters, including: an on-chip PDN impedance scanning module, an on-chip PDN parameter table storage module, an on-chip voltage monitoring module, an on-chip predictive digital power meter, and an on-chip voltage prediction calculation module; the on-chip PDN impedance scanning module obtains a PDN impedance-frequency curve by configuring currents of different frequencies on the chip; the on-chip voltage monitoring module is used to monitor and record the on-chip voltage under currents of different frequencies in real time, obtain the on-chip voltage under periodic current changes, and output historical voltage code values; the on-chip PDN parameter table storage module is used to store on-chip PDN parameters obtained based on the on-chip voltage under currents of different frequencies and the PDN impedance-frequency curve; the on-chip predictive digital power meter is used to monitor the on-chip current in real time and output predicted current code values; the on-chip voltage prediction calculation module calculates the predicted voltage code value of the digital system according to the on-chip voltage prediction formula by substituting the historical voltage code values ​​output by the on-chip voltage monitoring module and the predicted current code values ​​output by the on-chip predictive digital power meter into the on-chip voltage prediction formula obtained by quantizing the on-chip PDN parameters. The on-chip PDN parameters are obtained by the host computer based on the on-chip voltage at different frequency currents and the PDN impedance-frequency curve.

[0029] Figure 2 is a schematic diagram of the physical model of an on-chip power transmission network. Figure 2 shows the parasitic impedances encountered when off-chip power is transmitted to different physical locations. A regulated power supply typically uses a switching power supply structure, with an output end containing an inductor and filter capacitors. Long traces are typically required from the regulated power supply to the chip's power supply. To ensure that the chip's input power is not affected, decoupling capacitors are typically placed on the PCB near the chip to prevent low-impedance paths. During the chip packaging phase, package inductance and resistance are introduced by the package bonding wires and chip pins. Furthermore, the parasitic capacitance introduced by various on-chip components, including on-chip decoupling capacitors, should not be neglected. Figure 2 shows the frequency characteristic curve of a typical processor PDN impedance. The peak occurs near 100 MHz, primarily due to the package's parasitic inductance, on-chip parasitic capacitance, and decoupling capacitors. The voltage drop caused by this peak impedance is generally the maximum possible voltage drop on the chip, and a certain margin must be left for this worst-case voltage drop during chip design. The transfer function of the s-domain second-order impedance network model of the power transmission network represented by this curve is: The host computer calculates the second-order impedance network transfer function formula that conforms to the PDN impedance-frequency curve based on the Laplace frequency transform relationship. Perform the transformation to obtain the corresponding formula between impedance and frequency. Then, combine the data points on the PDN impedance-frequency curve and use the least squares method to fit the parameters a1, a2, b1, and b2 of the second-order impedance network transfer function formula. The on-chip voltage prediction calculation module then uses the bilinear transformation formula: The s-domain second-order impedance network transfer function formula can be converted into a discrete z-domain transfer function, where T in the bilinear transformation formula is the digital circuit system clock period:

[0030] The on-chip PDN impedance scanning module utilizes a configurable number of ring oscillator circuits on the chip. By configuring the ring oscillator's various frequencies, it simulates currents of varying frequencies on the load. Figure 3 shows a schematic diagram of the on-chip PDN impedance scanning module, which consists of a configuration module and M-level artificial current load modules. Each artificial current load module is composed of N inverters and a NAND gate connected end-to-end, where N is any odd number greater than 32. The other input of the NAND gate serves as an enable signal. When the enable signal is 1, the artificial current load oscillates, generating a current load of a fixed magnitude. When the enable signal is 0, the ring oscillation is disabled, and no current is generated. By controlling the enable signal at each moment, different current magnitudes can be generated at different times. The configuration module includes a state configuration, a state machine, a counter, and a lookup table. First, an average of X points from one complete cycle of a sinusoidal signal with an amplitude of 0 to M is sampled and stored in the lookup table. The configuration signal determines the interval p points to fetch a data from the lookup table to change the configured current oscillation frequency. Finally, the state machine and counter determine the position of the data in the lookup table corresponding to the enable signal output at the current moment. The enable signal is decoded to correspond to the number of artificial current loads of size 0-M that are turned on.

[0031] The host computer records the on-chip voltage at different frequency currents according to the on-chip voltage monitoring module and derives the effective value of the voltage. The calculation formula for the effective value of the on-chip voltage Ur(f) at frequency f is: Where Um(f) is half the difference between the maximum and minimum on-chip voltages at the monitored frequency f: The specific impedance of the power transmission network at the configured frequency f is obtained by dividing the effective value of the on-chip voltage at frequency f by the effective value of the current at frequency f. The host computer transforms the transfer function Z(s) of the s-domain second-order impedance network model of the power transmission network according to the Laplace frequency transform relationship to obtain the corresponding formula between impedance and frequency. Using the least squares method, the parameters a1, a2, b1, and b2 in the transfer function formula of the s-domain second-order impedance network model of the power transmission network can be fitted to each data point (Zk, fk) on the impedance-frequency curve obtained by the PDN scan. s represents the Laplace operator, Zk represents the impedance at the kth data point on the impedance-frequency curve, and fk represents the frequency at the kth data point on the impedance-frequency curve.

[0032] Figure 4 is a schematic diagram of the on-chip voltage monitoring module, which mainly includes a voltage-controlled ring oscillator, a cross-voltage domain sampling module, and a quantization logic module. The final output of the monitoring voltage code value V dnRepresents the voltage magnitude quantized at the current moment. First, a voltage-controlled ring oscillator is used to map voltage changes to device delay changes; the cross-voltage domain sampling module samples the flip position of the ring oscillator; then, the quantization logic module counts the position of the signal flip at the beginning of the cycle, the position of the signal flip at the end of the cycle, and the total number of oscillations within a sampling period T, and finally outputs the voltage code value V dn .

[0033] Figure 5 is a schematic diagram of the predictive digital power meter module. The predictive digital power meter module circuit consists of three parts: a signal flip monitoring module, a current calculation module, and a current correction module. For a multi-core digital system chip, each processor is configured with a signal flip monitoring module and a current calculation module. The signal flip monitoring module determines whether the input original signal has flipped, representing the signal flip detection result as 1 or 0. For multi-bit-width signals, an OR operation is performed on each signal flip detection result to determine whether the overall flip has occurred. The current calculation module uses a multiplier to multiply the signal flip detection result by the corresponding weight. Then, using an adder tree, the current corresponding to each signal flip is added together to obtain the current value corresponding to the signal flip on a single processor. The current correction module adds the current corresponding to the signal flip on each processor in the multi-core digital system with the current in the clock tree to obtain the current of each processor, determine whether the corresponding processor's clock is valid, and finally sum the currents of each processor to obtain the dynamic current code value for the entire multi-core digital system chip. The weight information in the current calculation module is obtained by training a feature network. Whether certain key signals in the digital chip system are flipped is used as the network input, and the corresponding system power consumption is used as the network label. The network is trained to obtain weights that enable the network output results to reflect the power consumption of the digital system.

[0034] Figure 6 is the circuit diagram of the on-chip voltage prediction and calculation module. The power transmission network curve is obtained by the scanning module, and the parameters in the z-domain transfer function are obtained by fitting. After that, the Z-domain transfer function is transformed inversely to obtain a discrete sequence equation that is conducive to circuit implementation, that is, the on-chip voltage prediction formula obtained by quantizing the on-chip PDN parameters: V dp [n] = c1 * I d [n]+c2*I d [n-1]+c3*I d [n-2]-d1*V dn [n-1]-d2*V dn [n-2]

[0035] Among them, I d [n] corresponds to the output of the predictive digital power meter, that is, the current prediction at time n, V dn[n-1] corresponds to the output of the voltage monitoring module, that is, the on-chip voltage monitoring value at time n-1. First, the corresponding parameters c1, c2, c3, d1, and d2 of the power transmission network are respectively compared with the current prediction value I at time n. d [n], the predicted current value I at time n-1 d The predicted current I at time [n-1] and time n-2 d On-chip voltage monitoring value V at time [n-2] and n-1 dn On-chip voltage monitoring value V at time [n-1] and n-2 dn [n-2] is multiplied by the multiplier, and then passes through the three-stage adder to add or subtract the calculation results to obtain the on-chip voltage prediction value V at time n. dp [n], the delay of discrete sequence is realized by clock register through D flip-flop.

[0036] Due to the quantization delay of the voltage monitoring module, the calculation is already behind the real-time voltage value, so the formula uses Id[n], Id[n-1], Id[n-2], V dn [n-1], V dn [n-2] These measurements, combined with the power transmission network parameters, are used to determine the real-time voltage V dp [n] Make predictions.

[0037] Figure 7 shows the simulation results of voltage prediction. The horizontal axis represents time in nanoseconds, and the vertical axis represents the voltage drop, which is calculated by subtracting the actual on-chip voltage from the output voltage of the off-chip regulated power supply. The gray line in the figure represents the voltage drop in the simulated waveform, while the black line represents the voltage drop predicted by the voltage prediction circuit of the present invention. As can be seen, the trends of the two are quite consistent, with the maximum prediction error within 5mV.

[0038] It will be understood that the present invention is described by way of some embodiments, and that those skilled in the art may make various changes or equivalent substitutions to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. An on-chip voltage prediction circuit based on power delivery network parameters, characterized in that: include: On-chip PDN impedance scanning module, used to configure currents of different frequencies on-chip and obtain PDN impedance-frequency curves; On-chip voltage monitoring module, used to monitor and record the on-chip voltage under different frequency currents in real time, obtain the on-chip voltage under periodic current changes, and output historical voltage code values; An on-chip PDN parameter table storage module is used to store on-chip PDN parameters obtained based on on-chip voltages and PDN impedance-frequency curves under different frequency currents; An on-chip predictive digital power meter for real-time monitoring of on-chip current and outputting a predicted current code value; and The on-chip voltage prediction calculation module is used to receive the historical voltage code value output by the on-chip voltage monitoring module and the predicted current code value output by the on-chip predictive digital power meter, substitute the received historical voltage code value and predicted current code value into the on-chip voltage prediction formula obtained by quantizing the on-chip PDN parameters, calculate the on-chip voltage prediction code value and output it.

2. The on-chip voltage prediction circuit based on power transmission network parameters according to claim 1, characterized in that: The on-chip PDN parameters are obtained by the host computer based on the on-chip voltage under different frequency currents and the PDN impedance-frequency curve. Specifically, the host computer calculates the effective value of the on-chip voltage under different frequency currents and calculates the impedance size of the PDN at different frequencies, fits the second-order impedance network transfer function formula that conforms to the PDN impedance-frequency curve, and extracts the parameters in the second-order impedance network transfer function formula as the on-chip PDN parameters.

3. The on-chip voltage prediction circuit based on power transmission network parameters according to claim 2, characterized in that: The specific method for the upper computer to calculate the effective value of the on-chip voltage at different frequency currents and calculate the impedance size of the PDN at different frequencies is as follows: for the on-chip voltage U(f) at frequency f, half of the difference between the maximum and minimum values of the on-chip voltage U(f) at frequency f is divided by the square root of 2 to obtain the effective value of the on-chip voltage at frequency f, and the effective value of the on-chip voltage at frequency f is divided by the effective value of the current at frequency f to obtain the impedance size of the PDN at frequency f.

4. The on-chip voltage prediction circuit based on power transmission network parameters according to claim 3, characterized in that: The second-order impedance network transfer function formula that fits the PDN impedance-frequency curve is specifically: the second-order impedance network transfer function formula that fits the PDN impedance-frequency curve is calculated based on the Laplace frequency transformation relationship. Perform the transformation to obtain the corresponding formula between impedance and frequency, and then combine the data points on the PDN impedance-frequency curve to use the least squares method to fit the parameters a1, a2, b1, and b2 of the second-order impedance network transfer function formula.

5. The on-chip voltage prediction circuit based on power transmission network parameters according to any one of claims 1 to 4, characterized in that: The on-chip voltage prediction formula obtained by quantifying the on-chip PDN parameters is V dp [n] = c1 * I d [n]+c2*I d [n-1]+c3*I d [n-2]-d1*V dn [n-1]-d2*V dn [n-2], where V dp [n] is the voltage prediction at time n, I d [n] is the predicted current at time n, I d [n-1] is the predicted current at time n-1, I d [n-2] is the predicted current at time n-2, V dn [n-1] is the on-chip voltage monitoring value at time n-1, V dn [n-2] is the on-chip voltage monitoring value at time n-2, and c1, c2, c3, d1, and d2 are based on the bilinear transformation formula: The parameters of the transfer function obtained by converting the second-order impedance network transfer function formula to the discrete z domain are: T is a system clock cycle.

6. The on-chip voltage prediction circuit based on power transmission network parameters according to claim 1, characterized in that: The on-chip PDN impedance scanning module includes: a configuration module for controlling the activation of each ring oscillator circuit in the artificial current load module; and The artificial current load module includes a configurable number of ring oscillator circuits, which simulate currents of different frequencies on the load under the control of the configuration module.

7. The on-chip voltage prediction circuit based on power transmission network parameters according to claim 1, characterized in that: The on-chip voltage monitoring module includes: A voltage-controlled oscillator, used to map changes in on-chip voltage at different frequency currents to device delay changes; A code value sampling module, used to sample the position of the signal flip on the voltage controlled oscillator; and The quantization logic module is used to count the position of the signal flip on the voltage-controlled oscillator at the beginning of the sampling period, the position of the signal flip on the voltage-controlled oscillator at the end of the sampling period, and the total number of oscillations within a system clock period T, and output the historical voltage code value.

8. The on-chip voltage prediction circuit based on power transmission network parameters according to claim 1, characterized in that: The on-chip predictive digital power meter comprises: A signal flip monitoring module deployed in each processor system is used to monitor the flip status of key signals in the processor system and output the flip monitoring results of the key signals in the processor system to the current calculation module in the processor system; A current calculation module deployed in each processor system is used to multiply the flip monitoring results of the key signals in the processor system by the corresponding weights through a multiplier to obtain the current corresponding to the flip of each key signal, and to add the current corresponding to the flip of each key signal through an addition tree to obtain the current value corresponding to the flip of the key signal on the processor system; and The current correction module is used to add the current value corresponding to the key signal flip on each processor system and the current value on the clock tree to obtain the current of each processor, and add the current of the processors with valid clocks to obtain the predicted current code value.

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