Photoelectric device, light-emitting module, and electronic device

Abstract

The present application discloses a photoelectric device, a light-emitting module, and an electronic device. The photoelectric device (10) comprises a plurality of light-emitting pixels (200), a trench region (400), and an electrode metal layer (230); the electrode metal layer (230) is used for being electrically connected to a second electrode; the trench region comprises a first trench portion (401) and a second trench portion (402); the electrode metal layer (230) covers at least part of the surface of each light-emitting pixel (200), at least part of the region of the first trench portion (401), and at least part of the region of the second trench portion (402). In this way, the line width of the electrode metal layer (230) is not limited by the size of the first trench portion (401), so that the electrode metal layer (230) meets a current expansion requirement, and the current uniformity of the light-emitting pixels is improved. In addition, the electrode metal layer (230) in the first trench portion (401) is insulated from a semiconductor functional layer (210), so that it is not needed to reserve a large region for the first trench portion (401), thereby greatly reducing the occupation of an active light-emitting region in the light-emitting pixel (200) by the first trench portion (401), and increasing the area of the active light-emitting region.

Description

Photoelectric device, light-emitting module and electronic equipment

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on February 8, 2024, with application number 202410178180.6 and application name “A photoelectric device, light-emitting module, preparation method and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of light emitting technology, and in particular to a photoelectric device, a light emitting module and an electronic device. Background Art

[0004] Light-emitting diodes (LEDs) have advantages such as long life, high brightness, and low power consumption, and are widely used in display, lighting, and projection applications. Typically, multiple LEDs are combined to form a photoelectric device. The electrodes of the LEDs in the device are connected to corresponding pins on a driver device, which then drives the LEDs to emit light. Summary of the Invention

[0005] The embodiments of the present application provide an optoelectronic device, a light-emitting module, and an electronic device for forming an optoelectronic device with high-density light-emitting pixels.

[0006] In a first aspect, an embodiment of the present application provides an optoelectronic device, comprising: a plurality of light-emitting pixels, a groove region, and an electrode metal layer, wherein each light-emitting pixel comprises a semiconductor functional layer and a first electrode, each semiconductor functional layer comprises a first semiconductor layer, and the plurality of light-emitting pixels share the first semiconductor layer. The groove region is formed in the semiconductor functional layer, the groove region is located between the plurality of light-emitting pixels, and the electrode metal layer is used to electrically connect to the second electrode. Furthermore, the groove region comprises a first groove portion and a second groove portion, and the electrode metal layer covers at least a portion of the surface of each light-emitting pixel, at least a portion of the first groove portion, and at least a portion of the second groove portion. The electrode metal layer is insulated from the semiconductor functional layer in the first groove portion, and the electrode metal layer is electrically connected to the first semiconductor layer in the second groove portion.

[0007] Since the second electrode in the prior art usually adopts a metal grid line, the width of the groove area needs to be relatively large. In the embodiment of the present application, by providing an electrode metal layer connected to the second electrode and electrically connecting the electrode metal layer to the first semiconductor layer in the second groove portion, the voltage in the second electrode can be input into the first semiconductor layer in each light-emitting pixel through the electrode metal layer, thereby powering the first semiconductor layer in each light-emitting pixel and reducing the number of interconnection points. In addition, by making the electrode metal layer cover not only at least a portion of the area of ​​the first groove portion, but also at least a portion of the surface of each light-emitting pixel and at least a portion of the area of ​​the second groove portion, the line width of the electrode metal layer is not limited by the size of the first groove portion, the conductive area of ​​the electrode metal layer can be increased, the voltage drop of the electrode metal layer can be reduced, and the electrode metal layer can be made to withstand a higher current, so that the electrode metal layer meets the requirements of current expansion and improves the current uniformity of the light-emitting pixel. In addition, by insulating the electrode metal layer from the semiconductor functional layer in the first groove portion, that is, the electrode metal layer in the first groove portion does not need to contact the first semiconductor layer, so that there is no need to reserve a large area for the first groove portion, but it is only necessary to enable the first groove portion to achieve isolation between the light-emitting pixels, thereby compressing the width of the first groove portion, which can greatly reduce the occupation of the first groove portion on the active light-emitting area in the light-emitting pixel and increase the area of ​​the active light-emitting area.

[0008] In addition, in general, the metal layer has strong light absorption. If a large area of ​​the metal layer contacts the first semiconductor layer, light will be absorbed by the metal layer through the first semiconductor layer, reducing the luminous efficiency of the device. In the embodiment of the present application, the electrode metal layer is insulated from the semiconductor functional layer in the first groove portion, and the electrode metal layer contacts the first semiconductor layer in the second groove portion to achieve electrical connection. Compared with the prior art in which all the electrode metal layers in the groove area need to contact the first semiconductor layer, in the embodiment of the present application, the area ratio of the electrode metal layer in direct contact with the first semiconductor layer can be reduced, thereby reducing the absorption of light by the electrode metal layer and improving the luminous efficiency of the device.

[0009] In some embodiments, the sidewalls of the trench region having the second trench portion have a first dimension, and the sidewalls of the trench region having the first trench portion have a second dimension, with the maximum of the first dimensions being larger than the maximum of the second dimensions. This arrangement can reduce the size of the first trench portion in the trench region while leaving a certain amount of space in the trench region for the second trench portion, thereby increasing the electrical connection area between the electrode metal layer and the first semiconductor layer and improving power supply reliability.

[0010] In some embodiments, the first groove portion is located between adjacent light-emitting pixels, and the first groove portion also surrounds and communicates with the second groove portion. In this configuration, the electrode metal layer can extend in the first groove portion and the second groove portion.

[0011] In some embodiments, the groove region is arranged in a grid pattern, and at least some of the grid intersections in the grid pattern are provided with second groove portions. Thus, by providing the second groove portions at the grid intersections, all grid lines can be provided as first groove portions. The width of the first groove portions provided at the grid lines can then be compressed, thereby expanding the area of ​​the active light-emitting area.

[0012] In some embodiments, the groove region is in a grid pattern, and the second groove portion is disposed on at least some of the grid lines in the grid pattern.

[0013] In some embodiments, the first trench portion accounts for greater than or equal to 50% of the trench region, and the first trench portion accounts for less than 100% of the trench region.

[0014] In some embodiments, the proportion of the second trench portion in the trench region is greater than 0, and the proportion of the second trench portion in the trench region is less than or equal to 50%.

[0015] In some embodiments, the electrode metal layer covers at least a portion of the bottom wall of the first trench portion. Exemplarily, the electrode metal layer covers the entire bottom wall of the first trench portion, thereby increasing the area of ​​the electrode metal layer as much as possible and improving current uniformity.

[0016] In some embodiments, the electrode metal layer covers at least a portion of the bottom wall of the second groove portion. Exemplarily, the electrode metal layer covers the entire bottom wall of the second groove portion, thereby increasing the area of ​​the electrode metal layer as much as possible and improving current uniformity.

[0017] In some embodiments, the portion of the electrode metal layer extending from the first groove portion to the second groove portion forms a step shape, which can reduce the risk of fracture of the electrode metal layer and improve reliability.

[0018] In some embodiments, a first dielectric layer is disposed between the electrode metal layer and the bottom wall of the first trench portion. Thus, the first dielectric layer insulates the electrode metal layer from the bottom wall of the first trench portion. Furthermore, by reusing the first dielectric layer and elevating the electrode metal layer, the electrode metal layer can be extended along the first dielectric layer to the bottom wall of the second trench portion, thereby forming a stepped portion of the electrode metal layer extending from the first trench portion to the second trench portion.

[0019] In some embodiments, the first semiconductor layer is protruded in areas corresponding to the light-emitting pixels, and the first semiconductor layers of adjacent light-emitting pixels are recessed to form a trench region. Furthermore, the first semiconductor layer between adjacent light-emitting pixels forms the bottom wall of the trench region, and the sidewalls of the protruding areas of the first semiconductor layer form at least a portion of the sidewalls of the trench region. Thus, the protruding first semiconductor layers in different light-emitting pixels can be separated by the trench region, i.e., a groove is formed in the shared first semiconductor layer to serve as part of the trench region.

[0020] In some embodiments, the semiconductor functional layer further includes a light-emitting layer and a second semiconductor layer. The light-emitting layer is disposed on the protruding first semiconductor layer, and the second semiconductor layer is disposed on the light-emitting layer. The first electrode is electrically connected to the second semiconductor layer. Furthermore, the sidewalls of the protruding region of the first semiconductor layer, the sidewalls of the light-emitting layer, and the sidewalls of the second semiconductor layer form the sidewalls of the groove region, that is, the groove completely isolates the light-emitting layer and the second semiconductor layer between adjacent pixels. With this arrangement, the groove region can be used to separate the light-emitting layer and the second semiconductor layer in different light-emitting pixels.

[0021] In some embodiments, the electrode metal layer covers the sidewalls of the first semiconductor layer, the sidewalls of the light-emitting layer, and the sidewalls of the second semiconductor layer, and a second dielectric layer is disposed between the electrode metal layer and the sidewalls of the first semiconductor layer, the sidewalls of the light-emitting layer, and the sidewalls of the second semiconductor layer. This configuration further increases the area of ​​the electrode metal layer and improves current uniformity.

[0022] In some embodiments, the luminescent pixel further includes a current spreading layer disposed on the second semiconductor layer. The second dielectric layer also covers the sidewalls of the current spreading layer. The electrode metal layer also covers the second dielectric layer on the sidewalls of the current spreading layer. This arrangement further increases the area of ​​the electrode metal layer and improves current uniformity.

[0023] In some embodiments, the surface of the current spreading layer facing away from the second semiconductor layer is a first surface. The electrode metal layer extends to cover the first surface and encloses a second contact hole on the first surface. The second dielectric layer extends to cover the first surface and encloses a third contact hole inside the second contact hole. Furthermore, the first electrode is electrically connected to the second semiconductor layer through the second and third contact holes, and the first electrode is insulated from the electrode metal layer.

[0024] In some embodiments, the portion of the electrode metal layer extending from the sidewall of the second semiconductor layer to the first surface forms a double-step shape, which can reduce the risk of fracture of the electrode metal layer and improve reliability.

[0025] In some embodiments, the second semiconductor layer has a first region and a second region on a surface facing away from the light-emitting layer. The first region surrounds the second region, and the current spreading layer covers the second region. Furthermore, the second dielectric layer also covers the first region, and the electrode metal layer also covers the second dielectric layer located above the first region. This arrangement allows the electrode metal layer to extend along the sidewalls of the second semiconductor layer to the portion of the first surface, forming a stepped shape. Furthermore, the area of ​​the electrode metal layer can be further increased, thereby improving current uniformity.

[0026] In some embodiments, the first electrode includes a first electrode connection layer and a first electrode pad layer connected to each other, the first electrode connection layer is arranged between the first electrode pad layer and the current spreading layer, and the first electrode connection layer is connected to the current spreading layer through the second contact hole and the third contact hole.

[0027] In some embodiments, in the stacking direction of the light-emitting layer and the second semiconductor layer, a distance between an outer boundary of the first electrode connection layer and an outer boundary of the second contact hole is greater than zero. In the stacking direction of the light-emitting layer and the second semiconductor layer, the first electrode connection layer covers the second contact hole, or in the stacking direction of the light-emitting layer and the second semiconductor layer, the first electrode connection layer is disposed within the second contact hole.

[0028] In some embodiments, in the stacking direction of the light emitting layer and the second semiconductor layer, the first electrode pad layer covers the second contact hole, and a passivation layer is provided between the first electrode pad layer and the electrode metal layer, thereby achieving an insulating setting.

[0029] In some embodiments, the cross-section of the first electrode connection layer in the stacking direction of the light-emitting layer and the second semiconductor layer has a first groove, and a portion of the first electrode pad layer fills the first groove. This configuration embeds a portion of the first electrode pad layer in the first groove, forming a stepped pad and improving reliability.

[0030] In some embodiments, the optoelectronic device further comprises: one or more boss structures, each boss structure having a second surface, with a second electrode disposed on the second surface. This configuration elevates the second electrode via the boss structure, and when the first electrode and the second electrode are interconnected to the driver device using the interconnect structure, the length difference between the interconnect structure connected to the first electrode and the interconnect structure connected to the second electrode can be minimized, thereby reducing the risk of device failure and improving the reliability of the interconnection between the optoelectronic device and the driver device.

[0031] In some embodiments, a groove region is further provided between the platform structure and the light-emitting pixel. For example, the groove structure provided between the platform structure and the light-emitting pixel may include only the first groove portion, the second groove portion, or both. This arrangement can further increase the area of ​​the electrode metal layer and improve the current uniformity of the light-emitting pixel.

[0032] In some embodiments, when multiple platform structures are provided, a groove region is further provided between the platform structures. For example, the groove structure provided between the platform structures may include only the first groove portion, the second groove portion, or both. This arrangement can further increase the area of ​​the electrode metal layer and improve the current uniformity of the light-emitting pixel.

[0033] In some embodiments, the electrode metal layer also covers the sidewalls of the boss structure. This arrangement can further increase the area of ​​the electrode metal layer and improve the current uniformity of the light-emitting pixel.

[0034] In some embodiments, the second electrode includes a second electrode connection layer and a second electrode pad layer that are interconnected, with the second electrode connection layer disposed between the second electrode pad layer and the platform structure. Furthermore, the second electrode connection layer covers at least a portion of the second surface, and the electrode metal layer and the second electrode connection layer are interconnected. This arrangement further increases the area of ​​the second electrode connection layer, improving current uniformity.

[0035] In some embodiments, a third dielectric layer is disposed between the second electrode connection layer and the platform structure, covering the sidewalls of the platform structure. Furthermore, the third dielectric layer extends to the second surface and encloses a fourth contact hole on the second surface. The second electrode connection layer covers the third dielectric layer and contacts the second surface through the fourth contact hole. Alternatively, the third dielectric layer covers the second surface, and the second electrode connection layer covers the third dielectric layer. This arrangement allows the second electrode connection layer on the second surface to have a structure as identical as possible to the first electrode connection layer on the first surface.

[0036] In some embodiments, the boss structure is a single-layer structure, and the boss structure includes: a semiconductor material layer, an insulating material layer, or a metal material layer.

[0037] In some embodiments, the mesa structure is a multi-layer structure, and the mesa structure includes a combination of a semiconductor material layer, an insulating material layer, or a metal material layer.

[0038] In some embodiments, the platform structure is a multi-layer structure, and the platform structure includes a semiconductor functional layer. This arrangement allows the platform structure to be formed when the semiconductor functional layer is formed, which not only minimizes the difference between the platform structure and the semiconductor functional layer but also reduces the number of manufacturing steps.

[0039] In some embodiments, the platform structure is a multilayer structure, and includes a semiconductor functional layer and a current spreading layer disposed on the semiconductor functional layer. This arrangement allows the platform structure to be formed simultaneously with the semiconductor functional layer and the current spreading layer. This not only minimizes the difference between the platform structure and the semiconductor functional layer and the current spreading layer, but also reduces the number of manufacturing steps.

[0040] In some embodiments, the luminescent pixel further includes a distributed Bragg reflector layer disposed between the electrode metal layer and the second dielectric layer, thereby improving reflection efficiency.

[0041] In a second aspect, an embodiment of the present application further provides an optoelectronic device comprising: a plurality of light-emitting pixels, a groove region, and a first reflective layer, wherein each light-emitting pixel comprises a semiconductor functional layer and a first electrode, and each semiconductor functional layer comprises a first semiconductor layer arranged in a stacked manner. Furthermore, the first reflective layer covers at least a portion of each light-emitting pixel and also covers at least a portion of the groove region. Furthermore, the first electrode is insulated from the first reflective layer so that the first electrode inputs a first voltage to the second semiconductor layer. Thus, the first reflective layer is used to reflect as much light as possible emitted from the semiconductor functional layer toward its sidewalls and the first electrode to the light-emitting surface, thereby improving the light extraction efficiency of the device.

[0042] Furthermore, the remaining structures of the optoelectronic devices of each embodiment of the second aspect may refer to the description of the relevant structures of each embodiment of the first aspect, and will not be described in detail here. It is worth mentioning that the various implementation methods of each embodiment of the second aspect may not rely on the implementation methods of the first aspect, and may also be other achievable methods, which are not specifically limited here.

[0043] In a third aspect, embodiments of the present application further provide an optoelectronic device comprising: a plurality of light-emitting pixels, a groove region, and an electrode metal layer, wherein each light-emitting pixel comprises a semiconductor functional layer and a first electrode, each semiconductor functional layer comprising a stacked first semiconductor layer, a light-emitting layer, and a second semiconductor layer, the second semiconductor layer being electrically connected to the first electrode, and the electrode metal layer being electrically connected to the second electrode. Furthermore, a groove region is formed in the semiconductor functional layer, and the groove region can be used to isolate the plurality of light-emitting pixels from one another. The groove region can include a first groove portion and a second groove portion, and the electrode metal layer covers at least a portion of the surface of each light-emitting pixel, at least a portion of the first groove portion, and at least a portion of the second groove portion. Furthermore, the electrode metal layer is insulated from the semiconductor functional layer in the first groove portion, and electrically connected to the first semiconductor layer in the second groove portion. Furthermore, a first dielectric layer is disposed between the electrode metal layer and the bottom wall of the first groove portion. Furthermore, the portion of the electrode metal layer extending from the first dielectric layer to the bottom wall of the second groove portion is stepped, thereby reducing the risk of fracture of the electrode metal layer and improving reliability.

[0044] Furthermore, the remaining structures of the optoelectronic devices of each embodiment of the third aspect may refer to the description of the relevant structures of each embodiment of the first aspect or the second aspect, and the details are not repeated here. It is worth mentioning that the various implementation methods of each embodiment of the third aspect may not rely on the implementation methods of the first aspect or the second aspect, and may also be other achievable methods, which are not specifically limited here.

[0045] In a fourth aspect, an embodiment of the present application further provides a light-emitting module, which includes: an optoelectronic device, a driver device, and an interconnection component. The driver device is located on a side of the optoelectronic device having multiple light-emitting pixels, and the driver device includes a first drive pad and a second drive pad. In addition, the interconnection component is located between the optoelectronic device and the driver device, and the interconnection component includes a first interconnection structure and a second interconnection structure, wherein the first end of the first interconnection structure is connected to the first electrode, the second end of the first interconnection structure is connected to the first drive pad, the first end of the second interconnection structure is connected to the second electrode, and the second end of the second interconnection structure is connected to the second drive pad.

[0046] The optoelectronic device is the optoelectronic device of the first aspect or any embodiment thereof. Alternatively, the optoelectronic device is the optoelectronic device of the second aspect or any embodiment thereof. Alternatively, the optoelectronic device is the optoelectronic device of the third aspect or any embodiment thereof.

[0047] In some embodiments, an underfill layer is further provided between the optoelectronic device and the driver device. Specifically, the interconnection components are disposed within the underfill layer. The underfill layer protects the optoelectronic device, the interconnection components, and the driver device, further improving the reliability of the light-emitting module and preventing stress damage. Exemplarily, the underfill layer comprises a polymer material and filler particles. The polymer material includes, but is not limited to, resin, and the filler material includes, but is not limited to, SiO2, TiO2, and the like.

[0048] In a fifth aspect, embodiments of the present application further provide an electronic device comprising a circuit board and a light-emitting module, wherein the circuit board is connected to a driver device in the light-emitting module, wherein the light-emitting module is the optoelectronic device in the fourth aspect or any embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] FIG1 is a schematic structural diagram of an electronic device in an embodiment of the present application;

[0050] FIG2a is a schematic diagram of a top view of a photoelectric device provided in an embodiment of the present application;

[0051] FIG2b is a top view of the groove region shown in FIG2a;

[0052] FIG2 c is another top view of the groove region in an embodiment of the present application;

[0053] FIG3a is a schematic cross-sectional view of the structure along the AA′ direction in FIG2a;

[0054] FIG3b is a schematic cross-sectional view of the structure along the BB' direction in FIG2a;

[0055] FIG3c is a schematic cross-sectional view of the structure along the CC' direction in FIG2a;

[0056] 4a to 4d are schematic diagrams of equivalent structures of a grid pattern provided in an embodiment of the present application;

[0057] 5a to 5g are schematic cross-sectional views of a photoelectric device during the preparation process according to an embodiment of the present application;

[0058] FIG6 a is a schematic diagram of another top view of the optoelectronic device provided in an embodiment of the present application;

[0059] FIG6 b is a top view of the groove region shown in FIG6 a ;

[0060] FIG6 c is another top view of the groove region in an embodiment of the present application;

[0061] FIG7 is a schematic cross-sectional view of the structure along the AA′ direction in FIG6a;

[0062] FIG8 is a schematic top view of another structure of an optoelectronic device provided in an embodiment of the present application;

[0063] FIG9 is a schematic cross-sectional view of the structure along the AA′ direction in FIG8 ;

[0064] 10a to 10e illustrate an arrangement of light-emitting pixels and boss structures in an embodiment of the present application;

[0065] 11a to 11g are schematic cross-sectional views of another embodiment of the optoelectronic device during the preparation process;

[0066] FIG12 is another schematic cross-sectional view of the structure along the AA′ direction in FIG8 ;

[0067] FIG13 is another schematic cross-sectional view of the structure along the AA′ direction in FIG8 ;

[0068] FIG14 is another schematic cross-sectional view of the structure along the AA′ direction in FIG8 ;

[0069] FIG15 is a schematic diagram of another top view of the optoelectronic device provided in an embodiment of the present application;

[0070] FIG16 is another schematic cross-sectional view of the structure along the AA′ direction in FIG15 ;

[0071] FIG17 is a schematic diagram of another top view of the optoelectronic device provided in an embodiment of the present application;

[0072] FIG18a is a schematic cross-sectional view of the structure along the AA′ direction in FIG17;

[0073] FIG18b is another schematic cross-sectional view of the structure along the AA′ direction in FIG17;

[0074] FIG19 is a schematic diagram of another top view of the optoelectronic device provided in an embodiment of the present application;

[0075] FIG20 is a schematic cross-sectional view of the structure along the AA′ direction in FIG19 ;

[0076] FIG21 is a schematic diagram of another top view of the optoelectronic device provided in an embodiment of the present application;

[0077] FIG22 is a schematic cross-sectional view of the structure along the AA′ direction in FIG21 ;

[0078] FIG23 is a schematic structural diagram of a light-emitting module provided in an embodiment of the present application;

[0079] FIG24 is a schematic diagram of another structure of a light-emitting module provided in an embodiment of the present application;

[0080] FIG25 is a schematic top view of another structure of an optoelectronic device provided in an embodiment of the present application;

[0081] FIG26a is a schematic cross-sectional view of the structure along the AA′ direction in FIG25 ;

[0082] FIG26b is a schematic cross-sectional view of the structure along the BB' direction in FIG25;

[0083] FIG26c is a schematic cross-sectional view of the structure along the CC' direction in FIG25;

[0084] FIG27 is a schematic diagram of another top view of the optoelectronic device provided in an embodiment of the present application;

[0085] FIG28a is a schematic cross-sectional view of the structure along the AA′ direction in FIG27;

[0086] FIG28b is a schematic cross-sectional view of the structure along the BB' direction in FIG27;

[0087] FIG28c is a schematic diagram of the cross-sectional structure along the CC' direction in FIG27.

[0088] Reference numerals

[0089] 1-light-emitting module; 2-circuit board; 10-optoelectronic device; 20-interconnection assembly; 21-first interconnection structure; 22-second interconnection structure; 30-driver; 31-first driver pad; 32-second driver pad; 100-substrate; 200-light-emitting pixel; 210-semiconductor functional layer; 211-first semiconductor layer; 212-light-emitting layer; 213-second semiconductor layer; 214-current spreading layer; 220-first electrode; 221-first electrode connection layer; 222-first electrode pad layer; 230-electrode metal layer; 240-passivation layer; 250-buffer layer; 322-first dielectric layer; 321-second dielectric layer; 330-contact through hole; 332-second contact hole; 333-third contact hole; 334-fourth contact hole; 400-groove region; 401-first groove portion; 402-second groove portion; 411-first intersection region; 412-second intersection region; 420-grid pattern; 510-boss structure; 520-second electrode; 521-second electrode connection layer; 522-second electrode pad layer; 610 / 812-distributed Bragg reflection layer; 710-first protrusion structure; 720-second protrusion structure; 810-first reflection layer; 811-first metal layer; 820-second reflection layer; 821-second metal layer; 830-contact electrode; 910-bottom fill structure layer; S1-first surface; S2-second surface; F0-vertical direction; F1-first direction; F2-second direction; Y221 / Y332-outer boundary; AX1-first groove; AX2-second groove; AC-recess; h1-first vertical distance; h2-second vertical distance. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operating methods in the method embodiments can also be applied to device embodiments or system embodiments. It is worth mentioning that in the description of the present application, "multiple" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used to distinguish the purpose of description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0091] It should be noted that the same reference numerals in the drawings of this application represent the same or similar structures, and thus their repeated description will be omitted. The words expressing positions and directions described in this application are all explained using the drawings as examples, but they can be modified as needed, and such modifications are included in the scope of protection of this application. The drawings of this application are only for illustrative purposes and do not represent true proportions.

[0092] FIG1 is a structural diagram of an electronic device in an embodiment of the present application. Referring to FIG1 , the electronic device includes: a circuit board 2 and a light-emitting module 1. The light-emitting module 1 includes a photoelectric device 10, an interconnection component 20, and a driver 30. The interconnection component 20 is located between the photoelectric device 10 and the driver 30, and the photoelectric device 10 is connected to the driver 30 through the interconnection component 20, thereby realizing signal transmission between the photoelectric device 10 and the driver 30. In addition, the driver 30 is connected to the circuit board 2 to realize signal transmission between the driver 30 and the circuit board 2, thereby realizing driving the photoelectric device 10 to emit light. Exemplarily, the circuit board 2 includes but is not limited to a printed circuit board (PCB).

[0093] The electronic device in this application can be a light-emitting device used in different scenarios. For example, the electronic device includes but is not limited to applications in the following fields: display field, lighting field, projection field, car field, detection field, etc. For example, the electronic device can be applied to the display field, the electronic device can be set as a display device, the display device includes, for example, a smart phone, a smart watch, a tablet computer, a car display, a large-size display, etc., then the light-emitting module can be used as a display screen in the display device or as a backlight module of a liquid crystal display. Alternatively, the display device includes, for example, an augmented reality (AR) device, a virtual reality (VR) device, etc., then the light-emitting module can be used as a bottom light source, and the light emitted by the light-emitting module passes through a digital light processor (DLP) or a silicon-based liquid crystal (LCOS) and then passes through an optical waveguide for imaging. For example, the electronic device can also be applied to the projection field, the electronic device can be set as a projection device, then the light-emitting module can be used as a bottom light source, and the light emitted by the light-emitting module passes through a silicon-based liquid crystal (LCOS) and then passes through an optical waveguide for imaging. For example, electronic devices can also be used in the field of lighting (such as the field of digital lighting), and the electronic device can be set as a lamp, and the light-emitting module can be used as the light source of the lamp. For example, electronic devices can also be used in the field of cars, and the electronic device can be set as a smart car light, and the light-emitting module can be used as the light source of the smart car light. The light-emitting module can be bonded with a complementary metal oxide semiconductor (CMOS) to achieve pixelated control of the lighting area. For example, electronic devices can also be used in the field of detection, and the electronic device can be set as a photodetector (such as an ultraviolet photodetector). It is understandable that the specific implementation of the electronic device can be determined according to the actual application scenario, and they are not listed here one by one.

[0094] The optoelectronic device provided in the embodiment of the present application will be described in detail below with reference to the first embodiment.

[0095] Example 1:

[0096] In practical applications, optoelectronic devices can be formed using multiple light-emitting pixels. Typically, each light-emitting pixel includes a semiconductor functional layer, a positive electrode, and a negative electrode. The positive electrode and negative electrode are usually arranged on the same side of the semiconductor function, and the positive electrode and negative electrode of each light-emitting pixel are interconnected with the positive electrode solder pin and the negative electrode solder pin of the driver device, respectively, resulting in a large number of interconnection points and increasing the difficulty of the process. To this end, metal grid lines are arranged in the groove area 400 between the semiconductor functional layers of each light-emitting pixel, and the metal grid lines are in contact with the N-type semiconductor layer in the semiconductor functional layer of each light-emitting pixel. The metal grid lines are used to power the N-type semiconductor layer of each light-emitting pixel. During the process preparation, in order to enable the metal grid lines to contact the N-type semiconductor layer in the groove area 400, the groove area 400 needs to have a certain width. Moreover, based on the current expansion requirements of the metal grid lines, the metal grid lines need to have a certain metal line width, which further increases the width of the groove area 400 (usually the width of the groove area 400 can reach 5um to 10um), thereby causing the active light-emitting area of ​​the light-emitting pixel to be largely occupied by the groove area 400, thereby reducing the area of ​​the active light-emitting area of ​​the light-emitting pixel.

[0097] To this end, embodiments of the present application provide an optoelectronic device that significantly reduces the amount of active light-emitting area of ​​a pixel occupied by the trench region 400, thereby increasing the active light-emitting area of ​​the pixel. Furthermore, the conductive area of ​​the electrode metal layer 230 is increased to meet current expansion requirements, thereby enabling the electrode metal layer 230 to withstand higher currents.

[0098] FIG2a is a schematic diagram of a top view of the optoelectronic device provided in an embodiment of the present application, FIG2b is a top view of the groove region shown in FIG2a, FIG2c is another top view of the groove region in an embodiment of the present application, FIG3a is a schematic diagram of a cross-sectional structure along the AA' direction in FIG2a, FIG3b is a schematic diagram of a cross-sectional structure along the BB' direction in FIG2a, and FIG3c is a schematic diagram of a cross-sectional structure along the CC' direction in FIG2a. Referring to FIG2a to FIG3c, the optoelectronic device 10 includes: a plurality of light-emitting pixels 200, a groove region 400, and an electrode metal layer 230, wherein each light-emitting pixel 200 includes a semiconductor functional layer 210 and a first electrode 220, each semiconductor functional layer 210 includes a first semiconductor layer 211, a light-emitting layer 212, and a second semiconductor layer 213 arranged in a stacked manner, the second semiconductor layer 213 is electrically connected to the first electrode 220, and the electrode metal layer 230 is electrically connected to the second electrode (not shown in FIG2a).

[0099] Furthermore, a trench region 400 is formed in the semiconductor functional layer 210 and may be located between a plurality of light-emitting pixels 200. The trench region 400 may include a first trench portion 401 and a second trench portion 402. The electrode metal layer 230 covers at least a portion of the surface of each light-emitting pixel 200, at least a portion of the first trench portion 401, and at least a portion of the second trench portion 402. Furthermore, the electrode metal layer 230 is insulated from the semiconductor functional layer in the first trench portion 401 and electrically connected to the first semiconductor layer 211 in the second trench portion 402.

[0100] Since the second electrode in the prior art typically utilizes metal grid lines, the width of the groove region 400 needs to be relatively large. In the embodiment of the present application, by providing an electrode metal layer 230 connected to the second electrode and electrically connecting the electrode metal layer 230 to the first semiconductor layer 211 in the second groove portion 402, the voltage of the second electrode can be input to the first semiconductor layer 211 in each light-emitting pixel through the electrode metal layer 230, thereby powering the first semiconductor layer 211 in each light-emitting pixel and reducing the number of interconnection points. Furthermore, by ensuring that the electrode metal layer 230 covers not only at least a portion of the first groove portion 401 but also at least a portion of the surface of each light-emitting pixel 200 and at least a portion of the second groove portion 402, the line width of the electrode metal layer 230 is not limited by the size of the first groove portion 401. This increases the conductive area of ​​the electrode metal layer 230, reduces the voltage drop across the electrode metal layer 230, and enables the electrode metal layer 230 to withstand higher currents, thereby meeting the current spreading requirements and improving the current uniformity of the light-emitting pixels. Furthermore, by insulating the electrode metal layer 230 from the semiconductor functional layer in the first groove portion 401, that is, the electrode metal layer 230 in the first groove portion 401 does not need to contact the first semiconductor layer 211, there is no need to reserve a large area for the first groove portion 401. Instead, it is only necessary to enable the first groove portion 401 to achieve isolation between the luminous pixels, thereby compressing the width of the first groove portion 401, which can greatly reduce the occupation of the first groove portion 401 on the active light-emitting area in the light-emitting pixel, thereby increasing the area of ​​the active light-emitting area.

[0101] In addition, in general, the metal layer has strong light absorption. If a large area of ​​the metal layer contacts the first semiconductor layer 211, light will be absorbed by the metal layer through the first semiconductor layer 211, reducing the luminous efficiency of the device. In the embodiment of the present application, the electrode metal layer 230 is insulated from the semiconductor functional layer in the first groove portion 401, and the electrode metal layer 230 contacts the first semiconductor layer 211 in the second groove portion 402 to achieve electrical connection. Compared with the prior art in which the entire electrode metal layer 230 in the groove area 400 needs to contact the first semiconductor layer 211, in the embodiment of the present application, the area ratio of the electrode metal layer 230 in direct contact with the first semiconductor layer 211 can be reduced, thereby reducing the absorption of light by the electrode metal layer 230 and improving the luminous efficiency of the device.

[0102] Continuing with reference to Figures 2a to 3c, the plurality of light-emitting pixels 200 share a common first semiconductor layer 211. For example, the first semiconductor layer 211 is a film layer laid over the entire surface, and the areas of the first semiconductor layer 211 corresponding to the light-emitting pixels 200 are protruding, while the first semiconductor layers 211 of adjacent light-emitting pixels 200 are recessed to form a groove region 400. That is, the first semiconductor layer 211 has a protruding portion, and the protruding portion is disposed in the area where the light-emitting pixels 200 are located. The first semiconductor layer 211 between adjacent light-emitting pixels 200 forms the bottom wall of the groove region 400, and the sidewalls of the protruding areas of the first semiconductor layer 211 form at least part of the sidewalls of the groove region 400. Thus, the protruding first semiconductor layers 211 located in different light-emitting pixels can be separated by the groove region 400.

[0103] Furthermore, the light-emitting layer 212 is located on the protruding portion, and the second semiconductor layer 213 is disposed on the light-emitting layer 212. Thus, the sidewalls of the protruding region of the first semiconductor layer 211, the sidewalls of the light-emitting layer 212, and the sidewalls of the second semiconductor layer 213 form the sidewalls of the groove region 400. With this arrangement, the groove region 400 can be used to separate the light-emitting layer 212 and the second semiconductor layer 213 in different light-emitting pixels 200.

[0104] In some embodiments of the present application, the first semiconductor layer 211 is an N-type semiconductor layer and the second semiconductor layer 213 is a P-type semiconductor layer. The first electrode 220 can be set as the positive electrode and the second electrode can be set as the negative electrode. The second semiconductor layer 213 is electrically connected to the first electrode 220, the first semiconductor layer 211 in the semiconductor functional layer 210 is electrically connected to the electrode metal layer 230, and the electrode metal layer 230 is electrically connected to the second electrode. Based on this, a first voltage is transmitted to the second semiconductor layer 213 through the first electrode 220, and a second voltage is transmitted to the first semiconductor layer 211 through the second electrode and the electrode metal layer 230, thereby driving the light-emitting layer 212 to emit light, so that the light-emitting pixel 200 emits light. In some other embodiments of the present application, the first semiconductor layer 211 can also be a P-type semiconductor layer and the second semiconductor layer 213 can be an N-type semiconductor layer, which is not limited here.

[0105] The first semiconductor layer 211 can have a single-layer structure, for example, comprising a GaN layer or an AlGaN layer. Alternatively, the first semiconductor layer 211 can have a multi-layer structure, for example, comprising a combination of a GaN layer and an AlGaN layer, wherein a GaN layer and an AlGaN layer are alternately stacked, or multiple GaN layers and multiple AlGaN layers are alternately stacked. For example, the Al content in the first semiconductor layer 211 is 0% to 30%, for example, 0%, 5%, 10%, 15%, 20%, 25%, 30%, etc., without limitation herein. Furthermore, the thickness of the first semiconductor layer 211 is 200nm to 5um, for example, 200nm, 500nm, 1um, 1.5um, 2um, 2.5um, 3um, 3.5um, 4um, 4.5um, 5um, etc., without limitation herein.

[0106] The light-emitting layer 212 is a multilayer structure. For example, the light-emitting layer 212 can be a combination of two or three of an InGaN layer, a GaN layer, and an AlGaN layer, and any stacking thereof. Exemplarily, the In component content in the light-emitting layer 212 is 0% to 50%, for example, the In component content is 0%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc., which is not limited here. And, the Al component content is 0% to 50%, for example, the Al component content is 0%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, etc., which is not limited here. Also, the thickness of the light emitting layer 212 is 50 nm to 500 nm. For example, the thickness of the light emitting layer 212 is 50 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, etc., which is not limited here.

[0107] The second semiconductor layer 213 can be a single-layer structure, for example, the second semiconductor layer 213 includes a GaN layer or an AlGaN layer. Alternatively, the second semiconductor layer 213 can be a multi-layer structure, for example, the second semiconductor layer 213 includes a combination of a GaN layer and an AlGaN layer, wherein a GaN layer and an AlGaN layer are alternately stacked, or multiple GaN layers and multiple AlGaN layers are alternately stacked. Exemplarily, the Al component content in the second semiconductor layer 213 is 0% to 30%, for example, the Al component content is 0%, 5%, 10%, 15%, 20%, 25%, 30%, etc., which is not limited here. Furthermore, the thickness of the second semiconductor layer 213 is 50nm to 500nm, for example, the thickness of the second semiconductor layer 213 is 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, etc., which is not limited here.

[0108] 3a to 3c, the optoelectronic device 10 further includes a buffer layer 250, which is located on the side of the first semiconductor layer 211 facing away from the light emitting layer 212. Exemplarily, the buffer layer 250 may be a single-layer structure, for example, the buffer layer 250 includes an AlN layer, a GaN layer, or an AlGaN layer. Alternatively, the buffer layer 250 may be a multi-layer structure, for example, the buffer layer 250 includes a combination of two or three of an AlN layer, a GaN layer, and an AlGaN layer. Exemplarily, the thickness of the buffer layer 250 is 200nm to 10um, for example, the thickness of the buffer layer 250 is 200nm, 500nm, 800nm, 1um, 1.5um, 5um, 10um, etc., which are not limited here. It is understood that the area of ​​the active light-emitting area in the light-emitting pixel may be the area of ​​the positive projection of the light-emitting layer on the buffer layer 250.

[0109] Based on the above, the light-emitting pixel 200 can be formed as a GaN-type LED. Furthermore, because micro-light-emitting diodes (Micro LEDs) and mini-light-emitting diodes (Mini LEDs) not only have the long life, high brightness, and low power consumption characteristics of light-emitting diodes (LEDs), but also have advantages such as ultra-high resolution, high color saturation, and nanosecond response speed, in some embodiments of the present application, the light-emitting pixel 200 can also be formed as a GaN-type Micro LED or GaN-type Mini LED.

[0110] In some embodiments of the present application, referring to Figures 3a to 3c, the electrode metal layer 230 also covers the sidewalls of the protruding portion of the first semiconductor layer 211, the sidewalls of the light-emitting layer 212, and the sidewalls of the second semiconductor layer 213, so as to further increase the area of ​​the electrode metal layer 230 and further improve the current uniformity. For example, the electrode metal layer 230 can fully wrap the sidewalls of the protruding portion of the first semiconductor layer 211, the sidewalls of the light-emitting layer 212, and the sidewalls of the second semiconductor layer 213. In other embodiments of the present application, the electrode metal layer 230 can also only cover a portion of the sidewalls of the protruding portion of the first semiconductor layer 211, the sidewalls of the light-emitting layer 212, and the sidewalls of the second semiconductor layer 213, that is, the electrode metal layer 230 does not completely cover the sidewalls. For example, if the orthographic projection of the semiconductor functional layer 210 on the buffer layer 250 is rectangular, the area not covered by the electrode metal layer 230 may be the corners of the adjacent two side walls of the semiconductor functional layer 210. Alternatively, the area not covered by the electrode metal layer 230 may be any side of the sidewalls of the semiconductor functional layer 210. For semiconductor functional layers 210 of other shapes, the same may be applied for reference and will not be described in detail here.

[0111] Continuing with FIG3a to FIG3c, in order to insulate the electrode metal layer 230 from the sidewalls of the protruding portion of the first semiconductor layer 211, the sidewalls of the light-emitting layer 212, and the sidewalls of the second semiconductor layer 213, a second dielectric layer 321 may be further provided between the electrode metal layer 230 and the sidewalls of the protruding portion of the first semiconductor layer 211, the sidewalls of the light-emitting layer 212, and the sidewalls of the second semiconductor layer 213. Exemplarily, the second dielectric layer 321 is a single-layer dielectric thin film structure or a multi-layer dielectric thin film composite structure, wherein the materials of the single-layer dielectric thin film structure and the multi-layer dielectric thin film composite structure include, but are not limited to, SiO2, Al2O3, MgF2, TiO2, Ta2O5, ZrO2, SiN, and the like.

[0112] Continuing with Figures 3a to 3c, the luminescent pixel 200 further includes a current spreading layer 214, which is disposed on the second semiconductor layer 213. Furthermore, the second dielectric layer 321 also covers the sidewalls of the current spreading layer 214, and the electrode metal layer 230 also covers the second dielectric layer 321 located on the sidewalls of the current spreading layer 214. This configuration further increases the area of ​​the electrode metal layer 230, further improving current uniformity. Exemplarily, the current spreading layer 214 includes one or a combination of a metal conductive layer and a transparent conductive layer to improve current uniformity. Exemplarily, the metal conductive layer includes one or more of Ni, Ag, and Au. For example, the metal conductive layer includes Ni and Ag, or the metal conductive layer includes Ni and Au. Exemplarily, the transparent conductive layer is a metal oxide transparent conductive film, such as, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0113] Furthermore, when the current spreading layer 214 is configured as a transparent conductive layer, the average refractive index of the current spreading layer 214 and the refractive index of the second dielectric layer 321 can be smaller than the refractive index of the first semiconductor layer 211, and the average refractive index of the current spreading layer 214 and the refractive index of the second dielectric layer 321 can be smaller than the refractive index of the second semiconductor layer 213. With this configuration, the current spreading layer 214 and the second dielectric layer 321 can be reused as a reflective layer, reflecting a portion of the light, further improving the light extraction efficiency of the device. Furthermore, when the electrode metal layer 230 is configured as a metal layer, the current spreading layer 214, the second dielectric layer 321, and the electrode metal layer 230 can be combined to reduce the defect of the metal layer absorbing some light, resulting in low luminous efficiency. Furthermore, the thickness of the luminescent pixel 200 can be reduced overall, facilitating the miniaturization of the luminescent pixel 200. Furthermore, to consider the thickness of the light-emitting pixel 200, the total thickness of the current spreading layer 214 and the second dielectric layer 321 can be set to 200 nm to 1000 nm. For example, the total thickness of the current spreading layer 214 and the second dielectric layer 321 can be set to 200 nm, 400 nm, 600 nm, 800 nm, 1000 nm, etc., without limitation herein. Furthermore, when the current spreading layer 214 is configured as a metallic conductive layer, it can directly reflect light emitted from the light-emitting layer 212 toward the first surface S1, thereby improving the light extraction efficiency of the device.

[0114] In general, metal materials have a high reflectivity. Referring to Figures 3a to 3c, the electrode metal layer 230 can also be reused as a reflective layer to reflect as much light emitted by the semiconductor functional layer 210 as possible to the light-emitting side, thereby improving the light extraction efficiency of the device. For example, the electrode metal layer 230 can be a single layer of metal or a multilayer of metal. In practical applications, suitable metal materials such as Al, Ag, etc. can be selected according to the reflectivity required for the wavelength of the light emitted by the light-emitting pixel 200. Alternatively, the electrode metal layer 230 can be set to a suitable metal combination stack according to the current conduction requirements. For example, the electrode metal layer 230 is set to a metal semiconductor functional layer composed of metals such as Au, Al, Ti, Pt, Ni, Cr, Ag, and combinations thereof. Among them, in order to improve the reflection performance, the metal material with high reflectivity for the light emitted by the light-emitting pixel 200 in the metal semiconductor functional layer, such as Al, Ag, etc., can be placed close to the second dielectric layer 321. Furthermore, in order to improve the adhesion and electrical contact performance of the metal semiconductor functional layer, a contact layer or adhesion layer is provided between the high-reflectivity metal material and the second dielectric layer 321 to improve the bonding strength between the electrode metal layer 230 and the second dielectric layer 321 and reduce the contact resistance. The material of the contact layer or adhesion layer is Ti, Cr, Ni, etc., and the thickness of the contact layer or adhesion layer is 0.1nm to 5nm. For example, the thickness of the contact layer or adhesion layer is 0.1nm, 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, etc., which are not limited here. It is understood that the light-emitting side is the side of the first semiconductor layer 211 facing away from the active layer. In addition, the electrode metal layer 230 is set as a metal layer, which can also provide heat dissipation function, avoid local overheating, and have better reliability under the thermal cycle impact in the subsequent process.

[0115] Continuing with Figures 3a to 3c, the portion of the electrode metal layer 230 extending from the sidewall of the second semiconductor layer 213 to the side of the current spreading layer 214 facing away from the light-emitting layer has a double-stepped shape. This facilitates stress release, reduces the risk of fracture in the electrode metal layer 230 extending from the sidewall of the second semiconductor layer 213 to the current spreading layer 214, and improves reliability. For example, the side of the second semiconductor layer 213 facing away from the light-emitting layer 212 comprises a first region BB1 and a second region BB2. The first region BB1 surrounds the second region BB2, and the current spreading layer 214 covers the second region BB2. Furthermore, the second dielectric layer 321 also covers the first region BB1. The second dielectric layer 321 extends along the sidewall of the second semiconductor layer 213 to the first region BB1, and then extends through the first region BB1 to the sidewall of the current spreading layer 214. Furthermore, the electrode metal layer 230 also covers the second dielectric layer 321 located on the first region BB1. Therefore, the electrode metal layer 230 extends along the second dielectric layer 321 to the sidewall of the current spreading layer 214.

[0116] Continuing with Figures 3a to 3c, the surface of the current spreading layer 214 facing away from the second semiconductor layer 213 is the first surface S1. The electrode metal layer 230 also extends to cover the first surface S1 and encloses a second contact hole 332 on the first surface S1, further increasing the area of ​​the electrode metal layer 230 and improving current uniformity. Furthermore, the second dielectric layer 321 also extends to cover the first surface S1 and encloses a third contact hole 333 inside the second contact hole 332. That is, the electrode metal layer 230 encloses the second contact hole 332 at a predetermined spacing SP from the third contact hole 333. Based on this, the first electrode 220 can be electrically connected to the second semiconductor layer 213 through the second contact hole 332 and the third contact hole 333, while the first electrode 220 is insulated from the electrode metal layer 230. This configuration insulates the electrode metal layer 230 from the semiconductor functional layer 210 via the second dielectric layer 321, improving the adhesion of the electrode metal layer 230. Furthermore, when the electrode metal layer 230 is a metal layer, it can further reflect as much light as possible emitted from the first surface S1 of the semiconductor functional layer 210 to the light-emitting side, thereby improving the light extraction efficiency of the device. Furthermore, the spacing SP can be determined based on the needs of the actual application scenario and is not limited here.

[0117] Furthermore, this configuration allows the second dielectric layer 321 to have a double-stepped shape in the portion extending from the sidewall of the second semiconductor layer 213 to the first surface S1, reducing the risk of fracture of the second dielectric layer 321. Because the electrode metal layer 230 extends along the surface of the second dielectric layer 321 to the second contact hole 332, the portion of the electrode metal layer 230 extending from the sidewall of the second semiconductor layer 213 to the first surface S1 can also have a double-stepped shape, reducing the risk of fracture of the electrode metal layer 230. Furthermore, this configuration allows the electrode metal layer 230 to conform to the semiconductor functional layer 210, allowing the electrode metal layer 230 to cover the gaps between the light-emitting pixels 200. When the electrode metal layer 230 is configured as a metal layer, it can further reflect as much light as possible emitted from the sidewall of the semiconductor functional layer 210 and the first surface S1 to the light-emitting side, thereby improving reflection efficiency and the luminous efficiency of the light-emitting pixels 200.

[0118] In some embodiments of the present application, the electrode metal layer 230 on the first surface S1 can be a full-surface structure, and the second contact hole 332 is formed in the full-surface structure, that is, the electrode metal layer 230 exposes the area of ​​the first surface S1 in the area where the second contact hole 332 is located. Alternatively, not only the second contact hole 332 is formed in the full-surface structure, but also other contact holes or openings can be formed in the full-surface structure, that is, the electrode metal layer 230 exposes not only the area of ​​the first surface S1 in the area where the second contact hole 332 is located, but also the area of ​​the first surface S1 in the areas where the other contact holes or openings are located. For example, if the orthographic projection of the semiconductor functional layer 210 is rectangular, the area not covered by the electrode metal layer 230 can be the area from the corner of the adjacent two sidewalls of the semiconductor functional layer 210 to the second contact hole 332. Alternatively, the area not covered by the electrode metal layer 230 can also be the area from any sidewall of the semiconductor functional layer 210 to the second contact hole 332. For semiconductor functional layers 210 of other shapes, please refer to the above for understanding, and will not be described in detail.

[0119] Continuing with reference to Figures 2a to 3c, the first electrode 220 may include a first electrode connection layer 221 and a first electrode pad layer 222 that are connected to each other. The first electrode connection layer 221 is disposed between the first electrode pad layer 222 and the current spreading layer 214. The first electrode connection layer 221 is connected to the current spreading layer 214 through a second contact hole 332 and a third contact hole 333, thereby electrically connecting the first electrode connection layer 221 to the second semiconductor layer 213 through the current spreading layer 214. For example, the materials of the first electrode connection layer 221 and the first electrode pad layer 222 may each include one or a combination of Au, Al, Ti, Pt, Ni, Cr, Ag, Sn, AuSn, etc. Among them, the material of the first electrode pad layer 222 may be AuSn to reduce contact resistance and improve connection reliability.

[0120] 2a to 3c , in the stacking direction F0 between the light-emitting layer 212 and the second semiconductor layer 213, the first electrode connection layer 221 has an outer boundary Y221, and the second contact hole 332 also has an outer boundary Y332. The spacing between the outer boundary Y221 and the outer boundary Y332 can be greater than zero. Furthermore, the first electrode connection layer 221 can be disposed within the second contact hole 332 in the stacking direction F0. This arrangement allows the first electrode connection layer 221 to be retracted within the second contact hole 332, and a gap is provided between the first electrode connection layer 221 and the electrode metal layer 230 at the sidewalls of the second contact hole 332, thereby insulating the first electrode connection layer 221 from the electrode metal layer 230.

[0121] Furthermore, the first electrode connection layer 221 and the electrode metal layer 230 are arranged in different layers, and a passivation layer 240 is provided between the first electrode connection layer 221 and the electrode metal layer 230. The passivation layer 240 also covers the electrode metal layer 230 and extends from the first surface S1 to the third contact hole 333, thereby allowing the first electrode connection layer 221 to not only cover the bottom wall of the third contact hole 333 but also extend along the sidewalls of the third contact hole 333 to the periphery of the opening of the third contact hole 333. With this arrangement, the portion of the first electrode connection layer 221 extending from the bottom wall of the third contact hole 333 to the periphery of the opening of the third contact hole 333 can be formed in a stepped shape, reducing the risk of fracture of the first electrode connection layer 221 and improving reliability. Furthermore, the periphery of the opening of the third contact hole 333 refers to a small portion of the edge of the opening of the third contact hole 333. Alternatively, the first electrode connection layer 221 may be formed when the electrode metal layer 230 is formed, that is, the first electrode connection layer 221 and the electrode metal layer 230 are formed in the same layer and material, thereby reducing the difficulty of process preparation. In addition, in order to further insulate the first electrode connection layer 221 from the electrode metal layer 230, a passivation layer 240 may be covered on the electrode metal layer 230, and the passivation layer 240 may be filled in the gap between the first electrode connection layer 221 and the electrode metal layer 230 at the sidewall of the second groove portion 402. In addition, the specific value of the distance between the outer boundary of the first electrode orthographic projection Y221 and the outer boundary of the second contact hole orthographic projection Y332 can be determined according to the requirements of the actual application scenario and is not limited here.

[0122] Referring to Figures 2a to 3c, in stacking direction F0, due to the gap between the first electrode connection layer 221 and the electrode metal layer 230, the first electrode pad layer 222 covers the second contact hole 332 to further improve luminous efficiency. With this arrangement, the first electrode pad layer 222 blocks the gap between the first electrode connection layer 221 and the electrode metal layer 230, thereby reflecting as much light as possible from the light-emitting layer 212 toward the current spreading layer 214 toward the light-emitting side, thereby improving reflection efficiency. Furthermore, the first electrode pad layer 222 can partially or entirely cover the second contact hole 332.

[0123] In addition, in order to insulate the first electrode pad layer 222 from the electrode metal layer 230, a passivation layer 240 is provided between the first electrode pad layer 222 and the electrode metal layer 230. Further, referring to Figures 3a to 3c, the cross-section of the first electrode connection layer 221 in the stacking direction F0 has a first groove AX1, and a portion of the first electrode pad layer 222 fills the first groove AX1. In this configuration, a portion of the first electrode pad layer 222 is embedded in the first groove AX1, forming a stepped pad, thereby improving reliability.

[0124] Continuing to refer to Figures 3a to 3c, the first electrode 220 covers at least a portion of the first surface S1. In addition, an angle β is formed between the sidewall of the semiconductor functional layer 210 and the first surface S1, and the angle β is toward one side of the semiconductor functional layer 210, and the angle β is set to a right angle. It is worth mentioning that the right angle defined in the embodiment of the present application is not limited to an absolute 90-degree relationship. It is allowed that the relationship is not an absolute 90-degree relationship due to factors such as assembly tolerance, design tolerance, and the influence of structural flatness, and an error in a small angle range is allowed. For example, 89 degrees to 91 degrees can be understood as a 90-degree relationship within the assembly error range, and the rest are similar and will not be repeated one by one. It is understandable that the sidewall of the semiconductor functional layer 210 corresponding to the angle β is composed of the sidewall of the protruding portion of the first semiconductor layer 211, the sidewall of the light-emitting layer 212, and the sidewall of the second semiconductor layer 213.

[0125] 2a to 3c , the first groove portion 401 is located between adjacent light-emitting pixels 200, and the first groove portion 401 also surrounds and communicates with the second groove portion 402. With this arrangement, the electrode metal layer 230 can extend in both the first groove portion 401 and the second groove portion 402.

[0126] In some embodiments of the present application, the electrode metal layer 230 may completely cover the bottom wall of the first trench portion 401, that is, the entire bottom wall area of ​​the first trench portion 401 is covered by the electrode metal layer 230. In other embodiments of the present application, the electrode metal layer 230 may only cover a portion of the bottom wall area of ​​the first trench portion 401, that is, the electrode metal layer 230 does not cover the entire bottom wall area of ​​the first trench portion 401, as long as it can ensure connectivity with the first semiconductor layer 211.

[0127] In some embodiments of the present application, the electrode metal layer 230 may completely cover the bottom wall of the second trench portion 402, thereby increasing the contact area between the electrode metal layer 230 and the first semiconductor layer 211. In other embodiments of the present application, the electrode metal layer 230 may only cover a portion of the bottom wall of the second trench portion 402. In other words, the electrode metal layer 230 does not cover the entire bottom wall of the second trench portion 402, as long as the electrode metal layer 230 and the first semiconductor layer 211 are electrically connected.

[0128] In some embodiments of the present application, referring to Figures 3a to 3c, a first dielectric layer 322 is disposed between the electrode metal layer 230 and the bottom wall of the first trench portion 401. That is, the bottom wall of the first trench portion 401 is completely covered by the first dielectric layer 322, while the bottom wall of the second trench portion 402 is not covered by the first dielectric layer 322. Instead, the bottom wall of the second trench portion 402 is covered by the electrode metal layer 230. It is worth noting that when the first dielectric layer 322 is disposed, if the electrode metal layer 230 completely covers the first dielectric layer 322, it can also be equivalent to the electrode metal layer 230 covering the entire area of ​​the bottom wall of the first trench portion 401. Furthermore, the first dielectric layer 322 and the second dielectric layer 321 can be formed of the same film layer, that is, the first dielectric layer 322 and the second dielectric layer 321 are provided in the same layer and material, and the first dielectric layer 322 and the second dielectric layer 321 are integrally structured.

[0129] As can be understood, referring to FIG. 2b , second groove portions 402 are not provided throughout the entire first groove portion 401, but rather are provided only in certain areas. This allows the size W404 of the first groove portion 401 not provided with the second groove portion 402 to be reduced. For example, W404 can be set to less than or equal to 2 μm, thereby expanding the area of ​​the active light-emitting area. For example, W404 can be set to 2 μm, 1.8 μm, 1.5 μm, etc. The specific value can be determined based on the actual application scenario and is not limited here.

[0130] 2a and 2b , the light-emitting pixels 200 are spaced apart from each other and arranged in an array, such that the groove region 400 forms a grid pattern 420. For example, referring to FIG. 2c , which is another top view of the groove region in an embodiment of the present application, second groove portions 402 may be provided on at least some of the grid lines of the grid pattern 420. Alternatively, referring to FIG. 2a , FIG. 2b , and FIG. 3b , second groove portions 402 may also be provided at at least some of the grid intersection regions of the grid pattern 420. For example, referring to FIG. 2a and 2b , second groove portions 402 may be provided at some of the grid intersection regions of the grid pattern 420. For example, the grid intersection region of the grid pattern 420 includes a plurality of first intersection regions 411 and a plurality of second intersection regions 412. The first intersection regions 411 are provided with second groove portions 402, i.e., the first intersection regions 411 are provided with both first groove portions 401 and second groove portions 402, and the first groove portions 401 in the first intersection regions 411 surround the second groove portions 402. The second intersection regions 412 are not provided with second groove portions 402, i.e., the second intersection regions are all provided with first groove portions 401. For example, referring to FIG4a, FIG4a is a schematic diagram of an equivalent structure of a grid pattern provided in an embodiment of the present application, in which the first intersection area 411 and the second intersection area 412 are alternately arranged along the first direction F1, and the first intersection area 411 and the second intersection area 412 are also alternately arranged along the second direction F2, and the first direction F1 and the second direction F2 intersect, so that the first intersection area 411 and the second intersection area 412 are arranged in a checkerboard manner, thereby being able to disperse the first intersection area 411 and the second intersection area 412 as evenly as possible, thereby improving the uniformity of conductivity. Alternatively, referring to FIG4b, FIG4b is another schematic diagram of an equivalent structure of a grid pattern provided in an embodiment of the present application, in which the two first intersection areas 411 and the two second intersection areas 412 are alternately arranged along the first direction F1, and the two first intersection areas 411 and the two second intersection areas 412 are alternately arranged along the second direction F2. Of course, it is also possible to arrange three or more first intersection regions 411 and three or more second intersection regions 412 alternately along the first direction F1, and to arrange three or more first intersection regions 411 and three or more second intersection regions 412 alternately along the second direction F2, without limitation herein. Alternatively, referring to FIG. 4 c , FIG. 4 c is a schematic diagram of another equivalent structure of the grid pattern provided in an embodiment of the present application, it is also possible to set all intersection regions in a row arranged along the first direction F1 as first intersection regions 411, and set all intersection regions in another row arranged along the first direction F1 as second intersection regions 412, and to arrange first intersection regions 411 and second intersection regions 412 alternately along the second direction F2.Alternatively, referring to Figure 4d, Figure 4d is another equivalent structural schematic diagram of the grid pattern provided in an embodiment of the present application, and a second groove portion 402 can also be provided in all grid intersection areas in the grid pattern 420. It is worth mentioning that Figures 4a to 4d only illustrate some arrangements of the first intersection area 411 and the second intersection area 412. Other arrangements of the first intersection area 411 and the second intersection area 412 are not listed here one by one. In addition, the first direction F1 and the second direction F2 are parallel to the substrate 100, and there is an angle between the first direction F1 and the second direction F2, wherein the angle can be a right angle, an acute angle or an obtuse angle. If the angle is a right angle, the first direction F1 and the second direction F2 are perpendicular.

[0131] As can be understood, referring to FIG. 2b , if the second groove portions 402 are positioned at the intersection of the grid, then the grid lines can all be configured as first groove portions 401. This allows the size W401 of the first groove portions 401 positioned at the grid lines to be compressed. For example, W401 can be set to less than or equal to 2 μm, thereby expanding the area of ​​the active light-emitting area. For example, W401 can be set to 2 μm, 1.8 μm, 1.5 μm, etc. The specific value can be determined based on the actual application scenario and is not limited here.

[0132] In some embodiments of the present application, the proportion of the first trench portion 401 in the trench region 400 can be greater than or equal to 50%, and the proportion of the first trench portion 401 in the trench region 400 can be less than 100%. For example, the proportion of the first trench portion 401 in the trench region 400 can be set to 50%, 60%, 70%, 80%, 90%, etc. The specific value can be determined according to the requirements of the actual application scenario and is not limited here.

[0133] In some embodiments of the present application, the proportion of the second trench portion 402 in the trench region 400 can be greater than 0, and the proportion of the second trench portion 402 in the trench region 400 can be less than or equal to 50%. For example, the proportion of the second trench portion 402 in the trench region 400 can be set to 10%, 20%, 30%, 40%, 50%, etc. The specific value can be determined according to the requirements of the actual application scenario and is not limited here.

[0134] In some embodiments of the present application, the coverage area of ​​the electrode metal layer 230 can account for 30% to 99% of the total area of ​​the entire optoelectronic device. Among them, 30% to 70% corresponds to normal current application scenarios, and 70% to 99% corresponds to high current application scenarios to meet high current requirements. In addition, in some extreme cases, the coverage area of ​​the electrode metal layer 230 can account for 99% of the total area of ​​the entire optoelectronic device.

[0135] The portion of the electrode metal layer 230 covering the second groove portion 402 is designated as the first electrode metal layer 230 portion. The area of ​​the first electrode metal layer 230 portion accounts for less than or equal to 70% of the total area of ​​the electrode metal layer 230. Furthermore, the area of ​​the first electrode metal layer 230 portion accounts for less than or equal to 30% of the total area of ​​the electrode metal layer 230. For example, the area of ​​the first electrode metal layer 230 portion accounts for less than or equal to 70%, 60%, 50%, 40%, 30%, 20%, etc., without limitation herein.

[0136] The portion of the electrode metal layer 230 covering the first groove portion 401 is designated as the second electrode metal layer 230 portion. The area of ​​the second electrode metal layer 230 portion accounts for less than or equal to 30% of the total area of ​​the electrode metal layer 230. Furthermore, the area of ​​the second electrode metal layer 230 portion accounts for less than or equal to 70% of the total area of ​​the electrode metal layer 230. For example, the area of ​​the second electrode metal layer 230 portion accounts for greater than or equal to 30%, 40%, 50%, 60%, 70%, 80%, 90%, etc., without limitation herein.

[0137] In addition, the shape of the second groove portion 402 is not limited in the present application. For example, the shape of the second groove portion 402 includes but is not limited to a circle, a rectangle, a polygon, etc.

[0138] Taking the structure of the optoelectronic device shown in FIG. 2a to FIG. 3c as an example, the method for preparing the optoelectronic device provided in the embodiment of the present application may include the following contents:

[0139] Referring to Figure 5a, Figure 5a illustrates a cross-sectional view of the structure of an optoelectronic device during fabrication according to an embodiment of the present application. For example, a substrate 100 is provided. This substrate 100 may include, but is not limited to, a Si substrate 100, a SiC substrate 100, a sapphire substrate 100, or a GaN substrate 100. A buffer layer 250, a first semiconductor layer 211, a light-emitting layer 212, and a second semiconductor layer 213 are sequentially epitaxially formed on substrate 100. Subsequently, a current spreading layer 214 is deposited.

[0140] Referring to Figure 5b, Figure 5b is another schematic cross-sectional view of the optoelectronic device during the fabrication process in an embodiment of the present application. For example, a patterning process is employed to pattern the first semiconductor layer 211, the light-emitting layer 212, and the second semiconductor layer 213. A recess is formed in the first semiconductor layer 211, and the protruding portion of the first semiconductor layer 211 is formed on the side facing away from the substrate 100 to form the light-emitting layer 212. Furthermore, the second semiconductor layer 213 is formed on the side facing away from the substrate 100 to form the light-emitting layer 212.

[0141] Referring to Figure 5c, Figure 5c illustrates another cross-sectional view of the optoelectronic device during fabrication in an embodiment of the present application. By way of example, a dielectric layer is deposited on the side of the current spreading layer 214 facing away from the substrate 100. The dielectric layer comprises a second dielectric layer 321 and a first dielectric layer 322. Subsequently, the dielectric layer is patterned using a patterning process to expose the second trench portion 402 and form the third contact hole 333.

[0142] Referring to Figure 5d, Figure 5d illustrates another cross-sectional view of the optoelectronic device during fabrication in an embodiment of the present application. For example, a metal material is deposited on the side of the dielectric layer facing away from the substrate 100 to form an electrode metal layer 230. The electrode metal layer 230 is then brought into contact with the first semiconductor layer 211 within the second trench portion 402. Subsequently, a patterning process is performed on the electrode metal layer 230 to form a second contact hole 332 extending through the electrode metal layer 230.

[0143] 5e is another cross-sectional view of the optoelectronic device during the manufacturing process according to an embodiment of the present application. For example, a passivation layer 240 is deposited on the side of the metal layer facing away from the substrate 100, and the third contact hole 333 is exposed.

[0144] Referring to Figure 5f, which illustrates another cross-sectional view of the optoelectronic device during fabrication in accordance with an embodiment of the present invention, a first electrode connection layer 221 is deposited on the side of the passivation layer 240 facing away from the substrate 100, and the first electrode connection layer 221 is in contact with the current spreading layer 214 on the semiconductor functional layer 210.

[0145] 5G , a first electrode pad layer 222 is formed on the first electrode connection layer 221 , and the first electrode pad layer 222 and the first electrode connection layer 221 are connected.

[0146] FIG6a is another schematic top view of the structure of the optoelectronic device provided in an embodiment of the present application, FIG6b is a top view of the trench region shown in FIG6a, FIG6c is another schematic top view of the trench region in an embodiment of the present application, and FIG7 is a schematic cross-sectional view of the structure along the AA' direction in FIG6a. Referring to FIG6a to FIG7, the optoelectronic device in this embodiment is modified from the optoelectronic device in the above embodiment, and the similarities therebetween are not repeated here. The difference is that the sidewalls of the trench region having the second trench portion 402 have a first dimension W403 between them, and the sidewalls of the trench region having the first trench portion have a second dimension W401 between them, wherein the maximum value of the first dimension W403 is greater than the maximum value of the second dimension W401. This configuration can reduce the size of the first trench portion in the trench region and reserve a certain amount of space in the trench region for the second trench portion, thereby increasing the electrical connection area between the electrode metal layer and the first semiconductor layer and improving power supply reliability.

[0147] Exemplarily, referring to FIG6 a , the first dimension W403 and the second dimension W401 may both be widths in different directions. For example, the second dimension W401 is the width in the first direction F1 , and the second dimension W401 is the width in a gas direction different from the first direction F1 .

[0148] Exemplarily, referring to FIG. 6B , the first size W403 and the second size W401 may both be widths in the same direction. For example, the first size W403 and the second size W401 may both be widths in the first direction F1 .

[0149] Furthermore, referring to Figures 6a and 6b, the sidewalls of the first trench portion 401 not surrounding the second trench portion 402 have a third dimension W404, and the second trench portion 402 has a fourth dimension W402, which is greater than the third dimension W404. The fourth dimension W402 and the third dimension W404 can be widths in the same direction or in different directions. For example, the fourth dimension W402 and the third dimension W404 can both be widths in the first direction F1. This configuration can increase the size of the second trench portion 402, thereby increasing the contact area between the electrode metal layer 230 and the first semiconductor layer 211, further improving power supply uniformity.

[0150] It is understandable that the specific values ​​of W401, W402, W403, and W404 can be determined according to the requirements of the actual application scenario and are not limited here.

[0151] In some embodiments of the present application, to increase the size of the second trench portion 402, for example, the semiconductor functional layer 210 surrounding the second trench portion 402 can be configured to provide a clearance for the second trench portion 402, reserving an area for the second trench portion 402. For example, in the stacking direction F0, the semiconductor functional layer 210 adjacent to the second trench portion 402 has an outer boundary Y210, and the second trench portion 402 has an outer boundary Y402. The outer boundary Y210 has a clearance recess AC on the side facing the outer boundary Y402. This is equivalent to forming the clearance recess AC on the sidewall of the semiconductor functional layer 210. This allows the clearance recess AC to provide a clearance for the second trench portion 402, thereby increasing the size of the second trench portion 402. Furthermore, by providing the clearance recess AC as a clearance for the second trench portion 402, the area enclosed by the outer boundary Y210 does not need to be uniformly reduced, thereby avoiding excessively reducing the area of ​​the semiconductor functional layer 210. With this arrangement, only the first groove portion 401 surrounding the second groove portion 402 needs to be expanded in all directions, and the remaining first groove portions 401 (especially the first groove portions 401 at the grid lines) do not need to be expanded, thereby ensuring the area of ​​the active light-emitting area and increasing the contact area between the electrode metal layer 230 and the first semiconductor layer 211.

[0152] Furthermore, the shape of the relief recess AC is identical or similar to the shape of the location corresponding to the outer boundary Y402. This allows the shape of the relief recess AC to be selected based on the shape of the location corresponding to the outer boundary Y402. Furthermore, by providing the relief recess AC on the semiconductor functional layer 210, better relief can be provided for the second trench portion 402. Exemplarily, the shape of the outer boundary Y402 includes, but is not limited to, a circle, a rectangle, a polygon, etc. For example, if the outer boundary Y402 is circular, the relief recess AC can be arc-shaped. Furthermore, the size of the second trench portion 402 can be greater than, equal to, or smaller than the size of the second contact hole 332 or the third contact hole 333, without limitation herein.

[0153] Furthermore, the portion of the electrode metal layer 230 extending from the first groove portion 401 to the second groove portion 402 is stepped, which is conducive to stress release, reduces the risk of fracture of the electrode metal layer 230, and improves reliability. For example, by providing the first dielectric layer 322, the portion of the electrode metal layer 230 extending from the first dielectric layer 322 to the bottom wall of the second groove portion 402 can be formed into a stepped shape. The present application raises the electrode metal layer 230 by reusing the first dielectric layer 322, so that the electrode metal layer 230 can extend along the first dielectric layer 322 to the bottom wall of the second groove portion 402, thereby forming a stepped shape in the portion of the electrode metal layer 230 extending from the first groove portion 401 to the second groove portion 402. Of course, in actual applications, other methods can also be used to form the electrode metal layer 230 into a stepped shape.

[0154] Furthermore, the electrode metal layer 230 may form three steps in the process of extending from the bottom wall of the second trench portion 402 to the first surface S1 , further reducing the risk of fracture.

[0155] For example, referring to FIG6c , which is another top view of the groove region in an embodiment of the present application, second groove portions 402 may be provided on at least some of the grid lines of the grid pattern 420. Alternatively, referring to FIG6a , second groove portions 402 may also be provided at at least some of the grid intersection regions of the grid pattern 420.

[0156] In addition, the above-described fabrication method can also be used for the photovoltaic device structures shown in Figures 6a and 7 . In the step shown in Figure 5b , the avoidance recess AC is formed. In the step shown in Figure 5c , the size of the second trench portion 402 exposed by the first dielectric layer 322 is made relatively large.

[0157] FIG8 is a schematic top view of another optoelectronic device provided in an embodiment of the present application, and FIG9 is a schematic cross-sectional view of FIG8 along the AA' direction. Referring to FIG8 and FIG9, the optoelectronic device in this embodiment is modified from the optoelectronic device in the above embodiment, and the similarities therebetween are not repeated here. The difference lies in that the optoelectronic device 10 not only has a light-emitting pixel 200 but also has one or more boss structures 510. The boss structure 510 has a second surface S2, and the second electrode 520 is disposed on the second surface S2. With this arrangement, the second electrode 520 is elevated by the boss structure 510. When the first electrode 220 and the second electrode 520 are interconnected to the driver device using the interconnection structure, the length difference between the interconnection structure connected to the first electrode 220 and the interconnection structure connected to the second electrode 520 can be minimized, thereby reducing the risk of device failure and improving the reliability of the interconnection between the optoelectronic device 10 and the driver device.

[0158] In some embodiments of the present application, referring to FIG9 , a first vertical distance h1 is defined between the first surface S1 and the surface of the first semiconductor layer 211 facing away from the first electrode 220, and a second vertical distance h2 is defined between the second surface S2 and the surface of the first semiconductor layer 211 facing away from the first electrode 220. The difference between the first vertical distance h1 and the second vertical distance h2 can be set to be less than or equal to a difference threshold, so that the difference between the first vertical distance h1 and the second vertical distance h2 is as small as possible or negligible. This configuration allows the surface of the second electrode 520 facing away from the substrate 100 and the surface of the first electrode 220 facing away from the substrate 100 to be formed on the same plane as much as possible, thereby minimizing the length difference between the interconnect structure connected to the first electrode 220 and the interconnect structure connected to the second electrode 520, thereby reducing the risk of device failure and improving the interconnect reliability between the optoelectronic device 10 and the driver device. It is understood that the difference between the first vertical distance h1 and the second vertical distance h2 can be the difference or ratio between the first vertical distance h1 and the second vertical distance h2. Furthermore, the difference threshold may be 0±Δh, where Δh may be the difference or error tolerance range allowed by the process preparation conditions.

[0159] In some embodiments of the present application, the platform structure 510 is configured as a multi-layer structure. For example, referring to FIG9 , the platform structure 510 may include a semiconductor functional layer 210 and a current spreading layer 214, that is, the platform structure 510 also includes a first semiconductor layer 211, a light-emitting layer 212, a second semiconductor layer 213, and a current spreading layer 214. With this configuration, the platform structure 510 can be formed when the semiconductor functional layer 210 and the current spreading layer 214 are formed, which not only ensures that the difference between the first vertical distance h1 and the second vertical distance h2 is as small as possible, but also reduces the process preparation process. It is understandable that the second surface S2 can be the surface of the current spreading layer 214 in the platform structure 510 facing away from the substrate 100.

[0160] 8 and 9 , since the platform structure 510 includes a semiconductor functional layer 210 and a current spreading layer 214, but since the electrode metal layer 230 is electrically connected to the second electrode 520 and the electrode metal layer 230 is also connected to the first semiconductor layer 211, the first semiconductor layer 211 and the second semiconductor layer 213 in the platform structure 510 are both input with the same voltage, resulting in the entire structure not emitting light. Therefore, the groove region 400 is also provided between adjacent platform structures 510 and between the platform structure 510 and the light-emitting pixel 200. Furthermore, in order to increase the area of ​​the metal electrode layer 230, the electrode metal layer 230 can also cover the sidewalls of the platform structure. In other words, there is a groove region 400 between the platform structure 510 and the semiconductor functional layer 210, and there is also a groove region 400 between the platform structure 510 and the platform structure 510. That is to say, not only the first semiconductor layer 211 in the light-emitting pixel 200 encloses the groove area 400, but the first semiconductor layer 211 in the boss structure 510 and the first semiconductor layer 211 in the semiconductor functional layer 210 also enclose the groove area 400, and the boss structure 510 and the first semiconductor layer 211 in the boss structure 510 also enclose the groove area 400.

[0161] It is worth mentioning that if multiple platform structures are provided, the groove region is provided between the platform structure and the light-emitting pixel, and the groove region is also provided between the platform structure and the platform structure. Alternatively, if one platform structure is provided, the groove region is provided between the platform structure and the light-emitting pixel.

[0162] For example, the groove structure disposed between the platform structure and the light-emitting pixel may include only the first groove portion or the second groove portion, or may include both the first groove portion and the second groove portion. This configuration can further increase the area of ​​the electrode metal layer and improve the current uniformity of the light-emitting pixel. It is understood that the implementation of the first groove portion and the second groove portion disposed between the platform structure and the light-emitting pixel can refer to the description of the above embodiment, and the details are not repeated here.

[0163] For example, the groove structure disposed between the platform structures may include only the first groove portion or the second groove portion, or may include both the first groove portion and the second groove portion. This configuration can further increase the area of ​​the electrode metal layer and improve the current uniformity of the light-emitting pixel. It is understood that the implementation of the first groove portion and the second groove portion disposed between the platform structures can refer to the description of the above embodiment, and the details are not repeated here.

[0164] Furthermore, to improve the reliability of the electrode metal layer 230, the electrode metal layer 230 and the second dielectric layer 321 are also extended into the groove region 400 between the platform structure 510 and the semiconductor functional layer 210. Furthermore, the electrode metal layer 230 and the second dielectric layer 321 are also extended into the groove region 400 between the platform structure 510. Furthermore, the arrangement of the second groove portion 402 in the groove region 400 can refer to the arrangement of the grid pattern 420 in the above embodiment, for example, the second groove portion 402 is arranged in the first intersection region 411.

[0165] In some embodiments of the present application, the outer boundary Y402 of the platform structure 510 in the stacking direction F0 also has an avoidance recess AC. The implementation of this avoidance recess AC can refer to the above embodiments and is not limited here. For example, the outer boundary Y402 of the platform structure 510 and the outer boundary Y210 of the semiconductor functional layer 210 can be mirror-symmetrical, translationally symmetrical, or rotationally symmetrical.

[0166] Continuing with reference to Figures 8 and 9, the second electrode 520 includes a second electrode connection layer 521 and a second electrode pad layer 522 that are interconnected. The second electrode connection layer 521 is disposed between the second electrode pad layer 522 and the boss structure 510. Furthermore, the second electrode connection layer 521 covers a portion or the entire area of ​​the second surface S2. The second electrode connection layer 521 also extends along the sidewalls of the boss structure 510 to the groove region 400, and the second electrode connection layer 521 is in contact with the electrode metal layer 230. With this arrangement, the second electrode connection layer 521 can be electrically connected to the electrode metal layer 230, and the second voltage can be transmitted to the electrode metal layer 230 via the second electrode connection layer 521. Furthermore, the conductive area can be increased, further reducing the voltage drop.

[0167] In some embodiments of the present application, the second electrode connection layer 521 may be provided to cover the sidewalls of the boss structure 510. The manner in which the second electrode connection layer 521 covers the sidewalls of the boss structure 510 may refer to the manner in which the electrode metal layer 230 covers the sidewalls of the semiconductor functional layer 210, and details thereof will not be repeated herein.

[0168] In some embodiments of the present application, the second electrode connection layer 521 can cover the entire area of ​​the second surface S2, further increasing the area of ​​the second electrode connection layer 521 and reducing the voltage drop of the second electrode connection layer 521. In addition, the surface of the second electrode pad layer 522 facing away from the substrate 100 can be the surface of the second electrode 520 facing away from the substrate 100.

[0169] To improve the adhesion of the second electrode connection layer 521, as shown in FIG9 , a third dielectric layer 323 is disposed between the second electrode connection layer 521 and the platform structure 510. The third dielectric layer 323 covers the sidewalls of the platform structure 510. Furthermore, the third dielectric layer 323 extends to the second surface S2 and encloses a fourth contact hole 334 therein. The second electrode connection layer 521 covers the third dielectric layer 323. Furthermore, the second electrode connection layer 521 contacts the second surface S2 through the fourth contact hole 334. This arrangement allows the second electrode connection layer 521 on the second surface S2 to have the same structure as the first electrode connection layer 221 on the first surface S1 as possible. Furthermore, by contacting the second electrode connection layer 521 with the current spreading layer 214 in the platform structure 510, a second voltage is applied to the second semiconductor layer 213 and the first semiconductor layer 211 in the platform structure 510, further preventing the light-emitting layer 212 in the platform structure 510 from emitting light.

[0170] Exemplarily, the third dielectric layer 323 is a single-layer dielectric thin film structure or a multi-layer dielectric thin film composite structure. The materials for the single-layer dielectric thin film structure and the multi-layer dielectric thin film composite structure include, but are not limited to, SiO2, Al2O3, MgF2, TiO2, Ta2O5, ZrO2, SiN, etc. Furthermore, the third dielectric layer 323 can be formed from the same film layer as the first dielectric layer 322 and the second dielectric layer 321, so that the third dielectric layer 323, the first dielectric layer 322, and the second dielectric layer 321 form a single structure. Of course, in actual manufacturing processes, the third dielectric layer 323, the first dielectric layer 322, and the second dielectric layer 321 can also be prepared separately, and this is not limited here.

[0171] Furthermore, the materials of the electrode metal layer 230 and the second electrode connection layer 521 can be the same or different. For example, referring to Figure 9, the electrode metal layer 230 and the second electrode connection layer 521 can be formed using the same film layer, that is, the second electrode connection layer 521 is formed when the electrode metal layer 230 is formed, so that the second electrode connection layer 521 and the electrode metal layer 230 have the same material and structure, so that the second electrode connection layer 521 and the electrode metal layer 230 form an integrated structure. This arrangement can not only reduce the process difficulty, but also further increase the area of ​​the electrode metal layer 230 and reduce the voltage drop of the electrode metal layer 230. Of course, in the actual process preparation, the second electrode connection layer 521 and the electrode metal layer 230 can also be prepared separately, which is not limited here.

[0172] In order to reduce the design difficulty of the first electrode pad layer 222 and the second electrode pad layer 522, referring to Figures 8 and 9, the sizes of the first electrode pad layer 222 and the second electrode pad layer 522 can be set to be the same. Of course, the sizes of the first electrode pad layer 222 and the second electrode pad layer 522 can also be set to be different, which is not limited here. Furthermore, the materials of the first electrode pad layer 222 and the second electrode pad layer 522 can be the same or different. For example, the second electrode pad layer 522 is formed when the first electrode pad layer 222 is formed, so that the materials of the first electrode pad layer 222 and the second electrode pad layer 522 are the same and the structures are the same, and it is ensured as much as possible that the surface of the second electrode 520 facing away from the substrate 100 and the surface of the first electrode 220 facing away from the substrate 100 are formed on the same plane as much as possible.

[0173] To reduce the design difficulty of the third contact hole 333 and the fourth contact hole 334, referring to Figures 8 and 9, the sizes of the third contact hole 333 and the fourth contact hole 334 can be set to be the same. Of course, the sizes of the third contact hole 333 and the fourth contact hole 334 can also be set to be different, which is not limited here.

[0174] 8 and 9 , the second electrode pad layer 522 may cover the fourth contact hole 334. Alternatively, since the second electrode connection layer 521 covers the boss structure 510, the second electrode pad layer 522 may also be disposed in the fourth contact hole 334, which is not limited here.

[0175] 9 , a cross-section of the second electrode connection layer 521 in the stacking direction F0 has a second groove AX2, and a portion of the second electrode pad layer 522 fills the second groove AX2. Thus, a portion of the second electrode pad layer 522 is embedded in the second groove AX2, forming a stepped pad and improving reliability.

[0176] 8 , when a boss structure 510 is provided in the optoelectronic device, the proportion of the first groove portion 401 in the groove area 400, the proportion of the second groove portion 402 in the groove area 400, the coverage area of ​​the electrode metal layer 230 can account for a percentage of the total area of ​​the entire optoelectronic device, the proportion of the area of ​​the first electrode metal layer 230 portion in the total area of ​​the electrode metal layer 230, and the proportion of the area of ​​the second electrode metal layer 230 portion in the total area of ​​the electrode metal layer 230 can also satisfy the numerical relationships in the above-mentioned embodiments, and the details will not be repeated here.

[0177] In addition, the present application does not limit the shape of the fourth contact hole 334. For example, the shape of the fourth contact hole 334 includes, but is not limited to, a circle, a rectangle, a polygon, etc. Furthermore, the shape of the fourth contact hole 334 can be the same as or different from that of the third contact hole 333. Furthermore, the size of the fourth contact hole 334 can be the same as or different from that of the third contact hole 333.

[0178] In the present application, the light-emitting pixels 200 and the platform structures 510 are arranged in an array to improve conductive uniformity. In some examples, the light-emitting pixels 200 can be completely surrounded by the platform structures 510. For example, referring to FIG10a, FIG10a shows an arrangement of the light-emitting pixels and the platform structures in an embodiment of the present application. The platform structures 510 enclose an enclosed area AA1, and all the light-emitting pixels 200 are disposed in the enclosed area AA1. Furthermore, the platform structures 510 that enclose all the light-emitting pixels 200 can be a single circle of platform structures 510, two circles of platform structures 510, or more circles of platform structures 510. Alternatively, the light-emitting pixels 200 can be partially surrounded by the platform structures 510. For example, referring to FIG10b, FIG10b shows another arrangement of the light-emitting pixels and the platform structures in an embodiment of the present application. The platform structures 510 enclose a semi-enclosed area AA2, and all the light-emitting pixels 200 are disposed in the semi-enclosed area AA2. Of course, the boss structures 510 may also be provided on both sides of the light-emitting pixel 200 along the second direction F2 or the first direction F1 , which is not limited here.

[0179] In some other examples, the light-emitting pixels 200 and the platform structures 510 may also alternate at a certain periodic ratio to improve conductive uniformity. For example, referring to FIG10c , FIG10c shows another arrangement of the light-emitting pixels and the platform structures in an embodiment of the present application. A plurality of light-emitting pixels 200 form a column of light-emitting pixels 200 along the second direction F2, and a plurality of platform structures 510 form a column of platform structures 510 along the second direction F2. A column of light-emitting pixels 200 and a column of platform structures 510 are alternately arranged along the first direction F1, or adjacent columns of light-emitting pixels 200 and adjacent columns of platform structures 510 are alternately arranged along the first direction F1. Alternatively, for example, referring to FIG10d, FIG10d illustrates another arrangement of the light-emitting pixels and the platform structures in an embodiment of the present application, wherein a plurality of light-emitting pixels 200 form a row of light-emitting pixels 200 along a first direction F1, and a plurality of platform structures 510 form a row of platform structures 510 along the first direction F1, wherein a row of light-emitting pixels 200 and a row of platform structures 510 are alternately arranged along a second direction F2, or adjacent rows of light-emitting pixels 200 and adjacent rows of platform structures 510 are alternately arranged along the second direction F2. Alternatively, for example, referring to FIG10e, FIG10e illustrates another arrangement of the light-emitting pixels and the platform structures in an embodiment of the present application, wherein the platform structures 510 include a plurality of repeatedly arranged structural units AA3, each structural unit AA3 including a light-emitting pixel 200 and a platform structure 510, and within the same structural unit AA3, the light-emitting pixels 200 surround all the platform structures 510, thereby achieving electrical connection and reducing the number of non-luminous platform structures 510 and increasing the number of luminous platform structures 510. Of course, in the same structural unit AA3 , the boss structure 510 may surround all or part of the light-emitting pixel 200 .

[0180] It is worth mentioning that FIG. 10 a to FIG. 10 e only illustrate some arrangements of the light-emitting pixels 200 and the boss structure 510 , and other arrangements of the light-emitting pixels 200 and the boss structure 510 are not listed here one by one.

[0181] Taking the structure of the optoelectronic device shown in FIG8 and FIG9 as an example, the method for preparing the optoelectronic device provided in the embodiment of the present application may include the following contents:

[0182] Referring to Figure 11a, Figure 11a illustrates a cross-sectional view of the structure of an optoelectronic device during fabrication according to an embodiment of the present application. For example, a substrate 100 is provided. This substrate 100 may include, but is not limited to, a Si substrate 100, a SiC substrate 100, a sapphire substrate 100, or a GaN substrate 100. A buffer layer 250, a first semiconductor layer 211, a light-emitting layer 212, and a second semiconductor layer 213 are sequentially epitaxially formed on substrate 100. Subsequently, a current spreading layer 214 is deposited.

[0183] Referring to Figure 11b, Figure 11b is another schematic cross-sectional view of the optoelectronic device during the preparation process in an embodiment of the present application. For example, a patterning process is used to pattern the first semiconductor layer 211, the light-emitting layer 212, and the second semiconductor layer 213. A groove region 400 is formed in the first semiconductor layer 211. The protruding portion of the first semiconductor layer 211 is formed on the side facing away from the substrate 100 to form the light-emitting layer 212. The second semiconductor layer 213 is formed on the side facing away from the substrate 100 to form the light-emitting layer 212. This forms the first semiconductor layer 211, the light-emitting layer 212, and the second semiconductor layer 213 in the semiconductor functional layer 210, and forms the first semiconductor layer 211, the light-emitting layer 212, the second semiconductor layer 213, and the current spreading layer 214 in the boss structure 510.

[0184] Referring to Figure 11c, Figure 11c illustrates another cross-sectional view of the optoelectronic device during fabrication in an embodiment of the present application. By way of example, a dielectric layer is deposited on the side of the current spreading layer 214 facing away from the substrate 100. The dielectric layer comprises a first dielectric layer 322, a second dielectric layer 321, and a third dielectric layer 323. Subsequently, the dielectric layer is patterned using a patterning process to expose the second trench portion 402 and form the third contact hole 333 and the fourth contact hole 334.

[0185] Referring to Figure 11d, Figure 11d illustrates another cross-sectional view of the optoelectronic device during fabrication in an embodiment of the present application. For example, a metal material is deposited on the side of the dielectric layer facing away from the substrate 100, and an electrode metal layer 230 and a second electrode connection layer 521 are simultaneously formed. The electrode metal layer 230 is brought into contact with the first semiconductor layer 211 through the second trench portion 402, and the second electrode connection layer 521 is brought into contact with the current spreading layer 214 in the platform structure 510 through the fourth contact hole 334. Subsequently, the electrode metal layer 230 is patterned using a patterning process to form a second contact hole 332 extending through the electrode metal layer 230.

[0186] Referring to Figure 11e, which is another schematic cross-sectional view of the optoelectronic device during fabrication in an embodiment of the present application, a passivation layer 240 is deposited on the side of the metal layer facing away from the substrate 100, exposing a portion of the third contact hole 333 and the second electrode connection layer 521 on the second surface.

[0187] Referring to Figure 11f, which illustrates another cross-sectional view of the optoelectronic device during fabrication in accordance with an embodiment of the present invention, a first electrode connection layer 221 is deposited on the side of the passivation layer 240 facing away from the substrate 100, and the first electrode connection layer 221 is in contact with the current spreading layer 214 on the semiconductor functional layer 210.

[0188] 11 g , the first electrode pad layer 222 and the second electrode pad layer 522 are formed, and the first electrode pad layer 222 and the first electrode connection layer 221 are connected, and the second electrode pad layer 522 and the second electrode connection layer 521 are connected.

[0189] FIG12 is another schematic cross-sectional view of the structure along the AA' direction in FIG8 . Referring to FIG12 , the optoelectronic device in this embodiment is a modification of the optoelectronic device in the above embodiment. The similarities are not further described here. The difference lies in: a plurality of first protrusion structures 710 are disposed between the buffer layer 250 and the first semiconductor layer 211. These first protrusion structures 710 are spaced apart from each other. This configuration, by roughening the surface of the first semiconductor layer 211 facing the buffer layer 250, can change the angle between the emitted light and the interface, reducing total internal reflection, improving light extraction efficiency, and preventing light from refracting back and forth within the light-emitting element. For example, the plurality of first protrusion structures 710 can be integrally formed with the buffer layer 250. For example, the plurality of first protrusion structures 710 extend from the buffer layer 250 toward the first semiconductor layer 211, further strengthening the bond between the first semiconductor layer 211 and the buffer layer 250. Alternatively, the plurality of first protrusion structures 710 can be independent of the buffer layer 250. For example, the first protruding structures 710 can be arranged in an array to uniformly improve light extraction efficiency. Furthermore, the height of the first protruding structures 710 is less than the thickness of the buffer layer 250 and the thickness of the first semiconductor layer 211. For example, the height of the first protruding structures 710 can be 0.5um to 3um. For example, the height of the first protruding structures 710 is 0.5um, 1um, 1.5um, 2um, 2.5um, 3um, etc. In practical applications, the shape of the first protruding structures 710 can be a cone, a cylinder, a pyramid, or a prism, and this application does not limit this. Furthermore, the method for preparing the structure of the optoelectronic device 10 shown in FIG. 12 can also adopt the above-described preparation method. After forming the buffer layer 250, the surface of the buffer layer 250 can be treated using a patterning process, a texturing process, or a roughening process to form multiple first protruding structures 710. Alternatively, a patterning process, a texturing process, or a roughening process can be used to form multiple first protruding structures 710 on the surface of the buffer layer 250 that are independent of the buffer layer 250.

[0190] Furthermore, the first semiconductor layer 211 at the bottom wall of the second groove portion 402 can have a plurality of second protrusion structures 720, which are spaced apart from each other. The plurality of first protrusion structures 710 extend from the first semiconductor layer 211 toward the electrode metal layer 230, which not only further enhances the bond between the first semiconductor layer 211 and the electrode metal layer 230, but also enables the light reflected from the electrode metal layer 230 to be emitted more uniformly. Furthermore, the implementation of the second protrusion structure 720 can refer to the implementation of the first protrusion structure 710 and will not be described in detail here. It is understood that the first semiconductor layer 211 at the bottom wall of the first groove portion 401 can also have a plurality of second protrusion structures 720 to enhance bonding.

[0191] FIG13 is another schematic cross-sectional view of the structure along the AA' direction in FIG8. Referring to FIG13, the optoelectronic device in this embodiment is modified from the optoelectronic device in the above embodiment. The similarities are not repeated here. The difference is that: an angle β is formed between the sidewall of the semiconductor functional layer 210 and the first surface S1, and the angle β is toward the side of the semiconductor functional layer 210 and is set to an obtuse angle. This configuration allows the sidewall of the semiconductor functional layer 210 to be inclined, further reducing the stress formed on the electrode metal layer 230 and further reducing the risk of its fracture.

[0192] FIG14 is another schematic cross-sectional view of the structure along the AA' direction in FIG8 . Referring to FIG14 , the optoelectronic device in this embodiment is modified from the optoelectronic device in the above embodiment. The similarities are not described here. The difference is that the luminescent pixel 200 further includes a distributed Bragg reflector layer 610, which is disposed between the second dielectric layer 321 and the electrode metal layer 230 to further improve reflection efficiency. In some embodiments of the present application, the distributed Bragg reflector layer 610 also covers one or more dielectric layers among the second dielectric layer 321, the first dielectric layer 322, and the third dielectric layer 323. With this arrangement, when the electrode metal layer 230 is a metal layer, light first passes through the distributed Bragg reflector layer 610 before entering the electrode metal layer 230. After being reflected by the electrode metal layer 230, light enters the distributed Bragg reflector layer 610 and is finally reflected from one side of the distributed Bragg reflector layer 610. This can address the problem of insufficient reflection bandwidth of the distributed Bragg reflector layer 610 through the electrode metal layer 230, and can also address the problem of low luminous efficiency caused by the metal layer absorbing some light. It can be understood that the distributed Bragg reflector layer 610 forms a distributed Bragg reflector mirror (DBR) structure.

[0193] In some other embodiments of the present application, referring to FIG. 14 , the distributed Bragg reflector 610 may expose the second trench portion 402, the third contact hole 333, and the fourth contact hole 334. In other words, the distributed Bragg reflector 610 may extend between the first dielectric layer 322 and the electrode metal layer 230. Furthermore, the distributed Bragg reflector 610 may extend between the third dielectric layer 322 and the second electrode connection layer 521, and may extend to the fourth contact hole 334.

[0194] In addition, the distributed Bragg reflector 610 includes multiple first refractive index layers and multiple second refractive index layers, with the first and second refractive index layers alternating. One of the first and second refractive index layers is in contact with the second dielectric layer 321. Furthermore, the refractive index of a first refractive index layer is greater than the refractive index of an adjacent second refractive index layer. In a specific implementation, the number of first and second refractive index layers is the same, and the specific number can be determined based on the requirements of the actual application scenario. Furthermore, each first refractive index layer has the same refractive index and the same thickness. Furthermore, each second refractive index layer has the same refractive index and the same thickness. Of course, the thicknesses of different first and second refractive index layers can also vary, and this is not limited here. Furthermore, the method for preparing the optoelectronic device structure shown in FIG. 14 can also employ the above-described method, with the addition of a step for preparing the distributed Bragg reflector between FIG. 11c and FIG. 11d.

[0195] FIG15 is a schematic top view of another optoelectronic device provided in an embodiment of the present application, and FIG16 is a schematic cross-sectional view of another optoelectronic device taken along the AA' direction in FIG15. Referring to FIG15 and FIG16, the optoelectronic device in this embodiment is a modification of the optoelectronic device in the above embodiment, and the similarities therebetween are not reiterated herein. The difference is that: the light-emitting pixel includes a semiconductor functional layer 210 but does not include a current spreading layer 214. The surface of the second semiconductor layer 213 in the semiconductor functional layer 210 facing away from the light-emitting layer 212 can be set as the first surface S1, and the first electrode connection layer 221 directly contacts the second semiconductor layer 213 in the light-emitting pixel 200, thereby electrically connecting the first electrode connection layer 221 to the second semiconductor layer 213 in the light-emitting pixel 200. In some embodiments of the present application, if a boss structure 510 is provided in the optoelectronic device and the boss structure 510 has the same structure as the semiconductor functional layer 210, the surface of the second semiconductor layer 213 in the boss structure 510 facing away from the light-emitting layer 212 can be set as the second surface S2. The second electrode connection layer 521 directly contacts the second semiconductor layer 213 in the boss structure 510. In addition, the manufacturing method of the optoelectronic device 10 shown in Figures 15 and 16 can also adopt the above manufacturing method and directly omit the step shown in Figure 5b.

[0196] FIG17 is a schematic top view of another optoelectronic device provided in an embodiment of the present application. FIG18a is a schematic cross-sectional view taken along the AA' direction in FIG17 , and FIG18b is a schematic cross-sectional view taken along the AA' direction in FIG17 . Referring to FIG17 and FIG18b , the optoelectronic device in this embodiment is a modification of the optoelectronic device in the above embodiment. Similarities are not described here. The difference lies in that the outer boundary Y221 overlaps the outer boundary Y332, i.e., the first electrode connection layer 221 extends from the bottom wall of the third contact hole 333 along the sidewalls of the third contact hole 333 to the sidewalls of the second contact hole 332, and further extends along the sidewalls of the second contact hole 332 to the periphery of the opening of the second contact hole 332. A passivation layer 240 is provided between the first electrode connection layer 221 and the electrode metal layer 230. Furthermore, the periphery of the opening of the second contact hole 332 refers to a small portion of the edge of the opening of the second contact hole 332.

[0197] 18a, in the stacking direction F0, the first electrode pad layer 222 may cover the first electrode connection layer 221. Alternatively, referring to FIG18b, in the stacking direction F0, the first electrode connection layer 221 may cover the first electrode pad layer 222.

[0198] In addition, the manufacturing method of the structure of the optoelectronic device 10 shown in FIG. 17 and FIG. 18 a may also adopt the above-mentioned manufacturing method.

[0199] FIG19 is another schematic top view of the structure of the optoelectronic device provided in an embodiment of the present application, and FIG20 is a schematic cross-sectional view of the structure along the AA' direction in FIG19. Referring to FIG19 and FIG20, the optoelectronic device in this embodiment is modified from the optoelectronic device in the above embodiment, and the similarities are not repeated here. The difference is that the third dielectric layer 323 covers the second surface S2 of the boss structure 510, that is, the fourth contact hole 334 is not provided. In addition, the second electrode connection layer 521 covers the third dielectric layer 323, insulating the second electrode connection layer 521 from the boss structure 510. Furthermore, the orthographic projection of the passivation layer 240 on the substrate 100 also covers the orthographic projection of the boss structure 510 on the substrate 100. In addition, the preparation method of the structure of the optoelectronic device 10 shown in FIG19 and FIG20 can also adopt the above preparation method.

[0200] Figure 21 is another schematic diagram of the top view structure of the optoelectronic device provided in an embodiment of the present application, and Figure 22 is a schematic diagram of the cross-sectional structure along the AA' direction in Figure 21. Referring to Figures 22 and 21, the optoelectronic device in this embodiment is modified with respect to the optoelectronic device in the above embodiment, and the similarities are not repeated here. The difference is that the structure of the boss structure 510 is different from that of the semiconductor functional layer 210. Exemplarily, the boss structure 510 is a single-layer structure, and the boss structure 510 includes: one of a semiconductor material layer, an insulating material layer or a metal material layer. Alternatively, the boss structure 510 is a multi-layer structure, and the boss structure 510 includes: a combination of two or all of the semiconductor material layers, insulating material layers or metal material layers. In addition, the materials in the semiconductor material layer, insulating material layer or metal material layer can be the materials mentioned in this application, or other materials can be used without limitation. Furthermore, in order to improve the reliability of the electrode metal layer 230, the first semiconductor layer 211 can be extended into the gap between the boss structure 510 and the semiconductor functional layer 210, so that the first semiconductor layer 211, the boss structure 510 and the semiconductor functional layer 210 are enclosed to form a groove area 400. In addition, the first semiconductor layer 211 extends into the gap between adjacent boss structures 510, so that the first semiconductor layer 211 and the adjacent boss structures 510 are enclosed to form a groove area 400. In addition, the arrangement of the electrode metal layer 230 in the groove area 400 can refer to the arrangement in the above embodiment, and the details are not repeated here. In addition, the preparation method of the structure of the optoelectronic device 10 shown in Figures 21 and 22 can also adopt the above preparation method, and form a boss structure 510 that is different from the structure of the semiconductor functional layer 210.

[0201] Based on this, an embodiment of the present application further provides a light-emitting module. Referring to FIG23 , FIG23 is a schematic structural diagram of a light-emitting module provided in an embodiment of the present application. The light-emitting module includes: an optoelectronic device 10, a driving device 30, and an interconnection assembly 20. The interconnection assembly 20 is located between the optoelectronic device 10 and the driving device 30, and the driving device 30 is located on the side of the optoelectronic device 10 having multiple light-emitting pixels 200. The driving device 30 includes: a first driving pad 31 and a second driving pad 32 facing the side of the optoelectronic device 10. The interconnection assembly 20 includes a first interconnect structure 21 and a second interconnect structure 22 spaced apart from each other. A first end of the first interconnect structure 21 is connected to the first electrode pad layer 222 in the first electrode 220, a second end of the first interconnect structure 21 is connected to the first driving pad 31, a first end of the second interconnect structure 22 is connected to the second electrode pad layer 522 in the second electrode 520, and a second end of the second interconnect structure 22 is connected to the second driving pad 32.

[0202] Specifically, the driving device 30 can output corresponding voltages to the first driving pad 31 and the second driving pad 32 respectively. In addition, the number of the first driving pads 31 is the same as the number of the light-emitting pixels 200 and corresponds one to one, and the number of the second driving pads 32 is the same as the number of the boss structures 510 and corresponds one to one. In addition, the driving device 30 also includes a plurality of third driving pads (for example, 33, 34) connected to the circuit board 2, and the plurality of third driving pads (for example, 33, 34) may include power supply electrode pads, ground electrode pads, and driving electrode pads for transmitting driving signals. Exemplarily, the driving device 30 can be set as a driving chip. Alternatively, the driving device 30 can also be a driving substrate provided with a plurality of pixel circuits and a common electrode, and the plurality of pixel circuits are connected one to one to the first driving pads 31, outputting relative voltages to the first driving pads 31, and the second driving pads 32 are connected to the common electrode.

[0203] Furthermore, the number of first interconnect structures 21 is the same as the number of light-emitting pixels 200 and corresponds one-to-one, and the number of second interconnect structures 22 is the same as the number of boss structures 510 and corresponds one-to-one. Furthermore, each first interconnect structure 21 and each second interconnect structure 22 are spaced apart from each other. Furthermore, the first end of the first interconnect structure 21 is connected to the first electrode pad layer 222 in the corresponding first electrode 220, and the second end of the first interconnect structure 21 is connected to the corresponding first drive pad 31, so that the driving device outputs a first voltage to the first electrode 220 through the first drive pad 31 and the first interconnect structure 21. Furthermore, the first end of the second interconnect structure 22 is connected to the second electrode pad layer 522 in the corresponding second electrode 520, and the second end of the second interconnect structure 22 is connected to the second drive pad 32, so that the driving device outputs a second voltage to the second electrode 520 through the second drive pad 32 and the second interconnect structure 22. Exemplarily, the first interconnect structure 21 and the second interconnect structure 22 can be metal interconnect structures, such as bumps, including micro bumps, copper pillar bumps (CPB), etc. In addition, the materials of the first interconnect structure 21 and the second interconnect structure 22 respectively include one or more materials selected from Au, Cu, Ni, Ag, and Sn. The materials of the first interconnect structure 21 and the second interconnect structure 22 each include at least one bonding metal layer (e.g., Sn, SnAg, AuSn, etc.). In addition, the structures of the first interconnect structure 21 and the second interconnect structure 22 are the same.

[0204] In addition, in the present application, the second electrode 520 is connected to the electrode metal layer, so that the second voltage transmitted by the second electrode 520 can be input into the first semiconductor layer 211 of the light-emitting pixel 200. The second semiconductor layer 213 of the light-emitting pixel 200 is connected to the first electrode 220 through the current spreading layer 214. The first voltage transmitted by the first electrode 220 is input into the second semiconductor layer 213, thereby driving the light-emitting layer 212 to emit light. Therefore, not only is the second electrode 520 formed on the second surface S2 of the boss structure 510, but the electrode metal layer 230 connected to the first semiconductor layer 211 of each light-emitting pixel 200 is also formed in the groove region 400, eliminating the need to form additional electrodes connected to the first semiconductor layer 211 in the light-emitting pixel 200. With this arrangement, only the same number of first interconnect structures 21 as the number of light-emitting pixels 200 and the same number of second interconnect structures 22 as the number of boss structures 510 need to be prepared to interconnect the driver device 30 with the optoelectronic device 10, thereby reducing the location of interconnection points and reducing process difficulty.

[0205] Furthermore, in the optoelectronic device 10 of the present application, the difference between the first vertical distance h1 and the second vertical distance h2 is less than or equal to the difference threshold, thereby minimizing the difference between the first vertical distance h1 and the second vertical distance h2. This configuration allows the second electrode 520 and the first electrode 220 to be formed on the same plane as much as possible, thereby minimizing the difference between the length of the first interconnect structure 21 and the length of the second interconnect structure 22, thereby reducing the risk of device failure and improving the reliability of the interconnection between the optoelectronic device 10 and the driver device.

[0206] 23 , the surface of the buffer layer 250 facing away from the interconnection component 20 may also be roughened to change the angle between the outgoing light and the interface, reduce the occurrence of total reflection, improve light extraction efficiency, and avoid light refraction back and forth within the light-emitting element.

[0207] FIG24 is another structural schematic diagram of the light-emitting module provided in an embodiment of the present application. Referring to FIG24 , the optoelectronic device in this embodiment is modified with respect to the optoelectronic device in the above embodiment. The similarities are not repeated here. The difference is that an underfill structure layer 910 is also filled between the optoelectronic device 10 and the driver device 30, that is, the interconnection component 20 is arranged in the underfill structure layer 910. The optoelectronic device 10, the interconnection component 20 and the driver device 30 are protected by the underfill structure layer 910, thereby further improving the reliability of the light-emitting module 1 and avoiding stress damage. Exemplarily, the material of the underfill structure layer 910 includes a polymer material and filler particles. The polymer material includes, but is not limited to, resin, etc., and the filler material includes, but is not limited to, SiO2, TiO2, etc. In a specific implementation, the physical properties of the material of the underfill structure layer 910 can be adjusted according to different particle sizes and mixing ratios.

[0208] In some examples, taking the structure of the light-emitting module shown in FIG. 24 as an example, the method for preparing the light-emitting module provided in an embodiment of the present application may include the following: preparing the optoelectronic device 10 and the driver device 30 separately. Then, preparing the first interconnection structure 21 and the second interconnection structure 22 on the driver device 30 side or the optoelectronic device 10 side, or simultaneously preparing the first interconnection structure 21 and the second interconnection structure 22 on the driver device 30 side and the optoelectronic device 10 side. Then, using a thermocompression bonding process, a reflow process, or a direct bond interconnect (DBI) process, the optoelectronic device 10 and the driver device 30 are electrically connected together through the first interconnection structure 21 and the second interconnection structure 22. Then, filling the gap between the optoelectronic device 10 and the driver device 30 with an underfill material to form an underfill structure layer 910. Then, removing the substrate 100 supporting the optoelectronic device 10, or thinning the substrate 100 supporting the optoelectronic device 10, or setting an opening in the area of ​​the substrate 100 supporting the optoelectronic device 10 corresponding to the light-emitting pixel 200. Furthermore, after removing the substrate 100 carrying the optoelectronic device 10, an optical conversion layer can also be prepared on the surface of the buffer layer 250 facing away from the driving device. The optical conversion layer includes but is not limited to a fluorescent conversion layer (for example, one or a combination of a red light fluorescent conversion layer, a green light fluorescent conversion layer, and a blue light fluorescent conversion layer) or a quantum dot conversion layer (for example, one or a combination of a red light quantum dot conversion layer, a green light quantum dot conversion layer, and a blue light quantum dot conversion layer).

[0209] In some other examples, taking the structure of the light-emitting module shown in Figure 24 as an example, the preparation method of the light-emitting module provided in the embodiment of the present application may include the following contents: preparing the optoelectronic device 10 and the driving device separately. Then, preparing the first interconnection structure 21 and the second interconnection structure 22 on the driving device side or the optoelectronic device 10 side, or simultaneously preparing the first interconnection structure 21 and the second interconnection structure 22 on the driving device side and the optoelectronic device 10 side. Then, applying an underfill film on the surface of the driving device or the optoelectronic device 10. Then, using a hot pressing bonding process, a reflow process or a direct bond interconnect (DBI) process, the optoelectronic device 10 and the driving device are electrically connected together through the first interconnection structure 21 and the second interconnection structure 22. Then, the substrate 100 carrying the optoelectronic device 10 is removed, or the substrate 100 carrying the optoelectronic device 10 can be thinned, or an opening can be set in the area of ​​the substrate 100 carrying the optoelectronic device 10 corresponding to the light-emitting pixel 200. Furthermore, after removing the substrate 100 carrying the optoelectronic device 10, an optical conversion layer can also be prepared on the surface of the buffer layer 250 facing away from the driving device. The optical conversion layer includes but is not limited to a fluorescent conversion layer (for example, one or a combination of a red light fluorescent conversion layer, a green light fluorescent conversion layer, and a blue light fluorescent conversion layer) or a quantum dot conversion layer (for example, one or a combination of a red light quantum dot conversion layer, a green light quantum dot conversion layer, and a blue light quantum dot conversion layer).

[0210] Based on the content described in the above embodiment 1, the embodiment of the present application further provides another optoelectronic device, which is described in detail below in conjunction with the embodiment 2.

[0211] Example 2:

[0212] Generally, the light generated by the light-emitting layer of the light-emitting pixel is randomly emitted in various directions, of which some light is emitted from the light-emitting surface of the light-emitting pixel, and some is emitted from the non-light-emitting surface of the light-emitting pixel. If the light from the non-light-emitting surface cannot be effectively utilized, it will not only cause energy loss, but also reduce the light extraction efficiency of the light-emitting array. To this end, an embodiment of the present application provides an optoelectronic device, which can effectively increase the reflection area by providing a first reflective layer and a second reflective layer, so that as much light as possible emitted by the light-emitting pixel toward the non-light-emitting surface can be reflected to the light-emitting surface, thereby improving the light extraction efficiency of the device.

[0213] The optoelectronic device provided in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0214] Figure 25 is a schematic top view of another optoelectronic device provided in an embodiment of the present application. Figure 26a is a schematic cross-sectional view of Figure 25 along the AA' direction, Figure 26b is a schematic cross-sectional view of Figure 25 along the BB' direction, and Figure 26c is a schematic cross-sectional view of Figure 25 along the CC' direction. Referring to Figures 25 to 26c, the optoelectronic device 10 includes: a plurality of light-emitting pixels 200, a trench region 400, and a first reflective layer. Each light-emitting pixel 200 includes a semiconductor functional layer 210 and a first electrode 220. Each semiconductor functional layer 210 includes a stacked first semiconductor layer 211, a light-emitting layer 212, and a second semiconductor layer 213. Furthermore, the first reflective layer 810 covers at least a portion of each light-emitting pixel and at least a portion of the trench region. Furthermore, the first electrode 220 is insulated from the first reflective layer 810, allowing the first electrode 220 to input a first voltage to the second semiconductor layer 213. With this arrangement, the first reflective layer 810 is used to reflect as much light as possible emitted from the semiconductor functional layer 210 toward its sidewalls and the first electrode 220 to the light-emitting surface, thereby improving the light-emitting efficiency of the device.

[0215] Referring to Figures 26a to 26c, a groove region 400 is formed in the semiconductor functional layer 210. The groove region 400 can be used to isolate the multiple light-emitting pixels 200 from each other. The groove region 400 can include a first groove portion 401 and a second groove portion 402. The first reflective layer 810 also covers at least a portion of the first groove portion 401. This configuration allows the first reflective layer 810 to reflect as much light incident on the first groove portion 401 as possible to the light-emitting surface, thereby improving the light extraction efficiency of the device.

[0216] For example, the first reflective layer 810 may cover the entire bottom wall of the first groove portion 401 , or the first reflective layer 810 may cover a portion of the bottom wall of the first groove portion 401 , which is not limited herein.

[0217] 26a to 26c , a second reflective layer 820 is further included, and the second reflective layer 820 covers at least a portion of the second groove portion 402. With this configuration, the second reflective layer 820 can reflect as much light incident into the second groove portion 402 as possible to the light-emitting surface, thereby improving the light extraction efficiency of the device.

[0218] For example, the second reflective layer 820 may cover the entire bottom wall of the second groove portion 402 , or the second reflective layer 820 may cover a portion of the bottom wall of the second groove portion 402 , which is not limited herein.

[0219] Exemplarily, the first groove portion 401 is located between adjacent light-emitting pixels 200, and the first groove portion 401 also surrounds and communicates with the second groove portion 402. This configuration allows the electrode metal layer 230 to extend within the first groove portion 401 and the second groove portion 402. It is understood that the implementation of the first groove portion 401 and the second groove portion 402 in this embodiment can refer to the implementation of the first groove portion 401 and the second groove portion 402 in the above embodiment, and will not be described in detail here.

[0220] In addition, the first reflective layer 810 covers the side wall of the semiconductor functional layer 210, and the first reflective layer 810 is also extended along the side wall of the semiconductor functional layer 210 to the side of the semiconductor functional layer 210 facing the first electrode 220. The first reflective layer 810 also encloses a contact hole 330 on the side of the semiconductor functional layer 210 facing the first electrode 220, and the first electrode 220 is electrically connected to the second semiconductor layer 213 through the contact hole 330.

[0221] In some embodiments of the present application, the proportion of the first groove portion 401 in the groove area 400, the proportion of the second groove portion 402 in the groove area 400, the coverage area of ​​the electrode metal layer 230 can account for a percentage of the total area of ​​the entire optoelectronic device, the proportion of the area of ​​the first electrode metal layer 230 portion in the total area of ​​the electrode metal layer 230, and the proportion of the area of ​​the second electrode metal layer 230 portion in the total area of ​​the electrode metal layer 230 can also satisfy the numerical relationships in the above embodiments, and the details are not repeated here.

[0222] 26a to 26c , the first reflective layer 810 may include a stacked first metal layer 811 and a distributed Bragg reflector 812. The distributed Bragg reflector 812 is disposed between the first metal layer 811 and the semiconductor functional layer 210. With this configuration, light first passes through the distributed Bragg reflector 812 before entering the first metal layer 811. After being reflected by the first metal layer 811, it enters the distributed Bragg reflector 812 and is finally reflected from one side of the distributed Bragg reflector 812. This can address the problem of insufficient reflection bandwidth of the distributed Bragg reflector 812 through the first metal layer 811, and also address the problem of low luminous efficiency caused by the metal layer absorbing some light. It is understood that the distributed Bragg reflector 812 forms a distributed Bragg reflector (DBR) structure.

[0223] It is understood that the implementation of the first metal layer 811 in this embodiment can refer to the implementation of the electrode metal layer 230 in the above embodiment, and will not be described in detail here. In addition, the implementation of the distributed Bragg reflector in this embodiment can refer to the implementation of the distributed Bragg reflector in the above embodiment, and will not be described in detail here.

[0224] In some embodiments of the present application, referring to FIG. 25 to FIG. 26 c , the contact via 330 includes a second contact hole 332 and a third contact hole 333. The first metal layer 811 extends to cover the first surface S1 and encloses the first surface S1 to form the second contact hole 332. The distributed Bragg reflector layer 812 extends to cover the first surface S1 and encloses the inner side of the second contact hole 332 to form the third contact hole 333. It is understood that the implementation of the second contact hole 332 and the third contact hole 333 can refer to the implementation of the second contact hole 332 and the third contact hole 333 in the above embodiments, and will not be described in detail here.

[0225] In some embodiments of the present application, referring to Figures 26a to 26c, the luminescent pixel 200 further includes a second dielectric layer 321. The second dielectric layer 321 is located between the distributed Bragg reflector layer 812 and the semiconductor functional layer 210. The second dielectric layer 321 covers the sidewalls of the semiconductor functional layer 210 and extends along the sidewalls of the semiconductor functional layer 210 to the third contact hole 333. It is understood that the implementation of the second dielectric layer 321 and the third contact hole 333 can refer to the implementation of the second dielectric layer 321 and the third contact hole 333 in the above embodiments, and will not be described in detail here.

[0226] In some embodiments of the present application, referring to Figures 26a to 26c, a first dielectric layer 322 is disposed between the first reflective layer 810 and the bottom wall of the first groove portion 401. It is understood that the implementation of the first dielectric layer 322 in this embodiment can refer to the implementation of the first dielectric layer 322 in the above embodiments, and will not be described in detail here.

[0227] In some embodiments of the present application, referring to Figures 26a to 26c, the second reflective layer 820 includes a second metal layer 821, and the first metal layer 811 is interconnected with the second metal layer 821. It is understood that the implementation of the second metal layer 821 can refer to the implementation of the electrode metal layer 230 in the second groove portion 402 in the above embodiment, and will not be described in detail here.

[0228] In some embodiments of the present application, referring to FIG26a , the portion of the first metal layer 811 extending along the first dielectric layer 322 to the bottom wall of the second trench portion 402 is stepped. It is understood that the implementation of this stepped shape can refer to the implementation of the stepped shape in the above embodiment and will not be described in detail here.

[0229] In some embodiments of the present application, referring to FIG. 26 a to FIG. 26 c , the second metal layer 821 and the first metal layer 811 are formed using the same film layer.

[0230] In some embodiments of the present application, referring to Figures 26a to 26c, the groove region 400 is arranged in a grid pattern, and at least some of the grid intersections in the grid pattern are provided with second groove portions 402, or at least some of the grid lines in the grid pattern are provided with second groove portions 402. It is understood that the implementation of the second groove portions 402 in the grid pattern can refer to the implementation of the second groove portions 402 in the grid pattern 420 in the above embodiment, and will not be described in detail here.

[0231] In some embodiments of the present application, referring to Figures 26a to 26c, the semiconductor functional layer 210 further includes a current spreading layer 214, which is disposed on the second semiconductor layer 213. The current spreading layer 214 may be a transparent conductive layer, and the average refractive index of the current spreading layer 214 and the second dielectric layer 321 is less than the refractive index of the first semiconductor layer 211 and the refractive index of the second semiconductor layer 213. It is understood that the implementation of the current spreading layer 214 can refer to the implementation of the current spreading layer 214 in the above embodiments, and will not be described in detail here.

[0232] In some embodiments of the present application, referring to FIG. 26 a to FIG. 26 c , the portion of the first metal layer 811 extending from the sidewall of the semiconductor functional layer 210 to the first surface S1 has a double-step shape.

[0233] In some embodiments of the present application, the second semiconductor layer has a first region and a second region on a surface facing away from the light-emitting layer. The first region surrounds the second region, the current spreading layer 214 covers the second region, the second dielectric layer 321 also covers the first region, and the electrode metal layer 230 also covers the second dielectric layer 321 located on the first region. It is understood that this embodiment can refer to the embodiment described above and will not be described in detail here.

[0234] In some embodiments of the present application, referring to Figures 26a to 26c, the first electrode 220 includes a first electrode connection layer 221 and a first electrode pad layer 222 that are connected to each other, the first electrode connection layer 221 is arranged between the first electrode pad layer 222 and the semiconductor functional layer 210, and the first electrode connection layer 221 is electrically connected to the second semiconductor layer 213 through the second contact hole 332 and the third contact hole 333.

[0235] In some embodiments of the present application, in the stacking direction of the light-emitting layer and the second semiconductor layer, the distance between the outer boundary of the first electrode connection layer and the outer boundary of the second contact hole is greater than zero. In the stacking direction of the light-emitting layer and the second semiconductor layer, the first electrode connection layer covers the second contact hole, or in the stacking direction of the light-emitting layer and the second semiconductor layer, the first electrode connection layer is disposed within the second contact hole. It is understood that the implementation of the outer boundary of the first electrode connection layer and the outer boundary of the second contact hole can refer to the implementation of the outer boundary of the first electrode connection layer and the outer boundary of the second contact hole in the above embodiments, and will not be repeated here.

[0236] In some embodiments of the present application, referring to FIG. 26 a to FIG. 26 c , the first electrode pad layer 222 covers the second contact hole 332 , and a passivation layer is provided between the first electrode pad layer 222 and the electrode metal layer 230 .

[0237] In some embodiments of the present application, referring to Figures 26a to 26c, the cross-section of the first electrode connection layer 221 in the stacking direction F0 has a first groove AX1, and a portion of the first electrode pad layer 222 fills the first groove AX1. The stacking direction F0 is perpendicular to the plane of the substrate 100.

[0238] It is understandable that the implementation of the first electrode connection layer 221 and the first electrode pad layer 222 in this embodiment can refer to the implementation of the first electrode connection layer 221 and the first electrode pad layer 222 in the above embodiment, and will not be repeated here.

[0239] In some embodiments of the present application, referring to Figures 25 and 26a, the optoelectronic device also includes one or more boss structures 510 and a second electrode 520, the boss structure 510 is spaced apart from the light-emitting pixel 200, the boss structure 510 has a second surface S2, the second electrode 520 is arranged on the second surface S2, and the second electrode 520 is interconnected with the first metal layer 811 and the second metal layer 821.

[0240] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , the second electrode 520 includes a second electrode connection layer 521 and a second electrode pad layer 522 connected to each other, and the second electrode connection layer 521 is disposed between the second electrode pad layer 522 and the platform structure 510. Furthermore, the second electrode connection layer 521 covers at least a portion of the second surface S2 and at least a portion of the sidewall of the platform structure 510.

[0241] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , the second electrode connection layer 521 covers the entire sidewall of the boss structure 510 .

[0242] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , the second electrode connection layer 521 covers the entire area of ​​the second surface S2 .

[0243] In some embodiments of the present application, referring to Figures 25 and 26a, a third dielectric layer 323 is arranged between the second electrode connection layer 521 and the boss structure 510. The third dielectric layer 323 covers the sidewalls of the boss structure 510. The third dielectric layer 323 also extends to the second surface S2 and encloses a fourth contact hole 334 on the second surface S2. The second electrode connection layer 521 contacts the second surface S2 through the fourth contact hole 334.

[0244] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , the second electrode pad layer 522 covers the fourth contact hole 334 .

[0245] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , a cross-section of the second electrode connection layer 521 in the stacking direction F0 has a second groove AX2 , and a portion of the second electrode pad layer 522 fills the second groove AX2 .

[0246] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , a third dielectric layer 323 is provided between the second electrode connection layer 521 and the boss structure 510 . The third dielectric layer 323 covers the sidewalls of the boss structure 510 , and the second dielectric layer 321 also covers the second surface S2 .

[0247] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , the second electrode connection layer 521 and the first metal layer 811 are formed using the same film layer.

[0248] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , the first dielectric layer 322 , the second dielectric layer 321 , and the third dielectric layer are formed using the same film layer.

[0249] In some embodiments of the present application, the boss structure 510 is a single-layer structure, and the boss structure 510 includes: a semiconductor material layer, an insulating material layer, or a metal material layer.

[0250] In some embodiments of the present application, the boss structure 510 is a multi-layer structure, and the boss structure 510 includes: a semiconductor material layer, an insulating material layer, or a combination of a metal material layer.

[0251] In some embodiments of the present application, referring to FIG. 25 and FIG. 26 a , the boss structure 510 is a multi-layer structure, and the boss structure includes a semiconductor functional layer, or the boss structure includes a semiconductor functional layer and a current spreading layer 214 disposed on the semiconductor functional layer.

[0252] It is understandable that the implementation of the boss structure 510 and the second electrode 520 in this embodiment can refer to the implementation of the boss structure 510 and the second electrode 520 in the above embodiments, and will not be described in detail here.

[0253] Based on this, an embodiment of the present application further provides a light-emitting module, referring to Figures 23 and 24 , which includes: an optoelectronic device 10, a driver device 30, and an interconnection assembly 20, wherein the driver device 30 is located on a side of the optoelectronic device 10 having multiple light-emitting pixels, and the driver device 30 includes a first driving pad 31. The interconnection assembly 20 is located between the optoelectronic device 10 and the driver device 30, and the interconnection assembly 20 includes a first interconnection structure 21. Furthermore, a first end of the first interconnection structure 21 is connected to the first electrode 220, and a second end of the first interconnection structure 21 is connected to the first driving pad 31.

[0254] In some embodiments of the present application, referring to FIG. 25 to FIG. 26 c , the optoelectronic device 10 further includes a boss structure 510 and a second electrode 520 located on the substrate 100, the driving device 30 further includes a second driving pad 32, and the interconnection assembly 20 further includes a second interconnect structure 22. Furthermore, a first end of the second interconnect structure 22 is connected to the second electrode 520, and a second end of the second interconnect structure 22 is connected to the second driving pad 32.

[0255] It is understandable that the preparation method of the optoelectronic device in this embodiment can also refer to the preparation method in the above embodiments, and will not be described in detail here.

[0256] It is worth mentioning that the various implementation methods in Example 2 may not depend on the implementation method in Example 1, and may also be other implementable methods, which are not specifically limited here.

[0257] Based on the contents described in Example 1 and Example 2, the embodiments of the present application further provide another optoelectronic device, which will be described in detail below in conjunction with Example 3.

[0258] Example 3:

[0259] Generally, light-emitting pixels need to input voltage through contact electrodes. If the transition between the two planes of the contact electrodes is not smooth enough, it is easy to cause the risk of the contact electrodes breaking, causing some light-emitting pixels to fail. To this end, an embodiment of the present application provides an optoelectronic device. By providing an electrode metal layer 230, extending the electrode metal layer 230 to the contact electrode and connecting it to the contact electrode, and making the portion of the electrode metal layer 230 extending to the contact electrode in a step-like shape, the risk of the electrode metal layer 230 breaking can be reduced and reliability can be improved. In addition, by connecting the electrode metal layer 230 to the contact electrode, the conductive area of ​​the contact electrode can be increased, the voltage drop of the contact electrode can be reduced, and the contact electrode can be made to withstand higher currents.

[0260] The optoelectronic device provided in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0261] FIG27 is a schematic top view of another optoelectronic device provided in an embodiment of the present application, FIG28a is a schematic cross-sectional view taken along the AA' direction in FIG27, FIG28b is a schematic cross-sectional view taken along the BB' direction in FIG27, and FIG28c is a schematic cross-sectional view taken along the CC' direction in FIG27. Referring to FIG27 to FIG28c, the optoelectronic device 10 includes: a plurality of light-emitting pixels 200, a groove region 400, and an electrode metal layer 230, wherein each light-emitting pixel 200 includes a semiconductor functional layer 210 and a first electrode 220, and each semiconductor functional layer 210 includes a first semiconductor layer 211, a light-emitting layer 212, and a second semiconductor layer 213 arranged in a stacked manner, wherein the second semiconductor layer 213 is electrically connected to the first electrode 220, and the electrode metal layer 230 is electrically connected to the second electrode.

[0262] Furthermore, a trench region 400 is formed in the semiconductor functional layer 210 and can be used to isolate the multiple light-emitting pixels 200 from each other. The trench region 400 may include a first trench portion 401 and a second trench portion 402. The electrode metal layer 230 covers at least a portion of the surface of each light-emitting pixel 200, at least a portion of the first trench portion 401, and at least a portion of the second trench portion 402. Furthermore, the electrode metal layer 230 is insulated from the semiconductor functional layer in the first trench portion 401 and electrically connected to the first semiconductor layer 211 in the second trench portion 402. Furthermore, a first dielectric layer 322 is disposed between the electrode metal layer 230 and the bottom wall of the first trench portion 401. Furthermore, the portion of the electrode metal layer 230 extending from the first dielectric layer 322 to the bottom wall of the second trench portion 402 is stepped, which reduces the risk of fracture of the electrode metal layer 230 and improves reliability.

[0263] It is understood that the implementation of the first dielectric layer 322 and the electrode metal layer 230 in this embodiment can refer to the implementation of the first dielectric layer 322 and the electrode metal layer 230 in the above embodiment, and the details are not repeated here. In addition, the implementation of the contact electrode 830 in this embodiment can refer to the implementation of the second metal layer 821 in the above embodiment, and the details are not repeated here.

[0264] In some embodiments of the present application, referring to FIG. 27 to FIG. 28 c , in the stacking direction, the semiconductor functional layer 210 adjacent to the second trench portion 402 has an escape recess on a side facing the second trench portion 402. It is understood that the implementation of the escape recess in this embodiment can refer to the implementation of the escape recess in the above embodiments, and the details are not repeated here.

[0265] In some embodiments of the present application, referring to FIG. 27 to FIG. 28 c , the shape of the avoidance recess is the same as the shape of the corresponding position of the second groove portion 402 .

[0266] In some embodiments of the present application, the proportion of the first groove portion 401 in the groove area 400, the proportion of the second groove portion 402 in the groove area 400, the coverage area of ​​the electrode metal layer 230 can account for a percentage of the total area of ​​the entire optoelectronic device, the proportion of the area of ​​the first electrode metal layer 230 portion in the total area of ​​the electrode metal layer 230, and the proportion of the area of ​​the second electrode metal layer 230 portion in the total area of ​​the electrode metal layer 230 can also satisfy the numerical relationships in the above embodiments, and the details are not repeated here.

[0267] In some embodiments of the present application, referring to FIG. 27 , the groove region 400 is in a grid pattern, and at least some of the grid intersections in the grid pattern are provided with second groove portions 402, or at least some of the grid lines in the grid pattern are provided with second groove portions 402. It is understood that the implementation of the grid pattern 420 in this embodiment can refer to the implementation of the grid pattern 420 in the above embodiments, and the details are not repeated here.

[0268] In some embodiments of the present application, an angle is formed between the sidewall of the semiconductor functional layer 210 and the first surface S1. The angle is toward the side of the semiconductor functional layer 210 and is an obtuse angle or a right angle. It is understood that the implementation of the angle in this embodiment can refer to the implementation of the angle in the above embodiments, and the details are not repeated here.

[0269] In some embodiments of the present application, referring to FIG. 28 a to FIG. 28 c , the electrode metal layer 230 covers part or all of the sidewalls of the semiconductor functional layer 210 .

[0270] In some embodiments of the present application, referring to Figures 28a to 28c, the electrode metal layer 230 extends to cover the first surface S1 and encloses a second contact hole 332 on the first surface S1. The second dielectric layer 321 extends to cover the first surface S1 and encloses a third contact hole 333 inside the second contact hole 332. Furthermore, the first electrode 220 is electrically connected to the second semiconductor layer 213 through the second contact hole 332 and the third contact hole 333, and the first electrode 220 is insulated from the electrode metal layer 230. It is understood that the implementation of the second contact hole 332 and the third contact hole 333 in this embodiment can refer to the implementation of the second contact hole 332 and the third contact hole 333 in the above embodiments, and the details are not repeated here.

[0271] In some embodiments of the present application, referring to Figures 28a to 28c, the portion of the electrode metal layer 230 extending from the sidewall of the semiconductor functional layer 210 to the first surface S1 is double-stepped. It is understood that the implementation of the double-stepped shape in this embodiment can refer to the implementation of the double-stepped shape in the above embodiments, and the details are not repeated here.

[0272] In some embodiments of the present application, referring to Figures 28a to 28c, the semiconductor functional layer 210 further includes a current spreading layer 214, which is disposed on the second semiconductor layer 213. The second semiconductor layer has a first region and a second region on a surface facing away from the light-emitting layer. The first region surrounds the second region, and the current spreading layer 214 covers the second region. The second dielectric layer 321 also covers the first region, and the electrode metal layer 230 also covers the second dielectric layer 321 located on the first region. It is understood that this embodiment can refer to the embodiment described in the above embodiment, and will not be described in detail here.

[0273] In some embodiments of the present application, referring to Figures 28a to 28c, the first electrode 220 includes a first electrode connection layer 221 and a first electrode pad layer 222 that are connected to each other. The first electrode connection layer 221 is disposed between the first electrode pad layer 222 and the semiconductor functional layer 210. The first electrode connection layer 221 is electrically connected to the second semiconductor layer 213 through the second contact hole 332 and the third contact hole 333. It is understood that the implementation of the first electrode connection layer 221 and the first electrode pad layer 222 in this embodiment can refer to the implementation of the first electrode connection layer 221 and the first electrode pad layer 222 in the above embodiments, and the specific details are not repeated here.

[0274] In some embodiments of the present application, in the stacking direction of the light-emitting layer and the second semiconductor layer, the distance between the outer boundary of the first electrode connection layer and the outer boundary of the second contact hole is greater than zero. In the stacking direction of the light-emitting layer and the second semiconductor layer, the first electrode connection layer covers the second contact hole, or in the stacking direction of the light-emitting layer and the second semiconductor layer, the first electrode connection layer is disposed within the second contact hole. It is understood that the implementation of the outer boundary of the first electrode connection layer and the outer boundary of the second contact hole can refer to the implementation of the outer boundary of the first electrode connection layer and the outer boundary of the second contact hole in the above embodiments, and will not be repeated here.

[0275] In some embodiments of the present application, referring to Figures 28a to 28c, the first electrode pad layer 222 covers the second contact hole 332, and a passivation layer is provided between the first electrode pad layer 222 and the electrode metal layer 230. It is understood that the implementation of the first electrode pad layer 222 in this embodiment can refer to the implementation of the first electrode pad layer 222 in the above embodiments, and the details are not repeated here.

[0276] In some embodiments of the present application, referring to Figures 28a to 28c, a cross-section of the first electrode connection layer 221 in the stacking direction F0 has a first groove AX1, and a portion of the first electrode pad layer 222 fills the first groove AX1. The stacking direction F0 is perpendicular to the plane of the substrate 100. It is understood that the implementation of the first groove AX1 in this embodiment can refer to the implementation of the first groove AX1 in the above embodiments, and the details are not repeated here.

[0277] In some embodiments of the present application, the light-emitting pixel further includes a distributed Bragg reflector layer 812, which is disposed between the electrode metal layer 230 and the second dielectric layer 321. It is understood that the implementation of the distributed Bragg reflector layer 812 in this embodiment can refer to the implementation of the distributed Bragg reflector layer 812 in the above embodiments, and the details are not repeated here.

[0278] In some embodiments of the present application, the distributed Bragg reflective layer 812 covers the first dielectric layer 322 , and the distributed Bragg reflective layer 812 exposes the second trench portion 402 and the third contact hole 333 .

[0279] In some embodiments of the present application, referring to Figures 27 and 28a, the optoelectronic device also includes one or more boss structures 510 and a second electrode 520, the boss structure 510 is spaced apart from the light-emitting pixel 200, the boss structure 510 has a second surface S2, the second electrode 520 is arranged on the second surface S2, and the second electrode 520 is interconnected with the electrode metal layer 230.

[0280] In some embodiments of the present application, referring to FIG. 27 and FIG. 28 a , the second electrode 520 includes a second electrode connection layer 521 and a second electrode pad layer 522 connected to each other, and the second electrode connection layer 521 is disposed between the second electrode pad layer 522 and the platform structure 510. Furthermore, the second electrode connection layer 521 covers at least a portion of the second surface S2, and the second electrode connection layer 521 also covers at least a portion of the sidewall of the platform structure 510. It is understood that the implementation of the second electrode connection layer 521 and the second electrode pad layer 522 in this embodiment can refer to the implementation of the second electrode connection layer 521 and the second electrode pad layer 522 in the above-mentioned embodiments, and the specific details are not repeated here.

[0281] In some embodiments of the present application, referring to FIG. 27 and FIG. 28 a , the second electrode connection layer 521 covers the entire sidewall of the boss structure 510 .

[0282] In some embodiments of the present application, referring to FIG. 27 and FIG. 28 a , the second electrode connection layer 521 covers the entire area of ​​the second surface S2 .

[0283] In some embodiments of the present application, referring to Figures 27 and 28a, a third dielectric layer 323 is arranged between the second electrode connection layer 521 and the boss structure 510. The third dielectric layer 323 covers the sidewalls of the boss structure 510. The third dielectric layer 323 also extends to the second surface S2 and encloses a fourth contact hole 334 on the second surface S2. The second electrode connection layer 521 contacts the second surface S2 through the fourth contact hole 334.

[0284] In some embodiments of the present application, referring to FIG. 27 and FIG. 28 a , the second electrode pad layer 522 covers the fourth contact hole 334 .

[0285] In some embodiments of the present application, referring to FIG. 28 a , a cross-section of the second electrode connection layer 521 in the stacking direction F0 has a second groove AX2, and a portion of the second electrode pad layer 522 fills the second groove AX2. It is understood that the implementation of the second groove AX2 in this embodiment can refer to the implementation of the second groove AX2 in the above embodiments, and the details are not repeated here.

[0286] In some embodiments of the present application, referring to Figures 27 and 28a, a third dielectric layer 323 is disposed between the second electrode connection layer 521 and the boss structure 510. The third dielectric layer 323 covers the sidewalls of the boss structure 510, and the second dielectric layer 321 also covers the second surface S2. It is understood that the implementation of the second dielectric layer 321 in this embodiment can refer to the implementation of the second dielectric layer 321 in the above embodiments, and the details are not repeated here.

[0287] In some embodiments of the present application, referring to FIG. 27 and FIG. 28 a , the first dielectric layer 322 , the second dielectric layer 321 , and the third dielectric layer are formed using the same film layer.

[0288] In some embodiments of the present application, referring to FIG. 27 and FIG. 28 a , the second electrode connection layer 521 and the electrode metal layer 230 are formed using the same film layer. It is understood that the implementation of the second electrode connection layer 521 and the electrode metal layer 230 in this embodiment can refer to the implementation of the second electrode connection layer 521 and the electrode metal layer 230 in the above-mentioned embodiments, and the details are not repeated here.

[0289] In some embodiments of the present application, the platform structure 510 is a single-layer structure, and the platform structure 510 includes: a semiconductor material layer, an insulating material layer, or a metal material layer. It is understood that the implementation of the platform structure 510 in this embodiment can refer to the implementation of the platform structure 510 in the above embodiment, and the details are not repeated here.

[0290] In some embodiments of the present application, the platform structure 510 is a multi-layer structure, and the platform structure 510 includes: a semiconductor material layer, an insulating material layer, or a combination of metal material layers. It is understood that the implementation of the platform structure 510 in this embodiment can refer to the implementation of the platform structure 510 in the above embodiments, and the details are not repeated here.

[0291] In some embodiments of the present application, referring to FIG. 28 a , the platform structure 510 is a multi-layer structure, and the platform structure includes a semiconductor functional layer, or the platform structure includes a semiconductor functional layer and a current spreading layer 214 disposed on the semiconductor functional layer. It is understood that the implementation of the platform structure 510 in this embodiment can refer to the implementation of the platform structure 510 in the above embodiments, and the details are not repeated here.

[0292] In some embodiments of the present application, referring to FIG. 28 a , the luminescent pixel further includes a distributed Bragg reflector layer 812, which extends between the third dielectric layer 323 and the second electrode connection layer 521. It is understood that the implementation of the distributed Bragg reflector layer 812 in this embodiment can refer to the implementation of the distributed Bragg reflector layer 812 in the above embodiments, and the details are not repeated here.

[0293] In some embodiments of the present application, a first vertical distance is defined between the first surface S1 of the semiconductor functional layer 210 and the first semiconductor layer, a second vertical distance is defined between the second surface S2 of the mesa structure 510 and the first semiconductor layer, and a difference between the first vertical distance and the second vertical distance is less than or equal to a difference threshold. It is understood that the implementation of the first vertical distance and the second vertical distance in this embodiment can refer to the implementation of the first vertical distance and the second vertical distance in the above-described embodiments, and the details are not further described here.

[0294] Based on this, an embodiment of the present application further provides a light-emitting module, referring to Figures 23 and 24 , which includes: an optoelectronic device 10, a driver device 30, and an interconnection assembly 20, wherein the driver device 30 is located on a side of the optoelectronic device 10 having multiple light-emitting pixels, and the driver device 30 includes a first driving pad 31. The interconnection assembly 20 is located between the optoelectronic device 10 and the driver device 30, and the interconnection assembly 20 includes a first interconnection structure 21. Furthermore, a first end of the first interconnection structure 21 is connected to the first electrode 220, and a second end of the first interconnection structure 21 is connected to the first driving pad 31.

[0295] In some embodiments of the present application, referring to FIG. 25 to FIG. 26 c , the optoelectronic device 10 further includes a boss structure 510 and a second electrode 520 located on the substrate 100, the driving device 30 further includes a second driving pad 32, and the interconnection assembly 20 further includes a second interconnect structure 22. Furthermore, a first end of the second interconnect structure 22 is connected to the second electrode 520, and a second end of the second interconnect structure 22 is connected to the second driving pad 32.

[0296] It is understandable that the preparation method of the optoelectronic device in this embodiment can also refer to the preparation method in the above embodiments, and will not be described in detail here.

[0297] It is worth mentioning that the various implementation methods in Example 3 may not depend on the implementation methods in Example 1 and Example 2, and may also be other implementable methods, which are not specifically limited here.

[0298] It is worth mentioning that, unless there is a conflict, the features of the above different embodiments can be combined with each other, which will not be described in detail here. In addition, the above content is only a specific implementation method of this application, but the scope of protection of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application, which should be covered by the scope of protection of this application.

Claims

1. A photoelectric device, characterized in that: include: A plurality of light-emitting pixels, each of the light-emitting pixels comprising a semiconductor functional layer and a first electrode; Each of the semiconductor functional layers includes a first semiconductor layer, and the plurality of light-emitting pixels share the first semiconductor layer; a groove region formed in the semiconductor functional layer, the groove region being located between the plurality of light-emitting pixels, the groove region including a first groove portion and a second groove portion; an electrode metal layer, configured to be electrically connected to the second electrode; The electrode metal layer covers at least a portion of the surface of each light-emitting pixel, at least a portion of the first groove portion, and at least a portion of the second groove portion; The electrode metal layer is insulated from the semiconductor functional layer in the first groove portion; The electrode metal layer is electrically connected to the first semiconductor layer in the second trench portion.

2. The optoelectronic device according to claim 1, wherein The sidewalls of the trench region having the second trench portion have a first dimension therebetween, the sidewalls of the trench region having the first trench portion have a second dimension therebetween, and a maximum value of the first dimensions is greater than a maximum value of the second dimensions.

3. The optoelectronic device according to claim 1 or 2, wherein: The first groove portion is located between adjacent light-emitting pixels, and the first groove portion further surrounds the second groove portion and communicates with the second groove portion.

4. The optoelectronic device according to claim 3, wherein The groove area is in a grid pattern, and the second groove portion is provided on at least some grid intersection areas in the grid pattern; or the second groove portion is provided on at least some grid lines in the grid pattern.

5. The optoelectronic device according to any one of claims 1 to 4, wherein: The first groove portion accounts for greater than or equal to 50% of the groove area, and the first groove portion accounts for less than 100% of the groove area; or, The proportion of the second trench portion in the trench region is greater than 0, and the proportion of the second trench portion in the trench region is less than or equal to 50%.

6. The optoelectronic device according to any one of claims 1 to 5, wherein: The electrode metal layer covers at least a portion of the bottom wall of the first trench portion, or the electrode metal layer covers at least a portion of the bottom wall of the second trench portion.

7. The optoelectronic device according to any one of claims 1 to 6, wherein: The portion of the electrode metal layer extending from the first groove portion to the second groove portion forms a step shape.

8. The optoelectronic device according to claim 7, wherein A first dielectric layer is provided between the electrode metal layer and the bottom wall of the first groove portion.

9. The optoelectronic device according to any one of claims 1 to 8, wherein: The first semiconductor layer is protruded in the area corresponding to the light-emitting pixels, the first semiconductor layer between adjacent light-emitting pixels forms the bottom wall of the groove area, and the sidewall of the protruding area of the first semiconductor layer forms at least part of the sidewall of the groove area.

10. The optoelectronic device according to claim 9, wherein The semiconductor functional layer further includes a light-emitting layer and a second semiconductor layer, wherein the light-emitting layer is provided on the first semiconductor layer which is provided in a protruding manner, and the second semiconductor layer is provided on the light-emitting layer, and the first electrode is electrically connected to the second semiconductor layer; The sidewalls of the protruding region of the first semiconductor layer, the sidewalls of the light emitting layer, and the sidewalls of the second semiconductor layer form the sidewalls of the trench region.

11. The optoelectronic device according to claim 10, wherein The electrode metal layer covers the sidewalls of the first semiconductor layer, the sidewalls of the light-emitting layer, and the sidewalls of the second semiconductor layer, and a second dielectric layer is provided between the electrode metal layer and the sidewalls of the first semiconductor layer, the sidewalls of the light-emitting layer, and the sidewalls of the second semiconductor layer.

12. The optoelectronic device according to claim 11, wherein The light-emitting pixel further includes a current spreading layer, which is disposed on the second semiconductor layer. The second dielectric layer also covers the sidewalls of the current spreading layer. The electrode metal layer also covers the second dielectric layer on the sidewall of the current spreading layer.

13. The optoelectronic device according to claim 12, wherein: The surface of the current spreading layer facing away from the second semiconductor layer is a first surface; the electrode metal layer extends to cover the first surface and forms a second contact hole on the first surface; the second dielectric layer extends to cover the first surface and forms a third contact hole on the inner side of the second contact hole; The first electrode is electrically connected to the second semiconductor layer through the second contact hole and the third contact hole, and the first electrode is insulated from the electrode metal layer.

14. The optoelectronic device according to claim 13, wherein The electrode metal layer extends from the sidewall of the second semiconductor layer to the first surface to form a double-step shape.

15. The optoelectronic device according to claim 14, wherein The second semiconductor layer has a first region and a second region on a side facing away from the light emitting layer, the first region surrounds the second region, and the current spreading layer covers the second region; The second dielectric layer further covers the first region, and the electrode metal layer further covers the second dielectric layer on the first region.

16. The optoelectronic device according to any one of claims 1 to 15, wherein: The first electrode includes a first electrode connection layer and a first electrode pad layer connected to each other, the first electrode connection layer is arranged between the first electrode pad layer and the current spreading layer, and the first electrode connection layer is connected to the current spreading layer through the second contact hole and the third contact hole.

17. The optoelectronic device according to claim 16, wherein In the stacking direction of the light emitting layer and the second semiconductor layer, a distance between an outer boundary of the first electrode connection layer and an outer boundary of the second contact hole is greater than zero; In the stacking direction of the light emitting layer and the second semiconductor layer, the first electrode connecting layer covers the second contact hole, or in the stacking direction of the light emitting layer and the second semiconductor layer, the first electrode connecting layer is arranged in the second contact hole.

18. The optoelectronic device according to claim 17, wherein In the stacking direction of the light emitting layer and the second semiconductor layer, the first electrode pad layer covers the second contact hole, and a passivation layer is provided between the first electrode pad layer and the electrode metal layer.

19. The optoelectronic device according to any one of claims 16 to 18, wherein: A cross section of the first electrode connection layer in the stacking direction of the light emitting layer and the second semiconductor layer has a first groove, and a portion of the first electrode pad layer fills the first groove.

20. The optoelectronic device according to any one of claims 1 to 19, wherein: The optoelectronic device further includes: one or more boss structures, the boss structures having a second surface, the second electrode being disposed on the second surface; The groove region is further provided between the boss structure and the light-emitting pixel; or, the groove region is further provided between the boss structure and the boss structure.

21. The optoelectronic device according to claim 20, wherein The groove region is further arranged between adjacent boss structures and between the boss structures and the light-emitting pixels, and the electrode metal layer also covers the sidewalls of the boss structures.

22. The optoelectronic device according to claim 21, wherein The second electrode includes a second electrode connection layer and a second electrode pad layer connected to each other, and the second electrode connection layer is arranged between the second electrode pad layer and the boss structure; The second electrode connection layer covers at least a portion of the second surface, and the electrode metal layer and the second electrode connection layer are connected to each other.

23. The optoelectronic device according to claim 21, wherein A third dielectric layer is provided between the second electrode connection layer and the boss structure, and the third dielectric layer covers the sidewalls of the boss structure; The third dielectric layer further extends to the second surface and encloses a fourth contact hole on the second surface, and the second electrode connection layer covers the third dielectric layer and contacts the second surface through the fourth contact hole; or, the third dielectric layer covers the second surface, and the second electrode connection layer covers the third dielectric layer.

24. The optoelectronic device according to any one of claims 20 to 23, wherein: The boss structure is a single-layer structure, and the boss structure includes: a semiconductor material layer, an insulating material layer or a metal material layer; or, The boss structure is a multi-layer structure, and the boss structure includes: a semiconductor material layer, an insulating material layer or a combination of a metal material layer.

25. The optoelectronic device according to claim 24, wherein The boss structure is the multi-layer structure; The boss structure includes the semiconductor functional layer, or the boss structure includes the semiconductor functional layer and a current spreading layer disposed on the semiconductor functional layer.

26. The optoelectronic device according to any one of claims 11 to 25, wherein: The light-emitting pixel further includes a distributed Bragg reflection layer, which is arranged between the electrode metal layer and the second dielectric layer.

27. A light emitting module, characterized in that: include: The optoelectronic device according to any one of claims 1 to 26; A driving device, located on a side of the optoelectronic device having a plurality of light-emitting pixels, the driving device comprising a first driving pad and a second driving pad; An interconnection component is located between the optoelectronic device and the driving device, and the interconnection component includes a first interconnection structure and a second interconnection structure, a first end of the first interconnection structure is connected to the first electrode, a second end of the first interconnection structure is connected to the first driving pad, a first end of the second interconnection structure is connected to the second electrode, and a second end of the second interconnection structure is connected to the second driving pad.

28. An electronic device, characterized in that: It comprises a circuit board and the light-emitting module as claimed in claim 27, wherein the circuit board is connected to a driving device in the light-emitting module.

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