Photomask, light-emitting diode, and manufacturing method for light-emitting diode

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a photomask, a light-emitting diode, and a manufacturing method for the light-emitting diode. The photomask comprises a plurality of light-transmitting areas; each light-transmitting area comprises an etching area and a diffraction area; the etching area is a circular hole; the diffraction area comprises a plurality of diffraction rings; the plurality of diffraction rings surround the etching area and are separately concentric with the etching area; and each diffraction ring comprises a plurality of diffraction holes which are sequentially arranged at intervals. According to the present disclosure, by means of the provision of the plurality of light-transmitting areas, a plurality of patterns can be etched. The etching area is a circular hole, and exposure light can normally pass through the etching area so as to form a fully exposed area at a part to be exposed. The exposure light is diffracted during the process of passing through the diffraction holes, so that a semi-exposed area is formed at the part to be exposed surrounding the outer edge of the fully exposed area. During the subsequent etching process, the etching depth of the fully exposed area is large, and the etching depth of the semi-exposed area is small, so that the inclination of walls of through holes formed by etching is relatively gentle.

Description

Photoresist, light-emitting diode, and method for preparing light-emitting diode

[0001] This application claims priority to Chinese patent application No. 202410165017.6, filed on February 5, 2024, entitled “Photoresist, Light-Emitting Diode, and Method for Preparing Light-Emitting Diode,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure belongs to the field of semiconductor technology, and in particular relates to a photomask, a light-emitting diode, and a method for manufacturing the light-emitting diode. Background Art

[0003] A light emitting diode (LED) is a semiconductor device that can convert electrical energy into light energy. It has the advantages of high light efficiency, energy saving, long service life, short response time, and environmental protection.

[0004] In related technologies, a light-emitting diode (LED) includes an epitaxial layer and a transparent conductive layer, a silver mirror layer, a protective layer, an insulating layer, an electrode, and other structures stacked sequentially on one side of the epitaxial layer. The epitaxial layer is used to emit light, the silver mirror layer reflects the light emitted by the epitaxial layer, and the insulating layer is used to electrically isolate different metal layers and also improve reflectivity. Distributed Bragg reflectors (DBRs) or SiO2 and other materials are mainly used.

[0005] However, to improve reflectivity and enhance electrical isolation, the aforementioned LEDs typically employ a multi-layer DBR structure or thicker SiO2 as the insulating layer. As the number of DBR layers increases or the SiO2 thickens, the thickness of the insulating layer increases. Consequently, when the insulating layer is etched, the slope angle of the insulating layer's through-holes becomes larger (i.e., steeper). This can easily lead to voids or fractures in the electrodes covering the insulating layer's slopes, potentially damaging the LEDs. Summary of the Invention

[0006] The present disclosure provides a photoresist, a light-emitting diode, and a method for manufacturing a light-emitting diode, which can form a first through-hole with a gentle slope, ensuring that subsequent electrode growth is not prone to breakage. The technical solution is as follows:

[0007] On the one hand, an embodiment of the present disclosure provides a photoresist, which includes multiple light-transmitting areas, each of which includes an etched area and a diffraction area; the etched area is a circular hole; the diffraction area includes multiple diffraction rings, each of which surrounds the etched area and is concentric with the etched area, and the diffraction rings include multiple diffraction holes arranged in sequence.

[0008] In an implementation of the present disclosure, the radius of the etched area is R1, the diffraction area is annular, the ring width of the diffraction area is R2, and 0.5R1≤R2≤2R1.

[0009] In another implementation of the present disclosure, the shape of the diffraction hole is any one of rectangular, circular and triangular.

[0010] In another implementation of the present disclosure, the diffraction hole is a square with a side length of L1; the centers of the multiple diffraction holes in the same diffraction ring are all located on a first circle, and the first circle is concentric with the etched area; the perpendicular bisector on one side of the diffraction hole passes through the center of the etched area; the minimum distance between two adjacent diffraction holes in the same diffraction ring is S1, S1≤L1.

[0011] In another implementation of the present disclosure, the diffraction hole is a circle with a diameter of L2; the centers of the multiple diffraction holes in the same diffraction ring are located on a second circle, and the second circle is concentric with the etched area; the minimum distance between two adjacent diffraction holes in the same diffraction ring is S2, S2≤L2.

[0012] In another implementation of the present disclosure, the diffraction hole is an equilateral triangle with a side length of L3; the centers of the multiple diffraction holes in the same diffraction ring are located on a third circle, and the third circle is concentric with the etched area; the perpendicular bisector of one side of the diffraction hole passes through the center of the etched area; the minimum distance between two adjacent diffraction holes in the same diffraction ring is S3, S3≤L3.

[0013] On the other hand, an embodiment of the present disclosure provides a method for preparing a light-emitting diode, which is based on the aforementioned photoresist, and the method includes: preparing an epitaxial wafer, the epitaxial wafer including a first doped layer, a light-emitting layer, and a second doped layer stacked in sequence, and growing a first insulating layer on one side of the second doped layer; etching a first through hole and a second through hole in the first insulating layer through the photoresist, so that the first through hole passes through the first insulating layer to the first doped layer, and the second through hole passes through the first insulating layer to the second doped layer; preparing a first electrode and a second electrode on the side of the first insulating layer facing away from the second doped layer, the first electrode being electrically connected to the epitaxial wafer through the first through hole, and the second electrode being electrically connected to the epitaxial wafer through the second through hole.

[0014] On the other hand, an embodiment of the present disclosure provides a light-emitting diode, which is manufactured using the preparation method, and includes: a first doped layer of a first conductive type; a light-emitting layer located on one side of the first doped layer; a second doped layer located on a side of the light-emitting layer facing away from the first doped layer, the second doped layer being of a second conductive type, and the second conductive type being different from the first conductive type; a first insulating layer located on a side of the second doped layer facing away from the first doped layer, having a first through hole and a second through hole; a first electrode located on a side of the first insulating layer facing away from the first doped layer, and electrically connected to the first doped layer through the first through hole; and a second electrode located on a side of the first insulating layer facing away from the first doped layer, and electrically connected to the second doped layer through the second through hole.

[0015] In one implementation of the present disclosure, the first insulating layer is a single layer of silicon oxide, and the thickness of the first insulating layer is 1.8 μm to 3.0 μm; the angle between the wall of the first through hole and the surface of the first doped layer is a first angle, and the angle between the wall of the second through hole and the surface of the second doped layer is a second angle, and the first angle and the second angle are both greater than 30 degrees and less than 65 degrees.

[0016] In another implementation of the present disclosure, the first insulating layer is a DBR multilayer, and the thickness of the first insulating layer is 3.0 μm to 5.0 μm; the angle between the hole wall of the first through hole and the surface of the first doped layer is a first angle, and the angle between the hole wall of the second through hole and the surface of the second doped layer is a second angle, and the first angle and the second angle are both greater than 41 degrees and less than 54 degrees. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG1 is a schematic diagram of a light-transmitting area provided by an embodiment of the present disclosure;

[0018] FIG2 is a photoresist topography diagram when the ring width of the diffraction zone is 0 micrometers according to an embodiment of the present disclosure;

[0019] FIG3 is a photoresist topography diagram when the ring width of the diffraction zone is 4 μm according to an embodiment of the present disclosure;

[0020] FIG4 is a photoresist topography diagram when the ring width of the diffraction zone is 6 microns according to an embodiment of the present disclosure;

[0021] FIG5 is an enlarged view of portion A in FIG1 ;

[0022] FIG6 is a schematic diagram of a circular diffraction hole provided in an embodiment of the present disclosure;

[0023] FIG7 is an enlarged view of portion B in FIG6 ;

[0024] FIG8 is a schematic diagram of a first equilateral triangle diffraction aperture provided by an embodiment of the present disclosure;

[0025] FIG9 is an enlarged view of portion C in FIG8 ;

[0026] FIG10 is a schematic diagram of a second equilateral triangle diffraction aperture provided by an embodiment of the present disclosure;

[0027] FIG11 is an enlarged view of portion D in FIG10 ;

[0028] FIG12 is a schematic diagram of a photomask provided in an embodiment of the present disclosure;

[0029] FIG13 is a topographical diagram of a DBR layer etched by a photoresist in the related art;

[0030] FIG14 is a topographical diagram of a DBR layer etched by a photoresist according to an embodiment of the present disclosure;

[0031] FIG15 is a topography of the SiO2 insulating layer after etching by a photoresist in the related art;

[0032] FIG16 is a morphology diagram of the SiO2 insulating layer after etching by the photoresist provided in an embodiment of the present disclosure;

[0033] FIG17 is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of the present disclosure;

[0034] FIG18 is a flow chart of a method for preparing a first light-emitting diode according to an embodiment of the present disclosure;

[0035] FIG19 is a flow chart of a second method for preparing a light-emitting diode according to an embodiment of the present disclosure;

[0036] FIG20 is a flow chart of etching a first through hole in a first insulating layer according to an embodiment of the present disclosure;

[0037] FIG21 is a flow chart of preparing an epitaxial wafer provided in an embodiment of the present disclosure.

[0038] The symbols in the figure represent the following meanings: 1. Light-transmitting area; 11. Etched area; 12. Diffraction area; 121. Diffraction ring; 1211. Diffraction hole; 13. First circle; 14. Second circle; 15. Third circle; 2. Light-emitting diode; 21. Epitaxial wafer; 211. Substrate; 212. Epitaxial layer; 2121. First doped layer; 2122. Light-emitting layer; 2123. Second doped layer; 22. Silver mirror layer; 23. Protective layer; 24. First insulating layer; 25. First through hole; 26. Second electrode; 27. First electrode; 28. Second insulating layer; 29. ​​Fourth electrode; 210. Third electrode; 220. Second through hole; 230. Transparent conductive layer; 3. Electrode hole; 4. Parallel line; 100. DBR layer; 200. SiO2 insulating layer; 300. Electrode layer; 400. Photoresist. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0040] The present disclosure provides a photomask. FIG1 is a schematic diagram of a light-transmitting region 1 provided in the present disclosure. Referring to FIG1 , the photomask includes multiple light-transmitting regions 1, each of which includes an etched region 11 and a diffraction region 12. The etched region 11 is a circular hole, and the diffraction region 12 includes multiple diffraction rings 121. The multiple diffraction rings 121 surround the etched region 11 and are concentric with the etched region 11. The diffraction rings 121 include multiple diffraction holes 1211 arranged in a sequentially spaced arrangement.

[0041] The photomask provided by the embodiment of the present disclosure includes a plurality of light-transmitting areas 1, which are used to etch a plurality of patterns during the photolithography process. The light-transmitting area 1 includes an etching area 11 and a diffraction area 12. For the etching area 11, the etching area 11 is a circular hole, and the exposure light can normally penetrate the etching area 11 to form a fully exposed area at the part to be exposed. For the diffraction area 12, it includes a plurality of diffraction holes 1211. The exposure light is diffracted in the process of penetrating the diffraction holes 1211 to form a semi-exposed area at the part to be exposed, that is, incomplete exposure. Since each diffraction hole 1211 can form a plurality of diffraction rings 121, and the plurality of diffraction rings 121 are concentrically arranged outside the etching area 11, the semi-exposed area is surrounded by the outer edge of the fully exposed area. After the photolithography is completed, there is no photoresist in the fully exposed area. In the direction from the fully exposed area to the unexposed area, the photoresist thickness of the semi-exposed area gradually changes from 0 to the photoresist thickness of the unexposed area. As a result, in the subsequent etching process, the fully exposed area is etched to a greater depth, while the half-exposed area is etched to a smaller depth, so that the inclination of the groove wall of the through hole formed by etching is relatively gentle.

[0042] With this design, when electrodes or other structures are subsequently grown in the through holes formed by the etching, voids or breaks are less likely to occur, thereby improving the quality of the light-emitting diode.

[0043] In the embodiment of the present disclosure, the radius of the etched area 11 is R1, the diffraction area 12 is annular, the ring width of the diffraction area 12 is R2, and 0.5R1≤R2≤2R1.

[0044] The size of the ring width R2 determines the width of the diffraction zone 12. The smaller the diffraction zone 12, the steeper the slope around the etched hole-shaped channel, and the larger the diffraction zone 12, the flatter the slope around the etched hole-shaped channel. When the film layer to be exposed is the DBR layer, and the through hole to be formed is the electrode through hole on the DBR layer, the radius of the etched zone 11 does not change much with the size of R1. At this time, the ring width of the diffraction zone 12 should not be less than half the radius of the etched zone 11. When R2<0.5R1, the width of the diffraction zone 12 is too small, making the slope around the etched hole-shaped channel too steep, which is not suitable for the subsequent growth of electrodes or other structures, and is prone to voids or fractures. When R2>2R1, the width of the diffraction zone 12 is too large, making the slope around the etched hole-shaped channel too flat, requiring a larger etching area, which is not conducive to the miniaturization design of the light-emitting diode.

[0045] By way of example, R2 = R1. Designing the ring width of the diffraction region 12 to be the same as the radius of the etching region 11 can ensure that the groove wall of the through hole formed by etching has a relatively gentle slope while ensuring the miniaturization of the light-emitting diode.

[0046] For example, R2 and R1 are 4 to 6 microns, such as 6 microns.

[0047] Figure 2 is a topographical diagram of the photoresist 400 when the ring width value of the diffraction zone is 0 microns according to an embodiment of the present disclosure. Referring to Figure 2, the slope of the photoresist 400 is relatively steep at this time. Figure 3 is a topographical diagram of the photoresist 400 when the ring width value of the diffraction zone is 4 microns according to an embodiment of the present disclosure. In combination with Figures 2 to 3, the slope of the photoresist 400 in Figure 3 is relatively gentle compared to the slope in Figure 2. Figure 4 is a topographical diagram of the photoresist 400 when the ring width value of the diffraction zone is 6 microns according to an embodiment of the present disclosure. In combination with Figures 2 to 4, the slope of the photoresist 400 in Figure 4 is gentler than the slopes in Figures 2 and 3. When the ring width value R2 is larger, the slope of the photoresist 400 will be gentler.

[0048] It should be noted that the photoresist morphology will be transferred to the chip through the etching step, that is, the steeper the slope of the photoresist 400, the steeper the slope of the etched through hole, and the flatter the slope of the photoresist 400, the flatter the slope of the etched through hole.

[0049] In the embodiment of the present disclosure, the shape of the diffraction hole 1211 is any one of a rectangle, a circle and a triangle.

[0050] In one example, the shape of the diffraction hole 1211 can be a square, a circle, or an equilateral triangle. The above shapes can all satisfy the condition of forming a continuous semi-transmissive region 1 for the diffraction ring 121.

[0051] In other embodiments, the shape of the diffraction hole 1211 can be other polygons or irregular shapes.

[0052] FIG. 5 is an enlarged view of part A in FIG. 1. Combining FIGS. 1 and 5, in the embodiments of the present disclosure, the diffraction hole 1211 is a square with a side length of L1. The centers of multiple diffraction holes 1211 within the same diffraction ring 121 are all located on the first circle 13, and the first circle 13 is concentric with the etching region 11. The perpendicular bisector of one side of the diffraction hole 1211 passes through the center of the etching region 11. The minimum distance between two adjacent diffraction holes 1211 within the same diffraction ring 121 is S1, and S1 ≤ L1.

[0053] With such a design, multiple diffraction holes 1211 surround the outside of the etching region 11, and are used to form obstacles to light between the multiple diffraction holes 1211 during the subsequent etching process, so that a diffraction phenomenon occurs during exposure. The centers of multiple diffraction holes 1211 within the same diffraction ring 121 are all located on the first circle 13, and the first circle 13 is concentric with the etching region 11. The centers of multiple square diffraction holes 1211 within the same diffraction ring 121 are all located on the first circle 13 concentric with the etching region 11, and multiple square diffraction holes 1211 are arranged around the etching region 11. The perpendicular bisector of one side of the diffraction hole 1211 passes through the center of the etching region 11, so that the square diffraction holes 1211 are arranged along the etching region 11 regularly at a certain angle. When using a photomask for exposure, the wavelength of the light used for exposure is a certain value. When the light passes through the diffraction region 12, an obstacle is formed between two adjacent diffraction holes 1211 within the same diffraction ring 121. When the width of the obstacle is equivalent to or greater than the wavelength of the light, an obvious diffraction phenomenon will occur. The minimum distance between two adjacent diffraction holes 1211 within the same diffraction ring 121 is S1, and the range of S1 depends on the wavelength of the light used for exposure when using a photomask for exposure. The diffraction hole 1211 is a square with a side length of L1. When L1 < S1, the width of the diffraction hole 1211 is less than the wavelength of the light, and the diffraction effect is not obvious, and a continuous semi-transmissive region 1 cannot be formed. During the subsequent etching process, a relatively gentle slope cannot be formed in the round hole, so L1 cannot be less than S1. Moreover, a smaller width requires higher precision for the photomask, resulting in a very high manufacturing cost for the photomask. By adopting the design of S1 ≤ L1, the above problems can be avoided, which can not only ensure a gentle slope for the etched through hole, but also reduce the cost of the photomask.

[0054] In the embodiments of the present disclosure, the wavelength of the light used for exposure is 365 nanometers, and the range of S1 is 250 - 600 nanometers.

[0055] Exemplarily, the range of S1 is 400 - 600 nanometers, such as 500 nanometers.

[0056] In an embodiment of the present disclosure, the range of L1 is 600 - 1000 nanometers, such as 1000 nanometers.

[0057] In other examples, the arrangement of the multiple diffraction holes 1211 may not be in the way that the perpendicular bisector of one side of the diffraction hole 1211 passes through the center of the etching area 11.

[0058] FIG. 6 is a schematic diagram of a circular diffraction hole provided by an embodiment of the present disclosure. Referring to FIG. 6, in an embodiment of the present disclosure, the diffraction hole 1211 is a circle with a diameter of L2, and the centers of the multiple diffraction holes 1211 within the same diffraction ring 121 are located on the second circle 14, and the second circle 14 is concentric with the etching area 11. FIG. 7 is an enlarged view of part B in FIG. 6. Combining FIGS. 6 - 7, the minimum distance between two adjacent diffraction holes 1211 within the same diffraction ring 121 is S2, and S2 ≤ L2.

[0059] With such a design, the multiple diffraction holes 1211 surround the outside of the etching area 11 and are used to form a relatively gentle slope in the subsequent etching process for the round hole. The centers of the multiple diffraction holes 1211 within the same diffraction ring 121 are all located on the second circle 14, and the second circle 14 is concentric with the etching area 11. The centers of the multiple circular diffraction holes 1211 within the same diffraction ring 121 are all located on the second circle 14 concentric with the etching area 11, and the multiple circular diffraction holes 1211 are arranged surrounding the etching area 11. When using a photomask for exposure, the wavelength of the light used for exposure is a certain value. When the light passes through the diffraction area 12, an obstacle is formed between two adjacent diffraction holes 1211 within the same diffraction ring 121. When the width of the obstacle is comparable to or greater than the wavelength of the light, an obvious diffraction phenomenon will occur. The minimum distance between two adjacent diffraction holes 1211 within the same diffraction ring 121 is S1, and the range of S1 depends on the wavelength of the light used for exposure when using a photomask for exposure. The diffraction hole 1211 is a circle with a side length of L2. When L2 < S2, the width of the diffraction hole 1211 is less than the wavelength of the light, and the diffraction effect is not obvious, and a continuous semi-transmissive area 1 cannot be formed. In the subsequent etching process, a relatively gentle slope cannot be formed in the round hole. Therefore, L2 cannot be less than S2. Moreover, a smaller width requires a higher precision for the photomask, resulting in a very high manufacturing cost of the photomask. By adopting the design of S2 ≤ L2, the above problems can be avoided. It can not only ensure a gentle slope for the etched through-hole but also reduce the cost of the photomask.

[0060] In an embodiment of the present disclosure, the wavelength of the light used for exposure is 365 nanometers, and the range of S2 is 250 - 600 nanometers.

[0061] Exemplarily, the range of S2 is 400 to 600 nanometers, such as 500 nanometers.

[0062] In the embodiment of the present disclosure, the range of L2 is 600 to 1000 nanometers, such as 1000 nanometers.

[0063] FIG. 8 is a schematic diagram of the first equilateral triangle diffraction hole provided by the embodiment of the present disclosure. Referring to FIG. 8, in the embodiment of the present disclosure, the diffraction hole 1211 is an equilateral triangle with a side length of L3. The centers of multiple diffraction holes 1211 within the same diffraction ring 121 are located on the third circle 15, and the third circle 15 is concentric with the etching region 11. The perpendicular bisector of one side of the diffraction hole 1211 passes through the center of the etching region 11. FIG. 9 is an enlarged view of part C in FIG. 8. Combining FIGS. 8-9, the minimum distance between two adjacent diffraction holes 1211 within the same diffraction ring 121 is S3, and S3 ≤ L3.

[0064] With such a design, multiple diffraction holes 1211 surround the outside of the etching region 11, which is used to form a relatively gentle slope in the subsequent etching process for the circular hole. The centers of multiple diffraction holes 1211 within the same diffraction ring 121 are all located on the third circle 15, and the third circle 15 is concentric with the etching region 11. The centers of multiple equilateral triangle diffraction holes 1211 within the same diffraction ring 121 are all located on the third circle 15 concentric with the etching region 11, and multiple equilateral triangle diffraction holes 1211 are arranged around the etching region 11. The perpendicular bisector of one side of the diffraction hole 1211 passes through the center of the etching region 1l, so that the equilateral triangle diffraction holes 1211 are arranged along the etching region 11 at a certain angular pattern. When using a photomask for exposure, the wavelength of the light used for exposure is a certain value. When the light passes through the diffraction region 12, an obstacle is formed between two adjacent diffraction holes 1211 within the same diffraction ring 121. When the width of the obstacle is equivalent to or greater than the wavelength of the light, an obvious diffraction phenomenon will occur. The minimum distance between two adjacent diffraction holes 1211 within the same diffraction ring 121 is S3, and the range of S3 depends on the wavelength of the light used for exposure when using a photomask for exposure. The diffraction hole 1211 is an equilateral triangle with a side length of L3. When L3 < S3, the width of the diffraction hole 1211 is less than the wavelength of the light, and the diffraction effect is not obvious, and a continuous semi-transmissive region 1 cannot be formed. In the subsequent etching process, a relatively gentle slope cannot be formed in the circular hole, so L3 cannot be less than S3. Moreover, a smaller width requires higher precision for the photomask, resulting in a very high manufacturing cost for the photomask. By adopting the design of S3 ≤ L3, the above problems can be avoided, which can not only ensure a gentle slope for the etched through-hole but also reduce the cost of the photomask. [[ID=ID=10]]

[0065] In the embodiment of the present disclosure, the wavelength of the light used for exposure is 365 nanometers, and the range of S3 is 250 to 600 nanometers.

[0066] Exemplarily, S3 ranges from 400 to 600 nanometers, for example, 500 nanometers.

[0067] In the embodiment of the present disclosure, L3 is in the range of 600 to 1000 nanometers, for example, 1000 nanometers.

[0068] In other examples, the arrangement of the multiple diffraction holes 1211 may not be such that the perpendicular midline of one side of the diffraction hole 1211 passes through the center of the etched area 11 .

[0069] FIG10 is a schematic diagram of a second equilateral triangle diffraction aperture provided in an embodiment of the present disclosure. Referring to FIG10 , in this embodiment, the diffraction aperture 1211 is an equilateral triangle with a side length of L3. The centers of the multiple diffraction apertures 1211 within the same diffraction ring 121 are located on a third circle 15, which is concentric with the etched region 11. The perpendicular bisector of one side of the diffraction aperture 1211 passes through the center of the etched region 11. FIG11 is an enlarged view of portion D in FIG10 . Combining FIG10 and FIG11 , the minimum distance between two adjacent diffraction apertures 1211 within the same diffraction ring 121 is S3, where S3 ≤ L3.

[0070] The difference between the equilateral triangle shown in FIG. 10 and the equilateral triangle shown in FIG. 8 is that the equilateral triangles are oriented in different directions.

[0071] FIG12 is a schematic diagram of a photomask provided by an embodiment of the present disclosure. Referring to FIG12 , a plurality of light-transmitting regions 1 are distributed along a plurality of parallel lines 4 , and the distance between two adjacent light-transmitting regions 1 on the same parallel line 4 is equal.

[0072] In one example, the photomask only includes the plurality of through-hole regions. In this case, both the first through-hole and the second through-hole on the first insulating layer are exposed and developed using the through-hole regions.

[0073] In another example, in addition to the multiple through-hole regions described above, the photoresist also includes multiple electrode holes 3. As shown in FIG12 , the electrode holes 3 are located between two parallel lines 4, and the multiple electrode holes 3 are spaced apart along the parallel lines. In this case, the first through-hole in the first insulating layer is exposed and developed using the through-hole region, and the second through-hole can be exposed and developed using the electrode holes 3.

[0074] Only part of the electrode holes 3 is shown in Figure 12. And because the first through hole is located on the step of the epitaxial wafer, the size of the first through hole is designed to be small, and accordingly, the area of ​​the light-transmitting region is smaller than that of the electrode hole.

[0075] In addition, since the first through hole is located at the step, the thickness of the photoresist is greater when it is formed. When the photoresist thickness is large and the size of the first through hole to be formed is small, it is easy to cause the slope of the etched through hole to be steeper, so it is more necessary to use the photoresist provided by the embodiment of the present disclosure to solve this problem.

[0076] It is worth noting that the parallel lines 4 are virtual lines used to assist in illustrating the arrangement of the light-transmitting areas 1 .

[0077] As mentioned above, the electrode hole 3 is used to etch the second through hole 220 on the first insulating layer. The second electrode 26 passes through the second through hole 220 to be electrically connected to the protective layer 23 and further to the epitaxial wafer.

[0078] In the embodiment of the present disclosure, the photoresist can be used to at least etch the DBR layer 100 and the SiO2 insulating layer 200. The etching of the DBR layer 100 and the SiO2 insulating layer 200 will be taken as examples below to compare the etching conditions of the photoresist provided by the embodiment of the present disclosure with those of the photoresist in the related art.

[0079] Taking etching the DBR layer 100, where the thickness of the DBR layer 100 is in the range of 3 to 5 microns as an example:

[0080] FIG13 is a topography diagram of the DBR layer 100 etched by a photoresist in the related art. Referring to FIG13 , in the related art, the angle α of the DBR layer 100 after etching is in the range of 73.7°.

[0081] Figure 14 shows the topography of the DBR layer 100 etched using the photomask provided in an embodiment of the present disclosure. As shown in Figure 14 , the angle β of the DBR layer 100 ranges from 41° to 54°, for example, 50.5°. Using the photomask provided in an embodiment of the present disclosure significantly reduces the angle of the DBR layer 100 after etching, resulting in a gentler slope on the through-hole sidewalls. This provides a good foundation for the subsequent growth of electrodes or other structural layers, reducing the risk of voids or fractures.

[0082] Taking etching of the SiO2 insulating layer 200, where the thickness of the SiO2 insulating layer 200 is in the range of 1.8 to 3 microns as an example:

[0083] FIG15 is a topography diagram of the SiO2 insulating layer 200 etched by a photoresist in the related art. Referring to FIG15 , in the related art, the angle γ of the SiO2 insulating layer 200 after etching is in the range of 86°.

[0084] Figure 16 is a topographical image of the SiO2 insulating layer 200 etched using a photomask provided in an embodiment of the present disclosure. Referring to Figure 16 , the angle θ of the SiO2 insulating layer 200 ranges from 30° to 65°, for example, 58°. Using the photomask provided in an embodiment of the present disclosure significantly reduces the angle of the SiO2 insulating layer 200 after etching, resulting in a gentler slope on the sidewalls of the through-holes. This provides a good foundation for the subsequent growth of electrodes or other structural layers, making voids and fractures less likely to occur.

[0085] FIG17 is a schematic diagram of the structure of a light-emitting diode provided by an embodiment of the present disclosure. Referring to FIG17 , an embodiment of the present disclosure provides a light-emitting diode, comprising: a first doped layer 2121 of a first conductivity type; a light-emitting layer 2122 located on one side of the first doped layer 2121; a second doped layer 2123 located on the side of the light-emitting layer 2122 facing away from the first doped layer 2121; the second doped layer 2123 having a second conductivity type that is different from the first conductivity type; a first insulating layer 24 located on the side of the second doped layer 2123 facing away from the first doped layer 2121; and having a first through-hole 25 and a second through-hole 220. A first electrode 27 located on the side of the first insulating layer 24 facing away from the first doped layer 2121 and electrically connected to the first doped layer 2121 via the first through-hole 25; and a second electrode 26 located on the side of the first insulating layer 24 facing away from the first doped layer 2121 and electrically connected to the second doped layer 2123 via the second through-hole 220.

[0086] In the embodiment of the present disclosure, the angle between the hole wall of the first through hole 25 and the surface of the first doping layer 2121 is the first angle, and the angle between the hole wall of the second through hole 220 and the surface of the second doping layer 2123 is the second angle.

[0087] In the embodiment of the present disclosure, the first insulating layer 24 is a single silicon oxide layer, the thickness of the first insulating layer 24 is 1.8 μm to 3.0 μm, and the first angle and the second angle are both greater than 30 degrees and less than 65 degrees.

[0088] Exemplarily, the thickness of the first insulating layer 24 is 2.4 μm.

[0089] Exemplarily, the first angle and the second angle are 58°.

[0090] In the embodiment of the present disclosure, the first insulating layer 24 is a DBR multilayer, the thickness of the first insulating layer 24 is 3.0 μm to 5.0 μm, and the first angle and the second angle are both greater than 41 degrees and less than 54 degrees.

[0091] Exemplarily, the thickness of the first insulating layer 24 is 4.5 μm.

[0092] Exemplarily, the first angle and the second angle are 50.5°.

[0093] The embodiment of the present disclosure provides a method for preparing a light-emitting diode, which is used to prepare the light-emitting diode 2 of Figure 17. The light-emitting diode 2 is prepared using the photomask of Figures 1 to 8, and includes all the beneficial effects of the photomask of Figures 1 to 8, which will not be repeated here.

[0094] FIG18 is a flow chart of a method for manufacturing a first light-emitting diode according to an embodiment of the present disclosure. Referring to FIG18 , the manufacturing method includes:

[0095] Step 1801: Prepare an epitaxial wafer 21. When the light emitting diode is working, the epitaxial wafer 21 emits light to provide a light source.

[0096] Epitaxial wafer 21 includes epitaxial layer 212 and other epitaxial structures. Epitaxial layer 212 includes a stacked first doped layer 2121, a light-emitting layer 2122, and a second doped layer 2123. First doped layer 2121 has a first conductivity type, and second doped layer 2123 has a second conductivity type different from the first conductivity type. Energy transition occurs between first doped layer 2121 and second doped layer 2123, causing light-emitting layer 2122 to emit light.

[0097] In one example, the first doped layer 2121 is an N-type semiconductor layer, and the second doped layer 2123 is a P-type semiconductor layer. In another example, the first doped layer 2121 is a P-type semiconductor layer, and the second doped layer 2123 is an N-type semiconductor layer. This is not a limitation. The following example uses the first doped layer 2121 as an N-type semiconductor layer and the second doped layer 2123 as a P-type semiconductor layer.

[0098] The above descriptions are merely optional examples of the present disclosure.

[0099] Step 1802 : growing a first insulating layer 24 on one side of the epitaxial wafer 21 .

[0100] Step 1803 : etching the first through hole 25 and the second through hole 220 in the first insulating layer 24 using a photoresist.

[0101] Step 1804 : forming a first electrode 27 and a second electrode 26 on a side of the first insulating layer 24 facing away from the second doping layer 2123 .

[0102] FIG19 is a flow chart of a second method for preparing a light-emitting diode according to an embodiment of the present disclosure. Referring to FIG19 , the preparation method includes:

[0103] Step 1901: Prepare an epitaxial wafer 21.

[0104] When the light emitting diode is working, the epitaxial wafer 21 emits light to provide a light source.

[0105] Step 1902 : growing a transparent conductive layer 230 on one side of the epitaxial wafer 21 .

[0106] Optionally, step 1802 includes: coating an indium tin oxide (ITO) film on the epitaxial wafer 21 using magnetron sputtering technology or electron beam evaporation process, and removing part of the ITO film using photolithography and chemical wet etching processes to form a transparent conductive layer 230.

[0107] Transparent conductive layer 230 is transparent and conductive. When light-emitting layer 2122 emits light, the light can pass smoothly through transparent conductive layer 230 without being absorbed or scattered, thereby improving the light extraction efficiency of the LED and, in turn, the brightness of the LED. Furthermore, transparent conductive layer 230 has a current spreading effect, making the current injected into various parts of epitaxial layer 212 more uniform.

[0108] Step 1903 : growing a silver mirror layer 22 on one side of the transparent conductive layer 230 .

[0109] The silver mirror layer 22 reflects the light emitted from the epitaxial wafer 21 so that the light is emitted from the same direction, thereby enhancing the brightness of the light emitting diode.

[0110] Illustratively, the silver mirror layer 22 is sputtered on the transparent conductive layer 230 by using magnetron sputtering technology or electron beam evaporation process, and the material is one or a combination of multiple materials such as Ag, Ni, Ti, and TiW.

[0111] Step 1904 : preparing a protective layer 23 on the side of the silver mirror layer 22 facing away from the epitaxial wafer 21 .

[0112] The protective layer 23 is provided to protect the silver mirror layer 22 so that the structure of the silver mirror layer 22 is not easily damaged, thereby avoiding the problem of insufficient light reflection.

[0113] For example, a Cr layer, a first Al layer, a Ti layer, a second Al layer, a Pt layer, and a Ti layer or a combination layer of other metals are sequentially deposited on the silver mirror layer 22 using an electron beam evaporation process, and then the excess metal layer is removed using a lift-off process to form a protective layer 23. The first Al layer has a high reflectivity and is used to reflect light. The material of the first Al layer can also be replaced with an AlCu alloy. The Ti layer and the second Al layer serve as a buffer layer and a filling layer. The Pt layer uses an inert metal such as Pt to play a blocking and protective role. The Ti layer acts as an adhesion layer to enhance adhesion with other thin film layers of the subsequent light-emitting diode.

[0114] Step 1905 : forming a first insulating layer 24 on the side of the protective layer 23 facing away from the silver mirror layer 22 .

[0115] The first insulating layer 24 is provided to better protect the epitaxial layer 212 and the silver mirror layer 22 from subsequent impacts, thereby reducing the possibility of potential safety hazards caused by environmental changes and other reasons.

[0116] Illustratively, the first insulating layer may be SiO 2 or a DBR layer.

[0117] Step 1906 : etching a first through hole 25 and a second through hole 220 on the first insulating layer using a photoresist, so that the first through hole 25 passes through the first insulating layer 24 to the epitaxial wafer 21 , and the second through hole 220 passes through the first insulating layer 24 to the protective layer 23 .

[0118] The photomask provided by the embodiments of the present disclosure is provided with multiple light-transmitting regions 1 for photolithography of multiple patterns. The light-transmitting regions 1 include an etching region 11 and a diffraction region 12. The etching region 11 is a circular hole. When the photomask is used, light passes through the etching region 11 to form the light-transmitting region 1, which is used to subsequently etch the hole-shaped channel. The diffraction region 12 includes multiple diffraction rings 121. The multiple diffraction rings 121 surround the etching region 11 and are respectively concentric with the etching region 11. When the photomask is used, light diffracts when passing through the diffraction region 12. The diffraction rings 121 form a continuous semi-transmitting region 1, which forms a relatively gentle slope around the circular hole during the subsequent etching process.

[0119] In the embodiment of the present disclosure, the first through hole 25 is formed by developing and exposing the photoresist in the light-transmitting area of ​​the photoresist, and then etching.

[0120] In the embodiment of the present disclosure, the second through hole 220 can be formed by developing and exposing the photoresist using the light-transmitting area of ​​the photomask and then etching. In this case, the etching method for the second through hole 220 can be the same as that for the first through hole 25. The second through hole 220 can also be formed by developing and exposing the photoresist using the electrode hole in the photomask and then etching.

[0121] In the embodiment of the present disclosure, the first through hole 25 and the second through hole 220 can be developed, exposed, and etched at the same time, or developed, exposed, and etched in two steps.

[0122] Step 1907 : forming a second electrode 26 and a first electrode 27 on a side of the first insulating layer 24 facing away from the protective layer 23 .

[0123] The second electrode 26 passes through the second through hole 220 and is connected to the protective layer 23 , and is further electrically connected to the second doping layer 2123 . The first electrode 27 passes through the first through hole 25 and is electrically connected to the first doping layer 2121 .

[0124] Exemplarily, the material of the second electrode 26 and the first electrode 27 is a combination of one or more of Cr, Al, AlCu, Ti, Ni, Pt, and Au.

[0125] In an embodiment of the present disclosure, the preparation method further comprises:

[0126] Step 1908 : preparing a second insulating layer 28 on the second electrode 26 and the first electrode 27 .

[0127] The second insulating layer 28 covers the first insulating layer 24 , the second electrode 26 and the first electrode 27 , protecting the light-emitting diode structure from environmental influences and reducing the possibility of safety hazards caused by environmental changes and other reasons.

[0128] Optionally, the second insulating layer 28 is made of one or more combinations of SiN, SiO2 or DBR. These materials have good insulation properties and high safety, and can better reduce the possibility of safety hazards caused by environmental changes and other reasons.

[0129] Step 1909 : preparing the fourth electrode 29 and the third electrode 210 , wherein the fourth electrode 29 and the third electrode 210 penetrate the second insulating layer 28 .

[0130] The fourth electrode 29 is electrically connected to the second doping layer 2123 through the second electrode 26, and the third electrode 210 is electrically connected to the first doping layer 2121 through the first electrode 27, so that when the third electrode 210 and the fourth electrode 29 are powered on, power is supplied to the first electrode 27 and the second electrode 26, thereby making the light-emitting diode emit light.

[0131] For example, the third electrode 210 and the fourth electrode 29 are made of a combination of Ti (or Cr) Ni and AuSn. Ti (or Cr) acts as an adhesive, and AuSn and the subsequent package bracket are eutectic after reflow soldering, and then connected to the bracket.

[0132] Optionally, the material of the third electrode 210 and the fourth electrode 29 is a combination of Cr, Pt, Au, Ni, Pt, Al, AlCu, and AuSn.

[0133] In the embodiment of the present disclosure, step 1909 may include: etching a third through hole and a fourth through hole on the second insulating layer; preparing a fourth electrode 29 and a third electrode 210; the fourth electrode 29 is connected to the second electrode 26 through the fourth through hole, and the third electrode 210 is electrically connected to the third electrode 210 through the third through hole.

[0134] Exemplarily, the third through hole and the fourth through hole are etched on the second insulating layer by a photoresist, and the photolithography method of the third through hole and the fourth through hole can refer to that of the first through hole or the second through hole.

[0135] FIG20 is a flow chart of etching a first through hole in a first insulating layer according to an embodiment of the present disclosure. Referring to FIG20 , in an embodiment of the present disclosure, etching a first through hole 25 in a first insulating layer 24 includes:

[0136] Step 2001 : Coat photoresist on the side of the first insulating layer 24 facing away from the protective layer 23 .

[0137] Step 2002: Expose the photoresist through a photomask.

[0138] In the embodiment of the present disclosure, the photoresist is exposed using light with a wavelength of 365 nm, R2 = R1, S ranges from 400 to 600 nm, L = 1000 nm, and the exposure amount is 1300 to 1500 mj / cm 2 .

[0139] For example, S is 500 nm and the exposure amount is 1400 mj / cm 2 .

[0140] In the embodiment of the present disclosure, the portion of the photoresist corresponding to the first through hole is exposed using the light-transmitting area in the photoresist.

[0141] Step 2003: Develop the photoresist.

[0142] Illustratively, a single-chip developer is used to spray a developer for development.

[0143] Step 2004: Bake the photoresist.

[0144] In the embodiment of the present disclosure, a hot plate is used for baking, the hot plate baking temperature range is 130° C. to 135° C., and the baking time is 120 to 180 seconds.

[0145] Exemplarily, the hot plate baking temperature range is 132° C. and the baking time is 150 seconds.

[0146] Step 2005 : Etching the first insulating layer 24 .

[0147] In the disclosed embodiment, an ICP etching machine is used for etching in two stages. The first stage has a source power of 1100-1300W, a bias power of 490-510W, and a CF4 flow rate of 110-130sccm. The second stage has a source power of 490-510W, a bias power of 190-210W, and a CF4 flow rate of 110-130sccm.

[0148] For example, an ICP etching machine is used for etching in two stages: the first stage has a source power of 1200 W, a bias power of 500 W, and a CF4 flow rate of 120 sccm; the second stage has a source power of 500 W, a bias power of 200 W, and a CF4 flow rate of 120 sccm.

[0149] Step 2006: removing the remaining photoresist, thereby obtaining a first through hole 25 with a gentle slope.

[0150] In the embodiment of the present disclosure, photoresist is coated on a side of the first insulating layer 24 facing away from the protective layer 23 , including: the thickness of the coated photoresist is 10.5 to 11.5 microns.

[0151] Exemplarily, the photoresist thickness is 11 microns.

[0152] FIG21 is a flow chart of preparing an epitaxial wafer according to an embodiment of the present disclosure. Referring to FIG21 , in an embodiment of the present disclosure, preparing an epitaxial wafer 21 includes:

[0153] Step 2101: Provide a substrate 211.

[0154] Optionally, step 2101 includes:

[0155] The surface of the substrate 211 is processed using a patterned substrate technology.

[0156] Exemplarily, the substrate 211 is a sapphire substrate, a silicon wafer substrate, or other light-emitting diode substrate materials.

[0157] Step 2102 : forming an epitaxial layer 212 on the surface of the substrate 211 , wherein the epitaxial layer 212 includes a first doping layer 2121 , a light emitting layer 2122 , and a second doping layer 2123 stacked in sequence.

[0158] Optionally, step 2102 includes:

[0159] First, a first doping layer 2121 , a light emitting layer 2122 and a second doping layer 2123 are sequentially grown on the substrate 211 using a metal-organic chemical vapor deposition (MOCVD) technique.

[0160] Exemplarily, the first doped layer 2121 is an N-type gallium nitride layer, the light-emitting layer 2122 is a quantum well layer, and the second doped layer 2123 is a P-type gallium nitride layer.

[0161] Optionally, the method may further include: performing patterning on the epitaxial wafer to form structures such as steps and isolation trenches on the epitaxial wafer.

[0162] The step extends from the second doped layer 2123 to the first doped layer 2121, meaning the bottom of the step is located in the first doped layer 2121. After the first insulating layer is provided, a first through-hole formed in the first insulating layer is located at the bottom of the step, allowing the first electrode to pass through the first through-hole and electrically connect to the first doped layer 2121 exposed at the step. A second through-hole formed in the first insulating layer is located at a position on the surface of the second doped layer 2123 where the step is not formed, allowing the second electrode to pass through the second through-hole and electrically connect to the second doped layer 2123.

[0163] The photoresist provided in the embodiment of the present disclosure is used to achieve a gentle slope of the through-hole. The implementation method is simple. It only needs to add a diffraction pattern to the edge of the original pattern on the photoresist, and there is no need to adjust other procedures such as ICP etching (related schemes will do this to achieve a gentle slope); and by adjusting the relevant parameters of the diffraction pattern (such as R2, S, L, etc.), the morphology of the photoresist can be directly adjusted to the required angle with a large adjustment space, and then the morphology of the photoresist can be transferred to the chip through ICP etching.

[0164] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A photoresist, comprising a plurality of light-transmitting regions (1), wherein the light-transmitting regions (1) include an etching region (11) and a diffraction region (12); The etched area (11) is a circular hole; The diffraction region (12) includes a plurality of diffraction rings (121), the plurality of diffraction rings (121) surround the etched region (11), and the plurality of diffraction rings (121) are respectively concentric with the etched region (11), and the diffraction rings (121) include a plurality of diffraction holes (1211) arranged in sequence and spaced apart.

2. The photoresist according to claim 1, wherein The radius of the etched area (11) is R1, the diffraction area (12) is annular, the ring width of the diffraction area (12) is R2, and 0.5R1≤R2≤2R1.

3. The photoresist according to claim 1 or 2, wherein The shape of the diffraction hole (1211) is any one of rectangular, circular and triangular.

4. The photoresist according to claim 3, wherein The diffraction hole (1211) is a square with a side length of L1; The centers of the plurality of diffraction holes (1211) in the same diffraction ring (121) are all located on a first circle (13), and the first circle is concentric with the etched area (11); A perpendicular bisector on one side of the diffraction hole (1211) passes through the center of the etched area (11); The minimum distance between two adjacent diffraction holes (1211) in the same diffraction ring (121) is S1, and S1≤L1.

5. The photoresist according to claim 3, wherein The diffraction hole (1211) is a circle with a diameter of L2; The centers of the multiple diffraction holes (1211) within the same diffraction ring (121) are located on a second circle (14), and the second circle (14) is concentric with the etched area (11); The minimum distance between two adjacent diffraction holes (1211) in the same diffraction ring (121) is S2, and S2≤L2.

6. The photoresist according to claim 3, wherein The diffraction hole (1211) is an equilateral triangle with a side length of L3; The centers of the plurality of diffraction holes (1211) within the same diffraction ring (121) are located on a third circle (15), and the third circle (15) is concentric with the etched area (11); The perpendicular bisector of one side of the diffraction hole (1211) passes through the center of the etched area (11); The minimum distance between two adjacent diffraction holes (1211) in the same diffraction ring (121) is S3, and S3≤L3.

7. A method for preparing a light-emitting diode, the method being based on the photoresist according to any one of claims 1 to 6, the method comprising: An epitaxial wafer (21) is prepared, wherein the epitaxial wafer (21) comprises a stacked first doping layer (2121), a light-emitting layer (2122), and a second doping layer (2123); growing a first insulating layer (24) on one side of the second doped layer (2123); Etching a first through hole (25) and a second through hole (220) in the first insulating layer (24) by using the photoresist, so that the first through hole (25) passes through the first insulating layer (24) to the first doping layer (2121), and the second through hole (220) passes through the first insulating layer (24) to the second doping layer (2123); A first electrode (27) and a second electrode (26) are prepared on a side of the first insulating layer (24) facing away from the second doping layer (2123); the first electrode (27) is electrically connected to the epitaxial wafer (21) through the first through hole (25); and the second electrode (26) is electrically connected to the epitaxial wafer (21) through the second through hole (220).

8. A light-emitting diode, prepared by the method according to claim 7, comprising: A first doped layer (2121) having a first conductivity type; a light-emitting layer (2122), located on one side of the first doped layer (2121); a second doping layer (2123), located on a side of the light-emitting layer (2122) facing away from the first doping layer (2121), wherein the second doping layer (2123) is of a second conductivity type, and the second conductivity type is different from the first conductivity type; a first insulating layer (24), located on a side of the second doping layer (2123) facing away from the first doping layer (2121), and having a first through hole (25) and a second through hole (220); a first electrode (27), located on a side of the first insulating layer (24) facing away from the first doping layer (2121), and electrically connected to the first doping layer (2121) via the first through hole (25); The second electrode (26) is located on a side of the first insulating layer (24) facing away from the first doping layer (2121) and is electrically connected to the second doping layer (2123) through the second through hole (220).

9. The light emitting diode according to claim 8, wherein The first insulating layer (24) is a single layer of silicon oxide, and the thickness of the first insulating layer (24) is 1.8 μm to 3.0 μm; The angle between the hole wall of the first through hole (25) and the surface of the first doping layer (2121) is a first angle, and the angle between the hole wall of the second through hole (220) and the surface of the second doping layer (2123) is a second angle, and the first angle and the second angle are both greater than 30 degrees and less than 65 degrees.

10. The light emitting diode according to claim 8, wherein The first insulating layer (24) is a DBR multilayer, and the thickness of the first insulating layer (24) is 3.0 μm to 5.0 μm; The angle between the hole wall of the first through hole (25) and the surface of the first doped layer (2121) is a first angle, and the angle between the hole wall of the second through hole (220) and the surface of the second doped layer (2123) is a second angle, and the first angle and the second angle are both greater than 41 degrees and less than 54 degrees.

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