Imaging element, electronic apparatus

Abstract

[Problem] To provide an imaging element that has an improved FD-boosting function. [Solution] An imaging element 101 includes a plurality of photoelectric conversion units PD, a plurality of floating diffusions FD, a plurality of transfer gates TG that transfer charge that has been generated at the photoelectric conversion units PD to the floating diffusions FD, an FD connection region 50 that is a wiring region that connects the plurality of floating diffusions FD, an FD-boosting region 60 that is a wiring region that is for boosting the FD connection region 50, a plurality of first wiring paths 61 that electrically connect gate signal lines of the plurality of transfer gates TG and the FD-boosting region 60, and a second wiring path 62 that electrically connects the FD-boosting region 60 and a ground GND via a resistance. The FD connection region 50 and the FD-boosting region 60 are formed from an N-type semiconductor region, and the first wiring paths 61 have a PN junction that is formed from a P-type semiconductor region and an N-type semiconductor region.

Description

Imaging devices, electronic devices

[0001] The present disclosure relates to an imaging element and an electronic device that captures images through photoelectric conversion.

[0002] 2. Description of the Related Art Image pickup elements such as complementary metal oxide semiconductor (CMOS) image sensors are widely used in digital still cameras, digital video cameras, and the like.

[0003] A CMOS image sensor has multiple pixels. Light incident on each pixel undergoes photoelectric conversion in the photodiode of each pixel, generating an electric charge. The electric charge generated in the photodiode of each pixel is transferred to a floating diffusion (FD) via a transfer transistor.

[0004] In such a CMOS image sensor, it has been proposed to provide a boost wiring (FD boost wiring) for boosting the voltage of the floating diffusion FD (see Patent Document 1). By using this FD boost wiring to boost the FD when charges are transferred to the FD via the transfer transistor, the dynamic range of the FD can be secured and deterioration of the pumping characteristics can be suppressed.

[0005] Japanese Patent Application Laid-Open No. 2020-21987

[0006] An object of the technology disclosed herein is to provide an imaging element with an improved FD boost function.

[0007] According to one aspect of the present disclosure, there is provided an imaging element including: a plurality of photoelectric conversion units that generate charges according to an amount of received light through photoelectric conversion; a plurality of floating diffusions that hold charges transferred from the photoelectric conversion units; a plurality of transfer gates that transfer the charges generated in the photoelectric conversion units to the floating diffusions; an FD connection region that is a wiring region that connects the plurality of floating diffusions; an FD boost region that is a wiring region for boosting the FD connection region; a plurality of first wiring paths that electrically connect gate signal lines of the plurality of transfer gates to the FD boost region; and a second wiring path that electrically connects the FD boost region to ground via a resistor, wherein the FD connection region and the FD boost region are formed of N-type semiconductor regions, and the first wiring path has a PN junction formed of a P-type semiconductor region and an N-type semiconductor region. The FD boost region may be disposed to surround the FD connection region in a front view.

[0008] The imaging element may have a first semiconductor substrate, an interlayer insulating layer stacked on an upper surface side of the first semiconductor substrate, and a second semiconductor substrate stacked on an upper surface side of the interlayer insulating layer, wherein the photoelectric conversion section and the floating diffusion are formed in the first semiconductor substrate, and the N-type semiconductor regions of the FD connection region and the FD boost region, and the P-type semiconductor region and N-type semiconductor region of the PN junction are formed in the second semiconductor substrate.

[0009] The image sensor may have the FD connection region and the FD boost region formed of N-type polysilicon regions, and may have a first semiconductor substrate, an interlayer insulating layer laminated on an upper surface of the first semiconductor substrate, and a second semiconductor substrate laminated on an upper surface of the interlayer insulating layer, wherein the photoelectric conversion unit and the floating diffusion are formed in the first semiconductor substrate, the N-type polysilicon regions of the FD connection region and the FD boost region are formed in the interlayer insulating layer, and the P-type semiconductor region and the N-type semiconductor region of the PN junction are formed in the second semiconductor substrate. At least one of a plurality of transistors constituting a readout circuit may be formed on the second semiconductor substrate.

[0010] An imaging element according to one aspect of the present disclosure includes a plurality of photoelectric conversion units that generate charges according to an amount of received light by photoelectric conversion, a plurality of floating diffusions that hold charges transferred from the photoelectric conversion units, a plurality of transfer gates that transfer the charges generated in the photoelectric conversion units to the floating diffusions, an FD connection region that is a wiring region that connects the plurality of floating diffusions, an FD boost region that is a wiring region for boosting the FD connection region, and a plurality of gate signal lines that electrically connect the gate signal lines of the plurality of transfer gates to the FD boost region. a first wiring path and an FD boost power supply electrically connected to the FD boost region and capable of switching between a ground voltage and an ON voltage of the transfer gate, wherein the FD connection region and the FD boost region are formed of N-type semiconductor regions, the first wiring path has a PN junction formed of a P-type semiconductor region and an N-type semiconductor region, and the FD boost power supply supplies the ON voltage to the FD boost region when any of the plurality of transfer gates is ON, and supplies the ground voltage to the FD boost region when all of the plurality of transfer gates are OFF. The FD boost region may be arranged to surround the FD connection region in a front view.

[0011] The imaging element may have a plurality of FD shared units, which are structural units each having the plurality of photoelectric conversion units, the plurality of floating diffusions, the plurality of transfer gates, the FD connection region, the FD boost region, and the plurality of first wiring paths, the plurality of FD shared units being arranged side by side in one direction when viewed from the front, the FD boost regions of two FD shared units adjacent to each other in the one direction being connected to each other, and the FD boost power supply being connected to the FD boost region of the FD shared unit located outermost among the plurality of FD shared units arranged side by side in the one direction.

[0012] An electronic device according to one aspect of the present disclosure is an electronic device including the imaging element.

[0013] 9A is a block diagram showing a schematic configuration of an image sensor according to the present embodiment; FIG. 9B is a diagram showing the circuit configuration of pixels and a readout circuit; FIG. 9C is a plan layout diagram of a part of a pixel region in a pixel array section; FIG. 9D is a plan layout diagram showing the configuration of an image sensor according to a first embodiment; FIG. 9E is a longitudinal sectional view showing the configuration of an image sensor according to a first embodiment, showing a cross section along the path A-B in FIG. 4; FIG. 9H is a longitudinal sectional view showing the configuration of an image sensor according to a first embodiment, showing a cross section along the path C-D-E in FIG. 4; FIG. 9F is a longitudinal sectional view showing the circuit configuration and operation of an image sensor according to a first embodiment; FIG. 9J is a longitudinal sectional view showing an example of a method for manufacturing an image sensor according to a first embodiment; FIG. 9A is a longitudinal sectional view continuing from FIG. 9B; FIG. 9C is a longitudinal sectional view continuing from FIG. 9D; FIG. 9E is a longitudinal sectional view continuing from FIG. 9F; FIG. 9G is a longitudinal sectional view continuing from FIG. 9H; FIG. 9I is a longitudinal sectional view continuing from FIG. 9J; FIG. 9F is a plan layout diagram showing the configuration of an image sensor according to a modified example of the first embodiment. 10A and 10B are longitudinal cross-sectional views showing the configuration of an image sensor according to a modified example of the first embodiment, taken along the path A-B in FIG. 10. FIG. 10A and 10B are longitudinal cross-sectional views showing the configuration of an image sensor according to a modified example of the first embodiment, taken along the path C-D-E in FIG. 10. FIG. 10A and 10B are longitudinal cross-sectional views showing the configuration of an image sensor according to a modified example of the first embodiment, taken along the path C-D-F in FIG. 10. FIG. 10B are planar layout views of an image sensor according to a second embodiment, showing the configuration of a first layer. FIG. 10B are planar layout views of an image sensor according to a second embodiment, showing the configuration of a second layer. FIG. 10B are planar layout views of an image sensor according to a second embodiment, showing the arrangement of connection wiring. FIG. 14A are longitudinal cross-sectional views showing the configuration of an image sensor according to a second embodiment, taken along the path A-B in FIGS. 14A to 14C. FIG. 14C are longitudinal cross-sectional views showing the configuration of an image sensor according to a second embodiment, taken along the path C-D-E-D-F in FIGS. 14A to 14C. 14A to 14C. FIG. 19B is a longitudinal cross-sectional view showing the configuration of the image sensor of the second embodiment, taken along the line CDE-G in FIGS. 14A to 14C. FIG. 19C is a longitudinal cross-sectional view showing the configuration of the image sensor of the second embodiment, taken along the line H-I in FIGS. 14A to 14C. FIG. 19C is a longitudinal cross-sectional view showing an example of a manufacturing method for the image sensor of the second embodiment. FIG. 19A is a longitudinal cross-sectional view following FIG. 19B.19B is a longitudinal sectional view continuing from FIG. 19C. FIG. 19C is a longitudinal sectional view continuing from FIG. 19D. FIG. 19E is a longitudinal sectional view continuing from FIG. 19F. FIG. 19F is a planar layout diagram showing the configuration of an image sensor of a third embodiment. FIG. 19C is a planar layout diagram showing the configuration of an image sensor of a fourth embodiment. FIG. 19D is a planar layout diagram showing the configuration of an image sensor of a fifth embodiment. FIG. 19F is a planar layout diagram of a pixel region in a pixel array section of an image sensor of a fifth embodiment. FIG. 19C is a block diagram showing an example of the configuration of a camera as an electronic device. FIG. 19D is a block diagram showing a schematic example of the configuration of a vehicle control system, which is an example of a mobile body control system. FIG. 19F is a diagram showing an example of the installation position of an image sensor.

[0014] Hereinafter, examples of embodiments of the present disclosure will be described with reference to the drawings. The description will be made in the following order: 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Application example to electronic devices 7. Application example to mobile objects 8. Summary

[0015] 1. First Embodiment First, an image sensor 101 according to a first embodiment will be described.

[0016] (Basic Configuration of Image Sensor 101) The image sensor 101 of the first embodiment is a rolling shutter back-illuminated image sensor using a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0017] A back-illuminated image sensor is an image sensor in which the back surface of a semiconductor substrate serves as the light-receiving surface where light from a subject enters. In a back-illuminated image sensor, a photoelectric conversion unit such as a photodiode that receives light from a subject and converts it into an electrical signal is disposed for each pixel between the light-receiving surface and a wiring layer where wiring such as transistors that drive each pixel is provided.

[0018] The technology according to the present disclosure may be applicable to image sensors of imaging methods other than CMOS image sensors. Furthermore, the technology according to the present disclosure may be applicable to image sensors of not only rolling shutter type but also global shutter type. The image sensor 101 according to a fifth embodiment described below is a global shutter type image sensor.

[0019] FIG. 1 is a block diagram showing a schematic configuration of an image sensor 101 according to this embodiment.

[0020] As will be described later, the image sensor 101 of this embodiment is formed on a semiconductor substrate 11, and therefore is technically a solid-state image sensor, but will be simply referred to as an image sensor hereinafter.

[0021] The imaging element 101 includes, for example, a pixel array section 111, a vertical driving section 112, a ramp wave module 113, a column signal processing section 114, a clock module 115, a data storage section 116, a horizontal driving section 117, a system control section 118, and a signal processing section 119.

[0022] The pixel array unit 111 has a plurality of pixels 121, each including a photoelectric conversion element that generates and accumulates an electric charge according to the amount of light incident from a subject. The plurality of pixels 121 are arranged in a horizontal direction (row direction) and a vertical direction (column direction), as shown in FIG.

[0023] The pixel array unit 111 also has pixel drive lines 122 and vertical signal lines 123. The pixel drive lines 122 are wired along the row direction for each pixel row made up of pixels 121 arranged in a row in the row direction. The vertical signal lines 123 are wired along the column direction for each pixel column made up of pixels 121 arranged in a row in the column direction.

[0024] The vertical drive unit 112 includes a shift register, an address decoder, etc. The vertical drive unit 112 supplies signals and the like to the plurality of pixels 121 via the plurality of pixel drive lines 122, thereby driving all of the plurality of pixels 121 in the pixel array unit 111 simultaneously or driving them in units of pixel rows.

[0025] The ramp module 113 generates a ramp signal used for A / D (Analog / Digital) conversion of the pixel signal, and supplies the ramp signal to the column signal processing unit 114 .

[0026] The column signal processing unit 114 is composed of a shift register, an address decoder, etc., and performs noise removal processing, correlated double sampling processing, A / D conversion processing, etc. to generate pixel signals. The column signal processing unit 114 supplies the generated pixel signals to the signal processing unit 119.

[0027] The clock module 115 supplies clock signals for operation to each part of the image sensor 101 .

[0028] The horizontal driving unit 117 sequentially selects unit circuits corresponding to pixel columns in the column signal processing unit 114. Through selective scanning by the horizontal driving unit 117, pixel signals that have been signal-processed for each unit circuit in the column signal processing unit 114 are output to the signal processing unit 119 sequentially.

[0029] The system control unit 118 includes a timing generator that generates various timing signals, etc. The system control unit 118 controls the driving of the vertical driving unit 112, the ramp wave module 113, the column signal processing unit 114, the clock module 115, and the horizontal driving unit 117 based on the timing signals generated by the timing generator.

[0030] The signal processing unit 119 performs signal processing such as arithmetic processing on the pixel signals supplied from the column signal processing unit 114 while temporarily storing the data in the data storage unit 116 as necessary, and outputs an image signal consisting of each pixel signal.

[0031] The image sensor 101 is composed of multiple semiconductor substrates. For example, the image sensor 101 is composed by stacking a semiconductor substrate on which the pixel array section 111 is formed and a semiconductor substrate on which the vertical drive section 112, ramp wave module 113, column signal processing section 114, clock module 115, data storage section 116, horizontal drive section 117, system control section 118, and signal processing section 119 are formed. It is also possible to form some of the elements constituting the pixel array section 111 on a separate semiconductor substrate. As described below, in the image sensor 101 of the first embodiment, some of the elements constituting the pixel array section 111 (specifically, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL constituting the readout circuit 124 described below) are formed on a separate semiconductor substrate.

[0032] Fig. 2 is a diagram showing the circuit configuration of the pixel 121 and the readout circuit 124. Fig. 3 is a planar layout diagram of a part of the pixel region in the pixel array section 111. Fig. 3 shows a 2 × 2 = 4 pixel region. The pixel shown in Fig. 3 has a structure in which two photodiodes PD are arranged in one pixel (a so-called dual photodiode structure).

[0033] The image sensor 101 of the first embodiment has an improved accuracy in detecting the phase difference because the dual photodiode structure enables detection of the phase difference in all pixels of the pixel array unit 111. Furthermore, the image sensor 101 of the first embodiment can capture an image in all pixels, thereby preventing degradation of the captured image due to the phase difference detection pixels.

[0034] The technology according to the present disclosure can be applied not only to pixels with a dual photodiode structure, but also to normal pixels each having one photodiode PD.

[0035] As shown in FIGS. 2 and 3, in the image sensor 101 of the first embodiment, four pixels 121 share one readout circuit 124 .

[0036] Each pixel 121 has a photodiode PD, a transfer transistor TR, and a floating diffusion FD. In the illustrated example, two pixels 121 share one floating diffusion FD.

[0037] The read circuit 124 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

[0038] 3 does not show the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL that constitute the readout circuit 124. The reason for this is that, in the example shown in Fig. 3, these transistors are formed on a semiconductor substrate (a third semiconductor substrate 31, described later) separate from the semiconductor substrate (a first semiconductor substrate 11, described later) on which the main parts of the pixel array section 111 (such as the photodiode PD, the transfer transistor TR, and the floating diffusion FD) are arranged.

[0039] The photodiode PD generates electric charges according to the amount of received light through photoelectric conversion. The photodiode PD corresponds to a specific example of a "photoelectric conversion unit" in the present disclosure. The anode of the photodiode PD is connected to ground GND. The cathode of the photodiode PD is connected to the drain of the transfer transistor TR.

[0040] The transfer transistor TR transfers the charge (pixel signal) photoelectrically converted by the photodiode PD to the floating diffusion FD. The transfer transistor TR has a transfer gate TG (gate electrode). The source of the transfer transistor TR is connected to the cathode of the photodiode PD. The drain of the transfer transistor TR is connected to the floating diffusion FD. The transfer gate TG is connected to a pixel drive line 122.

[0041] The floating diffusion FD is a floating diffusion region that temporarily holds the charge transferred from the photodiode PD via the transfer transistor TR. The floating diffusion FD is connected to the drain of the transfer transistor TRG, the source of the reset transistor RST, and the gate of the amplification transistor AMP.

[0042] As described above, in the illustrated example, two pixels 121 share one floating diffusion FD. Furthermore, the two floating diffusions FD, each shared by two pixels 121, are electrically connected by wiring. Therefore, it can be said that these two floating diffusions FD essentially constitute one floating diffusion. In other words, it can be said that four pixels 121 essentially share one floating diffusion consisting of two floating diffusions FD and wiring.

[0043] In the illustrated example, since pixel 121 has a dual photodiode structure, four photodiodes share one floating diffusion FD, and eight photodiodes PD essentially share one floating diffusion consisting of two floating diffusions FD and wiring.

[0044] In this specification, a group of pixels 121 that essentially share one floating diffusion (in the illustrated example, consisting of two floating diffusions FD and wiring connecting them) is referred to as an "FD sharing unit (150)." In the illustrated example, the FD sharing unit 150 has four pixels 121 and two floating diffusions PD connected by wiring. However, the FD sharing unit 150 of the technology according to the present disclosure is not limited to one consisting of four pixels 121. Furthermore, the number of floating diffusions PD included in one FD sharing unit 150 is not limited to two.

[0045] The reset transistor RST initializes (resets) each region from the photodiode PD to the floating diffusion FD in response to a control signal applied to the gate electrode. The drain of the reset transistor RST is connected to the power supply line VDD. The source of the reset transistor RST is connected to the floating diffusion FD.

[0046] For example, when the transfer transistor TR and the reset transistor RST are turned on, the potentials of the photodiode PD and the floating diffusion FD are reset to the potential level of the power supply line VDD. That is, by turning on the reset transistor RST, the photodiode PD and the floating diffusion FD are initialized.

[0047] The amplifier transistor AMP has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as the input of a source follower circuit that reads out the charge obtained by photoelectric conversion in the photodiode PD. That is, the amplifier transistor AMP has a source connected to the vertical signal line VSL (123) via the selection transistor SEL, and thereby forms a source follower circuit together with a constant current source connected to one end of the vertical signal line VSL (123).

[0048] The selection transistor SEL has a source connected to the vertical signal line VSL (123) and a drain connected to the source of the amplification transistor AMP. A control signal is supplied to the gate electrode of the selection transistor SEL as a selection signal. When the control signal is turned on, the selection transistor SEL becomes conductive, and the pixel 121 connected to the selection transistor SEL becomes selected. When the pixel 121 becomes selected, the pixel signal output from the amplification transistor AMP is read out to the column signal processing unit 114 via the vertical signal line VSL (123).

[0049] The planar layout of the transfer gate TG of the transfer transistor TR in the pixel 121 is not limited to that shown in Fig. 3. If the arrangement of the transfer gate TG in the pixel 121 changes, the arrangement location of the photodiode PD disposed below it also changes.

[0050] The basic configuration of the image sensor 101 has been described above.

[0051] (Specific Configuration of Image Sensor 101 of First Embodiment) Next, a specific configuration of the image sensor 101 of the first embodiment will be described.

[0052] FIG. 4 is a planar layout diagram showing the configuration of the image sensor 101 according to the first embodiment.

[0053] Fig. 5 is a longitudinal cross-sectional view showing the configuration of the image sensor 101 of the first embodiment, showing a cross section taken along the path A-B in Fig. 4. Fig. 6 is a longitudinal cross-sectional view showing the configuration of the image sensor 101 of the first embodiment, showing a cross section taken along the path C-D-E in Fig. 4. Fig. 7 is a longitudinal cross-sectional view showing the configuration of the image sensor 101 of the first embodiment, showing a cross section taken along the path C-D-F in Fig. 4.

[0054] FIG. 8 is a diagram showing the circuit configuration and operation of the image sensor 101 of the first embodiment.

[0055] First, a brief description will be given of the configuration related to the function of boosting the voltage of the floating diffusion FD.

[0056] As shown in FIG. 8 , the FD sharing unit 150 of the image sensor 101 has an FD connection region 50 , an FD boosting region 60 , a first wiring path 61 , and a second wiring path 62 .

[0057] The FD connection region 50 is a wiring region that connects two floating diffusions FD included in a PD sharing unit. In the examples shown in Figures 4 to 7, the FD connection region 50 is configured by an N-type semiconductor region 21N. Furthermore, each floating diffusion FD and the FD connection region 50 are electrically connected by vertical wirings 41 and 42.

[0058] The FD boost region 60 is a wiring region for boosting the floating diffusion FD. The FD boost region 60 is arranged to surround the FD connection region 50. In the examples shown in FIGS. 4 to 7, the FD boost region 60 is formed by the N-type semiconductor region 21N.

[0059] The first wiring path 61 is connected to the gate signal line (V ＧＴ The first wiring paths 61 are wiring paths that electrically connect the first wiring paths 61 to the FD boosting region 60. The first wiring paths 61 also have a PN junction. The first wiring paths 61 are provided for each transfer gate TG. In other words, the FD sharing unit 150 of the image sensor 101 has the same number of first wiring paths 61 as the number of transfer gates TG.

[0060] 4 to 7, the first wiring path 61 is formed by the vertical wiring 43 and the P-type semiconductor region 21P. The PN junction of the first wiring path 61 is formed by the P-type semiconductor region 21P of the first wiring path 61 and the N-type semiconductor region 21N of the FD boosting region 60.

[0061] The second wiring path 62 is a wiring path that electrically connects the FD boost region 60 and ground GND. The second wiring path 62 also has a resistor R. In the example shown in FIGS. 4 to 7, the second wiring path is configured by a region that includes an N-type semiconductor region 21N and an intrinsic semiconductor region (resistance region) 21I, and the intrinsic semiconductor region (resistance region) 21I functions as a resistor.

[0062] 8, the gate voltage V of one of the transfer gates TG in the PD sharing unit is ＧＴ is the ON voltage V ＯＮ When this happens, the gate signal line (V ＧＴ ) is forward biased. ＧＴ ) to the FD boost region 60, increasing the potential of the FD boost region 60. As the potential of the FD boost region 60 increases, the FD connection region 50 surrounded by the FD boost region 60 is also boosted.

[0063] In addition, the ON voltage V ＯＮ The gate signal line (V ＧＴ ) to the FD boost region 60, and the potential of the FD boost region 60 rises. When ＯＦＦ The gate signal line (V ＧＴ) and the FD boost region 60, a reverse bias is applied to the PN junction of the first wiring path 61. Therefore, when the FD boost region 60 is connected to the gate signal line (V ＧＴ ) the current i does not flow into

[0064] As described above, the FD boosting region 60 is connected to the ground GND via the second wiring path 62 having the resistance R. Therefore, the gate voltage V ＧＴ is the OFF voltage V ＯＦＦ GND voltage V ＧＮＤ That is, the gate voltage V of all the transfer gates TG is applied. ＧＴ is the OFF voltage V ＯＦＦ When this occurs, the FD boosted region 60 will have the potential of ground GND.

[0065] With this configuration, the image sensor 101 of the first embodiment applies an ON voltage V ＯＮ When a pixel signal is read out from the photodiode PD by applying a voltage to the floating diffusion FD, the voltage of the floating diffusion FD can be boosted at the same time.

[0066] Next, the specific configuration of the image sensor 101 of the first embodiment will be described in detail.

[0067] 4 shows a planar layout of the FD sharing unit 150 of the image sensor 101. The vertical cross-sectional view of FIG. 5 shows a cross section along a path connecting two floating diffusions FD. The vertical cross-sectional view of FIG. 6 shows a cross section along a path connecting two floating diffusions FD. ＧＴ 7 shows a cross section along the path when current flows from two transfer gates TG (gate signal lines (V ＧＴ )) along the path connecting the two.

[0068] In this specification, the light-receiving surface side of the image sensor 101 is referred to as the "lower" side, and the side opposite the light-receiving surface side is referred to as the "upper" side. Furthermore, in each part of the image sensor 101, the lower surface is referred to as the "lower surface" and the upper surface is referred to as the "upper surface." Furthermore, the up-down direction is sometimes referred to as the "vertical direction," and the direction perpendicular to the up-down direction is sometimes referred to as the "horizontal direction."

[0069] The imaging element 101 of the first embodiment has a first layer 10 , a second layer 20 stacked on the first layer, and a third layer 30 stacked on the second layer 20 .

[0070] The first layer 10 has a first semiconductor substrate 11, a photodiode PD, a floating diffusion FD, a transfer gate TG, an interlayer insulating layer 12, vertical wiring 41, and a pad electrode 41a.

[0071] The first semiconductor substrate 11 is, for example, a single-crystal silicon substrate.

[0072] The photodiode PD is formed in the first semiconductor substrate 11. The photodiode PD is formed, for example, by providing a P-type well in an N-type semiconductor substrate 21 and providing a low-concentration N-type region in the P-type well.

[0073] The floating diffusion FD is formed in a region near the upper surface of the first semiconductor substrate 11. The floating diffusion FD is configured as, for example, a high concentration N-type region provided in a P-type well.

[0074] 5 to 7, the gate electrode TG is formed of a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11. The gate electrode TG may include a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11 and a vertical gate electrode extending in the depth direction of the semiconductor substrate 11.

[0075] The interlayer insulating layer 12 is laminated on the upper surface side of the first semiconductor substrate 11. The interlayer insulating layer 12 is made of, for example, SiO ２ It is made of an insulating material such as silicon dioxide.

[0076] The vertical wiring 41 is a wiring that extends in the vertical direction and is connected to the upper surfaces of the floating diffusion FD and the transfer gate TG. The vertical wiring 41 extends from the upper surfaces of the floating diffusion FD and the transfer gate TG to the upper surface of the interlayer insulating layer 12. The pad electrode 41a is formed at the upper end of the vertical wiring 41. The pad electrode 41a is joined to a pad electrode 42a formed at the lower end of a vertical wiring 42 of the second layer 20, which will be described later. The vertical wiring 41 and the pad electrode 41a are made of a metal material, such as copper or aluminum.

[0077] Although not shown, an element isolation portion that electrically isolates adjacent pixels 121 is provided within the first semiconductor substrate 11. A fixed charge film, a color filter, and a light-receiving lens are provided on the underside of the first semiconductor substrate 11. The fixed charge film is a film having a negative fixed charge for suppressing the generation of dark current due to the interface state on the back surface of the semiconductor substrate. A color filter and a light-receiving lens are provided for each pixel 121.

[0078] The second layer 20 has an N-type semiconductor region 21N that constitutes the FD connection region 50, an N-type semiconductor region 21N that constitutes the FD boost region 60, a P-type semiconductor region 21P that constitutes the first wiring path 61, a region consisting of the N-type semiconductor region 21N and an intrinsic semiconductor region (resistance region) 21I that constitutes the second wiring path 62, interlayer insulating layers 22, 23, vertical wirings 42, 43, and a pad electrode 42a.

[0079] The N-type semiconductor region 21N, the P-type semiconductor region 21P, and the intrinsic semiconductor region (resistance region) 21I of the second layer 20 are regions formed in a second semiconductor substrate 21. The second semiconductor substrate 21 is, for example, a single crystal silicon substrate.

[0080] The N-type semiconductor region 21N is a region made of an N-type semiconductor. The N-type semiconductor region 21N is, for example, a region made of N-type single crystal silicon (an N-type single crystal polysilicon region). The P-type semiconductor region 21P is a region made of a P-type semiconductor. The P-type semiconductor region 21P is, for example, a region made of P-type single crystal silicon (a P-type single crystal silicon region). The intrinsic semiconductor region (resistance region) 21I is a region made of an intrinsic semiconductor. The intrinsic semiconductor region (resistance region) 21I is, for example, a region made of intrinsic single crystal silicon (an intrinsic single crystal silicon region). However, the intrinsic semiconductor region (resistance region) 21I only needs to have a certain resistance, and may be doped with a small amount of impurities.

[0081] 4, the N-type semiconductor region 21N constituting the FD connection region 50 has a strip-like shape in a front view. That is, the FD connection region 50 has a strip-like shape in a front view. The FD connection region 50 is electrically connected to the floating diffusion FD by vertical wirings 42 and 41 extending downward from near both ends of the strip-like shape.

[0082] In this specification, the term "front view" refers to observation from a direction perpendicular to the top surface of the image sensor 101.

[0083] 4, the N-type semiconductor region 21N constituting the FD boost region 60 has a hollow rectangular shape in front view, and surrounds the N-type semiconductor region 21N constituting the FD boost region 60. In other words, the N-type semiconductor region 21N constituting the FD boost region 60 has a strip-like shape in front view, and surrounds the N-type semiconductor region 21N constituting the FD boost region 60 along a rectangular path.

[0084] That is, the FD boost region 60 has a rectangular shape with a hollow inside when viewed from the front, and surrounds the FD boost region 60. Moreover, the FD boost region 60 has a band-like shape, and can be said to surround the FD boost region 60 along a rectangular path.

[0085] 4, the P-type semiconductor region 21P constituting the first wiring path 61 has a strip-like shape in a front view. One end of the strip-like P-type semiconductor region 21P is connected to the gate signal line (V ＧＴ ) and is electrically connected to the transfer gate TG via vertical wirings 42 and 41. The other end is connected to the long side of the rectangle of the N-type semiconductor region 21N that constitutes the FD boosting region 60.

[0086] A PN junction is formed by the P-type semiconductor region 21P that constitutes the first wiring path 61 and the N-type semiconductor region 21N that constitutes the FD boosting region 60. This PN junction allows the gate signal line (V ＧＴ ) to the FD boost region 60, while a current i flows from the FD boost region 60 to the gate signal line (V ＧＴ ) is designed so that the current i does not flow.

[0087] 4 , the region consisting of the N-type semiconductor region 21N and the intrinsic semiconductor region (resistance region) 21I that constitutes the second wiring path 62 has a strip-like shape when viewed from the front. One end of the strip-like region consisting of the N-type semiconductor region 21N and the intrinsic semiconductor region (resistance region) 21I is connected to the center of the long rectangular side of the N-type semiconductor region 21N that constitutes the FD boost region 60. The other end is electrically connected to ground GND via the vertical wiring 43.

[0088] The interlayer insulating layers 22 and 23 are laminated on the upper and lower surfaces of the second semiconductor substrate 21. The interlayer insulating layers 22 and 23 are made of, for example, SiO ２ It is made of an insulating material such as silicon dioxide.

[0089] The vertical wiring 42 is a wiring extending in the vertical direction and connected to the lower surfaces of the N-type semiconductor region 21N of the FD connection region 50 and the P-type semiconductor region 21P of the first wiring path 61. The vertical wiring 42 extends from the lower surfaces of the N-type semiconductor region 21N and the P-type semiconductor region 21P to the lower surface of the interlayer insulating layer 23. The pad electrode 42a is formed at the lower end of the vertical wiring 42. The pad electrode 42a is joined to the pad electrode 41a formed at the upper end of the vertical wiring 41 of the first layer 10 described above. The vertical wiring 42 and the pad electrode 42a are made of a metal material such as copper or aluminum.

[0090] The vertical wiring 43 is a wiring that extends in the vertical direction and is connected to the upper surfaces of the N-type semiconductor region 21N of the FD connection region 50, the P-type semiconductor region 21P of the first wiring path 61, and the N-type semiconductor region 21N of the second wiring path 62. The vertical wiring 43 extends from the upper surfaces of these N-type semiconductor region 21N and P-type semiconductor region 21P to a wiring layer 39 of the third layer 30, which will be described later. The vertical wiring 43 is made of a metal material, such as copper or aluminum.

[0091] The third layer 30 has a third semiconductor substrate 31, an interlayer insulating layer 32, an inner through-hole insulating layer 34, vertical wiring 43, and a wiring layer 39. The third layer 30 also has transistors that constitute a readout circuit 124 formed on the third semiconductor substrate 31.

[0092] The third semiconductor substrate 31 is, for example, a single crystal silicon substrate.

[0093] The interlayer insulating layer 31 is laminated on the upper surface side of the third semiconductor substrate 31. The interlayer insulating layer 31 is made of, for example, SiO ２ It is made of an insulating material such as silicon dioxide.

[0094] The through-hole insulating layer 34 is an insulating layer provided inside the through-hole provided in the third semiconductor substrate 31 to pass the vertical wiring 43. The through-hole insulating layer 34 is made of, for example, SiN (silicon nitride), SiO ２ It is made of insulating materials such as silicon dioxide.

[0095] The vertical wiring 43 is a wiring that extends in the vertical direction from the wiring layer 39 to the second layer 20. The vertical wiring 43 is made of a metal material such as copper or aluminum.

[0096] The wiring layer 39 is a layer in which various types of wiring are formed. The wiring layer 39 is laminated on the upper surface side of the interlayer insulating layer 32.

[0097] Furthermore, on the third semiconductor substrate 31, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and the like that constitute a read circuit 124 are formed.

[0098] The image sensor 101 of the first embodiment has the above-described configuration.

[0099] In the conventional configuration in which FD boost wiring is provided, it is necessary to lay the FD boost wiring and wiring connecting the power supply and the FD boost wiring, which causes a problem of restricting the wiring layout of the CMOS image sensor. However, in the image sensor 101 of the first embodiment described above, the FD boost regions 60 and 21N are formed in the semiconductor region, and the ON voltage V of the transfer gate TG is ＯＮ By using this to boost the voltage of the floating diffusion FD, the wiring layout is less constrained.

[0100] In the image sensor 101 of the first embodiment, the periphery of the FD connection region 50, 21N is connected to the ON voltage V ＯＮ or GND voltage V ＧＮＤ Therefore, the image sensor 101 of the first embodiment is less susceptible to the influence of crosstalk of signals from the surrounding FD sharing units 150.

[0101] It should be noted that the FD boost region 60 of the technology according to the present disclosure does not necessarily have to be disposed so as to surround the FD connection region 50. The FD boost region 60 only needs to be disposed in a manner that allows it to boost the FD connection region 50 and the floating diffusion FD. Therefore, the FD boost region 60 only needs to be disposed adjacent to the FD connection region 50.

[0102] However, from the viewpoint of reducing the influence of signal crosstalk from the surrounding FD sharing units 150 described above, it is preferable that the FD boosting region 60 be arranged so as to surround the FD connection region 50 in a front view.

[0103] (Method for Manufacturing the Image Sensor 101 of the First Embodiment) Next, an example of a method for manufacturing the image sensor 101 of the first embodiment will be described.

[0104] 9A to 9K are longitudinal cross-sectional views showing an example of a method for manufacturing the image sensor 101 according to the first embodiment.

[0105] The imaging element 101 of the first embodiment is manufactured by bonding together a laminate constituting the first layer 10 and a laminate constituting the second layer 20 and the third layer 30, which are molded separately.

[0106] 9A , in forming the stacked body that constitutes the first layer 10, first, a photodiode PD, a floating diffusion FD, a transfer gate TG, and a high-concentration P-type region 10c are formed in a first semiconductor substrate 21. The high-concentration P-type region 10c is a region that is electrically connected to the ground GND.

[0107] The first semiconductor substrate 21 is, for example, a single-crystal silicon substrate. The photodiode PD is formed, for example, by providing a P-type well in the N-type semiconductor substrate 21 and providing a low-concentration N-type region in the P-type well. The floating diffusion FD is, for example, configured as a high-concentration N-type region provided in the P-type well.

[0108] Next, as shown in FIG. 9B, an interlayer insulating layer 12, vertical wiring 41, and pad electrodes 41a are formed on the first semiconductor substrate 11.

[0109] The interlayer insulating layer 12 is made of SiO ２ The vertical wiring 41 and the pad electrode 41a are formed by laminating insulating materials such as silicon oxide. The vertical wiring 41 and the pad electrode 41a are made of a metal material such as copper or aluminum.

[0110] The interlayer insulating layer 12, the vertical wiring 41, and the pad electrode 41a can be formed by appropriately using well-known techniques such as, for example, CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), sputtering, plating, dry etching, wet etching, etc. The same applies to the steps for which the description of the formation method is omitted below.

[0111] In this way, a laminate constituting the first layer 10 of the imaging element 101 is formed.

[0112] In forming the laminate constituting the second layer 20 and the third layer 30, first, as shown in FIG. 9C , an N-type semiconductor region 21N, a P-type semiconductor region 21P, and an intrinsic semiconductor region (resistance region) 21I constituting the FD connection region 50, the FD boost region 60, the first wiring path 61, and the second wiring path 62 are formed near the upper surface of the second semiconductor substrate 21.

[0113] Thereafter, the substrate material is removed from regions near the upper surface of the second semiconductor substrate 21 except for the N-type semiconductor region 21N, the P-type semiconductor region 21P, and the intrinsic semiconductor region (resistance region) 21I. Thereafter, an interlayer insulating layer 22 is laminated on the second semiconductor substrate 21.

[0114] The second semiconductor substrate 21 is, for example, a single crystal silicon substrate. The N-type semiconductor region 21N is, for example, a region made of single crystal silicon doped with phosphorus. The P-type semiconductor region 21P is, for example, a region made of single crystal silicon doped with boron. The intrinsic semiconductor region (resistance region) 21I is, for example, a region made of single crystal silicon not doped with impurities. However, the intrinsic semiconductor region (resistance region) 21I only needs to have a certain resistance, and may be doped with a small amount of impurities. The interlayer insulating layer 12 is, for example, a SiO ２ It is formed by stacking insulating materials such as silicon dioxide.

[0115] Next, as shown in FIG. 9D, a third semiconductor substrate 31 is laminated on the interlayer insulating layer 22. The third semiconductor substrate 31 is, for example, a single crystal silicon substrate.

[0116] 9E, the upper surface side of the third semiconductor substrate 31 stacked on the interlayer insulating layer 22 is thinned. The third semiconductor substrate 31 can be thinned by, for example, CMP (Chemical Mechanical Polishing).

[0117] 9F, through holes for the vertical wiring 43 to be formed later are provided in the third semiconductor substrate 31, and an in-through-hole insulating layer 34 is formed in the through holes. The in-through-hole insulating layer 34 is made of, for example, silicon nitride (SiN), SiO ２ The third semiconductor substrate 31 is made of an insulating material such as silicon oxide. The reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the like that constitute the readout circuit 124 are formed on the third semiconductor substrate 31.

[0118] 9G, an interlayer insulating layer 32 and vertical wiring 43 are formed on the third semiconductor substrate 31. The interlayer insulating layer 32 is made of SiO ２ The vertical wiring 43 is formed by laminating insulating materials such as silicon oxide (SiO 2 ). The vertical wiring 43 is made of a metal material such as copper or aluminum. Thereafter, a wiring layer 39 is formed on the interlayer insulating layer 32 .

[0119] Next, as shown in FIG. 9H, the underside of the second semiconductor substrate 21 is thinned. The second semiconductor substrate 21 can be thinned by, for example, CMP. As a result, only the N-type semiconductor region 21N, the P-type semiconductor region 21P, and the intrinsic semiconductor region (resistance region) 21I remain in the second semiconductor substrate 21.

[0120] 9I, an interlayer insulating layer 23, a vertical electrode 42, and a pad electrode 42a are formed on the underside of the interlayer insulating layer 22, the N-type semiconductor region 21N, the P-type semiconductor region 21P, and the intrinsic semiconductor region (resistance region) 21I. The vertical wiring 42 and the pad electrode 42a are made of a metal material such as copper or aluminum.

[0121] In this way, a laminate constituting the second layer 20 and the third layer 30 of the image sensor 101 is formed.

[0122] 9J and 9K, the upper surface of the laminate constituting the first layer 10 is bonded to the lower surfaces of the laminates constituting the second layer 20 and the third layer 30. At this time, the pad electrode 41a formed on the upper surface of the first layer 10 and the pad electrode 42a formed on the lower surface of the second layer 20 are bonded to each other.

[0123] In this manner, the image sensor 101 of the first embodiment can be manufactured.

[0124] To summarize the above, the image sensor 101 of the first embodiment includes a photodiode PD (photoelectric conversion unit), a plurality of floating diffusions FD, a plurality of transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, and gate signal lines (V ＧＴ The FD boost region 60 includes a plurality of first wiring paths 61 that electrically connect the FD boost region 60 to the FD boost region 60, and a second wiring path 62 that electrically connects the FD boost region 60 to the ground GND via a resistor. The first wiring paths 61 include a PN junction that is formed by a P-type semiconductor region and an N-type semiconductor region.

[0125] The image sensor 101 of the first embodiment also has a first semiconductor substrate 21, interlayer insulating layers 12 and 23, and a second semiconductor substrate 21. The photodiode PD (photoelectric conversion unit) and floating diffusion FD are formed in the first semiconductor substrate 21, and the N-type semiconductor region 21N of the FD connection region 50 and the FD boost region 60, and the P-type semiconductor region 21P and N-type semiconductor region 21N of the PN junction are formed in the second semiconductor substrate 21.

[0126] Such an image pickup device 101 reduces the burden on the wiring layout.

[0127] Furthermore, in the image sensor 101 of the first embodiment, the FD boosting region 60 is disposed to surround the FD connection region 50 in a front view. In this image sensor 101, the influence of crosstalk is suppressed.

[0128] (Modification of the Image Sensor 101 of the First Embodiment) Next, a modification of the image sensor 101 of the first embodiment will be described.

[0129] FIG. 10 is a planar layout diagram showing the configuration of an image sensor 101 according to a modified example of the first embodiment.

[0130] 11 to 13 are longitudinal cross-sectional views showing the configuration of an image sensor 101 according to a modified example of the first embodiment. Fig. 11 shows a cross section taken along the path A-B in Fig. 10. Fig. 12 shows a cross section taken along the path C-D-E in Fig. 10. Fig. 13 shows a cross section taken along the path C-D-F in Fig. 10.

[0131] The imaging element 101 of the modified example has the same configuration as that of this embodiment, except for the points described below.

[0132] In the first embodiment, as shown in FIG. 5, the N-type semiconductor region 21N constituting the FD connection region 50 is electrically connected to the floating diffusion FD via the vertical wirings 42 and 41.

[0133] On the other hand, in the modified image sensor 101, as shown in FIG. 11, the N-type semiconductor region 21N constituting the FD connection region 50 is electrically connected to the floating diffusion FD via a vertical wiring 45 made of N-type polysilicon.

[0134] In the first embodiment, as shown in FIGS. 6 and 7, the P-type semiconductor region 21P constituting the first wiring path 61 is electrically connected to the transfer gate TG via the vertical wirings 42 and 41 extending downward, and the gate voltage V ＧＴ The device was electrically connected to the

[0135] 12 and 13, in the image sensor 101 of the modified example, the P-type semiconductor region 21P constituting the first wiring path 61 is electrically connected to the transfer gate TG via a vertical wiring 45 made of P-type polysilicon extending downward. The P-type semiconductor region 21P constituting the first wiring path 61 is electrically connected to the transfer gate TG via a vertical wiring 45 made of P-type polysilicon extending downward. ＧＴ In the image sensor 101 of the modified example, as shown in FIGS. 12 and 13, the gate voltage V of the transfer gate TGＧＴ The vertical wiring 44 connected to the first wiring path 61 is connected to the transfer gate TG. That is, in the image sensor 101 of the modified example, the P-type semiconductor region 21P constituting the first wiring path 61 is connected to the gate voltage V ＧＴ The device is electrically connected to the

[0136] As described above, the configuration of the first wiring path 61 of the technology according to the present disclosure is not limited to the configuration of Embodiment 1. The first wiring path 61 of the technology according to the present disclosure may be any wiring path that electrically connects the transfer gate TG and the FD boost region 60 and has a PN junction.

[0137] 2. Second Embodiment Next, an image sensor according to a second embodiment will be described.

[0138] The image sensor 101 of the second embodiment has the same configuration as that of the first embodiment, except for the configuration described below.

[0139] 14A to 14C are planar layout diagrams of the image sensor 101 of the second embodiment. FIG. 14A shows the configuration of the first layer 10. FIG. 14B shows the configuration of the second layer 20. FIG. 14C shows the arrangement of connection wirings 291 and 292.

[0140] Figures 15 to 18 are longitudinal cross-sectional views showing the configuration of the image sensor 101 of the second embodiment. Figure 15 shows a cross section taken along the path A-B in Figures 14A to 14C. Figure 16 shows a cross section taken along the path C-D-E-D-F in Figures 14A to 14C. Figure 17 shows a cross section taken along the path C-D-E-G in Figures 14A to 14C. Figure 18 shows a cross section taken along the path H-I in Figures 14A to 14C.

[0141] The circuit configuration and operation of the image sensor 101 of the first embodiment shown in FIG. 8 also apply to the image sensor 101 of the second embodiment.

[0142] First, a brief description will be given of the configuration related to the function of boosting the voltage of the floating diffusion FD.

[0143] As shown in Figure 8, the FD sharing unit 150 of the image sensor 101 of the second embodiment also has an FD connection region 50, an FD boost region 60, a first wiring path 61, and a second wiring path 62, similar to the first embodiment.

[0144] The FD connection region 50 is a wiring region that connects two floating diffusions FD included in a PD sharing unit. In the examples shown in Figures 14A to 18, the FD connection region 50 is configured by an N-type polysilicon region 15N. Furthermore, each floating diffusion FD and the FD connection region 50 are electrically connected by vertical wiring 46.

[0145] The FD boost region 60 is a wiring region for boosting the floating diffusion FD. The FD boost region 60 is a wiring region arranged to surround the FD connection region 50. In the examples shown in FIGS. 14A to 18, the FD boost region 60 is formed by an N-type polysilicon region 15N.

[0146] The first wiring path 61 is connected to the gate signal line (V ＧＴ The first wiring paths 61 electrically connect the transfer gates TG and the FD boosting region 60. The first wiring paths 61 also have a PN junction. The first wiring paths 61 are provided for each transfer gate TG. In other words, the shared unit of the image sensor 101 has the same number of first wiring paths 61 as the number of transfer gates TG.

[0147] 14A to 18, the first wiring path 61 is configured by the vertical wiring 48-P-type semiconductor region 21P-N-type semiconductor region-vertical wiring 48-connection wiring 292-vertical wiring 47. The PN junction of the first wiring path 61 is configured by the P-type semiconductor region 21P and the N-type semiconductor region 21N in the first wiring path 61.

[0148] The second wiring path 62 is a wiring path that electrically connects the FD boost region 60 and the ground GND. The second wiring path 62 also has a resistor R. In the example shown in FIGS. 14A to 18, the second wiring path is configured by a region that includes an N-type polysilicon region 15N and an intrinsic polysilicon region (resistance region) 15I, and the intrinsic polysilicon region (resistance region) 15I functions as a resistor.

[0149] As shown in FIG. 8, with this configuration, the gate voltage V of one of the transfer gates TG present in the PD sharing unit ＧＴ is the ON voltage V ＯＮ When this happens, the gate signal line (V ＧＴ ) is forward biased. ＧＴ ) to the FD boost region 60, increasing the potential of the FD boost region 60. As the potential of the FD boost region 60 increases, the FD connection region 50 surrounded by the FD boost region 60 is also boosted.

[0150] In addition, the ON voltage V ＯＮ The gate signal line (V ＧＴ ) to the FD boost region 60, and the potential of the FD boost region 60 rises. When ＯＦＦ The gate signal line (V ＧＴ ) and the FD boost region 60. Therefore, a reverse bias is applied to the PN junction of the first wiring path 61 connecting the FD boost region 60 to the gate signal line (V ＧＴ ) the current i does not flow into

[0151] As described above, the FD boosting region 60 is connected to the ground GND via the second wiring path 62 having the resistance R. Therefore, the gate voltage V ＧＴ is the OFF voltage V ＯＦＦ GND voltage V ＧＮＤ That is, the gate voltage V of all the transfer gates TG is applied. ＧＴ is the OFF voltage V ＯＦＦ When this occurs, the FD boosted region 60 will have the potential of ground GND.

[0152] With this configuration, the image sensor 101 of the first embodiment applies an ON voltage V ＯＮWhen a pixel signal is read out from the photodiode PD by applying a voltage to the floating diffusion FD, the voltage of the floating diffusion FD can be boosted at the same time.

[0153] Next, the specific configuration of the image sensor 101 according to the second embodiment will be described in detail.

[0154] 14A to 14C show the planar layout of the FD sharing unit 150 of the image sensor 101. The vertical cross-sectional view of FIG. 15 shows a cross section along a path connecting two floating diffusions FD. The vertical cross-sectional view of FIG. 16 shows a cross section along a path connecting two floating diffusions FD. ＧＴ 17 and 18 show cross sections along the path of current flowing from two transfer gates TG (gate signal lines (V ＧＴ )) along the path connecting the two.

[0155] The imaging element 101 of the second embodiment has a first layer 10 and a second layer 20 stacked on the first layer.

[0156] The first layer 10 includes a first semiconductor substrate 11 , a photodiode PD, a floating diffusion FD, a transfer gate TG, an interlayer insulating layer 12 , a polysilicon wiring layer 15 , and vertical wirings 46 and 47 .

[0157] The first semiconductor substrate 11 is, for example, a single crystal silicon substrate.

[0158] The photodiode PD is formed in the first semiconductor substrate 11. The photodiode PD is formed, for example, by providing a P-type well in an N-type semiconductor substrate 21 and providing a low-concentration N-type region in the P-type well.

[0159] The floating diffusion FD is formed in a region near the upper surface of the first semiconductor substrate 11. The floating diffusion FD is configured as, for example, a high concentration N-type region provided in a P-type well.

[0160] 14A to 18, the gate electrode TG is formed of a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11. The gate electrode TG may have a horizontal gate electrode extending in a direction parallel to the upper surface of the semiconductor substrate 11 and a vertical gate electrode extending in the depth direction of the semiconductor substrate 11.

[0161] The interlayer insulating layer 12 is laminated on the upper surface side of the first semiconductor substrate 11. The interlayer insulating layer 12 is made of, for example, SiO ２ It is made of an insulating material such as silicon dioxide.

[0162] The polysilicon wiring layer 15 is a layer formed in the interlayer insulating layer 12. The polysilicon wiring layer 15 includes an N-type polysilicon region 15N constituting the FD connection region 50, an N-type polysilicon region 15N constituting the FD boost region 60, a region consisting of the N-type polysilicon region 15N and an intrinsic polysilicon region (resistance region) 15I constituting the second wiring path 62, and a gate signal line (V ＧＴ ) and a P-type polysilicon region 15P that forms a wiring path connecting the transfer gate TG.

[0163] The N-type polysilicon region 15N is a region made of N-type polysilicon. The P-type polysilicon region 15P is a region made of P-type polysilicon. The intrinsic semiconductor region (resistance region) 21I is a region made of intrinsic polysilicon. The intrinsic semiconductor region (resistance region) 21I is a region made of intrinsic polysilicon. However, the intrinsic polysilicon region (resistance region) 15I only needs to have a certain resistance, and may be doped with a small amount of impurities.

[0164] 14A , the N-type polysilicon region 15N constituting the FD connection region 50 has a band-like shape in a front view. That is, the FD connection region 50 has a band-like shape in a front view. The FD connection region 50 is electrically connected to the floating diffusion FD by vertical wiring 46 extending downward from near both ends of the band-like shape.

[0165] 14A , the N-type polysilicon region 15N constituting the FD boost region 60 has a hollow rectangular shape in front view, and surrounds the N-type polysilicon region 15N constituting the FD boost region 60. In other words, the N-type polysilicon region 15N constituting the FD boost region 60 has a band-like shape in front view, and surrounds the N-type polysilicon region 15N constituting the FD boost region 60 along a rectangular path.

[0166] That is, the FD boost region 60 has a rectangular shape with a hollow inside when viewed from the front, and surrounds the FD boost region 60. Moreover, the FD boost region 60 has a band-like shape, and can be said to surround the FD boost region 60 along a rectangular path.

[0167] 14A , the region consisting of the N-type polysilicon region 15N and the intrinsic polysilicon region (resistance region) 15I that constitutes the second wiring path 62 has a strip-like shape when viewed from the front. One end of the strip-like region consisting of the N-type polysilicon region 15N and the intrinsic polysilicon region (resistance region) 15I is connected to the center of the long side of the rectangle of the N-type polysilicon region 15N that constitutes the FD boost region 60. The other end is electrically connected to ground GND via the vertical wiring 47.

[0168] Gate signal line (V ＧＴ The P-type polysilicon region 15P, which constitutes a wiring path connecting the gate signal line (V ) and the transfer gate TG, has a strip-like shape when viewed from the front. One end of the strip-like shape is electrically connected to the transfer gate TG via a vertical wiring 46. The other end is electrically connected to the gate signal line (V ＧＴ ) is electrically connected to

[0169] The vertical wiring 46 is connected to the N-type polysilicon region 15N constituting the FD connection region 50, the gate signal line (V ＧＴThe vertical wiring 46 connected to the lower surface of the N-type polysilicon region 15N constituting the FD connection region 50 is made of N-type polysilicon and extends to the floating diffusion FD. ＧＴ A vertical wiring 46 connected to the lower surface of the P-type polysilicon region 15P, which constitutes a wiring path connecting the P-type polysilicon region 15P and the transfer gate TG, is made of P-type polysilicon and extends to the transfer gate TG.

[0170] The vertical wiring 47 is connected to the N-type polysilicon region 15N constituting the FD connection region 50, the N-type polysilicon region 15N constituting the second wiring path 62, and the gate signal line (V ＧＴ The vertical wiring 47 is connected to the upper surface of the P-type polysilicon region 15P, which constitutes a wiring path connecting the N-type polysilicon region 15N and the P-type polysilicon region 15P, and extends in the vertical direction. The vertical wiring 47 extends from the upper surfaces of the N-type polysilicon region 15N and the P-type polysilicon region 15P to a wiring layer 29 of the second layer 20, which will be described later. The vertical wiring 47 is made of a metal material, such as copper or aluminum.

[0171] The second layer 20 has a second semiconductor substrate 21, a P-type semiconductor region 21P and an N-type semiconductor region 21N that form the first wiring path 61, an interlayer insulating layer 22, an inner-through-hole insulating layer 24, vertical wirings 47 and 48, connection wirings 291 and 292, and a wiring layer 29. The second layer 20 also has transistors that form a readout circuit 124 formed on the second semiconductor substrate 21.

[0172] The second semiconductor substrate 21 is, for example, a single crystal silicon substrate.

[0173] As shown in FIG. 14B , the N-type semiconductor region 21N constituting the first wiring path 61 has a hollow rectangular shape in front view (hollow rectangle), with the central portion of the short side of the rectangle separated. In other words, the N-type semiconductor region 21N constituting the first wiring path 61 has a strip-like shape in front view, extends along a rectangular path, and is separated at the central portion of the short side of the rectangle. These separated portions are electrically connected to each other via the vertical wiring 48, the connection wiring 292, and the vertical wiring 48, as shown in FIGS. 14B , 14C , and 17 .

[0174] 14B, the P-type semiconductor region 21P constituting the first wiring path 61 has a strip-like shape in a front view. One end of the strip-like P-type semiconductor region 21P is connected to the gate signal line (V ＧＴ The other end is connected to the long side of the rectangle of the N-type semiconductor region 21N that constitutes the first wiring path 61.

[0175] A PN junction is formed by the P-type semiconductor region 21P and the N-type semiconductor region 21N that form the first wiring path 61. This PN junction allows the gate signal line (V ＧＴ ) to the FD boost region 60, while a current i flows from the FD boost region 60 to the gate signal line (V ＧＴ ) is designed so that the current i does not flow.

[0176] The interlayer insulating layer 22 is laminated on the upper surface side of the second semiconductor substrate 21. The interlayer insulating layer 22 is made of, for example, SiO ２ It is made of an insulating material such as silicon dioxide.

[0177] The through-hole insulating layer 24 is an insulating layer provided inside a through-hole provided in the second semiconductor substrate 21 to pass the vertical wiring 47. The through-hole insulating layer 24 is made of an insulating material such as SiN (silicon nitride) or SiO2 (silicon oxide).

[0178] The vertical wiring 47 is a wiring that extends vertically from the wiring layer 29 to the first layer 10. The vertical wiring 48 is a wiring that extends vertically from the wiring layer 29 to the second semiconductor substrate 21. The connection wirings 291 and 292 are wirings that connect the vertical wirings 47 and 48. The vertical wirings 47 and 48 and the connection wirings 291 and 292 are made of a metal material such as copper or aluminum.

[0179] The wiring layer 29 is a layer in which various types of wiring are formed. The wiring layer 29 is laminated on the upper surface side of the interlayer insulating layer 22.

[0180] Furthermore, on the second semiconductor substrate 21, a reset transistor RST, an amplification transistor AMP, a selection transistor SEL, and the like that constitute a read circuit 124 are formed.

[0181] The image sensor 101 of the second embodiment has the above-described configuration.

[0182] In the conventional configuration in which FD boost wiring is provided, it is necessary to lay the FD boost wiring and wiring connecting the power supply and the FD boost wiring, which causes a problem of restricting the wiring layout of the CMOS image sensor. However, in the image sensor 101 of the second embodiment described above, the FD boost regions 60 and 15N are formed in the semiconductor region, and the ON voltage V of the transfer gate TG is ＯＮ By using this to boost the voltage of the floating diffusion FD, the wiring layout is less constrained.

[0183] In the image sensor 101 of the second embodiment, the periphery of the FD connection region 50, 15N is connected to the ON voltage V ＯＮ or GND voltage V ＧＮＤ Therefore, the image sensor 101 of the second embodiment is less susceptible to the influence of signal crosstalk from the surrounding FD sharing units 150.

[0184] It should be noted that the FD boost region 60 of the technology according to the present disclosure does not necessarily have to be disposed so as to surround the FD connection region 50. The FD boost region 60 only needs to be disposed in a manner that allows it to boost the FD connection region 50 and the floating diffusion FD. Therefore, the FD boost region 60 only needs to be disposed adjacent to the FD connection region 50.

[0185] However, from the viewpoint of reducing the influence of signal crosstalk from the surrounding FD sharing units 150 described above, it is preferable that the FD boosting region 60 be arranged so as to surround the FD connection region 50 in a front view.

[0186] As described above, in the technology according to the present disclosure, the semiconductor regions that form the FD connection region 50 and the FD boost region 60 can also be polysilicon regions. When the FD connection region 50 and the FD boost region 60 are formed from single crystal silicon regions as in the first embodiment, three semiconductor substrates are required, whereas when the FD connection region 50 and the FD boost region 60 are formed from polysilicon regions, only two semiconductor substrates are required. Therefore, using polysilicon regions for the semiconductor regions that form the FD connection region 50 and the FD boost region 60 has the advantage of saving semiconductor substrates.

[0187] (Method for Manufacturing the Image Sensor 101 of the Second Embodiment) Next, an example of a method for manufacturing the image sensor 101 of the second embodiment will be described.

[0188] 19A to 19G are longitudinal sectional views showing an example of a method for manufacturing the image sensor 101 according to the second embodiment.

[0189] 19A , in manufacturing the image sensor 101 of the second embodiment, first, a photodiode PD, a floating diffusion FD, a transfer gate TG, a high-concentration P-type region 10 a, etc. are formed on a first semiconductor substrate 21. The high-concentration P-type region 10 a is a region electrically connected to ground GND.

[0190] The first semiconductor substrate 21 is, for example, a single-crystal silicon substrate. The photodiode PD is formed, for example, by providing a P-type well in the N-type semiconductor substrate 21 and providing a low-concentration N-type region in the P-type well. The floating diffusion FD is, for example, configured as a high-concentration N-type region provided in the P-type well.

[0191] Next, as shown in FIG. 9B, an interlayer insulating layer 12, a polysilicon wiring layer 15 constituting the FD connection region 50, the FD boost region 60, etc., and vertical wiring 46 made of polysilicon are formed on the first semiconductor substrate 11.

[0192] The interlayer insulating layer 12 is made of SiO ２ It is formed by stacking insulating materials such as silicon dioxide.

[0193] The polysilicon wiring layer 15 has an N-type polysilicon region 15N, a P-type polysilicon region 15P, and an intrinsic polysilicon region (resistance region) 15I. The N-type polysilicon region 15N is, for example, a region made of polysilicon doped with phosphorus. The P-type polysilicon region 15P is, for example, a region made of polysilicon doped with boron. The intrinsic polysilicon region (resistance region) 15I is, for example, a region made of polysilicon that is not doped with impurities. However, the intrinsic polysilicon region (resistance region) 15I only needs to have a certain resistance, and may be doped with a small amount of impurities.

[0194] The vertical wiring 46 connected to the N-type polysilicon region 15N is made of N-type polysilicon, and the vertical wiring 41 connected to the P-type polysilicon region 15P is made of P-type polysilicon.

[0195] In this manner, the first layer 10 of the imaging element 101 is formed.

[0196] 19C, a second semiconductor substrate 21 is laminated on the interlayer insulating layer 12 of the first layer 10. The second semiconductor substrate 21 is, for example, a single crystal silicon substrate.

[0197] Next, as shown in 19D, the upper surface side of the second semiconductor substrate 21 stacked on the interlayer insulating layer 12 of the first layer 10 is thinned. The second semiconductor substrate 21 can be thinned by, for example, CMP.

[0198] Next, as shown in FIG. 19E, an N-type semiconductor region 21N and a P-type semiconductor region 21P that form the first wiring path 61 are formed near the upper surface of the second semiconductor substrate 21.

[0199] Furthermore, through holes for the vertical wirings 47 and 48 to be formed later are provided in the second semiconductor substrate 21, and an in-through-hole insulating layer 24 is formed in the through holes. The in-through-hole insulating layer 24 is made of an insulating material such as SiN (silicon nitride) or SiO2 (silicon oxide).

[0200] Furthermore, on the second semiconductor substrate 21, the reset transistor RST, the amplification transistor AMP, the selection transistor SEL, and the like that constitute the readout circuit 124 are formed.

[0201] 19F, an interlayer insulating layer 22 is formed on the second semiconductor substrate 21. Then, vertical wirings 47 and 48 are formed. The interlayer insulating layer 22 is made of SiO ２ The vertical wirings 47 and 48 are formed by laminating insulating materials such as silicon oxide, etc. The vertical wirings 47 and 48 are made of a metal material such as copper or aluminum, for example.

[0202] 19G, a wiring layer 29 is formed on the interlayer insulating layer 22. In this way, the second layer 20 of the imaging element 101 is formed.

[0203] In this manner, the image sensor 101 of the second embodiment can be manufactured.

[0204] To summarize the above, the image sensor 101 of the second embodiment includes a photodiode PD (photoelectric conversion unit), a plurality of floating diffusions FD, a plurality of transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, and gate signal lines (V ＧＴThe FD boost region 60 includes a plurality of first wiring paths 61 that electrically connect the FD boost region 60 to the FD boost region 60, and a second wiring path 62 that electrically connects the FD boost region 60 to the ground GND via a resistor. The first wiring paths 61 include a PN junction that is formed by a P-type semiconductor region and an N-type semiconductor region.

[0205] In the image sensor 101 of the second embodiment, the FD connection region 50 and the FD boost region 60 are formed of N-type polysilicon regions 15N. The image sensor 101 has a first semiconductor substrate 21, an interlayer insulating layer 12, and a second semiconductor substrate 22. The photodiode PD (photoelectric conversion unit) and floating diffusion PD are formed in the first semiconductor substrate 21. The N-type polysilicon regions 15N of the FD connection region 50 and the FD boost region 60 are formed in the interlayer insulating layer 12. The P-type semiconductor region 21P and the N-type semiconductor region 21N of the PN junction are formed in the second semiconductor substrate 21.

[0206] Such an image pickup device 101 reduces the burden on the wiring layout.

[0207] Furthermore, in the image sensor 101 of the second embodiment, the FD boosting region 60 is disposed to surround the FD connection region 50 in a front view. In this image sensor 101, the influence of crosstalk is suppressed.

[0208] Furthermore, in the image sensor 101 of the second embodiment, at least one of the plurality of transistors that make up the readout circuit 124 is formed on the second semiconductor substrate 21. In this type of image sensor 101, the use of the semiconductor substrate is reduced.

[0209] 3. Third Embodiment Next, an image sensor according to a third embodiment will be described.

[0210] FIG. 20 is a planar layout diagram showing the configuration of an image sensor 101 according to the third embodiment.

[0211] The image sensor 101 of the third embodiment basically has the same configuration as that of the first embodiment. However, while the FD boost regions 60 and 21N of the image sensor 101 of the first embodiment are electrically connected to ground GND via resistors, the FD boost regions 60 and 21N of the image sensor 101 of the third embodiment are not electrically connected to ground GND, but are instead electrically connected to an FD boost power supply 70.

[0212] The FD boost power supply 70 supplies the ON voltage V ＯＮ and GND voltage V ＧＮＤ When the transfer gate TG is ON, the FD boost power supply 70 supplies the ON voltage V of the transfer gate TG to the FD boost regions 60 and 21N. ＯＮ When the transfer gate TG is OFF, the FD boosting region 60, 21N is supplied with the GND voltage V ＧＮＤ supply.

[0213] In the image sensor 101 of the third embodiment having such a configuration, even when the transfer gate TG is ON, no current flows through the FD boost regions 60 and 21N. Therefore, the image sensor 101 of the third embodiment has reduced power consumption.

[0214] It is possible to boost the floating diffusion FD by connecting only the FD boost power supply 70 without connecting the FD boost region 60, 21N to the transfer gate TG, but by connecting the transfer gate TG and the FD boost region 60, 21N via a PN junction, the RC delay of driving is reduced.

[0215] In the image sensor 101 of the third embodiment, the periphery of the FD connection region 50, 21N is connected to the ON voltage V ＯＮ or GND voltage V ＧＮＤ Since the FD boosting region 60 is surrounded by the FD boosting region 21N to which the voltage is applied, it is less susceptible to the influence of signal crosstalk from the surrounding FD sharing unit 150.

[0216] In addition, in the image sensor 101 of the third embodiment, the FD boost regions 60, 21N between the FD sharing units 150 adjacent in one direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 21N of the FD supply units located at the outermost periphery of the pixel array section 111.

[0217] That is, the FD shared units 150 are arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two adjacent FD shared units 150 in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD shared unit 150 located on the outermost side among the multiple FD shared units 150 arranged side by side in that direction.

[0218] In the example shown in Figure 20, the FD boost regions 60, 21N of FD shared units 150 adjacent in the left-right direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 21N of the FD shared unit 150 located at the outermost periphery of the pixel array section 111 on the right side.

[0219] This configuration reduces the pressure on the wiring layout.

[0220] 20, the FD boost power supply 70 is directly connected to the FD boost regions 60 and 21N. However, the FD boost power supply 70 may be connected to the FD boost regions 60 and 21N via, for example, the wiring layer 39 and the vertical wiring 43.

[0221] To summarize the above, the image sensor 101 of the third embodiment includes a plurality of photodiodes PD (photoelectric conversion units), a plurality of floating diffusions FD, a plurality of transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, a plurality of first wiring paths 61 having PN junctions formed of a P-type semiconductor region and an N-type semiconductor region, and an FD boost power supply 70. When any of the plurality of transfer gates TG is ON, the FD boost power supply 70 outputs an ON voltage V ＯＮ is supplied to the FD boost region 60, and when all of the multiple transfer gates TG are OFF, the ground voltage V ＧＮＤto the FD boost region 60. The FD boost region 60 may be disposed so as to surround the FD connection region 50 in a front view.

[0222] Such an image pickup device 101 reduces power consumption and RC delay in driving.

[0223] Furthermore, in the image sensor 101 of the third embodiment, the FD boosting region 60 may be disposed to surround the FD connection region 50 in a front view. In such an image sensor 101, the influence of crosstalk is suppressed.

[0224] Furthermore, the image sensor 101 of the third embodiment has a plurality of FD shared units 150 arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two FD shared units 150 adjacent to each other in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD shared unit 150 located on the outermost side of the plurality of FD shared units 150 arranged side by side in that direction. In this image sensor 101, the wiring layout is minimized.

[0225] 4. Fourth Embodiment Next, an image sensor according to a fourth embodiment will be described.

[0226] FIG. 21 is a planar layout diagram showing the configuration of an image sensor 101 according to the fourth embodiment.

[0227] The image sensor 101 of the fourth embodiment basically has the same configuration as that of the image sensor 101 of the second embodiment, except that, whereas the FD boost regions 60 and 15N of the image sensor 101 of the second embodiment are electrically connected to ground GND via resistors, the image sensor 101 of the fourth embodiment is not electrically connected to ground GND, but is instead electrically connected to the FD boost power supply 70.

[0228] The configuration of the FD boost power supply 70 is the same as that of the FD boost power supply 70 of the third embodiment. ＯＮ and GND voltage V ＧＮＤWhen any of the transfer gates TG is ON, the FD boost power supply 70 supplies the ON voltage V of the transfer gate TG to the FD boost regions 60 and 15N. ＯＮ When all the transfer gates TG are OFF, the FD boosting regions 60 and 15N are supplied with the GND voltage V ＧＮＤ supply.

[0229] In the image sensor 101 of the fourth embodiment having such a configuration, even when the transfer gate TG is ON, no current flows through the FD boost regions 60 and 15N. Therefore, the image sensor 101 of the fourth embodiment has reduced power consumption.

[0230] It is possible to boost the floating diffusion FD by connecting only the FD boost power supply 70 without connecting the FD boost region 60, 15N to the transfer gate TG, but by connecting the transfer gate TG and the FD boost region 60, 15N via a PN junction, the RC delay of driving is reduced.

[0231] In the image sensor 101 of the fourth embodiment, the periphery of the FD connection region 50, 15N is connected to the ON voltage V ＯＮ or GND voltage V ＧＮＤ Since the FD boosting region 60 is surrounded by the FD boosting region 15N to which the voltage is applied, it is less susceptible to the influence of signal crosstalk from the surrounding FD sharing unit 150.

[0232] In addition, in the image sensor 101 of the fourth embodiment, the FD boost regions 60, 15N between the FD sharing units 150 adjacent in one direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 15N of the FD supply units located at the outermost periphery of the pixel array section 111.

[0233] That is, the FD shared units 150 are arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two adjacent FD shared units 150 in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD shared unit 150 located on the outermost side among the multiple FD shared units 150 arranged side by side in that direction.

[0234] In the example shown in Figure 21, the FD boost regions 60, 15N of FD shared units 150 adjacent in the left-right direction are connected to each other, and the FD boost power supply 70 is connected to the FD boost regions 60, 15N of the FD shared unit 150 located at the outermost periphery of the pixel array section 111 on the right side.

[0235] This configuration reduces the pressure on the wiring layout.

[0236] 21, the FD boost power supply 70 is directly connected to the FD boost regions 60 and 15N. However, the FD boost power supply 70 may be connected to the FD boost regions 60 and 15N via, for example, the wiring layer 29 and the vertical wiring 47.

[0237] To summarize the above, the image sensor 101 of the fourth embodiment includes a plurality of photodiodes PD (photoelectric conversion units), a plurality of floating diffusions FD, a plurality of transfer gates TG, an FD connection region 50 formed of an N-type semiconductor region, an FD boost region 60 formed of an N-type semiconductor region, a plurality of first wiring paths 61 having PN junctions formed of a P-type semiconductor region and an N-type semiconductor region, and an FD boost power supply 70. When any of the plurality of transfer gates TG is ON, the FD boost power supply 70 generates an ON voltage V ＯＮ is supplied to the FD boost region 60, and when all of the multiple transfer gates TG are OFF, the ground voltage V ＧＮＤ is supplied to the FD boost region 60.

[0238] Such an image pickup device 101 reduces power consumption and RC delay in driving.

[0239] Furthermore, in the image sensor 101 of the fourth embodiment, the FD boosting region 60 may be disposed to surround the FD connection region 50 in a front view. In such an image sensor 101, the influence of crosstalk is suppressed.

[0240] Furthermore, the image sensor 101 of the fourth embodiment has a plurality of FD shared units 150 arranged side by side in one direction when viewed from the front, and the FD boost regions 60 of two FD shared units 150 adjacent to each other in that direction are connected to each other. The FD boost power supply 70 is connected to the FD boost region 60 of the FD shared unit 150 located on the outermost side of the plurality of FD shared units 150 arranged side by side in that direction. In this image sensor 101, the wiring layout is minimized.

[0241] 5. Fifth Embodiment Next, an image sensor 101 according to a fifth embodiment will be described.

[0242] While the image sensor 101 of the first embodiment described above is a rolling shutter type image sensor, the image sensor 101 of the fifth embodiment is a global shutter type image sensor. The image sensor 101 of the fifth embodiment has the same configuration as that of the first embodiment, except for the configuration described below.

[0243] Fig. 22 is a diagram showing the circuit configuration of a pixel 121 of the image sensor 101 of the fifth embodiment. Fig. 23 is a planar layout diagram of a part of a pixel region in the pixel array unit 111 of the image sensor 101 of the fifth embodiment. Fig. 23 shows a region of 2 × 2, or four pixels.

[0244] In the image sensor 101 of the fifth embodiment, as in the first embodiment, four pixels 121 share one readout circuit 124. Fig. 22 shows only one pixel 121. The configuration of the readout circuit 124 is the same as that of the readout circuit 124 of the first embodiment shown in Fig. 2.

[0245] Each pixel 121 includes a photodiode PD, a charge storage unit MEM, three transfer transistors TRY, TRX, and TRG, a floating diffusion FD, and a discharge transistor OFG. In the illustrated example, two pixels 121 share one floating diffusion FD.

[0246] Similarly to the first embodiment, the read circuit 124 includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL.

[0247] The photodiode PD generates electric charges according to the amount of light received through photoelectric conversion. The anode of the photodiode PD is connected to ground (GND), and the cathode of the photodiode PD is connected to the source of the drain transistor OFG and the drain of the transfer transistor TRY.

[0248] The charge holding unit MEM is an area that temporarily holds the charges generated and accumulated in the photodiode PD in order to realize a global shutter function. The charge holding unit MEM holds the charges transferred from the photodiode PD.

[0249] The transfer transistors TRY and TRX are arranged on the charge holding unit MEM, in that order from the photodiode PD side. The gates of the transfer transistors TRY and TRX are connected to a pixel drive line 122. The transfer transistors TRY and TRX control the potential of the charge holding unit MEM by a control signal applied to the gate electrode, and transfer the charge photoelectrically converted by the photodiode PD.

[0250] For example, when the transfer transistors TRY and TRX are turned on, the potential of the charge holding unit MEM becomes deeper, and when the transfer transistors TRY and TRX are turned off, the potential of the charge holding unit MEM becomes shallower. Then, for example, when the transfer transistors TRY and TRX are turned on, the charge stored in the photodiode PD is transferred to the charge holding unit MEM via the transfer transistors TRY and TRX.

[0251] The transfer transistor TRG is disposed between the transfer transistor TRX and the floating diffusion FD. The source of the transfer transistor TRG is connected to the drain of the transfer transistor TRX, and the drain of the transfer transistor TRG is connected to the floating diffusion FD. The gate of the transfer transistor TRG is connected to a pixel drive line 122. The transfer transistor TRG transfers the charges held in the charge holding unit MEM to the floating diffusion FD in response to a control signal applied to the gate electrode.

[0252] For example, when the transfer transistor TRX is turned off and the transfer transistor TRG is turned on, the charge held in the charge holding unit MEM is transferred to the floating diffusion FD.

[0253] The floating diffusion FD is a floating diffusion region that temporarily holds the charge transferred from the photodiode PD via the transfer transistor TRG, and is connected to the drain of the transfer transistor TRG, the source of the reset transistor RST, and the gate of the amplification transistor AMP.

[0254] As described above, in the illustrated example, two pixels 121 share one floating diffusion FD. Furthermore, the two floating diffusions FD, each shared by two pixels 121, are electrically connected by wiring. Therefore, it can be said that these two floating diffusions FD essentially constitute one floating diffusion. In other words, it can be said that four pixels 121 essentially share one floating diffusion consisting of two floating diffusions FD and wiring.

[0255] The drain transistor OFG initializes (resets) the photodiode PD in response to a control signal applied to its gate electrode. The drain of the drain transistor OFG is connected to the power supply line VDD. The source of the drain transistor OFG is connected to the photodiode PD and the source of the transfer transistor TRY.

[0256] For example, when the drain transistor OFG is turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. That is, the photodiode PD is initialized. Furthermore, the drain transistor OFG forms an overflow path between the photodiode PD and the power supply line VDD, for example, and drains the charge overflowing from the photodiode PD to the power supply line VDD.

[0257] The reset transistor RST initializes (resets) each region from the charge holding unit MEM to the floating diffusion FD in response to a control signal applied to the gate electrode. The drain of the reset transistor RST is connected to the power supply line VDD. The source of the reset transistor RST is connected to the floating diffusion FD.

[0258] For example, when the transfer transistor TRG and the reset transistor RST are turned on, the potentials of the charge holding unit MEM and the floating diffusion FD are reset to the potential level of the power supply line VDD. That is, by turning on the reset transistor RST, the charge holding unit MEM and the floating diffusion FD are initialized.

[0259] The amplifier transistor AMP has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as the input of a source follower circuit that reads out the charge obtained by photoelectric conversion in the photodiode PD. That is, the amplifier transistor AMP has a source connected to the vertical signal line VSL (123) via the selection transistor SEL, and thereby forms a source follower circuit together with a constant current source connected to one end of the vertical signal line VSL (123).

[0260] The selection transistor SEL has a source connected to the vertical signal line VSL (123) and a drain connected to the source of the amplification transistor AMP. A control signal is supplied to the gate electrode of the selection transistor SEL as a selection signal. When the control signal is turned on, the selection transistor SEL becomes conductive, and the pixel 121 connected to the selection transistor SEL becomes selected. When the pixel 121 becomes selected, the pixel signal output from the amplification transistor AMP is read out to the column signal processing unit 114 via the vertical signal line VSL (123).

[0261] The planar layout of each transistor in the pixel 121 is not limited to that shown in Fig. 23. If the arrangement of each transistor in the pixel 121 changes, the arrangement locations of the photodiode PD and the charge holding unit MEM arranged below them also change.

[0262] Except for the configuration described above, the specific configuration of the image sensor 101 of the fifth embodiment is basically the same as that of the first embodiment.

[0263] However, the "transfer transistor TRG" in the fifth embodiment corresponds to the "transfer transistor TR" in the first embodiment, and the "gate electrode of the transfer transistor TRG" in the fifth embodiment corresponds to the "transfer gate TG" in the first embodiment.

[0264] In this way, the technology according to the present disclosure can be applied not only to rolling shutter type image sensors but also to global shutter type image sensors.

[0265] 6. Application Example to Electronic Devices FIG. 24 is a block diagram showing an example configuration of a camera 2000 as an electronic device to which the technology according to the present disclosure is applied.

[0266] The camera 2000 includes an optical unit 2001 including a lens group and the like, an image sensor (image sensor device) 2002 to which the image sensor 101 and the like are applied, and a DSP (Digital Signal Processor) circuit 2003, which is a camera signal processing circuit. The camera 2000 also includes a frame memory 2004, a display unit 2005, a recording unit 2006, an operation unit 2007, and a power supply unit 2008. The DSP circuit 2003, the frame memory 2004, the display unit 2005, the recording unit 2006, the operation unit 2007, and the power supply unit 2008 are connected to one another via a bus line 2009.

[0267] The optical unit 2001 takes in incident light (image light) from a subject and forms an image on the imaging surface of the image sensor 2002. The image sensor 2002 converts the amount of incident light formed on the imaging surface by the optical unit 2001 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal.

[0268] The display unit 2005 is formed of a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays moving images or still images captured by the imaging element 2002. The recording unit 2006 records the moving images or still images captured by the imaging element 2002 on a recording medium such as a hard disk or semiconductor memory.

[0269] An operation unit 2007, under the operation of a user, issues operation commands for various functions of the camera 2000. A power supply unit 2008 appropriately supplies various types of power to the DSP circuit 2003, frame memory 2004, display unit 2005, recording unit 2006, and operation unit 2007 as operating power sources.

[0270] As described above, by using the image sensor 101 or the like as the image sensor 2002, it is possible to expect to obtain a good image.

[0271] 7. Application Examples to Mobile Bodies The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0272] FIG. 25 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0273] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 25, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0274] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0275] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0276] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0277] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0278] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0279] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0280] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0281] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0282] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 25, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0283] FIG. 26 is a diagram showing an example of the installation position of the imaging unit 12031.

[0284] In FIG. 26, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0285] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0286] 26 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0287] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0288] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0289] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0290] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0291] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging element 101 shown in FIG. 1 and the like can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, excellent operation of the vehicle control system can be expected.

[0292] 8. Summary Although one example of an embodiment of the present disclosure has been described above, the present disclosure can be embodied in various other forms. For example, various modifications, substitutions, omissions, or combinations thereof are possible without departing from the spirit of the present disclosure. Such modifications, substitutions, omissions, etc. are also included within the scope of the present disclosure, as well as within the scope of the inventions described in the claims and their equivalents.

[0293] Furthermore, the effects of the present disclosure described in this specification are merely examples, and other effects may also be present.

[0294] The present disclosure may also have the following configurations: [Item 1] An image sensor comprising: a plurality of photoelectric conversion units that generate charges according to the amount of received light through photoelectric conversion; a plurality of floating diffusions that hold charges transferred from the photoelectric conversion units; a plurality of transfer gates that transfer the charges generated in the photoelectric conversion units to the floating diffusions; an FD connection region that is a wiring region that connects the plurality of floating diffusions; an FD boost region that is a wiring region for boosting the FD connection region; a plurality of first wiring paths that electrically connect gate signal lines of the plurality of transfer gates to the FD boost region; and a second wiring path that electrically connects the FD boost region to ground via a resistor, wherein the FD connection region and the FD boost region are formed by N-type semiconductor regions, and the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region. [Item 2] The image sensor according to item 1, wherein the FD boost region is arranged to surround the FD connection region in a front view. [Item 3] The image sensor according to item 1 or 2, comprising: a first semiconductor substrate; an interlayer insulating layer stacked on an upper surface of the first semiconductor substrate; and a second semiconductor substrate stacked on an upper surface of the interlayer insulating layer, wherein the photoelectric conversion unit and the floating diffusion are formed in the first semiconductor substrate, and the N-type semiconductor regions of the FD connection region and the FD boost region and the P-type and N-type semiconductor regions of the PN junction are formed in the second semiconductor substrate. [Item 4] The image sensor according to any one of items 1 to 3, wherein the FD connection region and the FD boost region are formed of N-type single crystal silicon regions, and the PN junction of the first wiring path is formed of a P-type single crystal silicon region and an N-type single crystal silicon region. [Item 5] The image sensor according to any one of items 1 to 3, wherein the FD connection region and the FD boost region are formed of N-type polysilicon regions.[Item 6] The image sensor according to Item 5, comprising: a first semiconductor substrate, an interlayer insulating layer stacked on an upper surface side of the first semiconductor substrate, and a second semiconductor substrate stacked on an upper surface side of the interlayer insulating layer, wherein the photoelectric conversion unit and the floating diffusion are formed in the first semiconductor substrate, N-type polysilicon regions of the FD connection region and the FD boost region are formed in the interlayer insulating layer, and P-type semiconductor region and N-type semiconductor region of the PN junction are formed in the second semiconductor substrate. [Item 7] The image sensor according to Item 6, wherein at least one of a plurality of transistors constituting a readout circuit is formed on the second semiconductor substrate. [Item 8] A semiconductor device comprising: a plurality of photoelectric conversion units that generate charges according to the amount of received light by photoelectric conversion; a plurality of floating diffusions that hold charges transferred from the photoelectric conversion units; a plurality of transfer gates that transfer the charges generated in the photoelectric conversion units to the floating diffusions; an FD connection region that is a wiring region that connects the plurality of floating diffusions; an FD boost region that is a wiring region for boosting the FD connection region; a plurality of first wiring paths that electrically connect gate signal lines of the plurality of transfer gates to the FD boost region; and an FD boost power supply that is a power supply electrically connected to the FD boost region and that can switch between supplying a ground voltage and an ON voltage of the transfer gate, wherein the FD connection region and the FD boost region are formed by N-type semiconductor regions, and the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region, an FD boost power supply configured to supply the ON voltage to the FD boost region when any of the plurality of transfer gates is ON, and to supply the ground voltage to the FD boost region when all of the plurality of transfer gates are OFF; [Item 9] The image sensor according to Item 8, wherein the FD boost region is disposed so as to surround the FD connection region in a front view;[Item 10] The image sensor according to item 8 or 9, comprising a plurality of FD shared units which are structural units each having the plurality of photoelectric conversion units, the plurality of floating diffusions, the plurality of transfer gates, the FD connection region, the FD boost region, and the plurality of first wiring paths, the plurality of FD shared units being arranged side by side in one direction when viewed from the front, the FD boost regions of two of the FD shared units adjacent to each other in the one direction being connected to each other, and the FD boost power supply being connected to the FD boost region of the FD shared unit located outermost among the plurality of FD shared units arranged side by side in the one direction. [Item 11] An electronic device including the image sensor according to any one of items 1 to 10.

[0295] 101 Image sensor 111 Pixel array section 112 Vertical drive section 113 Ramp wave module 114 Column signal processing section 115 Clock module 116 Data storage section 117 Horizontal drive section 118 System control section 119 Signal processing section 121 Pixel 122 Pixel drive line 123 Vertical signal line 124 Readout circuit 150 FD sharing unit 10 First layer 11 First semiconductor substrate 11c Highly doped P-type region 12 Interlayer insulating layer 15 Polysilicon wiring layer 15N N-type polysilicon region 15P P-type polysilicon region 15I Intrinsic polysilicon region (resistance region) 20 Second layer 21 Second semiconductor substrate 21N N-type semiconductor region 21P P-type semiconductor region 21I Intrinsic semiconductor region (resistance region) 22, 23 Interlayer insulating layer 24 Insulating layer in through hole 29 Wiring layer 291, 292 Connection wiring 30 Third layer 31 Third semiconductor substrate 32 Interlayer insulating layer 34 Insulating layer in through hole 39 Wiring layer 41, 42, 43, 44, 45, 46, 47, 48 Vertical wiring 41a, 42a Pad electrode 50 FD connection region 60 FD boosting region 61 First wiring path 62 Second wiring path 70 FD boosting power supply PD Photodiode TR Transfer transistor TG Transfer gate FD Floating diffusion RST Reset transistor AMP Amplifying transistor SEL Select transistor VDD Power line VSL Vertical signal line

Claims

1. An image sensor comprising: a plurality of photoelectric conversion units that generate electric charges according to the amount of received light through photoelectric conversion; a plurality of floating diffusions that hold electric charges transferred from the photoelectric conversion units; a plurality of transfer gates that transfer electric charges generated in the photoelectric conversion units to the floating diffusions; an FD connection region that is a wiring region that connects the plurality of floating diffusions; an FD boost region that is a wiring region for boosting the FD connection region; a plurality of first wiring paths that electrically connect gate signal lines of the plurality of transfer gates to the FD boost region; and a second wiring path that electrically connects the FD boost region to ground via a resistor, wherein the FD connection region and the FD boost region are formed by N-type semiconductor regions, and the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region.

2. An imaging device according to claim 1, wherein the FD boosting region is arranged to surround the FD connection region when viewed from the front.

3. An imaging element according to claim 1, comprising: a first semiconductor substrate; an interlayer insulating layer laminated on the upper surface side of said first semiconductor substrate; and a second semiconductor substrate laminated on the upper surface side of said interlayer insulating layer, wherein said photoelectric conversion section and said floating diffusion are formed within said first semiconductor substrate; and said N-type semiconductor regions of said FD connection region and said FD boost region, and said P-type semiconductor region and N-type semiconductor region of said PN junction are formed within said second semiconductor substrate.

4. An imaging element according to claim 1, wherein the FD connection region and the FD boosting region are made of N-type single crystal silicon regions, and the PN junction of the first wiring path is made of a P-type single crystal silicon region and an N-type single crystal silicon region.

5. An imaging device according to claim 1, wherein the FD connection region and the FD boosting region are formed of N-type polysilicon regions.

6. An imaging device according to claim 5, comprising: a first semiconductor substrate; an interlayer insulating layer laminated on the upper surface side of said first semiconductor substrate; and a second semiconductor substrate laminated on the upper surface side of said interlayer insulating layer, wherein said photoelectric conversion section and said floating diffusion are formed within said first semiconductor substrate, said FD connection region and said N-type polysilicon region of said FD boost region are formed within said interlayer insulating layer, and said P-type semiconductor region and N-type semiconductor region of said PN junction are formed within said second semiconductor substrate.

7. An image pickup device according to claim 6, wherein at least one of a plurality of transistors constituting a readout circuit is formed on said second semiconductor substrate.

8. A semiconductor device comprising: a plurality of photoelectric conversion units that generate charges according to the amount of received light by photoelectric conversion; a plurality of floating diffusions that hold charges transferred from the photoelectric conversion units; a plurality of transfer gates that transfer the charges generated in the photoelectric conversion units to the floating diffusions; an FD connection region that is a wiring region that connects the plurality of floating diffusions; an FD boost region that is a wiring region for boosting the FD connection region; a plurality of first wiring paths that electrically connect gate signal lines of the plurality of transfer gates to the FD boost region; and an FD boost power supply that is a power supply electrically connected to the FD boost region and that can switch between supplying a ground voltage and an ON voltage of the transfer gate, wherein the FD connection region and the FD boost region are formed by N-type semiconductor regions, and the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region, the FD boost power supply supplies the ON voltage to the FD boost region when any of the plurality of transfer gates is ON, and supplies the ground voltage to the FD boost region when all of the plurality of transfer gates are OFF.

9. An imaging device according to claim 8, wherein the FD boosting region is disposed so as to surround the FD connection region when viewed from the front.

10. An image sensor according to claim 8, comprising a plurality of FD shared units, which are structural units each having the plurality of photoelectric conversion sections, the plurality of floating diffusions, the plurality of transfer gates, the FD connection region, the FD boost region, and the plurality of first wiring paths, the plurality of FD shared units being arranged side by side in one direction when viewed from the front, the FD boost regions of two FD shared units adjacent to each other in the one direction being connected to each other, and the FD boost power supply being connected to the FD boost region of the FD shared unit located outermost among the plurality of FD shared units arranged side by side in the one direction.

11. An electronic device having an imaging element, wherein the imaging element has: a plurality of photoelectric conversion units that generate electric charges according to the amount of received light through photoelectric conversion; a plurality of floating diffusions that hold electric charges transferred from the photoelectric conversion units; a plurality of transfer gates that transfer electric charges generated in the photoelectric conversion units to the floating diffusions; an FD connection region that is a wiring region that connects the plurality of floating diffusions; an FD boost region that is a wiring region for boosting the FD connection region; a plurality of first wiring paths that electrically connect gate signal lines of the plurality of transfer gates to the FD boost region; and a second wiring path that electrically connects the FD boost region to ground via a resistor, wherein the FD connection region and the FD boost region are formed by N-type semiconductor regions, and the first wiring path has a PN junction formed by a P-type semiconductor region and an N-type semiconductor region.

Images