Electronic device and memory management method

Abstract

An electronic device according to an embodiment of the present disclosure comprises: a processor; and a memory storing instructions, wherein the instructions, when executed by the processor, enable the electronic device to: when there is a memory allocation request from a process, check whether all specific bits of a pointer are available; when at least some of the specific bits of the pointer are unavailable, check whether a selectable tag is present in a lookup table including indices of tags; when the selectable tag is present, select the tag; on the basis of the selected tag, configure a 3-tuple on the basis of a start address, an end address, and valid information for memory allocation and store the 3-tuple in the lookup table; set an operation bit to a first bit; store the tag and the operation bit in a first area of the pointer; and store the start address in a second area of the pointer to allocate a memory.

Description

Electronic Devices and Memory Management Methods

[0001] The present disclosure relates to an electronic device and a memory management method.

[0002] Memory safety refers to the safe use and management of memory in a computing environment, whether in a programming language or an operating system's memory management. Memory management refers to the task of properly using and freeing memory dynamically allocated by a program, while memory safety aims to protect against various bugs and security vulnerabilities that may arise through this process.

[0003] Due to memory safety bugs, if an array writes data beyond its allocated size, references memory that has already been freed, or continues to occupy unnecessary memory, problems may occur.

[0004] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0005] An electronic device according to one embodiment of the present disclosure may include a processor.

[0006] An electronic device according to one embodiment of the present disclosure may include a memory that stores instructions.

[0007] The instructions of the present disclosure, when executed by the processor, can cause the electronic device to determine whether all specific bits of a pointer are available when a process requests memory allocation.

[0008] The instructions of the present disclosure, when executed by the processor, may cause the electronic device to determine whether a selectable tag is present in a lookup table containing an index to a tag if at least some of the specific bits of the pointer are not available.

[0009] The instructions of the present disclosure, when executed by the processor, can cause the electronic device to select a tag if a selectable tag is present.

[0010] The instructions of the present disclosure, when executed by the processor, may cause the electronic device to construct a 3-tuple based on a start address, an end address, and valid information for memory allocation based on a selected tag and store the 3-tuple in the lookup table.

[0011] The instructions of the present disclosure, when executed by the processor, may cause the electronic device to set an operation bit to a first bit.

[0012] The instructions of the present disclosure, when executed by the processor, may cause the electronic device to allocate memory by storing the tag and the operation bit in a first area of ​​the pointer and storing a start address in a second area of ​​the pointer.

[0013] A memory management method according to one embodiment of the present disclosure may include an operation of checking whether all specific bits of a pointer can be used when a memory allocation request is made by a process.

[0014] A memory management method according to one embodiment of the present disclosure may include an operation of checking whether a selectable tag is present in a lookup table including an index to a tag if at least some of the specific bits of the pointer are unavailable.

[0015] A memory management method according to one embodiment of the present disclosure may include an operation of selecting a tag if there is a selectable tag.

[0016] A memory management method according to one embodiment of the present disclosure may include an operation of constructing a 3-tuple based on a start address, an end address, and valid information for memory allocation based on a selected tag and storing the 3-tuple in the lookup table.

[0017] A memory management method according to one embodiment of the present disclosure may include an operation of setting an operation bit to a first bit; and an operation of allocating memory by storing the tag and the operation bit in a first area of ​​the pointer and storing a start address in a second area of ​​the pointer.

[0018] In connection with the description of the drawings, the same or similar reference numerals may be used for the same or similar components.

[0019] FIG. 1 is a block diagram of an electronic device within a network environment according to various embodiments of the present disclosure.

[0020] FIG. 2 is a drawing showing an electronic device according to one embodiment of the present disclosure.

[0021] FIG. 3 is a diagram illustrating a memory safety violation detection module according to one embodiment of the present disclosure.

[0022] FIG. 4 is a diagram illustrating a memory management method of an electronic device according to one embodiment of the present disclosure.

[0023] FIG. 5 is a diagram illustrating a first memory management method according to one embodiment of the present disclosure.

[0024] FIG. 6 is a diagram illustrating a second memory management method according to one embodiment of the present disclosure.

[0025] FIG. 7 is a drawing specifically illustrating operation 601 of a second memory management method according to one embodiment of the present disclosure.

[0026] An electronic device and a memory management method according to one embodiment of the present disclosure are intended to efficiently and securely detect memory safety bugs based on the number of allocated memories.

[0027] An electronic device and a memory management method according to one embodiment of the present disclosure can improve detection performance and security by detecting memory safety bugs based on the number of allocated memories.

[0028] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings so that those skilled in the art can easily implement the present disclosure. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments described herein. In connection with the description of the drawings, the same or similar reference numerals may be used for identical or similar components. Furthermore, in the drawings and related descriptions, descriptions of well-known functions and configurations may be omitted for clarity and conciseness.

[0029] FIG. 1 is a block diagram of an electronic device (101) within a network environment (100) according to various embodiments.

[0030] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) via a first network (198) (e.g., a short-range wireless communication network), or may communicate with at least one of an electronic device (104) or a server (108) via a second network (199) (e.g., a long-range wireless communication network). In one embodiment, the electronic device (101) may communicate with the electronic device (104) via the server (108). According to one embodiment, the electronic device (101) may include a processor (120), a memory (130), an input module (150), an audio output module (155), a display module (160), an audio module (170), a sensor module (176), an interface (177), a connection terminal (178), a haptic module (179), a camera module (180), a power management module (188), a battery (189), a communication module (190), a subscriber identification module (196), or an antenna module (197). In some embodiments, the electronic device (101) may omit at least one of these components (e.g., the connection terminal (178)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (176), the camera module (180), or the antenna module (197)) may be integrated into one component (e.g., the display module (160)).

[0031] The processor (120) may, for example, execute software (e.g., a program (140)) to control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) and perform various data processing or calculations. According to one embodiment, as at least a part of the data processing or calculations, the processor (120) may store commands or data received from other components (e.g., a sensor module (176) or a communication module (190)) in a volatile memory (132), process the commands or data stored in the volatile memory (132), and store result data in a non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., a central processing unit or processor) or a secondary processor (123) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together therewith. For example, if the electronic device (101) includes a main processor (121) and a secondary processor (123), the secondary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a specified function. The secondary processor (123) may be implemented separately from the main processor (121) or as a part thereof.

[0032] The auxiliary processor (123) may control at least a portion of functions or states associated with at least one component (e.g., a display module (160), a sensor module (176), or a communication module (190)) of the electronic device (101), for example, on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (123) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (180) or a communication module (190)). In one embodiment, the auxiliary processor (123) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (101) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (108)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0033] The memory (130) can store various data used by at least one component (e.g., processor (120) or sensor module (176)) of the electronic device (101). The data can include, for example, software (e.g., program (140)) and input data or output data for commands related thereto. The memory (130) can include volatile memory (132) or non-volatile memory (134).

[0034] The program (140) may be stored as software in the memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0035] The input module (150) can receive commands or data to be used in a component of the electronic device (101) (e.g., a processor (120)) from an external source (e.g., a user) of the electronic device (101). The input module (150) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0036] The audio output module (155) can output audio signals to the outside of the electronic device (101). The audio output module (155) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0037] The display module (160) can visually provide information to an external party (e.g., a user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0038] The audio module (170) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150), output sound through the sound output module (155), or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (101).

[0039] The sensor module (176) can detect the operating status (e.g., power or temperature) of the electronic device (101) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (176) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0040] The interface (177) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (101) with an external electronic device (e.g., the electronic device (102)). In one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0041] The connection terminal (178) may include a connector through which the electronic device (101) may be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0042] The haptic module (179) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (179) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0043] The camera module (180) can capture still images and videos. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0044] The power management module (188) can manage power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0045] A battery (189) may power at least one component of the electronic device (101). In one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0046] The communication module (190) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may operate independently from the processor (120) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (194) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, the corresponding communication module can communicate with an external electronic device (104) via a first network (198) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (199) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can verify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) by using subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (196).

[0047] The wireless communication module (192) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (192) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (192) can support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), an external electronic device (e.g., the electronic device (104)), or a network system (e.g., the second network (199)). According to one embodiment, the wireless communication module (192) can support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0048] The antenna module (197) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (197) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (198) or the second network (199), may be selected from the plurality of antennas, for example, by the communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device via the at least one selected antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (197).

[0049] According to various embodiments, the antenna module (197) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0050] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0051] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) via a server (108) connected to a second network (199). Each of the external electronic devices (102 or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations executed in the electronic device (101) may be executed in one or more of the external electronic devices (102, 104, or 108). For example, when the electronic device (101) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (101) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (101) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (104) or the server (108) may be included in the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0052] FIG. 2 is a drawing showing an electronic device (101) according to one embodiment of the present disclosure.

[0053] In one embodiment, the electronic device (101) may include a first level (210), a second level (220), and a hardware layer (230). The first level (210) and the second level (220) may include levels of access rights to system resources. The second level (220) may have a higher level of access rights to system resources than the first level (210).

[0054] In one embodiment, the first level (210) may include a user framework. The electronic device (101) may execute application code and user space code in the first level (210) or the user framework under the control of the processor (120). The electronic device (101) may have restricted access to system resources in the first level (210) under the control of the processor (120).

[0055] In one embodiment, the second level (220) may include at least one of a kernel, an ARM trustzone operating system (e.g., TEEgris, QTEE Secure Enclave), a virtual machine (e.g., Android virtual framework), or a secure element (e.g., eSE, Apple Secure Enclave).

[0056] In one embodiment, the electronic device (101) may execute the kernel of the operating system at a second level (220) under the control of the processor (120). The electronic device (101) may perform system calls and exception handling at a second level (220) under the control of the processor (120).

[0057] In one embodiment, the first level (210) may include a user process (211), a first memory allocator (212), a first memory safety violation detection module (213), and a first hook function (214).

[0058] In one embodiment, the second level (220) may include a process (221) (e.g., a kernel process), a second memory allocator (222), a second memory safety violation detection module (223), and a second hook function (215).

[0059] In one embodiment, the hardware layer (230) may include instructions for tag setup (231) and a third memory safety violation detection module (233).

[0060] In one embodiment, when a user process (211) requests memory allocation and release, the electronic device (101) may, under the control of the processor (120), request a tag setup and / or release operation to the first memory safety violation detection module (213) through the first memory allocator (212).

[0061] In one embodiment, when a user process (211) requests memory access, a violation regarding memory security can be detected based on the first hook function (214).

[0062] In one embodiment, when a process (221) requests memory allocation and release, the electronic device (101) may, under the control of the processor (120), request a tag setup and / or release operation to the second memory safety violation detection module (223) through the second memory allocator (222).

[0063] In one embodiment, when the process (221) requests memory allocation and release, the electronic device (101) may, under the control of the processor (120), request a tag setup and / or release operation to the third memory safety violation detection module (233) via an instruction (231) for tag setup.

[0064] In one embodiment, when a user process (211) requests memory access, a violation regarding memory security can be detected based on the second hook function (215).

[0065] In one embodiment, when a user process (211) requests memory access, a violation regarding memory safety can be detected based on the third memory safety violation detection module (233).

[0066] In one embodiment, when a memory safety violation is detected from the first memory safety violation detection module (213), the second memory safety violation detection module (223), or the third memory safety violation detection module (233), the electronic device (101) may, under the control of the processor (120), perform an abort / alert (240) operation regarding the memory safety violation.

[0067] FIG. 3 is a diagram illustrating a memory safety violation detection module according to one embodiment of the present disclosure.

[0068] In one embodiment, the memory safety violation detection module may include a first memory safety violation detection module (213), a second memory safety violation detection module (223), or a third memory safety violation detection module (233).

[0069] In one embodiment, the memory safety violation detection module can manage all allocated memory (310) as a 3-tuple. A tuple can include a data type that expresses multiple values ​​as a single, immutable sequence in programming. The memory safety violation detection module can manage the allocated memory (310) as a tuple defined by three types: a start address, an end address, or additional data. The additional data can include, for example, tags, valid information, or various other information.

[0070] In one embodiment, the memory safety violation detection module may include a 3-tuple lookup table (301), a 3-tuple dynamic data structure (303), and / or a header structure (305) including a 3-tuple.

[0071] In one embodiment, the 3-tuple lookup table (301) may include a tag as an index. The 3-tuple lookup table (301) may include, for example, a start address, an end address, or a tag for allocated memory having a specific tag (a) as a 3-tuple. Accordingly, the 3-tuple lookup table (301) may not additionally include tag information. The 3-tuple lookup table (301) may include valid information (valid) for validity verification. For example, if the valid information is 0, it may indicate that the 3-tuple is empty. If the valid information is 1, it may indicate that the 3-tuple is stored.

[0072] In one embodiment, the tag repository may include a 3-tuple lookup table (301).

[0073] In one embodiment, the 3-tuple dynamic data structure (303) may include multiple distributed trees.

[0074] In one embodiment, a 3-tuple dynamic data structure (303) may include a data structure having an address range (e.g., a start address, an end address) as a key and a 3-tuple as a value.

[0075] In one embodiment, the header structure (305) including a 3-tuple may include a structure for storing the 3-tuple in the header. For example, the header structure (305) including a 3-tuple may configure a 3-tuple based on a start address, an end address, and tag information for memory allocation and store the 3-tuple in a header area. The header structure (305) including a 3-tuple may allocate memory by specifying the location of the header area as a base address and specifying a start address that adds a random offset value to the base address.

[0076] For example, when requesting memory access to a specific address, the electronic device (101) may, under the control of the processor (120), search for a 3-tuple for the specific address through the memory safety violation detection module and return a tag value. When requesting memory access to a specific address, the electronic device (101) may, under the control of the processor (120), determine that a memory safety violation has occurred if there is no 3-tuple searched for the specific address through the memory safety violation detection module.

[0077] In one embodiment, the electronic device (101) may, under the control of the processor (120), allocate / deallocate memory based on a 3-tuple lookup table (301), a 3-tuple dynamic data structure (303), and / or a header structure including a 3-tuple, and determine whether there is a memory safety violation when accessing the memory.

[0078] FIG. 4 is a diagram illustrating a memory management method of an electronic device (101) according to one embodiment of the present disclosure.

[0079] In one embodiment, when there is a request to allocate, free, or access memory, the electronic device (101), under the control of the processor (120), may determine, in operation 401, whether all specific bits of a pointer are available for use.

[0080] In one embodiment, the memory (130) may include instructions that, when executed by the processor (120), may cause the electronic device to perform a memory management method.

[0081] In one embodiment, when there is a request to allocate, free, or access memory, instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to determine, in operation 401, whether all specific bits of the pointer are available for use.

[0082] In one embodiment, if at least some of the specific bits of the pointer are unusable, the electronic device (101) may manage allocation, deallocation, or access of memory using the first memory management method (402) under the control of the processor (120). A memory safety violation detection module (e.g., the first memory safety violation detection module (213), the second memory safety violation detection module (223), or the third memory safety violation detection module (233)) may include the first memory management method (402).

[0083] In one embodiment, if at least some of the specific bits of the pointer are unavailable, instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to manage allocation, deallocation, or access of the memory using the first memory management method (402).

[0084] In one embodiment, if all specific bits of the pointer are available, the electronic device (101) can manage allocation, deallocation, or access of memory using the second memory management method (403) under the control of the processor (120). A memory safety violation detection module (e.g., the first memory safety violation detection module (213), the second memory safety violation detection module (223), or the third memory safety violation detection module (233)) may include the second memory management method (403).

[0085] In one embodiment, if all specific bits of the pointer are available, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to manage allocation, release, or access of the memory using the second memory management method (403).

[0086] For example, a specific bit of a pointer may include the upper 16 bits of the pointer. For example, if the electronic device (101) is using any one of the functions of pointer authentication codes (PAC) and / or memory tagging extension (MTE), the electronic device (101) may not be able to use at least some of the specific bits of the pointer.

[0087] FIG. 5 is a diagram illustrating a first memory management method (402) according to one embodiment of the present disclosure.

[0088] In one embodiment, a memory safety violation detection module (e.g., a first memory safety violation detection module (213), a second memory safety violation detection module (223), or a third memory safety violation detection module (233)) may include a first memory management method (402).

[0089] Referring to 501, the electronic device (101) can manage the pointer as a tag area (511, 512) and an address area (513) under the control of the processor (120). The electronic device (101) can define the pointer as a tag area (511, 512) and an address area (513) under the control of the processor (120). The tag area (511, 512) can include the lowest bit of the tag area as an operation bit (512). The tag area can include the remaining bits excluding the middle operation bit (512) as a tag (511).

[0090] In one embodiment, the instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to manage pointers to tag areas (511, 512) and address areas (513). The instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to define pointers to tag areas (511, 512) and address areas (513).

[0091] Referring to 503, the electronic device (101) can manage the pointer as a tag area (531, 532) and an address area (533) under the control of the processor (120). Referring to 503, the electronic device (101) can define the pointer as a tag area (531, 532) and an address area (533) under the control of the processor (120). The tag area (531, 532) can include the lowest bit of the tag area as an operation bit (532). The tag area can include the remaining bits excluding the middle operation bit (532) as a tag (531).

[0092] In one embodiment, the instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to manage pointers to tag areas (531, 532) and address areas (533). The instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to define pointers to tag areas (531, 532) and address areas (533).

[0093] In one embodiment, the electronic device (101), under the control of the processor (120), may set the operation bit (512, 532) to a first bit (e.g., “0”) if there is an index capable of storing a 3-tuple in the 3-tuple lookup table (520).

[0094] In one embodiment, instructions stored in memory (130), when executed by the processor (120), may cause the electronic device (101) to set an operation bit (512, 532) to a first bit (e.g., “0”) if an index capable of storing a 3-tuple exists in the 3-tuple lookup table (520).

[0095] In one embodiment, the electronic device (101), under the control of the processor (120), may set the operation bits (512, 532) to a second bit (e.g., “1”) if there is no index capable of storing a 3-tuple in the 3-tuple lookup table (520) (or if 3-tuple storage is not possible).

[0096] In one embodiment, instructions stored in memory (130), when executed by the processor (120), may cause the electronic device (101) to set the operation bit (512, 532) to a second bit (e.g., “1”) if there is no index capable of storing a 3-tuple (or if 3-tuple storage is not possible).

[0097] In one embodiment, the electronic device (101) can manage allocation, deallocation, or access of memory using a 3-tuple lookup table (520) according to operation bits (512, 532) under the control of the processor (120).

[0098] In one embodiment, instructions stored in memory (130), when executed by the processor (120), may cause the electronic device (101) to manage allocation, deallocation, or access of memory using a 3-tuple lookup table (520) according to operation bits (512, 532).

[0099] In one embodiment, when the operation bit (512, 532) is set to the first bit, the electronic device (101) can manage allocation, deallocation, or access of memory using the 3-tuple lookup table (520) under the control of the processor (120).

[0100] In one embodiment, when the operation bits (512, 532) are set to the first bit, instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to manage allocation, deallocation, or access of memory using the 3-tuple lookup table (520).

[0101] In one embodiment, the electronic device (101) may manage allocation, deallocation, or access of memory using a cache tuple (541) and / or a 3-tuple dynamic data structure (543) according to operation bits (512, 532) under the control of the processor (120).

[0102] In one embodiment, instructions stored in memory (130), when executed by processor (120), may cause electronic device (101) to manage allocation, deallocation, or access of memory using cache tuples (541) and / or 3-tuple dynamic data structures (543) according to operation bits (512, 532).

[0103] In one embodiment, when the operation bits (512, 532) are set to the second bit, the electronic device (101) can manage allocation, deallocation, or access of memory using the cache tuple (541) and / or the 3-tuple dynamic data structure (543) under the control of the processor (120).

[0104] In one embodiment, when the operation bits (512, 532) are set to the second bit, instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to manage allocation, deallocation, or access of memory using the cache tuple (541) and / or the 3-tuple dynamic data structure (543).

[0105] In one embodiment, a cache tuple (541) may include a data table. The cache tuple (541) may store 3-tuple information in which the operation bits (512, 532) are set to the second bit within a certain period of time. The cache tuple (541) may store the 3-tuple information as a data table. The size of the data table may be scalable as the parallel scale of the system.

[0106] In one embodiment, the 3-tuple dynamic data structure (543) may include a plurality of distributed trees. The number of distributed trees may include a divisor value of the number of tags. For example, if there are K distributed trees (K is an integer greater than or equal to 1), the electronic device (101) may, under the control of the processor (120), divide the 3-tuples to be managed into K and manage them. The electronic device (101), under the control of the processor (120), may determine one of the plurality of distributed trees based on the tag, and perform operations of adding, searching, and deleting 3-tuples in the corresponding distributed tree.

[0107] Referring to 501, when there is a memory allocation request from a process, the electronic device (101) can, under the control of the processor (120), check whether there is a selectable tag in a lookup table containing an index for the tag. The lookup table may include a 3-tuple lookup table.

[0108] Referring to 501, instructions stored in memory (130), when executed by the processor (120), may cause the electronic device (101) to check whether a selectable tag is present in a lookup table containing an index to the tag.

[0109] Referring to 501, the electronic device (101) can, under the control of the processor (120), select a tag if there is a selectable tag in the lookup table. The tag may be randomly generated in advance.

[0110] Referring to 501, the electronic device (101) may, under the control of the processor (120), construct a 3-tuple based on a start address, an end address, and valid information for memory allocation based on a selected tag and store the construct in a lookup table. The valid information may, for example, be “1” to indicate that the 3-tuple is valid, and “0” to indicate that the 3-tuple is invalid. When constructing a 3-tuple and storing it in a lookup table, the valid information may be set to 1.

[0111] Referring to 501, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to construct a 3-tuple based on the start address, end address, and valid information for memory allocation and store it in a lookup table.

[0112] Referring to 501, the electronic device (101), under the control of the processor (120), can set the operation bit to the first bit (e.g., “0”) when configuring a 3-tuple and storing it in the lookup table.

[0113] Referring to 501, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to configure a 3-tuple and store it in a lookup table, setting the operation bit to the first bit.

[0114] Referring to 501, the electronic device (101) can, under the control of the processor (120), allocate memory by storing a selected tag and an operation bit set to a first bit in a first area of ​​the pointer and storing a start address in a second area of ​​the pointer.

[0115] Referring to 501, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to allocate memory by storing a selected tag and an operation bit set to a first bit in a first area of ​​the pointer and storing a start address in a second area of ​​the pointer.

[0116] Referring to 503, the electronic device (101) can, under the control of the processor (120), re-select a random tag if there is no selectable tag in the lookup table.

[0117] Referring to 503, the instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to re-select a random tag if there is no selectable tag in the lookup table.

[0118] Referring to 503, the electronic device (101), under the control of the processor (120), configures and stores a 3-tuple based on a start address, an end address, and a randomly selected tag for memory allocation, and can store the 3-tuple in a specific tree.

[0119] Referring to 503, the instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to construct and store a 3-tuple based on a start address, an end address, and a randomly selected base for memory allocation based on the selected tag, and to store the 3-tuple in a specific tree.

[0120] For example, if there are K multiple distribution trees (K is an integer greater than or equal to 1), the electronic device (101) can, under the control of the processor (120), store a 3-tuple in the remaining R-th distribution tree obtained by dividing the tag value by K.

[0121] Referring to 503, the electronic device (101), under the control of the processor (120), may set the operation bit to a second bit (e.g., “1”) when a 3-tuple is stored in a specific tree.

[0122] Referring to 503, instructions stored in memory (130), when executed by the processor (120), may cause the electronic device (101) to set the operation bit to a second bit (e.g., “1”) when storing a 3-tuple in a specific tree.

[0123] Referring to 503, the electronic device (101), under the control of the processor (120), may allocate memory by setting the operation bit to the second bit (e.g., “1”), storing the tag and the operation bit in the first area of ​​the pointer, and storing the start address in the second area of ​​the pointer when a 3-tuple is stored in a specific tree.

[0124] Referring to 503, the instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to allocate memory by storing a 3-tuple in a specific tree, setting the operation bit to a second bit (e.g., “1”), storing the tag and operation bit in a first area of ​​the pointer, and storing the starting address in a second area of ​​the pointer.

[0125] Referring to 501, the electronic device (101), under the control of the processor (120), can check the operation bit of a pointer when a process or pointer attempts to access a specific memory address.

[0126] Referring to 501, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the operation bit of a pointer when a process or pointer attempts to access a specific memory address.

[0127] Referring to 501, when a process or pointer accesses a specific memory address, the electronic device (101), under the control of the processor (120), can check whether the operation bit corresponds to the start address and end address for memory allocation based on the 3-tuple stored in the lookup table and determine whether there is a memory safety violation, and can determine whether there is a memory safety violation.

[0128] Referring to 501, instructions stored in the memory (130), when executed by the processor (120), cause the electronic device (101) to check whether the start address and end address for memory allocation correspond to the 3-tuple stored in the lookup table and whether valid information is available if the operation bit is set to the first bit (e.g., “0”), and determine whether there is a memory safety violation.

[0129] Referring to 501, when a process or pointer accesses a specific memory address, the electronic device (101), under the control of the processor (120), if the operation bit is set to the first bit (e.g., “0”), can check the tag value included in the pointer and check the 3-tuple corresponding to the tag value in the lookup table. Referring to 501, the 3-tuple can include a start address, an end address, and valid information. The electronic device (101), under the control of the processor (120), can check whether the address of the pointer or processor requesting access corresponds to the start address and the end address included in the 3-tuple.

[0130] Referring to 501, the electronic device (101), under the control of the processor (120), may allow a process or pointer to access a specific memory address if the address of the pointer or processor requesting access corresponds to the start address and end address included in the 3-tuple, and the valid information included in the 3-tuple is valid. The electronic device (101), under the control of the processor (120), may determine a memory security violation if the address of the pointer or processor requesting access does not correspond to the start address and end address included in the 3-tuple, or the valid information included in the 3-tuple is invalid.

[0131] Referring to 501, when a process or pointer accesses a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the tag value contained in the pointer if the operation bit is set to the first bit (e.g., “0”), and to check the 3-tuple corresponding to the tag value in the lookup table.

[0132] Referring to 501, the instructions stored in the memory (130), when executed by the processor (120), may allow the electronic device (101) to allow a process or pointer to access a specific memory address if the address of the pointer or processor that requested access corresponds to the start address and end address included in the 3-tuple, and the valid information included in the 3-tuple is valid. The instructions stored in the memory (130), when executed by the processor (120), may allow the electronic device (101) to determine a memory safety violation if the address of the pointer or processor that requested access does not correspond to the start address and end address included in the 3-tuple, or the valid information included in the 3-tuple is invalid.

[0133] Referring to 503, the electronic device (101), under the control of the processor (120), can check the operation bit of the pointer when the pointer attempts to access a specific memory address.

[0134] Referring to 503, when a process or pointer accesses a specific memory address, the electronic device (101), under the control of the processor (120), can determine whether a memory safety violation has occurred by determining whether the start address and end address for tag and memory allocation correspond to a cache tuple (541) if the operation bit is set to the second bit (e.g., “1”).

[0135] Referring to 503, when a process or pointer accesses a specific memory address, the electronic device (101), under the control of the processor (120), can determine whether a memory safety violation has occurred by determining whether the start address and end address for tag and memory allocation correspond to a 3-tuple dynamic data structure (543) containing a specific tree, if the start address and end address for tag and memory allocation do not correspond to a cache tuple (541).

[0136] Referring to 503, instructions stored in memory (130), when executed by the processor (120), can cause the electronic device (101) to check the operation bit of the pointer.

[0137] Referring to 503, when a process or pointer accesses a specific memory address, instructions stored in the memory (130) can cause the electronic device (101) to determine whether a memory safety violation has occurred by determining whether the start address and end address for tag and memory allocation correspond to a cache tuple (541) when the operation bit is set to the second bit (e.g., “1”) when executed by the processor (120).

[0138] Referring to 503, when a process or pointer accesses a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to determine whether a memory safety violation has occurred by determining whether the start address and end address for tag and memory allocation correspond to a 3-tuple dynamic data structure (543) including a specific tree, if the start address and end address for tag and memory allocation do not correspond to a cache tuple (541).

[0139] Referring to 501, the electronic device (101), under the control of the processor (120), can check the operation bit of the pointer when requesting the release of a specific memory address in a process or pointer.

[0140] Referring to 501, instructions stored in memory (130), when executed by the processor (120), may cause the electronic device (101) to check the operation bit of the pointer when requesting the release of a specific memory address in a process or pointer.

[0141] Referring to 501, when a process or pointer requests the release of a specific memory address, the electronic device (101), under the control of the processor (120), if the identified operation bit is set to the first bit (e.g., “0”), can check whether the start address and end address for memory allocation correspond to the valid information based on the 3-tuple stored in the lookup table and change the valid information to invalid (e.g., “0”) to release the memory usage.

[0142] Referring to 501, when a process or pointer requests the release of a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check whether the start address and end address for memory allocation correspond to the valid information based on the 3-tuple stored in the lookup table if the confirmed operation bit is set to the first bit (e.g., “0”), and change the valid information to invalid (e.g., “0”) to release the memory usage.

[0143] Referring to 503, when a process or pointer requests the release of a specific memory address, the electronic device (101), under the control of the processor (120), can change the 3-tuple stored in the cache tuple (541) to specific data (e.g., (0. 0, 0)) based on the start address, end address, and tag for memory allocation, if the identified operation bit is set to the second bit (e.g., “1”).

[0144] Referring to 503, when a process or pointer requests the release of a specific memory address, instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to change the 3-tuple stored in the cache tuple (541) to specific data (e.g., (0. 0, 0)) based on the start address, end address, and tag for memory allocation, if the identified operation bit is set to the second bit (e.g., “1”).

[0145] Referring to 503, when a process or pointer requests the release of a specific memory address, the electronic device (101), under the control of the processor (120), can search a specific tree corresponding to the tag and delete a 3-tuple stored in the specific tree if the identified operation bit is set to the second bit (e.g., “1”).

[0146] Referring to 503, when a process or pointer requests the release of a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to search a specific tree corresponding to the tag and delete a 3-tuple stored in the specific tree if the identified operation bit is set to the second bit (e.g., “1”).

[0147] FIG. 6 is a diagram illustrating a second memory management method (403) according to one embodiment of the present disclosure.

[0148] FIG. 7 is a drawing specifically illustrating operation 601 of a second memory management method (403) according to one embodiment of the present disclosure.

[0149] In one embodiment, a memory safety violation detection module (e.g., a first memory safety violation detection module (213), a second memory safety violation detection module (223), or a third memory safety violation detection module (233)) may include a second memory management method (403).

[0150] Referring to 601 of FIG. 6 and 601 of FIG. 7, the electronic device (101) can manage pointers to tag areas (611, 6111, 612) and address areas (613) under the control of the processor (120).

[0151] Referring to 601 of FIG. 6 and 601 of FIG. 7, the electronic device (101) can store tag information in the tag areas (611, 6111, 612) of the pointer under the control of the processor (120). The tag information (611, 6111) excluding the operation bit (612) may include first tag information (611) and second tag information (6111). For example, if the size of the tag areas (611, 6111, 612) is 16 bits, 15 bits excluding the operation bit (612) may be used as the tag information (611, 6111). For example, if the size of the first tag information (611) includes b bits, the size of the second tag information (6111) may include 15-b bits.

[0152] The first tag information (611) may include a base address where the header is stored, and the second tag information (6111) may include actual tag information.

[0153] Referring to 601 of FIG. 6 and 601 of FIG. 7, the electronic device (101) can, under the control of the processor (120), determine the location of the header within an address using a random offset. The offset may include a value indicating a relative location in the memory address. The present invention can enhance security by randomly defining the location of the header within an address.

[0154] For example, the size of the random number of the random offset may include m bits, and the alignment size of the address where the tag area (611, 6111, 612) is to be stored may include k bits. The size of the random offset may be determined by the product of 2^m and 2^k. At this time, the maximum size of the size of the random offset may include 2^(m+k).

[0155] Referring to 601 of FIG. 6 and 601 of FIG. 7, the electronic device (101) can, under the control of the processor (120), determine the location of the first tag information (611) in the memory address or pointer (613) based on the alignment size of the address where the tag area (611, 6111, 612) is to be stored from the base address where the header is stored. For example, if the alignment size of the address where the tag area (611, 6111, 612) is to be stored is k bits, the first tag information (611) can be located from the k bit to the b+k-1 bit of the memory address or pointer (613). For example, when a process or pointer accesses a specific memory address, the tag area (611, 6111, 612) can be searched or detected by filling the first tag information (611) from bit K to bit b+k-1 of the memory address or pointer (613) and filling the remaining bits with 0. However, due to the limitation of the memory address size, the address of the tag area (611, 6111, 612) may have a limited memory size that can be recovered. The recoverable memory size may include a specific size. For example, the specific size may include 2^(b+k).

[0156] Referring to 603, the electronic device (101) can manage the pointer as a tag area (631, 632) and an address area (633) under the control of the processor (120). The electronic device (101) can define the pointer as a tag area (631, 632) and an address area (633) under the control of the processor (120). The tag area (631, 632) and the address area (633) can include the lowest bit of the tag area as an operation bit (632). The tag area can include the remaining bits excluding the middle operation bit (632) as a tag (631).

[0157] In one embodiment, the instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to manage pointers to tag areas (631, 632) and address areas (633). The instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to define pointers to tag areas (631, 632) and address areas (633).

[0158] In one embodiment, the electronic device (101) can, under the control of the processor (120), check whether the sum of the allocation size of the memory and the size of the random offset is less than a specific size.

[0159] In one embodiment, the electronic device (101), under the control of the processor (120), may set the operation bit (612, 632) to the first bit (e.g., “0”) if the sum of the allocation size of the memory and the size of the random offset is less than a specific size. The allocation size of the memory may include the alignment size of the address where the tag area (611, 6111, 612) is to be stored.

[0160] In one embodiment, instructions stored in memory (130), when executed by processor (120), may cause the electronic device (101) to set the operation bit (612, 632) to a first bit (e.g., “0”) if the sum of the allocated size of the memory and the size of the random offset is less than a specific size.

[0161] In one embodiment, the electronic device (101), under the control of the processor (120), may set the operation bit (612, 632) to a second bit (e.g., “1”) if the sum of the allocation size of the memory and the size of the random offset is greater than or equal to a specific size.

[0162] In one embodiment, the instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to set the operation bit (612, 632) to a second bit (e.g., “1”) if the sum of the allocated size of the memory and the size of the random offset is greater than or equal to a specific size.

[0163] In one embodiment, the electronic device (101) can manage allocation, deallocation, or access of memory using a 3-tuple lookup table (643) according to operation bits (612, 632) under the control of the processor (120).

[0164] In one embodiment, instructions stored in memory (130), when executed by the processor (120), may cause the electronic device (101) to manage allocation, deallocation, or access of memory using a 3-tuple lookup table (643) according to operation bits (612, 632).

[0165] In one embodiment, when the operation bits (612, 632) are set to the second bit, the electronic device (101) can manage allocation, deallocation, or access of memory using the 3-tuple lookup table (643) under the control of the processor (120).

[0166] In one embodiment, when the operation bits (612, 632) are set to the second bit, instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to manage allocation, deallocation, or access of memory using the 3-tuple lookup table (643).

[0167] Referring to 601 of FIG. 6 and 601 of FIG. 7, if the sum of the allocation size of the memory and the size of the random offset is smaller than a specific size, the electronic device (101), under the control of the processor (120), sets the operation bit (612) to the first bit, configures a 3-tuple based on the start address, the end address, and the second tag information (6111) for memory allocation and stores it in the header area, and allocates memory by designating the location of the header area as a base address and designating the start address as the base address plus a random offset value. For example, the start address for memory allocation may include a value obtained by adding a random offset address to the base address.

[0168] Referring to 601 of FIG. 6 and 601 of FIG. 7, if the sum of the allocation size of the memory and the size of the random offset is smaller than a specific size, the instructions stored in the memory (130), when executed by the processor (120), cause the electronic device (101) to set the operation bit (612) to the first bit, configure a 3-tuple based on the start address, the end address, and the second tag information (6111) for memory allocation, and store the 3-tuple in the header area, and allocate memory by designating the location of the header area as a base address and designating the start address as the base address plus the random offset value.

[0169] Referring to 603, if the sum of the allocation size of the memory and the size of the random offset is greater than or equal to a specific size, the electronic device (101) may, under the control of the processor (120), set the operation bit (632) to a second bit (e.g., “1”).

[0170] Referring to 603, if the sum of the allocation size of the memory and the size of the random offset is greater than or equal to a specific size, the instructions stored in the memory (130) may cause the electronic device (101) to set the operation bit (632) to a second bit (e.g., “1”) when executed by the processor (120).

[0171] Referring to 603, the electronic device (101) can allocate memory by configuring a 3-tuple based on a start address, an end address, and valid information for memory allocation based on a selected tag (631) under the control of the processor (120).

[0172] Referring to 603, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to allocate memory by constructing a 3-tuple based on the start address, end address, and valid information for memory allocation based on the selected tag (631).

[0173] Referring to 603, the electronic device (101) can, under the control of the processor (120), construct a 3-tuple based on the start address, end address, and valid information for memory allocation based on the selected tag (631) and store it in the lookup table (643).

[0174] Referring to 603, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to construct a 3-tuple based on the start address, end address, and valid information for memory allocation and store the same in the lookup table (643).

[0175] Referring to 601 of FIG. 6 and 601 of FIG. 7, when a pointer attempts to access a specific memory address, the electronic device (101) can check the operation bit of the pointer under the control of the processor (120).

[0176] Referring to 601 of FIG. 6 and 601 of FIG. 7, when a pointer attempts to access a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the operation bit of the pointer.

[0177] Referring to 601 of FIG. 6 and 601 of FIG. 7, the electronic device (101), under the control of the processor (120), if the operation bit is set to the first bit (e.g., “0”), can check the location of the header area, whether it corresponds to the start address and the end address for memory allocation included in the header area, and check the second tag information. The electronic device (101), under the control of the processor (120), can check whether a specific memory address corresponds to the start address and the end address and whether the second tag information (6111) matches. The electronic device (101), under the control of the processor (120), can allow memory access if the specific memory address corresponds to the start address and the end address and the second tag information (6111) matches. The electronic device (101), under the control of the processor (120), may determine a memory security violation if a specific memory address does not correspond to a start address or an end address, or if the second tag information (6111) does not match.

[0178] Referring to 601 of FIG. 6 and 601 of FIG. 7, when a pointer attempts to access a specific memory address, the instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the location of the header area if the operation bit is set to the first bit (e.g., “0”), and to check whether it corresponds to the start address and the end address for memory allocation included in the header area and to check the second tag information. The instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check whether a specific memory address corresponds to the start address and the end address and to check whether the second tag information (6111) matches. The instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to allow memory access if a specific memory address corresponds to a start address or an end address and the second tag information (6111) matches. The instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to determine a memory security violation if a specific memory address does not correspond to a start address or an end address or the second tag information (6111) does not match.

[0179] Referring to 603, the electronic device (101), under the control of the processor (120), can check the operation bit (632) of the pointer when a process or pointer attempts to access a specific memory address.

[0180] Referring to 603, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the operation bit (632) of a pointer when a process or pointer attempts to access a specific memory address.

[0181] Referring to 603, when a process or pointer accesses a specific memory address, the electronic device (101), under the control of the processor (120), if the operation bit (632) is set to the second bit (e.g., “1”), can check whether the start address and end address for memory allocation correspond to the valid information based on the 3-tuple stored in the lookup table and determine whether there is a memory safety violation.

[0182] Referring to 603, the instructions stored in the memory (130), when executed by the processor (120), cause the electronic device (101) to check whether the operation bit (632) corresponds to the start address and end address for memory allocation based on the 3-tuple stored in the lookup table (643) and whether there is valid information, and determine whether there is a memory safety violation.

[0183] Referring to 603, when a process or pointer accesses a specific memory address, the electronic device (101), under the control of the processor (120), can check the tag value included in the pointer if the operation bit (632) is set to the second bit (e.g., “1”), and check the 3-tuple corresponding to the tag value in the lookup table (643).

[0184] Referring to 603, a 3-tuple may include a start address, an end address, and valid information. Under the control of the processor (120), the electronic device (101) may determine whether the address of the pointer or processor requesting access corresponds to the start address and end address included in the 3-tuple.

[0185] Referring to 603, the electronic device (101), under the control of the processor (120), may allow a process or pointer to access a specific memory address if the address of the pointer or processor requesting access corresponds to the start address and end address included in the 3-tuple, and the valid information included in the 3-tuple is valid. The electronic device (101), under the control of the processor (120), may determine a memory security violation if the address of the pointer or processor requesting access does not correspond to the start address and end address included in the 3-tuple, or the valid information included in the 3-tuple is invalid.

[0186] Referring to 603, when a process or pointer accesses a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the tag value included in the pointer if the operation bit is set to the first bit (e.g., “0”), and to check the 3-tuple corresponding to the tag value in the lookup table.

[0187] Referring to 603, the instructions stored in the memory (130), when executed by the processor (120), may allow the electronic device (101) to allow a process or pointer to access a specific memory address if the address of the pointer or processor that requested access corresponds to the start address and end address included in the 3-tuple, and the valid information included in the 3-tuple is valid. The instructions stored in the memory (130), when executed by the processor (120), may allow the electronic device (101) to determine a memory safety violation if the address of the pointer or processor that requested access does not correspond to the start address and end address included in the 3-tuple, or the valid information included in the 3-tuple is invalid.

[0188] Referring to 601 of FIG. 6 and 601 of FIG. 7, when requesting release of a specific memory address from a process or pointer, the electronic device (101) can, under the control of the processor (120), check the operation bit (612) of the pointer.

[0189] Referring to 601 of FIG. 6 and 601 of FIG. 7, when requesting release of a specific memory address from a process or pointer, if the operation bit is set to the first bit (e.g., “0”), the electronic device (101) may, under the control of the processor (120), change the start address, end address, and second tag information (612) for memory allocation included in the header area to invalid. For example, the start address, end address, and second tag information (612) may be changed to (0,0,0).

[0190] Referring to 601 of FIG. 6 and 601 of FIG. 7, when requesting release of a specific memory address from a process or pointer, if the operation bit is set to the first bit (e.g., “0”), the electronic device (101) can, under the control of the processor (120), check the first tag information (611) (e.g., base address) to check the location of the header area. The electronic device (101) can, under the control of the processor (120), check the start address, end address, and second tag information (612) in the checked header area.

[0191] Referring to 601 of FIG. 6 and 601 of FIG. 7, when a process or pointer requests the release of a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the operation bit (612) of the pointer.

[0192] Referring to 601 of FIG. 6 and 601 of FIG. 7, when requesting release of a specific memory address from a process or pointer, if the operation bit is set to the first bit (e.g., “0”), instructions stored in the memory (130) can cause the electronic device (101) to change to invalid based on the start address, end address, and second tag information (612) for memory allocation included in the header area when executed by the processor (120).

[0193] Referring to 601 of FIG. 6 and 601 of FIG. 7, when requesting release of a specific memory address from a process or pointer, if the operation bit is set to the first bit (e.g., “0”), the instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check the location of the header area by checking 1 tag information (611) (e.g., base address).

[0194] Referring to 603, the electronic device (101), under the control of the processor (120), can check the operation bit (632) of the pointer when requesting the release of a specific memory address in a process or pointer.

[0195] Referring to 603, instructions stored in the memory (130), when executed by the processor (120), may cause the electronic device (101) to check the operation bit (632) of the pointer when requesting the release of a specific memory address in the process or pointer.

[0196] Referring to 603, when requesting release of a specific memory address from a process or pointer, the electronic device (101), under the control of the processor (120), if the identified operation bit is set to the second bit (e.g., “1”), checks whether the start address and end address for memory allocation correspond to the valid information based on the 3-tuple stored in the lookup table, and changes the valid information to invalid (e.g., “0”) to release the memory usage.

[0197] Referring to 603, when a process or pointer requests the release of a specific memory address, instructions stored in the memory (130), when executed by the processor (120), can cause the electronic device (101) to check whether the start address and end address for memory allocation correspond to the valid information based on the 3-tuple stored in the lookup table if the confirmed operation bit is set to the second bit (e.g., “1”), and change the valid information to invalid (e.g., “0”) to release the memory usage.

[0198] In one embodiment, the electronic device (101) includes a processor (120); and a memory (130) storing instructions, which, when executed by the processor (120), cause the electronic device (101) to: when there is a memory allocation request of a process, check whether all specific bits of a pointer are available; if at least some of the specific bits of the pointer are not available, check whether a selectable tag is available in a lookup table including an index to a tag; if there is a selectable tag, select the tag; and based on the selected tag, construct a 3-tuple based on a start address, an end address, and valid information for memory allocation and store the 3-tuple in the lookup table; set an operation bit to a first bit; store the tag and the operation bit in a first region of the pointer; and store a start address in a second region of the pointer to allocate memory.

[0199] In one embodiment, the instructions, when executed by the processor (120), may cause the electronic device (101) to reselect a tag if no selectable tag is available, construct and store a 3-tuple based on the selected tag, a start address, an end address, and a tag for memory allocation, store the 3-tuple in a specific tree, set an operation bit to a second bit, store the tag and the operation bit in a first region of the pointer, and store the start address in a second region of the pointer to allocate memory.

[0200] In one embodiment, the instructions, when executed by the processor (120), cause the electronic device (101) to check the operation bit of the pointer when the pointer attempts to access a specific memory address, and if the operation bit is set to the first bit, to check whether the pointer corresponds to a start address for memory allocation, an end address, and validity information based on a 3-tuple stored in a lookup table, and to determine whether a memory safety violation has occurred by checking whether the pointer corresponds to a start address, an end address, and validity information for memory allocation.

[0201] In one embodiment, the instructions, when executed by the processor (120), may cause the electronic device (101) to check the operation bit of a pointer when the pointer attempts to access a particular memory address, and if the operation bit is set to the second bit, determine whether a memory safety violation has occurred by determining whether the start address and end address for the tag and memory allocation correspond to a cache tuple.

[0202] In one embodiment, the instructions, when executed by the processor (120), may cause the electronic device (101) to determine whether a memory safety violation has occurred based on whether the start and end addresses for tag and memory allocation correspond to a particular tree, if the start and end addresses for tag and memory allocation do not correspond to cache tuples.

[0203] In one embodiment, the instructions, when executed by the processor (120), cause the electronic device (101) to check the operation bit of the pointer when requesting the release of a specific memory address, and if the operation bit is set to the first bit, to check whether the start address and end address for memory allocation correspond to a 3-tuple stored in the lookup table and to check the validity information, and to change the validity information to invalid.

[0204] In one embodiment, the instructions, when executed by the processor (120), cause the electronic device (101) to check the operation bit of a pointer when requesting the release of a particular memory address, and if the operation bit is set to the second bit, to release tuples and cache tuples of a particular tree based on a start address, an end address, and a tag for the memory allocation.

[0205] In one embodiment, the instructions, when executed by the processor (120), may cause the electronic device (101) to determine whether the sum of the allocation size of the memory and the size of the random offset is less than a specific size if all specific bits of the pointer are available, set the operation bit to the first bit if the sum of the allocation size of the memory and the size of the random offset is less than the specific size, construct a 3-tuple in the header based on the start address, the end address, and the tag for the memory allocation and store it in the pointer, and allocate memory by specifying a value obtained by adding the random offset to the position of the header as the start address.

[0206] In one embodiment, the instructions, when executed by the processor (120), may cause the electronic device (101) to set the operation bit to a second bit if the sum of the allocation size of the memory and the size of the random offset is greater than or equal to a specific size, and to allocate memory by constructing a 3-tuple based on the start address, end address, and valid information for the memory allocation based on the selected tag.

[0207] In one embodiment, the instructions, when executed by the processor (120), cause the electronic device (101) to check the operation bit of the pointer when the pointer attempts to access a specific memory address, and if the operation bit is set to the first bit, to check the location of the header, and to check whether the tag corresponds to a start address, an end address, and a start address for memory allocation included in the header, and to check whether the tag corresponds to a start address, an end address, and a start address for memory allocation to determine whether a memory safety violation has occurred.

[0208] In one embodiment, the instructions, when executed by the processor (120), cause the electronic device (101) to:

[0209] When a pointer attempts to access a specific memory address, the pointer's operation bit is checked, and if the operation bit is set to the second bit, it can be used to determine whether memory safety is violated by checking whether the starting address and ending address for valid information and memory allocation are valid.

[0210] In one embodiment, the instructions, when executed by the processor (120), cause the electronic device (101) to check the operation bit of the pointer when requesting the release of a particular memory address, and if the operation bit is set to the first bit, to invalidate it based on the start address, end address, and tag for the memory allocation included in the header.

[0211] In one embodiment, the instructions, when executed by the processor (120), may cause the electronic device (101) to check the operation bit of the pointer when requesting the release of a specific memory address, to check whether it corresponds to the start address and end address for memory allocation included in the header, to check the validity information, and to change the validity information to invalid.

[0212] In one embodiment, a memory management method may include, when a memory allocation request of a process is made, an operation of checking whether all specific bits of a pointer are available for use; an operation of checking whether at least some of the specific bits of the pointer are available for use in a lookup table including an index to a tag; an operation of selecting a tag if there is a selectable tag; an operation of constructing a 3-tuple based on a start address, an end address, and valid information for memory allocation based on the selected tag and storing the 3-tuple in the lookup table; an operation of setting an operation bit to a first bit; and an operation of allocating memory by storing the tag and the operation bit in a first area of ​​the pointer and storing the start address in a second area of ​​the pointer.

[0213] In one embodiment, the memory management method may include an operation of reselecting a tag if there is no selectable tag; an operation of constructing and storing a 3-tuple based on a start address, an end address, and a tag for memory allocation based on the selected tag, and storing the 3-tuple in a specific tree; an operation of setting an operation bit to a second bit; and an operation of allocating memory by storing a tag and an operation bit in a first region of a pointer and storing a start address in a second region of the pointer.

[0214] In one embodiment, the memory management method may include an operation of checking an operation bit of a pointer when a pointer attempts to access a specific memory address; an operation of checking whether the operation bit corresponds to a start address for memory allocation and an end address and validity information based on a 3-tuple stored in a lookup table if the operation bit is set to the first bit; and an operation of determining whether a memory safety violation exists by checking whether the start address corresponds to the end address for memory allocation and the validity information.

[0215] In one embodiment, the memory management method may include: checking an operation bit of a pointer when the pointer attempts to access a specific memory address; and, if the operation bit is set to a second bit, determining whether a memory safety violation occurs by determining whether a start address and an end address for tag and memory allocation correspond to a cache tuple.

[0216] In one embodiment, the memory management method may include: an operation of determining whether the sum of the allocation size of the memory and the size of the random offset is less than a specific size if all specific bits of the pointer are available; an operation of setting the operation bit to the first bit if the sum of the allocation size of the memory and the size of the random offset is less than the specific size; and an operation of configuring a 3-tuple in a header based on a start address, an end address, and a tag for memory allocation and storing the 3-tuple in the pointer, and allocating memory by specifying a value obtained by adding a random offset to the position of the header as the start address.

[0217] In one embodiment, the memory management method may include: setting an operation bit to a second bit if the sum of an allocation size of memory and a size of a random offset is greater than or equal to a specific size; and allocating memory by constructing a 3-tuple based on a start address, an end address, and valid information for memory allocation based on the selected tag.

[0218] In one embodiment, the memory management method may include: checking an operation bit of a pointer when a pointer attempts to access a specific memory address; if the operation bit is set to the first bit, checking the location of a header, checking whether it corresponds to a start address and an end address for memory allocation included in the header and a tag, and determining whether a memory safety violation occurs by checking whether it corresponds to the start address and an end address for memory allocation and the tag; and if the operation bit is set to the second bit, determining whether a memory safety violation occurs based on whether valid information and the start address and an end address for memory allocation are valid.

[0219] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0220] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0221] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0222] Various embodiments of the present document may be implemented as software (e.g., a program (140)) including one or more instructions stored in a storage medium (e.g., an internal memory (136) or an external memory (138)) readable by a machine (e.g., an electronic device (101)). For example, a processor (e.g., a processor (120)) of the machine (e.g., an electronic device (101)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0223] According to one embodiment, the method according to various embodiments disclosed in this document may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0224] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and arranged in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In electronic devices, processor; and Contains memory for storing instructions, The above instructions, when executed by the processor, cause the electronic device to: When a process requests memory allocation, it checks whether all specific bits of the pointer are available. If at least some of the specific bits of the above pointer are not available, a lookup table containing an index to the tag is checked to see if there is a selectable tag, If there are selectable tags, let them select a tag, Based on the selected tag, a 3-tuple is constructed based on the start address, end address, and valid information for memory allocation and stored in the lookup table. Set the operation bit to the first bit, An electronic device that stores the tag and the operation bit in a first area of the pointer and stores a start address in a second area of the pointer to allocate memory.

2. In paragraph 1, The above instructions, when executed by the processor, cause the electronic device to: If there are no selectable tags, select the tag again. Based on the selected tag, a 3-tuple is constructed and stored based on the start address, end address, and the tag for memory allocation, and the 3-tuple is stored in a specific tree. Set the above operation bit to the second bit, An electronic device that stores the tag and the operation bit in a first area of the pointer and stores a start address in a second area of the pointer to allocate memory.

3. In paragraph 1, The above instructions, when executed by the processor, cause the electronic device to: When the above pointer attempts to access a specific memory address, the operation bit of the above pointer is checked, If the above operation bit is set to the first bit, it is checked whether the start address and end address for memory allocation correspond to the 3-tuple stored in the lookup table and the valid information, An electronic device that determines whether there is a memory safety violation by checking whether the start address and end address for memory allocation correspond to the above valid information.

4. In paragraph 2, The above instructions, when executed by the processor, cause the electronic device to: When the above pointer attempts to access a specific memory address, the operation bit of the above pointer is checked, If the above operation bit is set to the second bit, it is determined whether there is a memory safety violation by whether the start address and end address for the tag and memory allocation correspond to a cache tuple, An electronic device that determines whether a memory safety violation has occurred based on whether the start address and end address for the tag and memory allocation correspond to the specific tree, if the start address and end address for the tag and memory allocation do not correspond to the cache tuple.

5. In paragraph 2, The above instructions, when executed by the processor, cause the electronic device to: When requesting release of the above specific memory address, the operation bit of the above pointer is checked, An electronic device that, if the operation bit is set to the first bit, verifies whether the start address and end address for memory allocation correspond to the 3-tuple stored in the lookup table and the valid information, and changes the valid information to invalid.

6. In paragraph 2, The above instructions, when executed by the processor, cause the electronic device to: When requesting release of the above specific memory address, the operation bit of the above pointer is checked, An electronic device that releases tuples and cache tuples of a specific tree based on a start address, an end address, and the tag for memory allocation when the operation bit is set to the second bit.

7. In paragraph 1, The above instructions, when executed by the processor, cause the electronic device to: If all specific bits of the above pointer are available, check whether the sum of the allocated size of the memory and the size of the random offset is less than a specific size. If the sum of the memory allocation size and the random offset size is less than a specific size, the operation bit is set to the first bit. A 3-tuple is formed in the header based on the start address, end address, and the tag for memory allocation, and is stored in the pointer, and a value obtained by adding a random offset to the position of the header is designated as the start address to allocate memory. If the sum of the memory allocation size and the random offset size is greater than or equal to a specific size, the operation bit is set to the second bit. Based on the selected tag, memory is allocated by constructing a 3-tuple based on the start address, end address, and valid information for memory allocation, and the electronic device.

8. In paragraph 7, The above instructions, when executed by the processor, cause the electronic device to: When the above pointer attempts to access a specific memory address, the operation bit of the above pointer is checked, If the operation bit is set to the first bit, the location of the header is checked, and whether it corresponds to the start address and end address for memory allocation included in the header and the tag are checked, An electronic device that determines whether there is a memory safety violation by checking whether the start address and end address for memory allocation correspond to the above tag.

9. In paragraph 7, The above instructions, when executed by the processor, cause the electronic device to: When the above pointer attempts to access a specific memory address, the operation bit of the above pointer is checked, An electronic device that determines whether a memory safety violation has occurred by determining whether the start address and end address for the valid information and memory allocation are valid when the operation bit is set to the second bit.

10. In paragraph 7, The above instructions, when executed by the processor, cause the electronic device to: When requesting release of the above specific memory address, the operation bit of the above pointer is checked, An electronic device that, if the above operation bit is set to the first bit, changes the start address, end address, and tag for memory allocation included in the header to invalid.

11. In paragraph 7, The above instructions, when executed by the processor, cause the electronic device to: When requesting release of the above specific memory address, the operation bit of the above pointer is checked, An electronic device that checks whether the start address and end address for memory allocation included in the above header correspond to the above valid information and changes the above valid information to invalid.

12. In the memory management method, When a process requests memory allocation, an action is taken to check whether all specific bits of the pointer can be used; If at least some of the specific bits of the above pointer are not available, an operation of checking whether there is a selectable tag in a lookup table containing an index to the tag; Action to select a tag if there are selectable tags; An operation of constructing a 3-tuple based on the start address, end address, and valid information for memory allocation based on the selected tag and storing the tuple in the lookup table; An action of setting the operation bit to the first bit; and A method comprising an operation of allocating memory by storing the tag and the operation bit in a first area of the pointer and storing a start address in a second area of the pointer.

13. In paragraph 12, If there are no selectable tags, an action is taken to reselect the tag; An operation of storing a 3-tuple based on a start address, an end address, and the tag for memory allocation based on the selected tag, and storing the 3-tuple in a specific tree; An operation of setting the above operation bit to the second bit; and A method comprising an operation of allocating memory by storing the tag and the operation bit in a first area of the pointer and storing a start address in a second area of the pointer.

14. In paragraph 13, When the above pointer attempts to access a specific memory address, an action of checking the operation bit of the above pointer; If the above operation bit is set to the first bit, an operation of checking whether the start address and end address for memory allocation correspond to the 3-tuple stored in the lookup table and the validity information; An operation to determine whether there is a memory safety violation by checking whether the start address and end address for memory allocation correspond to each other and the validity information; and A method comprising an operation of determining whether a memory safety violation occurs by determining whether the start address and end address for the tag and memory allocation correspond to a cache tuple if the operation bit is set to the second bit.

15. In paragraph 12, If all specific bits of the above pointer are available, an operation to check whether the sum of the allocated size of the memory and the size of the random offset is less than a specific size; An operation of setting the operation bit to the first bit if the sum of the allocation size of the memory and the size of the random offset is less than a specific size; and An operation of configuring a 3-tuple in a header based on a start address, an end address, and the tag for memory allocation and storing it in the pointer, and allocating memory by specifying a value obtained by adding a random offset to the position of the header as the start address; An operation of setting the operation bit to the second bit if the sum of the allocation size of the memory and the size of the random offset is greater than or equal to a specific size; An operation to allocate memory by constructing a 3-tuple based on the start address, end address, and valid information for memory allocation based on the selected tag; When the above pointer attempts to access a specific memory address, an action of checking the operation bit of the above pointer; If the operation bit is set to the first bit, an operation of checking the location of the header, checking whether it corresponds to the start address and end address for memory allocation included in the header, and checking the tag, and determining whether there is a memory safety violation by checking whether it corresponds to the start address and end address for memory allocation; and A method comprising an operation of determining whether a memory safety violation occurs by determining whether the start address and end address for the valid information and memory allocation are valid when the operation bit is set to the second bit.

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