Small volume plasma confinement ring for high conductance and uniformity

Abstract

A confinement ring is disclosed. The confinement ring includes a lower section extending between a lower inner diameter and a lower outer diameter. The confinement ring includes an upper section extending between an upper inner diameter and an upper outer diameter. The confinement ring includes a middle section that provides a vertical connection between the lower section and the upper section. A lower part of the middle section connects with the lower section proximate to a lower outer diameter and connects with the upper section between an inner upper section and an outer upper section. A plurality of fingers are defined from a portion of the lower section and a portion of the middle section. Spacing between respective ones of the plurality of fingers provide conduction pathways through the confinement ring.

Description

SMALL VOLUME PLASMA CONFINEMENT RING FOR HIGH CONDUCTANCE AND UNIFORMITYBACKGROUND1. Field of the Invention

[0001] The present embodiments relate to semiconductor processing equipment structures, and in particular, to plasma confinement structures used to enable high conductance and improved etch uniformity.2. Description of the Related Art

[0001] In semiconductor processing, a substrate undergoes various operations to form features that define integrated circuits. For example, for an etch operation, the substrate is received into a processing chamber and, depending on type of feature to be formed, specific types of reactive gases are supplied to the chamber while radio frequency power is applied to generate plasma. The substrate is placed on a substrate support defined over a lower electrode, such as an electrostatic chuck. An upper electrode, functioning as a showerhead, is used to provide reactive gases into the process chamber. Radio frequency power is applied to the reactive gases through a corresponding match network to generate the plasma used to selectively etch features of an integrated circuit (IC). Generally, reactive gases and etch by-products generated during etching need to be removed from the plasma chamber in order to maintain processing integrity.

[0002] In chambers that utilize small plasma volumes, there is also a need to confine the plasma for optimal performance. The need for plasma confinement, however, must be balanced with the need to provide efficient levels of conductance, i.e., to remove gases from the small plasma volume. As will be appreciated, any change to parts and / or structure of a plasma processing chamber will require many engineering improvements to ensure optimal performance. Prior designs include those described in US 8,826,855 B2, which is assigned to Lam Research Corporation, and is incorporated by reference for all purposes.

[0003] It is in this context that embodiments of the invention arise.SUMMARY

[0004] Embodiments of the disclosure provide embodiments of a process chamber, used for processing semiconductor wafers. An embodiment provided is a confinement ring used for confining plasma inside of a plasma processing chamber.

[0005] In one embodiment, a diameter of the silicon wall (e.g., middle section 206) of the confinement ring is adjusted to a smaller diameter. A vertical slot is cut into the wall (e.g., middle section 206) to keep a large open area for high conductance, in addition to the slot in the lower section 202. In one embodiment, conductance can be kept equal to or larger (as needed for the application) than prior art confinement designs. Using a smaller wall diameter is believed to provide for improved plasma uniformity over the wafer area. The design of the confinement ring 120 disclosed herein was especially useful to improve uniformity for lower power processes used in logic applications.

[0006] In one configuration, the middle section 206 inside diameter of the confinement ring 120 was decreased. In one embodiment, the inside diameter was decreased by approximately 20%. In another embodiment, the inside diameter was decreased by approximately 15%. In another embodiment, the inside diameter was decreased by approximately 10%. Even with the decrease of the inside diameter (making the plasma volume 103 smaller), the conductance was able to remain high (e.g., up to 50 sccm / Torr). As disclosed herein, the inside diameter will define the approximate space for the plasma volume in the horizontal dimension. Reducing the volume will also assist in confining more of the plasma in a region that is closer to the top of the wafer area.

[0007] Therefore, the design of the confinement ring 120 provided for a significant advantage by enabling a larger range of confined conductance. In tests, it was discovered that the plasma remains confined at maximum 60 MHz power delivery for conductance values of 50 sccm / Torr.

[0008] In one embodiment, a confinement ring is disclosed. The confinement ring includes a lower section extending between a lower inner diameter and a lower outer diameter. The confinement ring includes an upper section extending between an upper inner diameter and an upper outer diameter. The confinement ring includes a middle section that provides a vertical connection between the lower section and the upper section. A lower part of the middle section connects with the lower section proximate to a lower outer diameter and connects with the upper section between an inner upper section and an outer upper section. A plurality of fingers are defined from a portion of the lower section and a portion of the middle section. Spacing, e.g., slots, between respective ones of the plurality of fingers provide conduction pathways through the confinement ring.

[0009] In some embodiments, the spacing between respective ones of the plurality of fingers define an uninterrupted opening between the horizontal lower section and the vertical middle section.

[0010] In some embodiments, an extension section having a downward projection is integral with the lower section, the extension section is proximate to the lower inner diameter.

[0011] In some embodiments, the outer upper section extends radially out from the connection with the middle section and the inner upper section extends radially in from the connection with the middle section.

[0012] In some embodiments, an interface between the middle section and the lower section form an inward L-shape, such that said plurality of fingers retain said inward L-shape.

[0013] In some embodiments, the lower section is substantially horizontal, or the lower section has a sloping surface, or the middle section has a sloping surface.

[0014] In some embodiments, the plurality of fingers of the confinement ring surround a plasma volume of a plasma processing chamber that is configured to receive the confinement ring.

[0015] In one embodiment, a confinement ring for confining plasma in a semiconductor processing chamber is disclosed. The confinement ring includes a lower section extending between a lower inner diameter and a lower outer diameter. The confinement ring includes an extension section having a downward projection that is integral with the lower section, the extension section is proximate to the lower inner diameter. The confinement ring includes a middle section that is connected to the lower section proximate to the lower outer diameter. The confinement ring includes an upper section extending between an upper inner diameter and an upper outer diameter. The middle section connects with the upper section between an inner upper section and an outer upper section. The outer upper section is larger in annular diameter than the inner upper section. A first region of the lower section and a second region of the middle section form a plurality of fingers. Conduction pathways, e.g., slots, are disposed between respective ones of the plurality of fingers.

[0016] In some embodiments, the conduction pathways extend continuously from along the first region of the lower section to along the second region of the middle section.

[0017] In some embodiments, the conduction pathways form slots between said plurality of fingers. The plurality fingers are arranged radially and are configured to surround an inner region of a plasma volume.

[0018] In some embodiments, the lower section is substantially horizonal, the middle section is substantially vertical, and the upper section is substantially horizontal.BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A illustrates a high level diagram of a semiconductor plasma processing chamber, in accordance with one embodiment.

[0020] Figure IB illustrates a plot of total power verses conductance, to illustrate an advantage of the confinement ring, in accordance with one embodiment.

[0021] Figure 2 illustrates a more detailed cross-sectional view of the confinement ring, in accordance with one embodiment.

[0022] Figure 3 illustrates a three-dimensional view of a side of the confinement ring, in accordance with one embodiment.

[0023] Figures 4A and 4B illustrate three-dimensional views of the confinement ring, in accordance with one embodiment.

[0024] Figure 5A provides a top view of the confinement ring with a cut-out view for a detail, in accordance with one embodiment.

[0025] Figure 5B is a side view that shows the conduction pathways disposed between the plurality of fingers of the middle section, in accordance with one embodiment.

[0026] Figure 6 illustrates a cross-sectional view of the confinement ring, in accordance with one embodiment.

[0027] Figure 7 illustrates a more detailed view of the confinement ring crosssection, in accordance with one embodiment.

[0028] Figure 8A is a magnified view a detail shown in Figure 5A, in accordance with one embodiment.

[0029] Figure 8B illustrates a magnified side view E-E of Figure 5 A, in accordance with one embodiment.

[0030] Figure 9A illustrates an alternate shape of the conduction pathway slots, in accordance with another embodiment.

[0031] Figures 9B-9E illustrate alternate embodiments where the lower section and / or the middle section have a sloped angle.

[0032] Figure 9F illustrates another configuration of the confinement ring, in accordance with an alternate embodiment.DESCRIPTION

[0033] Embodiments of the disclosure illustrate examples of a confinement ring for use in a semiconductor processing chamber. The confinement ring is used to define and control an interior plasma volume that surrounds a region over the wafer disposed between the lower electrode and upper electrode. The confinement ring surrounds the plasma volumeand assists confining plasma to the region over the wafer while preventing unconfined plasma ignition outside of the plasma volume. The confinement ring, through its slots, also assists in allowing conduction of gases out of the plasma volume for efficient removal of plasma gases and plasma byproducts away from the regions over the wafer. In one embodiment, the confinement ring disclosed herein is optimized with a smaller diameter than usually found in advanced semiconductor etching chambers. The confinement ring is also designed to include unique conduction pathways, i.e., slots, defined in a lower section as well as the middle section of the confinement ring. The disclosed design of the confinement ring provides significant improvement in plasma etch performance and uniformity over the wafer. The unique design is especially useful in low power applications used for etching logic features, and the design provides for a wider range of conduction while still providing confinement of plasma.

[0034] It should be appreciated that the present embodiments can be implemented in numerous ways, such as a process, an apparatus, a system, a device, or a method. Several embodiments are described below.

[0035] Figure 1 A illustrates a high level diagram of a semiconductor plasma processing chamber, in accordance with one embodiment. As shown, a chamber 100 is configured to enclose components that define a plasma volume 103. A wafer 101 is configured to be placed over a substrate support structure, which is disposed over a lower electrode 102. Typically, the lower electrode 102 functions as an electrostatic chuck for clamping and securing the wafer 101 to the substrate support structure. In this example embodiment, a radio frequency (RF) generator 114 is connected to a match network and then to the lower electrode 102. It should be understood that in other configurations, more than one RF generator may be connected to the lower electrode, and such generators are typically configured to operate a various frequencies, e.g., 100kHz, 400kHz, 2 MHz, 27 MHz, 13.56 MHz, 60 MHz, etc. More than one match network may be used. The chamber 100 may be operated at more than one RF frequency, e.g., at high and low dual frequencies. The upper inner electrode 104, in one configuration is connected to ground 113, to enable capacitively coupled plasma (CCP) operation. In alternate configurations, the upper electrode may also be powered using one or more RF generators. The configuration of the RF generators, the power supplied, the frequencies supplied, and other control parameters are usually set based on a recipe required for a particular plasma processing operation, e.g., etching and / or deposition.

[0036] Continuing with the chamber 100 of Figure 1 A, an edge ring 108 is typically provided to surround an edge of the wafer 101. The edge ring 108 is engineered to compensate for edge effects on the wafer by reducing non-uniformity effects caused by the edge transition of the wafer. As shown, a dielectric structure 110 is configured to surround the lower electrode and the edge ring 108. For ease of discussion, the dielectric structure 110 is shown as one part, but in some embodiments, the dielectric structure 110 is formed by two or more rings. The dielectric structure 110 is typically made of a ceramic material. One example ceramic material is quartz. In some embodiments, other types of structures, such as a conductive ground ring, may be disposed adjacent to the dielectric structure 110. For instance, a ground ring may surround at least part of the radially outer portion of dielectric structure 110. In some instances, the confinement ring can be lowered to a position where the lower extension surface would radially surround, and forming a gap with a top portion of the grounding ring.

[0037] Further enclosing the plasma volume 103 is an upper outer electrode 106. The upper outer electrode may be connected to ground or power, depending on the process being run in the chamber 100. A ground ring 116 is shown to at least partially surround part of the dielectric structure 110 and the lower electrode 102.

[0038] In one embodiment, a confinement ring 120 is disclosed. The confinement ring 120 is configured to surround the plasma volume 103. The confinement ring 120 is configured with a lower selection 202 and a middle section 206, and an upper section 204 (see, FIG. 2). A portion of the lower section 202 and a portion of the middle section 206 form a plurality of fingers 207 that are radially arranged around the enclosing perimeter of the confinement ring 120. Therefore, spaces in the form of slots are defined between the respective fingers 207 (See FIG. 3). The spaces between the respective fingers 207 provide conduction pathways for gases leaving the plasma volume 103, while also functioning to confine the plasma generated within the plasma volume 103. In one embodiment, the spaces between the fingers 207 form slots that have a width of about .110 inch and each of the respective fingers 207 have a width of about .110 inch. In some embodiments, the spaces between the fingers have a width that is substantially the same all along the slots between the fingers 207. In other words, in some embodiments, the width of a single slot is substantially uniform when measured from the middle section 206 to the lower section 202.

[0039] In other embodiments, the slots may have different width profiles to account for anticipated erosion wear of the width of the slots. For instance, the slots width closer to the inner diameter (e.g., 214a) in the lower section 202 may be smaller than thewidth closer the outer diameter of the lower section 202 (e.g., 214b). Thus, as wear proceeds, the inner diameter of the slots may have more material to erode and therefore extend the lifetime use of the confinement ring. Having a tapered slot design (i.e. smaller diameter / slot width closer to the inner diameter portion of the confinement ring compare to the outer radial portion of the confinement ring) is especially advantages when the ring is used in semiconductor fabrication processes that cause expedited inner diameter slot erosion.

[0040] In one configuration, a throttle plate 118 in the form of a radial disc can be integrated with the chamber 100 to provide throttling of the conduction gases leaving the plasma volume 103 via the conduction pathways. By way of example, the throttle plate 118 can be raised to be closer to a lower outer surface of the confinement ring 120, thus reducing conduction out of the slots of the lower section 202. If the throttle plate 118 is lowered to be further from the lower outer surface of the confinement ring 120, the conduction of gases out of the slots of the lower section 202 will not be reduced or throttled.

[0041] In one embodiment, the confinement ring 202 has middle section 206 that is reduced in diameter, and does not define outer diameter of the confinement ring 202. As shown in FIG. 1A, instead of having the middle section 206 extend out to diameter A, the diameter is reduced inwardly toward diameter B. This places connection of the middle section 206 with an upper section 204 closer to the inner diameter of said upper section 204. This leaves a larger upper section 204 beyond the connection to the middle section 206. In one embodiment, the upper section 204 has an annular width that enables the upper section 204 to be attached to an upper structure (e.g., backplate) of the chamber 100, when installed.

[0042] Figure IB illustrates a plot of total power verses conductance, to illustrate an advantage of the confinement ring 120, in accordance with one embodiment. As shown, the Y-axis provides conductance measured in standard cubic centimeter per minute / millitorr (sccm / mT) and the X-axis provides total RF power in watts (W). By way of example, the total RF power is that power provided to the plasma chamber 100 through one or more power supplies to generate a plasma in the plasma volume 103. As mentioned above, the measurement of conduction refers to a measured flow of process gases and gaseous byproducts that are produced during a plasma processing operation, and which must be removed (e.g., conducted out) of the plasma volume 103.

[0043] Other confinement structures were tested at lower power ranges, e.g., 1,000 W to about 2,500 W. It was discovered that at low conductance levels, e.g., lower than 20 sccm / mT, the plasma remains confined. Plot line 152 shows the approximate location where plasm becomes unconfined, while plot line 154 shows the approximate location where plasma confinement is marginal (i.e., some confinement but not sufficient for commercialapplications). However, in order to achieve improved etch performance when etching logic features on a wafer, it is necessary to increase the conductance. In other confinement structures tested, it was shown that plasma confinement was marginal above 20 sccm / mT, and above 30 sccm / mT, the plasma became unconfined within the plasma volume 103.

[0044] However, when implementing the confinement ring 120, tests in the optimal lower power levels used in logic etching (e.g., 1,000 W to about 2,500 W, at 60 MHz) showed significant improvement to enable plasma confinement at conductance levels of 50 sccm / mT and higher, as illustrated by plot line 150. As a result of the improvements to the confinement ring 120 structure, having a smaller diameter and conduction paths in a lower section and middle section, plasma etch uniformity across the surface of the wafer was significantly improved. In general, the confinement ring 120 provides for an advantageously wider range of confined plasma conductance as compared to prior confinement structures.

[0045] Figure 2 illustrates a more detailed cross-sectional view of the confinement ring 120, in accordance with one embodiment. As shown, the confinement ring 120 includes a lower section 202, an upper section 204, and a middle section 206. An interface between the middle section and the lower section form an inward or backwards L- shape, such that said plurality of fingers 207 (in each of the lower section 202 and the middle section 206) retain said inward L-shape. The lower section 202 and the middle section 206 includes regions that form conduction pathways 240 between respective ones of a plurality of fingers 207. The plurality of fingers 207 are formed from material of the lower section 202 and the middle section 206, in the approximate location of the conduction pathways 240. The conduction pathways 240 are spaces that form slots in portions between respective adjacent ones of the plurality of fingers 207. In one embodiment, the confinement ring 120 is made of silicon or polysilicon. In other embodiments, anodized aluminum may also be used for the confinement ring 120.

[0046] In one embodiment, the lower section 202 is substantially horizontal and the middle section 206 is substantially vertical, and the upper section 204 is substantially horizontal. In other embodiments, the sections need not be exactly horizontal and vertical and may have light tilting. By way of example, the lower section 202 may have a slight slope between the inner diameter and the outer diameter of the lower section 202. Similarly, the middle section 206 may have a slope between the lower section 202 and the upper section. Examples of varying slope configurations are shown in Figures 9B-9F.

[0047] The lower section 202 has a lower inner diameter 214a and a lower outer diameter 214b. An extension section 217 is disposed proximate to the lower inner diameter 214a. The extension section 217 has a structure that is downwardly extending just below alower outer wall 228 of the lower section 202. The extension section 217 has an extension corner 232 proximate to where the lower section 202 projects downwardly. The extension section 217 has a lower extension surface 216 that faces downward when the confinement ring 120 is installed in the chamber 100. In one embodiment, the lower extension surface 216 may be configured to contact the ground ring (e.g., 116) to facilitate RF return. In some embodiments, the lower extension surface 216 is configured to contact a gasket of the ground ring 116 to provide for improved electrical conduction to ground. The lower section 202 has a lower inner wall 208, which is defined from material of the plurality of fingers 207 formed in the lower section 202. An inner lower-middle edge 224 defines an intersection between the lower section 202 and the middle section 206. An outer lower-middle edge 222 is on the exterior side of the intersection between the lower section 202 and the middle section 206.

[0048] The middle section 206 includes an inner middle wall 210 and an outer middle wall 226, which respectively define the inner and outer surfaces of the plurality of fingers 207 that extend along the middle section 206. As shown, the conduction pathways 240 extend uninterrupted in the space between the plurality of fingers 207 in a region along the lower section 202 and the continuation of the space between the plurality of fingers 207 in a region along the middle section 206. This space forms a slot that is continuous along the lower section 202 and the middle section 206, thus forming the conduction pathways 240. In one embodiment, the portion of the slot in the middle section extends up close to and proximate to the upper section 204, e.g., up to where the outer upper-middle edge 231 and the inner-upper middle edge 233 are disposed. In this configuration, each of the plurality of fingers 207 connect to the upper section 204 between an outer upper section 204a and an inner upper section 204b. In one embodiment, the outer upper section 204a is longer than the inner upper section 204b. In other embodiments, the outer upper section 204a may be equal to or shorter than the inner upper section 204b.

[0049] In this embodiment, middle section 206 connects to the upper section 204 at a radius location B that is inward from the radius location A. By disposing the middle section 206 closer in radius to the center, it is possible to reduce the plasma volume 103. That is, the middle section 206 at radius location B acts to bring the diameter of the vertical part of the middle section 206 inwardly and thus reducing the plasma volume 103. However, reducing the plasma volume 103 with a middle section 206 at radius location B will also reduce the potential conduction out of the lower section 202. If conduction pathways 240 were only present on the lower section 202, and the middle section 206 were placed at location B, instead of location A, the available pathways for conduction would be reduced.To address this possible reduction in conduction pathways 240, the present configuration provides for conduction pathways 240 to also extend along the middle section 206.

[0050] Advantageously, having conduction pathways 240 in both the lower section 202 and the middle section 206 will provide for more efficient conduction of gases out of the plasma volume 103 during processing (compared to when the pathway is formed only on the lower section 202), while still providing for plasma confinement by the plurality of fingers 207 that extend along both the lower section 202 and the middle section 206. The middle section 206 therefore connects to the upper section 204 closer to the inner radius of the upper section 204 (e.g., the inner upper section 204b is shorter in annular diameter than the outer upper section 204a). With this configuration, the upper section 204 will still have enough overall annular diameter to enable the confinement ring to be secured to an upper structure in the chamber 100, when installed. In one embodiment, one or more screws can be used to secure the confinement ring 102 along the outer upper section 204a.

[0051] The upper section 204 has an upper inner diameter 221, with an upper inner step 218, in some embodiments. In some embodiments, the upper inner step 218 may have a different geometry or eliminated entirely. The upper section 204 has an upper outer diameter 220 that defines the outermost diameter of the confinement ring 120. The upper section 204 has an upper top surface 232, which interfaces with an upper structure of the chamber. The upper top surface 232 is then secured to the upper structure for connecting the confinement ring 120 in the chamber 100. In one configuration, the upper structure (not shown) is movable to enable raising and lowering of the confinement ring 120 to allow for inserting and removing of wafers into the chamber 100.

[0052] Figure 3 illustrates a three-dimensional view of a side of the confinement ring 120. The perspective is an upside-down partial view through the slots between the respective plurality of fingers 207. This illustration shows how each finger extends along a region of the lower section 202 and a region of the middle section 206, and the slot that forms each conduction pathway 240 is uninterrupted between the transition that happens between the lower section 202 and the middle section 206. The conduction pathways 240 form a type of grill or grate that allows for a flow of gases out of the plasma volume 103. By way of example, the gases include those used for striking a plasma in the plasma volume to affect an etch of a material disposed on or in the wafer 101. Plasma byproducts that are volatized may also flow and conduct out of the plasma volume 103 to another region of the chamber 100.

[0053] These gases and byproducts, for example, are ultimately removed from the chamber 100 using one or more pumps, e.g., turbo pumps, that evacuate said gases andbyproducts. As mentioned above, the plurality of fingers 207 are configured to provide for efficient conduction of gases out of the plasma volume 103, but at the same time, provide for confinement of ignited plasma within the confines of the plasma volume 103. That is, plasma is not allowed to go unconfined because the plurality of fingers 107 restrain plasma from uncontrollably leaking out side of the confinement ring 120, yet the conduction pathways 240 efficiently allow for gases to flow out of the spaces between the respective plurality of fingers 207.

[0054] In one embodiment, the confinement ring 120 is optimized for dielectric etch logic applications, which use lower power levels. Example lower power levels by range below about 5000 Watts, or below about 2000 Watts. In one example, a lower power level tested was about 1400 Watts, 60 MHz, and pressures of about 15mTorr to about 60mTorr.

[0055] In the embodiments disclosed herein, the plasma volume 103 is reduced because the middle section 206 has a reduced diameter B (e.g., compared to a diameter A, as shown in Fig. 1 A). The reduced plasma volume 103 is more efficient for lower power applications, while still providing efficient conduction via the conduction pathways 240 disposed in the portions of the lower section 202 and the middle section 206. In one example, the conduction pathways 240 provide for conduction up to about 50 sccm / Torr, while still maintaining plasma confinement. In some prior art designs, unconfinement of plasma was found to occur for conductance values in the range of 10 sccm / Torr to about 20 sccm / Torr. Allowing for conductance up to about 50 sccm / Torr without unconfinement is a significant advancement achieved by the design of the confinement ring 120. In one embodiment, providing for conductance up to about 40 sccm / mT is also a significant achievement.

[0056] Therefore, the confinement ring 120 provides for high conduction with a smaller plasma volume 103, which has been shown to provide improved results in low power etch operations. For example, the improved results are exhibited by improved uniformity in etching over the surface of the processed / etched wafer. As mentioned above, one practical application of the present confinement ring 120 is for use logic feature etching. Logic applications in general etch “softer” dielectric materials which require less ion energy to etch. They also have lower aspect ratio requirements (e.g., < 10: 1). Therefore, logic operations require more uniformity and selectivity. In one embodiment, lower power levels, e.g., less than 7000 Watts, or less than 3000 Watts were found to provide good performance characteristics for etching logic features, using the confinement ring 120.

[0057] Figures 4A and 4B illustrate three-dimensional views of the confinement ring 120, in accordance with one embodiment. Figure 4A is a view looking down over theupper section 204, which shows the lower section 202 and the middle section 206 having a plurality of fingers 207 with conduction pathways 240, i.e., slots between respective ones of the plurality of fingers 207. Holes 402 are used to secure the upper section 204 to an upper structure of the chamber 100, when the confinement ring 120 is installed therein. The illustration in Figure 4B is a bottom view of the confinement ring 120. This view shows how each of the plurality of fingers 207 are uninterrupted as they extend along both the lower section 202 and the middle section 206. Further shown in the views of Figures 4A and 4B is the upper inner step 218, the lower inner diameter 214, the upper outer under surface 230, and the upper outer diameter 220.

[0058] Figure 5A provides a top view of the confinement ring 120 with a cut-out view for detail D (shown in Fig. 8 A below). The top view of Figure 5 A shows the conduction pathways 240 disposed between the plurality of fingers 207 of the lower section 202. Figure 5B is a side view that shows the conduction pathways 240 disposed between the plurality of fingers 207 of the middle section 206. As noted above, the plurality of fingers 207 in the lower section 202 and the middle section 206 are continuous and uninterrupted. For example, the space between the fingers 207 remains uninterrupted in the transition between the middle section 206 and lower section 202. Also shown in the side view of Figure 5B is the extension section 217 and the upper section 204.

[0059] Figure 6 illustrates a cross-sectional view of the confinement ring 120, in accordance with one embodiment. The following example dimensions of Figure 6 are provided to illustrate one example configuration of the confinement ring 120. It should be understood that variations in sizes are possible so long as the structural shape of the confinement ring operates to provide high conduction in a low power logic application. Dimension DI is about 20 inches. Dimensions D2 is about 18 inches. Dimension D3 is about 17.5 inches. Dimension D4 is about 17 inches. Dimension D5 is about 16.8 inches. Dimension D6 is about 14.9 inches. Dimension D7 is about 15.4 inches. Detail B in Figure 6 is shown in Figure 7.

[0060] Figure 7 illustrates a more detailed view of the confinement ring 120 cross-section, in accordance with one embodiment. The following example dimensions of Figure 7 are provided to illustrate one example configuration of the confinement ring 120. It should be understood that variations in sizes are possible so long as the structural shape of the confinement ring operates to provide high conduction in a low power logic application. Dimension D8 is about 1.4 inches. Dimension D9 is about 1.3 inches. Dimension D10 is about 1.6 inches. Dimension Dl l is about 0.3 inch. Dimension D12 is about 0.17 inch. Dimension D13 is about .46 inch. Dimension D14 is about .2 inch. In one configuration,certain of the edges of the surfaces are rounded. In other configurations, certain edges may not be rounded and may have shaper profiles. With this in mind, radius R1 is about .025 inch. Radius R2 is about .025 inch. Radius R3 is about .025 inch. Radius R4 is about .025 inch. Radius R5 is about .075 inch. Radius R6 is about .040 inch. Radius R7 is about .025 inch. Radius R8 is about .025 inch. Radius R9 is about .025 inch. Radius R10 is about .025 inch. Radius R11 is about .025 inch. Radius R12 is about .025 inch. Radius R13 is about .030 inch. Radius R14 is about .075 inch.

[0061] Figure 8 A is a magnified view of Detail D, shown in Figure 5 A, in accordance with one embodiment. The following example dimensions of Figure 8 A are provided to illustrate one example configuration of the confinement ring 120. It should be understood that variations in sizes are possible so long as the structural shape of the confinement ring operates to provide high conduction in a low power logic application. Dimension DI 5 is about .110 inch. Dimension DI 5 is the approximate width of one of the slots that define conduction pathways 240 between the plurality of fingers 207. Dimension D16 is a diameter measuring about 15.9 inches. Dimension D17 is a diameter measuring about 17.6 inches. D17 represents the start of the vertical part of the middle section 206 that extends up from the lower section 202 of the confinement ring 120. Dimension D18 is a diameter measuring about 14.9 inches. In one embodiment, the inner diameter ends of the slots that define the conduction pathways 240 have an optional radius R16 that measures about .015 inch.

[0062] Figure 8B illustrates a magnified side view E-E of Figure 5 A, in accordance with one embodiment. The following example dimensions of Figure 8B are provided to illustrate one example configuration of the confinement ring 120. It should be understood that variations in sizes are possible so long as the structural shape of the confinement ring operates to provide high conduction in a low power logic application. Dimension D21 represents an exemplary width of about .110 inch, which corresponds to a slot that forms the spacing of the conduction pathways 240 between respective ones of the fingers 207. In this example, the approximate width of each of the fingers 207 is substantially similar to the width of the slots. In one configuration, each finger 207 is defined to be approximately 1.481 degrees slot to slot, or approximately 0.095 inch for each finger 207 width. Dimension D20 is about 1.05 inches. As shown in Detail F of Figure 8C, the slot may have a slightly flat top with rounded edges having a radius R17 of about .040 inch.

[0063] Figure 9A illustrates an alternate shape of the conduction pathway 240a slots, in accordance with another embodiment. As shown, it is possible to have conductionpathways 240a with a tapered ending as the slot approaches the inner diameter of the slot. For example, the width of the slot near the inner diameter may be wider than the width of the slot near the outer diameter. In this configuration, since erosion wear may occur over time (e.g., slightly more near the inner diameter), the conduction pathways 240a may start with narrow width slots near the inner diameter, and as wear occurs over time, the widths may equalize. In other embodiments, the slot width in the middle section 206 may also be tapered. In some embodiments, the slot in both the lower section 202 and the middle section 206 may have tapered or just one of the lower section 202 or the middle section 206 may be tapered.

[0064] Figures 9B-9E illustrate alternate embodiments where the lower section 202 and / or the middle section 206 have a sloped angle. For example, Figure 9B is shown to have the lower section 202 with a falling slope, i.e., the slope falls from the outer radius to the lower inner radius of the lower section 202. Figure 9C illustrates an embodiment where the slope falls from the inner radius to the lower outer radius of the lower section 202. Figure 9D illustrates an example where the middle section 206 has a slope that slants outward near the upper part of the middle section 206. Figure 9E illustrates an example where the middle section 206 has a slope that slants inward near the upper part of the middle section 206. It should be understood that the sloping of the lower section 202 or the middle section 206 may be combined, e.g., such that both the lower section 202 and the middle section 206 can slope at the same time in any combination of slops shown in Figures 9B-9E. Still further, it should be understood that in some embodiments, the lower section 202, the middle section 206 and the upper section 204 may be formed using multiple parts or annular rings that are assembled together to form the confinement ring 120.

[0065] Figure 9F illustrates another configuration of the confinement ring 120, in accordance with an alternate embodiment. In this illustration, it should be understood that the inside walls of the middle section 206 may have a unique interior curvature at the intersection of the middle section 206 and the lower section 202. By way of example, the curvature may be slight, e.g., as shown by dashed line 902a. Alternatively, the curvature of the surface an be more as shown by dashed lines 902b or 902c, or 902d. In some embodiments, the exterior walls of the lower section 202 and middle section 206 may also have some curvature or rounding 902e. These variations are provided to illustrate the flexibility of the design and how the shapes can vary to provide additional tuning in performance.

[0066] The confinement ring 120 is useful as a component of a capacitively- coupled plasma processing chamber wherein inner surfaces of the confinement ring 120provide an extended plasma confinement zone surrounding a gap between an upper electrode and a lower electrode on which a semiconductor substrate is supported during plasma processing in the chamber. While the confinement ring has been described in detail with reference to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made, and equivalents employed, without departing from the scope of the appended claims.

[0067] Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within their scope and equivalents of the claims. What is claimed is:

Claims

CLAIMS1. A confinement ring, comprising: a lower section extending between a lower inner diameter and a lower outer diameter; an upper section extending between an upper inner diameter and an upper outer diameter; and a middle section that provides a vertical connection between the lower section and the upper section, wherein a lower part of the middle section connects with the lower section proximate to a lower outer diameter and connects with the upper section between an inner upper section and an outer upper section; wherein a plurality of fingers are defined from a portion of the lower section and a portion of the middle section; wherein spacing between respective ones of the plurality of fingers provide conduction pathways through the confinement ring.

2. The confinement ring of claim 1, wherein the spacing between respective ones of the plurality of fingers define an uninterrupted opening between the horizontal lower section and the vertical middle section.

3. The confinement ring of claim 1, wherein an extension section having a downward projection is integral with the lower section, the extension section is proximate to the lower inner diameter.

4. The confinement ring of claim 1, wherein said outer upper section extends radially out from the connection with the middle section; wherein said inner upper section extends radially in from the connection with the middle section.

5. The confinement ring of claim 1, wherein an interface between the middle section and the lower section form an inward L-shape, such that said plurality of fingers retain said inward L-shape.

6. The confinement ring of claim 1, wherein said lower section is substantially horizontal.

7. The confinement ring of claim 1, wherein the plurality of fingers of the confinement ring surround a plasma volume of a plasma processing chamber that is configured to receive the confinement ring.

8. A confinement ring for confining plasma in a semiconductor processing chamber, the confinement ring comprising: a lower section extending between a lower inner diameter and a lower outer diameter;an extension section having a downward projection that is integral with the lower section, the extension section is proximate to the lower inner diameter; a middle section is connected to the lower section proximate to the lower outer diameter; an upper section extending between an upper inner diameter and an upper outer diameter, the middle section connects with the upper section between an inner upper section and an outer upper section, the outer upper section being larger than the inner upper section; wherein a first region of the lower section and a second region of the middle section form an plurality of fingers, and wherein conduction pathways are disposed between respective ones of the plurality of fingers.

9. The confinement ring of claim 8, wherein said conduction pathways extend continuously from along the first region of the lower section to along the second region of the middle section.

10. The confinement ring of claim 8, wherein the conduction pathways form slots between said plurality of fingers, the plurality fingers are arranged radially and are configured to surround an inner region of a plasma volume.

11. The confinement ring of claim 8, wherein the lower section is substantially horizonal, the middle section is substantially vertical, and the upper section is substantially horizontal.

12. The confinement ring of claim 8, wherein the downward projection is oriented in a vertical direction when the confinement ring is installed in the semiconductor processing chamber.

13. The confinement ring of claim 8, wherein each finger of said plurality of fingers is defined by said first region of the lower section and said second region of the middle section, and wherein, said first region of said lower section includes a lower outer wall and a lower inner wall; and said second region of said middle section includes an inner middle wall and an outer middle wall.

14. The confinement ring of claim 8, wherein said outer upper section extends radially away from a connection with the middle section and wherein said inner upper section extends radially in from the connection with the middle section.

15. The confinement ring of claim 8, wherein the conduction pathways are defined from slots between respective ones of the fingers.

16. The confinement ring of claim 15, wherein the conduction pathways between the plurality of fingers define an uninterrupted opening between the first region of the lower section and the second region of the middle section.

17. A confinement ring, comprising: a horizontal lower section extending between a lower inner diameter and a lower outer diameter; an extension section having a downward projection that is integral with the lower section, the extension section is proximate to the lower inner diameter; a vertical middle section is connected to the lower the horizontal lower section proximate to the lower outer diameter; a horizontal upper section extending between an upper inner diameter and an upper outer diameter, the vertical middle section connects with the horizontal upper section between an inner upper section and an outer upper section; wherein a plurality of fingers are defined from a portion of the horizontal lower section and a portion of the vertical middle section, and wherein spacing between respective ones of the plurality of fingers provide conduction pathways through the confinement ring.

18. The confinement ring of claim 17, wherein the outer upper section is radially longer than the inner upper section.

19. The confinement ring of claim 17, wherein the spacing between respective ones of the plurality of fingers define an uninterrupted opening between the horizontal lower section and the vertical middle section.

20. The confinement ring of claim 17, wherein said outer upper section extends radially away from the connection with the horizontal middle section and wherein said inner upper section extends radially in from the connection with the horizontal middle section.

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