Digital-to-analog converter with distributed reference buffers

Abstract

A DAC (25) is disclosed that comprises an impedance network (200) having a plurality of inputs (2051 - 205M). The DAC (25) also comprises a plurality of driver buffers (2101 - 210M), one for each input of the impedance network, each driver buffer (210i) being connected to a dedicated one of the inputs (205i) of the impedance network (200) at an output of the driver buffer (210i) and configured to receive a control signal (ci(t)) at an input of the driver buffer (210i). Furthermore, the DAC (25) comprises a control-signal generation circuit (240) configured to generate the control signals (c1(t) - CM(t)) that are input to the driver buffers (2101 - 210M) in response to a digital input signal (x[n]) of the DAC (25). Moreover, the DAC comprises a plurality of reference buffers (2201 -220K). Each reference buffer (220i) is configured to provide a reference voltage (Vref-i) to a corresponding one of a plurality of disjoint sets (2301-230K) of said driver buffers (2101 - 210M).

Description

[0001] DIGITAL-TO- ANALOG CONVERTER WITH DISTRIBUTED REFERENCE BUFFERS

[0002] Technical field

[0003] The present invention relates to a digital -to-analog converter.

[0004] Background

[0005] Digital-to-analog converters (DACs) are used to convert digital signals into corresponding analog representations. For instance, in many communications applications, such as wireless communications applications, baseband processing is to a large extent performed in the digital domain, whereas the transmitted signals are in the analog domain. DACs are used in such applications in the interface between the digital domain and the analog domain.

[0006] Some existing and emerging communications applications, such as the 5th generation (5G) and 6th generation (6G) cellular communications applications set relatively high demands on the DAC performance, e.g. in terms of sample rate, resolution, linearity, etc. One type of DAC that can be used in such applications is the voltage-mode DAC. A voltage mode DAC can e.g. be implemented using an impedance network which is driven by a number of driver buffers, whose input signals are derived from the digital input signal of the DAC. The impedance network can e.g. be implemented with capacitors, resulting in a capacitive DAC (CD AC), or with resistors, resulting in a resistive DAC (RD AC). An example of the latter is e.g. disclosed in P.THOMSSON, C.S.AGHAMIRI, Master Thesis: ’’Design of a 16 GSps RF Sampling Resistive DAC with on-chip Voltage Regulator", Linkoping University 2021 (in the following referred to as “the Thomsson reference”).

[0007] As requirements continue to become harder to meet, there is a need for circuit solutions that even further improves the performance of DACs.

[0008] Summary

[0009] The inventors have developed a DAC architecture where a plurality of reference buffers are used to provide reference voltages to separate sets of driver buffers. This facilitates an improved performance, e.g. in terms of increased sample rate and / or reduced distortion (e.g. improved spurious-free dynamic range, or SFDR).

[0010] According to a first aspect, there is provided a DAC comprising an impedance network having a plurality of inputs. The DAC comprises a plurality of driver buffers, one for each input of the impedance network. Each driver buffer is connected to a dedicated one of the inputs of the impedance network at an output of the driver buffer and configured to receive a control signal at an input of the driver buffer. Furthermore, the DAC comprises a controlsignal generation circuit configured to generate the control signals that are input to the driver buffers in response to a digital input signal of the DAC, such that an analog output signal corresponding to said digital input signal is generated by the impedance network. Moreover, the DAC comprises a first plurality of reference buffers. Each reference buffer is configured to provide a reference voltage to a corresponding one of a plurality of disjoint sets of said driver buffers.

[0011] According to some embodiments, each set of driver buffers consists of a single driver buffer.

[0012] In some embodiments, the DAC comprises a global control voltage generator circuit configured to generate a common control voltage input to each of the reference buffers. The reference buffers may all have the same circuit topology, and the global control voltage generator circuit may comprise a replica buffer having the same circuit topology as the reference buffers. Furthermore, the global control voltage generator circuit may comprise a differential amplifier configured to receive a global reference voltage at a first input of the differential amplifier. The differential amplifier may be connected to an output of the replica buffer at a second input of the differential amplifier and connected to an input of the replica buffer at an output of the differential amplifier. The global control voltage generator circuit may be configured to generate the common control voltage at the output of the differential amplifier.

[0013] In some embodiments, the DAC comprises a plurality of local control voltage generator circuits. Each local control voltage generator may be configured to generate a dedicated control voltage to a dedicated one of the reference buffers. Each local control voltage generator circuit may comprise a differential amplifier configured to receive a global reference voltage at a first input of the differential amplifier. The differential amplifier may be connected to an output of the dedicated reference buffer at a second input of the differential amplifier, and configured to generate the dedicated control voltage at an output of the differential amplifier.

[0014] For each reference buffer, the DAC may in some embodiments comprise a filter circuit having a first input configured to receive the control voltage, a second input connected to a local ground supply node of the reference buffer and its corresponding set of driver buffers, and an output connected to an input of the reference buffer. The filter circuit may have a low- pass path between its first input and its output, and a high-pass or band-pass path between its second input and its output. According to some embodiments, each reference buffer may be configured to generate the reference voltage relative to a local ground supply node of the reference buffer and its corresponding set of driver buffers.

[0015] According to some embodiments, each input of the impedance network may be a differential input. Each driver buffer may be a differential driver buffer.

[0016] According to some embodiments, each reference buffer may be a push-pull common-drain amplifier.

[0017] The control-signal generation circuit may comprise a plurality of retiming circuits, one for each driver buffer. Each retiming circuit may be configured to provide the control signal for a current sample of the digital input signal of the DAC to a dedicated one of the driver buffers in response to an edge of a sample clock signal.

[0018] The DAC may comprise a second plurality of reference buffers. Each reference buffer of the second plurality of reference buffers may be configured to provide a reference voltage to a corresponding one of a plurality of disjoint sets of said retiming circuits.

[0019] According to some embodiments, each set of retiming circuits consists of a single retiming circuit.

[0020] The impedance network may e.g. be a resistor network, capacitor network, or a hybrid resistor capacitor network.

[0021] According to a second aspect, there is provided an integrated circuit comprising the DAC of the first aspect.

[0022] According to a third aspect, there is provided an electronic apparatus comprising the DAC of the first aspect and / or the integrated circuit of the second aspect. The electronic apparatus may e.g. be a communication apparatus, such as a wireless communication device for a cellular communications system or a base station for a cellular communications system.

[0023] Further embodiments are defined in the dependent claims. It should be emphasized that the term “comprises / comprising” when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

[0024] Brief description of the drawings

[0025] Fig. 1 illustrates a communication environment.

[0026] Fig. 2 is a block diagram of a transceiver circuit,

[0027] Fig. 3 is a block diagram of a known DAC.

[0028] Figs. 4-5 are block diagrams of DACs according to embodiments. Figs. 6-10 illustrate reference-voltage generation.

[0029] Fig. 11 illustrates use of a differential driver buffer.

[0030] Figs. 12-13 are block diagrams of DACs according to embodiments.

[0031] Fig. 14 illustrates reference-voltage generation to re-timing circuits.

[0032] Fig. 15 is a schematic circuit diagram of a push-pull buffer.

[0033] Figs. 16-18 illustrate implementations of impedance networks.

[0034] Fig. 19 schematically illustrates an integrated circuit.

[0035] Detailed description

[0036] Fig. 1 illustrates a communication environment wherein embodiments of the present invention may be employed. A wireless communication device 1, or wireless device 1 for short, of a cellular communications system is in wireless communication with a radio base station 2 of the cellular communications system. The wireless device 1 may be what is generally referred to as a user equipment (UE). The wireless devices 1 is depicted in Fig. 1 as a mobile phone, but may be any kind of device with cellular communication capabilities, such as a tablet or laptop computer, machine-type communication (MTC) device, or similar. Furthermore, a cellular communications system is used as an example throughout this disclosure. However, embodiments of the present invention may be applicable in other types of systems as well, such as but not limited to WiFi systems.

[0037] The radio base station 2 and wireless device 1 are examples of what in this disclosure is generically referred to as communication apparatuses. Embodiments are described below in the context of a communication apparatus in the form of the radio base station 2 or wireless device 1. However, other types of communication apparatuses can be considered as well, such as a WiFi access point or WiFi enabled device.

[0038] Fig. 2 is a block diagram of an embodiment of a transceiver circuit 10, which can be comprised in a communication apparatus, such as the radio base station 2 or the wireless device 1. In the embodiment illustrated in Fig. 2, the transceiver circuit 10 comprises a digital signal processing (DSP) circuit 15. The DSP circuit 15 may e.g. be what is commonly referred to as baseband processor. The DSP circuit 15 may e.g. be configured to perform various digital signal processing tasks, such as one or more of coding, decoding, modulation, demodulation, fast Fourier transform (FFT), inverse FFT (IFFT), mapping, demapping, etc.

[0039] Furthermore, in the embodiment illustrated in Fig. 2, the transceiver circuit 10 comprises a transmitter circuit 20. The transmitter circuit 20 comprises a digital-to-analog converter (DAC) 25. The DAC 25 is connected to the DSP circuit 15 and configured to receive, as an input signal of the DAC 25, a digital representation of a signal to be transmitted from the DSP circuit 15. The DAC 25 is further configured to convert the signal to be transmitted to an analog representation, which is an output signal of the DAC 25. The transmitter circuit 20 also comprises a transmitter (Tx) frontend (FE) circuit 30 connected between the DAC 25 and an antenna 35. The Tx FE circuit 30 is configured to transform the output signal from the DAC 25 to a format suitable for transmission via the antenna 35. This may include operations such as frequency upconversion, filtering, and / or amplification. In some embodiments, the DAC 25 may be configured to generate its output at RF (Radio Frequency), whereby no frequency upconversion is needed in the analog domain. The Tx FE circuit 30 may comprise one or more mixers, filters, and / or amplifiers, such as power amplifiers (PAs), to perform such operations. The design of such Tx FE circuits is, per se, well known to a person skilled in the field of radio transceiver design, and is not discussed herein in any further detail.

[0040] Moreover, in the embodiment illustrated in Fig. 2, the transceiver circuit 10 comprises a receiver circuit 40. The receiver circuit 40 comprises a receiver (Rx) FE circuit 45 connected to the antenna 35. Furthermore, the receiver circuit 40 comprises an ADC 50. The ADC 50 is connected between the Rx FE circuit 45 and the DSP circuit 15. The Rx FE circuit is 45 is configured to transform a signal received via the antenna 35 to a format suitable to be input to the ADC 50. This may include operations such as frequency downconversion, filtering, and / or amplification. The Rx FE circuit 45 may comprise one or more mixers, filters, and / or amplifiers, such as low-noise amplifiers (LNAs), to perform such operations. The design of such Rx FE circuits is, per se, well known to a person skilled in the field of radio transceiver design, and is not discussed herein in any further detail. The ADC 50 is configured to receive its (analog) input signal from the Rx FE circuit, and convert it to a digital representation to generate the digital output signal of the ADC 50. This digital output signal of the ADC 50 is input to the DSP circuit 15 for further digital signal processing. In some embodiments, the ADC 50 may be configured to sample signals at RF, whereby no frequency downconversion is needed in the analog domain.

[0041] Fig. 3 illustrates a DAC implementation used herein as a reference example to compare embodiments of the present disclosure with. A DAC implementation as illustrated in Fig. 3 is e.g. described in the Thomsson reference mentioned in the background section. To facilitate a high sample rate, data is arriving in a number of parallel samples at a lower sample rate. In the Thomsson reference, 16 parallel samples at 1 GSps (Giga Samples per Second) is used. The data is then decoded and serialized in the data decoder and serializer 100 up to the higher sample rate, i.e. the number of parallel samples times the lower sample rate. In the Thomsson reference, the higher sample rate is 16 GSps. The decoded data is then sent to the waveform generator 110 which is synchronized by the clock buffer 130. The waveform generator is then driving the resistive network 120 which is connected to the load resistor RL. Each of the three blocks has its own LDO supply voltage regulator labeled 140, 150, and 160 in Fig. 3.

[0042] Fig. 4 illustrates an embodiment of the DAC 25. It comprises an impedance network 200 having a plurality of inputs 2051 - 205M. Different embodiments of the impedance network 200 are described in more detail further down, e.g. in the context of Figs. 16-18. It should be noted that the reference voltage generation and distribution described in this disclosure is applicable regardless of what type of impedance network 200 is used.

[0043] Furthermore, the embodiment of the DAC 25 illustrated in Fig. 4 comprises a plurality of driver buffers 210i - 210M, one for each input 205I-205M of the impedance network 200. As illustrated in Fig. 4, each driver buffer 210i is connected to a dedicated one of the inputs 205i of the impedance network 200 at an output of the driver buffer 210i. Furthermore, each driver buffer 210i is configured to receive a control signal Ci(t) at an input of the driver buffer 21 Oi.

[0044] The embodiment of the DAC 25 illustrated in Fig. 4 further comprises a control-signal generation circuit 240 configured to generate the control signals ci(t) - CM(t) that are input to the driver buffers 210i - 210M in response to a digital input signal x[n] of the DAC 25. The control-signal generation circuit 240 is configured to generate the control signals ci(t) - CM(t) such that an analog output signal y(t) corresponding to said digital input signal x[n] is generated by the impedance network 200. Each control signal Ci(t) may correspond to a control bit with a certain bit weight and could, ideally, be viewed as a piecewise constant signal with a value corresponding to a ‘0’ or a ‘ 1’ updated at a sample rate of the DAC. However, in practical implementations, such piecewise constant signals cannot be generated due to an inherent limited bandwidth in the circuitry generating the control signals ci(t) - CM(t). In particular, this becomes evident at higher sample rates, such as in the GHz range, where the waveforms for the control signals m(t) - CM(t) may have the qualitative appearance of amplitude-continuous and time-continuous analog signals rather than distinct ‘l’s and ‘0’s. What the different bit weights are depends on what type of digital coding is used internally in the DAC 25. For instance, the DAC 25 may be binary weighted, thermometer coded, or segmented. This also impacts the topology and / or component values to be used for the impedance network. Such deliberations are well understood by a person skilled in the art of designing DACs using impedance networks and are not elaborated here in any further detail. Furthermore, the embodiment of the DAC 25 illustrated in Fig. 4 comprises a first plurality of reference buffers 220I-220K. Each reference buffer 220i is configured to provide a reference voltage Vref-i to a corresponding one of a plurality of disjoint sets 230I-230K of said driver buffers 210i - 210M. With the notation used in Fig. 4, the reference buffer 220i is configured to provide the reference voltage Vref-i to the set 230i. For example, in Fig. 4, the reference buffer 220i is configured to provide the reference voltage Vref-i to the set 230i, comprising the driver buffers 210i-210g, the reference buffer 2202 is configured to provide the reference voltage Vref-2 to the set 2302, comprising the driver buffers 21 Oh-210k, and the reference buffer 220K is configured to provide the reference voltage Vref-K to the set 230K, comprising the driver buffers 2101-210M. The reference voltages may, in some embodiments, be provided as a supply voltage to the respective driver buffers, e.g. as described below in connection with Fig. 11. The reference voltage may have nominally the same value as a global supply voltage of the DAC 25 in some embodiments, but may also in some embodiments be tuned or controlled to other value(s). As illustrated in Fig. 4, each reference buffer 220i may have an input configured to receive a control voltage Vc-i. Examples on how such control voltages Vc-i may be generated are described further down in this detailed description.

[0045] Referring back to the reference example illustrated in Fig. 3, driver buffers similar to the driver buffers 21 Oi would be present at the output of the waveform generator 110, together with clocked flip-flops (DFFs) that generate the input signals to these driver buffers. In the reference example, all these driver buffers and DFFs are supplied with a supply voltage / reference voltage from the single LDO 150. The inventors have realized that, by instead suppling the disjoint sets 230I-230K of said driver buffers 210i - 210M with reference voltages from separate reference buffers, as in embodiments of the present disclosure, an improved performance can be achieved. For instance, the crosstalk between driver buffers and signal-dependent ripple on supply and reference lines can be significantly reduced, which in turn facilitates an improved spurious-free dynamic range (SFDR), e.g. due to reduced amplitude modulation and / or signal dependent timing variations caused by reference-voltage variations. Furthermore, individual calibration of the reference voltage supplied to each subset may be used in some embodiments. Thereby, the relative weights of the different subsets can be fine-tuned. Moreover, since each reference buffer only supplies a subset of the driver buffers, shorter settling times are achievable which in turn facilitates higher sampling rates compared with the reference example where a single LDO 150 is used to supply the whole waveform generator block 110. For instance, the size of decoupling capacitors can be reduced, or in some embodiments the use of at least some decoupling capacitors can be eliminated.

[0046] In some embodiments, each set 230I-230K of driver buffers 210i - 210M consists of a single driver buffer 210i. In other words, in such embodiments, each driver buffer 210i has its own dedicated reference buffer 220i. This is illustrated in Fig. 5, wherein each subset 230i consists of the single driver buffer 210i which is supplied the reference voltage Vref-i by the reference buffer 220i, where i runs from 1 to M.

[0047] In other embodiments, there may be several driver buffers in each subset 230I-K (or at least in some of them), e.g. as illustrated in Fig. 4 earlier. For instance, in a segmented architecture, where bits in the digital input x[n] (which may be binary coded) are divided into segments of “neighboring” bits and each such segment of bits is encoded into a thermometer code, each such segment may have a corresponding subset 230j of driver buffers 210i supplied with a reference voltage Vref-j from a common reference buffer 220j. A different index j is used here for the subset 230j and reference buffer 220j than the index i used for the driver buffers 210i since there is not a one-to-one correspondence between each reference buffer and a single driver buffer. In text describing embodiments where each driver buffer 210i has its own dedicated reference buffer 220i, or the circuits are not described in combination, the index i is used as a general index in the text. This may, for instance, facilitate fine tuning the relative weights between the different segments for calibration purposes. As a mere example, for a 12- bit input x[n], one segment (“MSB segment”) may be the four most significant bits (MSBs), another segment (“LSB segment”) may be the four least significant bits (LSBs), and yet another segment may be the four intermediate bits in between the LSB segment and the MSB segment. Other ways of partitioning segments in a DAC are possible as is well understood by a person skilled in the art of DAC design.

[0048] In some embodiments, the DAC 25 comprises a global control voltage generator circuit configured to generate a common control voltage Vc input to each of the reference buffers 220I-220K. An example of this is shown in Fig. 6. In Fig. 6, the reference buffers 220I-220K may, for instance, all have the same circuit topology. For instance, they may all be identically designed. Alternatively, some of the reference buffers 220I-220K may be designed as scaled versions of another one of the reference buffers 220I-220K, e.g. if they need different currentdriving capability.

[0049] Furthermore, in Fig. 6, the global control voltage generator circuit comprises a buffer 310. The buffer 310 may have the same circuit topology as the reference buffers 220I-220K. Therefore, it is in the following referred to as “the replica buffer 310”. Furthermore, in Fig. 6, the global control voltage generator circuit comprises a differential amplifier 300. The differential amplifier 300 is configured to receive a global reference voltage Vref at a first input of the differential amplifier 300. Moreover, in Fig. 6, the differential amplifier 300 is connected to an output of the replica buffer 310 at a second input of the differential amplifier 300. Also, in Fig. 6, the differential amplifier 300 is connected to an input of the replica buffer 310 at an output of the differential amplifier 300. In Fig. 6, the global control voltage generator circuit is configured to generate the common control voltage Vc at the output of the differential amplifier 300. In Fig. 6, it has been assumed that both the differential amplifier 300 and the replica buffer has a positive gain, whereby the “first input” is the positive input of the differential amplifier 300 and the “second input” is the negative input of the differential amplifier 300. A skilled person would be capable of selecting the correct first and second inputs, depending on circumstances, in order to provide a functioning circuit.

[0050] With the feedback configuration shown in Fig. 6, the global control voltage generator circuit generates a control voltage Vc such that the output voltage of the replica buffer is ideally (e.g. assuming very high, or “infinite”, gain and no input offset error in the differential amplifier 300) driven to be equal to the global reference voltage Vref. Provided that the reference drivers 220I-220K are relatively well matched (e.g. in terms of manufacturing inaccuracies) with the replica buffer 310, their generated reference voltages Vref-i-Vref-K will also be driven to be close to the global reference voltage Vref. Static and dynamic load currents consumed by the driver buffers 210I-M will to some extent influence the reference voltages Vref-i-Vref-K generated by the reference drivers 2201 -220K and cause them to fluctuate and deviate from ideal values. A skilled person would be capable of dimensioning the currentdriving capability of the reference buffers 220I-220K to keep such deviations and / or fluctuations within tolerable bounds for a given application. It can also be noted that, provided that the replica buffer 310 experiences approximately the same temperature variations as the reference buffers 220I-220K, the global control voltage generator circuit would generate the control voltage Vc such that these temperature variations are at least partially counteracted.

[0051] It should be noted that, in some embodiments, the DAC 25 may instead comprise a global control -current generator circuit that distributes copies of a global control current to each reference buffer 220i. In such embodiments, the reference buffers 220i may e.g. be implemented as transimpedance amplifiers.

[0052] In some embodiment, the DAC 25 comprises a plurality of local control voltage generator circuits. Each local control voltage generator may be configured to generate a dedicated control voltage to a dedicated one of the reference buffers 220i. Examples of such embodiments are illustrated in Figs. 7-8.

[0053] In the embodiment illustrated in Fig. 7, each local control voltage generator circuit comprises a differential amplifier 300i configured to receive a global reference voltage Vref at a first input of the differential amplifier 300i. Furthermore, in Fig. 7, each differential amplifier 300i is connected to an output of the dedicated reference buffer 220i at a second input of the differential amplifier 300i. Moreover, in Fig. 7, each differential amplifier 300i is configured to generate the dedicated control voltage Vc-i at an output of the differential amplifier 300i.

[0054] In the embodiment illustrated in Fig. 8, each local control voltage generator circuit is implemented similarly to the embodiment of the global control voltage generator circuit shown in Fig. 6. As in Fig. 7, each local control voltage generator circuit comprises a differential amplifier 300i configured to receive a global reference voltage Vref at a first input of the differential amplifier 300i. Moreover, in Fig. 8, each local control voltage generator circuit comprises a buffer 310i. The buffer 310i may have the same circuit topology as the dedicated reference buffer 220i. Therefore, it is in the following referred to as “the local replica buffer 310 ”. In Fig. 8, each differential amplifier 300i is connected to an output of the local replica buffer 310i at a second input of the differential amplifier 300i. Also, in Fig. 8, the differential amplifier 300i is connected to an input of the replica buffer 310i at an output of the differential amplifier 300i. In the embodiment illustrated in Fig. 8, each local control voltage generator circuit is configured to generate the dedicated control voltage Vc-i at the output of the differential amplifier 300i.

[0055] It should be noted that, in some embodiments, the DAC 25 may instead comprise a plurality of local control -current generator circuit that each is configured to generate a local control current to respective reference buffer 220i. Again, in such embodiments, the reference buffers 220i may e.g. be implemented as transimpedance amplifiers.

[0056] For the embodiments illustrated in Figs. 6-8, the feedforward nature of the reference buffers 220i facilitates relatively high settling speed. Furthermore, relatively low and constant output impedance of the reference buffers 220i can be achieved even at relatively high frequencies. This facilitates relatively low ripple in the frequency response of the DAC. The embodiment illustrated in Fig. 6 has the additional benefit of a relatively small layout footprint and lower power consumption due to only a single copy of the error amplifier 300 and replica buffer 310. Using a dedicated control loop for each reference buffer 220i as in Figs. 7 and 8 has the benefit that precise reference voltages, and hence, bit weights can be achieved. Bit weights will not drift with, for example, temperature, and temperature gradients, or at least such drift can be kept relatively low. For the embodiment illustrated in Fig. 8, this is particularly true if each local replica buffer 300i is located in relatively close proximity with the corresponding reference buffer 220i.

[0057] The embodiment of Fig. 7, which uses the output of the actual reference buffer 220i for feedback, has the advantage that a higher precision may be obtained compared with Figs. 6 and 8 where matching between the reference buffer 220i and the replica buffer 300 or 300i may influence the achievable precision. On the other hand, the feedback configuration of the reference buffers 220i in Fig. 7 may limit the achievable settling speed compared with the embodiments in Figs. 6 and 8.

[0058] According to some embodiments, the DAC 25 may comprise a filter circuit 350i for each reference buffer 220i. An example is illustrated in Fig. 9. The filter circuit 350i in Fig. 9 has a first input configured to receive the control voltage Vc-i (e.g. in embodiments using a local control voltage generator circuit as discussed above) or Vc (e.g. in embodiments using a global control voltage generator circuit as also discussed above). Furthermore, the filter circuit 350i in Fig. 9 has a second input connected to a local ground supply node, labeled local gnd, of the reference buffer 220i and its corresponding set 230i of driver buffers. Moreover, in Fig. 9, an output of the filter circuit 350i is connected to an input of the reference buffer 220i.

[0059] Fig. 9 also illustrates a global ground supply node, labeled global gnd, which all local ground supply nodes for the different reference buffers 220i are connected to via a ground distribution network. This ground distribution network does not have a zero impedance, but will have a certain non-zero finite impedance, modeled in Fig. 9 with a resistance Rgnd-i. The actual voltages in the local ground supply nodes relative to the global ground will fluctuate over time depending on the currents in the ground distribution network. To counteract these fluctuations, the filter circuit 350i may have a low-pass path between its first input and its output, and a high-pass or band-pass path between its second input and its output. The low- pass path may help suppress fluctuations in Vc-i. At the same time, the high-pass or band-pass path will let fluctuations in the voltage at the local ground-supply node pass through to the output of the reference buffer 220i, and thereby see to that the difference between Vref-i and the voltage at local ground-supply node is kept relatively stable.

[0060] More generally speaking, it can be beneficial to design the circuitry in the DAC 25 in such a way that each reference buffer 220i is configured to generate the reference voltage Vref-i relative to a local ground supply node of the reference buffer 220i and its corresponding set 230i of driver buffers. This is advantageous because the local ground supply node functions as a negative reference to the driver buffer 210i, which forms a bit weight proportional to the difference between Vref-i and the local ground supply. Thus, if the voltage ripple on Vref-i exactly follows (nominally with unity gain and zero phase) the ripple on the local ground supply the generated bit weight corresponding to Ci(t) would remain constant.

[0061] Fig. 10 illustrates an example of how the filter circuit 350i can be implemented in some embodiments. In Fig 10, the filter circuit 350i comprises a resistor Ri connected between the first input and the output of the filter circuit 350i (i.e. between the control voltage Vc-i or Vc and the input of the reference buffer 220i), and a capacitor Ci connected between the second input and the output of the filter circuit 350i (i.e. between the local ground and the input of the reference buffer 220i). Other types of implementations are possible as well.

[0062] It should be noted that Figs. 9 and 10 illustrate the case with a single driver buffer 210i per reference buffer 220i, but that the same types of solutions are applicable to embodiments where more than one driver buffer share the same reference buffer (e.g. as in Fig. 4).

[0063] According to some embodiments, the driver buffers 210i may be implemented with inverters, for instance as CMOS inverters. The inverters may be connected to receive the reference voltage generated by the corresponding reference buffer 220i (or 220j) as a positive supply voltage (in the case of a regular CMOS inverter, on the source terminal of the PMOS transistor). Furthermore, in some embodiments, the inverters may be connected to the above- mentioned local ground-supply nodes with their ground terminals (in the case of a regular CMOS inverter, the source terminal of the NMOS transistor).

[0064] In some embodiments, each input 205i of the impedance network 200 is a differential input. In such embodiments, each driver buffer 210i may be a differential, or pseudo differential, driver buffer. A (pseudo) differential driver buffer 210i may e.g. be implemented with a pair of single-ended buffers. Each single-ended buffer may e.g. be implemented with an inverter as discussed above. Fig. 11 illustrates an example of such a (pseudo) differential driver buffer 210i. Here, the control signal Ci(t) is a differential signal with a positive and a negative signal component. In Fig. 11, one of the inverters in the differential driver buffer 210i is configured to receive the positive signal component of Ci(t) at its input, and the other inverter is configured to receive the negative signal component of Ci(t) at its input. Furthermore, the outputs of the inverters are connected to respective terminals of the differential input 205i of the impedance network. Fig. 11 also illustrates how the inverters may be connected to receive the reference voltage Vref-i generated by the corresponding reference buffer 220i as a positive supply voltage, and also how the inverters may be connected to the local ground-supply node with their ground terminals as discussed above.

[0065] It should be noted that Fig. 11 illustrates the case with a single driver buffer 210i per reference buffer 220i (i.e. the reference voltage to the driver buffer 210i is labeled Vref-i), but that the same type of solution is applicable to embodiments where more than one driver buffer share the same reference buffer (e.g. as in Fig. 4).

[0066] It should also be noted that other types of implementations of the driver buffers may be applied as well.

[0067] According to some embodiments of the DAC 25, the control-signal generation circuit 240 comprises a plurality of retiming circuits rti, one for each driver buffer. Each retiming circuit rti may be configured to provide the control signal Ci(t) for a current sample of the digital input signal x[n] of the DAC 25 to a dedicated one of the driver buffers 210i in response to an edge (e.g. rising or falling edge) of a sample clock signal elk. An example of this is illustrated in Fig. 12. In Fig. 12, the input sample x[n] is represented internally in the control-signal generation circuit 240 with a word of bits Ci[n] . The word may e.g. have a binary -weighted representation, a thermometer coded representation, a segmented representation, or a multisegmented representation. Such representations are well known by a person skilled in the art of DAC design. Other representations may be used as well. The retiming circuit rti may be connected to receive the bit Ci[n] at its input. The internal voltage waveforms representing the bits Ci[n] may be skewed in time, e.g. due to finite bandwidth and internal delays in circuitry and electrical connections within the DAC 25 (e.g. within the control-signal generation circuit 240). The retiming circuits rti can be used to reduce such skew in the corresponding control signals Ci(t) that enter the driver buffers 210i. The retiming circuits rti may e.g. be implemented with D flip-flops or similar edge-triggered circuits.

[0068] According to some embodiments, each retiming circuit rti may be connected to the same reference buffer as the corresponding driver buffer 210i. That is, in these embodiments, the retiming circuit rti is configured to receive the same reference voltage as the corresponding driver buffer 210i. The retiming circuit rti may e.g. be connected to receive the reference voltage as a positive supply voltage at a supply-voltage input of the retiming circuit rti. Furthermore, in some embodiments, each retiming circuit rti may be connected to the same local ground supply node as the corresponding driver buffer 210i.

[0069] In addition to the retiming circuits rti, the control-signal generation circuit 240 may comprise additional circuitry, for instance corresponding to the data decoder and serializer circuit 100 of the reference example illustrated in Fig. 3. Fig. 13 illustrates the case with a single driver buffer 210i and a single retiming circuit rti per reference buffer 220i (i.e. the reference voltage to the driver buffer 210i and retiming circuit rti is labeled Vref-i), but that the same type of solution is applicable to embodiments where more than one driver buffer and retiming circuit share the same reference buffer (e.g. as in Fig. 4).

[0070] According to other embodiments, the retiming circuits rti may have their own reference buffers separate from the reference buffers 220i. The DAC 25 may comprise a second plurality of reference buffers 420I-420L as illustrated in Fig. 14. Each reference buffer 420j of the second plurality of reference buffers 420I-420L may be configured to provide a reference voltage to a corresponding one of a plurality of disjoint sets 430I-430L of said retiming circuits rti in a similar way as described above for the driver buffers 220i. This is illustrated in Fig. 14.

[0071] Similar to the description above relating to the disjoint sets 230I-230K of driver buffers 220i, each set 430i of retiming circuits rti may consist of a single retiming circuit rti in some embodiments.

[0072] In other embodiments, there may be several retiming circuits rti in each subset 430I-430L (or at least in some of them).

[0073] The inventors have realized that the reference buffers 220i can be efficiently implemented as a push-pull common-drain amplifier. An example of a reference buffer 220i is illustrated in Fig. 15. NMOS transistors Ml and M3 have their drain terminals connected to a local supplyvoltage node (local VDD). The gate terminals of Ml and M3 are connected to the input of the reference buffer 200i. This is indicated in Fig. 15 by having the control voltage Vc-i supplied to the gate terminals of Ml and M3. It should be noted that in some embodiments, there may be an intervening component, such as the filter circuit 350i connected in between the gate terminals of Ml and M3 and the control voltage Vc-i. The source terminal of Ml is connected to the output of the reference buffer 220i. A PMOS transistor M2 has its source connected to the output of the reference buffer 220i and its drain terminal connected to a local groundsupply node (local gnd). A diode-connected PMOS transistor M4 has its source terminal connected to the source terminal of M3 and its gate and drain terminals connected to the gate terminal of M2. M4 is biased with a DC drain current by the PMOS transistor M5 that has its source terminal connected to the drain terminal of M4, its drain terminal connected to the local ground supply node. M5 is in a current-mirror configuration with a diode-connected PMOS transistor M7. M7 has its gate and drain terminals connected to the gate terminal of M5 and a bias current source Ibias is connected between the drain terminal of M7 and the local ground supply node. As indicated in Fig. 15, a decoupling capacitor Cbias may be connected between the gate terminals of M5 and M7 and the local ground supply node. A further diode- connected PMOS transistor M6 has its gate and drain terminals connected to the source terminal of M7 and its source terminal connected to the source terminals of M3 and M4. M6 thereby provides that M7 and M5 undergo approximately the same source-voltage variations. The configuration of transistors M3-M7 effectively provides a suitably level-shifted version of the input voltage of the reference buffer 220i to the gate terminal of M2, such that Ml and M2 together operates in a push-pull configuration.

[0074] The circuit in Fig. 15 is only an example, and the reference buffer 220i may be implemented in many different ways, such as but not limited to a differential amplifier connected in a source-follower configuration or as a common-drain amplifier implemented in a different way than in Fig. 15, e.g. without the push-pull configuration.

[0075] According to some embodiments, the impedance network 200 may be a resistor network. Thus, the DAC 25 may be what is often referred to as a RD AC. An example of this is illustrated in Fig. 16. In Fig. 16, the load impedance ZL is a load resistor RL. Furthermore, in Fig. 16, a differential structure is used where each input 205i of the resistor network 200 has a positive and a negative terminal. Between each such positive terminal and one of the terminals of the load resistor RL, there is a resistor Ri connected. Similarly, between each such negative terminal and the other one of the terminals of the load resistor RL, there is also a resistor Ri connected. The resistance of the resistor Ri is selected in dependence of the bit weight of the corresponding bit Ci[n] . The design and dimensioning of such resistor networks 200 are well known to persons skilled in the art of DAC design and is not further described herein. Furthermore, other types of resistor networks, such as R-2R ladder networks and combinations of R-2R ladder networks and the type of network shown in Fig. 16, may also be used in some embodiments of the present invention, as would be readily understood by a person skilled in the art of DAC design. Embodiments of the present invention are not limited to any particular topology of the resistor network 200.

[0076] According to some embodiments, the impedance network 200 may be a capacitor network. Thus, the DAC 25 may be what is often referred to as a CD AC. An example of this is illustrated in Fig. 17. In Fig. 17, the load impedance ZL is a load capacitor CL. Furthermore, also in Fig. 17, a differential structure is used where each input 205i of the capacitor network 200 has a positive and a negative terminal. Between each such positive terminal and one of the terminals of the load capacitor CL, there is a capacitor Ci connected. Similarly, between each such negative terminal and the other one of the terminals of the load capacitor CL, there is also a capacitor Ci connected. The capacitance of the capacitor Ci is selected in dependence of the bit weight of the corresponding bit Ci[n] . The design and dimensioning of such capacitor networks 200 are well known to persons skilled in the art of DAC design and is not further described herein. Furthermore, other types of capacitor networks, such as C-2C ladder networks and combinations of C-2C ladder networks and the type of network shown in Fig. 17, may also be used in some embodiments of the present invention, as would be readily understood by a person skilled in the art of DAC design. Embodiments of the present invention are not limited to any particular topology of the capacitor network 200.

[0077] According to some embodiments, the impedance network 200 is a hybrid resistor capacitor network. An example of this is illustrated in Fig. 18, which shows a hybrid of the circuit in Fig. 16 and the circuit in Fig. 17. The load impedance ZL is a parallel connection of a load resistor RL and a load capacitor CL. Furthermore, between each positive terminal of the inputs 205i and one of the terminals of the load impedance ZL = RL / / CL, there is a capacitor Ci connected in parallel with a resistor Ri. Similarly, between each negative terminal of the inputs 205i and the other one of the terminals of the load impedance ZL = RL / / CL, there is also a capacitor Ci connected in parallel with a resistor Ri. Variations of the hybrid resistor capacitor network similar to those described for the resistor network and the capacitor network are possible, which would be readily understood by a person skilled in the art of DAC design. Embodiments of the present invention are not limited to any particular topology of the hybrid resistor capacitor network 200.

[0078] Embodiments of the DAC 25 described herein are well suited for integration on an integrated circuit (IC). This is schematically illustrated in Fig. 19, showing an IC 500 comprising the DAC 25. For instance, the IC 500 may comprise the transceiver circuit 10 (Fig. 2) or parts thereof including the DAC 25.

[0079] The disclosure above refers to specific embodiments. However, other embodiments than the above described are possible within the scope of the invention. For example, the DAC 25 may be used in other types of electronic apparatuses than communication apparatuses. Other types of load impedances than those indicated in Figs. 16-18 may be used in some embodiments. The different features and steps of the embodiments may be combined in other combinations than those described.

Claims

CLAIMS1. A digital-to-analog converter, DAC, (25) comprising: an impedance network (200) having a plurality of inputs (2051 - 205M); a plurality of driver buffers (210i - 210M), one for each input of the impedance network, each driver buffer (210i) being connected to a dedicated one of the inputs (205i) of the impedance network (200) at an output of the driver buffer (210i) and configured to receive a control signal (ci(t)) at an input of the driver buffer (21 Oi); a control-signal generation circuit (240) configured to generate the control signals (ci(t) - CM(t)) that are input to the driver buffers (210i - 210M) in response to a digital input signal (x[n]) of the DAC (25) such that an analog output signal (y(t)) corresponding to said digital input signal (x[n]) is generated by the impedance network (200); and a first plurality of reference buffers (220I-220K), each reference buffer (220i) being configured to provide a reference voltage (Vref-i) to a corresponding one of a plurality of disjoint sets (230I-230K) of said driver buffers (210i - 210M).

2. The DAC (25) of claim 1, wherein each set (230I-230K) of driver buffers (210i - 210M) consists of a single driver buffer (210i).

3. The DAC (25) of any preceding claim, comprising a global control voltage generator circuit configured to generate a common control voltage (Vc) input to each of the reference buffers (220I-220K).

4. The DAC (25) of claim 3, wherein the reference buffers (220I-220K), all have the same circuit topology; the global control voltage generator circuit comprises:- a replica buffer (310) having the same circuit topology as the reference buffers (220i- 220K); and- a differential amplifier (300) configured to receive a global reference voltage (Vref) at a first input of the differential amplifier (300), connected to an output of the replica buffer (310) at a second input of the differential amplifier (300), and connected to an input of the replica buffer (310) at an output of the differential amplifier (300); and the global control voltage generator circuit is configured to generate the common control voltage (Vc) at the output of the differential amplifier (300).

5. The DAC (25) of claim 1 or 2, comprising a plurality of local control voltage generator circuits, each local control voltage generator configured to generate a dedicated control voltage to a dedicated one of the reference buffers.

6. The DAC (25) of claim 5, wherein each local control voltage generator circuit comprises a differential amplifier (300i) configured to receive a global reference voltage (Vref) at a first input of the differential amplifier (300i), connected to an output of the dedicated reference buffer (220i) at a second input of the differential amplifier (300i), and configured to generate the dedicated control voltage (Vc-i) at an output of the differential amplifier (300i).

7. The DAC (25) of any one of the claims 3-6, wherein, for each reference buffer (220i), the DAC comprises a filter circuit (350i) having a first input configured to receive the control voltage (Vc, Vci); a second input connected to a local ground supply node (local gnd) of the reference buffer (220i) and its corresponding set (230i) of driver buffers; and an output connected to an input of the reference buffer (220i); wherein the filter circuit (350i) has a low-pass path between its first input and its output, and a high- pass or band-pass path between its second input and its output.

8. The DAC (25) of any preceding claim, wherein each reference buffer (220i) is configured to generate the reference voltage (Vref-i) relative to a local ground supply node (local gnd) of the reference buffer (220i) and its corresponding set (230i) of driver buffers.

9. The DAC (25) of any preceding claim, wherein each input (205i) of the impedance network (200) is a differential input, and each driver buffer (210i) is a differential driver buffer.

10. The DAC (25) of any preceding claim, wherein each reference buffer (220i) is a push- pull common-drain amplifier.

11. The DAC (25) of any preceding claim, wherein the control-signal generation circuit (240) comprises: a plurality of retiming circuits (rti), one for each driver buffer, each retiming circuit (rti) being configured to provide the control signal (ci(t)) for a current sample of the digital input signal (x[n]) of the DAC (25) to a dedicated one of the driver buffers (210i) in response to an edge of a sample clock signal (elk).

12. The DAC (25) of claim 11, comprising a second plurality of reference buffers (420I-420L), each reference buffer (420j) of the second plurality of reference buffers (420I-420L) being configured to provide a reference voltage to a corresponding one of a plurality of disjoint sets (430I-430L) of said retiming circuits.

13. The DAC (25) of claim 12, wherein each set (430i) of retiming circuits (rti) consists of a single retiming circuit (rti).

14. The DAC (25) of any preceding claim, wherein the impedance network (200) is a resistor network.

15. The DAC (25) of any one of the claims 1-13, wherein the impedance network (200) is a capacitor network.

16. The DAC (25) of any one of the claims 1-13, wherein the impedance network (200) is a hybrid resistor capacitor network.

17. An integrated circuit (500) comprising the DAC (25) of any preceding claim.

18. An electronic apparatus (1, 2) comprising the DAC (25) of any one of the claims 1 - 16 or the integrated circuit according (500) to claim 17.

19. The electronic apparatus (1,2) of claim 18, wherein the electronic apparatus is a communication apparatus.

20. The electronic apparatus (1) of claim 19, wherein the communication apparatus is a wireless communication device for a cellular communications system.

21. The electronic apparatus (2) of claim 19, wherein the communication apparatus is a base station for a cellular communications system.

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