Fast gating circuit for a photon detector and improved circuit arrangement comprising the same

Abstract

A gating circuit for generating a voltage gating signal for controlling on / off operation of a photon detector, said photon detector having a superconducting sensing element for detecting photons and one input / output configured to both input the voltage gating signal to the superconducting sensing element and output a readout signal from said superconducting sensing element, said gating circuit comprising a signal generator for generating a first periodic signal, said gating circuit being characterised in that it further comprises a gate shaping circuit configured to shape the first periodic signal to obtain a periodic voltage gating signal having during each period a transient pulse followed by a plateau.

Description

[0001] improved gating speed, and improved circuit arrangements comprising the same with an improved readout signal. More specifically the invention is dedicated to improving the speed gating for SNSPDs (Superconducting Nanowire Single Photon detectors), and / or their readout signal accuracy.

[0002] BACKGROUND

[0003] In the current information age, our lives rely on the creation, distribution, and detection of short light pulses forming the Internet. This demand for high data throughput has pushed the speed of laser modulators and detectors close to the Ips time limit. However, to reach these speeds, current telecom detectors require at least a thousand photons per pulse. The number of photons per pulse has been pushed to the physical limit of a single photon, while preserving a good time response.

[0004] To that end, SNSPDs were developed to detect one single photon, more than a thousand times more sensitive than the best telecom detectors available today, while maintaining a time resolution on the order of 20 ps full width at half maximum. However, the best superconducting detectors cannot operate faster than several tens of MHz at telecom wavelength while maintaining their full efficiency. Figure 1 illustrates the principle behind a superconducting nanowire single photon detector 20 (SNSPD). In such detectors, single photons are counted with extremely high sensitivity by detecting the transition from the superconducting to resistive state of a nanowire 21. A SNSPD detector is constituted by a thin film of superconducting material shaped into a meandering nanowire 21 through nanofabrication processes. This pattern enables covering a large surface area, collecting the whole output of an optical fiber 200, while constituting a single path for the current. The detectors are operated at low temperatures such that the nanowire is superconducting (e.g. at 2.5 Kelvin) and a constant gating / bias current below the critical current of the superconductor is applied to the device. The nanoscale cross section gives the photon detectors extremely high sensitivity and temporal capabilities upon absorption of just a single photon. Once a single photon is absorbed in the meandering nano wire 21, superconductivity is locally broken. As a result, a voltage pulse is created. After the photon is absorbed, superconductivity recovers in the nanowire within a short time and the SNSPD is ready to detect the next photon. A cryogenic amplifier 22 may further be present in between the nanowire and an input / output I / O for receiving / transmitting a signal 5. Typically, an SNSPD 20 is connected, as illustrated in Figure 2, to a voltage square wave generator 11 and to readout electronics 30 via a tee element 40. The tee connection 40 ensures a biased three- way transmission between the square wave generator 11, the SNSPD 20, and the readout electronics 40. A tee element 40 is typically a resistor network for interconnecting three electrical potentials. The SNSPD 20 comprises a single input / output I / O which is suitable for both receiving a voltage gating signal 4 from the voltage square wave generator 11, the voltage gating signal being such as to drive the superconducting sensing element 21 (nanowire) on and off, and for generating a readout signal 6 to readout electronics 30 for detecting photons impinging on the photon detector. Signal 5 at the single input / output I / O of the SNSPD transmission is thus both affected by the voltage gating signal 4 from the voltage square wave generator 11 to the SNSPD 20 and by the response from the SNSPD 20 to be output to the readout electronics 30. The three-way transmission further implies that the readout signal 6 to be output to the readout electronics 30 is also affected by both the voltage gating signal 4 and the signal 5 from the single input / output I / O of the SNSPD. In particular, any electrical reflection from an SNSPD of the voltage gating signal 4 due to non-matching impedances will be present the readout signal 6, as well as any direct transmission of the voltage gating signal 4. The readout signal 6 is thus subject to a plurality of parasitic influences on top of the photon detection pulses meant to be detected. The readout electronics 30 may be configured to process the readout signal 6, provide bias current adjustment, further amplify the SNSPD voltage pulse to a user readable signal for time tagging electronics. Time tagging electronics typically determine the exact time of electrical events. Recognized events are then marked with a timestamp and a list of events may then be created and sent for further evaluation.

[0005] To understand the gating response of an SNSPD to a standard square wave voltage gating signal, the electrical equivalent circuit of an SNSPD is of importance.

[0006] In essence, an SNSPD acts mainly as a combination of an inductor (due to the large kinetic inductance of the superconducting material) and a resistor in series when it detects a photon. The kinetic inductance of the superconducting material is due to the resistance to acceleration of the charge carriers inside the superconducting material. An SNSPD has typically a kinetic inductance of several hundreds of nanohenry. Figure 3 represents an equivalent circuit of an SNSPD circuit comprising an RF cable for connection, an amplifier, and a superconducting sensing element. The equivalent circuit can be described in lumped elements as a series inductor Lk, a load time dependent resistor Rn(t), an impedance Zo representing the impedance of the cable with the amplifier stage, a bias current source Ibias and a switch. The switch represents the triggered photon detection. A photon detector can thus be seen as an LR circuit with a specific time constant, labeled tau which is equal to L / Z0.

[0007] It is noted that an SNSPD is fully operational when its current reaches an optimal biasing value, typically from a few microamperes to several tens of microamperes. When the SNSPD is used in gated mode, the time needed for the detector to reach this optimal bias point reflects the LR timing characteristics of the circuit. When the current in the SNSPD reaches the optimal bias point, a probability of detecting photons of 99,9% (full detection probability) is then achieved or in other words photon detection begins. This time may be referred to as “efficiency recovery time from gate start” by reference to the time needed to recover full detection probability, i.e. full efficiency, or as “gating speed” by reference to the gating circuit or even simply as “turn-on time” or “start-up time” by reference to detector itself. All these terminologies may be used in the rest of the present text.

[0008] When an SNSPD is gated, the characteristic turn-on or off time is thus limited by the L / ZO time constant. This value usually lies between 10-30 nanoseconds depending on the device dimensions (basically depending on the kinetic inductance L_k). In fact, to recover the full internal efficiency after the gate start, a ramp up time of 5 tau to recover to 99.9% should be awaited to the steady state current as depicted in figure 4a. In comparison, a ramp-up time of 3 tau may reach only 95% of detection probability. Therefore, a standard square wave gate approach can only lead to gating speeds ranging from 50 to 150 ns. If either the duty cycle or the frequency of the gating window is too fast / short, the SNSPD has no time to fully turn on / off: as shown in Figure 4b, choosing a slow frequency for the voltage gating signal allows for the current in an LR circuit to settle, while as shown in Figure 4c, choosing a high frequency may impede the current to fully recover and reach an optimal steady state value.

[0009] The gating speed affects thus the detector efficiency, and it is highly desired to reduce it to the nanosecond range for time-stringent applications where precise timing / fast turn on dynamics is important, and / or applications where filtering of spurious light from an excitation source is desired. This can encompass photoluminescence experiments, quantum optics, communication experiments / protocols, and bio-imaging applications.

[0010] A known prior art solution to this problem of detector efficiency is to reduce the time constant tau of the detector by increasing artificially the load impedance. Figure 4 illustrates this prior art solution. Typically, in the prior art a resistive network 23 is added right next to the nanowire 21, that is in between the nanowire 21 and the cryogenic amplifier 22. Such a network typically consists of a series resistor and a resistor to ground, such that the time constant of the new circuit scales as L / [(Z0 || R_gnd) + R_{series}]. However, adding these resistors does not help reaching the targeted time scales up to the order of a nanosecond or sub-nanoseconds. In addition, the signal amplitude is also affected by these resistors which cannot be made too large and could also lead to detector latching, namely a non-working state of the SNSPD.

[0011] There is thus a need for an improved gating circuit improving the detector efficiency while overcoming the shortcomings of the prior art. SUMMARY

[0012] The object of the invention is to provide a gating circuit moving forward / advancing the time at which photon detection begins, in particular shortening the start-up time of the detector up to the order of a nanosecond or sub-nanoseconds.

[0013] According to a first aspect of the invention, a gating circuit for generating a voltage gating signal for controlling on / off operation of a photon detector is provided. The photon detector has a superconducting sensing element for detecting photons and one input / output configured to both input the voltage gating signal to the superconducting sensing element and output a readout signal from said superconducting sensing element. The gating circuit comprises a signal generator for generating a first periodic signal, and a gate shaping circuit configured to, based on the first periodic signal, obtain a periodic voltage gating signal having during each period a transient pulse followed by a (steady state) plateau. The transient pulse has a width and an amplitude.

[0014] In this way, the gate shaping circuit is able to generate a customized voltage gating signal for faster switch on / off of the photon detector. The customized voltage gating signal comprises an initial pulse for a fast current rise inside the SNSPD up to the optimal bias point and a plateau for steady state detection. The transient pulse helps reaching faster the optimal bias point at which photon detection begins. The (steady state) plateau is for maintaining the current at the optimal bias point after the transient. In other words, the plateau has a value determined to drive the superconducting sensing element ON and the pulse has a maximum amplitude higher than the value of the plateau. By transient pulse is meant a rise and a fall, defining a shape having a width and an amplitude. According to a preferred embodiment, the gate shaping circuit is configured to shape the transient pulse so as to oppose a kinetic inductance of the photon detector and advance a time at which photon detection begins. In other words, the transient pulse is shaped so as to adjust a time at which optimal bias is reached and photon detection begins.

[0015] According to a preferred embodiment, the gate shaping circuit is configured to set the width and / or amplitude of the transient pulse to adjust a time at which photon detection begins. In this way, by adjusting the initial pulse, the rate of ramp-up of the current in the photon detector may be adjusted, adjusting thus the time at which the optimal bias point is reached, and photon detection begins. Preferably said time is reduced by more than two orders of magnitude with respect to the time constant of the photon detector.

[0016] According to a preferred embodiment, the gating circuit is configured such that the time at which photon detection begins is set to be in the order of a nanosecond or sub-nanoseconds. In this way, the gating circuit is rendered suitable for time -stringent applications where precise timing / fast turn on dynamics is important, and / or applications where filtering of spurious light from an excitation source is desired. This can range from photoluminescence experiments, quantum optics and communication experiments / protocols, bio-imaging applications. According to a preferred embodiment, the gate shaping circuit comprises a pulse shaping circuit configured to control the shape of the transient pulse. In this way, the shape of the transient pulse may be adjustable via one specific circuit which may be customized by a user to his needs. The pulse shaping circuit preferably receives the first periodic voltage signal and derives the transient pulse from the first periodic signal.

[0017] According to a preferred embodiment, the pulse shaping circuit is a second order filter receiving the first periodic signal, preferably an analog RLC circuit. Preferably the analog RLC circuit comprises a series circuit of a resistor and an inductor, arranged in parallel with a capacitor. Alternatively, other topologies of second order filters may be envisaged depending on circumstances. Digital second order filters may for instance be envisaged. More generally, any element of the gate shaping circuit need not be limited to a disclosed analog implementation and may be similarly embodied digitally without inventive step.

[0018] According to a preferred embodiment the pulse shaping circuit comprises at least one tunable element, preferably a tunable inductor or a tunable resistor. In this way, a user may easily adjust the voltage gating signal to create custom-made gate shapes meeting its requirements. According to a preferred embodiment, the shaping circuit comprises a high-pass filter configured to receive the first periodic signal and output a shaped first intermediate signal. In this way, the shape of the AC component of the pulse portion can be adjusted independently from the DC component of the pulse portion and from the value of plateau. The high pass filter function may be implemented in an analog or digital manner.

[0019] According to a preferred embodiment, the shaping circuit comprises a high-pass filter configured to receive the first periodic signal and output a shaped first intermediate signal. In this way, the shape of the AC component of the pulse portion can be adjusted independently from the DC component of the pulse portion and from the value of plateau.

[0020] According to a preferred embodiment, the gate shaping circuit comprises at least one attenuating circuit configured to control the amplitude of the pulse and / or the value of the steady state plateau. In this way, the plateau and / or amplitude of the first pulse may be adjustable.

[0021] According to a preferred embodiment, the attenuating circuit is a voltage variable attenuator, preferably a tunable voltage divider network, more preferably a tunable 7t-type voltage divider network. In this way, an off-the shelf component can be used to control the attenuation. Alternatively, a digital variable attenuator may be envisaged.

[0022] According to a preferred embodiment, the at least one attenuating circuit comprises a first voltage variable attenuator configured to receive the shaped first intermediate signal and output an attenuated first intermediate signal, and a second voltage variable attenuator configured to receive the first periodic signal and output an attenuated second intermediate signal. In this way, the amplitude of the AC component of the pulse portion and respectively the amplitude of the DC component of the pulse portion and the value of plateau can be tailored to user requirements independently.

[0023] According to a preferred embodiment, the gating circuit comprises an adder configured to sum the attenuated first intermediate signal and the attenuated second intermediate signal to output the voltage gating signal. In this way, the AC and DC components of the voltage gating signal can be combined to obtain an entirely custom-made voltage gating signal.

[0024] According to a preferred embodiment, the pulse gating circuit is a transient pulse signal generator for generating the transient pulse. Preferably the transient pulse signal generator is a square wave generator with a tunable frequency and / or duty cycle and / or amplitude.

[0025] According to a preferred embodiment, the gate shaping circuit further comprises an adder for adding the generated transient pulse to the first periodic signal to obtain the periodic voltage gating signal.

[0026] According to a preferred embodiment, the signal generator is a square wave generator, preferably with a tunable frequency and / or duty cycle. In this way, a standard signal generator may be used, while offering the possibility to adjust the frequency and duty cycle of the signal in an easy manner. Preferably the square wave generator comprises a comparator. In this way, a fast rise time can be achieved while using a simple arrangement with an external clock.

[0027] According to a preferred embodiment, a circuit arrangement for photon detection is provided. The arrangement comprises a main photon detector for detecting photons emitted from an optical fiber, said main photon detector comprising a sensing element, said main photon detector having one input / output configured to input a main voltage gating signal to the sensing element and to output a main readout signal from said sensing element and a gating circuit according to any of the above embodiments, generating a main voltage gating signal for the main photon detector. In this circuit a complete solution for improved photon detection is offered in which the gating and the photon detector are matched to each other and which gating speed, i.e., turn-on time of the photon detector, can be adjusted to user needs.

[0028] According to a second aspect, the circuit arrangement further comprises a mirror photon detector, a mirror gating circuit and a combiner circuit. The mirror photon detector is identical to the main photon detector but receives no photons, said mirror photon detector having one input / output configured to input a mirror voltage gating signal to its respective sensing element and to output a mirror readout signal from said respective sensing element. The mirror gating circuit is configured to derive a mirror voltage gating signal from the main voltage gating signal. The combiner circuit is configured to combine the main and mirror readout signal to obtain an improved readout signal. In this way, the accuracy of the readout signal can be improved by removing a gating artefact. Due to the input / output of the photon detector being used for both inputting the voltage gating signal and outputting the readout signal, the readout signal contains a parasitic artefact due to the voltage gating signal being amplified and reflected back from the SNSPD onto the readout signal. By using a mirror SNSPD, a signal comprising only the artefact can be created. By combining the readout signals from the main and the mirror SNSPD, the artefact can then be entirely compensated, thus improving the accuracy of the readout signal.

[0029] It is noted that although this arrangement is shown in combination with the fast-gating circuit idea of the first aspect, this aspect may be used independently, i.e., with any kind of gating circuit. In that case the gating circuit need thus not be according to any of the above embodiments, as long as the mirror voltage gating signal and the main voltage gating signal are related to each other in terms of phase and amplitude (same phase, same or opposite amplitude).

[0030] According to a preferred embodiment, the mirror voltage gating signal has an opposite amplitude with respect to the first voltage gating signal and the combiner circuit comprises an adder. Alternatively, the mirror voltage gating signal is identical to the main voltage gating signal and the combiner circuit comprises a subtractor, preferably a balun, more preferably a transformer balun with a first and second primary windings with opposite winding orientations.

[0031] BRIEF DESCRIPTION OF THE FIGURES

[0032] This and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing currently preferred embodiments of the invention. Like numbers refer to like features throughout the drawings

[0033] Figure 1 illustrates a schematic representation of an SNSPD coupled to an optical fibre to detect photons emitted from said fibre;

[0034] Figure 2 illustrates a schematic electrical connection of an SNSPD with a square wave generator and readout electronics according to the prior art;

[0035] Figure 3 illustrates an equivalent circuit of an SNSPD system;

[0036] Figure 4a illustrates the typical response of a typical LR circuit to a square wave transient;

[0037] Figures 4b and 4c illustrate responses of an LR circuit to a square wave stimulation with respectively a frequency lower and higher than 5 times the time constant of the LR circuit;

[0038] Figure 5 shows a prior art solution with an additional resistor network;

[0039] Figure 6 illustrates a schematic electrical connection of a circuit arrangement comprising an SNSPD, readout electronics and a gating circuit according to a first aspect;

[0040] Figure 7 illustrates a block diagram of a gating circuit according to an embodiment of the first aspect;

[0041] Figure 8 illustrates a representation of an electrical circuit according to the embodiment of Figure Figure 9 illustrates waveforms of current responses of an SNSPD to a plurality of voltage gating signals from a gating circuit according to an embodiment;

[0042] Figure 10 illustrates a block diagram of a gating circuit according to another embodiment of the first aspect;

[0043] Figures Ila and 1 lb illustrate waveforms of the readout signal over time and a histogram representing the efficiency recovery over time after the start of the detector according to embodiments of Figures 6-10;

[0044] Figure 12 illustrates a circuit arrangement with an improved readout signal according to a second aspect;

[0045] Figure 13 illustrates a circuit arrangement with an improved readout signal according to an embodiment of the second aspect;

[0046] Figure 14 illustrates a representation of an electrical circuit according to the embodiment of Figure 13;

[0047] Figures 15 illustrates waveforms according to the embodiments of Figures 13 and 14;

[0048] Figure 16 illustrates a circuit arrangement with an improved readout signal according to another embodiment of the second aspect;

[0049] Figure 17 illustrates a representation of an electrical circuit according to the embodiment of Figure 16;

[0050] Figures 18 and 19 illustrates waveforms according to the embodiments of Figures 16 and 17;

[0051] Figure 20a illustrates normalized voltage gate signals obtained according to embodiments of the present invention for different peak pulse width powers Pw;

[0052] Figure 20b describes the response in current from the SNSPD receiving the gate voltage signals of Figures 21a and 21b show the waveforms of Figure 20a during a short time frame around the first occurrence of a transient pulse;

[0053] Figure 22 illustrates a block diagram of a gating circuit according to another embodiment.

[0054] DESCRIPTION OF THE EMBODIMENTS

[0055] Although the figure description may mention SNSPDs for single photon detection and using a nanowire, it is noted that the invention applies similarly to any photon detector using a superconducting sensing element. The teaching of the present application should thus not be limited to SNSPDs but is relevant to photon detectors in general in as far as their electrical behaviour amounts to that mostly of an RL circuit.

[0056] Figure 6 illustrates a schematic electrical connection of a photon detector 20 (for instance an SNSPD) with readout electronics 30, and a gating circuit 10 according to a first aspect. The gating circuit 10 is configured for generating a voltage gating signal 15 for controlling on / off operation of a photon detector 20. As in the prior art, the photon detector 20 has a superconducting sensing element for detecting photons and one input / output configured to both input the voltage gating signal to the superconducting sensing element and output a readout signal from said superconducting sensing element.

[0057] Embodiments according to the first aspect are based inter alia on the insight to introduce a high pulse at the start of the voltage gating signal to oppose the kinetic inductance of the photon detector and thus improve the gating speed. The gating circuit 10 is configured to generate a periodic voltage gating signal 15 having during each period a transient pulse 15a followed by a steady state plateau 15b, wherein the transient pulse 15a is dimensioned so as to adjust, typically advance, a time at which photon detection begins. The transient pulse 15a opposes the kinetic inductance of the photon detector to have a fast(er) ramp-up of the current up to the biasing point. The term faster is here to understand with respect to a reference ramp-up imposed by the time constant of the photon detector when the voltage gating signal is a square wave.

[0058] Figure 7 illustrates a block diagram of a gating circuit 10 according to an embodiment of the first aspect. The gating circuit 10 comprises a signal generator 11 for generating a first periodic signal 16. The signal generator 11 is an AWG (arbitrary waveform generator) that creates a flexible square wave signal 16 having a tuneable period T, as well as a tuneable duty cycle a. A user may tune T and a to its needs. The gating circuit 10 further comprises a gate shaping circuit 14 configured to shape the first periodic signal 16 to obtain a periodic voltage gating signal 15 having during each period a transient pulse 15a followed by a steady state plateau 15b, wherein the transient pulse 15a is dimensioned so as to adjust a time at which photon detection begins. The gate shaping circuit 14 comprises a pulse shaping circuit 12 and a voltage variable attenuator 13. The pulse shaping circuit 12 is configured to control the shape of the voltage gating signal 15 and, in particular, the shape of the transient pulse 15a. The width and / or amplitude of the transient pulse 15a can be set by the user to adjust the gating time at photon detection begins. Indeed, the shape of the pulse will affect the ramp-up time of the current in the photon detector up to the biasing point at which photon detection will start, also referred to previously as turn-on time or gating speed. Although an analog implementation of the gating circuit 10 will now be described, digital implementations of a square wave generator 11, a gat shaping circuit 14, a pulse shaping circuit 12 and a voltage variable attenuator 13 may also be envisaged.

[0059] Figure 8 illustrates an electrical circuit according to the embodiment of Figure 7. A comparator V 1 is used as square wave generator 11, an REC network is used as pulse shaping circuit 12 and a voltage divider is used as voltage variable attenuator 13. The RLC network for shaping the voltage gating signal comprises a resistor R3 in series with an inductor L2, said series connection being connected in parallel with a capacitor Cl. The RLC network is further connected in parallel with the comparator VI. The voltage divider 13 comprises three resistors arranged in 7t topology to form a 7t-ly pc voltage divider network. One end of the divider network is connected to the connection point between the comparator 11 and the pulse shaping circuit 12, while the other end outputs the voltage gating signal 15. The plateau voltage of the voltage gating signal 15 can be tuned via the attenuator 13, while the amplitude and width of the transient pulse 15a of the voltage gating signal 15 can be tuned via the pulse shaping circuit 12, in particular via a tuneable inductor L2. The attenuator 13 can be used to finely tune the gate amplitude of the plateau 15b and avoid over / under biasing of the photon detector.

[0060] Figure 9 illustrates a simulation of SNSPD current responses to a plurality of voltage gating signals output by a gating circuit as a function of the tuneable inductor according to an embodiment. The voltage gating signals are expressed in mV while the values of the tuneable inductors are expressed in nH. The illustrated voltage gating signals for different values of the tuneable inductors show transient pulses 15a of different amplitudes and widths followed by consecutive plateaus 15b. As can be seen in Figure 9, a wider initial peak 15a leads to a quicker ramp-up of the current inside the SNSPD, compensating the physical limit of the LR time constant. By adjusting the inductor of the pulse shaping circuit 12, a user can thus tailor the gating speed of the photon detector.

[0061] Figure 10 illustrates a block diagram of a gating circuit according to another embodiment of the first aspect. In this embodiment, the pulse shaping circuit 12 comprises a high-pass filter 12a configured to receive the first periodic signal 16 output by the square wave generator 11 and output a shaped first intermediate signal 17 shaped as a pulse. The at least one attenuating circuit 13 comprises a first voltage variable attenuator 13a configured to receive the shaped first intermediate signal 17 and output an attenuated first intermediate signal 18, and a second voltage variable attenuator 13b configured to receive the first periodic signal 16 output by the square wave generator 11 and output an attenuated second intermediate signal 19. The gating circuit 10 further comprises an adder 13c configured to sum the attenuated first intermediate signal 18 and the attenuated second intermediate signal 19 to output the voltage gating signal 15 comprising the transient pulse 15a and a plateau 15b. As previously mentioned, this embodiment may be implemented either with analog or digital elements.

[0062] Figure Ila illustrates a waveform of the readout signal 35 over time send to the readout electronics 30 according to embodiments of Figures 6-10 while Figure 11b illustrates a histogram representing the efficiency recovery over time after the start of the detector. The signal 35 received by the readout electronics is represented in Figure Ila. The signal 35 presents during an initial time frame A (around 0-5 ns) a first large pulse corresponding to a pulse created by the gating signal 15 going from the gating circuit 10 through the tee element 40 directly to the readout electronics. The signal 35 further presents during a later time frame B (around 30 ns) a second pulse corresponding to a reflection of the voltage gating signal 15 from the SNSPD. This phenomenon will be called a gating artefact. This gating artefact present on the readout signal 35 fed to the readout electronics affects the accuracy of the photon detection. It is a parasitic phenomenon due to the tee-coupling. Immediately after the gating artefact, from 35 ns till >80 ns one can see actual photon pulses from the photon detector 20. Time frame C marks in particular the beginning of the switch-on period of the photon detector. The waveforms of Figures 1 la and 1 lb were obtained for experiments using an improved gating circuit according to the first aspect of the invention described in previous Figures 6-9, with in particular a fast gating speed. Figure 1 lb represents a histogram of the efficiency recovery during time frame C, i.e., from the gate start. The time to reach a 100% detection probability can there be seen as attained within the timeframe D, amounting roughly to the first two nanoseconds. By comparison, the photon detector used in this experiment would have a L / Zo constant of around 15 ns, meaning a typical gating speed of 75 ns. The increase in gating speed is thus significant compared to the prior art. However, the values given here are merely indicative, and the gating speed may be tailored to the user needs. In essence, a gating speed in the range of a nanosecond or sub-nanoseconds (around 500 ps) is achievable with the disclosed gating circuit.

[0063] Figure 12 illustrates a circuit arrangement with an improved readout signal according to another aspect. As seen in Figure Ila, the gating artefact when using the gating system of Figures 6-9 is detrimental to the accuracy of the detection. As SNSPD pulses occur on top of the gating artefact in the readout signal, time-tagged experiments are rendered difficult. The gating artefact also leads to a poor timing jitter.

[0064] To address that problem, embodiments according to a second aspect are offered based inter-alia on the idea of generating a signal containing solely the gating artefact using a second dummy / mirror SNSPD, identical to the one in use but not receiving any input light. Such a mirror SNSPD would not generate any photon counting pulses, only gating artefact pulses.

[0065] Two alternative embodiments are provided. Both embodiments comprise a mirror SNSPD 20’, a mirror gating circuit 10’ and a combiner 50. The mirror photon detector 20’ is identical to the main photon detector 20 but does not receive photons. In other words, the mirror photon detector is not coupled to an optical fiber. The mirror photon detector 20’ has one input / output I / O’ configured to input a mirror voltage gating signal 45’ from its dedicated mirror gating circuit 10’ to its respective sensing element and to output a mirror readout signal 35’ from said respective sensing element. The mirror gating circuit 10’ is configured to generate a mirror voltage gating signal 45’ that is correlated to the main voltage gating signal 45. In particular, the mirror voltage gating signal 45’ may derive from the main voltage gating signal 45 directly or indirectly. The mirror voltage gating signal 45’ and the main voltage gating signal 45 can be seen as outputs of a general gating circuit 40 containing the gating circuit 10 and its mirror 10’.

[0066] The combiner circuit 50 is then configured to combine the main readout signal 35 and the mirror readout signal 35’ to obtain a final readout signal 36 in which the gating artefact is absent. By combining the main readout signal 35 and the mirror readout signal 35’, the gating artefact pulse prior to start of photon detection can be eliminated from the signal 36 fed to the readout electronics 30.

[0067] Figure 13 illustrates a circuit arrangement with an improved readout signal according to an embodiment. In this embodiment, the general gating circuit 40 comprises a gating circuit 10 which first voltage gating signal 15 is received by a power divider 41. The power divider 41 is configured to generate a main voltage gating signal 45 and a mirror voltage gating signal 45’ that are identical to each other, and that are derived from the first voltage gating signal 15 of the gating circuit 10. A subtractor 51 is then used as combiner circuit 50 to subtract the mirror readout signal 35’ from the main readout signal 35 to obtain the final readout signal 36.

[0068] Figure 14 illustrates an electrical circuit according to the embodiment of Figure 13. In Figure 14, the gating circuit 10 is a schematic representation of a gating circuit according to the embodiments of Figure 10. The voltage gating signal of the gating circuit 10 is obtained by combining a pulse component obtained from a voltage source V2 and capacitor Cl in series, with an attenuated square wave component obtained from a voltage source VI and an attenuator resistor network (R1-R3). In between the gating circuit 10 and the power divider 41, the presence of coax cables has been taken into account. The main and mirror voltage gating signals 45 and 45’ at the output of the power divider are connected respectively to the main SNSPD 10 and the mirror SNSPD 20’. The main and mirror voltage gating signals 45 and 45’ are identical. The combiner 51 is a balun circuit comprising a transformer with two primary windings L2 and L3 having the same inductance but opposite polarities. In this way, the main and mirror readout signals 35 and 35’ can be subtracted from each other to remove the gating artefact present in both signals.

[0069] Figures 15 illustrates waveforms according to the embodiments of Figures 13 and 14 for different gating speeds. Curves 61 represent the current going through the main SNSPD for different gating speeds. Curves 62 represent the current going through the mirror SNSPD for different gating speeds. Curves 63 represent the final readout signal 36 associated with the respective curves 61 and 62. At to the SNSPDs receive their respective but identical voltage gating signals 45 and 45’. The currents through the SNSPDs then increase in the same manner up to ti, when a photon impinges on the main SNSPD. As a consequence of the photon impinging on the main SNSPD, the current through the main SNSPD drops, creating a voltage pulse in the final readout signal 36 as can be seen on curves 63. The current through the mirror SNSPD does not show this drop at ti but a continuous waveform in response to the mirror voltage gating signal 45’. It can thus be seen from these waveforms how the main and the mirror SNSPD have the same electrical behaviour except that only the main SNSPD detects actually photons. Thus, although not represented directly, it derives from the waveforms for Figure 15 that the main and mirror readout signals 35 and 35’ will contain the same reflection of the voltage gating signals 45 and 45’, or in other words the same gating artefacts. However, the mirror readout signal will not contain pulses corresponding to photon detections, such that when subtracting the mirror readout signal 45’ from the main readout signal 45, the gating artefacts present in both signals will cancel each other out while the pulses of the photon detections of the main SNSPD will remain. In this way, the issue of the gating artefact can be reliably solved, and the detection accuracy improved.

[0070] Figure 16 illustrates a circuit arrangement with an improved readout signal according to another embodiment. In this embodiment, the general gating circuit 40 comprises a gating circuit 10 and an inverted gating circuit 10’. The inverted gating circuit 10’ is configured to generate a mirror voltage gating signal 45’ that has an inversed polarity with respect to the main voltage gating signal 45. The inverted gating circuit may be a standalone element or may receive the main voltage gating signal 45 from the main gating circuit 10 and invert it. In both cases, the main voltage gating signal 45 and the mirror voltage gating signal 45’ are synchronised but have opposite amplitudes. An adder 52 is then used as combiner circuit 50 to add the mirror readout signal 35’ to the main readout signal 35 to obtain the final readout signal 36.

[0071] Figure 17 illustrates an electrical circuit according to the embodiment of Figure 16. In Figure 17, the gating circuit 10 is a schematic representation of a gating circuit according to the embodiments of Figure 10, like in Figure 14. A first gating circuit 10 generates a first voltage gating signal 45, while a second gating circuit 10’ generates a second voltage gating signal 45’. The first and second voltage gating signals 45 and 45’ are synchronised but have opposite amplitudes. The first and second voltage gating signals 45 and 45’ are provided via respective coax cables 42 to the single input / output I / O of main SNSD 20 and respectively the single input / output I / O’ of the mirror SNSPD 20’. The main and mirror voltage gating signals 45 and 45’ are synchronised but have opposite amplitudes. The T and T’ connection points define the connection point in the circuit arrangement at which the voltage gating signals 45 and the readout signals 35 are joined. In such an embodiment no T piece need yet be present and no cryogenic amplifier may be used. The main and mirror readout signals 35 and 35’ can then be added together to remove the gating artefact present in both signals but with opposite amplitudes.

[0072] Figures 18 and 19 illustrates waveforms according to the embodiments of Figures 16 and 17. The curves of Figure 19 represent the main and mirror readout signals 35 and 35’. As can be seen, during period B the readout signals35 and 35’ show gating artefact pulses of opposite amplitudes, while during period E, only the main readout signal 35 contains photon detection pulses. Figure 18 is a zoom of period E of Figure 19 showing two photon detection pulses 35i during period C while the mirror readout signal does not change any abrupt changes. It can thus be seen that the main and mirror readout signals 35 and 35’ will contain the same gating artefacts but with opposite amplitudes. However, the mirror readout signal will not contain pulses corresponding to photon detections, such that when adding the mirror readout signal 45’ to the main readout signal 45, the gating artefacts present in both signals will cancel each other out while the pulses of the photon detections of the main SNSPD will remain. In this way, the issue of the gating artefact can be reliably solved, and the detection accuracy improved.

[0073] Figures 20a describe normalized voltage gate signals obtained according to embodiments of the present invention for different peak pulse width powers Pw. Figure 20b describes the response in current from the SNSPD receiving the gate voltage signals of Figure 20a. Figures 21a and 21b describe zoom in portions of Figure 20a explaining respectively in more detail the transient pulse portion 15a of the gate voltage signals and the plateau portion 15b of the gate voltage signals represented in Figure 20a.

[0074] By peak pulse width power Pw is meant a metric calculated by multiplying the (peak) amplitude of the transient pulse 15a, also called pulse voltage Vpuise , by the width of the transient pulse 15a , also called pulse duration TpUise, according to the equation: Pw = VpUise* TpUise. The peak pulse width power Pw determines how fast the SNSPD can be activated. The skilled person may either use a higher Vpuise with a shorter TpuiSe , or a reduced VpuiSe with a wider TpuiSe. In the figures 20a and 20b, Pw was varied by varying TPeUiSe for a constant VpuiSe. In practice, VpuiSe may indeed be set to a constant value, for instance a maximum allowable transient pulse voltage Vpuise-max being a constraint related to the electronics generating the pulse.

[0075] As can be seen in Figure 20a, the peak pulse width power Pw was varied from 250ps to lOOOps in four steps. At the scale of representation of Figure 20a, all waveforms corresponding to the voltage gate signals for the four peak pulse width powers Pw are overlayed on one another. The voltage gate signals comprise a first transient pulse portion 15a, followed by a plateau portion 15b. In this simulation, the SNSPD detector was simulated as having a lOOOnH inductance. More generally, the present invention relates to SNSPDs with relatively high inductance values in the order of several hundreds of nH and over a microhenry . For such SNSPDs, as explained in Figure 8, the behaviour of the SNSPD amounts as explained in the context of Figure 3 to an LR circuit.

[0076] The voltage gate signals are shown in Figure 20a as having a period of 500ns, starting by a high transient pulse 15a having a maximum(Zpeak) pulse voltage VpUisefollowed by a plateau 15b during which the detector is on. The amplitude of the transient pulse 15a, ie the pulse voltage VpUise>is much higher than the amplitude of the gate signal during the plateau 15b, i.e. Vpiateau- For completeness, to turn off the detector the voltage gate signals further comprise a turn-off portion during which the voltage gate signals are reversed (negative pulse 15c and negative plateau 15d). To describe in detail the transient pulse portion 15a and the plateau portion 15b of the voltage gate signal, Figures 21a and 21b show the waveforms of Figure 20a during a short time frame around the first occurrence of a transient pulse. Figures 21a and 21b show in particular the first 2 ns of Figure 20a with different scales for the normalized voltage gate signals to respectively show the width of the transient pulse 15a and the amplitude of the plateau 15b. Figure 21a shows four waveforms corresponding to the voltage gate signals for the four pulse widths Pw of Figures 20a and 20b. Looking at one voltage gate signal, for instance the first waveform for a peak pulse width power value Pw of 250ps, that voltage gate signal first rises up to a maximum voltage, i.e. the pulse voltage Vpuise, to form a peak before falling back to a plateau value Vpiateau- The width of the transient pulse, i.e. the pulse duration TpUise, amounts then to the sum of a rise time from zero, a peak time and a fall time to the value Vpiateau- The plateau 15b extents up until the reverse pulse 15c for turning off the SNSPD. The voltage value of the plateau 15b, i.e. Vpiateau , is smaller than the amplitude of the pulse voltage VpuiSe. As a matter of fact, the amplitude of the pulse has a different order of magnitude than the voltage value of the plateau. This is the reason why the first portion 15a is called a transient pulse and why the voltage gate signal may look in Figure 20a merely as single pulses. However, the value of gate voltage Vpiateau is sufficient to maintain the bias the SNSPD once the dynamic behaviour created by the LR nature of the SNSPD (and compensated by the transient pulse 15a) is over.

[0077] Figure 20b shows how the bias current through the SNSPD behaves for the voltage gate signals of Figures 10a, 21a and 21b. It is clear that a higher Pw relates into a faster turn-on of the SNSPD, or in other words a faster activation time. In particular compared to a prior art waveform without a transient pulse, the activation time is greatly reduced thanks to the transient pulse. Whilst the principles of the invention have been set out above in connection with specific embodiments, it is understood that this description is merely made by way of example and not as a limitation of the scope of protection which is determined by the appended claims.

[0078] Figure 22 illustrates a gating circuit according to another embodiment. The gating circuit 10 comprises a signal generator 11 generating a periodic voltage signal I la, and a gate shaping circuit 14 configured to obtain a final periodic gating signal 15 based on the periodic voltage signal I la. The periodic voltage signal I la corresponds to a prior art gating signal with slow gating. The gate shaping circuit 14 enables an improved (faster) gating by injecting a transient pulse on top of the signal I la. The gate shaping circuit 14 comprises a transient pulse signal generator 12 for generating a transient pulse signal 12a, and an adder 13c for adding the generated transient pulse signal 12a to the first periodic signal I la to obtain the periodic voltage gating signal 15 comprising during each period a transient pulse 15a followed by a plateau 15b. The transient pulse signal generator 12 is preferably a square wave generator with a tunable frequency and / or duty cycle and / or amplitude. The elements 11, 12, 13c, 14 of this embodiment may be implemented either in an analog or digital manner. This embodiment differs from the embodiments of Figures 7 and 10 in that the transient pulse portion 15a is generated independently from the first periodic signal I la used to form the on / off periodicity of the final gating signal 15. Yet in all embodiments, the final gating signal is based on the first periodic signal I la.

[0079] Further embodiments are defined by the appended clauses. Clause 1. A gating circuit for generating a gating signal for controlling on / off operation of a photon detector, said photon detector having a superconducting sensing element for detecting photons and one input / output configured to both input the gating signal to the superconducting sensing element and output a readout signal from said superconducting sensing element, said gating circuit comprising: a signal generator for generating a first periodic signal, said gating circuit being characterised in that it further comprises: a gate shaping circuit configured to shape the first periodic signal to obtain a periodic gating signal having during each period a transient pulse followed by a plateau.

[0080] Clause 2: Gating circuit according to clause 1, wherein the transient pulse is shaped to oppose a kinetic inductance of the photon detector and advance a time at which photon detection begins. Clause 3: Gating circuit according to any of the above clauses, wherein the width and / or amplitude of the transient pulse is set to adjust a time at which photon detection begins.

[0081] Clause 4 : Gating circuit according to any of the above clauses, wherein the gate shaping circuit is configured such that photon detection begins within the order of a nanosecond or sub-nanoseconds. Clause 5 : Gating circuit according to any of the above clauses, wherein the gate shaping circuit comprises a pulse shaping circuit configured to control the shape of the transient pulse.

[0082] Clause 6: Gating circuit according to the previous clause, wherein the pulse shaping circuit is an RLC circuit.

[0083] Clause 7 : Gating circuit according to the previous clause, wherein the RLC circuit comprises at least one tunable element, preferably a tunable inductor or a tunable resistor.

[0084] Clause 8: Gating circuit according to clause 5, wherein the pulse shaping circuit comprises a high- pass filter configured to receive the first periodic signal and output a shaped first intermediate signal.

[0085] Clause 9: Gating circuit according to any of the above clauses, wherein the gate shaping circuit comprises at least one attenuating circuit configured to control the amplitude of the pulse and / or the value of the plateau.

[0086] Clause 10:Gating circuit according to the previous clause and any of clauses 1-7, wherein the attenuating circuit is a voltage variable attenuator, preferably a tunable voltage divider network, more preferably a tunable 7t-type voltage divider network.

[0087] Clause 11 : Gating circuit according to the clause 7 and clause 8, wherein the at least one attenuating circuit comprises a first voltage variable attenuator configured to receive the shaped first intermediate signal and output an attenuated first intermediate signal, and a second voltage variable attenuator configured to receive the first periodic signal and output an attenuated second intermediate signal. Clause 12: Gating circuit according to the previous clause, wherein the gating circuit comprises an adder configured to sum the attenuated first intermediate signal and the attenuated second intermediate signal to output the gating signal.

[0088] Clause 13: Gating circuit according to any of the above clauses, wherein the signal generator is a square wave generator, preferably with a tunable frequency and / or duty cycle.

[0089] Clause 14: Circuit arrangement for photon detection, the arrangement comprising: a main photon detector for detecting photons emitted from an optical fiber, said main photon detector comprising a sensing element, said main photon detector having one input / output configured to input a main gating signal to the sensing element and to output a main readout signal from said sensing element; a gating circuit according to any of the above clauses, generating a main gating signal for the main photon detector.

[0090] Clause 15: Circuit arrangement according to the previous clause, further comprising: a mirror photon detector, said mirror photon detector being identical to the main photon detector but receiving no photons, said mirror photon detector having one input / output configured to input a mirror gating signal to its respective sensing element and to output a mirror readout signal from said respective sensing element; a mirror gating circuit configured to derive a mirror gating signal from the main gating signal, and a combiner circuit configured to combine the main and mirror readout signal to obtain an improved readout signal.

[0091] Clause 16: Circuit arrangement according to the previous clause, wherein the mirror gating signal has a reversed amplitude with respect to the first gating signal and the combiner circuit comprises an adder.

[0092] Clause 17: Circuit arrangement according to clause 15, wherein the mirror gating signal is identical to the main gating signal and the combiner circuit comprises a subtractor, preferably a balun, more preferably a transformer balun with a first and second primary windings with opposite winding orientations.

Claims

CLAIMS1. A gating circuit for generating a voltage gating signal for controlling on / off operation of a photon detector, said photon detector having a superconducting sensing element for detecting photons and one input / output configured to both input the voltage gating signal to the superconducting sensing element and output a readout signal from said superconducting sensing element, said gating circuit comprising: a signal generator for generating a first periodic voltage signal, said gating circuit being characterised in that it further comprises: a gate shaping circuit configured to, based on the first periodic voltage signal, obtain a periodic voltage gating signal having during each period a transient pulse followed by a plateau, said transient pulse having a width and an amplitude.

2. Gating circuit according to claim 1, wherein the gate shaping circuit is configured to shape the transient pulse to oppose a kinetic inductance of the photon detector and advance a time at which photon detection begins.

3. Gating circuit according to any of the above claims, wherein the gate shaping circuit is configured to set the width and / or amplitude of the transient pulse to adjust a time at which photon detection begins.

4. Gating circuit according to any of the above claims, wherein the gate shaping circuit is configured such that photon detection begins within the order of a nanosecond or subnanoseconds.

5. Gating circuit according to any of the above claims, wherein the gate shaping circuit comprises a pulse shaping circuit configured to control the shape of the transient pulse.

6. Gating circuit according to the previous claim, wherein the pulse shaping circuit is a second order filter receiving the first periodic signal, preferably an analog RLC circuit.

7. Gating circuit according to the previous claim, wherein the pulse shaping circuit comprises at least one tunable element, preferably a tunable inductor or a tunable resistor.

8. Gating circuit according to claim 6, wherein the pulse shaping circuit comprises a high- pass filter configured to receive the first periodic voltage signal and output a shaped first intermediate signal.

9. Gating circuit according to any of the above claims, wherein the gate shaping circuit comprises at least one attenuating circuit configured to control the amplitude of the pulse and / or the value of the plateau.

10. Gating circuit according to the previous claim, wherein the attenuating circuit is a voltage variable attenuator, preferably a tunable voltage divider network, more preferably a tunable 7t-type voltage divider network.

11. Gating circuit according to claim 9, wherein the at least one attenuating circuit comprises a first voltage variable attenuator configured to receive the shaped first intermediate signal and output an attenuated first intermediate signal, and a second voltage variable attenuator configured to receive the first periodic signal and output an attenuated second intermediate signal.

12. Gating circuit according to the previous claim, wherein the gating circuit comprises an adder configured to sum the attenuated first intermediate signal and the attenuated second intermediate signal to output the voltage gating signal.

13. Gating circuit according to claim 5, wherein the pulse shaping circuit is a transient pulse signal generator for generating the transient pulse.

14. Gating circuit according to the previous claim, wherein the transient pulse signal generator has a tunable frequency and / or duty cycle and / or amplitude.

15. Gating circuit according to any of the last two claims, wherein the gate shaping circuit further comprises an adder for adding the generated transient pulse to the first periodic signal to obtain the periodic voltage gating signal.

16. Gating circuit according to any of the above claims, wherein the signal generator is a square wave generator, preferably with a tunable frequency and / or duty cycle and / or amplitude.

17. Circuit arrangement for photon detection, the arrangement comprising: a main photon detector for detecting photons emitted from an optical fiber, said main photon detector comprising a sensing element, said main photon detector having one input / output configured to input a main voltage gating signal to the sensing element and to output a main readout signal from said sensing element; a gating circuit according to any of the above claims, generating a main voltage gating signal for the main photon detector.

18. Circuit arrangement according to the previous claim, further comprising: a mirror photon detector, said mirror photon detector being identical to the main photon detector but receiving no photons, said mirror photon detector having one input / output configured to input a mirror voltage gating signal to its respective sensing element and to output a mirror readout signal from said respective sensing element; a mirror gating circuit configured to derive a mirror voltage gating signal from the main voltage gating signal, and a combiner circuit configured to combine the main and mirror readout signal to obtain an improved readout signal.

19. Circuit arrangement according to the previous claim, wherein the mirror voltage gating signal has a reversed amplitude with respect to the first voltage gating signal and the combiner circuit comprises an adder.

20. Circuit arrangement according to claim 18, wherein the mirror voltage gating signal is identical to the main voltage gating signal and the combiner circuit comprises a subtractor, preferably a balun, more preferably a transformer balun with a first and second primary windings with opposite winding orientations.

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