Techniques for parallel polar code decoding

Abstract

Various aspects of the present disclosure relate to receiving (1602), at a UE, a polar codeword and determining (1604) a plurality of polar subcodes based on the polar codeword. Aspects of the present disclosure may relate to identifying (1606), for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns. Aspects of the present disclosure may relate to decoding (1608) the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

Description

TECHNIQUES FOR PARALLEL POLAR CODE DECODING TECHNICAL FIELD

[0001] The present disclosure relates to wireless communications, and more specifically to techniques for parallelization of polar code decoders. BACKGROUND

[0002] A wireless communications system may include one or multiple network communication devices, which may be known as a network equipment (NE), supporting wireless communications for one or multiple user communication devices, which may be otherwise known as user equipment (UE), or other suitable terminology. The wireless communications system may support wireless communications with one or multiple user communication devices by utilizing resources of the wireless communication system (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers, or the like). Additionally, the wireless communications system may support wireless communications across various radio access technologies (RATs) including third generation (3G) radio access technology, fourth generation (4G) radio access technology, fifth generation (5G) radio access technology, among other suitable radio access technologies beyond 5G (e.g., 5G- Advanced (5G-A), sixth generation (6G)). SUMMARY

[0003] An article “a” before an element is unrestricted and understood to refer to “at least one” of those elements or “one or more” of those elements. The terms “a,” “at least one,” “one or more,” and “at least one of one or more” may be interchangeable. As used herein, including in the claims, “or” as used in a list of items (e.g., a list of items prefaced by a phrase such as “at least one of” or “one or more of” or “one or both of) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” may be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the samemanner as the phrase “based at least in part Further, as used herein, including in the claims, a “set” may include one or more elements.

[0004] A UE for wireless communication is described. The UE may be configured to, capable of, or operable to receive a polar codeword; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

[0005] A processor for wireless communication is described. The processor may be configured to, capable of, or operable to receive a polar codeword; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

[0006] A method performed or performable by a UE for wireless communication is described. The method may include receiving, at a UE, a polar codeword; determining a plurality of polar subcodes based on the polar codeword; identifying, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decoding the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

[0007] A base station for wireless communication is described. The base station may be configured to, capable of, or operable to receive a polar codeword; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders,where each parallel polar code component comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

[0008] A processor for wireless communication by a base station is described. The processor may be configured to, capable of, or operable to receive a polar codeword; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

[0009] A method performed or performable by a base station for wireless communication is described. The method may include receiving, at a base station, a polar codeword; determining a plurality of polar subcodes based on the polar codeword; identifying, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decoding the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 illustrates an example of a wireless communications system in accordance with aspects of the present disclosure.

[0011] Figure 2 illustrates an example of a protocol stack in accordance with aspects of the present disclosure.

[0012] Figure 3 illustrates an example of use cases and target requirements in accordance with aspects of the present disclosure.

[0013] Figure 4 illustrates an example of channel combining in accordance with aspects of the present disclosure.

[0014] Figure 5 illustrates an example of a channel polarization effects in accordance with aspects of the present disclosure.

[0015] Figure 6A illustrates an example a binary tree traversal in accordance with aspects of the present disclosure.

[0016] Figure 6B illustrates an example of messaging during the binary tree traversal in accordance with aspects of the present disclosure.

[0017] Figure 7 illustrates an example of a SR0 / REP node in accordance with aspects of the present disclosure.

[0018] Figure 8 illustrates an example of a decoder with two parallel component decoders in accordance with aspects of the present disclosure.

[0019] Figure 9 illustrates an example of a decoder with multiple parallel component decoders in accordance with aspects of the present disclosure.

[0020] Figure 10 illustrates an example of a polar code tree partitioning in accordance with aspects of the present disclosure.

[0021] Figure 11 illustrates an example of a multisphere tree partitioning in accordance with aspects of the present disclosure.

[0022] Figure 12 illustrates an example of a binary search tree using pruning in accordance with aspects of the present disclosure.

[0023] Figure 13 illustrates an example of a UE in accordance with aspects of the present disclosure.

[0024] Figure 14 illustrates an example of a processor in accordance with aspects of the present disclosure.

[0025] Figure 15 illustrates an example of a NE in accordance with aspects of the present disclosure.

[0026] Figure 16 illustrates a flowchart of a method performed by a UE in accordance with aspects of the present disclosure.

[0027] Figure 17 illustrates a flowchart of a method performed by an NE in accordance with aspects of the present disclosure. DETAILED DESCRIPTION

[0028] The 6G enhanced ultra-reliable latency communication (eURLLC) and enhanced mobile broadband (eMBB) use cases are aimed at services with stringent requirements for low end-to-end transmission latency, ultra-reliability, packet size flexibility and availability as well as high throughput (e.g., around 1Tbit / s). In 6G, eURLLC plays an essential role in providing connectivity for the new services and applications from vertical domains, such as factory automation, tactile internet, autonomous driving and so on.

[0029] To achieve these requirements and performance targets, enhancements are made to channel encoding and decoding procedures. Polar codes are used due to their capacity-achieving performance and low complexity encoding and decoding.

[0030] Some of the bottlenecks for achieving 6G eURLLC and eMBB performance targets (e.g., low latencies and terabit throughputs) are the decoding delays associated with the use of polar codes and the lack of parallelization for polar code decoding (especially in the case of polar codes when sequential CRC-aided successive cancellation list (CRC-SCL) decoding is used). While certain fast and simplified polar code successive cancellation list (SCL) decoders have been investigated in the literature, they are based on a tree traversal method highly inspired by Reed-Solomon decoding methods. Additionally, some fast decoders described in the literature are able to realize high gains but at the expense of altering the polar encoding design.

[0031] The proposed fast SCL decoders are based on the implementation of parallel decoders at the intermediate levels of the successive cancellation (SC) decoding tree for some special nodes (or special Kernels) with specific patterns of information and frozen bits. Several special nodes have been identified such as Rate-1, Rate-0, repetition (REP) and single parity check (SPC) nodes, which enabled high latency and throughput gains. Despite the latency and throughput gains to date, these enhancements are still not sufficient to attain 6G key performance indicators (KPIs) and more aggressive techniques are needed.

[0032] The present disclosure describes techniques for further parallelization of fast simplified successive cancellation (FSSC) decoders. In some implementations, further parallelization is achieved by partitioning the code tree (i.e., the original polar codeword) into multiple subtrees (i.e., polar subcodes). These subtrees are then fed to parallel fast component decoders (FCDs). In certain implementations, each of the subtrees may beindependently searched by one of the FCDs. In various implementations, each FCD may use pattern identification or special node identification. Accordingly, each of these component decoders may include modules for fast decoding of the identified special nodes.

[0033] As used herein, a “fast decoder" refers to a category of decoding algorithm with low computational complexity and fast execution time to facilitate the real-time, or near-real-time, decoding of sophisticated encoding schemes. Examples of fast decoders include the fast successive cancellation decoder, the FSSC decoder, and the like. A component decoder refers to a decoding algorithm used as part of a larger decoding process, e.g., by operating on a partitioned section (or component) of the codeword. Accordingly, a fast component decoder refers to a fast decoder that also operates as a component decoder in the decoding process.

[0034] In some embodiments, one or more of the FCDs may combine sphere decoding (SD) techniques and SCL decoding techniques. SD allows for the pruning of sub-subtrees which fall outside the sphere radius at the cost of additional computational complexity of the enumeration and determination of distance spectrum of the polar codewords. Beneficially, the above techniques allow for higher latency and throughput gains without altering the encoding procedure of polar codes.

[0035] Aspects of the present disclosure are described in the context of a wireless communications system.

[0036] Figure 1 illustrates an example of a wireless communications system 100 in accordance with aspects of the present disclosure. The wireless communications system 100 may include one or more NE 102, one or more UE 104, and a core network (CN) 106. The wireless communications system 100 may support various radio access technologies. In some implementations, the wireless communications system 100 may be a 4G network, such as a Long-Term Evolution (LTE) network or an LTE-Advanced (LTE-A) network. In some other implementations, the wireless communications system 100 may be a New Radio (NR) network, such as a 5G network, a 5G-Advanced (5G-A) network, or a 5G ultrawideband (5G-UWB) network.

[0037] In other implementations, the wireless communications system 100 may be a combination of a 4G network and a 5G network, or other suitable radio access technology(RAT) including Institute of Electrical and Engineers (IEEE) 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20. The wireless communications system 100 may support radio access technologies beyond 5G, for example, 6G. Additionally, the wireless communications system 100 may support technologies, such as time division multiple access (TDMA), frequency division multiple access (FDMA), or code division multiple access (CDMA), etc.

[0038] The one or more NE 102 may be dispersed throughout a geographic region to form the wireless communications system 100. One or more of the NE 102 described herein may be or include or may be referred to as a network node, a base station, a network element, a network function, a network entity, a radio access network (RAN), a NodeB, an eNodeB (eNB), a next-generation NodeB (gNB), or other suitable terminology. An NE 102 and a UE 104 may communicate via a communication link, which may be a wireless or wired connection. For example, an NE 102 and a UE 104 may perform wireless communication (e.g., receive signaling, transmit signaling) over a Uu interface.

[0039] An NE 102 may provide a geographic coverage area for which the NE 102 may support services for one or more UEs 104 within the geographic coverage area. For example, an NE 102 and a UE 104 may support wireless communication of signals related to services (e.g., voice, video, packet data, messaging, broadcast, etc.) according to one or multiple radio access technologies. In some implementations, an NE 102 may be moveable, for example, a satellite associated with a non-terrestrial network (NTN). In some implementations, different geographic coverage areas associated with the same or different radio access technologies may overlap, but the different geographic coverage areas may be associated with different NE 102.

[0040] The one or more UE 104 may be dispersed throughout a geographic region of the wireless communications system 100. A UE 104 may include or may be referred to as a remote unit, a mobile device, a wireless device, a remote device, a subscriber device, a transmitter device, a receiver device, or some other suitable terminology. In some implementations, the UE 104 may be referred to as a unit, a station, a terminal, or a client, among other examples. Additionally, or alternatively, the UE 104 may be referred to as an internet-of-things (IoT) device, an internet-of-everything (IoE) device, or machine- type communication (MTC) device, among other examples.

[0041] A UE 104 may be able to wireless communication directly with other UEs 104 over a communication link. For example, a UE 104 may support wireless communication directly with another UE 104 over a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular-V2X deployments, the communication link may be referred to as a sidelink. For example, a UE 104 may support wireless communication directly with another UE 104 over a PC5 interface.

[0042] An NE 102 may support communications with the CN 106, or with another NE 102, or both. For example, an NE 102 may interface with other NE 102 or the CN 106 through one or more backhaul links (e.g., S1, N2, N3, or network interface). In some implementations, the NE 102 may communicate with each other directly. In some other implementations, the NE 102 may communicate with each other or indirectly (e.g., via the CN 106). In some implementations, one or more NE 102 may include subcomponents, such as an access network entity, which may be an example of an access node controller (ANC). An ANC may communicate with the one or more UEs 104 through one or more other access network transmission entities, which may be referred to as a radio heads, smart radio heads, or transmission-reception points (TRPs).

[0043] The CN 106 may support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. The CN 106 may be an evolved packet core (EPC), or a 5G core (5GC), which may include a control plane entity that manages access and mobility (e.g., a mobility management entity (MME), an access and mobility management functions (AMF)) and a user plane entity that routes packets or interconnects to external networks (e.g., a serving gateway (S-GW), a Packet Data Network (PDN) gateway (P-GW), or a user plane function (UPF)). In some implementations, the control plane entity may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signal bearers, etc.) for the one or more UEs 104 served by the one or more NE 102 associated with the CN 106.

[0044] The CN 106 may communicate with a packet data network over one or more backhaul links (e.g., via an S1, N2, N3, or another network interface). The packet data network may include an application server. In some implementations, one or more UEs 104 may communicate with the application server. A UE 104 may establish a session(e.g., a protocol data unit (PDU) session, or PDN connection, or the like) with the CN 106 via an NE 102. The CN 106 may route traffic (e.g., control information, data, and the like) between the UE 104 and the application server using the established session (e.g., the established PDU session). The PDU session may be an example of a logical connection between the UE 104 and the CN 106 (e.g., one or more network functions of the CN 106).

[0045] In the wireless communications system 100, the NEs 102 and the UEs 104 may use resources of the wireless communications system 100 (e.g., time resources (e.g., symbols, slots, subframes, frames, or the like) or frequency resources (e.g., subcarriers, carriers)) to perform various operations (e.g., wireless communications). In some implementations, the NEs 102 and the UEs 104 may support different resource structures. For example, the NEs 102 and the UEs 104 may support different frame structures. In some implementations, such as in 4G, the NEs 102 and the UEs 104 may support a single frame structure. In some other implementations, such as in 5G and among other suitable radio access technologies, the NEs 102 and the UEs 104 may support various frame structures (i.e., multiple frame structures). The NEs 102 and the UEs 104 may support various frame structures based on one or more numerologies.

[0046] One or more numerologies may be supported in the wireless communications system 100, and a numerology may include a subcarrier spacing and a cyclic prefix. A first numerology (e.g., ^=0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first numerology (e.g., ^=0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one slot per subframe. A second numerology (e.g., ^=1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third numerology (e.g., ^=2) may be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth numerology (e.g., ^=3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth numerology (e.g., ^=4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

[0047] A time interval of a resource (e.g., a communication resource) may be organized according to frames (also referred to as radio frames). Each frame may have a duration, for example, a 10 millisecond (ms) duration. In some implementations, eachframe may include multiple subframes. each frame may include 10 subframes, and each subframe may have a duration, for example, a 1 ms duration. In some implementations, each frame may have the same duration. In some implementations, each subframe of a frame may have the same duration.

[0048] Additionally or alternatively, a time interval of a resource (e.g., a communication resource) may be organized according to slots. For example, a subframe may include a number (e.g., quantity) of slots. The number of slots in each subframe may also depend on the one or more numerologies supported in the wireless communications system 100. For instance, the first, second, third, fourth, and fifth numerologies (i.e., ^=0, ^=1, ^=2, ^=3, ^=4) associated with respective subcarrier spacings of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single slot per subframe, two slots per subframe, four slots per subframe, eight slots per subframe, and 16 slots per subframe, respectively.

[0049] Each slot may include a number (e.g., quantity) of symbols (e.g., orthogonal frequency domain multiplexing (OFDM) symbols). In some implementations, the number (e.g., quantity) of slots for a subframe may depend on a numerology. For a normal cyclic prefix, a slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable for 60 kHz subcarrier spacing), a slot may include 12 symbols. The relationship between the number of symbols per slot, the number of slots per subframe, and the number of slots per frame for a normal cyclic prefix and an extended cyclic prefix may depend on a numerology. It should be understood that reference to a first numerology (e.g., ^=0) associated with a first subcarrier spacing (e.g., 15 kHz) may be used interchangeably between subframes and slots.

[0050] In the wireless communications system 100, an electromagnetic (EM) spectrum may be split, based on frequency or wavelength, into various classes, frequency bands, frequency channels, etc. By way of example, the wireless communications system 100 may support one or multiple operating frequency bands, such as frequency range designations FR1 (410 MHz – 7.125 GHz), FR2 (24.25 GHz – 52.6 GHz), FR3 (7.125 GHz – 24.25 GHz), FR4 (52.6 GHz – 114.25 GHz), FR4a or FR4-1 (52.6 GHz – 71 GHz), and FR5 (114.25 GHz – 300 GHz). In some implementations, the NEs 102 and the UEs 104 may perform wireless communications over one or more of the operating frequency bands. In some implementations, FR1 may be used by the NEs 102 and theUEs 104, among other equipment or cellular communications traffic (e.g., control information, data). In some implementations, FR2 may be used by the NEs 102 and the UEs 104, among other equipment or devices for short-range, high data rate capabilities.

[0051] FR1 may be associated with one or multiple numerologies (e.g., at least three numerologies). For example, FR1 may be associated with a first numerology (e.g., ^=0), which includes 15 kHz subcarrier spacing; a second numerology (e.g., ^=1), which includes 30 kHz subcarrier spacing; and a third numerology (e.g., ^=2), which includes 60 kHz subcarrier spacing. FR2 may be associated with one or multiple numerologies (e.g., at least 2 numerologies). For example, FR2 may be associated with a third numerology (e.g., ^=2), which includes 60 kHz subcarrier spacing; and a fourth numerology (e.g., ^=3), which includes 120 kHz subcarrier spacing.

[0052] Wireless communication in unlicensed spectrum (also referred to as “shared spectrum”) in contrast to licensed spectrum offer some obvious cost advantages allowing communication to obviate overlaying operator’s licensed spectrum and rather use license free spectrum according to local regulation in specific geographies. From the third generation partnership project (3GPP) technology perspective, the unlicensed operation can be on the Uu interface (referred to as NR-U) or also on sidelink interface (e.g., SL-U).

[0053] For initial access, a UE 104 detects a candidate cell and performs downlink (DL) synchronization. For example, the gNB (e.g., an embodiment of the NE 102) may transmit a synchronization signal and physical broadcast channel (SS / PBCH) transmission, referred to as a synchronization signal block (SSB). In various embodiments, the SSB comprises the primary synchronization signal (PSS), the secondary synchronization signal (SSS), and the master information block (MIB). The synchronization signal (i.e., comprising the PSS and SSS) is a predefined data sequence known to the UE 104 (or derivable using information already stored at the UE 104) and is in a predefined location in time relative to frame / subframe boundaries, etc. The UE 104 searches for the SSB and uses the SSB to obtain DL timing information (e.g., symbol timing) for the DL synchronization. The UE 104 may also decode system information (SI) based on the SSB. Note that with beam-based communication, each DL beam may be associated with a respective SSB.

[0054] After performing DL and acquiring essential system information, such as the MIB and the system information block type 1 (SIB1), the UE 104 performs uplink (UL) synchronization and resource request by performing a random- access procedure, referred to as “RACH procedure” by selecting and transmitting a preamble on the physical random access channel (PRACH). The PRACH preamble is transmitted during a random access channel (RACH) occasion, i.e., a predetermined set of time-frequency resources that are available for the reception of the PRACH preamble. Note that with beam-based communication, the UE 104 may select a certain DL beam and transmit the PRACH preamble on a corresponding UL beam. In such embodiments, there may be a mapping between SSB and RACH occasion, allowing the network to determine which beam the UE 104 has selected.

[0055] Regarding random access, two types of RACH procedure are supported in a 3GPP wireless communication network: A) a 4-step random-access (RA) type initiated by the sending of a RACH message 1 (Msg1) and 2-step RA type with RACH message A (MsgA). Both types of RACH procedure support contention-based random access (CBRA) and contention-free random access (CFRA).

[0056] The UE 104 selects the RA type at the initiation of the RACH procedure, e.g., based on network configuration. In one example, when CFRA resources are not configured, a reference signal received power (RSRP) threshold is used by the UE 104 to select between 2-step RA type and 4-step RA type. In another example, when CFRA resources for 4-step RA type are configured, the UE 104 performs random access with 4- step RA type. In another example, when CFRA resources for 2-step RA type are configured, the UE 104 performs random access with 2-step RA type.

[0057] Note that the network does not configure CFRA resources for 4-step and 2- step RA types at the same time for a bandwidth part (BWP). Additionally, the CFRA with 2-step RA type is only supported for handover.

[0058] The Msg1 of the 4-step RA type consists of a preamble transmitted on a physical random access channel (PRACH). After the Msg1 transmission, the UE 104 monitors for a response from the network within a configured window. For CFRA, a dedicated preamble for Msg1 transmission is assigned by the network and upon receiving a random access response (RAR) from the network, the UE 104 ends the random access procedure. For CBRA, upon reception of the RAR, the UE 104 sends a RACH message 3(Msg3) using a UL grant scheduled in the and monitors for contention resolution. If contention resolution is not successful after Msg3 (re)transmission(s), then the UE 104 goes back to Msg1 transmission.

[0059] The MsgA of the 2-step RA type includes a preamble on the PRACH and a payload on a physical uplink shared channel (PUSCH). After the MsgA transmission, the UE 104 monitors for a response from the network within a configured window. For CFRA, a dedicated preamble and PUSCH resource are configured for MsgA transmission and upon receiving the network response, the UE 104 ends the random access procedure. For CBRA, if contention resolution is successful upon receiving the network response, then the UE 104 ends the random access procedure; however, if a fallback indication is received in a RACH message B (MsgB), the UE 104 performs Msg3 transmission using the UL grant scheduled in the fallback indication and monitors for contention resolution. If contention resolution is not successful after Msg3 (re)transmission(s), the UE 104 goes back to MsgA transmission.

[0060] If the random access procedure with 2-step RA type is not completed after a number of MsgA transmissions, the UE 104 can be configured to switch to CBRA with 4- step RA type.

[0061] In 3GPP New Radio (NR), the gNB may transmit the maximum 64 SSBs and the maximum 64 corresponding copies of physical downlink control channel (PDCCH) and / or physical downlink shared channel (PDSCH) for delivery of SIB1 in high frequency bands (e.g., 28 GHz). This may cause significant network energy consumption even for a very low traffic load condition. According to 3GPP Technical Report (TR) 38.864 (v18.1.0), for network energy savings, on-demand SSB and / or SIB1 (SSB / SIB1) transmissions and a cell without SSB / SIB1 transmission were considered. When a cell does not transmit SSB / SIB1, for a UE 104 to access the cell, the UE 104 should obtain SI of the cell from other associated carriers / cells and synchronize from other associated carriers / cells. When a cell is in a long period of cell inactivity, a UE 104 served by the cell can trigger SSB / SIB1 transmissions by sending a request to the cell.

[0062] Figure 2 illustrates an example of a protocol stack 200, in accordance with aspects of the present disclosure. In some embodiments, the protocol stack 200 may be an NR protocol stack used in a 5G NR system. While Figure 2 shows a UE 206, a RAN node 208, and a 5G core network (5GC) 210 (e.g., comprising at least an AMF), these arerepresentative of a set of UEs 104 an NE 102 (e.g., base station) and a CN 106. As depicted, the protocol stack 200 comprises a user plane protocol stack 202 and a control plane protocol stack 204. The user plane protocol stack 202 includes a physical (PHY) layer 212, a medium access control (MAC) sublayer 214, a radio link control (RLC) sublayer 216, a packet data convergence protocol (PDCP) sublayer 218, and a service data adaptation protocol (SDAP) sublayer 220. The control plane protocol stack 204 includes a PHY layer 212, a MAC sublayer 214, a RLC sublayer 216, and a PDCP sublayer 218. The control plane protocol stack 204 also includes a radio resource control (RRC) layer 222 and a non-access stratum (NAS) layer 224.

[0063] The access stratum (AS) layer 226 (also referred to as “AS protocol stack”) for the user plane protocol stack 202 consists of at least SDAP, PDCP, RLC and MAC sublayers, and the physical layer. The AS layer 228 for the control plane protocol stack 204 consists of at least RRC, PDCP, RLC and MAC sublayers, and the physical layer. The layer-1 (L1) includes the PHY layer 212. The layer-2 (L2) is split into the SDAP sublayer 220, PDCP sublayer 218, RLC sublayer 216, and MAC sublayer 214. The layer- 3 (L3) includes the RRC layer 222 and the NAS layer 224 for the control plane and includes, e.g., an internet protocol (IP) layer and / or PDU Layer (not depicted) for the user plane. L1 and L2 are referred to as “lower layers,” while L3 and above (e.g., transport layer, application layer) are referred to as “higher layers” or “upper layers.”

[0064] The PHY layer 212 offers transport channels to the MAC sublayer 214. The PHY layer 212 may perform a beam failure detection procedure using energy detection thresholds, as described herein. In certain embodiments, the PHY layer 212 may send an indication of beam failure to a MAC entity at the MAC sublayer 214. The MAC sublayer 214 offers logical channels to the RLC sublayer 216. The RLC sublayer 216 offers RLC channels to the PDCP sublayer 218. The PDCP sublayer 218 offers radio bearers to the SDAP sublayer 220 and / or RRC layer 222. The SDAP sublayer 220 offers QoS flows to the core network (e.g., 5GC). The RRC layer 222 provides for the addition, modification, and release of carrier aggregation and / or dual connectivity. The RRC layer 222 also manages the establishment, configuration, maintenance, and release of signaling radio bearers (SRBs) and data radio bearers (DRBs).

[0065] The NAS layer 224 is between the UE 206 and an AMF in the 5GC 210. NAS messages are passed transparently through the RAN. The NAS layer 224 is used tomanage the establishment of and for maintaining continuous communications with the UE 206 as it moves between different cells of the RAN. In contrast, the AS layers 226 and 228 are between the UE 206 and the RAN (i.e., RAN node 208) and carry information over the wireless portion of the network. While not depicted in Figure 2, the IP layer exists above the NAS layer 224, a transport layer exists above the IP layer, and an application layer exists above the transport layer.

[0066] The MAC sublayer 214 is the lowest sublayer in the L2 architecture of the NR protocol stack. Its connection to the PHY layer 212 below is through transport channels, and the connection to the RLC sublayer 216 above is through logical channels. The MAC sublayer 214 therefore performs multiplexing and demultiplexing between logical channels and transport channels: the MAC sublayer 214 in the transmitting side constructs MAC PDUs (also known as transport blocks (TBs)) from MAC service data units (SDUs) received through logical channels, and the MAC sublayer 214 in the receiving side recovers MAC SDUs from MAC PDUs received through transport channels.

[0067] The MAC sublayer 214 provides a data transfer service for the RLC sublayer 216 through logical channels, which are either control logical channels which carry control data (e.g., RRC signaling) or traffic logical channels which carry user plane data. On the other hand, the data from the MAC sublayer 214 is exchanged with the PHY layer 212 through transport channels, which are classified as UL or downlink (DL). Data is multiplexed into transport channels depending on how it is transmitted over the air.

[0068] The PHY layer 212 is responsible for the actual transmission of data and control information via the air interface, i.e., the PHY layer 212 carries all information from the MAC transport channels over the air interface on the transmission side. Some of the important functions performed by the PHY layer 212 include coding and modulation, link adaptation (e.g., adaptive modulation and coding (AMC)), power control, cell search and random access (for initial synchronization and handover purposes) and other measurements (inside the 3GPP system (i.e., NR and / or LTE system) and between systems) for the RRC layer 222. The PHY layer 212 performs transmissions based on transmission parameters, such as the modulation scheme, the coding rate (i.e., the modulation and coding scheme (MCS)), the number of physical resource blocks (PRBs), etc.

[0069] Note that an LTE protocol similar structure to the protocol stack 200, with the differences that the LTE protocol stack lacks the SDAP sublayer 220 in the AS layer 226, that an EPC replaces the 5GC 210, and that the NAS layer 224 is between the UE 206 and an MME in the EPC. Also note that the present disclosure distinguishes between a protocol layer (such as the aforementioned PHY layer 212, MAC sublayer 214, RLC sublayer 216, PDCP sublayer 218, SDAP sublayer 220, RRC layer 222 and NAS layer 224) and a transmission layer in multiple-input multiple-output (MIMO) communication (also referred to as a “MIMO layer” or a “data stream”).

[0070] Enhanced ultra-reliable low-latency communications (eURLLC) in 6G requires a significantly lower end-to-end latency (e.g., less than 1ms) compared to the 5G new radio (NR), and a high level of transmission reliability, requiring a block error rate (BLER) of less than 10^(-7). eURLLC will enable emerging applications, such as future factory applications, tactile internet, distributed utility grid, and metaverse, as well as mission-critical applications, such as telesurgery, autonomous driving and factory automation.

[0071] Figure 3 depicts future 5G-advanced and / or 6G use cases and different target requirements. Table 1 describes target requirements of some of these use cases. Table 1: Examples of ultra-reliable low latency use cases and their target requirements Scenario End-to-end latency Reliability Discrete automation – motion control 1 ms 99.9999% Electricity distribution – high voltage 5 ms 99.9999% Remote control 5 ms 99.999% Discrete automation 10 ms 99.99% Intelligent transport systems – infrastructure backhaul 10 ms 99.9999% Process automation – remote control 50 ms 99.9999% Process automation – monitoring 50 ms 99.9% Electricity distribution – medium voltage 25 ms 99.9%

[0072] Polar codes have been the active research in recent times, mainly since they are the first ever provably capacity achieving codes, with explicit construction and very low complexity of encoding and decoding. The polar codes were invented by Erdal Arikan, using a novel concept called channel polarization. Soon after, both the concept of channel polarization as well as polar codes have been extended to several applications and generalizations.

[0073] Consider W: X → Y to denote a generic binary-input, discrete, memoryless channels (B-DMC) with input alphabet X, output alphabet Y, and transition probabilities W (y|x), x ∈ X , y ∈ Y. The input alphabet X will always be {0,1}, the output alphabet and the transition probabilities may be arbitrary. We write ^^to denote the channel corresponding to N uses of W; thus, ^^ : ^^→ ^^ with ^^^^^^ |^^^ ) = ∏^^^^ ^^^^|^^) .

[0074] Given a B-DMC W, there are two channel parameters of primary interest, the symmetric capacity ^^^)and the Bhattacharyya parameter ^^^), which are defined as follows: ^^^) = 1^ ^^∈^ ^∈^2 ^^^|^) log^ ^^^|^)1 ) 2^^^|0) + 12 ^^^|1)^^^) ≜ ^ !^^^|0)^^^|1)

[0075] These reliability, respectively. I(W) is the highest rate at which reliable communication is possible across W using the inputs of W with equal frequency. Z(W) is an upper bound on the probability of maximum-likelihood (ML) decision error when W is used only once to transmit a 0 or 1. It is easy to see that Z(W) takes values in [0 ,1], whereby a 0 indicates a null probability of error in ML-sense, and respectively, a 1 indicates a certain probability of error in ML- sense.

[0076] Channel polarization is an operation by which one manufactures out of N independent copies of a given B-DMC W, a second set of N channels {^^^)^ : 1 ≤ i ≤ N} that show a polarization effect in the sense that, as N becomes large,symmetriccapacity terms {I(^^^)^ )} tend towards 0 or all but a vanishing fraction of indices i. This operation consists of a channel combining phase and a channel splitting phase.

[0077] Regarding channel combining, this phase combines copies of a given B-DMC W in a recursive manner to produce a vector channel ^^: ^^→ ^^, where N can be anypower of two, " = 2#, n ≥ 0. The recursion begins at the 0-th level (n = 0) with only onecopy of W and we set ^^ ≜ ^.

[0078] Figure 4 depicts a block diagram of channel combining, in accordance with aspects of the present disclosure. The first level (n = 1) of the recursion combines two independent copies of ^^(as shown in Figure 4) and obtains the channel ^$: ^$→ ^$with the transition probabilities: ^$^^^ , ^$|&^, &$) = ^^^^|&^ ⊕ &$) ^^^$| &$)

[0079] channel ^^out of ^^, the next step of channel polarization is to split ^^back into a set of N binary-inputcoordinate channels ^^^)^ : ^ → ^^ × ^^+^, 1 ≤ i ≤ N, defined by the transitionprobabilities: ^^^) ^ ^+ ^^ ,^^ , & ^^ -&^) ≜ ∑2 / 341 ∈ ^ / 03$ / 01 ^^ ^^^^ |&^^ )where (^^, &^+^^ )anunderstanding of the channels {^^^)a genie-aided successive decoder in which the ith est^imates &^after observing ^^and the past channel inputs &^+^(supplied correctly by theregardless of any decision errors earlier stages). If &^^is a-priori uniform on ^^, then ^^^)^ is the effective channel seen by the ithin this scenario.

[0080] Figure 5 depicts the effects of channel polarization. It is a well-known result that for any B-DMC W, the channels {^^^)^ } polarize in the sense that, for any fixed δ ∈ (0, 1), as N goes to infinity throughof two, the fraction of indices i ∈ {1, ... , N} for which I(^^^)) ∈ (1 − δ, 1] goes to I(W) a^^)^ nd the fraction for which I(^^) ∈ [0, δ) goes to 1−I(W).

[0081] Let 5 = 61 01 17, 5^# is a " × known as the Kernel or the polar basematrix, where " 9 − ;ℎ Kronecker power, and 5^# = 5^5^^#+^).Let the n-bitof integer = be >#+^, >#+$, … >@ . The n-bitrepresentation >@ , >^ , … , ># is a bit-reversal order of =. The generator matrix of polar codeis defined as A ^#^= B^5 , where B^ is a bit- permutation matrix. The polarcode is generated by: ^^ = &^A = ^ ^#^ ^ ^ &^ B^5where ^^^ = ^^^, ^$, … ^^) is the encoded bit sequence, and &^^ = ^&^, &$, … &^) is thebit sequence. The bit indexes of &^^are divided two subsets: the onethe information bits and the containing bits. For simplicity,the frozen bits are set “0”.

[0082] The main idea of polar codes encoding is the splitting of data sequence indexes into two different sets before transmission. The first set includes the indexes of the data to be transmitted on the noise-free channels. The other set includes the indexes corresponding to the known frozen bits to be transmitted on the pure-noise channel. Over the last decades, many techniques were introduced to construct polar codes. The traditional technique suggested by Arikan was based on Bhattacharyya parameter bounds. This technique has the least complexity relative to all other proposed techniques. In addition, Arikan suggested Monte-Carlo estimation approach that could be used to construct polar codes; however, this approach has higher complexity than the other techniques.

[0083] Mori and Tanaka proposed a density evolution (DE) technique. This technique approximates the exact transition probability of each binary input channel to overcome difficulties in calculating the actual values of the Bhattacharyya parameter. Recently, a Gaussian approximation (GA) technique has been proposed to construct polar codes by Trifonov. This technique estimates a bit channel metric inversely proportional to a defined Q-function, which represents its bit error rate (BER) under Gaussian approximation. Mostly, all these techniques are equally good in improving the signal-to- noise ratio (SNR) for additive white Gaussian noise (AWGN) channel.

[0084] Polar codes construction depends on the Bhattacharyya parameter bounds. In this case, first a generalized upper and lower bound of Bhattacharyya parameter aredetermined. In fact, the upper bound of this corresponds to the noisiest channel, while its lower bound corresponds to the lowest noisy channel. Thus, for better performance, it is required to increase the gap between the Bhattacharyya parameter extremes. This increases the polarization of the synthetic channels carrying the information bits. Then, selecting the most appropriate kernel matrix associated with Bhattacharyya parameter constraints as proposed by Karim Al Abassi et al.

[0085] Many techniques are introduced to decode polar codes. Three main techniques considered for decoding are: successive cancellation (SC), successive cancellation list (SCL) and log-likelihood ratio (LLR) based SCL. The SC decoding technique was proposed by Arikan. It was improved to SCL by Tal for a finite small length of polar block codes. Later, Balatsoukas-Stimming proposed LLR-based SCL decoding method.

[0086] As successive cancellation (SC) decoding is sub-optimal for finite length polar codes, successive cancellation list (SCL) decoding was introduced achieving the maximum likelihood (ML) bound for a sufficiently large list size L, at the cost of increased complexity due to the list decoding nature. Further enhancement of the code was conducted via concatenating a high-rate outer code such as Cyclic Redundancy Check (CRC) and parity-check (PC) codes. Under SCL decoding, these CRC-aided polar codes and parity-check concatenated polar codes were shown to outperform the state-of- the-art low-density parity check (LDPC) codes. Later, an extension of polar codes, namely Polar Subcodes, were proposed, outperforming the above-mentioned code constructions.

[0087] However, the SCL decoder is characterized by a high complexity and an inherently serial decoding nature, which in turn reduces the decoding throughput and causes high decoding latency. In addition, SCL decoding is not a good match to iterative detection and decoding due to its hard decision output nature (i.e., not a soft-in / soft-out decoder). Iterative decoding of polar codes based on message passing over the encoding graph has been possible through belief propagation (BP) decoders.

[0088] The BP decoder algorithm enjoys some fundamental advantages over SC- based decoding, as it can be easily parallelized, thus high throughput / low latency implementations are possible, and it inherently enables soft-in / soft-out decoding, facilitating joint iterative detection and decoding. Thus, BP decoding is a promising candidate for high data rate and low latency demanding applications. A belief propagationlist (BPL) decoder with comparable to the successive cancellation list (SCL) decoder of polar codes, which already achieves the maximum likelihood (ML) bound of polar codes for sufficiently large list size L, was also proposed.

[0089] Although the SC decoding algorithm seems unsuitable for high-throughput applications due to its serial nature, state-of-the-art SC decoders managed to significantly simplify and parallelize the decoding process such that the area efficiency of SC decoding has far exceeded that of belief propagation (BP) decoding for low-density parity check codes (LDPC). In particular, these works represent SC decoding as a binary tree traversal, with each subtree therein representing a shorter polar code.

[0090] Figure 6A depicts an example of binary tree traversal in accordance with aspects of the present disclosure. The binary tree search process that starts from the root node to the leaf node and from the left branch to the right. At the p-th (0 ≤ p ≤ n) level of the decoding tree, each parent node referred as CD, has a lefD+^^ t child node C$^+^and aright child node CD+^$^ , where 1 ≤ i ≤29 − E.

[0091] messaging associated with the binary tree traversal, in accordance with aspects of the present disclosure. There are two types ofmessages, i.e., the soft LLRs FD^ [1: 2E] that are propagated from the parent node to theirchild nodes, and the hard codeword ID^ [1: 2E] that is propagated from the child nodes totheir parent node in return.

[0092] The original SC decoding algorithm traverses the tree by visiting all the nodes and edges, leading to high decoding latency. Simplified SC decoders can fast decode certain subtrees (shorter polar codes) and thus "prune" those subtrees. The resulting decoding latency is largely determined by the number of remaining edges and nodes in the pruned binary tree.

[0093] The fast simplified successive cancellation (FSSC) decoding algorithm can be significantly simplified for some nodes with special information and frozen bit patterns. In particular, four types of special nodes, i.e., Rate-0, Rate-1, REP and SPC, are considered in the FSSC decoder, and their structures are described as follows: Rate-0 → all bits are frozen bits, c = {0, 0, … , 0}; Rate-1 → all bits are information bits, c = {1, 1, …, 1}; REP → all bits are frozen bits except the rightmost one, c = {0, …., 0, 1}; SPC → all bits are information bits except the leftmost one, c = {0, 1, …., 1}.

[0094] As used herein, a “frozen bit” to a specific bit position in the information block that is predetermined and known to both the transmitter and the receiver. Frozen bits are crucial elements of the polarization process in polar coding, wherein certain bit positions are selectively frozen, meaning their values are fixed and not allowed to change during encoding or decoding. These frozen bits are typically chosen based on their positions in the binary sequence and their impact on achieving reliable communication over the channel.

[0095] The purpose of freezing certain bits is to ensure that the most reliable channels are utilized for transmitting important information (these are referred to as “information bits”), while less reliable channels are effectively “frozen” to minimize errors. By freezing certain bits, polar coding can achieve the capacity of the channel while maintaining low encoding and decoding complexity.

[0096] Moreover, further enhancements to the FSSC decoding speed were achieved by identifying five additional special nodes along with their efficient SC decoders. In addition, some works have also identified a new class of multi-node information and frozen bit patterns, namely SR0 / REP node, which includes most of the existing special nodes as special cases.

[0097] Figure 7 depicts a generalized structure 700 of a SR0 / REP node, in accordance with aspects of the present disclosure. For an SR0 / REP node at level p, all its descendants are Rate-0 or REP nodes except the rightmost one at level q, which is a generic source node.

[0098] Sphere decoding is a depth-first tree search, it can find the closest decoded sequence from the received sequence in codeword space under the radius constraint. Similar to maximum-likelihood (ML), SD algorithm can solve the problem by enumerating the possible sequence J satisfying the sphere constraint: K^J^) ≜ ‖^ − ^1 − 2J ‖$ $^ A) ≤ Nwhere N denotes the radius for the SD search and K^J^^ )is the squared Euclidean distance along with the sequence J^^.

[0099] MultiSphere a more enhanced sphere decoding (SD) tree partitioning method, which adjusts to the transmission channel while achieving ML performance. The partitioning can take place offline, based on the average channelcharacteristics, or “on-the-fly”, when the channel changes after each QR decomposition. This adds preprocessing latency to that of the QR decomposition (i.e., a decomposition of a matrix A into a product A = QR of an orthonormal matrix Q and an upper triangular matrix R). However, the partitioning latency scales linearly with the number of transmit antennas 9Oin contrast to the QR decomposition latency which scales almost cubically with the number of transmit antennae.

[0100] After SD partitioning, MultiSphere applies a new symbol-to-subtree allocation method which efficiently maps nodes to processing elements (PEs) without introducing dependencies and minimizes the number of redundant calculations across PEs. Each PE performs depth-first subtree traversal with Schnorr-Euchner enumeration, according to which, nodes are visited in ascending order of their partial Euclidean distances (PDs).

[0101] Several approaches have been proposed to avoid exhaustively calculating and sorting the PDs. However, they are not applicable to MultiSphere since their ordering is sequential (to find the P;ℎ smallest PD, the (P − 1) ;ℎ smallest PDs must be found first, starting from P = 1). In addition, a new tree traversal and enumeration method is introduced for meeting MultiSphere’s needs. MultiSphere runs the parallel SDs in a nearly independent form. They interact only once, after they have all reached the first leaf node. Then, the N$of each subtree is replaced by the value of the leaf node with the minimum PD across all parallel SDs. The search is terminated when all parallel trees have been searched. Then, the detection output is the leaf node with the minimum PD across all subtrees and the overall processing latency is determined by the slowest parallel SD.

[0102] As noted above, one of the bottlenecks for achieving 6G eURLLC and eMBB targeted low latencies and extremely high throughputs (Tbit / s) are polar codes decoding delays and lack of parallelization. Despite the latency and throughput gains of conventional polar code SCL decoders, current techniques are still insufficient to attain 6G KPIs.

[0103] The solutions of the present disclosure describe various techniques, mechanisms and procedures to further enhance and parallelize the fast simplified successive cancellation (FSSC) decoder. These techniques allow for the polar code tree partitioning into independent subtrees that are allocated to each of the parallel fast component decoders (FSD). Each of the component decoders further uses special nodes’ identification and implement modules to fast decode these special nodes (also referred toas special kernels). This could further decoding latency at each component decoder and allow higher throughput.

[0104] As used herein, a “special node” refers to a specific type of node in the decoding algorithm that facilitates quicker and more efficient computation and reliability of the decoding. The special nodes in polar coding correspond to specific patterns of information and frozen bits that are common or particularly useful. The special nodes exploit the structure of polar codes to optimize the decoding process, thereby achieving low decoding latency while maintaining high decoding performance. A special node may also be referred to as a special kernel.

[0105] As used herein, a “kernel” refers to a subcode that exhibits certain properties. Kernels are typically chosen based on their ability to transform the reliability of the channels, ensuring that the resulting polar code achieves capacity with low encoding and decoding complexity. The kernel represents the building block used in the recursive construction of the polar code.

[0106] The tree partitioning procedure may be based on techniques that leverage the special properties of the Kernel / base matrix of Polar codes or on a MultiSphere SD-like decoding technique. In the latter case, the partitioning adapts to the transmission channel and is based on path metrics that are based on the enumeration and determination of distance spectrum (Hamming distance) of different polar subcodes. The techniques presented in this disclosure may be summarized as follows:

[0107] The code tree representing the received polar codeword ^^Qof length R is partitioned into "STsubtrees (polar subcodes), where "STrepresents the number of parallel component SC / SCL decoders. Each of these binary subtrees is searched in an independent and fast manner by each of the fast component decoders (FCD).

[0108] According to embodiments of a first solution, the received polar codeword of size R is decomposed, according to the special characteristics of the Kernel / base polar matrix, into multiple polar subcodes of length R / "ST. Each of the fast component decoders (FCD), receives as an input, a polar subcode of length R / "STand performs code tree search methods over the subtree and outputs log-likelihood ratios of the combined received bits that could be detected using a shared detection block that decodes the codeword based on the combined log-likelihood ratios from different componentdecoders. The parallel decoder enables "STdecoding speed. In another embodiment, tree partitioning is based on MultiSphere tree partitioning of the polar codewords which adapt to the transmission channel and is based on the determination of path metrics.

[0109] According to embodiment of a second solution, each fast component decoder includes the implementation of modules that enable the fast decoding of special nodes. Different special nodes may be identified within the subtrees based on the frozen and information bits’ patterns. The fast decoding could also be further enhanced using sub- subtree pruning using an SD-like approach. In this case, all nodes and their dependencies that fall outside the SD squared radius may be pruned prior to any tree search procedure. This comes with additional computational complexity mainly for enumerating and determining the polar code distance spectrum but allows a faster tree traversal.

[0110] Note that the decoding enhancements presented herein may be implemented within the UE, or the base station (BS), or any network entity that transmits and receives data over a noisy channel. The channel is assumed to be an additive white Gaussian noise (AWGN) channel.

[0111] According to aspects of the first solution, the received polar codeword ^ of length R is decomposed into multiple polar subcodes each with a block size R / "ST, where "STis the number of processing elements or fast decoder components. Accordingly, the decomposition of y may be expressed as follows: ^Q Q / ^ $^ = ^^ VW^ , ^ Q / ^VWQ , … . , ^^Q^+^)Q) ^X^ VW X^

[0112] Each ofone of the parallel fast component decoders (FCD) which perform a tree traversal search technique over the polar subcode. This enables higher gains in terms of latency and throughput without altering the error correction performance of polar codes and the hardware implementation complexity of the encoder and decoder. This technique allows to reduce the decoding latency by an "STfactor.

[0113] In one implementation, "STmay be determined based on the code block length R e.g such as the ratio R / "STis an even number. The choice of "STcould also be based on the number of parallel processing elements (PEs) or component decoders (CDs)e.g., in Many-Processor systems on Chips , a PE can be a different processor, in field programmable gate array (FPGA) designs it can be a specifically allocated part of the FPGA chip and in graphics processing unit (GPU) implementations the PE can be a separate thread, or a combination thereof.

[0114] In a first embodiment of the first solution, within each of the component decoders, prior to the code subtree search, the subtrees may be further partitioned and parallelized into multiple parallel modules that fast decode special nodes without searching the trees.

[0115] In a second embodiment of the first solution, the polar code tree may be partitioned based on the special characteristics of the Kernel matrix or according to a MultiSphere SD-like approach.

[0116] Both techniques enable the construction of independent subtrees which may be searched by parallel independent component decoders. The tree partitioning of the received codeword may be performed based on the special characteristics of the polar code Kernel matrix.

[0117] Figure 8 depicts an exemplary decoder 800 that implements tree partitioning into two parallel SC code tree decoders, in accordance with aspects of the presentdisclosure. In this case, for " = 2, due to the special structure of ma ^#ST trix 5 , a polarcodeword may be expressed as: ^^#+^)^Q^ = &Q^ BQ × Z5 0 [[QQ^Q = / $are

[0119] At the receiver, the received ^Q Q Q^ = ℎ^^ + `^ may bedecomposed into ^^Q / $and ^^Q, each is then fed to a fast decoder as shown _X^in Figure 8, where the decoding procedure at each of the parallel decoders is independent of others. The log-likelihood ratios (LLRs) of the input ^^Q / $and ^^Qto different _X^component decoders may be expressed as follows: QQfNQ^^)c^$^ , ]d^^+^)^ g ]^ = 0 )) )0 )aabQ^^)c^QQ , >h^^+^) X^^ e = log^ $ $) $$ X^fNQ^^)c^QQ h^^+^)X , >^ g >^ = 1 )$ $ ^

[0120] However, a detection block, as shown in Figure 8, is common to all component decoders, this is due to the correlation of ]^ / $ ^ / $^ and >^.

[0121] For "ST = 4, a proposed parallel SC decoder consists of four componentdecoders. The four component decoders use ^^Q / j, ^ Q / $ lQ / j ^ , ^ and ^mQ^as inputs to kX^ ^ X^ k X^decode ]Q / j, >Q / j Q / j Q / j^ , n^ , o^ ,calculatelikelihood ratios: ^ ^ a= a^^)k , ]d^^+^) , a =^^)_ h^^+^)^^)lQ / j ^^+^)^c^^ ^ e a^c^, >^ e , ar = a^c^, n e , at =^Xk ^X_ ^X k )are decoded first, bythe equally combined log likelihood ratios: d^,d ,d Q ,d lQ

[0123] Figure 9 depicts an alternative 900, that implements tree partitioning into "STparallel SC code tree decoders, in accordance with aspects of the present disclosure. In this case, the Kernel matrix 5^#is further decomposed (i.e., as compared to the decomposition of Figure 8), and multiple component decoders (where the number of parallel component decoders is "ST) may be implemented in parallel to decode the resulting polar subcodes.

[0124] Figure 10 depicts an exemplary polar code tree partitioning 1000 in accordance with aspects of the present disclosure. Since the Kernel matrix associated to each of the fast component decoders (FSDs) is a lower triangular matrix, the decoding of each sub-polar code may be translated into a sub-tree search as illustrated in Figure 10.

[0125] In a first implementation, the path searching process at each component decoder could include special node identification within the subtree and subtree pruning to avoid visiting same nodes multiple times and thus enable higher decoding latency and throughput gains.

[0126] In an alternate embodiment, the component decoders could perform LLR- based successive cancellation list (SCL) decoding over the polar code subtrees. In this case, each of the component SCL decoders outputs the L best paths and their corresponding path metrics (e.g., metric computation unit MCU, or any other path metric). The detection block generates the combined paths (L / 2L... / "STa), determines the path metrics of the combined paths and finally selects the L survival paths.

[0127] According to a third embodiment of the first solution, the tree partitioning may be performed according to the tree partitioning procedure used for MultiSphere sphere decoding (SD) as described above. In this case, the tree partitioning scheme adjusts to the transmission channel or its statistics instead of leveraging the Kernel matrix properties. MultiSphere runs the parallel component decoders (CDs) in a nearly independent form. They interact only once, after they all have reached the first leaf node.

[0128] The subtree construction for MultiSphere SD may be summarized as including a seed identification phase and a MultiSphere subtree construction phase.

[0129] During the seed identification phase, the decoder determines the "STmost promising paths given the received polar codeword. This determination is based on a metric ℳS^which is function of the distances between the transmitted symbols. Thesemetrics ℳS^characterize each of the the paths that have the smallest metrics are designated. The determination of the metrics ℳS^may be performed offline based on channel statistics or ‘on the fly’ anytime the channel changes.

[0130] During the MultiSphere subtree construction phase, after calculating the "STseeds with metrics ℳS^(= = 1, ..., "ST), each seed is used to construct a corresponding subtree ^^so that the union of all subtrees forms the original polar code tree. The process may be designed so that PEs can independently construct their subtrees in parallel in order to minimize the latency of the procedure.

[0131] Figure 11 depicts an example of MultiSphere tree partitioning 1100 in accordance with aspects of the present disclosure. Figure 11 depicts the construction of subtrees for paths m1, m2, m3, and m4. The union of paths m1, m2, m3, and m4 forms the full Polar code tree. Note that nodes may appear in several subtrees.

[0132] In one embodiment, the path metric ℳS^used to for MultiSphere subtree construction may be determined recursively thanks to the Plotkin construction of polar codes. In this case: ℳ^ = ^X^S^ ℳS^ + ^here ^ is the path cost between the level ^ and the level ^^ + 1). The optimum path metricℳS^should maximize the likelihood probability: ℳS^ = ^ f^^^^Q^ ^^^+^)^ ^f^ ^^^+^)^ = o^^+^)^ )here o^^+^)^ = ^o^could takepossible value. o^, ^ = 1,2 … , ^= − 1) is either +1 or −1 withprobability of 1 / 2.

[0133] The path cost ^ may be expressed as: ^ = ^ T ^r)^^)$|^^r)^ − ^^|$, where ^^ beingthe symbol at level ^ which is closest to the received point. This metric is not function of the received symbols but a function of the ordered distance between transmitted symbols which may be known in advance and can be pre-calculated.

[0134] These distances may be, according to the first implementation, Hamming distances. In this case, the minimum weight distribution (MWD) of the polar code may bedetermined and enumerated using different for example the SD-like procedure, or by transmitting an all zero vector.

[0135] The search is terminated when all parallel trees have been searched. Then, the detection output is the leaf node with the minimum metric ℳS^across all subtrees.

[0136] In the case of MultiSphere SD, the decoding latency may be "STtimes faster than legacy LLR-based SCL decoders without added complexity and hardwareimplementation. The SCL decoder was proved to complete decoding in ^2R + ^ − 2)timesteps, where ^ is the number of information bits. The tree partitioning algorithm presented above reduces the decoding latency by an "STfactor, which makes the ^$QX^+$) decoding process completes in^VWtimesteps. In this case, the larger the number of parallel component decoders and partitioned subtrees, the higher decoding latency gains we could achieve. This MultiSphere SD technique allows high throughput gains as well.

[0137] According to aspects of the second solution, due to the lower triangular structure of the Kernel matrix associated with each component decoders, the decoding of each polar subcode may be viewed as a binary subtree search by each of the component decoders. Each subtree search could include modules at intermediate levels of the subtree that allow fast decoding and subtree ‘pruning’.

[0138] Special nodes are nodes whose leaves present certain patterns of information bits and frozen bits and do not need to be traversed. In this case, FCDs could perform decoding over polar subcodes (or tree search over polar code subtrees) in parallel. This enables further decoding latency gains by implementing modules at each of the parallel component decoders which allow decoding special nodes (or special Kernels) at intermediate levels without traversing the bottom of the tree.

[0139] In one embodiment of the second solution, several special nodes may be identified according to the information and frozen bit patterns they incorporate, e.g., rate- one nodes (all bits are information bits), rate-zero nodes (all bits are frozen bits), REP nodes (all bits are frozen bits except the rightmost one) or SPC nodes (all bits are information bits except the leftmost one) or a combination thereof. Additional special nodes which consist of a combination of the aforementioned special nodes could also be identified and fast decoded such as SR1 / SPC (a sequence of rate 1 or single parity checknodes which can be easily found especially high-rate polar code), SR0 / SPC, SR1 / REP and SR0 / REP.

[0140] In addition to the above, additional special nodes may be associated withspecific rates for example rates {$ l ^^+l) ^^+$)^ ,^ , ^ , ^ }, where ^ is the number of leaf nodes ina subtree. These nodes are 2), repeated parity check (RPC), parity- checked repetition (PCR) andnodes, respectively. These nodes may be fast decoded reusing existing decoding circuits for repetition (REP) and single parity check (SPC).

[0141] In another embodiment of the second solution, partitioning the code tree corresponding to the received codeword into polar subcodes (subtrees) enables the identification of more patterns and special nodes within each subtree which enable further higher latency and throughput gains. For example, this may be achieved by decomposing the received polar codeword such that the sub-polar codewords present certain patterns of information and frozen bits or are a combination of two different special nodes or such that the rate of the sub-polar codes falls into one the above cases of special rates.

[0142] In an alternate embodiment of the second solution, other metrics characterizing the subtrees and allowing for more parallelization of the decoding algorithm may be determined. These metrics enable the evaluation, in the ML sense, of the enumerated polar codewords.

[0143] In a first implementation, these metrics may be partial Euclidean distance (PD) or alternatively, the metric is the minimum weight distance (MWD) of the polar code. These metrics enable the evaluation of the ML performance of the polar code.

[0144] In a second implementation, prior to determining the MCU of each path and using successive cancellation list decoding (SCL), the algorithm may enumerate the codewords and check their corresponding metrics, if it is larger than the squared sphere radius N$, then the descendants of this node, as well as its siblings and all their siblings and all descendants can be safely pruned.

[0145] Figure 12 depicts an example of a binary search tree 1200 using pruning with code length 4 and sphere constraint dmin. The initial squared radius N$may be determined using artificial intelligence (AI) and / or machine learning (ML) methods and may be basedon channel statistics. When a leaf node is with o,^^^)^ < N$, N$ is updated too,^^^)^. Upon meeting a node ^^^), if o^^^^)) > N$, this node, its descendants and itssiblings with all their descendants are excluded from the tree search (i.e., they are pruned). The squared radius N$may be updated a number of times, ^D^2#^, to reduce the number of paths for SCL decoding.

[0146] In such embodiments, ^D^2#^is determined such that the complexity of the codewords enumeration is not high and such as the subtree is sufficiently pruned to reduce decoding latency. In certain embodiments, SCL and SD decoding algorithms are combined at each of the component decoders. This further reduces overall decoding latency at the expense of additional computational complexity at the beginning of the decoding algorithm.

[0147] In an alternate embodiment, the polar subcodes may be decoded using hybrid SCL-ML decoding. In this case, the parallel component decoders may be composed of SCL decoders and maximum likelihood (ML) decoders. For example, the code subtrees which does not present special nodes patterns and thus cannot be pruned and fast decoded using fast simplified SCL decoding may be decoded by ML. This might further allow decoding latency and throughput gains since ML decoding is not sequential as SCL decoders.

[0148] Figure 13 illustrates an example of a UE 1300 in accordance with aspects of the present disclosure. The UE 1300 may include a processor 1302, a memory 1304, a controller 1306, and a transceiver 1308. The processor 1302, the memory 1304, the controller 1306, or the transceiver 1308, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces.

[0149] The processor 1302, the memory 1304, the controller 1306, or the transceiver 1308, or various combinations or components thereof may be implemented in hardware (e.g., circuitry). The hardware may include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, orany combination thereof configured as or supporting a means for performing the functions described in the present disclosure.

[0150] The processor 1302 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a central processing unit (CPU), an ASIC, a field programmable gate array (FPGA), or any combination thereof). In some implementations, the processor 1302 may be configured to operate the memory 1304. In some other implementations, the memory 1304 may be integrated into the processor 1302. The processor 1302 may be configured to execute computer-readable instructions stored in the memory 1304 to cause the UE 1300 to perform various functions of the present disclosure.

[0151] The memory 1304 may include volatile or non-volatile memory. The memory 1304 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1302, cause the UE 1300 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such the memory 1304 or another type of memory. Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non- transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

[0152] In some implementations, the processor 1302 and the memory 1304 coupled with the processor 1302 may be configured to cause the UE 1300 to perform various functions (e.g., operations, signaling) described herein (e.g., executing, by the processor 1302, instructions stored in the memory 1304). In some implementations, the processor 1302 may include multiple processors and the memory 1304 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may be individually or collectively, configured to perform various functions (e.g., operations, signaling) of the UE 1300 as disclosed herein.

[0153] For example, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to receive a polar codeword via a transmission channel. In certain embodiments, the transmission channel is between the UE 1300 and a TRP of a base station, e.g., gNB.

[0154] The processor 1302 coupled memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to determine a plurality of polar subcodes based on the polar codeword. In some embodiments, the length of a respective polar subcode of the plurality of polar subcodes is based on a length of the polar codeword or a number of the plurality of parallel polar code component decoders, or a combination thereof. For example, a codeword of length M may be divided into multiple subcodes of length (M / NPE), where NPEis the number of the plurality of parallel component decoders. In certain embodiments, NPEis based on a received code block length or a number of parallelizable processing elements at the base station, or a combination thereof.

[0155] The processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to identify, for each polar subcode of the plurality of polar subcodes, a set of special kernels corresponding to particular bit patterns (e.g., where each special kernel is associated with a specific pattern of information and / or frozen bits). In some embodiments, the set of special kernels corresponds to a set of special nodes associated with a decoding tree. In such embodiments, the particular bit patterns correspond to special or pre-defined bit patterns of information bits or frozen bits, or both.

[0156] In certain embodiments, the set of special nodes / kernels corresponding to the particular bit patterns comprises one or more of: 1) a Rate-0 node having only frozen bits (i.e., c = {0, 0, …, 0}); 2) a Rate-1 node having only information bits (i.e., c = {1, 1, …, 1}); 3) a REP node wherein a rightmost bit is an information bit and a remainder of the bits are frozen bits (i.e., c = {0, …, 0, 1}); 4) a SPC node wherein a leftmost bit is a frozen bit and the remainder of the bits are information bits (i.e., c = {0, 1, …, 1}); 5) a REP-2 node wherein the node includes only two information bits, and the information bits indices are the two largest bits (i.e., c = {0, …, 0, 1, 1}); 6) a RPC node wherein the node includes only three frozen bits, and the frozen bits indices are the three smallest bits (i.e., c = {0, 0, 0, 1, …, 1, }); 7) a PCR node wherein the node includes only three information bits, and the information bits indices are the three largest bits (i.e., c = {0, …, 0, 1, 1, 1}); 8) a SPC-2 node wherein the node includes only two frozen bits, and the frozen bits indices are the two smallest bits (i.e., c = {0, 0, 1, …, 1}); or 9) a combination thereof.

[0157] The processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to decode the plurality of polar subcodesusing a plurality of parallel polar code decoders. In such embodiments, each parallel polar code component decoder implements one or more fast decode modules to decode a corresponding special kernel of the set of special kernels. In some embodiments, the plurality of parallel polar code component decoders comprises one or more of: SC decoders, SCL decoders, list sphere decoders (List-SD), ML decoders, or a combination thereof.

[0158] In some embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to: A) determine a code tree based on the polar codeword; and B) partition the code tree into the plurality of polar subcodes, wherein each polar subcode of the plurality of polar subcodes corresponds to a subtree.

[0159] In certain embodiments, the polar codeword is encoded based on a polar base matrix. In such embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to partition the code tree based on a structure of the polar base matrix. In certain embodiments, the plurality of component decoders implement the one or more fast decode modules at intermediate levels of the subtrees to fast decode the special nodes / kernels.

[0160] In certain embodiments, to decode the plurality of polar subcodes, the at least one processor is configured to cause a respective component decoder to: A) perform a subtree traversal technique on a corresponding polar subcode; B) output a log-likelihood ratio associated with the corresponding polar subcode based on the subtree traversal; and C) decode a set of correlated received code bits based on the combined log-likelihood ratios.

[0161] In certain embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to: A) prune a respective subtree based on a sphere decoding procedure, a code tree based on the polar codeword; and B) perform a simplified subtree traversal of the pruned subtree based on a successive cancellation decoder or a successive cancellation list decoder.

[0162] In such embodiments, to prune the respective subtree based on a sphere decoding procedure, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to: 1) define a squared radiusbased at least in part on channel statistics; 2) discard a respective node outside the squared radius. In further embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to define the squared radius based at least in part on an artificial intelligence or machine-learning model.

[0163] In some embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to: A) determine a path metric based on a maximized likelihood probability between a received vector and a random vector; and B) partition the code tree based on the path metric and a MultiSphere subtree construction procedure.

[0164] In certain embodiments, the MultiSphere subtree construction procedure may be based on a minimum weight distributions of candidate codewords. In such embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to partition the code tree based at least in part on a candidate codewords associated with a lowest path metric.

[0165] In some embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to decode the polar codeword based on a combined output of the plurality of component decoders. In certain embodiments, the processor 1302 coupled with the memory 1304 may be configured to, capable of, or operable to cause the UE 1300 to decode the polar codeword based on a combined log-likelihood ratio associated with the plurality of polar subcodes.

[0166] The controller 1306 may manage input and output signals for the UE 1300. The controller 1306 may also manage peripherals not integrated into the UE 1300. In some implementations, the controller 1306 may utilize an operating system (OS) such as iOS®, ANDROID®, WINDOWS®, or other operating systems. In some implementations, the controller 1306 may be implemented as part of the processor 1302.

[0167] In some implementations, the UE 1300 may include at least one transceiver 1308. In some other implementations, the UE 1300 may have more than one transceiver 1308. The transceiver 1308 may represent a wireless transceiver. The transceiver 1308 may include one or more receiver chains 1310, one or more transmitter chains 1312, or a combination thereof.

[0168] A receiver chain 1310 may be to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receiver chain 1310 may include one or more antennas for receiving the signal over the air or wireless medium. The receiver chain 1310 may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain 1310 may include at least one demodulator configured to demodulate the received signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 1310 may include at least one decoder for decoding / processing the demodulated signal to receive the transmitted data.

[0169] A transmitter chain 1312 may be configured to generate and transmit signals (e.g., control information, data, packets). The transmitter chain 1312 may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmitter chain 1312 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 1312 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

[0170] Figure 14 illustrates an example of a processor 1400 in accordance with aspects of the present disclosure. The processor 1400 may be an example of a processor configured to perform various operations in accordance with examples as described herein. The processor 1400 may include a controller 1402 configured to perform various operations in accordance with examples as described herein. The processor 1400 may optionally include at least one memory 1404, which may be, for example, an L1 / L2 / L3 cache. Additionally, or alternatively, the processor 1400 may optionally include one or more arithmetic-logic units (ALUs) 1406. One or more of these components may be in electronic communication or otherwise coupled (e.g., operatively, communicatively, functionally, electronically, electrically) via one or more interfaces (e.g., buses).

[0171] The processor 1400 may be a processor chipset and include a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations(e.g., receiving, obtaining, retrieving, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) in accordance with examples as described herein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the processor chipset (e.g., the processor 1400) or other memory (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and others).

[0172] The controller 1402 may be configured to manage and coordinate various operations (e.g., signaling, receiving, obtaining, retrieving, transmitting, outputting, forwarding, storing, determining, identifying, accessing, writing, reading) of the processor 1400 to cause the processor 1400 to support various operations in accordance with examples as described herein. For example, the controller 1402 may operate as a control unit of the processor 1400, generating control signals that manage the operation of various components of the processor 1400. These control signals include enabling or disabling functional units, selecting data paths, initiating memory access, and coordinating timing of operations.

[0173] The controller 1402 may be configured to fetch (e.g., obtain, retrieve, receive) instructions from the memory 1404 and determine subsequent instruction(s) to be executed to cause the processor 1400 to support various operations in accordance with examples as described herein. The controller 1402 may be configured to track memory address of instructions associated with the memory 1404. The controller 1402 may be configured to decode instructions to determine the operation to be performed and the operands involved. For example, the controller 1402 may be configured to interpret the instruction and determine control signals to be output to other components of the processor 1400 to cause the processor 1400 to support various operations in accordance with examples as described herein. Additionally, or alternatively, the controller 1402 may be configured to manage flow of data within the processor 1400. The controller 1402 may be configured to control transfer of data between registers, arithmetic logic units (ALUs), and other functional units of the processor 1400.

[0174] The memory 1404 may include one or more caches (e.g., memory local to or included in the processor 1400 or other memory, such RAM, ROM, DRAM, SDRAM,SRAM, MRAM, flash memory, etc. In the memory 1404 may reside within or on a processor chipset (e.g., local to the processor 1400). In some other implementations, the memory 1404 may reside external to the processor chipset (e.g., remote to the processor 1400).

[0175] The memory 1404 may store computer-readable, computer-executable code including instructions that, when executed by the processor 1400, cause the processor 1400 to perform various functions described herein. The code may be stored in a non- transitory computer-readable medium such as system memory or another type of memory. The controller 1402 and / or the processor 1400 may be configured to execute computer- readable instructions stored in the memory 1404 to cause the processor 1400 to perform various functions. For example, the processor 1400 and / or the controller 1402 may be coupled with or to the memory 1404, the processor 1400, the controller 1402, and the memory 1404 may be configured to perform various functions described herein. In some examples, the processor 1400 may include multiple processors and the memory 1404 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may, individually or collectively, be configured to perform various functions herein.

[0176] The one or more ALUs 1406 may be configured to support various operations in accordance with examples as described herein. In some implementations, the one or more ALUs 1406 may reside within or on a processor chipset (e.g., the processor 1400). In some other implementations, the one or more ALUs 1406 may reside external to the processor chipset (e.g., the processor 1400). One or more ALUs 1406 may perform one or more computations such as addition, subtraction, multiplication, and division on data. For example, one or more ALUs 1406 may receive input operands and an operation code, which determines an operation to be executed. One or more ALUs 1406 be configured with a variety of logical and arithmetic circuits, including adders, subtractors, shifters, and logic gates, to process and manipulate the data according to the operation. Additionally, or alternatively, the one or more ALUs 1406 may support logical operations such as AND, OR, exclusive-OR (XOR), not-OR (NOR), and not-AND (NAND), enabling the one or more ALUs 1406 to handle conditional operations, comparisons, and bitwise operations.

[0177] In various implementations, the 1400 may support various functions (e.g., operations, signaling) of a UE, in accordance with examples as disclosed herein. For example, the controller 1402 coupled with the memory 1404 may be configured to, capable of, or operable to cause the processor 1400 to receive a polar codeword, e.g., via a transmission channel; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels. Additionally, the controller 1402 coupled with the memory 1404 may be configured to, capable of, or operable to cause the processor 1400 to perform one or more functions (e.g., operations, signaling) of the UE as described herein.

[0178] In various implementations, the processor 1400 may support various functions (e.g., operations, signaling) of a base station (e.g., gNB), in accordance with examples as disclosed herein. For example, the controller 1402 coupled with the memory 1404 may be configured to, capable of, or operable to cause the processor 1400 to receive a polar codeword, e.g., via a transmission channel; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels. Additionally, the controller 1402 coupled with the memory 1404 may be configured to, capable of, or operable to cause the processor 1400 to perform one or more functions (e.g., operations, signaling) of the base station as described herein.

[0179] Figure 15 illustrates an example of a NE 1500 in accordance with aspects of the present disclosure. The NE 1500 may include a processor 1502, a memory 1504, a controller 1506, and a transceiver 1508. The processor 1502, the memory 1504, the controller 1506, or the transceiver 1508, or various combinations thereof or various components thereof may be examples of means for performing various aspects of the present disclosure as described herein. These components may be coupled (e.g.,operatively, communicatively, electrically) via one or more interfaces.

[0180] The processor 1502, the memory 1504, the controller 1506, or the transceiver 1508, or various combinations or components thereof may be implemented in hardware (e.g., circuitry). The hardware may include a processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic device, or any combination thereof configured as or otherwise supporting a means for performing the functions described in the present disclosure.

[0181] The processor 1502 may include an intelligent hardware device (e.g., a general-purpose processor, a DSP, a CPU, an ASIC, an FPGA, or any combination thereof). In some implementations, the processor 1502 may be configured to operate the memory 1504. In some other implementations, the memory 1504 may be integrated into the processor 1502. The processor 1502 may be configured to execute computer-readable instructions stored in the memory 1504 to cause the NE 1500 to perform various functions of the present disclosure.

[0182] The memory 1504 may include volatile or non-volatile memory. The memory 1504 may store computer-readable, computer-executable code including instructions when executed by the processor 1502 cause the NE 1500 to perform various functions described herein. The code may be stored in a non-transitory computer-readable medium such the memory 1504 or another type of memory. Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non- transitory storage medium may be any available medium that may be accessed by a general-purpose or special-purpose computer.

[0183] In some implementations, the processor 1502 and the memory 1504 coupled with the processor 1502 may be configured to cause the NE 1500 to perform various functions (e.g., operations, signaling) described herein (e.g., executing, by the processor 1502, instructions stored in the memory 1504). In some implementations, the processor 1502 may include multiple processors and the memory 1504 may include multiple memories. One or more of the multiple processors may be coupled with one or more of the multiple memories, which may be individually or collectively, configured to perform various functions (e.g., operations, signaling) of the NE 1500 as disclosed herein.

[0184] For example, the processor with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to receive a polar codeword via a transmission channel. In certain embodiments, the transmission channel is between a UE and a TRP of the NE.

[0185] The processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to determine a plurality of polar subcodes based on the polar codeword. In some embodiments, the length of a respective polar subcode of the plurality of polar subcodes is based on a length of the polar codeword or a number of the plurality of parallel polar code component decoders, or a combination thereof. In certain embodiments, the number of the plurality of parallel polar code component decoders is based on a received code block length or a number of parallelizable processing elements at the base station, or a combination thereof.

[0186] The processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to identify, for each polar subcode of the plurality of polar subcodes, a set of special kernels corresponding to particular bit patterns (e.g., where each special kernel is associated with a specific pattern of information and / or frozen bits). In some embodiments, the set of special kernels corresponds to a set of special nodes associated with a decoding tree. In such embodiments, the particular bit patterns correspond to special or pre-defined bit patterns of information bits or frozen bits, or both.

[0187] In certain embodiments, the set of special nodes / kernels corresponding to the particular bit patterns comprises one or more of: 1) a Rate-0 node having only frozen bits; 2) a Rate-1 node having only information bits; 3) a REP node wherein a rightmost bit is an information bit and a remainder of the bits are frozen bits; 4) a SPC node wherein a leftmost bit is a frozen bit and the remainder of the bits are information bits; 5) a REP-2 node wherein the node includes only two information bits, and the information bits indices are the two largest; 6) a RPC node wherein the node includes only three frozen bits, and the frozen bits indices are the three smallest; 7) a PCR node wherein the node includes only three information bits, and the information bits indices are the three largest; 8) a SPC-2 node wherein the node includes only two frozen bits, and the frozen bits indices are the two smallest; or 9) a combination thereof.

[0188] The processor 1502 coupled memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to decode the plurality of polar subcodes using a plurality of parallel polar code component decoders. In such embodiments, each parallel polar code component decoder implements one or more fast decode modules to decode a corresponding special kernel of the set of special kernels. In some embodiments, the plurality of parallel polar code component decoders comprises one or more of: SC decoders, SCL decoders, list sphere decoders (List-SD), ML decoders, or a combination thereof.

[0189] In some embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to: A) determine a code tree based on the polar codeword; and B) partition the code tree into the plurality of polar subcodes, wherein each polar subcode of the plurality of polar subcodes corresponds to a subtree.

[0190] In certain embodiments, the polar codeword is encoded based on a polar base matrix. In such embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to partition the code tree based on a structure of the polar base matrix. In certain embodiments, the plurality of component decoders implement the one or more fast decode modules at intermediate levels of the subtrees to fast decode the special nodes / kernels.

[0191] In certain embodiments, to decode the plurality of polar subcodes, the at least one processor is configured to cause a respective component decoder to: A) perform a subtree traversal technique on a corresponding polar subcode; B) output a log-likelihood ratio associated with the corresponding polar subcode based on the subtree traversal; and C) decode a set of correlated received code bits based on the combined log-likelihood ratios.

[0192] In certain embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to: A) prune a respective subtree based on a sphere decoding procedure, a code tree based on the polar codeword; and B) perform a simplified subtree traversal of the pruned subtree based on a successive cancellation decoder or a successive cancellation list decoder.

[0193] In such embodiments, to prune respective subtree based on a sphere decoding procedure, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to: 1) define a squared radius based at least in part on channel statistics; and 2) discard a respective node outside the squared radius. In further embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to define the squared radius based at least in part on an artificial intelligence or machine-learning model.

[0194] In some embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to: A) determine a path metric based on a maximized likelihood probability between a received vector and a random vector; and B) partition the code tree based on the path metric and a MultiSphere subtree construction procedure.

[0195] In certain embodiments, the MultiSphere subtree construction procedure may be based on a minimum weight distributions of candidate codewords. In such embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to partition the code tree based at least in part on a candidate codewords associated with a lowest path metric.

[0196] In some embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to decode the polar codeword based on a combined output of the plurality of component decoders. In certain embodiments, the processor 1502 coupled with the memory 1504 may be configured to, capable of, or operable to cause the NE 1500 to decode the polar codeword based on a combined log-likelihood ratio associated with the plurality of polar subcodes.

[0197] The controller 1506 may manage input and output signals for the NE 1500. The controller 1506 may also manage peripherals not integrated into the NE 1500. In some implementations, the controller 1506 may utilize an operating system such as iOS®, ANDROID®, WINDOWS®, or other operating systems. In some implementations, the controller 1506 may be implemented as part of the processor 1502.

[0198] In some implementations, the NE 1500 may include at least one transceiver 1508. In some other implementations, the NE 1500 may have more than one transceiver1508. The transceiver 1508 may represent transceiver. The transceiver 1508 may include one or more receiver chains 1510, one or more transmitter chains 1512, or a combination thereof.

[0199] A receiver chain 1510 may be configured to receive signals (e.g., control information, data, packets) over a wireless medium. For example, the receiver chain 1510 may include one or more antennas for receiving the signal over the air or wireless medium. The receiver chain 1510 may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain 1510 may include at least one demodulator configured to demodulate the received signal and obtain the transmitted data by reversing the modulation technique applied during transmission of the signal. The receiver chain 1510 may include at least one decoder for decoding / processing the demodulated signal to receive the transmitted data.

[0200] A transmitter chain 1512 may be configured to generate and transmit signals (e.g., control information, data, packets). The transmitter chain 1512 may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes like phase-shift keying (PSK) or quadrature amplitude modulation (QAM). The transmitter chain 1512 may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over the wireless medium. The transmitter chain 1512 may also include one or more antennas for transmitting the amplified signal into the air or wireless medium.

[0201] Figure 16 depicts one embodiment of a method 1600 in accordance with aspects of the present disclosure. In various embodiments, the operations of the method 1600 may be implemented by a UE as described herein. In some implementations, the UE may execute a set of instructions to control the function elements of the UE to perform the described functions.

[0202] At step 1602, the method 1600 may include receiving a polar codeword. The operations of step 1602 may be performed in accordance with examples as described herein. In some implementations, aspects of the operation of step 1602 may be performed by a UE, as described with reference to Figure 13.

[0203] At step 1604, the method 1600 include determining a plurality of polar subcodes based on the polar codeword. The operations of step 1604 may be performed in accordance with examples as described herein. In some implementations, aspects of the operation of step 1604 may be performed by a UE, as described with reference to Figure 13.

[0204] At step 1606, the method 1600 may include identifying, for each polar subcode of the plurality of polar subcodes, a set of kernels, where each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns. The operations of step 1606 may be performed in accordance with examples as described herein. In some implementations, aspects of the operation of step 1606 may be performed by a UE, as described with reference to Figure 13.

[0205] At step 1608, the method 1600 may include decoding the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder implements one or more fast decode modules to decode a corresponding special kernel. The operations of step 1608 may be performed in accordance with examples as described herein. In some implementations, aspects of the operation of step 1608 may be performed by a UE, as described with reference to Figure 13.

[0206] It should be noted that the method 1600 described herein describes one possible implementation, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible.

[0207] Figure 17 depicts one embodiment of a method 1700 in accordance with aspects of the present disclosure. The operations of the method 1700 may be implemented by a NE, e.g., in a RAN, as described herein. In some implementations, the NE may execute a set of instructions to control the function elements of the NE to perform the described functions.

[0208] At step 1702, the method 1700 may include receiving a polar codeword. The operations of step 1702 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of step 1702 may be performed by a NE, as described with reference to Figure 15.

[0209] At step 1704, the method 1700 include determining a plurality of polar subcodes based on the polar codeword. The operations of step 1704 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of step 1704 may be performed by a NE, as described with reference to Figure 15.

[0210] At step 1706, the method 1700 may include identifying, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns. The operations of step 1706 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of step 1706 may be performed by a NE, as described with reference to Figure 15.

[0211] At step 1708, the method 1700 may include decoding the plurality of polar subcodes using a plurality of parallel polar code component decoders, where each parallel polar code component decoder implements one or more fast decode modules to decode a corresponding special kernel. The operations of step 1708 may be performed in accordance with examples as described herein. In some implementations, aspects of the operations of step 1708 may be performed by a NE, as described with reference to Figure 15.

[0212] It should be noted that the method 1700 described herein describes one possible implementation, and that the operations and the steps may be rearranged or otherwise modified and that other implementations are possible.

[0213] The description herein is provided to enable a person having ordinary skill in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to a person having ordinary skill in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

What is claimed is:

1. A user equipment (UE) for wireless communication, comprising: at least one memory; and at least one processor coupled with the at least one memory and configured to cause the UE to: receive a polar codeword; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders, wherein each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

2. The UE of claim 1, wherein a length of a respective polar subcode of the plurality of polar subcodes is based on a length of the polar codeword or a number of the plurality of parallel polar code component decoders, or a combination thereof.

3. The UE of claim 2, wherein the number of the plurality of parallel polar code component decoders is based on a received code block length or a number of parallelizable processing elements at the UE, or a combination thereof.

4. The UE of claim 1, wherein the set of kernels corresponds to a set of special nodes associated with a decoding tree, and wherein the set of one or more bit patterns corresponds to bit patterns of information bits or frozen information bits, or both.

5. The UE of claim 4, wherein the set of one or more bit patterns comprises one or more of: a Rate-0 node having only frozen bits, a Rate-1 node having only information bits, a repetition (REP) node wherein a rightmost bit is an information bit and a remainder of the bits are frozen bits,a single parity check (SPC) wherein a leftmost bit is a frozen bit and the remainder of the bits are information bits, a dual REP (REP-2) node wherein the node includes only two information bits, and bit indices of the two information bits correspond to two largest indices, a repeated parity check (RPC) node wherein the node includes only three frozen bits, and bit indices of the three frozen bits correspond to three smallest indices, a parity-checked repetition (PCR) node wherein the node includes only three information bits, and the bit indices of the information bits correspond to three largest indices, a dual SPC (SPC-2) node wherein the node includes only two frozen bits, and bit indices of the two frozen bits correspond to two smallest indices, or a combination thereof.

6. The UE of claim 1, wherein the at least one processor is configured to cause the UE to: determine a code tree based on the polar codeword; and partition the code tree into the plurality of polar subcodes, wherein each polar subcode of the plurality of polar subcodes corresponds to a subtree.

7. The UE of claim 6, wherein the polar codeword is encoded based on a polar base matrix, and wherein the at least one processor is configured to cause the UE to partition the code tree based on a structure of the polar base matrix.

8. The UE of claim 6, wherein the plurality of component decoders implement the one or more fast decode modules at intermediate levels of the subtrees to fast decode the set of kernels.

9. The UE of claim 6, wherein to decode the plurality of polar subcodes, the at least one processor is configured to cause a respective component decoder to: perform a subtree traversal technique on a corresponding polar subcode;output a log-likelihood ratio with the corresponding polar subcode based on the subtree traversal; and decode a set of correlated received code bits based on combined log- likelihood ratios.

10. The UE of claim 6, wherein the at least one processor is configured to cause the UE to: prune a respective subtree based on a sphere decoding procedure, a code tree based on the polar codeword; and perform a simplified subtree traversal of the pruned subtree based on a successive cancellation decoder or a successive cancellation list decoder.

11. The UE of claim 10, wherein to prune the respective subtree based on a sphere decoding procedure, the at least one processor is configured to cause the UE to: define a squared radius based at least in part on channel statistics; and discard a respective node outside the squared radius.

12. The UE of claim 11, wherein the at least one processor is configured to cause the UE to define the squared radius based at least in part on an artificial intelligence or machine-learning model.

13. The UE of claim 6, wherein the at least one processor is configured to cause the UE to: determine a path metric based on a maximized likelihood probability between a received vector and a random vector; and partition the code tree based on the path metric and a multisphere subtree construction procedure.

14. The UE of claim 13, wherein the multisphere subtree construction procedure is based on a minimum weight distributions of candidate codewords, wherein the at least one processor is configured to cause the UE to partition the code tree based at least in part on a candidate codewords associated with a lowest path metric.

15. The UE of claim 1, wherein the at one processor is configured to cause the UE to decode the polar codeword based on a combined output of the plurality of component decoders.

16. The UE of claim 15, wherein the at least one processor is configured to cause the UE to decode the polar codeword based on a combined log-likelihood ratio associated with the plurality of polar subcodes.

17. The UE of claim 1, wherein the plurality of parallel polar code component decoders comprises one or more of: successive cancellation decoders (SC), successive cancellation list decoders (SCL), list sphere decoders (List-SD), Maximum-likelihood (ML) decoders or a combination thereof.

18. A base station for wireless communication, comprising: at least one memory; and at least one processor coupled with the at least one memory and configured to cause the base station to: receive a polar codeword; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decode the plurality of polar subcodes using a plurality of parallel polar code component decoders, wherein each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

19. A processor for wireless communication, comprising: at least one controller coupled with at least one memory and configured to cause the processor to: receive a polar codeword; determine a plurality of polar subcodes based on the polar codeword; identify, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; anddecode the plurality of polar using a plurality of parallel polar code component decoders, wherein each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

20. A method performed by a decoder, the method comprising: receiving a polar codeword; determining a plurality of polar subcodes based on the polar codeword; identifying, for each polar subcode of the plurality of polar subcodes, a set of kernels, wherein each kernel of the set of kernels is associated with a bit pattern of a set of one or more bit patterns; and decoding the plurality of polar subcodes using a plurality of parallel polar code component decoders, wherein each parallel polar code component decoder comprises one or more fast decode modules to decode a corresponding kernel of the set of kernels.

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