Thin-film capacitor

Abstract

[Problem] To suppress the occurrence of warpage in a thin film capacitor having a structure in which a plurality of capacitor layers are laminated with an insulating layer therebetween. [Solution] This thin film capacitor 10 comprises: a laminate comprising capacitor layers L2-L4 and a dummy capacitor layer L5, which are layered with prepregs PP1-PP3 disposed therebetween; and via conductors V1, V2 that penetrate the laminate. Upper electrodes 22A, 32A, 42A, which are included in the capacitor layers L2-L4, are connected to an upper external electrode 12 through the via conductor V1. Lower electrodes 21A, 31A, 41A, which are included in the capacitor layers L2-L4, are connected to a lower external electrode 11 through the via conductor V2. A dummy upper electrode 52D3 and a dummy lower electrode 51D3, which are included in the dummy capacitor layer L5, are not connected to either the via conductor V1 or the via conductor V2.

Description

thin film capacitor

[0001] The present disclosure relates to a thin film capacitor, and more particularly to a thin film capacitor having a structure in which a plurality of capacitor layers are stacked with an insulating layer interposed therebetween.

[0002] Patent Document 1 discloses a stacked thin film capacitor formed by stacking a plurality of thin film capacitors.

[0003] Japanese Patent Application Laid-Open No. 2019-140312

[0004] In this type of thin film capacitor, warping of the thin film capacitor can be suppressed by matching the number of capacitor layers on the front and back sides with respect to the insulating film located at the center in the thickness direction.

[0005] This disclosure describes a technique for suppressing the occurrence of warpage in a thin film capacitor having a structure in which a plurality of capacitor layers are stacked with an insulating layer interposed therebetween.

[0006] A thin film capacitor according to one aspect of the present disclosure includes a first insulating layer having first and second surfaces located opposite to each other, a first capacitor layer disposed on the first surface of the first insulating layer, a dummy capacitor layer disposed on the second surface of the first insulating layer, first and second via conductors provided to penetrate the first insulating layer, the first capacitor layer, and the dummy capacitor layer, a first external electrode connected to the first via conductor, and a second external electrode connected to the second via conductor, wherein the first capacitor layer includes an upper electrode layer including an upper electrode and a dummy upper electrode separated from each other by a slit, a lower electrode layer including a lower electrode and a dummy lower electrode separated from each other by a slit, and a capacitive insulating film located between the upper electrode layer and the lower electrode layer, and the dummy capacitor layer includes the first and a second dummy upper electrode layer, a dummy lower electrode layer including first and second dummy lower electrodes, and a capacitive insulating film located between the dummy upper electrode layer and the dummy lower electrode layer, wherein the first via conductor is provided without contacting the lower electrode included in the first capacitor layer, penetrating the upper electrode, dummy lower electrode, and capacitive insulating film included in the first capacitor layer, and the first dummy upper electrode, first dummy lower electrode, and capacitive insulating film included in the dummy capacitor layer, and the second via conductor is provided without contacting the upper electrode included in the first capacitor layer, penetrating the dummy upper electrode, lower electrode, and capacitive insulating film included in the first capacitor layer, and the second dummy upper electrode, second dummy lower electrode, and capacitive insulating film included in the dummy capacitor layer.

[0007] A thin film capacitor according to another aspect of the present disclosure comprises a laminate consisting of a plurality of alternatingly stacked capacitor layers and a plurality of insulating layers, and first and second via conductors provided through the laminate, each of the plurality of capacitor layers including an upper electrode, a lower electrode, and a capacitive insulating film located between the upper electrode and the lower electrode, the plurality of capacitor layers including a first capacitor layer and a plurality of second capacitor layers, each of the plurality of second capacitor layers having one of the upper electrode and the lower electrode connected to the first via conductor and the other of the upper electrode and the lower electrode connected to the second via conductor, at least a portion of the upper electrode included in the first capacitor layer being electrically isolated from the first and second via conductors, and at least a portion of the lower electrode included in the first capacitor layer being electrically isolated from the first and second via conductors.

[0008] According to the present disclosure, a technique is provided for suppressing the occurrence of warpage in a thin film capacitor having a structure in which a plurality of capacitor layers are stacked with an insulating layer interposed therebetween.

[0009] Fig. 1 is a schematic cross-sectional view of a thin film capacitor 10 according to an embodiment of the present disclosure. Fig. 2A is a schematic plan view showing the shapes of a lower electrode layer 21 located on capacitor layer L2, an upper electrode layer 32 located on capacitor layer L3, and a lower electrode layer 41 located on capacitor layer L4. Fig. 2B is a schematic plan view showing the shapes of an upper electrode layer 22 located on capacitor layer L2, a lower electrode layer 31 located on capacitor layer L3, and an upper electrode layer 42 located on capacitor layer L4. Fig. 2C is a schematic plan view showing the shape of a dummy upper electrode layer 52 located on dummy capacitor layer L5. Fig. 2D is a schematic plan view showing the shape of a dummy lower electrode layer 51 located on dummy capacitor layer L5.

[0010] Hereinafter, embodiments of the technology according to the present disclosure will be described in detail with reference to the accompanying drawings.

[0011] FIG. 1 is a simplified cross-sectional view of a thin film capacitor 10 according to one embodiment of the present disclosure.

[0012] The thin film capacitor 10 shown in Figure 1 has a conductor layer L1 on which an upper external electrode 12 is formed, a conductor layer L6 on which a lower external electrode 11 is formed, capacitor layers L2 to L4 on which capacitors are formed, and a dummy capacitor layer L5 on which a dummy capacitor is formed. Layers L1 and L2 are separated by a prepreg PP4. Layers L2 and L3 are separated by a prepreg PP2. Layers L3 and L4 are separated by a prepreg PP1. Layers L4 and L5 are separated by a prepreg PP3. Layers L5 and L6 are separated by a prepreg PP5. All of the prepregs PP1 to PP5 constitute insulating layers.

[0013] Prepreg PP1 is located at the center in the thickness direction of the thin film capacitor 10. Prepreg PP2 covers one surface of prepreg PP1 via a capacitor layer L3. Prepreg PP3 covers the other surface of prepreg PP1 via a capacitor layer L4. Prepreg PP2 and prepreg PP3 may have the same thickness. Prepreg PP4 covers the surface of prepreg PP2 opposite the surface facing prepreg PP1 via a capacitor layer L2. Prepreg PP5 covers the surface of prepreg PP3 opposite the surface facing prepreg PP1 via a dummy capacitor layer L5. Prepreg PP4 and prepreg PP5 may have the same thickness.

[0014] The capacitor layer L2 includes an upper electrode layer 22 including an upper electrode 22A and a dummy upper electrode 22D separated from each other by a slit S1, a lower electrode layer 21 including a lower electrode 21A and a dummy lower electrode 21D separated from each other by a slit S2, and a capacitive insulating film 23 located between the upper electrode layer 22 and the lower electrode layer 21. The region where the upper electrode 22A and the lower electrode 21A overlap with each other via the capacitive insulating film 23 constitutes a capacitor C2. Although the dummy upper electrode 22D overlaps with the lower electrode 21A with the capacitive insulating film 23 interposed therebetween, the two are short-circuited and therefore do not function as a capacitor. Similarly, although the dummy lower electrode 21D overlaps with the upper electrode 22A with the capacitive insulating film 23 interposed therebetween, the two are short-circuited and therefore do not function as a capacitor.

[0015] The capacitor layer L3 includes an upper electrode layer 32 including an upper electrode 32A and a dummy upper electrode 32D separated from each other by a slit S4, a lower electrode layer 31 including a lower electrode 31A and a dummy lower electrode 31D separated from each other by a slit S3, and a capacitive insulating film 33 located between the upper electrode layer 32 and the lower electrode layer 31. The region where the upper electrode 32A and the lower electrode 31A overlap with each other via the capacitive insulating film 33 constitutes a capacitor C3. Although the dummy upper electrode 32D overlaps with the lower electrode 31A via the capacitive insulating film 33, they are short-circuited and therefore do not function as a capacitor. Similarly, although the dummy lower electrode 31D overlaps with the upper electrode 32A via the capacitive insulating film 33, they are short-circuited and therefore do not function as a capacitor.

[0016] The capacitor layer L4 includes an upper electrode layer 42 including an upper electrode 42A and a dummy upper electrode 42D separated from each other by a slit S5, a lower electrode layer 41 including a lower electrode 41A and a dummy lower electrode 41D separated from each other by a slit S6, and a capacitance insulating film 43 located between the upper electrode layer 42 and the lower electrode layer 41. The region where the upper electrode 42A and the lower electrode 41A overlap with each other via the capacitance insulating film 43 constitutes a capacitor C4. Although the dummy upper electrode 42D overlaps with the lower electrode 41A via the capacitance insulating film 43, they are short-circuited and therefore do not function as a capacitor. Similarly, although the dummy lower electrode 41D overlaps with the upper electrode 42A via the capacitance insulating film 43, they are short-circuited and therefore do not function as a capacitor.

[0017] The dummy capacitor layer L5 includes a dummy upper electrode layer 52 including dummy upper electrodes 52D1, 52D2, and 52D3 separated from one another by slits S7 and S8, a dummy lower electrode layer 51 including dummy lower electrodes 51D1, 51D2, and 51D3 separated from one another by slits S9 and S10, and a capacitive insulating film 53 located between the dummy upper electrode layer 52 and the dummy lower electrode layer 51. Although the dummy upper electrode 52D1 and the dummy lower electrode 51D1 overlap each other via the capacitive insulating film 53, they are short-circuited and therefore do not function as a capacitor. Similarly, although the dummy upper electrode 52D2 and the dummy lower electrode 51D2 overlap each other via the capacitive insulating film 53, they are short-circuited and therefore do not function as a capacitor. The dummy upper electrode 52D3 and the dummy lower electrode 51D3 are electrically isolated from the via conductors V1 and V2 and may be in an electrically floating state. The dummy upper electrode 52D3 may have an area larger than each of the dummy upper electrodes 52D1 and 52D2. The dummy lower electrode 51D3 may have an area larger than each of the dummy lower electrodes 51D1 and 51D2.

[0018] The upper electrode layer 22, the lower electrode layer 31, the upper electrode layer 42, and the dummy lower electrode layer 51 may be made of the same metal material, such as Cu, and have the same thickness. The lower electrode layer 21, the upper electrode layer 32, the lower electrode layer 41, and the dummy upper electrode layer 52 may be made of the same metal material, such as Ni, and have the same thickness.

[0019] 1, capacitor layers L3 and L4 are first formed on both sides of prepreg PP1. In this case, if the same metal material having the same thickness, such as Cu, is selected as the conductive material constituting lower electrode layer 31 of capacitor layer L3 and upper electrode layer 42 of capacitor layer L4, and the same metal material having the same thickness, such as Ni, is selected as the conductive material constituting upper electrode layer 32 of capacitor layer L3 and lower electrode layer 41 of capacitor layer L4, symmetry between the front and back of prepreg PP1 is ensured, making warping unlikely to occur at this stage.

[0020] Next, the capacitor layers L3 and L4 are covered with prepregs PP2 and PP3, respectively, and then the capacitor layer L2 and the dummy capacitor layer L5 are formed on the surfaces of the prepregs PP2 and PP3. In this case, by using prepregs PP2 and PP3 that are the same thickness and made of the same material, symmetry between the front and back of the prepreg PP1 is ensured. Furthermore, by selecting the same metal material with the same thickness, such as Ni, for the conductive material constituting the lower electrode layer 21 of the capacitor layer L2 and the dummy upper electrode layer 52 of the dummy capacitor layer L5, and selecting the same metal material with the same thickness, such as Cu, for the conductive material constituting the upper electrode layer 22 of the capacitor layer L2 and the dummy lower electrode layer 51 of the dummy capacitor layer L5, symmetry between the front and back of the prepreg PP1 is ensured, making warping unlikely to occur at this stage.

[0021] Next, the capacitor layer L2 and the dummy capacitor layer L5 are covered with prepregs PP4 and PP5, respectively, and then the upper external electrode 12 and the lower external electrode 11 are formed on the surfaces of the prepregs PP4 and PP5, respectively. In this case, by using prepregs PP4 and PP5 that have the same thickness and are made of the same material, symmetry between the front and back of the prepreg PP1 is ensured.

[0022] In this way, by matching the number of capacitor layers or dummy capacitor layers laminated on the front and back of the prepreg PP1, symmetry of the structure in the thickness direction around the prepreg PP1 is ensured, making it less likely for warping to occur in the thin-film capacitor 10. Moreover, by starting from the prepreg PP1 and sequentially laminating capacitor layers or dummy capacitor layers on the front and back of the prepreg PP1 with prepregs interposed therebetween, warping is less likely to occur during fabrication.

[0023] Fig. 2A is a schematic plan view showing the shapes of the lower electrode layer 21 located in the capacitor layer L2, the upper electrode layer 32 located in the capacitor layer L3, and the lower electrode layer 41 located in the capacitor layer L4. Fig. 2B is a schematic plan view showing the shapes of the upper electrode layer 22 located in the capacitor layer L2, the lower electrode layer 31 located in the capacitor layer L3, and the upper electrode layer 42 located in the capacitor layer L4. Fig. 2C is a schematic plan view showing the shape of the dummy upper electrode layer 52 located in the dummy capacitor layer L5. Fig. 2D is a schematic plan view showing the shape of the dummy lower electrode layer 51 located in the dummy capacitor layer L5.

[0024] As shown in FIG. 2A , a slit S2 is provided in the lower electrode layer 21 located in the capacitor layer L2, a slit S2 is provided in the upper electrode layer 32 located in the capacitor layer L3, and a slit S6 is provided in the lower electrode layer 41 located in the capacitor layer L4. The lower electrode layer 21 located in the capacitor layer L2 is separated by the slit S2 into a lower electrode 21A and a dummy lower electrode 21D. The upper electrode layer 32 located in the capacitor layer L3 is separated by the slit S4 into an upper electrode 32A and a dummy upper electrode 32D. The lower electrode layer 41 located in the capacitor layer L4 is separated by the slit S6 into a lower electrode 41A and a dummy lower electrode 41D. A plurality of slits S2, S4, and S6 may be provided. The planar positions of the slits S2, S4, and S6 may coincide with each other.

[0025] As shown in FIG. 2B , a slit S1 is provided in the upper electrode layer 22 located on the capacitor layer L2, a slit S3 is provided in the lower electrode layer 31 located on the capacitor layer L3, and a slit S5 is provided in the upper electrode layer 42 located on the capacitor layer L4. The upper electrode layer 22 located on the capacitor layer L2 is separated by the slit S1 into an upper electrode 22A and a dummy upper electrode 22D. The lower electrode layer 31 located on the capacitor layer L3 is separated by the slit S3 into a lower electrode 31A and a dummy lower electrode 31D. The upper electrode layer 42 located on the capacitor layer L4 is separated by the slit S5 into an upper electrode 42A and a dummy upper electrode 42D. A plurality of slits S1, S3, and S5 may be provided. The planar positions of the slits S1, S3, and S5 may coincide with each other.

[0026] 2C, slits S7 and S8 are provided in the dummy upper electrode layer 52 located on the dummy capacitor layer L5. The dummy upper electrode layer 52 located on the dummy capacitor layer L5 is separated by the slit S7 into a dummy upper electrode 52D2 and a dummy upper electrode 52D3, and is also separated by the slit S8 into a dummy upper electrode 52D1 and a dummy upper electrode 52D3.

[0027] 2D, slits S9 and S10 are provided in the dummy lower electrode layer 51 located in the dummy capacitor layer L5. The dummy lower electrode layer 51 located in the dummy capacitor layer L5 is separated into a dummy lower electrode 51D2 and a dummy lower electrode 51D3 by the slit S9, and is also separated into a dummy lower electrode 51D1 and a dummy lower electrode 51D3 by the slit S10.

[0028] The laminate made up of the prepregs PP1 to PP3, the capacitor layers L2 to L4, and the dummy capacitor layer L5 is provided with via conductors V1 and V2 that pass through them.

[0029] The via conductor V1 is provided penetrating the upper electrode 22A and dummy lower electrode 21D located on the capacitor layer L2, the dummy upper electrode 32D and lower electrode 31A located on the capacitor layer L3, the upper electrode 42A and dummy lower electrode 41D located on the capacitor layer L4, and the dummy upper electrode 52D1 and dummy lower electrode 51D1 located on the dummy capacitor layer L5 so as to be in contact with them. The via conductor V1 is not in contact with the dummy upper electrode 22D and lower electrode 21A located on the capacitor layer L2, the upper electrode 32A and dummy lower electrode 31D located on the capacitor layer L3, the dummy upper electrode 42D and lower electrode 41A located on the capacitor layer L4, or the dummy upper electrodes 52D2, 52D3 and dummy lower electrodes 51D2, 51D3 located on the dummy capacitor layer L5. The via conductor V1 is connected to the upper external electrode 12 located on the surface of the prepreg PP4 through a wiring pattern and via conductors provided inside the prepreg PP4.

[0030] The via conductor V2 penetrates the dummy upper electrode 22D and lower electrode 21A located on the capacitor layer L2, the upper electrode 32A and dummy lower electrode 31D located on the capacitor layer L3, the dummy upper electrode 42D and lower electrode 41A located on the capacitor layer L4, and the dummy upper electrode 52D2 and dummy lower electrode 51D2 located on the dummy capacitor layer L5 so as to be in contact with them. The via conductor V2 does not contact the upper electrode 22A and dummy lower electrode 21D located on the capacitor layer L2, the dummy upper electrode 32D and lower electrode 31A located on the capacitor layer L3, the upper electrode 42A and dummy lower electrode 41D located on the capacitor layer L4, or the dummy upper electrodes 52D1, 52D3 and dummy lower electrodes 51D1, 51D3 located on the dummy capacitor layer L5. The via conductor V2 is connected to the lower external electrode 11 located on the surface of the prepreg PP5 through a wiring pattern and via conductors provided inside the prepreg PP5.

[0031] With this configuration, the three capacitors C2 to C4 located on the capacitor layers L2 to L4 are connected in parallel between the upper external electrode 12 and the lower external electrode 11. The capacitors C2 to C4 form a capacitor region CR. In contrast, the dummy upper electrode 52D3 and dummy lower electrode 51D3 located on the dummy capacitor layer L5 are not connected to either the upper external electrode 12 or the lower external electrode 11, and therefore do not contribute to the capacitance. This makes it possible to adjust the capacitance while ensuring symmetry of the structure in the thickness direction around the prepreg PP1. The dummy upper electrode 52D3 and dummy lower electrode 51D3 located on the dummy capacitor layer L5 may overlap the capacitor region CR in a plan view.

[0032] The dummy upper electrode 52D3 and the dummy lower electrode 51D3 located in the dummy capacitor layer L5 also contribute to improving heat dissipation. In particular, when the dummy upper electrode 52D3 has an area larger than each of the dummy upper electrodes 52D1 and 52D2 and the dummy lower electrode 51D3 has an area larger than each of the dummy lower electrodes 51D1 and 51D2, the heat dissipation of the dummy upper electrode 52D3 and the dummy lower electrode 51D3 is further improved.

[0033] In the dummy capacitor layer L5, the slit S7 may be omitted. In this case, the dummy upper electrode 52D2 and the dummy upper electrode 52D3 are short-circuited. In the dummy capacitor layer L5, the slit S8 may be omitted. In this case, the dummy upper electrode 52D1 and the dummy upper electrode 52D3 are short-circuited. However, if both the slit S7 and the slit S8 are omitted, the upper external electrode 12 and the lower external electrode 11 are short-circuited, and therefore, it is inappropriate to omit both the slit S7 and the slit S8.

[0034] In the dummy capacitor layer L5, the slit S9 may be omitted. In this case, the dummy lower electrode 51D2 and the dummy lower electrode 51D3 are short-circuited. In the dummy capacitor layer L5, the slit S10 may be omitted. In this case, the dummy lower electrode 51D1 and the dummy lower electrode 51D3 are short-circuited. However, if both the slit S9 and the slit S10 are omitted, the upper external electrode 12 and the lower external electrode 11 are short-circuited, and therefore, it is inappropriate to omit both the slit S9 and the slit S10.

[0035] Furthermore, if both slits S7 and S10 are omitted, the overlapping portion of the dummy upper electrode 52D3 and the dummy lower electrode 51D3 functions as a capacitor, causing the overall capacitance to deviate from the design value, and therefore it is inappropriate to omit both slits S7 and S10. Similarly, if both slits S8 and S9 are omitted, the overlapping portion of the dummy upper electrode 52D3 and the dummy lower electrode 51D3 functions as a capacitor, causing the overall capacitance to deviate from the design value, and therefore it is inappropriate to omit both slits S8 and S9.

[0036] 1 is used as a decoupling capacitor, the upper external electrode 12 may be connected to a power supply wiring and the lower external electrode 11 may be connected to a ground wiring. Because the ground wiring serves as the main heat dissipation route, this allows the dummy capacitor consisting of the dummy upper electrode 52D3 and the dummy lower electrode 51D3 to be located closer to the heat dissipation route, thereby improving heat dissipation. For example, if a large-area ground pattern is provided on the mounting surface of the mounting board, mounting the thin film capacitor 10 shown in FIG. 1 on the mounting surface of the mounting board so that the ground pattern and the lower external electrode 11 are in contact will allow efficient heat dissipation to the ground pattern of the mounting board via the dummy capacitor.

[0037] 1, a dummy capacitor consisting of a dummy upper electrode 52D3 and a dummy lower electrode 51D3 is disposed on layer L5, but it may be disposed on any of layers L2 to L4. Also, in the example shown in Fig. 1, there are four layers L2 to L5 on which the capacitors are disposed, but the number of layers on which the capacitors are disposed may be six or eight.

[0038] The above describes embodiments of the technology according to the present disclosure, but the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible within the scope of the gist of the technology, and it goes without saying that these modifications are also included within the scope of the technology according to the present disclosure.

[0039] The technology according to the present disclosure includes, but is not limited to, the following configuration examples.

[0040] A thin film capacitor according to one aspect of the present disclosure includes a first insulating layer having first and second surfaces located opposite to each other, a first capacitor layer disposed on the first surface of the first insulating layer, a dummy capacitor layer disposed on the second surface of the first insulating layer, first and second via conductors provided to penetrate the first insulating layer, the first capacitor layer, and the dummy capacitor layer, a first external electrode connected to the first via conductor, and a second external electrode connected to the second via conductor, wherein the first capacitor layer includes an upper electrode layer including an upper electrode and a dummy upper electrode separated from each other by a slit, a lower electrode layer including a lower electrode and a dummy lower electrode separated from each other by a slit, and a capacitive insulating film located between the upper electrode layer and the lower electrode layer, and the dummy capacitor layer includes the first and a second dummy upper electrode layer, a dummy lower electrode layer including first and second dummy lower electrodes, and a capacitive insulating film located between the dummy upper electrode layer and the dummy lower electrode layer, wherein the first via conductor is provided without contacting the lower electrode included in the first capacitor layer, penetrating the upper electrode, dummy lower electrode, and capacitive insulating film included in the first capacitor layer, and the first dummy upper electrode, first dummy lower electrode, and capacitive insulating film included in the dummy capacitor layer, and the second via conductor is provided without contacting the upper electrode included in the first capacitor layer, penetrating the dummy upper electrode, lower electrode, and capacitive insulating film included in the first capacitor layer, and the second dummy upper electrode, second dummy lower electrode, and capacitive insulating film included in the dummy capacitor layer. Since the dummy capacitor layer does not contribute to capacitance, it is possible to adjust the capacitance while maintaining the number of layers.

[0041] In the above-described thin film capacitor, the lower electrode layer of the first capacitor layer and the dummy upper electrode layer of the dummy capacitor layer face each other via a first insulating layer, and the upper electrode layer of the first capacitor layer and the dummy lower electrode layer of the dummy capacitor layer may both be made of a first metal material, and the lower electrode layer of the first capacitor layer and the dummy upper electrode layer of the dummy capacitor layer may both be made of a second metal material different from the first metal material, thereby improving the vertical symmetry with respect to the first insulating layer.

[0042] In the above-described thin film capacitor, the dummy upper electrode layer further includes a third dummy upper electrode separated from the first and second dummy upper electrodes, and the dummy lower electrode layer further includes a third dummy lower electrode separated from the first and second dummy lower electrodes, and the first and second via conductors do not have to be connected to either the third dummy upper electrode or the third dummy lower electrode. This improves heat dissipation by the third dummy upper electrode and the third dummy lower electrode. In this case, the third dummy upper electrode may have a larger area than the first and second dummy upper electrodes, and the third dummy lower electrode may have a larger area than the first and second dummy lower electrodes. This further improves heat dissipation.

[0043] The thin film capacitor further includes a second insulating layer having third and fourth surfaces opposite to each other, a third insulating layer having fifth and sixth surfaces opposite to each other, a second capacitor layer disposed on the third surface of the second insulating layer, and a third capacitor layer disposed on the fourth surface of the second insulating layer, wherein the third insulating layer is located between the first capacitor layer and the second capacitor layer such that the fifth surface covers the first capacitor layer and the sixth surface covers the second capacitor layer, and the first and second via conductors further penetrate the second insulating layer, the third insulating layer, the second capacitor layer, and the third capacitor layer, and each of the second and third capacitor layers includes an upper electrode layer including an upper electrode and a dummy upper electrode separated from each other by a slit, and a dummy upper electrode layer separated from each other by the slit. and a capacitance insulating film located between the upper electrode layer and the lower electrode layer, wherein the first via conductor is provided without contacting the upper electrode included in the second capacitor layer and the lower electrode included in the third capacitor layer, penetrating the lower electrode, dummy upper electrode, and capacitance insulating film included in the second capacitor layer and the dummy lower electrode, upper electrode, and capacitance insulating film included in the third capacitor layer, and the second via conductor is provided without contacting the lower electrode included in the second capacitor layer and the upper electrode included in the third capacitor layer, penetrating the dummy lower electrode, upper electrode, and capacitance insulating film included in the second capacitor layer, and the lower electrode, dummy upper electrode, and capacitance insulating film included in the third capacitor layer, and the first to third capacitor layers are connected in parallel between the first and second external electrodes.

[0044] According to another aspect of the present disclosure, there is provided a thin film capacitor comprising: a laminate including a plurality of alternating capacitor layers and a plurality of insulating layers; and first and second via conductors extending through the laminate, wherein each of the plurality of capacitor layers includes an upper electrode, a lower electrode, and a capacitive insulating film located between the upper electrode and the lower electrode, the plurality of capacitor layers including a first capacitor layer and a plurality of second capacitor layers, wherein each of the plurality of second capacitor layers has one of the upper electrode and the lower electrode connected to the first via conductor and the other of the upper electrode and the lower electrode connected to the second via conductor, wherein at least a portion of the upper electrode included in the first capacitor layer is electrically isolated from the first and second via conductors, and at least a portion of the lower electrode included in the first capacitor layer is electrically isolated from the first and second via conductors. This configuration improves heat dissipation by the first capacitor layer.

[0045] REFERENCE SIGNS LIST 10 thin film capacitor 11 lower external electrode 12 upper external electrode 21, 31, 41 lower electrode layer 21A, 31A, 41A lower electrode 21D, 31D, 41D, 51D1 to 51D3 dummy lower electrode 22, 32, 42 upper electrode layer 22A, 32A, 42A upper electrode 22D, 32D, 42D, 52D1 to 52D3 dummy upper electrode 23, 33, 43, 53 capacitance insulating film 51 dummy lower electrode layer 52 dummy upper electrode layer C2 to C4 capacitor CR capacitor region L1, L6 conductor layer L2 to L4 capacitor layer L5 dummy capacitor layer PP1 to PP5 prepreg S1 to S10 slit V1, V2 via conductor

Claims

1. A semiconductor device comprising: a first insulating layer having first and second surfaces located opposite to each other; a first capacitor layer disposed on the first surface of the first insulating layer; a dummy capacitor layer disposed on the second surface of the first insulating layer; first and second via conductors provided to penetrate the first insulating layer, the first capacitor layer, and the dummy capacitor layer; a first external electrode connected to the first via conductor; and a second external electrode connected to the second via conductor; wherein the first capacitor layer comprises an upper electrode layer including an upper electrode and a dummy upper electrode separated from each other by a slit, a lower electrode layer including a lower electrode and a dummy lower electrode separated from each other by a slit, and a capacitive insulating film located between the upper electrode layer and the lower electrode layer; and the dummy capacitor layer comprises a dummy upper electrode layer including first and second dummy upper electrodes, a dummy lower electrode layer including first and second dummy lower electrodes, and a capacitive insulating film located between the dummy upper electrode layer and the dummy lower electrode layer; a first via conductor provided without contacting the lower electrode included in the first capacitor layer, penetrating the upper electrode, the dummy lower electrode, and the capacitance insulating film included in the first capacitor layer, and the first dummy upper electrode, the first dummy lower electrode, and the capacitance insulating film included in the dummy capacitor layer; and a second via conductor provided without contacting the upper electrode included in the first capacitor layer, penetrating the dummy upper electrode, the lower electrode, and the capacitance insulating film included in the first capacitor layer, and the second dummy upper electrode, the second dummy lower electrode, and the capacitance insulating film included in the dummy capacitor layer.

2. The thin film capacitor according to claim 1, wherein the lower electrode layer of the first capacitor layer and the dummy upper electrode layer of the dummy capacitor layer face each other via the first insulating layer, the upper electrode layer of the first capacitor layer and the dummy lower electrode layer of the dummy capacitor layer are both made of a first metal material, and the lower electrode layer of the first capacitor layer and the dummy upper electrode layer of the dummy capacitor layer are both made of a second metal material different from the first metal material.

3. The thin film capacitor of claim 1, wherein the dummy upper electrode layer further includes a third dummy upper electrode separated from the first and second dummy upper electrodes, the dummy lower electrode layer further includes a third dummy lower electrode separated from the first and second dummy lower electrodes, and the first and second via conductors are not connected to either the third dummy upper electrode or the third dummy lower electrode.

4. The thin film capacitor according to claim 3, wherein the third dummy upper electrode has an area larger than those of the first and second dummy upper electrodes, and the third dummy lower electrode has an area larger than those of the first and second dummy lower electrodes.

5. A semiconductor device further comprising: a second insulating layer having third and fourth surfaces opposite to each other; a third insulating layer having fifth and sixth surfaces opposite to each other; a second capacitor layer disposed on the third surface of the second insulating layer; and a third capacitor layer disposed on the fourth surface of the second insulating layer, wherein the third insulating layer is disposed between the first capacitor layer and the second capacitor layer such that the fifth surface covers the first capacitor layer and the sixth surface covers the second capacitor layer; the first and second via conductors further penetrate the second insulating layer, the third insulating layer, the second capacitor layer, and the third capacitor layer; and each of the second and third capacitor layers includes an upper electrode layer including an upper electrode and a dummy upper electrode separated from each other by a slit, a lower electrode layer including a lower electrode and a dummy lower electrode separated from each other by a slit, and a capacitive insulating film disposed between the upper electrode layer and the lower electrode layer, 2. The thin film capacitor according to claim 1, wherein the first via conductor is provided so as to penetrate the lower electrode, the dummy upper electrode, and the capacitance insulating film included in the second capacitor layer, and the dummy lower electrode, the upper electrode, and the capacitance insulating film included in the third capacitor layer, without contacting the upper electrode included in the second capacitor layer and the lower electrode included in the third capacitor layer; and the second via conductor is provided so as to penetrate the dummy lower electrode, the upper electrode, and the capacitance insulating film included in the second capacitor layer, and the lower electrode, the dummy upper electrode, and the capacitance insulating film included in the third capacitor layer, without contacting the lower electrode included in the second capacitor layer and the upper electrode included in the third capacitor layer.

6. A thin film capacitor comprising: a laminate consisting of a plurality of alternately stacked capacitor layers and a plurality of insulating layers; and first and second via conductors provided to penetrate the laminate, wherein each of the plurality of capacitor layers includes an upper electrode, a lower electrode, and a capacitive insulating film located between the upper electrode and the lower electrode, the plurality of capacitor layers including a first capacitor layer and a plurality of second capacitor layers, wherein each of the plurality of second capacitor layers has one of the upper electrode and the lower electrode connected to the first via conductor and the other of the upper electrode and the lower electrode connected to the second via conductor, at least a portion of the upper electrode included in the first capacitor layer is electrically isolated from the first and second via conductors, and at least a portion of the lower electrode included in the first capacitor layer is electrically isolated from the first and second via conductors.

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