Holographic display

Abstract

A holographic display is provided. The holographic display comprises: a light source panel including a plurality of light-emitting elements and a plurality of light-receiving elements configured to sense light emitted from the plurality of light-emitting elements; a spatial light modulator disposed on the light source panel; and a holography generation unit configured to provide hologram pattern information to the spatial light modulator on the basis of information on the light sensed by the light-receiving elements.

Description

holographic display

[0001] The present invention relates to a holographic display.

[0002] As the information society develops, demand for display devices capable of displaying images is increasing in various forms. In particular, holographic displays utilize the principle of reproducing an image of an original object by diffracting a reference light onto a holographic pattern, which records the interference pattern created by interfering the object light reflected from the original object with a reference light.

[0003] Meanwhile, as a type of digital holographic display, research is actively being conducted on a holographic display that provides a computer-generated hologram (CGH) as an electrical signal to a spatial light modulator instead of directly exposing an original object to obtain a hologram pattern, and the spatial light modulator forms a hologram pattern according to the input CGH signal and diffracts a reference light to create a 3D image.

[0004] The problem to be solved by the present invention is to provide a holographic display using an incoherent light source.

[0005] Another problem that the present invention seeks to solve is to provide a thin holographic display.

[0006] Another problem that the present invention seeks to solve is to provide a holographic display capable of complex modulation.

[0007] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0008] A holographic display according to one embodiment for solving the above problem includes a light source panel including a plurality of light-emitting elements and a plurality of light-receiving elements that sense light emitted from the plurality of light-emitting elements, a spatial light modulator arranged on the light source panel, and a holography generation unit configured to provide hologram pattern information to the spatial light modulator based on information of light sensed by the light-receiving elements.

[0009] The plurality of light-emitting elements and the plurality of light-receiving elements may correspond one-to-one to each other.

[0010] The plurality of light-emitting elements and the plurality of light-receiving elements can be arranged alternately.

[0011] The plurality of light-receiving elements may be positioned higher than the plurality of light-emitting elements.

[0012] The plurality of light-emitting elements and the plurality of light-receiving elements can be arranged in the same layer.

[0013] A reflector is disposed between the plurality of light-emitting elements and the plurality of light-receiving elements, and the reflector can reflect light emitted from the plurality of light-emitting elements and cause it to be incident on the plurality of light-receiving elements.

[0014] The light source panel further includes a separation portion that surrounds at least a portion of the plurality of light-emitting elements and at least a portion of the plurality of light-receiving elements on a plane, wherein the plurality of light-emitting elements include a first light-emitting element, and the plurality of light-receiving elements include a first light-receiving element and a second light-receiving element that are respectively arranged on both sides of the first light-emitting element, and the separation portion may not be arranged between the first light-emitting element and the first light-receiving element, but may be arranged between the first light-emitting element and the second light-receiving element.

[0015] The height of the above separation portion may be greater than the height of the light-emitting element and the height of the light-receiving element.

[0016] The light-receiving element may include a first electrode, a light-receiving layer disposed on the first electrode, and a second electrode disposed on the light-receiving layer.

[0017] The above light-receiving element may further include a light sorting layer disposed on the light-receiving layer and including a plurality of polarizing plates having polarization axes at different angles.

[0018] The above light-receiving layer may include a plurality of polarizing patterns having polarization axes at different angles.

[0019] The above spatial light modulator may be a transmissive spatial light modulator.

[0020] The above light source panel is a self-luminous panel and may include an incoherent light source.

[0021] The lights emitted from the plurality of light-emitting elements have random phases that are the same or different from each other, and the holography generating unit can be configured to reflect the difference in the random phases of the lights emitted from the plurality of light-emitting elements in the hologram pattern information and provide it to the spatial light modulator.

[0022] The light source panel may be configured to control the amplitude of the lights emitted from the plurality of light-emitting elements, and the spatial light modulator may be configured to control the phase of the lights emitted from the plurality of light-emitting elements.

[0023] The above light source panel and the above spatial light modulator may have a planar or plate-shaped shape.

[0024] The light source panel may include a plurality of light source pixels in which the plurality of light emitting elements are respectively arranged, and the spatial light modulator may include a plurality of light modulation pixels corresponding one-to-one to the plurality of light source pixels.

[0025] The light source panel further includes a light source driving device that drives the plurality of light source pixels, the spatial light modulator further includes a light modulation driving device that drives the plurality of light modulation pixels, and the light source driving device and the light modulation driving device may be provided separately.

[0026] According to another embodiment for solving the above problem, a holographic display includes a light source panel including a first conductive layer, a first material layer disposed on the first conductive layer, a second conductive layer disposed on the first material layer, a light emitting element including a pixel electrode included in the first conductive layer, a light emitting layer included in the first material layer, and a common electrode included in the second conductive layer, and a light receiving element including a sensor electrode included in the first conductive layer, a light receiving layer included in the first material layer, and the common electrode, a spatial light modulator disposed on the light source panel, and a holographic generation unit configured to provide hologram pattern information to the spatial light modulator based on information of light sensed by the light receiving element, wherein the light source panel further includes a reflector disposed between the light emitting element and the light receiving element.

[0027] The above reflective portion may be disposed on the second conductive layer.

[0028] According to another embodiment for solving the above problem, a holographic display includes a light source panel including a first conductive layer, a first material layer disposed on the first conductive layer, a second conductive layer disposed on the first material layer, a third conductive layer disposed on the second conductive layer, a second material layer disposed on the third conductive layer, a fourth conductive layer disposed on the second material layer, a light emitting element including a pixel electrode included in the first conductive layer, a light emitting layer included in the first material layer, and a common electrode included in the second conductive layer, and a light receiving element including a first electrode included in the third conductive layer, a light receiving layer included in the second material layer, and a second electrode included in the fourth conductive layer, a spatial light modulator disposed on the light source panel, and a holographic generation unit configured to provide hologram pattern information to the spatial light modulator based on information of light sensed by the light receiving element, wherein the light receiving element is positioned higher than the light emitting element.

[0029] According to a holographic display according to one embodiment of the present invention, an incoherent light source can be used.

[0030] According to one embodiment of the present invention, a holographic display can be made thinner.

[0031] According to a holographic display according to one embodiment of the present invention, complex modulation may be possible.

[0032] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0033] FIG. 1 is a perspective view illustrating a holographic display according to one embodiment.

[0034] FIG. 2 is an exploded perspective view showing a holographic display according to one embodiment.

[0035] FIG. 3 is a cross-sectional view showing a holographic display according to one embodiment.

[0036] FIG. 4 is a plan view showing a light source panel according to one embodiment.

[0037] FIG. 5A is a cross-sectional view showing an example of a light source panel according to one embodiment.

[0038] FIG. 5b is a cross-sectional view showing another example of a light source panel according to one embodiment.

[0039] Fig. 5c is a cross-sectional view showing a light emitting diode element of the light source panel of Fig. 5b.

[0040] FIG. 5d is a cross-sectional view showing another example of a light source panel according to one embodiment.

[0041] FIG. 6 is a plan view showing a spatial light modulator according to one embodiment.

[0042] FIG. 7 is a plan view showing a display area of ​​a holographic display according to one embodiment.

[0043] FIG. 8 is a cross-sectional view showing a light-emitting area of ​​a holographic display according to one embodiment.

[0044] FIG. 9 is a cross-sectional view showing a sensor area of ​​a holographic display according to one embodiment.

[0045] Fig. 10 is a plan view showing an optical classification layer according to one embodiment.

[0046] Fig. 11 is a plan view showing a light-receiving layer according to one embodiment.

[0047] Fig. 12 is a cross-sectional view showing a light-emitting area and a sensor area according to one embodiment.

[0048] Fig. 13 is a plan view showing a light-receiving layer according to another embodiment.

[0049] Fig. 14 is a cross-sectional view showing a light-emitting area and a sensor area according to another embodiment.

[0050] Fig. 15 is a plan view showing a light source panel according to another embodiment.

[0051] Fig. 16 is a plan view showing a spatial light modulator according to another embodiment.

[0052] FIG. 17 is a cross-sectional view showing a holographic display according to another embodiment.

[0053] Fig. 18 is a cross-sectional view showing a light-emitting area and a sensor area according to another embodiment.

[0054] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0055] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly above the other element or layer or where there is another layer or material intervening therebetween. Similarly, references to "below," "left," and "right" include both cases where the other element or layer is directly adjacent to the other element or where there is another layer or material intervening therebetween. Like reference numerals throughout the specification refer to like elements.

[0056] Specific embodiments are described below with reference to the attached drawings.

[0057] FIG. 1 is a perspective view illustrating a holographic display according to one embodiment.

[0058] Referring to FIG. 1, a holographic display (10) according to one embodiment can reproduce an image of an original object by diffracting a reference light onto a holographic pattern that records an interference pattern obtained by interfering the object light reflected from the original object with the reference light. For example, the holographic display (10) can generate and reproduce a holographic image (HI) of a three-dimensional shape.

[0059] In some embodiments, the holographic display (10) can generate a holographic image (HI) using information about a digitized object via a computer instead of an actual original object. For example, a computer-generated hologram (CGH) generated by a holography generation unit (700) (see FIG. 2) is provided as an electrical signal to a spatial light modulator (300) (see FIG. 2), and the spatial light modulator (300) (see FIG. 2) can generate a holographic image (HI) by diffracting a reference light based on the computer-generated hologram (CGH).

[0060] The holographic image (HI) generated by the holographic display (10) according to the present embodiment is formed three-dimensionally in a three-dimensional space using interference of light, so that the user (PS) can view the holographic image (HI) with the naked eye without wearing separate glasses or a head mounted display (HMD).

[0061] Fig. 2 is an exploded perspective view showing a holographic display according to one embodiment. Fig. 3 is a cross-sectional view showing a holographic display according to one embodiment.

[0062] Referring to FIGS. 2 and 3, a holographic display (10) according to one embodiment may include a light source panel (100), a spatial light modulator (300), an optical member (500), and a holography generating unit (700).

[0063] The light source panel (100) can emit light in a direction facing the user (PS). For example, the light source panel (100) can emit light in a third direction (DR3).

[0064] In the illustrated drawing, the third direction (DR3) may refer to the thickness direction of the holographic display (10). The third direction (DR3) may be a vertical direction. The first direction (DR1) and the second direction (DR2) intersect with respect to the third direction (DR3), and may be, for example, a horizontal direction orthogonal to the third direction (DR3). The first direction (DR1) and the second direction (DR2) intersect with each other as a horizontal direction, and for example, the first direction (DR1) and the second direction (DR2) may be orthogonal to each other. Unless otherwise defined, in the present specification, the direction indicated by the arrows of the first to third directions (DR1, DR2, DR3) may be referred to as one side, and the opposite direction may be referred to as the other side.

[0065] The light source panel (100) may have a planar or plate-like shape extending in a direction perpendicular to the thickness direction of the holographic display (10). For example, the light source panel (100) may extend in a horizontal direction perpendicular to a third direction (DR3), for example, in the first direction (DR1) and the second direction (DR2). The thickness of the light source panel (100), for example, the length in the third direction (DR3), may be smaller than the horizontal length of the light source panel (100), for example, the length in the first direction (DR1) and the second direction (DR2).

[0066] The light source panel (100) may be a self-luminous panel. The light source panel (100) may include an incoherent light source. For example, the light source panel (100) may be an organic light emitting display panel, a micro light emitting diode display panel, or a nano light emitting diode display panel. However, if the light source panel (100) is a display panel including an incoherent light source, it is not limited to the types of display panels described above.

[0067] The light source panel (100) may include a plurality of light source pixels (SP) that are arranged to be spaced apart from each other in the horizontal direction. The plurality of light source pixels (SP) may each emit light in a third direction (DR3).

[0068] The light source panel (100) can individually control the intensity of light emitted from each of the plurality of light source pixels (SP). Accordingly, the light source panel (100) can individually control the amplitude of light emitted from each of the plurality of light source pixels (SP).

[0069] A detailed description of the structure of the light source panel (100) will be described later with reference to FIG. 4, etc.

[0070] The spatial light modulator (300) may be disposed on one side of the light source panel (100). For example, the spatial light modulator (300) may be disposed on one side of the light source panel (100) in the third direction (DR3). The spatial light modulator (300) may be disposed on the display surface or the light-emitting surface of the light source panel (100). The surface of the light source panel (100) on which the spatial light modulator (300) is disposed may be a surface facing the user (PS). The spatial light modulator (300) may be located between the light source panel (100) and the user (PS).

[0071] The spatial light modulator (300) may have a planar or plate-like shape extending in a direction perpendicular to the thickness direction of the holographic display (10). For example, the spatial light modulator (300) may extend in a horizontal direction perpendicular to a third direction (DR3), for example, in the first direction (DR1) and the second direction (DR2). The thickness of the spatial light modulator (300), for example, the length in the third direction (DR3), may be smaller than the horizontal length of the spatial light modulator (300), for example, the length in the first direction (DR1) and the second direction (DR2).

[0072] The holographic display (10) according to the present embodiment can be easily made thinner by attaching a spatial light modulator (300) in a planar or plate-shaped shape to a light source panel (100) in a planar or plate-shaped shape.

[0073] The spatial light modulator (300) may include a plurality of light modulation pixels (MP) that are arranged to be spaced apart from each other in the horizontal direction. The plurality of light modulation pixels (MP) may transmit light emitted from the plurality of light source pixels (SP) in a third direction (DR3). The light emitted from the plurality of light source pixels (SP) may be transmitted through the plurality of light modulation pixels (MP) and provided to the user (PS). The user (PS) may recognize a holographic image (HI) through the light transmitted through the spatial light modulator (300).

[0074] The plurality of light modulation pixels (MP) of the spatial light modulator (300) can individually control the phase or amplitude of light emitted from the plurality of light source pixels (SP) of the light source panel (100). For example, the spatial light modulator (300) can individually control the phase or amplitude of light emitted from the plurality of light source pixels (SP) based on digital hologram pattern information provided from the holography generation unit (700), thereby generating a holographic image (HI).

[0075] The spatial light modulator (300) may be a transmissive spatial light modulator (300). For example, the spatial light modulator (300) may be a liquid crystal spatial light modulator (LC-SLM).

[0076] The optical member (500) may be disposed on one side of the spatial light modulator (300). For example, the optical member (500) may be disposed on one side of the spatial light modulator (300) in the third direction (DR3). The optical member (500) may be disposed on the light-emitting surface of the spatial light modulator (300). The surface of the spatial light modulator (300) on which the optical member (500) is disposed may be a surface facing the user (PS). The optical member (500) may be positioned between the spatial light modulator (300) and the user (PS).

[0077] The optical member (500) can adjust the size and shape of the image, such as enlarging or reducing the image of the holographic image (HI), by controlling the light transmitted from the spatial light modulator (300). For example, the optical member (500) can include various lenses, such as a convex lens, a concave lens, a cylindrical lens, a compound lens, a Fresnel lens, an anamorphic lens, a meniscus lens, etc. However, the present invention is not limited thereto, and the optical member (500) may also include other members, such as a mirror.

[0078] The holographic generation unit (700) can generate a computer-generated hologram (CGH). For example, a computer-generated hologram is a holographic pattern and can include information about the amplitude and phase of light for generating a holographic image (HI).

[0079] The holography generation unit (700) can generate a hologram pattern by reflecting information about the amplitude and phase of the lights emitted from each of the plurality of light source pixels (SP) of the light source panel (100). The holography generation unit (700) can provide a hologram pattern in which information about the amplitude and phase of the lights emitted from each of the plurality of light source pixels (SP) of the light source panel (100) is reflected to the spatial light modulator (300). The spatial light modulator (300) can individually adjust the phase of the light according to the amplitude and phase of the lights reflected in the hologram pattern.

[0080] For example, the first lights (LGT1) emitted from each light source pixel (SP) may emit light with the same or different random phases (pseudo random phases). The holography generation unit (700) converts the random phases of the first lights (LGT1) into digital signals so that the phases of the first lights (LGT1) can be individually controlled through the spatial light modulator (300). Accordingly, the phases of the first lights (LGT1) can be synchronized with each other. Alternatively, the holography generation unit (700) may form a hologram pattern by considering the phase difference of the first lights (LGT1) without phase synchronization, and based on this, the spatial light modulator (300) may individually control the phases of the first lights (LGT1) to generate a holographic image (HI).

[0081] The light source panel (100) of the holographic display (10) according to the present embodiment may further include a plurality of light sensing pixels (OP) to sense the phase of the first light (LGT1).

[0082] The light sensing pixels (OP) can be arranged to be spaced apart from each other in the horizontal direction. The light sensing pixels (OP) can be arranged alternately with the light source pixels (SP). The light sensing pixels (OP) can be arranged to correspond one-to-one to the light source pixels (SP). The light sensing pixels (OP) can sense the first light (LGT1) emitted from each light source pixel (SP).

[0083] For example, a plurality of light source pixels (SP) can emit a first light (LGT1). Some of the first light (LGT1) can be incident on a plurality of light sensing pixels (OP). A holographic generation unit (700) can generate a holographic pattern based on information about the phase or amplitude of the first light (LGT1) sensed by the light sensing pixels (OP). The holographic generation unit (700) can provide the holographic pattern to the spatial light modulator (300).

[0084] Meanwhile, another portion of the first light (LGT1) may be incident on a plurality of light modulation pixels (MP). The plurality of light modulation pixels (MP) provided with the holographic pattern may control the phase or amplitude of the first light (LGT1). The first light (LGT1) may be converted into a second light (LGT2) by controlling the phase or amplitude. The user (PS) may recognize the holographic image (HI) through the converted second light (LGT2).

[0085] The holographic display (10) according to the present embodiment can control the amplitude of light using an incoherent light source and can control the phase or amplitude of light using a spatial light modulator (300) and a holography generating unit (700). That is, the holographic display (10) according to the present embodiment can be a holographic display (10) capable of complex modulation of amplitude and phase.

[0086] Meanwhile, the holographic display (10) according to the present embodiment may further include a reflector (RFP) depending on the positions of the light source pixel (SP) and the light sensing pixel (OP). The light source pixel (SP), the reflector (RFP), and the light sensing pixel (OP) will be described later with reference to FIG. 7 and the like.

[0087] FIG. 4 is a plan view showing a light source panel according to one embodiment.

[0088] In addition to FIG. 3, referring to FIG. 4, the light source panel (100) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be positioned approximately at the center of the light source panel (100), and the non-display area (NDA) may be positioned to surround the display area (DA).

[0089] The display area (DA) of the light source panel (100) may include a plurality of light source pixels (SP), a plurality of light sensing pixels (OP), a plurality of light source power lines (VL_LS), a plurality of gate lines (GL), a plurality of light emission control lines (ECL), a plurality of data lines (DL), and a readout line (ROL).

[0090] A plurality of light source pixels (SP) can be arranged in a first direction (DR1) and a second direction (DR2). For example, the plurality of light source pixels (SP) can be arranged in a matrix direction. Each of the plurality of light source pixels (SP) can be connected to a gate line (GL), a data line (DL), a light emission control line (ECL), and a light source power line (VL_LS). Each of the plurality of light source pixels (SP) can include at least one transistor, a light emitting element, and a capacitor.

[0091] A plurality of light sensing pixels (OP) can be arranged in a first direction (DR1) and a second direction (DR2). For example, the plurality of light sensing pixels (OP) can be arranged in a matrix direction. The plurality of light sensing pixels (OP) can be arranged alternately with a plurality of light source pixels (SP) in the first direction (DR1) and the second direction (DR2). Each of the plurality of light sensing pixels (OP) can be connected to a gate line (GL), a read-out line (ROL), and a light source power line (VL). Each of the plurality of light sensing pixels (OP) can include at least one transistor and a light receiving element.

[0092] Gate lines (GL) can extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2). The gate lines (GL) can sequentially supply gate signals to a plurality of light source pixels (SP) and a plurality of light sensing pixels (OP).

[0093] The light emission control lines (ECLs) can extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2). The light emission control lines (ECLs) can sequentially supply light emission signals to a plurality of light source pixels (SP).

[0094] The data lines (DL) can extend in a second direction (DR2) and be spaced apart from each other in a first direction (DR1). The data lines (DL) can supply data voltages received from the light source display driver (120) to a plurality of light source pixels (SP). The data voltages can determine the brightness of each of the plurality of light source pixels (SP).

[0095] The read-out lines (ROLs) can extend in a second direction (DR2) and be spaced apart from each other in a first direction (DR1). The read-out lines (ROLs) can receive sensing signals from a plurality of light sensing pixels (OP). The sensing signals can include information about the brightness of the sensed light. The read-out lines (ROLs) can provide the sensing signals received from the plurality of light sensing pixels (OPs) to the light source display driver (120).

[0096] The light source power line (VL_LS) can extend in the second direction (DR2) and be spaced apart from each other in the first direction (DR1). The light source power line (VL_LS) can supply a power voltage to a plurality of light source pixels (SP) and a plurality of light sensing pixels (OP). The power voltage can be at least one of a driving voltage, a high-potential voltage, an initialization voltage, a reference voltage, a bias voltage, and a low-potential voltage.

[0097] The light source timing control unit (110) can receive light source digital data (DATA_LS) and timing signals from the holography generation unit (700). The light source timing control unit (110) can generate a light source data control signal (DCS) based on the timing signals. The light source timing control unit (110) can control the operation timing of the light source display driving unit (120) by supplying the light source digital data (DATA_LS) and the light source data control signal (DCS) to the light source display driving unit (120).

[0098] The light source timing control unit (110) can generate a gate control signal (GCS) based on timing signals. The light source timing control unit (110) can control the operation timing of the light source gate driver (130) by supplying the gate control signal (GCS) to the light source gate driver (130). The light source timing control unit (110) can generate a light emission control signal (ECS) based on timing signals. The light source timing control unit (110) can control the operation timing of the light emission control driver (140) by supplying the light emission control signal (ECS) to the light emission control driver (140).

[0099] The light source display driving unit (120) can convert light source digital data (DATA_LS) into analog data voltages and supply them to the data line (DL). The light source display driving unit (120) can convert a sensing signal received through the read-out line (ROL) into light sensing digital data (DATA_SS) and supply them to the holography generation unit (700).

[0100] The light source gate driver (130) and the light emission control driver (140) may be positioned on the left or right side of the non-display area (NDA). For example, the light source gate driver (130) and the light emission control driver (140) may be positioned on the left and right sides of the non-display area (NDA), but the present invention is not limited thereto. For another example, the light source gate driver (130) may be positioned on the left side of the non-display area (NDA), and the light emission control driver (140) may be positioned on the right side of the non-display area (NDA).

[0101] The light source gate driver (130) may include a plurality of transistors and may generate gate signals based on a gate control signal (GCS). The gate signals of the light source gate driver (130) may select light source pixels (SP) and light sensing pixels (OP) to which data voltages are supplied, and the selected light source pixels (SP) may receive data voltages through data lines (DL) or the selected light sensing pixels (OP) may transmit sensing signals through read-out lines (ROL).

[0102] The light emission control driver (140) may include a plurality of transistors and may generate light emission signals based on a light emission control signal (ECS). For example, the transistors of the light source gate driver (130) and the transistors of the light emission control driver (140) may be formed on the same layer as the transistors of each of the light source pixels (SP). The light source gate driver (130) may supply gate signals to the gate lines (GL), and the light emission control driver (140) may supply light emission signals to the light emission control lines (ECL).

[0103] The light source power supply unit (150) can supply power voltage to the light source display driver unit (120) and the light source panel (100). The light source power supply unit (150) can generate a power voltage and supply it to the light source power line (VL_LS), and can generate a common voltage and supply it to a common electrode common to the light source pixels (SP) and the light sensing pixels (OP). The light source power supply unit (150) can generate a driving voltage of a light emitting element and supply it to the driving voltage line, generate an initialization voltage and supply it to the initialization voltage line, generate a bias voltage and supply it to the bias voltage line, and generate a low-potential voltage and supply it to the low-potential line.

[0104] A light source timing control unit (110), a light source display driving unit (120), a light source gate driving unit (130), a light emission control driving unit (140), and a light source power supply unit (150) may be included in the light source driving device.

[0105] FIG. 5A is a cross-sectional view showing an example of a light source panel according to one embodiment.

[0106] Referring to FIG. 5a, a light source panel (100) according to one embodiment may be an organic light emitting diode display panel having an organic light emitting diode element (LEL) including an organic light emitting layer (LE).

[0107] The light source panel (100) may include a base member (BS), a display layer (DISL), and an encapsulation layer (ENC).

[0108] The base member (BS) may include a substrate (SUB) and a first buffer film (BF1).

[0109] The substrate (SUB) may be made of an insulating material such as glass, quartz, or a polymer resin. Examples of the polymer material include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the substrate (SUB) may include a metallic material.

[0110] The substrate (SUB) may be a rigid substrate (SUB) or a flexible substrate (SUB) that can be bent, folded, rolled, etc. If the substrate (SUB) is a flexible substrate (SUB), it may be formed of polyimide (PI), but is not limited thereto.

[0111] The first buffer film (BF1) may be disposed on the substrate (SUB). The first buffer film (BF1) may be formed of an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. Alternatively, the first buffer film (BF1) may be formed as a multi-film in which a plurality of layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated.

[0112] The display layer (DISL) may include a thin film transistor layer (TFTL) including a plurality of thin film transistors and an light emitting element layer (EML) including a plurality of light emitting elements.

[0113] An active layer including a channel region (TCH), a source region (TS), and a drain region (TD) of a thin film transistor (TFT) may be disposed on a first buffer film (BF1). The active layer may be formed of polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material. When the active layer includes polycrystalline silicon or an oxide semiconductor material, the source region (TS) and the drain region (TD) in the active layer may be conductive regions doped with ions or impurities to have conductivity.

[0114] A gate insulating film (GI) may be disposed on an active layer of a thin film transistor (TFT). The gate insulating film (GI) may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0115] A first gate metal layer including a gate electrode (TG) of a thin film transistor (TFT), a first capacitor electrode (CAE1) of a capacitor (Cst), and scan lines may be disposed on a gate insulating film (GI). The gate electrode (TG) of the thin film transistor (TFT) may overlap a channel region (TCH) in a first direction (DR1). The first gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0116] A first interlayer insulating film (ILD1) may be disposed on the first gate metal layer. The first interlayer insulating film (ILD1) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film (ILD1) may include a plurality of inorganic films.

[0117] A second gate metal layer including a second capacitor electrode (CAE2) of a capacitor (Cst) may be disposed on a first interlayer insulating film (ILD1). The second capacitor electrode (CAE2) may overlap the first capacitor electrode (CAE1) in the first direction (DR1). Therefore, the capacitor (Cst) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the inorganic insulating dielectric film disposed therebetween and serving as a dielectric film. The second gate metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0118] A second interlayer insulating film (ILD2) may be disposed on the second gate metal layer. The second interlayer insulating film (ILD2) may be formed of an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film (ILD2) may include a plurality of inorganic films.

[0119] A first data metal layer including a first connection electrode (CE1) and data lines may be disposed on a second interlayer insulating film (ILD2). The first connection electrode (CE1) may be connected to a drain region (TD) through a first contact hole (CT1) penetrating the gate insulating film (GI), the first interlayer insulating film (ILD1), and the second interlayer insulating film (ILD2). The first data metal layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0120] A first organic film (PVX1) for leveling the steps caused by thin film transistors (TFTs) may be disposed on the first connection electrode (CE1). The first organic film (PVX1) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0121] A second data metal layer including a second connection electrode (CE2) may be disposed on a first organic film (PVX1). The second data metal layer may be connected to the first connection electrode (CE1) through a second contact hole (CT2) penetrating the first organic film (PVX1). The second data metal layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0122] The second organic film (PVX2) may be disposed on the second connection electrode (CE2). The second organic film (PVX2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0123] Meanwhile, the second data metal layer including the second connection electrode (CE2) and the second organic film (PVX2) may be omitted.

[0124] An emission layer (EML) may be disposed on a thin film transistor layer (TFTL). The emission layer (EML) may include light emitting diode elements (LELs) and a bank (PDL).

[0125] Each of the light emitting diode elements (LEL) may include a pixel electrode (AE), an emission layer (LE), and a common electrode (CE). Each of the emission areas (EA) represents a region in which the pixel electrode (AE), the emission layer (LE), and the common electrode (CE) are sequentially laminated, and holes from the pixel electrode (AE) and electrons from the common electrode (CE) combine with each other in the emission layer (LE) to emit light. In this case, the pixel electrode (AE) may be an anode electrode, and the common electrode (CE) may be a cathode electrode.

[0126] A pixel electrode layer including a pixel electrode (AE) may be formed on a second organic film (PVX2). The pixel electrode (AE) may be connected to a second connection electrode (CE2) through a third contact hole (CT3) penetrating the second organic film (PVX2). The pixel electrode layer may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0127] In a top emission structure that emits light in the direction of a common electrode (CE) based on the light-emitting layer (LE), the pixel electrode (AE) may be formed as a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0128] The bank (PDL) may serve to define the light emitting areas (EA) of the pixels. The bank (PDL) may be formed to expose a portion of the pixel electrode (AE) on the second organic film (PVX2). The bank (PDL) may cover an edge of the pixel electrode (AE). At least a portion of the bank (PDL) may be disposed within the third contact hole (CT3). That is, the third contact hole (CT3) may be filled by the bank (PDL). The bank (PDL) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0129] A spacer (SPC) may be placed on the bank (PDL). The spacer (SPC) may serve to support the mask during the process of manufacturing the light-emitting layer (LE). The spacer (SPC) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0130] An emission layer (LE) may be formed on the pixel electrode (AE). The emission layer (LE) may include an organic material and emit light of a predetermined color. For example, the emission layer (LE) may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host and a dopant. The organic material layer may include a material that emits a predetermined light, and may be formed using a phosphorescent material or a fluorescent material.

[0131] A common electrode (CE) may be formed on the light-emitting layer (LE). The common electrode (CE) may be formed to cover the light-emitting layer (LE). The common electrode (CE) may be a common layer formed in common across the light-emitting areas (EA). A capping layer may be formed on the common electrode (CE).

[0132] In the upper light-emitting structure, the common electrode (CE) can be formed of a transparent conductive material (TCO) that can transmit light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode (CE) is formed of a semi-transmissive metallic material, the light-emitting efficiency can be increased by the micro cavity.

[0133] An encapsulation layer (ENC) may be formed on the light emitting element layer (EML). The encapsulation layer (ENC) may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer (EML). In addition, the encapsulation layer (ENC) may include at least one organic film to protect the light emitting element layer (EML) from foreign substances such as dust. For example, the encapsulation layer (ENC) may include a first encapsulation inorganic film (TFE1), an encapsulation organic film (TFE2), and a second encapsulation inorganic film (TFE3).

[0134] A first encapsulating inorganic film (TFE1) may be disposed on a common electrode (CE), an encapsulating organic film (TFE2) may be disposed on the first encapsulating inorganic film (TFE1), and a second encapsulating inorganic film (TFE3) may be disposed on the encapsulating organic film (TFE2). The first encapsulating inorganic film (TFE1) and the second encapsulating inorganic film (TFE3) may be formed as a multi-film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated. The encapsulating organic film (TFE2) may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0135] Fig. 5b is a cross-sectional view showing another example of a light source panel according to one embodiment. Fig. 5c is a cross-sectional view showing a light emitting diode element of the light source panel of Fig. 5b.

[0136] Referring to FIGS. 5b and 5c, a light source panel (100) according to one embodiment may be an inorganic light emitting diode display panel having an inorganic light emitting layer (LE_1) and an inorganic light emitting diode element (LEL_1) extending in a third direction (DR3). The light emitting diode element (LEL_1) may have a length or size in micrometers and may be a micro light emitting diode made of an inorganic material. In this case, the light source panel (100) according to one embodiment may be a micro light emitting diode display panel.

[0137] Since the light source panel (100) according to one embodiment includes a light emitting diode element (LEL_1) made of an inorganic material, an encapsulation structure is not required. Therefore, the light source panel (100) according to one embodiment may not include an encapsulation layer (ENC) (see FIG. 5a).

[0138] Additionally, when the light emitting diode element (LEL_1) of the light source panel (100) according to one embodiment emits the same light, it may include a color control layer (CCL). When the light emitting diode element (LEL_1) of the light source panel (100) according to one embodiment is divided into elements that emit multiple colors, the color control layer (CCL) may be omitted.

[0139] The light source panel (100) may include a base member (BS) and a display layer (DISL). The display layer (DISL) may include a thin film transistor layer (TFTL), an emission layer (EML), and a color control layer (CCL).

[0140] The base member (BS) and the thin film transistor layer (TFTL) illustrated in FIG. 5b are substantially the same as the base member (BS) and the thin film transistor layer (TFTL) described with reference to FIG. 5a, and therefore, the description of the base member (BS) and the thin film transistor (TFTL) is omitted in FIG. 5b.

[0141] The light emitting element layer (EML) may include light emitting diode elements (LEL_1), a bank (PDL), a third organic film (PVX3), and a fourth organic film (PVX4).

[0142] Each of the light emitting diode elements (LEL_1) may include a pixel electrode (AE_1), a light emitting layer (LE_1), and a common electrode (CE_1). Each of the plurality of light emitting diode elements (LEL_1) is exemplified as a vertical micro LED extending in a third direction (DR3). In this case, each of the plurality of light emitting diode elements (LEL_1) may have a rectangular or reverse taper cross-sectional shape. However, each of the plurality of light emitting diode elements (LEL_1) is not limited to being a vertical micro LED, and may be a flip-type micro LED.

[0143] Each of the plurality of light-emitting diode elements (LEL_1) may be formed of an inorganic material such as GaN. Each of the plurality of light-emitting diode elements (LEL_1) may have a length of several to several hundred μm. For example, each of the plurality of light-emitting diode elements (LEL_1) may have a length of approximately 100 μm or less.

[0144] The light emitting diode element (LEL_1) may have a length or size in micrometers and may be an inorganic light emitting diode made of an inorganic material. The light emitting diode element (LEL_1) may have a shape extending in one direction. Each of the plurality of light emitting diode elements (LEL_1) may have a shape such as a cylinder, a rod, a wire, a tube, etc. However, the shape of the light emitting diode element (LEL_1) is not limited thereto, and may have a shape of a polygonal column such as a cube, a rectangular parallelepiped, a hexagonal column, or a shape extending in one direction but having an outer surface that is partially inclined.

[0145] Since the pixel electrode (AE_1) is substantially the same as the pixel electrode (AE) described in conjunction with FIG. 5a, the description of the pixel electrode (AE_1) is omitted in FIG. 5b.

[0146] The bank (PDL) may be arranged to cover the edge of the pixel electrode (AE_1). The bank (PDL) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The bank (PDL) may include a light-blocking material to prevent light from a light-emitting diode element (LEL_1) of a sub-pixel from propagating to an adjacent sub-pixel. For example, the bank (PDL) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0147] Each of the plurality of light-emitting layers (LE_1) can be arranged on a pixel electrode (AE_1) that is exposed and not covered by a bank (PDL).

[0148] Each of the light-emitting layers (LE_1) of the light-emitting diode element (LEL_1) can be grown and formed on a semiconductor substrate such as a silicon wafer. Each of the light-emitting layers (LE_1) of the light-emitting diode element (LEL_1) can be transferred directly from the silicon wafer onto the pixel electrode (AE_1). Alternatively, each of the light-emitting layers (LE_1) of the light-emitting diode element (LEL_1) can be transferred onto the pixel electrode (AE_1) by an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0149] The light-emitting layer (LE_1) of the light-emitting diode elements (LEL_1) may include a contact electrode (CTE), a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2), as shown in FIG. 5c.

[0150] The contact electrode (CTE) may be disposed on the pixel electrode (AE_1). The contact electrode (CTE) and the pixel electrode (AE_1) may be melt-bonded by heat and pressure. Alternatively, the contact electrode (CTE) and the pixel electrode (AE_1) may be bonded to each other through a conductive adhesive such as an anisotropic conductive film or an anisotropic conductive adhesive. Alternatively, the contact electrode (CTE) and the pixel electrode (AE_1) may be bonded to each other through a soldering process. For example, the contact electrode (CTE) may include at least one of gold (Au), copper (Cu), aluminum (Al), and tin (Sn).

[0151] The first semiconductor layer (SEM1) may be disposed on the contact electrode (CTE). The first semiconductor layer (SEM1) may be formed of GaN doped with a p-type conductive dopant such as Mg, Zn, Ca, Se, or Ba.

[0152] An electron blocking layer (EBL) may be disposed on the first semiconductor layer (SEM1). The electron blocking layer (EBL) may be a layer that suppresses or prevents excessive electrons from flowing into the active layer (MQW). For example, the electron blocking layer (EBL) may be p-AlGaN doped with p-type magnesium. The electron blocking layer (EBL) may be omitted.

[0153] The active layer (MQW) can be disposed on the electron blocking layer (EBL). The active layer (MQW) can emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0154] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer (MQW) may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, or may include different group III to group V semiconductor materials depending on the wavelength of the emitted light.

[0155] When the active layer (MQW) includes InGaN, the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift toward a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift toward a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of the light-emitting diode element (LEL_1) that emits light in a blue wavelength band may be approximately 10 wt% to 20 wt%.

[0156] A superlattice layer (SLT) may be disposed on the active layer (MQW). The superlattice layer (SLT) may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer (SLT) may be formed of InGaN or GaN. The superlattice layer (SLT) may be omitted.

[0157] The second semiconductor layer (SEM2) may be disposed on the superlattice layer (SLT). The second semiconductor layer (SEM2) may be doped with a second conductivity type dopant, such as Si, Ge, Sn, etc. For example, the second semiconductor layer (SEM2) may be n-GaN doped with n-type Si.

[0158] A third organic film (PVX3) may be disposed on the pixel electrode (AE_1) that is not covered by the bank (PDL) and the plurality of light-emitting diode elements (LEL_1). The third organic film (PVX3) may be disposed to cover a side surface and a portion of an upper surface of the bank (PDL). The height of the third organic film (PVX3) may be greater than the height of the bank (PDL). The third organic film (PVX3) may be disposed on a portion of a side surface of each of the plurality of light-emitting diode elements (LEL_1). The height of the third organic film (PVX3) may be less than the height of each of the plurality of light-emitting diode elements (LEL_1). The third organic film (PVX3) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0159] The fourth organic film (PVX4) may be disposed on the third organic film (PVX3). The fourth organic film (PVX4) may be disposed on a portion of a side surface of each of the plurality of light-emitting diode elements (LEL_1). The sum of the height of the third organic film (PVX3) and the height of the fourth organic film (PVX4) may be smaller than the height of each of the plurality of light-emitting diode elements (LEL_1). The fourth organic film (PVX4) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0160] The third organic film (PVX3) and the fourth organic film (PVX4) are layers for leveling the steps caused by the plurality of light-emitting diode elements (LEL_1). If the height of each of the plurality of light-emitting diode elements (LEL_1) is similar to the height of the third organic film (PVX3), the fourth organic film (PVX4) may be omitted.

[0161] The common electrode (CE_1) may be disposed on the upper surface of each of the light-emitting layers (LE_1) and the upper surface of the fourth organic film (PVX4). The common electrode (CE_1) may be disposed on the bank (PDL) that is exposed and not covered by the third organic film (PVX3) and the fourth organic film (PVX4). The common electrode (CE_1) may be a common layer formed commonly in the first sub-pixel, the second sub-pixel, and the third sub-pixel. The common electrode (CE_1) may be made of a transparent conductive material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0162] The color control layer (CCL) may include a first capping layer (CAP1), a light-shielding layer (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), a light-transmitting layer (TPL), a second capping layer (CAP2), a fifth organic film (PVX5), a plurality of color filters (CF1, CF2, CF3), and a sixth organic film (PVX6).

[0163] The first capping layer (CAP1) may be disposed on the common electrode (CE_1). The first capping layer (CAP1) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0164] A light-shielding layer (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light-transmitting layer (TPL) may be disposed on a first capping layer (CAP1). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL) may be formed by the partitioning of the light-shielding layer (BM). Therefore, in a first sub-pixel that outputs a first light, a first light conversion layer (QDL1) may be disposed on the first capping layer (CAP1), in a second sub-pixel that outputs a second light, a second light conversion layer (QDL2) may be disposed on the first capping layer (CAP1), and in a third sub-pixel that outputs a third light, a light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The shading layer (BM) overlaps the bank (PDL) in the third direction (DR3) and may not overlap the plurality of light-emitting diode elements (LEL_1).

[0165] The first light conversion layer (QDL1) can convert a portion of the light in the blue wavelength band incident from the light emitting diode element (LEL_1) into light in the red wavelength band. The first light conversion layer (QDL1) can include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) can include a light-transmitting organic material. For example, the first base resin (BRS1) can include an epoxy-based resin, an acrylic resin, a cardo-based resin, or an imide-based resin. The first wavelength conversion particle (WCP1) can convert a portion of the light in the blue wavelength band incident from the light emitting diode element (LEL_1) into light in the red wavelength band. The first wavelength conversion particle (WCP1) can be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material.

[0166] The second light conversion layer (QDL2) can convert a portion of the light in the blue wavelength band incident from the light emitting diode element (LEL_1) into light in the green wavelength band. It can include a second base resin (BRS2) and a second wavelength conversion particle (WCP2). The second base resin (BRS2) can include a light-transmitting organic material. For example, the second base resin (BRS2) can include an epoxy-based resin, an acrylic resin, a cardo-based resin, or an imide-based resin. The second wavelength conversion particle (WCP2) can convert a portion of the light in the blue wavelength band incident from the light emitting diode element (LEL_1) into light in the green wavelength band. The second wavelength conversion particle (WCP2) can be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material.

[0167] The light transmitting layer (TPL) may include a light transmitting organic material. For example, the light transmitting layer (TPL) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin.

[0168] The light-blocking layer (BM) may include a first light-blocking layer (BM1) and a second light-blocking layer (BM2) that are sequentially laminated. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include a light-blocking material to prevent light from a light-emitting diode element (LEL_1) of a sub-pixel from propagating to an adjacent sub-pixel. For example, the first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0169] A second capping layer (CAP2) may be disposed on the light-shielding layer (BM), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL). The second capping layer (CAP2) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The light-shielding layer (BM), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL) may be encapsulated by the first capping layer (CAP1) and the second capping layer (CAP2).

[0170] A fifth organic film (PVX5) may be disposed on the second capping layer (CAP2). The fifth organic film (PVX5) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0171] A plurality of color filters (CF1, CF2, CF3) may be arranged on the fifth organic film (PVX5). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0172] Each of the first color filters (CF1) arranged in the first sub-pixel can transmit light in the red wavelength band and absorb or block light in the blue wavelength band. Therefore, each of the first color filters (CF1) can transmit light in the red wavelength band converted by the first light conversion layer (QDL1) among the light in the blue wavelength band emitted from the light emitting diode element (LEL_1), and absorb or block light in the blue wavelength band not converted by the first light conversion layer (QDL1). Therefore, the first sub-pixel can emit light in the red wavelength band.

[0173] Each of the second color filters (CF2) arranged in the second sub-pixel can transmit light in the green wavelength band and absorb or block light in the blue wavelength band. Therefore, each of the second color filters (CF2) can transmit light in the green wavelength band converted by the first light conversion layer (QDL1) among the light in the blue wavelength band emitted from the light emitting diode element (LEL_1), and absorb or block light in the blue wavelength band not converted by the first light conversion layer (QDL1). Therefore, the second sub-pixel can emit light in the green wavelength band.

[0174] Each of the third color filters (CF3) arranged in the third sub-pixel can transmit light in the blue wavelength band. Therefore, each of the third color filters (CF3) can transmit light in the blue wavelength band emitted from the light-emitting diode element (LEL_1) passing through the light-transmitting layer (TPL). Therefore, the third sub-pixel can emit light in the blue wavelength band.

[0175] A sixth organic film (PVX6) for planarization may be disposed on a plurality of color filters (CF1, CF2, CF3). The sixth organic film (PVX6) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0176] FIG. 5d is a cross-sectional view showing another example of a light source panel according to one embodiment.

[0177] Referring to FIG. 5D, a light source panel (100) according to one embodiment may be an inorganic light emitting diode display panel having an inorganic light emitting layer (LE_2) and an inorganic light emitting diode element (LEL_2) extending in a horizontal direction perpendicular to a third direction (DR3). The light emitting diode element (LEL_2) may have a length or size in nanometers and may be a nano light emitting diode made of an inorganic material. In this case, the light source panel (100) according to one embodiment may be a nano light emitting diode display panel.

[0178] Since the light source panel (100) according to one embodiment includes a light emitting diode element (LEL_2) made of an inorganic material, an encapsulation structure is not required. Therefore, the light source panel (100) according to one embodiment may not include an encapsulation layer (ENC) (see FIG. 5a).

[0179] In addition, when the light emitting diode element (LEL_2) of the light source panel (100) according to one embodiment emits the same light, the color control layer (CCL) (see FIG. 5b) illustrated in FIG. 5b may be included. In FIG. 5d, for convenience of explanation, the color control layer (CCL) is omitted. In addition, when the light emitting diode element (LEL_2) of the light source panel (100) according to one embodiment is divided into elements that emit a plurality of colors, the color control layer (CCL) may be omitted.

[0180] The light source panel (100) may include a base member (BS) and a display layer (DISL). The display layer (DISL) may include a thin film transistor layer (TFTL) and a light emitting element layer (EML).

[0181] The thin film transistor layer (TFTL) illustrated in FIG. 5d will be described mainly based on differences from the thin film transistor layer (TFTL) illustrated in FIG. 5a, and duplicate descriptions will be omitted.

[0182] In Fig. 5d, the second gate metal layer, the second interlayer insulating film (ILD2) (see Fig. 5a), the second data metal layer, and the second organic film (PVX2) (see Fig. 5a) are omitted. In addition, in Fig. 5d, the capacitor (Cst) (see Fig. 5a) is omitted for convenience of explanation.

[0183] As illustrated in FIG. 5D, a first data metal layer including a first connection electrode (CE1), a second connection electrode (CE2_1), and a third connection electrode (CE3) may be disposed on a first interlayer insulating film (ILD1). The first connection electrode (CE1) may be connected to a drain region (TD) through a first contact hole (CT1) penetrating the first interlayer insulating film (ILD1). The second connection electrode (CE2_1) may be connected to a source region (TS) through a second contact hole (CT2_1) penetrating the first interlayer insulating film (ILD1).

[0184] The light emitting element layer (EML) may include first to third bank patterns (BP1, BP2, BP3), an alignment electrode (RME), a contact electrode (CNE), and light emitting diode elements (LEL_2).

[0185] The first bank pattern (BP1) may be arranged between the second bank pattern (BP2) and the third bank pattern (BP3). That is, the second bank pattern (BP2) may be arranged on one side of the first bank pattern (BP1), and the third bank pattern (BP3) may be arranged on the other side of the first bank pattern (BP1).

[0186] A plurality of light emitting diode elements (LEL_2) may be arranged between the first and second bank patterns (BP1, BP2) and between the second and third bank patterns (BP2, BP3). The first to third bank patterns (BP1, BP2, BP3) may be arranged in an island pattern.

[0187] The first to third bank patterns (BP1, BP2, BP3) may be arranged on the first organic film (PVX1). Each of the first to third bank patterns (BP1, BP2, BP3) may protrude in the third direction (DR3) on the first organic film (PVX1). Each of the first to third bank patterns (BP1, BP2, BP3) may have an inclined side surface.

[0188] The first to third alignment electrodes (RME1, RME2, RME3) can be arranged on the first organic film (PVX1) and the first to third bank patterns (BP1, BP2, BP3).

[0189] A first portion of the first alignment electrode (RME1) may be disposed between the second alignment electrode (RME2) and the third alignment electrode (RME3). The first portion of the first alignment electrode (RME1) may cover the upper surface and the inclined side surface of the first bank pattern (BP1). The first portion of the first alignment electrode (RME1) may reflect light emitted from the plurality of light-emitting diode elements (LEL_2) in a third direction (DR3).

[0190] A second portion of the first alignment electrode (RME1) may be disposed on one side of the second alignment electrode (RME2). The second portion of the first alignment electrode (RME1) is connected to the first connection electrode (CE1) through the third contact hole (CT3), thereby being electrically connected to a thin film transistor (TFT).

[0191] Although the first and second portions of the first alignment electrode (RME1) are depicted as being spaced apart in the drawing, in some embodiments, the first and second portions of the first alignment electrode (RME1) may be a single electrode that is electrically connected to each other.

[0192] The second alignment electrode (RME2) may be arranged on one side of the first alignment electrode (RME1). The second alignment electrode (RME2) may cover the upper surface and the inclined side surface of the second bank pattern (BP2). The second alignment electrode (RME2) may reflect light emitted from a plurality of light-emitting diode elements (LEL_2) arranged between the first and second bank patterns (BP1, BP2) in a third direction (DR3).

[0193] The third alignment electrode (RME3) may be arranged on the other side of the first alignment electrode (RME1). The third alignment electrode (RME3) may cover the upper surface and the inclined side surface of the third bank pattern (BP3). The third alignment electrode (RME3) may reflect light emitted from a plurality of light-emitting diode elements (LEL_2) arranged between the second and third bank patterns (BP2, BP3) in the third direction (DR3).

[0194] The third alignment electrode (RME3) can be connected to the third connection electrode (CE3) through the fourth contact hole (CT4). Since the third connection electrode (CE3) is electrically connected to the first power line, the first power voltage of the first power line can be applied to the third connection electrode (CE3).

[0195] The first to third alignment electrodes (RME1, RME2, RME3) are electrically connected to the light emitting diode elements (LEL_2) and can reflect light emitted from the plurality of light emitting diode elements (LEL_2) toward the upper side of the substrate (SUB). To this end, the first to third alignment electrodes (RME1, RME2, RME3) may include a conductive material having a high reflectivity. For example, the first to third alignment electrodes (RME1, RME2, RME3) may include a metal such as silver (Ag), copper (Cu), aluminum (Al), or an alloy including aluminum (Al), nickel (Ni), lanthanum (La), or a structure in which a metal layer such as titanium (Ti), molybdenum (Mo), and niobium (Nb) and the alloy are laminated. In some embodiments, the first to third alignment electrodes (RME1, RME2, RME3) may be formed as a double layer or multilayer in which an alloy including aluminum (Al) and at least one metal layer including titanium (Ti), molybdenum (Mo), and niobium (Nb) are laminated.

[0196] Alternatively, the first to third alignment electrodes (RME1, RME2, RME3) may further include a transparent conductive material. For example, the first to third alignment electrodes (RME1, RME2, RME3) may include a material such as ITO, IZO, ITZO, etc. In some embodiments, each alignment electrode (RME) may have a structure in which a transparent conductive material and a high-reflectivity metal layer are each laminated one or more layers, or may be formed as a single layer including the transparent conductive material and the high-reflectivity metal layer. For example, the first to third alignment electrodes (RME1, RME2, RME3) may have a laminated structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0197] Each of the plurality of light-emitting layers (LE_2) may include a contact electrode (CTE), a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2), as shown in FIG. 5c. Since the description of the contact electrode (CTE), the first semiconductor layer (SEM1), the electron blocking layer (EBL), the active layer (MQW), the superlattice layer (SLT), and the second semiconductor layer (SEM2) of each of the plurality of light-emitting layers (LE_2) is substantially the same as that of FIG. 5c, the description thereof is omitted.

[0198] Each of the plurality of light-emitting layers (LE_2) may be aligned between the first alignment electrode (RME1) and the second alignment electrode (RME2) or between the second alignment electrode (RME2) and the third alignment electrode (RME3). The first insulating film (PAS1) may cover the first to third alignment electrodes (RME1, RME2, RME3). Each of the plurality of light-emitting layers (LE_2) may be insulated from the first to third alignment electrodes (RME1, RME2, RME3) by the first insulating film (PAS1). Each of the first to third alignment electrodes (RME1, RME2, RME3) may receive an alignment signal, thereby forming an electric field between the first to third alignment electrodes (RME1, RME2, RME3). For example, each of the plurality of light-emitting layers (LE_2) can be sprayed onto the first to third alignment electrodes (RME1, RME2, RME3) through an inkjet printing process, and each of the plurality of light-emitting layers (LE_2) dispersed in the ink can be aligned by receiving a dielectrophoresis force by an electric field formed between the first to third alignment electrodes (RME1, RME2, RME3). Accordingly, each of the plurality of light-emitting layers (LE_2) can be aligned in the horizontal direction between the first alignment electrode (RME1) and the second alignment electrode (RME2) and between the second alignment electrode (RME2) and the third alignment electrode (RME3).

[0199] A first insulating film (PAS1) may be disposed on the first organic film (PVX1) and the first to third alignment electrodes (RME1, RME2, RME3). The first insulating film (PAS1) may include an insulating material to protect the first to third alignment electrodes (RME1, RME2, RME3). Since the first insulating film (PAS1) is disposed to cover the first to third alignment electrodes (RME1, RME2, RME3) before the bank layer (BNL) is formed, the first to third alignment electrodes (RME1, RME2, RME3) may be prevented from being damaged during the process of forming the bank layer (BNL). In addition, the first insulating film (PAS1) may also prevent each of the plurality of light-emitting layers (LE_2) from being damaged by direct contact with other members.

[0200] The first to third contact electrodes (CNE1, CNE2, CNE3) may be disposed on the first to third alignment electrodes (RME1, RME2, RME3). The second insulating film (PAS2) may be disposed on the central portion of the bank layer (BNL), the first insulating film (PAS1), and each of the plurality of light-emitting layers (LE_2). The third insulating film (PAS3) may cover the second insulating film (PAS2) and the first to third contact electrodes (CNE1, CNE2, CNE3). The second and third insulating films (PAS2, PAS3) may insulate the first to third contact electrodes (CNE1, CNE2, CNE3), respectively.

[0201] The first contact electrode (CNE1) may be disposed on the first alignment electrode (RME1). Although not shown in the drawing, the first contact electrode (CNE1) may be connected to the first alignment electrode (RME1) through a first contact hole penetrating the first insulating film (PAS1). The first contact electrode (CNE1) may connect one end of the light emitting diode elements (LEL_2) disposed between the first bank pattern (BP1) and the second bank pattern (BP2) and the second alignment electrode (RME2).

[0202] The second contact electrode (CNE2) may be disposed on the first and second alignment electrodes (RME1, RME2) and may be insulated from the first and second alignment electrodes (RME1, RME2). A first portion of the second contact electrode (CNE2) may be disposed on the second alignment electrode (RME2). A second portion of the second contact electrode (CNE2) may be disposed on the first alignment electrode (RME1). The second contact electrode (CNE2) may connect other ends of the light emitting diode elements (LEL_2) disposed between the first bank pattern (BP1) and the second bank pattern (BP2) and one end of the light emitting diode elements (LEL_2) disposed between the first bank pattern (BP1) and the third bank pattern (BP3).

[0203] The third contact electrode (CNE3) may be disposed on the third alignment electrode (RME3). Although not shown in the drawing, the third contact electrode (CNE3) may be connected to the third alignment electrode (RME3) through a second contact hole penetrating the first insulating film (PAS1). The third contact electrode (CNE3) may connect the other end of the light emitting diode elements (LEL_2) disposed between the first bank pattern (BP1) and the third bank pattern (BP3) to the third alignment electrode (RME3).

[0204] As discussed in FIGS. 5A to 5D , the light source panel (100) according to one embodiment may be an organic light emitting display panel, a micro light emitting diode display panel, or a nano light emitting diode display panel. However, if the light source panel (100) is a display panel including an incoherent light source, it is not limited to the types of display panels described above. Hereinafter, for the convenience of explanation, the organic light emitting display panel of FIG. 5A will be described as an example, but the present invention is not limited thereto, and the same technical idea may be equally applied to other types of display panels within the scope to which it is applied.

[0205] The light source panel (100) including the aforementioned types of display panels can easily control the intensity of light emitted from each light source pixel (SP) by controlling the intensity of an electric signal applied to each light source pixel (SP). Accordingly, the holographic display (10) according to the present embodiment can easily control the amplitude of light used as a light source.

[0206] Meanwhile, the display panels of the types described above are incoherent light sources, and the light emitted from the display panels of the types described above may be incoherent light. Unlike the holographic displays (10) according to the conventional embodiments that use coherent light to facilitate phase synchronization, the holographic display (10) according to the present embodiment can use an incoherent light source since the phase of light can be adjusted through the spatial light modulator (300) and the holography generating unit (700).

[0207] For example, as described above with reference to FIG. 3, the lights emitted from each light source pixel (SP) may emit light with different random phases (pseudo random phases). These lights with random phases may be sensed by each light sensing pixel (OP). The holography generation unit (700) may individually adjust the phases of the lights emitted from each light source pixel (SP) through the spatial light modulator (300) based on the phases of the sensed lights. Accordingly, the phases of the lights emitted from each light source pixel (SP) may be synchronized with each other. Alternatively, the holography generation unit (700) may form a hologram pattern by considering the phase difference of each light without phase synchronization, and based on this, the spatial light modulator (300) may individually adjust the phases of each light to generate a holographic image (HI).

[0208] The holographic display (10) according to the present embodiment can control the amplitude of light using an incoherent light source and can control the phase of light using a spatial light modulator (300) and a holography generating unit (700). That is, the holographic display (10) according to the present embodiment can be a holographic display (10) capable of complex modulation of amplitude and phase.

[0209] FIG. 6 is a plan view showing a spatial light modulator according to one embodiment.

[0210] In addition to FIGS. 3 and 4, referring to FIG. 6, the spatial light modulator (300) may include a display area (DA) and a non-display area (NDA). The display area (DA) and the non-display area (NDA) of the spatial light modulator (300) are substantially the same as the display area (DA) and the non-display area (NDA) of the light source panel (100) described with reference to FIG. 4, respectively, and therefore, a description of the display area (DA) and the non-display area (NDA) of the spatial light modulator (300) will be omitted.

[0211] The display area (DA) of the spatial light modulator (300) may include a plurality of light modulation pixels (MP), a plurality of light modulation power lines (VL_LM) connected to the plurality of light modulation pixels (MP), a plurality of row-axis light modulation data lines (RL), and a plurality of column-axis light modulation data lines (CL).

[0212] A plurality of light modulation pixels (MP) may be arranged in a first direction (DR1) and a second direction (DR2). For example, a plurality of light source pixels (SP) may be arranged in a matrix direction. Each of the plurality of light modulation pixels (MP) may be connected to a plurality of light modulation power lines (VL_LM), a plurality of row-axis light modulation data lines (RL), and a plurality of column-axis light modulation data lines (CL). Each of the plurality of light modulation pixels (MP) may include at least one transistor, a light modulation element, and a capacitor. In some embodiments, the capacitor may be omitted.

[0213] The row-axis optical modulation data lines (RL) can extend in a first direction (DR1) and can be spaced apart from each other in a second direction (DR2) intersecting the first direction (DR1). The row-axis optical modulation data lines (RL) can sequentially supply row-axis optical modulation data signals to a plurality of optical modulation pixels (MP).

[0214] The thermal axis optical modulation data lines (CL) can extend in a second direction (DR2) and be spaced apart from each other in a first direction (DR1). The thermal axis optical modulation data lines (CL) can supply thermal axis optical modulation data signals to a plurality of optical modulation pixels (MP).

[0215] The optical modulation power line (VL_LM) can extend in the second direction (DR2) and be spaced apart from each other in the first direction (DR1). The optical modulation power line (VL_LM) can supply a power voltage to a plurality of optical modulation pixels (MP). The power voltage can be at least one of a driving voltage, a high-potential voltage, an initialization voltage, a reference voltage, a bias voltage, and a low-potential voltage.

[0216] The optical modulation timing control unit (310) can receive optical modulation digital data (DATA_LM) and timing signals from the holography generation unit (700). The optical modulation timing control unit (310) can generate a column-axis optical modulation data control signal (CCS) and a row-axis optical modulation data control signal (RCS) based on the timing signals. The optical modulation timing control unit (310) can control the operation timing of the column-axis optical modulation driving unit (320) by supplying the optical modulation digital data (DATA_LM) and the column-axis optical modulation data control signal (CCS) to the column-axis optical modulation driving unit (320). The optical modulation timing control unit (310) can control the operation timing of the row-axis optical modulation driving unit (330) by supplying the optical modulation digital data (DATA_LM) and the row-axis optical modulation data control signal (RCS) to the row-axis optical modulation driving unit (330).

[0217] The column-axis optical modulation driving unit (320) and the row-axis optical modulation driving unit (330) can convert the column-axis optical modulation data control signal (CCS) and the row-axis optical modulation data control signal (RCS) into analog optical modulation data voltages and supply them to the column-axis optical modulation data line (CL) and the row-axis optical modulation data line (RL), respectively.

[0218] The row-axis optical modulation driving unit (330) may be positioned on the left or right side of the non-display area (NDA). The column-axis optical modulation driving unit (320) may be positioned on the upper or lower side of the non-display area (NDA).

[0219] The optical modulation power supply unit (340) can supply power voltage to the spatial light modulator (300), the column-axis optical modulation driving unit (320), and the row-axis optical modulation driving unit (330). The optical modulation power supply unit (340) can generate a driving voltage of the optical modulation element and supply it to a driving voltage line, generate an initialization voltage and supply it to an initialization voltage line, generate a bias voltage and supply it to a bias voltage line, and generate a low-potential voltage and supply it to a low-potential line.

[0220] An optical modulation timing control unit (310), a thermal axis optical modulation driving unit (320), a row axis optical modulation driving unit (330), and an optical modulation power supply unit (340) may be included in the optical modulation driving device.

[0221] A plurality of light modulation pixels (MP) of a spatial light modulator (300) according to the present embodiment can be arranged in a one-to-one correspondence to a plurality of light source pixels (SP) of a light source panel (100). Accordingly, the plurality of light modulation pixels (MP) can individually control the phases of the lights emitted from the plurality of light source pixels (SP).

[0222] The holographic display (10) according to the present embodiment comprises a light modulation driving device including a light modulation timing control unit (310), a column-axis light modulation driving unit (320), a row-axis light modulation driving unit (330), and a light modulation power supply unit (340), separately from a light source driving device including a light source timing control unit (110), a light source display driving unit (120), a light source gate driving unit (130), a light emission control driving unit (140), and a light source power supply unit (150), thereby enabling the light source panel (100) and the spatial light modulator (300) to be driven independently, thereby enabling a fast response speed to be implemented.

[0223] Meanwhile, since the light source timing control unit (110) of the light source panel (100) and the light modulation timing control unit (310) of the spatial light modulator (300) are provided with light source digital data (DATA_LS) and light modulation digital data (DATA_LM) calculated and generated by the holography generation unit (700), respectively, the light source timing control unit (110) and the light modulation timing control unit (310) can be linked and driven by the holography generation unit (700). Accordingly, the timing of the light source panel (100) and the spatial light modulator (300) can be easily synchronized.

[0224] FIG. 7 is a plan view showing a display area of ​​a holographic display according to one embodiment.

[0225] Referring to FIG. 7, the display area (DA) of the light source panel (100) may include light source pixels (SP) and light sensing pixels (OP). In some embodiments, the light source pixels (SP) may include a first light source pixel (SP1), a second light source pixel (SP2), and a third light source pixel (SP3), and the light sensing pixels (OP) may include a first light sensing pixel (OP1), a second light sensing pixel (OP2), and a third light sensing pixel (OP3).

[0226] The first to third light source pixels (SP1, SP2, SP3) may be arranged to be spaced apart from each other in a first direction (DR1). The first to third light sensing pixels (OP1, OP2, OP3) may be arranged to be spaced apart from each other in the first direction (DR1). The first to third light source pixels (SP1, SP2, SP3) and the first to third light sensing pixels (OP1, OP2, OP3) may be arranged to be alternately arranged in the first direction (DR1). For example, the first light source pixel (SP1), the first light sensing pixel (OP1), the second light source pixel (SP2), the second light sensing pixel (OP2), the third light source pixel (SP3), and the third light sensing pixel (OP3) may be arranged in this order. However, this is not limited thereto, and the arrangement of the first to third light source pixels (SP1, SP2, SP3) and the first to third light sensing pixels (OP1, OP2, OP3) can be varied.

[0227] In the drawing, the first to third light source pixels (SP1, SP2, SP3) and the first to third light sensing pixels (OP1, OP2, OP3) are depicted as rectangular, but are not limited thereto. The shapes of the first to third light source pixels (SP1, SP2, SP3) and the first to third light sensing pixels (OP1, OP2, OP3) can be modified in various ways.

[0228] In one embodiment, the first light source pixel (SP1) can emit light of a first color, the second light source pixel (SP2) can emit light of a second color, and the third light source pixel (SP3) can emit light of a third color. The light of the first color may be light in a red wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a blue wavelength band. The red wavelength band may be a wavelength band of about 600 nm to 750 nm, the green wavelength band may be a wavelength band of about 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of about 370 nm to 460 nm, but is not limited thereto. In another embodiment, the first to third light source pixels (SP1, SP2, SP3) may emit light of the same color. In this case, the color may be implemented for each pixel through a separate color conversion filter.

[0229] A plurality of light-sensing pixels (OP) correspond one-to-one to a plurality of light source pixels (SP) and can sense light emitted from each of the plurality of light source pixels (SP) on a one-to-one basis. For example, the first to third light-sensing pixels (OP1, OP2, OP3) can sense light emitted from the first to third light source pixels (SP1, SP2, SP3), respectively. The first light-sensing pixel (OP1) can sense light emitted from the first light source pixel (SP1), the second light-sensing pixel (OP2) can sense light emitted from the second light source pixel (SP2), and the third light-sensing pixel (OP3) can sense light emitted from the third light source pixel (SP3).

[0230] In some embodiments, the light source panel (100) may further include a separator (SEP). The separator (SEP) may include a first separator (SEP1), a second separator (SEP2), and a third separator (SEP3).

[0231] The separation unit (SEP) can surround at least a portion of the light source pixels (SP) and light sensing pixels (OP) that correspond to each other on a one-to-one basis. For example, the first separation unit (SEP1) can surround the first light source pixel (SP1) and the first light sensing pixel (OP1), the second separation unit (SEP2) can surround the second light source pixel (SP2) and the second light sensing pixel (OP2), and the third separation unit (SEP3) can surround the third light source pixel (SP3) and the third light sensing pixel (OP3).

[0232] In the drawing, the separation portion (SEP) is depicted as completely surrounding the light source pixel (SP) and the light sensing pixel (OP) on a plane (e.g., a closed shape), but is not limited thereto. The separation portion (SEP) may have a shape in which at least a portion is open on a plane. For example, the separation portion (SEP) may include an open portion in which a portion of an edge is open.

[0233] The holographic display (10) according to the present embodiment includes a separation portion (SEP), thereby preventing light emitted from a light source pixel (SP) from being incident on an adjacent light sensing pixel (OP) that does not correspond to each other. Accordingly, sensing accuracy can be improved.

[0234] The detailed structure of the separation unit (SEP) will be described later with reference to Fig. 12.

[0235] FIG. 8 is a cross-sectional view showing a light-emitting area of ​​a holographic display according to one embodiment.

[0236] Referring to FIG. 8, the light source panel (100) may include a base member (BS), a display layer (DISL), and an encapsulation layer (ENC). The base member (BS) may include a substrate (SUB) and a first buffer film (BF1). The display layer (DISL) may include a thin film transistor layer (TFTL) and a light emitting element layer (EML). The thin film transistor layer (TFTL) may include a first active layer (ACTL1), a first gate insulating film (GI1), a first gate layer (GTL1), a second gate insulating film (GI2), a second gate layer (GTL2), a first interlayer insulating film (ILD1), a second active layer (ACT2), a third gate insulating film (GI3), a third gate layer (GTL3), a second interlayer insulating film (ILD2), a first source metal layer (SDL1), a first organic film (PVX1), a second source metal layer (SDL2), and a second organic film (PVX2). The light emitting device layer (EML) may include a bank (PDL) and a light emitting device (ED).

[0237] The description of the substrate (SUB), the first buffer film (BF1), the first interlayer insulating film (ILD1), the second interlayer insulating film (ILD2), the first organic film (PVX1), the second organic film (PVX2), the bank (PDL), and the encapsulation layer (ENC) illustrated in FIG. 8 is substantially the same as that described above with reference to FIG. 5a, and therefore, the description thereof will be omitted.

[0238] A first active layer (ACTL1) may be disposed on a first buffer film (BF1). The first active layer (ACTL1) may include a silicon-based material. For example, the first active layer (ACTL1) may be formed of low-temperature polycrystalline silicon (LTPS). The first active layer (ACTL1) may include a semiconductor region (ACT1), a first electrode (SE1), and a second electrode (DE1) of a first transistor (ST1), and a semiconductor region (ACT2), a first electrode (SE2), and a second electrode (DE2) of a second transistor (ST2).

[0239] A first gate insulating film (GI1) may be disposed on a first active layer (ACTL1). The first gate insulating film (GI1) may insulate the first active layer (ACTL1) and the first gate layer (GTL1). The first gate insulating film (GI1) may include any of the same materials as the gate insulating film (GI) described above with reference to FIG. 5A.

[0240] A first gate layer (GTL1) may be disposed on a first gate insulating film (GI1). The first gate layer (GTL1) may include a gate electrode (GE1) of a first transistor (ST1), a gate electrode (GE2) of a second transistor (ST2), and a first capacitor electrode (CPE1). The gate electrode (GE1) of the first transistor (ST1) may be a portion of the first capacitor electrode (CPE1), and the gate electrode (GE2) of the second transistor (ST2) may be a portion of a gate line (GL) (see FIG. 4).

[0241] A second gate insulating film (GI2) may be disposed on the first gate layer (GTL1). The second gate insulating film (GI2) may insulate the first gate layer (GTL1) and the second gate layer (GTL2). The second gate insulating film (GI2) may include any of the same materials as the gate insulating film (GI) described above with reference to FIG. 5A.

[0242] The second gate layer (GTL2) may be disposed on the second gate insulating film (GI2). The second gate layer (GTL2) may include a second capacitor electrode (CPE2). The second capacitor electrode (CPE2) may overlap the first capacitor electrode (CPE1).

[0243] The second active layer (ACTL2) may be disposed on the first interlayer insulating film (ILD1). The second active layer (ACTL2) may include an oxide-based material. For example, the second active layer (ACTL2) may include low-temperature polycrystalline oxide (LTPO). The second active layer (ACTL2) may include a semiconductor region (ACT3), a first electrode (DE3), and a second electrode (SE3) of the third transistor (ST3).

[0244] A third gate insulating film (GI3) may be disposed on the second active layer (ACTL2). The third gate insulating film (GI3) may insulate the second active layer (ACTL2) and the third gate layer (GTL3). The third gate insulating film (GI3) may include any of the same materials as the gate insulating film (GI) described above with reference to FIG. 5A.

[0245] The third gate layer (GTL3) may be disposed on the third gate insulating film (GI3). The third gate layer (GTL3) may include a gate electrode (GE3) of a third transistor (ST3). The gate electrode (GE3) of the third transistor (ST3) may be a portion of a gate line (GL) (see FIG. 4).

[0246] A first source metal layer (SDL1) may be disposed on a second interlayer insulating film (ILD2). The first source metal layer (SDL1) may include first to third connection electrodes (CE1, CE2, CE3). The first connection electrode (CE1) may electrically connect a data line (DL) and a first electrode (SE2) of a second transistor (ST2). The second connection electrode (CE2) may electrically connect a first capacitor electrode (CPE1) and a second electrode (SE3) of a third transistor (ST3). Although not shown in the drawing, the third connection electrode (CE3) may electrically connect a first electrode (DE3) of a third transistor (ST3) and a second electrode (DE1) of the first transistor (ST1).

[0247] A second source metal layer (SDL2) may be disposed on the first organic film (PVX1). The second source metal layer (SDL2) may include a data line (DL). The data line (DL) may be substantially the same as the data line (DL) described with reference to FIG. 4.

[0248] The light emitting element (ED) may include a pixel electrode (AE), a hole transport layer (HTL), an emitting layer (EL), an electron transport layer (ETL), and a common electrode (CAT).

[0249] The light emitting element (ED) illustrated in Fig. 8 is substantially the same as the light emitting element (LEL) illustrated in Fig. 5a, so the differences will be mainly explained.

[0250] The pixel electrode (AE) may be disposed on the second organic film (PVX2). The pixel electrode (AE) may overlap one of a plurality of light-emitting areas (EA) defined by the bank (PDL). The pixel electrode (AE) may receive a driving current from a pixel circuit of a light source pixel (SP). The plurality of light-emitting areas (EA) may be included in the light source pixel (SP). The pixel electrode (AE) illustrated in FIG. 8 may be substantially the same as the pixel electrode (AE) illustrated in FIG. 5A.

[0251] A hole transport layer (HTL) may be disposed on a pixel electrode (AE) in an emission area (EA) and may be disposed on a bank (PDL) in an area other than the emission area (EA). The hole transport layer (HTL) may not be divided into light source pixels (SP) and light sensing pixels (OP) (see FIG. 9), but may be implemented as a common layer for all light source pixels (SP) and all light sensing pixels (OP) (see FIG. 9).

[0252] The light-emitting layer (EL) may be disposed on the hole transport layer (HTL) in the light-emitting area (EA). For example, the light-emitting layer (EL) may be an organic light-emitting layer made of an organic material, but is not limited thereto. The light-emitting layer (EL) illustrated in FIG. 8 may be substantially the same as the light-emitting layer (LE) illustrated in FIG. 5A.

[0253] The electron transport layer (ETL) may be disposed on the emitting layer (EL) in the emitting area (EA) and on the hole transport layer (HTL) in an area other than the emitting area (EA). The electron transport layer (ETL) may not be separated by light source pixel (SP) and light sensing pixel (OP) (see Fig. 9), but may be implemented as a common layer for all light source pixels (SP) and light sensing pixels (OP) (see Fig. 9).

[0254] The common electrode (CAT) may be disposed on the electron transport layer (ETL). For example, the common electrode (CAT) may be implemented in the form of an electrode common to all light source pixels (SPs) and light sensing pixels (OPs) without being differentiated for each light source pixel (SP). The common electrode (CAT) may be a transparent electrode and may transmit light. The common electrode (CAT) may be electrically connected to a low-potential line and may receive a low-potential voltage, a common voltage, or a cathode voltage. The common electrode (CAT) illustrated in FIG. 8 may be substantially the same as the common electrode (CE) illustrated in FIG. 5A.

[0255] FIG. 9 is a cross-sectional view showing a sensor area of ​​a holographic display according to one embodiment.

[0256] Referring to FIG. 9, the light source panel (100) may include a base member (BS), a display layer (DISL), and an encapsulation layer (ENC). The base member (BS) may include a substrate (SUB) and a first buffer film (BF1). The display layer (DISL) may include a thin film transistor layer (TFTL) and a light emitting element layer (EML). The thin film transistor layer (TFTL) may include a first active layer (ACTL1), a first gate insulating film (GI1), a first gate layer (GTL1), a second gate insulating film (GI2), a first interlayer insulating layer (ILD1), a second active layer (ACT2), a third gate insulating film (GI3), a third gate layer (GTL3), a second interlayer insulating film (ILD2), a first source metal layer (SDL1), a first organic film (PVX1), a second source metal layer (SDL2), and a second organic film (PVX2). The light emitting device layer (EML) may include a bank (PDL) and a photodetector (PD).

[0257] The description of the substrate (SUB), the first buffer film (BF1), the first gate insulating film (GI1), the second gate insulating film (GI2), the first interlayer insulating film (ILD1), the third gate insulating film (GI3), the second interlayer insulating film (ILD2), the first organic film (PVX1), the second organic film (PVX2), the bank (PDL), and the encapsulation layer (ENC) illustrated in FIG. 9 is substantially the same as that described above with reference to FIG. 8, and therefore, the description thereof will be omitted.

[0258] A first active layer (ACTL1) may be disposed on a first buffer film (BF1). The first active layer (ACTL1) may include a silicon-based material. For example, the first active layer (ACTL1) may be formed of low-temperature polycrystalline silicon (LTPS). The first active layer (ACTL1) may include a semiconductor region (PACT1), a first electrode (PSE1), and a second electrode (PDE1) of a first sensor transistor (PT1).

[0259] A first gate layer (GTL1) may be disposed on a first gate insulating film (GI1). The first gate layer (GTL1) may include a gate electrode (PGE1) of a first sensor transistor (PT1).

[0260] The second active layer (ACTL2) may be disposed on the first interlayer insulating layer (ILD1). The second active layer (ACTL2) may include an oxide-based material. For example, the second active layer (ACTL2) may include low-temperature polycrystalline oxide (LTPO). The second active layer (ACTL2) may include a semiconductor region (PACT2), a first electrode (PDE2), and a second electrode (PSE2) of the second sensor transistor (PT2).

[0261] The third gate layer (GTL3) may be disposed on the third gate insulating film (GI3). The third gate layer (GTL3) may include a gate electrode (PGE2) of the second sensor transistor (PT2).

[0262] A first source metal layer (SDL1) may be disposed on a second interlayer insulating film (ILD2). The first source metal layer (SDL1) may include a sensor connection electrode (PCE) and a first sensor node electrode (NSE1). The sensor connection electrode (PCE) may electrically connect a reset voltage line (VRL) and a second electrode (PSE2) of a second sensor transistor (PT2). The first sensor node electrode (NSE1) may electrically connect a first electrode (PDE2) of the second sensor transistor (PT2) and a gate electrode (PGE1) of the first sensor transistor (PT1).

[0263] A second source metal layer (SDL2) may be disposed on the first organic film (PVX1). The second source metal layer (SDL2) may include a reset voltage line (VRL) and a second sensor node electrode (NSE2). The second sensor node electrode (NSE2) may electrically connect the sensor electrode (PE) and the first sensor node electrode (NSE1).

[0264] A photodetector (PD) can sense light emitted from an ED. Examples of the PD may include inorganic photodetectors such as a photodiode, a quantum dot photodiode, and a superconducting photodetector, and organic photodetectors such as an organic photodetector and an organic photovoltaic cell. The PD may include a sensor electrode (PE), a hole transport layer (HTL), a light-receiving layer (RCL), an electron transport layer (ETL), a common electrode (CAT), and an optical sorting layer (OCL).

[0265] The sensor electrode (PE) is disposed on the second organic film (PVX2) and may be disposed on the same layer as the pixel electrode (AE) of the light-emitting element (ED). The sensor electrode (PE) may overlap one of a plurality of sensor areas (PDAs) defined by the bank (PDL). The plurality of sensor areas (PDAs) may be included in a light-sensing pixel (OP).

[0266] The hole transport layer (HTL) is disposed on the sensor electrode (PE) in the sensor area (PDA) and may be disposed on the bank (PDL) in an area other than the light emitting area (EA). As described above, the hole transport layer (HTL) is not divided into light source pixels (SP) (see FIG. 8) and light sensing pixels (OP), but may be implemented as a common layer for all light source pixels (SP) (see FIG. 8) and all light sensing pixels (OP).

[0267] The photodetector layer (RCL) can be disposed on the hole transport layer (HTL) in the sensor area (PDA). The photodetector layer (RCL) can sense light emitted from the emission area (EA). The photodetector element (PD) can convert the energy of light into an electrical signal (current or voltage) formed between the sensor electrode (PE) and the common electrode (CAT). For example, when the photodetector element (PD) receives light and an electric field is formed between the sensor electrode (PE) and the common electrode (CAT) of the photodetector element (PD), a current proportional to the amount of light can flow in the photodetector element (PD).

[0268] The light-receiving layer (RCL) may include a light-sensing material that includes an inorganic or organic material. For example, examples of the light-sensing material that includes an inorganic material may include polycrystalline silicon, amorphous silicon, microcrystalline silicon, crystalline selenium, amorphous selenium, CIGS (CuInGaSe), CIS (CuInSe2), CuInS2, CuAlS2, CuAlSe2, CuGaS2, CuGaSe2, AgAlS2, AgAlSe2, AgInS2, AgInSe2, GaAs, InP, AlGaAs, InGaP, AlGaInP, InGaAsP, CdSe, CdS, In2Se3, In2S3, Bi2Se3, Bi2S3, ZnSe, ZnS, PbSe, PbS, and quantum dot semiconductors.

[0269] As another example, an example of a light sensing material comprising an organic material may include at least one of the materials according to the following chemical formulae 1 to 5.

[0270]

[0271] The electron transport layer (ETL) may be disposed on the photodetector layer (RCL) in the sensor area (PDA) and on the hole transport layer (HTL) in an area other than the emission area (EA). As described above, the electron transport layer (ETL) may not be divided into light source pixels (SP) (see FIG. 8) and light sensing pixels (OP), but may be implemented as a common layer for all light source pixels (SP) (see FIG. 8) and all light sensing pixels (OP).

[0272] The common electrode (CAT) may be disposed on the electron transport layer (ETL). For example, the common electrode (CAT) may be implemented as an electrode common to all light source pixels (SPs) and light sensing pixels (OPs) without being differentiated by the plurality of light source pixels (SPs). The common electrode (CAT) may be a transparent electrode and may transmit light. The common electrode (CAT) may be electrically connected to a low-potential line and may receive a low-potential voltage, a common voltage, or a cathode voltage.

[0273] The optical sorting layer (OCL) can be disposed on the light-receiving layer (RCL) in the sensor area (PDA). For example, as illustrated in the drawing, the optical sorting layer (OCL) can be disposed on the common electrode (CAT). However, the present invention is not limited thereto, and the optical sorting layer (OCL) can be disposed between the common electrode (CAT) and the light-receiving layer (RCL). For example, the optical sorting layer (OCL) can be disposed between the light-receiving layer (RCL) and the electron transport layer (ETL) or between the electron transport layer (ETL) and the common electrode (CAT). The optical sorting layer (OCL) can at least partially overlap the sensor area (PDA).

[0274] The optical sorting layer (OCL) can classify light incident on the light receiving layer (RCL) by phase. The optical sorting layer (OCL) may include a plurality of polarizers having different angles of polarization axes to classify the light by phase. For example, the optical sorting layer (OCL) may include a plurality of wire grid polarizers having different angles of polarization axes. Although not shown in the drawing, the optical sorting layer (OCL) may further include a phase retarder, such as a wave plate.

[0275] The optical classification method of the optical classification layer (OCL) will be described later with reference to FIGS. 10 and 11.

[0276] Fig. 10 is a plan view showing a light classification layer according to one embodiment. Fig. 11 is a plan view showing a light receiving layer according to one embodiment.

[0277] In addition to FIGS. 8 and 9, referring to FIGS. 10 and 11, the optical sorting layer (OCL) may include a first region (OCL1), a second region (OCL2), a third region (OCL3), and a fourth region (OCL4). Although the optical sorting layer (OCL) is illustrated as including four regions in the drawing, the number of regions included in the optical sorting layer (OCL) is not limited thereto.

[0278] As shown in the drawing, the first region (OCL1) may be arranged on one side of the first direction (DR1) and one side of the second direction (DR2) on the plane, the second region (OCL2) may be arranged on the other side of the first direction (DR1) and one side of the second direction (DR2) on the plane, the third region (OCL3) may be arranged on the other side of the first direction (DR1) and the other side of the second direction (DR2) on the plane, and the fourth region (OCL4) may be arranged on one side of the first direction (DR1) and the other side of the second direction (DR2) on the plane, but is not limited thereto.

[0279] As another example, the first to fourth regions (OCL1, OCL2, OCL3, OCL4) may be arranged side by side in the first direction (DR1) or the second direction (DR2). As another example, the first to fourth regions (OCL1, OCL2, OCL3, OCL4) may have coincident centers, and the first region (OCL1) may be surrounded by the second region (OCL2), the second region (OCL2) may be surrounded by the third region (OCL3), and the third region (OCL3) may be surrounded by the fourth region (OCL4).

[0280] The shape and arrangement of the first to fourth areas (OCL1, OCL2, OCL3, OCL4) are not limited to those shown in the drawing.

[0281] The first to fourth regions (OCL1, OCL2, OCL3, OCL4) may each include polarizing plates having polarization axes of different angles. For example, the polarizing plate included in the first region (OCL1) may include a 135 degree polarization axis, the polarizing plate included in the second region (OCL2) may include a 90 degree polarization axis, the polarizing plate included in the third region (OCL3) may include a 45 degree polarization axis, and the polarizing plate included in the fourth region (OCL4) may include a 0 degree polarization axis.

[0282] However, this is not limited thereto, and the first to fourth regions (OCL1, OCL2, OCL3, OCL4) may include polarizing plates having polarization axes other than 0 degrees, 45 degrees, 90 degrees, and 135 degrees.

[0283] Meanwhile, the light-receiving layer (RCL) may include a first portion (RCL1), a second portion (RCL2), a third portion (RCL3), and a fourth portion (RCL4). In the drawing, the light-receiving layer (RCL) is illustrated as including four portions, but the number of portions included in the light-receiving layer (RCL) is not limited thereto.

[0284] As shown in the drawing, the first part (RCL1) can be arranged on one side in the first direction (DR1) and one side in the second direction (DR2) on the plane, the second part (RCL2) can be arranged on the other side in the first direction (DR1) and one side in the second direction (DR2) on the plane, the third part (RCL3) can be arranged on the other side in the first direction (DR1) and the other side in the second direction (DR2) on the plane, and the fourth part (RCL4) can be arranged on one side in the first direction (DR1) and the other side in the second direction (DR2) on the plane, but is not limited thereto.

[0285] As another example, the first to fourth parts (RCL1, RCL2, RCL3, RCL4) may be arranged side by side in the first direction (DR1) or the second direction (DR2). As another example, the first to fourth parts (RCL1, RCL2, RCL3, RCL4) may have coincident centers, and the first part (RCL1) may be surrounded by the second part (RCL2), the second part (RCL2) may be surrounded by the third part (RCL3), and the third part (RCL3) may be surrounded by the fourth part (RCL4).

[0286] The shape and arrangement of the first to fourth parts (RCL1, RCL2, RCL3, RCL4) are not limited to those shown in the drawing.

[0287] The first to fourth parts (RCL1, RCL2, RCL3, RCL4) of the light receiving layer (RCL) overlap with the first to fourth regions (OCL1, OCL2, OCL3, OCL4) of the light sorting layer (OCL) in the third direction (DR3), respectively, and can correspond one-to-one with each other. For example, the first part (RCL1) overlaps with the first region (OCL1) in the third direction (DR3) and can correspond one-to-one with each other, the second part (RCL2) overlaps with the second region (OCL2) in the third direction (DR3) and can correspond one-to-one with each other, the third part (RCL3) overlaps with the third region (OCL3) in the third direction (DR3) and can correspond one-to-one with each other, and the fourth part (RCL4) overlaps with the fourth region (OCL4) in the third direction (DR3) and can correspond one-to-one with each other.

[0288] In some embodiments, the first direction (DR1) width (OCL_W1) and the second direction (DR2) width (OCL_W2) of each of the first to fourth regions (OCL1, OCL2, OCL3, OCL4) may be greater than the first direction (DR1) width (RCL_W1) and the second direction (DR2) width (RCL_W2) of each of the first to fourth portions (RCL1, RCL2, RCL3, RCL4). Accordingly, all light incident on the light-receiving layer (RCL) can pass through the light classification layer (OCL), so that all light incident on the light-receiving layer (RCL) can be classified by phase. Accordingly, the sensing accuracy of the light-receiving element (PD) can be improved.

[0289] The holographic display (10) according to the present embodiment classifies light emitted from a light-emitting element (ED) by phase by including an optical classification layer (OCL), and measures the intensity of light for each phase through a light-receiving layer (RCL), thereby obtaining information on the random phase of light emitted from the light-emitting element (ED).

[0290] For example, light emitted from an emitting element (ED) can pass through an optical sorting layer (OCL) before being incident on a light-receiving element (PD). The light incident on the optical sorting layer (OCL) can be classified by phase by polarizing plates having polarization axes at different angles and can then be incident on a light-receiving layer (RCL). The light-receiving layer (RCL) can provide phase information of each light classified by phase to a holography generating unit (700) (see FIG. 3).

[0291] Fig. 12 is a cross-sectional view showing a light-emitting area and a sensor area according to one embodiment.

[0292] In addition to FIGS. 7 to 9, referring to FIG. 12, the holographic display (10) may include a light source panel (100) and a spatial light modulator (300) disposed on the light source panel (100).

[0293] The spatial light modulator (300) may include a light modulation pixel (MP) that overlaps the light emitting area (EA) of the light source pixel (SP) of the light source panel (100) in a third direction (DR3).

[0294] The light source panel (100) may further include a reflective layer (RFL). The reflective layer (RFL) may be disposed on the light emitting element layer (EML). The reflective layer (RFL) may be disposed between the light emitting element layer (EML) and the spatial light modulator (300). The reflective layer (RFL) may include a reflective portion (RFP), a light shielding layer (BM), and an overcoat layer (OC).

[0295] The reflective portion (RFP) can reflect light emitted from the light-emitting element (ED). The reflective portion (RFP) can reflect the light emitted from the light-emitting element (ED) and allow it to enter the light-receiving element (PD). For example, some of the first light (LGT1) emitted from the light-emitting element (ED) can be reflected by the reflective portion (RFP) and allowed to enter the light-receiving element (PD).

[0296] A light-shielding layer (BM) may be disposed on the reflective portion (RFP). The light-shielding layer (BM) may include a light-shielding material that blocks or absorbs light. The light-shielding layer (BM) may include an aperture (OPN) that overlaps an emission area (EA) or a light-modulating pixel (MP).

[0297] Some of the first light (LGT1) emitted from the light-emitting element (ED) may be blocked or absorbed by the light-shielding layer (BM). Others of the first light (LGT1) emitted from the light-emitting element (ED) may be incident on the light-modulating pixel (MP) through the opening (OPN) of the light-shielding layer (BM).

[0298] An overcoat layer (OC) can be disposed on a light-shielding layer (BM). The overcoat layer (OC) can level the step formed by the reflective portion (RFP) and the light-shielding layer (BM).

[0299] The holographic display (10) according to the present embodiment can sense light emitted from a light-emitting element (ED) in real time through a light-receiving element (PD), and generate a holographic image (HI) by controlling the phase and amplitude of the light in real time through a spatial light modulator (300) based on the phase and amplitude information of the sensed light. Accordingly, the holographic display (10) according to the present embodiment can be a holographic display (10) that can not only use an incoherent light source, but also perform complex modulation of amplitude and phase.

[0300] For example, the first lights (LGT1) emitted from the light-emitting element (ED) may emit light with the same or different random phases (pseudo random phases). Some of these first lights (LGT1) may be reflected through the reflector (RFP), classified by phase by the light classification layer (OCL), and then incident on the light-receiving element (PD). The holography generation unit (700) may generate a hologram pattern based on information about the phase and amplitude of the first lights (LGT1) provided through the light-receiving element (PD), and provide the hologram pattern to the spatial light modulator (300).

[0301] Meanwhile, another portion of the first light (LGT1) may be incident on a plurality of light modulation pixels (MPs). The plurality of light modulation pixels (MPs) provided with the holographic pattern may control the phase or amplitude of the first light (LGT1). The first light (LGT1) may be converted into a second light (LGT2) with the phase or amplitude controlled to generate a holographic image (HI).

[0302] A separator (SEP) can cut a hole transport layer (HTL), an electron transport layer (ETL), and a common electrode (CAT) at both ends of a light source pixel (SP) and a light sensing pixel (OP) that correspond to each other. A height of the separator (SEP) (e.g., a length in a third direction (DR3)) can be greater than a height of a light emitting element (ED) and a height of a light receiving element (PD). The separator (SEP) can prevent light emitted from one light source pixel (SP) from being incident on an adjacent light sensing pixel (OP) that does not correspond to each other. For example, the separator (SEP) may not be arranged between one light source pixel (SP) and a light sensing pixel (OP) located on one side of the one light source pixel (SP), and may be arranged between one light source pixel (SP) and a light sensing pixel (OP) located on the other side of the one light source pixel (SP). Accordingly, the sensing accuracy of the light receiving element (PD) can be improved.

[0303] In some embodiments, the separator (SEP) may have a raised shape protruding on the bank (PDL). As illustrated in the drawing, the raised shape of the separator (SEP) may have a reverse taper angle structure. For example, the upper width of the separator (SEP) may be larger than the lower width of the separator (SEP). However, the shape of the separator (SEP) is not limited thereto, and may not include an inclined surface on the side surface of the separator (SEP) and may have a normal taper angle structure.

[0304] Below, other embodiments of a holographic display according to one embodiment are described. In the following embodiments, the same components as in the previously described embodiments are referred to by the same reference numerals, and redundant descriptions are omitted or simplified, with the differences being primarily described.

[0305] Fig. 13 is a plan view showing a light-receiving layer according to another embodiment. Fig. 14 is a cross-sectional view showing a light-emitting region and a sensor region according to another embodiment.

[0306] Referring to FIGS. 13 and 14, the holographic display (10) according to the present embodiment is different from the holographic display (10) according to the embodiment described with reference to FIG. 11, etc. in that the optical sorting layer (OCL) is omitted and the pattern is formed directly on the light receiving layer (RCL).

[0307] More specifically, the optical classification layer (OCL) may be omitted in the light-receiving element (PD) according to the present embodiment. In this case, the light-receiving layer (RCL) may include a plurality of patterns having different polarization axis angles to classify light by phase. For example, the light-receiving layer (RCL) may include a plurality of wire grid polarization patterns having different polarization axis angles.

[0308] For example, the polarization pattern included in the first portion (RCL1) may include a 135 degree polarization axis, the polarization pattern included in the second portion (RCL2) may include a 90 degree polarization axis, the polarization pattern included in the third portion (RCL3) may include a 45 degree polarization axis, and the polarization pattern included in the fourth portion (RCL4) may include a 0 degree polarization axis.

[0309] However, it is not limited thereto, and the first to fourth sections (RCL1, RCL2, RCL3, RCL4) may include polarization patterns having polarization axes other than 0 degrees, 45 degrees, 90 degrees, and 135 degrees.

[0310] In the case of the photodetector (PD) according to the present embodiment, the process can be simplified by omitting a separate optical classification layer (OCL) and forming a polarization pattern directly on the photodetector layer (RCL).

[0311] Fig. 15 is a plan view illustrating a light source panel according to another embodiment. Fig. 16 is a plan view illustrating a spatial light modulator according to another embodiment. Fig. 17 is a cross-sectional view illustrating a holographic display according to another embodiment. Fig. 18 is a cross-sectional view illustrating a light-emitting region and a sensor region according to another embodiment.

[0312] Referring to FIGS. 15 to 18, the holographic display (10) according to the present embodiment is different from the holographic display (10) according to the embodiment described with reference to FIG. 4, etc., in that the light-receiving element (PD) is provided in a separate layer from the light-emitting element (ED).

[0313] More specifically, the holographic display (10) according to the present embodiment may have a separate light-receiving element layer (ESL) and place a light-receiving element (PD) on the light-receiving element layer (ESL), instead of having a light-sensing pixel (OP) on a layer (e.g., a thin film transistor layer (TFTL) and a light-emitting element layer (EML)) in which a pixel circuit and a light-emitting element (ED) constituting a light source pixel (SP) are placed.

[0314] For example, as illustrated in FIGS. 15 and 16, the light source panel (100) may include a plurality of light source pixels (SP), and the spatial light modulator (300) may include a plurality of light modulation pixels (MP). In this case, the light source panel (100) may not include a separate light sensing pixel (OP).

[0315] As illustrated in FIG. 17, the light source panel (100) may include a light sensing unit (PHS) positioned on the light source pixel (SP). The light sensing unit (PHS) may be included in the light receiving element layer (ESL), as illustrated in FIG. 18.

[0316] The light-receiving element layer (ESL) may be disposed on the light-emitting element layer (EML). For example, the light-receiving element layer (ESL) may be disposed on the encapsulation layer (ENC). The light-receiving element layer (ESL) may include a light-shielding layer (BM), a light-receiving element (PD), and an overcoat layer (OC). The light-sensing unit (PHS) may include the light-receiving element (PD).

[0317] The light-receiving element layer (ESL) may include a first conductive layer on which a common electrode (CAT) of the light-receiving element (PD) is disposed, a first material layer on which an electron transport layer (ETL) of the light-receiving element (PD) is disposed, a second material layer on which a light-receiving layer (RCL) of the light-receiving element (PD) is disposed, a third material layer on which a hole transport layer (HTL) of the light-receiving element (PD) is disposed, and a second conductive layer on which a sensor electrode (PE) of the light-receiving element (PD) is disposed.

[0318] The holographic display (10) according to the present embodiment may not have a separate reflector (RFP) (see FIG. 3) by separately positioning the light-receiving element (PD) at a higher layer than the light-emitting element (ED). Accordingly, since the first light (LGT1) emitted from the light source pixel (SP) is directly incident on the light sensing unit (PHS), the sensing accuracy can be improved.

[0319] In some embodiments, although not shown in the drawings, when the light-receiving element of the light-receiving element layer (ESL) comprises an organic material, a separate encapsulating structure substantially identical to the encapsulating layer (ENC) may be further disposed on the light-receiving element layer (ESL).

[0320] In addition, the light receiving element (PD) according to the present embodiment may further include an optical sorting layer (OCL) (see FIG. 9), similar to the light receiving element (PD) described with reference to FIG. 9, etc.

[0321] The circuit for driving the light-receiving element (PD) provided in the light-receiving element layer (ESL) can utilize the wiring of the thin film transistor layer (TFTL) provided with the circuit for driving the light-emitting element (ED). In this case, separate connection wirings may be further included for connecting the wiring of the thin film transistor layer (TFTL) located relatively lower and the light-receiving element (PD) of the light-receiving element layer (ESL) located relatively upper. These connection wirings may be arranged in the non-display area (NDA) illustrated in FIG. 18.

[0322] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. A light source panel including a plurality of light-emitting elements and a plurality of light-receiving elements that sense light emitted from the plurality of light-emitting elements; A spatial light modulator disposed on the light source panel; and A holographic display including a holographic generation unit configured to provide holographic pattern information to the spatial light modulator based on light information sensed by the light receiving element.

2. In paragraph 1, A holographic display in which the plurality of light-emitting elements and the plurality of light-receiving elements correspond one-to-one to each other.

3. In paragraph 2, A holographic display in which the plurality of light-emitting elements and the plurality of light-receiving elements are arranged alternately.

4. In paragraph 3, A holographic display wherein the plurality of light-receiving elements are positioned higher than the plurality of light-emitting elements.

5. In paragraph 3, A holographic display in which the plurality of light-emitting elements and the plurality of light-receiving elements are arranged on the same layer.

6. In paragraph 5, It includes a reflector disposed between the plurality of light-emitting elements and the plurality of light-receiving elements, A holographic display in which the above reflector reflects light emitted from the plurality of light-emitting elements and causes the light to enter the plurality of light-receiving elements.

7. In paragraph 2, The light source panel further includes a separation portion that surrounds at least a portion of the plurality of light-emitting elements and at least a portion of the plurality of light-receiving elements on a plane, The plurality of light-emitting elements include a first light-emitting element, The plurality of light-receiving elements include a first light-receiving element and a second light-receiving element respectively disposed on both sides of the first light-emitting element, A holographic display in which the separating portion is not disposed between the first light-emitting element and the first light-receiving element, but is disposed between the first light-emitting element and the second light-receiving element.

8. In paragraph 7, A holographic display wherein the height of the above separation portion is greater than the height of the light-emitting element and the height of the light-receiving element.

9. In paragraph 1, A holographic display, wherein the light-receiving element comprises a first electrode, a light-receiving layer disposed on the first electrode, and a second electrode disposed on the light-receiving layer.

10. In paragraph 9, A holographic display wherein the light-receiving element further includes a light sorting layer disposed on the light-receiving layer and including a plurality of polarizing plates having polarization axes at different angles.

11. In paragraph 9, A holographic display wherein the light-receiving layer comprises a plurality of polarization patterns having polarization axes at different angles.

12. In paragraph 1, The above spatial light modulator is a holographic display that is a transmissive spatial light modulator.

13. In paragraph 1, The above light source panel is a self-luminous panel, and is a holographic display including an incoherent light source.

14. In paragraph 13, The lights emitted from the above plurality of light-emitting elements have random phases that are the same or different from each other, A holographic display configured such that the holographic generation unit reflects the difference in the random phase of the light emitted from the plurality of light-emitting elements into the hologram pattern information and provides the information to the spatial light modulator.

15. In paragraph 1, The above light source panel is configured to control the amplitude of lights emitted from the plurality of light emitting elements, A holographic display in which the spatial light modulator is configured to control the phase of the lights emitted from the plurality of light-emitting elements.

16. In paragraph 1, The above light source panel and the above spatial light modulator are planar or plate-shaped holographic displays.

17. In paragraph 1, The above light source panel includes a plurality of light source pixels in which the plurality of light emitting elements are respectively arranged, A holographic display in which the above spatial light modulator includes a plurality of light modulation pixels corresponding one-to-one to the plurality of light source pixels.

18. In paragraph 17, The above light source panel further includes a light source driving device that drives the plurality of light source pixels, The above spatial light modulator further includes an optical modulation driving device that drives the plurality of optical modulation pixels, A holographic display in which the light source driving device and the light modulation driving device are provided separately.

19. 1st challenge layer, A first material layer disposed on the first conductive layer, A second conductive layer disposed on the first material layer, A light-emitting element including a pixel electrode included in the first conductive layer, a light-emitting layer included in the first material layer, and a common electrode included in the second conductive layer, and A light source panel including a sensor electrode included in the first conductive layer, a light receiving layer included in the first material layer, and a light receiving element including the common electrode; A spatial light modulator disposed on the light source panel; and A holographic generating unit configured to provide hologram pattern information to the spatial light modulator based on light information sensed by the light receiving element is included. A holographic display wherein the light source panel further includes a reflector disposed between the light emitting element and the light receiving element.

20. In paragraph 19, A holographic display in which the above reflective portion is disposed on the second conductive layer.

21. 1st challenge layer, A first material layer disposed on the first conductive layer, A second conductive layer disposed on the first material layer, A third conductive layer disposed on the second conductive layer, A second material layer disposed on the third conductive layer, A fourth conductive layer disposed on the second material layer, A light-emitting element including a pixel electrode included in the first conductive layer, a light-emitting layer included in the first material layer, and a common electrode included in the second conductive layer, and A light source panel including a light receiving element including a first electrode included in the third conductive layer, a light receiving layer included in the second material layer, and a second electrode included in the fourth conductive layer; A spatial light modulator disposed on the light source panel; and A holographic generating unit configured to provide hologram pattern information to the spatial light modulator based on light information sensed by the light receiving element is included. A holographic display wherein the light-receiving element is positioned higher than the light-emitting element.

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