Display substrate and manufacturing method therefor, and display device

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a plurality of circuit units, at least one first data connecting line, and at least one second data connecting line; a circuit unit comprises a pixel driving circuit, a data signal line, and at least one constant potential signal line, the data signal line is connected to the first data connecting line, and the first data connecting line is connected to the second data connecting line; a circuit unit further comprises a first discontinuity and a discontinuity shielding structure, the first discontinuity is arranged on the first data connecting line, the discontinuity shielding structure is connected to the constant potential signal line, the first data connecting line is arranged in one conductive layer, and the discontinuity shielding structure is arranged in any conductive layer or multiple conductive layers other than the conductive layer where the first data connecting line is located; the orthographic projection of the first discontinuity on a base at least partially overlaps with the orthographic projection of the discontinuity shielding structure on the base. The present disclosure can increase transmittance, facilitate artifacts elimination, and avoid poor appearance of the display substrate.

Description

Display substrate and manufacturing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 23, 2024, with application number 202410205573.1 and invention name “Display substrate, preparation method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate, wherein in a direction parallel to the display substrate, the display substrate includes a plurality of circuit units, at least one first data connection line extending along a first direction, and at least one second data connection line extending along a second direction, wherein the first direction and the second direction intersect; at least one circuit unit includes a pixel driving circuit, a data signal line, and at least one constant potential signal line, wherein the data signal line is configured to provide a data signal to the pixel driving circuit, the constant potential signal line is configured to provide a constant potential signal to the pixel driving circuit, the data signal line is connected to the first data connection line, and the first data connection line is connected to the second data connection line. The display substrate is connected to the data connection line; at least one circuit unit further includes at least one first break and at least one break shielding structure, the first break is arranged on the first data connection line and cuts off the first data connection line, and the break shielding structure is connected to the constant potential signal line; in a direction perpendicular to the display substrate, the display substrate includes at least a plurality of conductive layers arranged on a base, the first data connection line is arranged in a conductive layer, and the break shielding structure is arranged in any one conductive layer or multiple conductive layers other than the conductive layer where the first data connection line is located; the orthographic projection of the first break on the base at least partially overlaps with the orthographic projection of the break shielding structure on the base.

[0006] In an exemplary embodiment, at least one fracture shielding structure includes a first fracture shielding block, the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the first fracture shielding block on the substrate, and the first fracture shielding block is arranged in the conductive layer on the side of the conductive layer where the first data connection line is located close to the substrate.

[0007] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the first data connection line is arranged in the third conductive layer, and the first fracture shielding block is arranged in the first conductive layer and / or the second conductive layer.

[0008] In an exemplary embodiment, at least one constant potential signal line includes a first initial signal line, and the pixel driving circuit includes at least a first transistor and a second transistor, the gate electrode of the first transistor is connected to the second scanning signal line, the first pole of the first transistor is connected to the first initial signal line, the gate electrode of the second transistor is connected to the third scanning signal line, and the first pole of the second transistor is connected to the second pole of the first transistor; in at least one circuit unit, the first initial signal line is arranged between the second scanning signal line and the third scanning signal line, and the first fracture shielding block is connected to the first initial signal line.

[0009] In an exemplary embodiment, in at least one circuit unit, the first data connection line is disposed between the second scan signal line and the first initial signal line, and the first break shielding block is disposed on a side of the first initial signal line close to the second scan signal line.

[0010] In an exemplary embodiment, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, the second region of the first active layer is connected to the first region of the second active layer, and in at least one circuit unit, the orthographic projection of the first fracture blocking block on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer on the substrate.

[0011] In an exemplary embodiment, at least one constant potential signal line includes a second initial signal line, and the pixel driving circuit includes at least a third transistor and a seventh transistor as driving transistors, the gate electrode of the seventh transistor is connected to the first scanning signal line, and the first electrode of the seventh transistor is connected to the second initial signal line; in at least one circuit unit, the second initial signal line is arranged on a side of the first scanning signal line away from the third transistor, and the first fracture shielding block is connected to the second initial signal line.

[0012] In an exemplary embodiment, in at least one circuit unit, the first data connection line is disposed between the first scan signal line and the second initial signal line, and the first break shielding block is disposed on a side of the second initial signal line close to the first scan signal line.

[0013] In an exemplary embodiment, at least one first break is provided between circuit units adjacent to each other in the first direction, and at least one first break blocking block is provided between circuit units adjacent to each other in the first direction.

[0014] In an exemplary embodiment, at least one circuit unit further includes at least one second break and at least one second break blocking block, wherein the second break is arranged on the second data connection line and cuts off the second data connection line, and the orthographic projection of the second break on the substrate at least partially overlaps with the orthographic projection of the second break blocking block on the substrate.

[0015] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer arranged on a substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the second data connection line is arranged in the fourth conductive layer, and the second fracture shielding block is arranged in any one conductive layer or multiple conductive layers among the first conductive layer, the second conductive layer and the third conductive layer.

[0016] In an exemplary embodiment, at least one constant potential signal line includes a first initial signal line, which is configured to provide a first initial signal to the pixel driving circuit, and in at least one circuit unit, the second break shielding block is connected to the first initial signal line.

[0017] In an exemplary embodiment, at least one constant potential signal line includes a second initial signal line, which is configured to provide a second initial signal to the pixel driving circuit, and in at least one circuit unit, the second break shielding block is connected to the second initial signal line.

[0018] In an exemplary embodiment, at least one second break is provided between circuit units adjacent to each other in the first direction, and at least one second break blocking block is provided between circuit units adjacent to each other in the first direction.

[0019] In an exemplary embodiment, at least one fracture shielding structure includes a third fracture shielding block, the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the third fracture shielding block on the substrate, and the third fracture shielding block is arranged in the conductive layer on the side of the conductive layer where the first data connection line is located away from the substrate.

[0020] In an exemplary embodiment, the multiple conductive layers include at least a first conductive layer arranged on a substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the first data connection line is arranged in the third conductive layer, and the third fracture shielding block is arranged in the fourth conductive layer.

[0021] In an exemplary embodiment, at least one constant potential signal line includes a first power line configured to provide a first power signal to the pixel driving circuit; in at least one circuit unit, the third fracture shielding block is connected to the first power line.

[0022] In an exemplary embodiment, at least one constant potential signal line includes a second power line configured to provide a second power signal to the light emitting device; and in at least one circuit unit, the third break blocking block is connected to the second power line.

[0023] In an exemplary embodiment, at least one circuit unit further includes a first power line, which is configured to provide a first power signal to the pixel driving circuit, and the first power line simultaneously serves as the break shielding structure and the constant potential signal line; the orthographic projection of the first break on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and the first power line is arranged in a conductive layer on a side of the conductive layer where the first data connection line is located away from the substrate.

[0024] In an exemplary embodiment, the pixel driving circuit includes at least a first transistor and a second transistor, the gate electrode of the first transistor is connected to the second scanning signal line, the first electrode of the first transistor is connected to the first initial signal line, the gate electrode of the second transistor is connected to the third scanning signal line, and the first electrode of the second transistor is connected to the second electrode of the first transistor; in at least one circuit unit, the first initial signal line is arranged between the second scanning signal line and the third scanning signal line, and the first data connection line is arranged between the first initial signal line and the third scanning signal line.

[0025] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0026] On the other hand, the present disclosure further provides a method for preparing a display substrate, the display substrate comprising a plurality of circuit units, at least one first data connection line extending along a first direction, and at least one second data connection line extending along a second direction, the first direction and the second direction intersecting; at least one circuit unit comprising a pixel driving circuit, a data signal line, and at least one constant potential signal line, the data signal line being configured to provide a data signal to the pixel driving circuit, the constant potential signal line being configured to provide a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data connection line, and the first data connection line being connected to the second data connection line; at least one circuit unit further comprising at least one first break and at least one break shielding structure, the first break being provided on the first data connection line and cutting off the first data connection line, the break shielding structure being connected to the constant potential signal line; the preparation method comprising:

[0027] Multiple conductive layers are formed on the substrate, the first data connection line is arranged in a conductive layer, and the fracture shielding structure is arranged in any one conductive layer or multiple conductive layers other than the conductive layer where the first data connection line is located, and the orthographic projection of the first fracture on the substrate and the orthographic projection of the fracture shielding structure on the substrate at least partially overlap.

[0028] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0030] FIG1 is a schematic structural diagram of a display device;

[0031] FIG2 is a schematic structural diagram of a display substrate;

[0032] FIG3A is a schematic diagram of a planar structure of a display area in a display substrate;

[0033] FIG3B is a schematic diagram of a planar structure of a display area in another display substrate;

[0034] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0035] FIG5 is an equivalent circuit diagram of a pixel driving circuit;

[0036] FIG6 is a schematic structural diagram of a data connection line according to an exemplary embodiment of the present disclosure;

[0037] FIG7 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0038] FIG8 is a schematic diagram of an embodiment of the present disclosure after forming a shielding layer pattern;

[0039] 9A and 9B are schematic diagrams of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0040] 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0041] 11A and 11B are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0042] FIG12 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern;

[0043] 13A and 13B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0044] FIG14 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern;

[0045] 15A and 15B are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0046] 16, 17A and 17B are schematic structural diagrams of another display substrate according to an embodiment of the present disclosure;

[0047] 18 , 19A and 19B are schematic structural diagrams of yet another display substrate according to an embodiment of the present disclosure;

[0048] 20, 21A and 21B are schematic structural diagrams of another display substrate according to an embodiment of the present disclosure;

[0049] 22 and 23 are schematic structural diagrams of another display substrate according to an embodiment of the present disclosure;

[0050] FIG24 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0051] 25 and 26 are schematic structural diagrams of yet another display substrate according to an embodiment of the present disclosure;

[0052] FIG27 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0053] FIG28 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.

[0054] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 18—node active layer; 21—first scan signal line; 22—second scan signal line; 23—third scan signal line; 25—fifth gate electrode; 26—sixth gate electrode; 27—first light-emitting signal line; 28—second light-emitting signal line; 31—first electrode plate; 32—second electrode plate; 33—opening; 34—plate connecting bar; 35—plate connecting electrode; 41—first initial signal line; 42—second initial signal line; 43—first shielding electrode; 44—second shielding electrode; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 57—seventh connecting electrode; 61—first break shielding block; 62—second break shielding block; 63—third break shielding block; 71—first power line; 72—second power line; 73—data signal line; 74—anode connecting electrode; 80—data lead line; 81—first data connection line; 82—second data connection line; 83—data connection block; 90—shielding electrode; 91—first shielding connecting bar; 92—second shielding connecting bar; 93—third shielding connecting bar; 94—fourth shielding connecting bar; 95—first shielding block; 96—second shielding block; 100—display area; 101—substrate; 102—driving structure layer; 103—light-emitting structure layer; 104—encapsulation structure layer; 200—binding area; 201—lead-out area; 202—bending area; 300—border area. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0056] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0057] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0058] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0059] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0060] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0061] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0062] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0063] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0064] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0065] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation. The term "approximately" in this disclosure does not strictly define the boundaries, but allows for values ​​within the range of process and measurement errors.

[0066] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to the data signal lines DATA1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to the data signal lines DATA1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to the scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit the scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The emission driver can generate emission signals to be supplied to the emission signal lines EM1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines EM1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0067] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that form a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic images or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0068] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bending area 202, a driver chip area and a binding pin area arranged in sequence along a direction away from the display area, and the lead area 201 is connected to the display area 100 and includes at least a data lead. The bending area 202 is connected to the lead area 201 and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines. The binding pin area may include a binding pad (Bonding Pad), which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0069] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.

[0070] In an exemplary embodiment, the lead line area in the binding area 200 and the power line area in the border area 300 can be provided with an isolation dam, and the isolation dam can extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100. The edge of the display area is the edge of one side of the display area binding area or the border area.

[0071] FIG3A is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG3A , the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0072] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged in an RGBG pattern.

[0073] Figure 3B is a schematic diagram of the planar structure of the display area in another display substrate. As shown in Figure 3B , the pixel unit P may include three sub-pixels: the first sub-pixel P1 may be a red sub-pixel emitting red light, the second sub-pixel P2 may be a blue sub-pixel emitting blue light, and the third sub-pixel P3 may be a green sub-pixel emitting green light. The three sub-pixels may be arranged in a Real RGB manner.

[0074] In other exemplary embodiments, three sub-pixels or four sub-pixels may be arranged in parallel horizontally or vertically, and the present disclosure does not limit this.

[0075] Figure 4 is a schematic cross-sectional view of the display region within a display substrate, illustrating the structure of four sub-pixels within the display region. As shown in Figure 4, in a plane perpendicular to the display substrate, the display region may include a drive structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive structure layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display region may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0076] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0077] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit is respectively connected to 9 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, first light-emitting signal line EM1, second light-emitting signal line EM2, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power line VDD).

[0078] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively; the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, respectively; the third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively; and the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0079] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0080] In an exemplary embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor is connected to the first node N1 .

[0081] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the third scan signal line S3 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0082] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0083] In an exemplary embodiment, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0084] In an exemplary embodiment, a gate electrode of the fifth transistor T5 is connected to the first light emitting signal line EM1 , a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2 .

[0085] In an exemplary embodiment, a gate electrode of the sixth transistor T6 is connected to the second light emitting signal line EM2 , a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0086] In an exemplary embodiment, a gate electrode of the seventh transistor T7 is connected to the first scan signal line S1 , a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .

[0087] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0088] In an exemplary embodiment, the first power line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second voltage signal to the light-emitting device, wherein the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial voltage signal and the second initial voltage signal may be constant voltage signals, which is not limited in this disclosure.

[0089] In an exemplary embodiment, the first to seventh transistors T1 to T7 in the pixel driving circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to seventh transistors T1 to T7 may include P-type transistors and N-type transistors.

[0090] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0091] With the development of OLED display technology, consumers are increasingly demanding higher quality and display effects from display products. Narrow bezels have become a new trend in display product development. Therefore, narrower or even borderless bezels are gaining increasing attention in OLED display product design. In one display substrate, the data signals from the integrated circuits in the bonding area must be fanned out to the wider display area via data lead wires. This results in a larger bottom bezel width due to the large space occupied by the lead wire area.

[0092] To reduce the width of the lower bezel, exemplary embodiments of the present disclosure provide a display substrate employing a fanout in panel (FIP) structure. Multiple data connection lines are arranged in the display area. One end of each of the multiple data connection lines is connected to a plurality of data signal lines in the display area. The other ends of the multiple data connection lines extend to a binding area and are connected to the integrated circuit via a plurality of lead lines in a lead-out area. Because the lead-out area does not require fan-shaped diagonal lines, the width of the lead-out area is reduced, thereby reducing the width of the lower bezel.

[0093] An exemplary embodiment of the present disclosure provides a display substrate, wherein the display substrate includes, in a direction parallel to the display substrate, a plurality of circuit units, at least one first data connection line extending along a first direction, and at least one second data connection line extending along a second direction, wherein the first direction and the second direction intersect; at least one circuit unit includes a pixel driving circuit, a data signal line, and at least one constant potential signal line, wherein the data signal line is configured to provide a data signal to the pixel driving circuit, the constant potential signal line is configured to provide a constant potential signal to the pixel driving circuit, the data signal line is connected to the first data connection line, and the first data connection line is connected to the second The data connection line is connected; at least one circuit unit also includes at least one first break and at least one break shielding structure, the first break is arranged on the first data connection line and cuts off the first data connection line, and the break shielding structure is connected to the constant potential signal line; in a direction perpendicular to the display substrate, the display substrate includes at least a plurality of conductive layers arranged on a base, the first data connection line is arranged in a conductive layer, and the break shielding structure is arranged in any one conductive layer or multiple conductive layers other than the conductive layer where the first data connection line is located; the orthographic projection of the first break on the base at least partially overlaps with the orthographic projection of the break shielding structure on the base.

[0094] In an exemplary embodiment, at least one fracture shielding structure includes a first fracture shielding block, the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the first fracture shielding block on the substrate, and the first fracture shielding block is arranged in the conductive layer on the side of the conductive layer where the first data connection line is located close to the substrate.

[0095] In an exemplary embodiment, at least one constant potential signal line includes a first initial signal line, and the pixel driving circuit includes at least a first transistor and a second transistor, the gate electrode of the first transistor is connected to the second scanning signal line, the first pole of the first transistor is connected to the first initial signal line, the gate electrode of the second transistor is connected to the third scanning signal line, and the first pole of the second transistor is connected to the second pole of the first transistor; in at least one circuit unit, the first initial signal line is arranged between the second scanning signal line and the third scanning signal line, and the first fracture shielding block is connected to the first initial signal line.

[0096] In an exemplary embodiment, at least one constant potential signal line includes a second initial signal line, and the pixel driving circuit includes at least a third transistor and a seventh transistor as driving transistors, the gate electrode of the seventh transistor is connected to the first scanning signal line, and the first electrode of the seventh transistor is connected to the second initial signal line; in at least one circuit unit, the second initial signal line is arranged on a side of the first scanning signal line away from the third transistor, and the first fracture shielding block is connected to the second initial signal line.

[0097] In an exemplary embodiment, at least one circuit unit further includes at least one second break and at least one second break blocking block, wherein the second break is arranged on the second data connection line and cuts off the second data connection line, and the orthographic projection of the second break on the substrate at least partially overlaps with the orthographic projection of the second break blocking block on the substrate.

[0098] In an exemplary embodiment, at least one fracture shielding structure includes a third fracture shielding block, the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the third fracture shielding block on the substrate, and the third fracture shielding block is arranged in the conductive layer on the side of the conductive layer where the first data connection line is located away from the substrate.

[0099] In an exemplary embodiment, at least one constant potential signal line includes a first power line configured to provide a first power signal to the pixel driving circuit; in at least one circuit unit, the third fracture shielding block is connected to the first power line.

[0100] In an exemplary embodiment, at least one constant potential signal line includes a second power line configured to provide a second power signal to the light emitting device; and in at least one circuit unit, the third break blocking block is connected to the second power line.

[0101] FIG6 is a schematic diagram of the structure of a data connection line according to an exemplary embodiment of the present disclosure, wherein the data connection line adopts a FIP structure. As shown in FIG6 , in a plane parallel to the display substrate, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The driving structure layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 73, a plurality of first data connection lines 81, and a plurality of second data connection lines 82. At least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of light-emitting units, and at least one light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0102] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0103] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X intersects the second direction Y.

[0104] In an exemplary embodiment, the second direction Y (vertical direction) may be an extending direction of the data signal line, and the first direction X (horizontal direction) may be perpendicular to the second direction Y.

[0105] In an exemplary embodiment, the first data connection line 81 may be in the shape of a straight line or a zigzag line extending along the first direction X, and the data signal line 73 and the second data connection line 82 may be in the shape of a straight line or a zigzag line extending along the second direction Y. Multiple data signal lines 73 are arranged sequentially at predetermined intervals along the first direction X. At least one data signal line 73 is connected to multiple pixel driving circuits in a cell column, and the data signal line 73 is configured to provide data signals to the connected pixel driving circuit. A first end of at least one first data connection line 81 is connected to a data signal line 73, and a second end is connected to one end of a second data connection line 82. The other end of the second data connection line 82 extends to the bonding area and is connected to a data lead line 80. This connects the data signal line 73 in the display area to the data lead line 80 in the bonding area 200 via the first and second data connection lines 81 and 82, forming a FIP structure (also known as a FIAA structure). In an exemplary embodiment, the first and second data connection lines 81 and 82 are collectively referred to as data connection lines.

[0106] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bend area, a driver chip area, and a binding pin area, arranged sequentially along a direction away from the display area. The lead area 201 is connected to the display area 100, and the bend area is connected to the lead area 201. The lead area 201 may be provided with a plurality of data lead lines 80, extending in a direction away from the display area. The first ends of some of the data lead lines 80 are connected to the second data connection lines 82 in the display area 100, while the first ends of other data lead lines 80 are connected to the data signal lines 73 in the display area 100. The second ends of all data lead lines 80 extend along a second direction Y, cross the bend area, and connect to the integrated circuit in the driver chip area. This allows the integrated circuit to apply data signals to the data signal lines via the data lead lines and data connection lines. Since the first and second data connection lines 81, 82 are arranged within the display area, the length of the lead area in the second direction Y can be effectively reduced, significantly reducing the width of the bottom bezel and increasing the screen-to-body ratio, thus facilitating full-screen display.

[0107] In an exemplary embodiment, the number of data connection lines in the display area may be the same as the number of data signal lines, and each data signal line is connected to a corresponding lead line via a data connection line. Alternatively, the number of data connection lines in the display area may be less than the number of data signal lines, with some of the data signal lines in the display area being connected to corresponding lead lines via data connection lines, while other data signal lines are directly connected to the lead lines. This disclosure is not limited herein.

[0108] Figure 7 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a circuit unit comprising one circuit row and two circuit columns. As shown in Figure 7, within a plane parallel to the display substrate, the drive structure layer may include multiple circuit units constituting multiple unit rows and multiple unit columns, at least one of which may include a pixel drive circuit, which may be connected to a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a first light-emitting signal line 27, a second light-emitting signal line 28, a first initial signal line 41, a second initial signal line 42, a first power line 71, and a data signal line 73, respectively. The first to third scan signal lines 21 to 23 are configured to provide first to third scan signals, respectively, to the pixel driving circuit; the first light-emitting signal line 27 and the second light-emitting signal line 28 are configured to provide first and second light-emitting control signals, respectively, to the pixel driving circuit; the first initial signal line 41 and the second initial signal line 42 are configured to provide first and second initial signals, respectively, to the pixel driving circuit; the first power line 71 is configured to provide a first power signal to the pixel driving circuit; and the data signal line 73 is configured to provide a data signal to the pixel driving circuit. The plurality of signal lines connected to the pixel driving circuit may be located within the circuit unit.

[0109] In an exemplary embodiment, the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the first light-emitting signal line 27, the second light-emitting signal line 28, the first initial signal line 41 and the second initial signal line 42 can be straight lines or broken lines with the main parts extending along the first direction X, and the shapes of the first power line 71 and the data signal line 73 can be straight lines or broken lines with the main parts extending along the second direction Y.

[0110] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the first direction X may be the direction of unit rows, and the second direction Y may be the direction of unit columns.

[0111] In an exemplary embodiment, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors. The plurality of transistors may include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a drive transistor, a fourth transistor T4 as a data write transistor, a fifth transistor T5 as a first emission control transistor, a sixth transistor T6 as a second emission control transistor, and a seventh transistor T7 as a second reset transistor. The storage capacitor may include a first plate and a second plate stacked together.

[0112] In the exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the first electrode and the first plate of the second transistor T2 (which also serves as the gate electrode of the third transistor T3). The gate electrode of the second transistor T2 is connected to the third scan signal line 23, and the second electrode of the second transistor T2 is respectively connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 73, and the second electrode of the fourth transistor T4 is respectively connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The gate electrode of the fifth transistor T5 is connected to the first light emission signal line 27, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the second light emission signal line 28, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the first scanning signal line 21 , and a first electrode of the seventh transistor T7 is connected to the second initial signal line 42 .

[0113] In an exemplary embodiment, in at least one circuit unit, the third scan signal line 23 may be disposed on a side of the storage capacitor opposite to the second direction Y, the first initial signal line 41 may be disposed on a side of the third scan signal line 23 away from the storage capacitor, and the second scan signal line 22 may be disposed on a side of the first initial signal line 41 away from the storage capacitor, i.e., the first initial signal line 41 is disposed between the second scan signal line 22 and the third scan signal line 23. The first light-emitting signal line 27 may be disposed on a side of the storage capacitor in the second direction Y, the first scan signal line 21 may be disposed on a side of the first light-emitting signal line 27 away from the storage capacitor, the second light-emitting signal line 28 may be disposed on a side of the first scan signal line 21 away from the storage capacitor, and the second initial signal line 42 may be disposed on a side of the second light-emitting signal line 28 away from the storage capacitor, i.e., the second initial signal line 42 is disposed on a side of the first scan signal line 21 away from the storage capacitor (the third transistor T3).

[0114] In an exemplary embodiment, at least one circuit unit may further include at least one first data connection line 81 and at least one second data connection line 82. The first data connection line 81 may be in the shape of a straight line or a zigzag line extending along the first direction X, and the second data connection line 82 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The at least one first data connection line 81 is connected to the data signal line 73 and the second data connection line 82, respectively, to form a structure in which the data connection lines are located in the display area.

[0115] In an exemplary embodiment, at least one first data link line 81 may be disposed between the second scan signal line 22 and the first initial signal line 41 in the second direction Y. At least one second data link line 82 may be disposed between adjacent cell columns in the first direction X, that is, between adjacent circuit cells in the first direction X.

[0116] In an exemplary embodiment, at least one circuit unit may further include at least one first break K1, which is arranged on the first data connection line 81 and cuts the first data connection line 81 into a first connection sub-line and a second connection sub-line, the first connection sub-line is located on the side of the first break K1 in the opposite direction of the first direction X, and the second connection sub-line is located on the side of the first break K1 in the first direction X, the first connection sub-line is configured to be connected to a data signal line 73, and the second connection sub-line is configured as a first virtual line.

[0117] In an exemplary embodiment, at least one circuit unit may further include a first fracture blocking block 61 as a shielding structure, and the orthographic projection of the first fracture K1 on the substrate at least partially overlaps with the orthographic projection of the first fracture blocking block 61 on the substrate, and the first fracture blocking block 61 can shield the first fracture K1 from below to improve transmittance.

[0118] In an exemplary embodiment, in at least one circuit unit, the shape of the first fracture blocking block 61 can be block-shaped (such as rectangular), and can be arranged on the side of the first initial signal line 41 close to the second scanning signal line 22, and connected to the first initial signal line 41 which is the constant potential signal line of the present invention.

[0119] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first conductive layer disposed on a substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate. The first data connection line 81 may be disposed in the third conductive layer, and the first break blocking block 61 may be disposed in the conductive layer on a side of the third conductive layer close to the substrate. For example, the first break blocking block 61 may be disposed in the first conductive layer. For another example, the first break blocking block 61 may be disposed in the second conductive layer. For another example, the first break blocking block 61 may be disposed in both the first conductive layer and the second conductive layer.

[0120] In an exemplary embodiment, the first initial signal line 41 and the first fracture shielding block 61 may be disposed in the same layer in the second conductive layer and may be an integrated structure connected to each other.

[0121] In an exemplary embodiment, the first transistor T1 may include at least a first active layer, the second transistor may include at least a second active layer, and the second region of the first active layer and the first region of the second active layer are interconnected. In at least one circuit unit, the orthographic projection of the first notch blocking block 61 on the substrate at least partially overlaps the orthographic projection of the second region of the first active layer on the substrate, such that the first notch blocking block 61 forms a node capacitance with the first node N1 of the pixel driving circuit.

[0122] In an exemplary embodiment, at least one circuit unit may further include at least one second break K2, which is arranged on the second data connection line 82 and cuts the second data connection line 82 into a third connection sub-line and a fourth connection sub-line, the third connection sub-line is located on the second direction Y side of the second break K2, and the fourth connection sub-line is located on the opposite direction of the second direction Y of the second break K2, the third connection sub-line is connected to the first connection sub-line in the first data connection line 81, and the fourth connection sub-line is configured as a second virtual line.

[0123] In an exemplary embodiment, at least one circuit unit may further include a second fracture blocking block 62, and the orthographic projection of the second fracture K2 on the substrate at least partially overlaps with the orthographic projection of the second fracture blocking block 62 on the substrate, and the second fracture blocking block 62 can block the second fracture K2 from below to improve transmittance.

[0124] In an exemplary embodiment, in at least one circuit unit, the second break shielding block 62 may be block-shaped (e.g., rectangular). In the first direction X, the second break K2 and the second break shielding block 62 may be disposed between adjacent circuit units in the first direction X. In the second direction Y, the second break shielding block 62 may be disposed on a side of the second initial signal line 42 away from the second scan signal line 22 and connected to the second initial signal line 42.

[0125] In an exemplary embodiment, the second data connection line 82 may be disposed in the fourth conductive layer, and the second break shielding block 62 may be disposed in the conductive layer on the side of the fourth conductive layer closer to the substrate. For example, the second break shielding block 62 may be disposed in the first conductive layer. In another example, the second break shielding block 62 may be disposed in the second conductive layer. In another example, the second break shielding block 62 may be disposed in the third conductive layer.

[0126] In an exemplary embodiment, the second initial signal line 42 and the second fracture shielding block 62 may be disposed in the same layer in the second conductive layer and are an integrated structure connected to each other.

[0127] In an exemplary embodiment, at least one circuit unit may further include a second power line 72 . The second power line 72 may be in a straight line or a zigzag shape extending along the second direction Y and may be disposed between the first power line 71 and the data signal line 73 .

[0128] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in a unit row may be symmetrically arranged relative to a column centerline, where the column centerline may be a straight line located between two adjacent circuit units in the first direction X and extending along the second direction Y. For example, the pixel driving circuits in the Nth unit column and the N+1th unit column may be symmetrically arranged relative to the column centerline. In an exemplary embodiment, the pixel driving circuits in adjacent unit rows may be substantially identical.

[0129] The following is an exemplary description of the preparation process of the substrate shown in this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating a photoresist on the film layer, mask exposure, development, etching, and stripping the photoresist for metal materials, inorganic materials, or transparent conductive materials. For organic materials, it includes processes such as coating an organic material, mask exposure, and development. Deposition can be achieved by any one or more of sputtering, evaporation, and chemical vapor deposition. Coating can be achieved by any one or more of spraying, spin coating, and inkjet printing. Etching can be achieved by any one or more of dry etching and wet etching, and this disclosure does not limit this. "Thin film" refers to a thin film made by depositing, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are provided in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0130] In an exemplary embodiment, taking two circuit units of one unit row and two unit columns as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0131] (11) Forming a blocking layer pattern. In an exemplary embodiment, forming the blocking layer pattern may include: depositing a blocking film on a substrate, patterning the blocking film through a patterning process, and forming a blocking layer pattern on the substrate, as shown in FIG8 . In an exemplary embodiment, the blocking layer may be referred to as a bottom metal (LS) layer.

[0132] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 90 , a first shielding connection bar 91 , a second shielding connection bar 92 , a third shielding connection bar 93 , a fourth shielding connection bar 94 , a first shielding block 95 , and a second shielding block 96 .

[0133] In an exemplary embodiment, the shape of the blocking electrode 90 can be rectangular, and the corners of the rectangle can be chamfered or grooved. The blocking electrode 90 can be set in the middle area of ​​the circuit unit in the first direction X and the second direction Y. The blocking electrode 90 is configured to block the channel area of ​​the third transistor T3.

[0134] In an exemplary embodiment, the first shielding connection bar 91 may be in the shape of a bar and may be disposed between partially adjacent shielding electrodes 90. A first end of the first shielding connection bar 91 is connected to the shielding electrode 90 in one circuit unit, and a second end of the first shielding connection bar 91 is connected to the shielding electrode 90 in the other circuit unit. For example, the first shielding connection bar 91 may be disposed between the shielding electrode 90 in the Nth cell column and the shielding electrode 90 in the (N+1)th cell column.

[0135] In an exemplary embodiment, the second shielding connection bar 92 may be in the shape of a bar and may be disposed between adjacent shielding electrodes 90. The first end of the second shielding connection bar 92 is connected to the shielding electrode 90 in one circuit cell, and the second end of the second shielding connection bar 92 is connected to the shielding electrode 90 in the other circuit cell. For example, the second shielding connection bar 92 may be disposed between the shielding electrode 90 in the N-1th cell column and the shielding electrode 90 in the Nth cell column. For another example, the second shielding connection bar 92 may be disposed between the shielding electrode 90 in the N+1th cell column and the shielding electrode 90 in the N+2th cell column.

[0136] In an exemplary embodiment, the extension direction of the first shielding connection strip 91 and the second shielding connection strip 92 may be along the first direction X, or may have a set angle with the first direction X, which is not limited in the present disclosure.

[0137] In an exemplary embodiment, in at least one cell row, the shielding electrode 90 , the first shielding connection bar 91 , and the second shielding connection bar 92 may be an integrated structure connected to each other.

[0138] In an exemplary embodiment, the shape of the third shielding connection bar 93 and the fourth shielding connection bar 94 can be a straight line or a broken line with the main part extending along the second direction Y. The third shielding connection bar 93 can be set on the side of the shielding electrode 90 in the opposite direction of the second direction Y, and the fourth shielding connection bar 94 can be set on the side of the shielding electrode 90 in the second direction Y. The first end of the third shielding connection bar 93 in this unit row is connected to the shielding electrode 90 in this unit row, and the second end of the third shielding connection bar 93 is connected to the second end of the fourth shielding connection bar 94 in the previous unit row. The first end of the fourth shielding connection bar 94 in this unit row is connected to the shielding electrode 90 in this unit row, and the second end of the fourth shielding connection bar 94 is connected to the second end of the third shielding connection bar 93 in the next unit row.

[0139] In an exemplary embodiment, the extension direction of the third shielding connection bar 93 and the fourth shielding connection bar 94 may be along the second direction Y, or may have a set angle with the second direction Y, which is not limited in the present disclosure.

[0140] In an exemplary embodiment, the first shielding block 95 may be shaped like a block (e.g., a rectangle), and the second shielding block 96 may be shaped like an "L." In the first direction X, the first shielding block 95 may be positioned on a side of the third shielding connecting bar 93 opposite to the first direction X, and the second shielding block 96 may be positioned on a side of the third shielding connecting bar 93 opposite to the first direction X. In the second direction Y, the second shielding block 96 may be positioned on a side of the shielding electrode 90 opposite to the second direction Y, and the first shielding block 95 may be positioned on a side of the second shielding block 96 away from the shielding electrode 90. The first shielding block 95 is configured to shield the channel region of the first transistor T1, and the second shielding block 96 is configured to shield the channel region of the second transistor T2.

[0141] In an exemplary embodiment, a first end of the first shielding block 95 may be connected to the third shielding connection bar 93, and a second end of the first shielding block 95 may extend in a direction opposite to the first direction X. A first end of the second shielding block 96 proximate to the shielding electrode 90 may be connected to the shielding electrode 90 and the first shielding connection bar 91, a second end of the second shielding block 96 proximate to the third shielding connection bar 93 may be connected to the third shielding connection bar 93, and a third end of the second shielding block 96 distal from the third shielding connection bar 93 may be connected to the second shielding block 96 of an adjacent circuit unit in the first direction X.

[0142] In an exemplary embodiment, in at least one unit column, the shielding electrode 90 , the third shielding connection bar 93 , the fourth shielding connection bar 94 , the first shielding block 95 , and the second shielding block 96 may be an integrated structure connected to each other.

[0143] In an exemplary embodiment, the blocking layers in multiple unit rows and multiple unit columns can be an integrated structure that is interconnected, which can ensure that the blocking layers in the display substrate have the same electric potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0144] In an exemplary embodiment, the position and shape of the shielding layers in two adjacent circuit cells in a cell row can be symmetrically arranged relative to the column centerline. For example, the position and shape of the shielding layers in the Nth cell column and the N+1th cell column can be symmetrically arranged relative to the column centerline. In an exemplary embodiment, the position and shape of the shielding layers in multiple circuit cells in a cell column can be substantially identical.

[0145] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG9A and FIG9B , where FIG9B is a plan view schematic diagram of the semiconductor layer in FIG9A .

[0146] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7 , and the first to seventh active layers 11 to 17 may be an integral structure connected to each other.

[0147] In an exemplary embodiment, in the second direction Y, the first active layer 11 and the second active layer 12 may be located on a side of the third active layer 13 in the opposite direction of the second direction Y, and the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, the seventh active layer 17 and the seventh active layer 17 may be located on a side of the third active layer 13 in the second direction Y.

[0148] In an exemplary embodiment, the third active layer 13 may have an arch shape, the first active layer 11 may have an "n" shape, the second active layer 12 and the fifth active layer 15 may have an "L" shape, and the fourth active layer 14, the sixth active layer 16, and the seventh active layer 17 may have an "I" shape.

[0149] In some possible implementations, the third active layer 13 may be in the shape of a strip extending along the first direction X.

[0150] In an exemplary embodiment, each of the first to seventh active layers 11 to 17 may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be interconnected, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be interconnected, and the second region 12-2 of the second active layer may serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer can be provided separately.

[0151] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may further include a node active layer 18. The node active layer 18 may be block-shaped (e.g., rectangular), may be disposed between the first region 12-1 of the second active layer and the second region 12-2 of the second active layer, and may be connected to the second active layer 12.

[0152] In an exemplary embodiment, the node active layers 18 in some adjacent circuit cells may be interconnected to form an interconnected integral structure. For example, the node active layer 18 in the Nth cell column and the node active layer 18 in the N+1th cell column may be interconnected as an integral structure.

[0153] In the exemplary embodiment, since the first active layer 11 to the seventh active layer 17 in each circuit unit are interconnected as an integrated structure, the second active layer 12 is connected to the node active layer 18, and the node active layers 18 in adjacent circuit units are interconnected, the semiconductor layers in some adjacent circuit units can be interconnected as an integrated structure. For example, the semiconductor layer in the Nth unit column and the semiconductor layer in the (N+1)th unit column can be interconnected as an integrated structure.

[0154] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 90 on the substrate. The shielding electrode 90 can serve as a shielding layer for the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0155] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer 13 on the substrate is located within the range of the orthographic projection of the shielding electrode 90 on the substrate.

[0156] In an exemplary embodiment, the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the first blocking block 95 on the substrate. The first blocking block 95 can serve as a blocking layer for the first transistor T1, blocking the channel region of the first transistor T1 and ensuring the electrical performance of the first transistor T1.

[0157] In an exemplary embodiment, the orthographic projection of the channel region of the first active layer 11 on the substrate is located within the range of the orthographic projection of the first blocking block 95 on the substrate.

[0158] In an exemplary embodiment, the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the second blocking block 96 on the substrate. The second blocking block 96 can serve as a blocking layer for the second transistor T2, blocking the channel region of the second transistor T2 and ensuring the electrical performance of the second transistor T2.

[0159] In an exemplary embodiment, the orthographic projection of the channel region of the second active layer 12 on the substrate is located within the range of the orthographic projection of the second blocking block 96 on the substrate.

[0160] In an exemplary embodiment, the positions and shapes of the semiconductor layers in two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the positions and shapes of the semiconductor layers in the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. In an exemplary embodiment, the positions and shapes of the shielding layers in multiple circuit cells in a cell column may be substantially identical.

[0161] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), i.e., the third to seventh transistors are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a semiconductor layer pattern.

[0162] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the first conductive layer in FIG10A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0163] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a fifth gate electrode 25, a sixth gate electrode 26 and a first plate 31 of a storage capacitor.

[0164] In an exemplary embodiment, the shape of the first electrode plate 31 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The first electrode plate 31 can serve as the lower plate of the storage capacitor and the gate electrode of the third transistor T3 at the same time.

[0165] In an exemplary embodiment, the orthographic projection of the overlapping area between the first electrode 31 and the third active layer on the substrate can be located within the range of the orthographic projection of the blocking electrode 90 on the substrate. The blocking electrode 90 can block the channel area of ​​the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0166] In an exemplary embodiment, the shape of the first scanning signal line 21 can be a straight line or a broken line extending along the first direction X, and can be arranged on one side of the first electrode plate 31 in the second direction Y. The area where the first scanning signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, and the area where the first scanning signal line 21 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7.

[0167] In an exemplary embodiment, the shape of the second scanning signal line 22 can be a straight line or a broken line extending along the first direction X, and can be arranged on the side of the first electrode plate 31 in the opposite direction of the second direction Y. The area where the second scanning signal line 22 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0168] In an exemplary embodiment, the orthographic projection of the overlapping area of ​​the second scan signal line 22 and the first active layer on the substrate can be located within the range of the orthographic projection of the first blocking block 95 on the substrate, and the first blocking block 95 can block the channel area of ​​the first transistor T1 to ensure the electrical performance of the first transistor T1.

[0169] In an exemplary embodiment, the third scan signal line 23 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed between the first electrode plate 31 and the second scan signal line 22. A gate block 23-1 may be disposed on the third scan signal line 23. The gate block 23-1 may be in the shape of a bar extending along the second direction Y. A first end of the gate block 23-1 is connected to a side of the third scan signal line 23 that is close to the second scan signal line 22, and a second end of the gate block 23-1 extends toward the second scan signal line 22. The region where the third scan signal line 23, the gate block 23-1, and the second active layer overlap may serve as the gate electrode of the second transistor T2 having a dual-gate structure.

[0170] In an exemplary embodiment, the positive projection of the overlapping area of ​​the third scan signal line 23 and the gate block 23-1 with the second active layer on the substrate can be located within the range of the positive projection of the second blocking block 96 on the substrate, and the second blocking block 96 can block the channel area of ​​the second transistor T2 to ensure the electrical performance of the second transistor T2.

[0171] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, and the third scan signal line 23 can be straight lines of unequal widths, and the widths of the first scan signal line 21, the second scan signal line 22, and the third scan signal line 23 at the intersection with the semiconductor layer can be greater than the widths at other positions.

[0172] In an exemplary embodiment, the fifth gate electrode 25 may be in the shape of a strip extending along the first direction X and may be disposed between the first electrode plate 31 and the first scan signal line 21. The region where the fifth gate electrode 25 overlaps the fifth active layer may serve as the gate electrode of the fifth transistor T5.

[0173] In an exemplary embodiment, a fifth gate connection block 25-1 may be provided on the fifth gate electrode 25. The fifth gate connection block 25-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the fifth gate electrode 25 close to the sixth gate electrode 26 and connected to the fifth gate electrode 25. The fifth gate connection block 25-1 is configured to be connected to a first light-emitting signal line formed subsequently.

[0174] In an exemplary embodiment, the sixth gate electrode 26 may be in the shape of a strip extending along the first direction X and may be disposed between the first electrode plate 31 and the first scan signal line 21. The region where the sixth gate electrode 26 overlaps the sixth active layer may serve as the gate electrode of the sixth transistor T6.

[0175] In an exemplary embodiment, a sixth gate connection block 26-1 may be provided on the sixth gate electrode 26. The sixth gate connection block 26-1 may be in a block shape (e.g., rectangular) and may be provided on a side of the sixth gate electrode 26 away from the fifth gate electrode 25 and connected to the sixth gate electrode 26. The sixth gate connection block 26-1 is configured to be connected to a second light-emitting signal line formed subsequently.

[0176] In an exemplary embodiment, the sixth gate connection blocks 26-1 in some adjacent circuit cells may be interconnected to form an interconnected integral structure, so that the sixth gate electrodes 26 of two circuit cells share the same sixth gate connection block 26-1. For example, the sixth gate electrodes 26 and the sixth gate connection blocks 26-1 in the Nth cell column and the (N+1)th cell column may be interconnected integral structures.

[0177] The present disclosure sets the sixth gate electrodes 26 of adjacent circuit units as an interconnected integrated structure, so that the sixth transistors T6 of two adjacent pixel driving circuits share the same sixth gate connection block, which can effectively reduce the occupied space of the pixel driving circuit and improve the display resolution.

[0178] In an exemplary embodiment, the positions and shapes of the first conductive layers of two adjacent circuit cells in a cell row may be symmetrically arranged relative to the column centerline. For example, the positions and shapes of the first conductive layers of the Nth cell column and the N+1th cell column may be symmetrically arranged relative to the column centerline. In an exemplary embodiment, the positions and shapes of the first conductive layers of multiple circuit cells in a cell column may be substantially the same.

[0179] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film through a patterning process to form a third insulating layer covering the first conductive layer pattern, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the second conductive layer in FIG11A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0180] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: a second plate 32 of the storage capacitor, a first initial signal line 41 , a second initial signal line 42 , a first shielding electrode 43 , and a second shielding electrode 44 .

[0181] In an exemplary embodiment, the outline of the second plate 32 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second plate 32 on the substrate at least partially overlaps with the orthographic projection of the first plate 31 on the substrate. The second plate 32 can serve as the upper plate of the storage capacitor, and the first plate 31 and the second plate 32 constitute a storage capacitor.

[0182] In an exemplary embodiment, an opening 33 is provided on the second electrode plate 32. Opening 33 can be rectangular and located in the central region of the second electrode plate 32, forming a ring-shaped second electrode plate 32. Opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of opening 33 on the substrate. In an exemplary embodiment, opening 33 is configured to accommodate a ninth via hole to be formed later. The ninth via hole is located within opening 33 and exposes the first electrode plate 31, allowing a first connecting electrode to be formed later to connect to the first electrode plate 31.

[0183] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate connection bar 34. The plate connection bar 34 may be in the shape of a straight line or a broken line extending along the first direction X. The plate connection bar 34 may be provided on one side of the second electrode plate 32 in the first direction X or on a side opposite to the first direction X. The first end of the plate connection bar 34 is connected to the second electrode plate 32 in the current circuit unit, and the second end of the plate connection bar 34 is connected to the second electrode plate 32 in the adjacent circuit unit in the first direction X.

[0184] In an exemplary embodiment, the second plates 32 and plate connection bars 34 in two adjacent circuit cells in a cell row can be interconnected as a single, integrated structure. For example, the second plates 32 in the Nth cell column and the second plates 32 in the N+1th cell column are interconnected via the plate connection bars 34, forming a connected, integrated structure. Because the second plates 32 in each circuit cell are connected to a subsequently formed first power line, by forming the second plates 32 of adjacent circuit cells into a connected, integrated structure, the second plates of this integrated structure can be reused as power signal lines, ensuring that multiple second plates in a cell row have the same potential, which helps improve panel uniformity, avoid display defects on the display substrate, and ensure the display quality of the display substrate.

[0185] In an exemplary embodiment, the second electrode plate 32 may be provided with a plate connection electrode 35. The plate connection electrode 35 may be in the shape of a strip extending along the second direction Y and may be provided on a side of the second electrode plate 32 close to the first scan signal line 21. A first end of the plate connection electrode 35 is connected to the side of the second electrode plate 32 close to the first scan signal line 21, and a second end of the plate connection electrode 35 extends in a direction close to the first scan signal line 21. The plate connection electrode 35 is configured to be connected to the first region of the fifth active layer via a third connection electrode formed subsequently.

[0186] In an exemplary embodiment, the first initial signal line 41 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed between the second scan signal line 22 and the third scan signal line 23. A first initial connection block 41-1 may be disposed on the first initial signal line 41. The first initial connection block 41-1 may be in the shape of a bar extending along the second direction Y. A first end of the first initial connection block 41-1 is connected to a side of the first initial signal line 41 close to the third scan signal line 23, and a second end of the first initial connection block 41-1 extends in a direction close to the third scan signal line 23. The first initial connection block 41-1 is configured to be connected to the first region of the first active layer via a sixth connection electrode formed subsequently.

[0187] In an exemplary embodiment, the second initial signal line 42 may be in the shape of a straight line or a zigzag line extending along the first direction X, and may be disposed on a side of the first scan signal line 21 away from the second electrode plate 32. A second initial connection block 42-1 may be disposed on the second initial signal line 42. The second initial connection block 42-1 may be in the shape of a block (e.g., a rectangle). A first end of the second initial connection block 42-1 is connected to a side of the second initial signal line 42 that is close to the first scan signal line 21, and a second end of the second initial connection block 42-1 extends in a direction close to the first scan signal line 21. The second initial connection block 42-1 is configured to be connected to the first region of the seventh active layer via a subsequently formed seventh connection electrode.

[0188] In an exemplary embodiment, the first shielding electrode 43 can be block-shaped (e.g., rectangular) and can be disposed on a side of the first initial signal line 41 near the third scan signal line 23. A first end of the first shielding electrode 43 is connected to a side of the first initial signal line 41 near the third scan signal line 23, and a second end of the first shielding electrode 43 extends toward the third scan signal line 23. The orthographic projection of the first shielding electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second active layer and the node active layer 18 between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 43 is configured to shield the node between the two gate electrodes of the second transistor T2, thereby preventing the impact of data voltage jumps on the second transistor T2, reducing the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improving the display effect.

[0189] In an exemplary embodiment, the first preliminary signal line 41 , the first preliminary connection block 41 - 1 , and the first shielding electrode 43 may be an integral structure connected to each other.

[0190] In an exemplary embodiment, the first shielding electrodes 43 in some adjacent circuit cells may be connected to each other to form an integrated structure. For example, the first shielding electrode 43 in the Nth cell column and the first shielding electrode 43 in the N+1th cell column may be connected to each other to form an integrated structure.

[0191] In an exemplary embodiment, the second shielding electrode 44 can be block-shaped (e.g., rectangular) and can be disposed on a side of the second initial signal line 42 that is close to the first scan signal line 21. A first end of the second shielding electrode 44 is connected to a side of the second initial signal line 42 that is close to the first scan signal line 21, and a second end of the second shielding electrode 44 extends toward the first scan signal line 21. The orthographic projection of the second shielding electrode 44 on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes of the first transistor T1 on the substrate. In an exemplary embodiment, the second shielding electrode 44 is configured to shield the node between the two gate electrodes of the first transistor T1, thereby preventing the impact of data voltage jumps on the first transistor T1, reducing the impact of data voltage jumps on the normal operation of the pixel driving circuit, and improving the display effect.

[0192] In an exemplary embodiment, the second preliminary signal line 42 , the second preliminary connection block 42 - 1 , and the second shielding electrode 44 may be an integral structure connected to each other.

[0193] In an exemplary embodiment, the second conductive layer of at least one circuit unit may further include a first break blocking block 61. The first break blocking block 61 may be block-shaped (e.g., rectangular) and may be disposed on a side of the first initial signal line 41 that is adjacent to the second scan signal line 22. A first end of the first break blocking block 61 is connected to a side of the first initial signal line 41 that is adjacent to the second scan signal line 22, and a second end of the first break blocking block 61 extends toward the second scan signal line 22. The first break blocking block 61 is configured to block a first break on the first data link line that is subsequently formed from below.

[0194] In an exemplary embodiment, the first fracture blocking block 61 may be provided in the circuit cell of the (N+1)th cell column.

[0195] In the exemplary embodiment, the orthographic projection of the first fracture shielding block 61 on the substrate at least partially overlaps the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate. Because the second region of the first active layer (also the first region of the second active layer) is connected to a subsequently formed first connection electrode, which serves as the first node N1 of the pixel driving circuit, the first fracture shielding block 61 forms a node capacitance with the first node N1. The node capacitance is configured to stabilize the potential of the first node N1.

[0196] In an exemplary embodiment, the second conductive layer of at least one circuit unit may further include a second break blocking block 62. The second break blocking block 62 may be block-shaped (e.g., rectangular) and may be disposed on a side of the second initial signal line 42 away from the second scan signal line 22. A first end of the second break blocking block 62 is connected to a side of the second initial signal line 42 away from the second scan signal line 22, and a second end of the second break blocking block 62 extends away from the second scan signal line 22. The second break blocking block 62 is configured to block a second break on the second data link line that is subsequently formed from below.

[0197] In an exemplary embodiment, the first break shielding block 61 and the second break shielding block 62 can be provided in the same circuit unit, or respectively provided in two circuit units, which is not limited in this disclosure. For example, the first break shielding block 61 can be provided in the circuit unit of the Mth unit row, and the second break shielding block 62 can be provided in the circuit unit of the M-1th unit row, where M can be a positive integer greater than or equal to 2.

[0198] In an exemplary embodiment, the positions and shapes of the second conductive layers (excluding the first and second break shielding blocks) in two adjacent circuit cells in a cell row can be symmetrically arranged relative to the column centerline. For example, the positions and shapes of the second conductive layers in the Nth cell column and the N+1th cell column can be symmetrically arranged relative to the column centerline. In an exemplary embodiment, the positions and shapes of the second conductive layers in multiple circuit cells in a cell column can be substantially identical.

[0199] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein the fourth insulating layer is provided with a plurality of vias, as shown in FIG. 12 .

[0200] In an exemplary embodiment, the multiple vias of each circuit unit in the display substrate include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12 and a thirteenth via V13.

[0201] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the second insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed sixth connecting electrode to the first region of the first active layer through the via hole.

[0202] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the second insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer within the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0203] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the first region of the fourth active layer through the via hole.

[0204] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fourth via hole V4 are etched away to expose the surface of the first region of the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed third connecting electrode to the first region of the fifth active layer through the via hole.

[0205] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the fifth via hole V5 is configured to connect the subsequently formed fourth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via hole V6 is configured to connect the subsequently formed seventh connecting electrode to the first region of the seventh active layer through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the fifth gate connection block 25-1 of the fifth gate electrode 25 on the substrate, the third insulating layer and the fourth insulating layer in the seventh via hole V7 are etched away to expose the surface of the fifth gate connection block 25-1, and the seventh via hole V7 is configured to connect the subsequently formed first light-emitting signal line to the fifth gate connection block 25-1 through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the sixth gate connection block 26-1 of the sixth gate electrode 26 on the substrate. The third insulating layer and the fourth insulating layer within the eighth via hole V8 are etched away, exposing the surface of the sixth gate connection block 26-1. The eighth via hole V8 is configured to connect a subsequently formed second light-emitting signal line to the sixth gate connection block 26-1 through the via hole. In an exemplary embodiment, the eighth via hole V8 can be referred to as a gate connection via hole.

[0209] In an exemplary embodiment, since the sixth gate electrodes 26 in some adjacent circuit units are an integrated structure connected to each other, the sixth gate electrodes 26 of the two circuit units share the same sixth gate connection block 26-1, and thus the two circuit units can share the same gate connection via, effectively reducing the number of vias, which can effectively reduce the space occupied by the pixel driving circuit, and is conducive to improving the resolution.

[0210] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, the third insulating layer and the fourth insulating layer in the ninth via hole V9 are etched away to expose the surface of the first electrode 31, and the ninth via hole V9 is configured to connect the subsequently formed first connecting electrode to the first electrode 31 through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the fourth insulating layer in the tenth via hole V10 is etched away, exposing the surface of the second electrode plate 32, and the tenth via hole V10 is configured to connect the subsequently formed fifth connecting electrode to the second electrode plate 32 through the via hole.

[0212] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the fourth insulating layer in the eleventh via V11 is etched away, exposing the surface of the first initial connection block 41-1, and the eleventh via V11 is configured to connect the subsequently formed sixth connection electrode to the first initial connection block 41-1 through the via.

[0213] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the fourth insulating layer in the twelfth via V12 is etched away, exposing the surface of the second initial connection block 42-1, and the twelfth via V12 is configured to connect the subsequently formed seventh connection electrode to the second initial connection block 42-1 through the via.

[0214] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the plate connecting electrode 35 of the second electrode plate 32 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away, exposing the surface of the plate connecting electrode 35, and the thirteenth via hole V13 is configured to connect the subsequently formed third connecting electrode to the plate connecting electrode 35 through the via hole.

[0215] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG13A and FIG13B , where FIG13B is a plan view schematic diagram of the third conductive layer in FIG13A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0216] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first light emitting signal line 27, a second light emitting signal line 28, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57 and a first data connection line 81.

[0217] In an exemplary embodiment, the first light-emitting signal line 27 may be in the shape of a straight line or a zigzag line extending along the first direction X. It may be located between the second electrode plate 32 and the first scanning signal line 21. The first light-emitting signal line 27 is connected to the fifth gate connection block 25-1 via a seventh via hole V7. Since the fifth gate connection block 25-1 is connected to the fifth gate electrode 25, the first light-emitting signal line 27 is connected to the fifth gate electrode 25. The first light-emitting signal line 27 can control the conduction or disconnection of the fifth transistor T5.

[0218] In an exemplary embodiment, the second light-emitting signal line 28 may be in the shape of a straight line or a zigzag line extending along the first direction X and may be located between the first light-emitting signal line 27 and the second initial signal line 42. A light-emitting connection block 28-1 may be provided on the second light-emitting signal line 28. The light-emitting connection block 28-1 may be in the shape of a bar extending along the second direction Y and may be provided on a side of the second light-emitting signal line 28 near the first light-emitting signal line 27. A first end of the light-emitting connection block 28-1 is connected to a side of the second light-emitting signal line 28 near the first light-emitting signal line 27. A second end of the light-emitting connection block 28-1 extends toward the first light-emitting signal line 27 and is connected to the sixth gate connection block 26-1 through an eighth via V8. Since the sixth gate connection block 26-1 is connected to the sixth gate electrode 26, the second light-emitting signal line 28 is connected to the sixth gate electrode 26. The second light-emitting signal line 28 can control the conduction or disconnection of the sixth transistor T6.

[0219] In an exemplary embodiment, the light-emitting connection blocks 28-1 in some adjacent circuit units can be connected to each other to form an integrated structure that is connected to each other, so that the second light-emitting signal lines 28 of the two circuit units share the same light-emitting connection block 28-1 and are connected to the sixth gate connection block 26-1 through the eighth via V8 shared by the two circuit units.

[0220] In an exemplary embodiment, the present disclosure effectively reduces the resistance of the light-emitting signal lines and the voltage drop of the light-emitting signals by setting the first light-emitting signal line 27 and the second light-emitting signal line 28 in a first source-drain metal (SD1) layer with a larger thickness, thereby improving the quality of light-emitting control and display quality.

[0221] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the first direction X. A first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the first connection electrode 51 is connected to the first electrode plate 31 via a ninth via hole V9. Because the first electrode plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 interconnects the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 of the storage capacitor, thereby forming a first node N1 of the pixel driving circuit.

[0222] In an exemplary embodiment, the second connection electrode 52 may be block-shaped (eg, rectangular), connected to the first region of the fourth active layer through the third via hole V3, and configured to be connected to a subsequently formed data signal line.

[0223] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip extending along the first direction X. A first end of the third connection electrode 53 is connected to the first region of the fifth active layer via a fourth via hole V4, and a second end of the third connection electrode 53 is connected to the plate connection electrode 35 via a thirteenth via hole V13. Because the plate connection electrode 35 is connected to the second plate 32, the third connection electrode 53 connects the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor to each other, and the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor have the same potential.

[0224] In an exemplary embodiment, the shape of the fourth connecting electrode 54 can be block-shaped (such as rectangular), and the fourth connecting electrode 54 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the fifth via V5. The fourth connecting electrode 54 is configured to be connected to the subsequently formed anode connecting electrode.

[0225] In an exemplary embodiment, the fifth connection electrode 55 may be block-shaped (eg, rectangular) and connected to the second electrode plate 32 through the tenth via hole V10 . The fifth connection electrode 55 is configured to be connected to a first power line formed subsequently.

[0226] In an exemplary embodiment, the sixth connection electrode 56 may be in the shape of a strip extending along the first direction X. A first end of the sixth connection electrode 56 is connected to the first region of the first active layer via a first via hole V1, and a second end of the sixth connection electrode 56 is connected to the first initial connection block 41-1 via an eleventh via hole V11. Because the first initial connection block 41-1 is connected to the first initial signal line 41, the sixth connection electrode 56 enables the first initial signal line 41 to write the first initial signal to the first electrode of the first transistor T1.

[0227] In an exemplary embodiment, the seventh connection electrode 57 may be in the shape of a strip extending along the first direction X. A first end of the seventh connection electrode 57 is connected to the first region of the seventh active layer via a sixth via hole V6, and a second end of the seventh connection electrode 57 is connected to the second initial connection block 42-1 via a twelfth via hole V12. Because the second initial connection block 42-1 is connected to the second initial signal line 42, the seventh connection electrode 57 enables the second initial signal line 42 to write the second initial signal to the first electrode of the seventh transistor T7.

[0228] In an exemplary embodiment, the first data link line 81 may be in a straight line or a zigzag line shape extending along the first direction X, and may be located between the second scan signal line 22 and the first initial signal line 41 .

[0229] In an exemplary embodiment, the first data link line 81 in at least one circuit unit may be provided with a first break K1 , which may cut off the first data link line 81 so that the first data link lines 81 on both sides of the first break K1 are insulated from each other.

[0230] In an exemplary embodiment, the first data connection line 81 may include a first connection sub-line 81-1 located on the opposite side of the first direction X of the first break K1 and a second connection sub-line 81-2 located on the side of the first direction X of the first break K1, the first connection sub-line 81-1 being configured to be connected to a data signal line in the display area, and the second connection sub-line 81-2 being configured as a first dummy line.

[0231] In an exemplary embodiment, at least one first break K1 may be provided in the circuit unit of the (N+1)th unit column, and an orthographic projection of the first break K1 on the substrate at least partially overlaps with an orthographic projection of the first break blocking block 61 on the substrate.

[0232] In an exemplary embodiment, the orthographic projection of the first fracture K1 on the substrate can be located within the range of the orthographic projection of the first fracture blocking block 61 on the substrate, so that the first fracture blocking block 61 can block the first fracture K1 from below, which can not only effectively eliminate the difference in film layers in different areas, which is beneficial to eliminating shadows and avoiding poor appearance of the display substrate, but also can block the first fracture K1 from below, which is beneficial to improving transmittance.

[0233] In an exemplary embodiment, a data connection block 83 may be provided on the first connection sub-line 81-1 in at least one circuit unit. The data connection block 83 may be in a block shape (e.g., rectangular). The data connection block 83 may be provided between the Nth unit column and the N+1th unit column in the first direction X. The data connection block 83 may be provided on a side of the first connection sub-line 81-1 close to the third scan signal line 23 in the second direction Y and connected to the first connection sub-line 81-1. The data connection block 83 is configured to connect to a subsequently formed second data connection line located between the Nth unit column and the N+1th unit column.

[0234] In an exemplary embodiment, the first connection sub-line 81 - 1 and the data connection block 83 may be an integral structure connected to each other.

[0235] In an exemplary embodiment, the second connecting sub-line 81-2 serving as the first dummy line may not be connected to any signal line, or may be connected to the first power line, or may be connected to the second power line, or may be connected to the first initial signal line, or may be connected to the second initial signal line, and the present disclosure does not limit this.

[0236] In an exemplary embodiment, the positions and shapes of the third conductive layers (excluding the data connection block and the first break) in two adjacent circuit cells in a cell row can be symmetrically arranged relative to the column centerline. For example, the positions and shapes of the third conductive layers in the Nth cell column and the N+1th cell column can be symmetrically arranged relative to the column centerline. In an exemplary embodiment, the positions and shapes of the third conductive layers in multiple circuit cells in a cell column can be substantially the same.

[0237] (17) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 14 .

[0238] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0239] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer in the twenty-first via hole V21 is removed, exposing the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the second connecting electrode 52 through the via hole.

[0240] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer in the twenty-second via hole V22 is removed, exposing the surface of the fifth connecting electrode 55, and the twenty-second via hole V22 is configured to connect the subsequently formed first power line to the fifth connecting electrode 55 through the via hole.

[0241] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer in the twenty-third via hole V23 is removed, exposing the surface of the fourth connecting electrode 54, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the fourth connecting electrode 54 through the via hole.

[0242] In an exemplary embodiment, at least one circuit unit may further include a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the data connection block 83 of the first data connection line 81 on the substrate. The first planar layer within the twenty-fourth via hole V24 is removed, exposing the surface of the data connection block 83. The twenty-fourth via hole V24 is configured to connect the subsequently formed second data connection line 82 to the data connection block 83 through the via hole.

[0243] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG15A and FIG15B , where FIG15B is a planar schematic diagram of the fourth conductive layer in FIG15A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0244] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a first power line 71 , a second power line 72 , a data signal line 73 , and an anode connection electrode 74 .

[0245] In an exemplary embodiment, the first power line 71 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 71 is connected to the fifth connection electrode 55 via the twenty-second via hole V22. Since the fifth connection electrode 55 is connected to the second electrode plate 32 via the via hole, and the second electrode plate 32 is connected to the first region of the fifth active layer via the plate connection electrode 35 and the third connection electrode 53, the first power line 71 can write the first power signal to the second electrode plate 32 and the first electrode of the fifth transistor T5.

[0246] In an exemplary embodiment, the first power line 71 may be a zigzag line with a variable width, and the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Because the first connection electrode 51 serves as the first node N1 of the pixel driving circuit, the first power line 71, which has a constant potential, can shield the first node N1, thereby preventing the impact of data voltage jumps on the first node N1, improving the operating stability of the pixel driving circuit and enhancing the display effect.

[0247] In an exemplary embodiment, the second power line 72 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. It may be disposed between the first power line 71 and the data signal line 73. The second power line 72 is configured to connect to the cathode of the light-emitting device. By disposing the second power line within the display area, the disclosed embodiment implements a VSS-in-pixel structure. This not only effectively reduces the resistance of the second power line, reduces the voltage drop of the second power signal, and effectively improves the uniformity of the second power signal within the display substrate, effectively improving display uniformity and display quality, but also significantly reduces the width of the frame power lead, significantly reducing the width of the left and right frame widths, and improving the screen-to-body ratio, which facilitates the realization of a full-screen display.

[0248] In an exemplary embodiment, the data signal line 73 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 73 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fourth active layer through the via hole, the data signal line 73 can write a data signal to the first electrode of the fourth transistor T4.

[0249] In an exemplary embodiment, the orthographic projection of the data signal line 73 on the substrate does not overlap with the orthographic projections of the channel regions of the first to seventh transistors T1 to T7 on the substrate, thereby avoiding signal crosstalk caused by data voltage jumps on the data signal line 73 and the influence of the data voltage jumps on the first to seventh transistors T1 to T7, thereby improving the operating stability of the pixel driving circuit and the display effect.

[0250] In an exemplary embodiment, the anode connection electrode 74 may be block-shaped (e.g., rectangular) and connected to the fourth connection electrode 54 via a twenty-third via hole V23. The anode connection electrode 74 is configured to be connected to a subsequently formed anode. Since the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the via hole, the pixel driving circuit can output a driving current to the light-emitting device.

[0251] In an exemplary embodiment, the fourth conductive layer of at least one circuit cell may further include a second data connection line 82. The second data connection line 82 may be in the form of a straight line or a zigzag line, with the main portion extending along the second direction Y, and may be arranged between adjacent cell columns. The second data connection line 82 may be connected to a data connection block 83 on the first connection sub-line 81-1 via a twenty-fourth via hole V24. The second data connection line 82 is configured to connect to the data lead lines in the binding area. Since the data connection block 83 is connected to the first connection sub-line 81-1 of the first data connection lines 81, the first connection sub-line 81-1 is configured to connect to the data signal lines in the display area, and the second data connection line 82 is configured to connect to the data lead lines in the binding area, interconnection is achieved between the first data connection line 81 extending along the first direction X and the second data connection line 82 extending along the second direction Y. The data lead lines in the binding area are connected to the data signal lines in the display area via the first and second data connection lines 81, 82.

[0252] In an exemplary embodiment, the second data connection line 82 can be arranged between the first power line 71 of the Nth unit column and the first power line 71 of the N+1th unit column. The first power line 71 with a constant potential can shield the influence of the data voltage jump of the second data connection line 82 on the key nodes of the pixel driving circuit, thereby improving the working stability of the pixel driving circuit and improving the display effect.

[0253] In an exemplary embodiment, a second break K2 may be provided on the second data link line 82 of at least one circuit unit. The second break K2 may cut off the second data link line 82 so that the second data link lines 82 on both sides of the second break K2 are insulated from each other.

[0254] In an exemplary embodiment, the second data connection line 82 may include a third connection sub-line 82-3 located on the second direction Y side of the second break K2 (the side close to the binding area) and a fourth connection sub-line 82-4 located on the opposite direction Y side of the second break K2 (the side away from the binding area). The third connection sub-line 82-3 is connected to the first connection sub-line 81-1 in the first data connection line 81 and is configured to be connected to the data lead-out line in the binding area. The fourth connection sub-line 82-4 is configured as a second virtual line.

[0255] In an exemplary embodiment, an orthographic projection of the second break K2 on the substrate at least partially overlaps with an orthographic projection of the second break blocking block 62 on the substrate.

[0256] In an exemplary embodiment, the orthographic projection of the second fracture K2 on the substrate can be located within the range of the orthographic projection of the second fracture blocking block 62 on the substrate, so that the second fracture blocking block 62 can block the second fracture K2 from below, which can not only effectively eliminate the difference in film layers in different areas, which is beneficial to eliminating shadows and avoiding poor appearance of the display substrate, but also can block the second fracture K2 from below, which is beneficial to improving transmittance.

[0257] In an exemplary embodiment, the fourth connecting sub-line 82-4 serving as the second dummy line may not be connected to any signal line, or may be connected to the first power line, or may be connected to the second power line, or may be connected to the first initial signal line, or may be connected to the second initial signal line, and the present disclosure is not limited thereto.

[0258] The subsequent preparation process may include forming a second flat layer, on which an anode via is provided, the anode via exposing the surface of the anode connection electrode, and the anode via is configured to connect a subsequently formed anode to the anode connection electrode through the via.

[0259] At this point, the drive structure layer of this embodiment is completed on the substrate. In a plane parallel to the display substrate, the drive structure layer may include multiple circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first initial signal line, a second initial signal line, a first power line, and a data signal line connected to the pixel drive circuit.

[0260] In a plane perpendicular to the display substrate, the driving structure layer may include a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer, which are sequentially arranged on the base. The shielding layer may include at least a shielding electrode, a plurality of shielding connecting strips, and a plurality of shielding blocks. The semiconductor layer may include at least an active layer of a plurality of transistors. The first conductive layer may include at least a first scanning signal line, a second scanning signal line, a third scanning signal line, and a first plate of a storage capacitor. The second conductive layer may include at least a first initial signal line, a second initial signal line, and a second plate of a storage capacitor. The third conductive layer may include at least a first luminous signal line, a second luminous signal line, a first data connection line, and a plurality of connection electrodes. The fourth conductive layer may include at least a first power line, a second power line, a data signal line, and a second data connection line.

[0261] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and one or more of textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0262] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or may be made of an alloy material composed of a metal such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure or a multilayer composite structure such as Ti / Al / Ti. The first planar layer and the second planar layer may be made of an organic material such as a resin or polyimide.

[0263] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer may be prepared on the driving structure layer, and an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0264] An exemplary embodiment of the present disclosure provides a display substrate, in which a first data connection line and a second data connection line are arranged in a display area, and a data lead line in a binding area is connected to a data signal line through the first data connection line and the second data connection line, so that a fan-shaped oblique line does not need to be arranged in the lead line area, thereby effectively reducing the length of the lead line area, greatly reducing the width of the lower frame, and improving the screen-to-body ratio, which is conducive to achieving full-screen display.

[0265] The embodiment of the present disclosure utilizes a first fracture blocking block to block the first fracture on the first data connection line from below, and the first fracture blocking block is connected to the first initial signal line, which not only effectively improves the transmittance, but also effectively eliminates the differences in film layers in different areas, is beneficial to eliminating shadows, avoids poor appearance of the display substrate, and improves the display quality.

[0266] The embodiment of the present disclosure utilizes a second fracture shielding block to shield the second fracture from below, and the second fracture shielding block is connected to the second initial signal line, which can not only further improve the transmittance, which is conducive to sensor recognition, but also further improve the display quality.

[0267] In the embodiment of the present disclosure, a first fracture shielding block is arranged to overlap with a first node of a pixel driving circuit to form a node capacitance, which can effectively stabilize the potential of the first node in the pixel driving circuit and improve the driving performance of the pixel driving circuit.

[0268] The embodiment of the present disclosure effectively reduces the resistance of the luminous signal lines and the voltage drop of the luminous signals by setting the first luminous signal line and the second luminous signal line in the first source-drain metal layer, thereby improving the quality of luminous control and display quality.

[0269] By adopting a mirror-symmetrical design, the embodiment of the present disclosure allows pixel driving circuits in adjacent circuit units to share the same connecting vias and connecting electrodes, effectively reducing the number of vias and electrodes, effectively reducing the space occupied by the pixel driving circuit, and facilitating improved resolution.

[0270] The disclosed embodiment realizes a VSS in pixel structure by setting a second power line in the display area. This not only effectively reduces the resistance of the second power line, reduces the voltage drop of the second power signal, effectively improves the uniformity of the second power signal in the display substrate, effectively improves the display uniformity, and improves the display quality, but also significantly reduces the width of the frame power lead, greatly reduces the width of the left and right frames, improves the screen-to-body ratio, and is conducive to achieving full-screen display.

[0271] The preparation process of the embodiment of the present disclosure is well compatible with the existing preparation process, and the process is simple to implement, easy to implement, high in production efficiency, low in production cost, and high in yield rate.

[0272] Figure 16 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, Figure 17A is a plan view of the second conductive layer in Figure 16, and Figure 17B is a plan view of the third conductive layer in Figure 16. As shown in Figures 16, 17A, and 17B, the display substrate structure of this embodiment is substantially the same as that shown in Figure 7, except that the positions of the first fracture shielding block 61 and the first fracture K1 are different.

[0273] In an exemplary embodiment, the structure of the second conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG. 7 , except that the first break shielding block 61 provided on the first initial signal line 41 can be provided between the Nth unit column and the N+1th unit column. The structure of the third conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG. 7 , except that the first break K1 on the first data connection line 81 can be provided between the Nth unit column and the N+1th unit column, and the orthographic projection of the first break K1 on the substrate at least partially overlaps with the orthographic projection of the first break shielding block 61 on the substrate.

[0274] In an exemplary embodiment, the orthographic projection of the first fracture K1 on the substrate can be located within the range of the orthographic projection of the first fracture blocking block 61 on the substrate, so that the first fracture blocking block 61 can block the first fracture K1 from below, which not only effectively improves the transmittance, but also effectively eliminates the differences in film layers in different areas, is conducive to eliminating shadows, avoids poor appearance of the display substrate, and improves the display quality.

[0275] In an exemplary embodiment, the first data connection line 81 may include a first connection sub-line 81-1 located on one side of the first break K1 in the opposite direction of the first direction X and a second connection sub-line 81-2 located on one side of the first break K1 in the first direction X. The first connection sub-line 81-1 may be provided with a data connection block (not shown). For example, if the first break K1 is provided between the Nth unit column and the N+1th unit column, the data connection block may be provided between the N-2th unit column and the N-1th unit column and configured to connect to a subsequently formed second data connection line located between the N-2th unit column and the N-1th unit column.

[0276] In an exemplary embodiment, the second conductive layer of at least one circuit unit may further include a second break blocking block (not shown), and at least one second data link line 82 may be provided with a second break (not shown). The orthographic projection of the second break on the substrate may be located within the orthographic projection of the second break blocking block on the substrate. For example, if the first break blocking block 61 and the first break K1 are provided in the Mth unit row, the second break blocking block and the second break may be provided in the M-1th unit row, where M may be a positive integer greater than or equal to 2.

[0277] This embodiment provides a display substrate, which not only has the technical effect of the display substrate shown in Figure 7, but also can improve the consistency of the pixel driving circuit structure in multiple circuit units and improve the process quality by setting the first fracture and the first fracture blocking block between the unit columns.

[0278] Figure 18 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, Figure 19A is a plan view schematic diagram of the second conductive layer in Figure 18, and Figure 19B is a plan view schematic diagram of the third conductive layer in Figure 18. As shown in Figures 18, 19A, and 19B, the display substrate structure of this embodiment is substantially the same as that shown in Figure 7, except that the positions of the first fracture shielding block 61 and the first fracture K1 are different.

[0279] In an exemplary embodiment, the structure of the second conductive layer of this embodiment is basically the same as that of the aforementioned embodiment, except that the first break blocking block 61 can be set on the side of the second initial signal line 42 close to the first scanning signal line 21, and the second break blocking block 62 can be set on the side of the first initial signal line 41 close to the second scanning signal line 22, and the first initial signal line 41 serves as the constant potential signal line of the present disclosure.

[0280] In the exemplary embodiment, a first end of the first break shielding block 61 is connected to a side of the second shielding electrode 44 close to the first scan signal line 21, and a second end of the first break shielding block 61 extends toward a side close to the first scan signal line 21. A first end of the second break shielding block 62 is connected to a side of the first initial signal line 41 close to the second scan signal line 22, and a second end of the second break shielding block 62 extends toward a side of the second scan signal line 22.

[0281] In an exemplary embodiment, the first break blocking block 61 may be disposed in the circuit unit of the (N+1)th unit column, and the second break blocking block 62 may be disposed between the (N)th unit column and the (N+1)th unit column.

[0282] In an exemplary embodiment, the second initial signal line 42 , the second shielding electrode 44 and the first break blocking block 61 may be an interconnected integral structure, and the first initial signal line 41 and the second break blocking block 62 may be an interconnected integral structure.

[0283] In an exemplary embodiment, the structure of the third conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG. 7 , except that the first data link line 81 may be located between the first scan signal line 21 and the second initial signal line 42 .

[0284] In an exemplary embodiment, at least one first break K1 may be provided in the circuit unit of the (N+1)th unit column, and an orthographic projection of the first break K1 on the substrate at least partially overlaps with an orthographic projection of the first break blocking block 61 on the substrate.

[0285] In an exemplary embodiment, the structure of the fourth conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG7 , and the second data connection line 82 can be arranged between the first power line 71 of the Nth unit column and the first power line 71 of the N+1th unit column, and the second data connection line 82 is connected to the data connection block 83 through a via, and the orthographic projection of the second break K2 on the second data connection line 82 on the substrate at least partially overlaps with the orthographic projection of the second break blocking block 62 on the substrate.

[0286] This embodiment provides a display substrate, which utilizes a first fracture blocking block and a second fracture blocking block to respectively block the first fracture from below, which not only effectively improves the transmittance, but also effectively eliminates the film layer differences in different areas, is conducive to eliminating shadows, avoids poor appearance of the display substrate, and improves the display quality.

[0287] Figure 20 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, Figure 21A is a plan view schematic diagram of the second conductive layer in Figure 20, and Figure 21B is a plan view schematic diagram of the third conductive layer in Figure 20. As shown in Figures 20, 21A, and 21B, the display substrate structure of this embodiment is substantially the same as that shown in Figure 18, except that the positions of the first fracture shielding block 61 and the first fracture K1 are different.

[0288] In an exemplary embodiment, the structure of the second conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG. 18 , except that the first break shielding block 61 provided on the second initial signal line 42 can be provided between the Nth unit column and the N+1th unit column. The structure of the third conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG. 18 , except that the first break K1 on the first data connection line 81 can be provided between the Nth unit column and the N+1th unit column, and the orthographic projection of the first break K1 on the substrate at least partially overlaps with the orthographic projection of the first break shielding block 61 on the substrate.

[0289] In an exemplary embodiment, the orthographic projection of the first fracture K1 on the substrate can be located within the range of the orthographic projection of the first fracture blocking block 61 on the substrate, so that the first fracture blocking block 61 can block the first fracture K1 from below, which not only effectively improves the transmittance, but also effectively eliminates the differences in film layers in different areas, is conducive to eliminating shadows, avoids poor appearance of the display substrate, and improves the display quality.

[0290] In an exemplary embodiment, the first data connection line 81 may include a first connection sub-line 81-1 located on one side of the first break K1 in the opposite direction of the first direction X and a second connection sub-line 81-2 located on one side of the first break K1 in the first direction X. The first connection sub-line 81-1 may be provided with a data connection block (not shown). For example, if the first break K1 is provided between the Nth unit column and the N+1th unit column, the data connection block may be provided between the N-2th unit column and the N-1th unit column and configured to connect to a subsequently formed second data connection line located between the N-2th unit column and the N-1th unit column.

[0291] In an exemplary embodiment, the second conductive layer of at least one circuit unit may further include a second break blocking block (not shown), and at least one second data link line 82 may be provided with a second break (not shown). The orthographic projection of the second break on the substrate may be located within the orthographic projection of the second break blocking block on the substrate. For example, if the first break blocking block 61 and the first break K1 are provided in the Mth unit row, the second break blocking block and the second break may be provided in the M-1th unit row, where M may be a positive integer greater than or equal to 2.

[0292] This embodiment provides a display substrate, which not only has the technical effect of the display substrate shown in Figure 18, but also can improve the consistency of the pixel driving circuit structure in multiple circuit units and improve the process quality by setting the first fracture and the first fracture blocking block between the unit columns.

[0293] Figure 22 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 23 is a plan view of the fourth conductive layer in Figure 22. As shown in Figures 22 and 23, the display substrate structure of this embodiment is substantially the same as that shown in Figure 7, except that the first fracture blocking block 61 and the third fracture blocking block 63 serve as the fracture blocking structure of the present disclosure. The first fracture blocking block 61 blocks the first fracture K1 from below, and the third fracture blocking block 63 blocks the first fracture K1 from above.

[0294] In this exemplary embodiment, the structures of the second and third conductive layers of this embodiment are substantially the same as those of the embodiment shown in FIG. 7 , except that the orthographic projection of the first break blocking block 61 on the substrate at least partially overlaps with the orthographic projection of the first region of the first active layer on the substrate. That is, in the first direction X, the position of the first break blocking block 61 is adjusted from the location of the second region of the first active layer to the location of the first region of the first active layer. The first break K1 on the first data link line 81 is adjusted to the location of the first break blocking block 61, and the orthographic projection of the first break K1 on the substrate is within the range of the orthographic projection of the first break blocking block 61 on the substrate.

[0295] In an exemplary embodiment, the structure of the fourth conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG. 7 , except that a third break shielding block 63 is provided on the second power line 72 of at least one circuit unit.

[0296] In an exemplary embodiment, the third break shielding block 63 can be block-shaped (e.g., rectangular) and can be disposed on a side of the second power line 72 that is proximate to the first power line 71. A first end of the third break shielding block 63 is connected to a side of the second power line 72 that is proximate to the first power line 71, and a second end of the third break shielding block 63 extends toward the first power line 71. The orthographic projection of the third break shielding block 63 on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate.

[0297] In an exemplary embodiment, the orthographic projection of the first break K1 on the substrate can be located within the range of the orthographic projections of the second power line 72 and the third break blocking block 63 on the substrate, so that the second power line 72 and the third break blocking block 63 can block the first break K1 from above, which is conducive to eliminating shadows and avoiding poor appearance of the display substrate.

[0298] In an exemplary embodiment, the first initial signal line 41 and the second power line 72 serve as constant potential signal lines of the present disclosure. The first break shielding block 61 is connected to the first initial signal line 41 , and the third break shielding block 63 is connected to the second power line 72 .

[0299] This embodiment provides a display substrate, which not only has the technical effects of the display substrate shown in Figure 7, but also provides a third fracture shielding block 63 on the second power line 72, so that there are shielding blocks above and below the first fracture K1 to shield the first fracture K1, which can further eliminate the difference in film layers in different areas, is conducive to eliminating shadows, and further avoids the poor appearance of the display substrate.

[0300] Figure 24 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 24, the display substrate structure of this embodiment is substantially the same as that shown in Figure 22, except that the third break shielding block 63 shields the first break K1 from above, and no first break shielding block is provided below the first break K1.

[0301] In an exemplary embodiment, the structures of the second conductive layer, the third conductive layer and the fourth conductive layer of this embodiment are basically the same as those of the embodiment shown in Figure 22, except that the first fracture shielding block is not set on the first initial signal line 41 in the second conductive layer, the third fracture shielding block 63 serves as the fracture shielding structure of the present disclosure, and the second power line 72 serves as the constant potential signal line of the present disclosure.

[0302] This embodiment provides a display substrate. By setting a third fracture blocking block 63 on the second power line 72, the third fracture blocking block 63 can block the first fracture K1 from above, which is beneficial to eliminating shadows and avoiding poor appearance of the display substrate. At the same time, it simplifies the structure of the second conductive layer, which is beneficial to improving the transmittance.

[0303] Figure 25 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 26 is a plan view schematic diagram of the fourth conductive layer in Figure 25. As shown in Figures 25 and 26, the display substrate structure of this embodiment is substantially the same as that shown in Figure 7, except that the first fracture shielding block 61 and the third fracture shielding block 63 serve as the fracture shielding structure of the present disclosure. The first fracture shielding block 61 shields the first fracture K1 from below, and the third fracture shielding block 63 shields the first fracture K1 from above.

[0304] In an exemplary embodiment, the structures of the second conductive layer, the third conductive layer and the fourth conductive layer of this embodiment are substantially the same as those of the embodiment shown in FIG. 7 , except that a third fracture shielding block 63 is provided on the first power line 71 of at least one circuit unit.

[0305] In an exemplary embodiment, the third break shielding block 63 can be block-shaped (e.g., rectangular) and can be disposed on a side of the first power line 71 that is adjacent to the second power line 72. A first end of the third break shielding block 63 is connected to a side of the first power line 71 that is adjacent to the second power line 72, and a second end of the third break shielding block 63 extends toward the second power line 72. The orthographic projection of the third break shielding block 63 on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate.

[0306] In an exemplary embodiment, the orthographic projection of the first break K1 on the substrate can be located within the range of the orthographic projections of the first power line 71 and the third break blocking block 63 on the substrate, so that the first power line 71 and the third break blocking block 63 can block the first break K1 from above, which is conducive to eliminating shadows and avoiding poor appearance of the display substrate.

[0307] In an exemplary embodiment, the first initial signal line 41 and the first power line 71 serve as constant potential signal lines of the present disclosure. The first break shielding block 61 is connected to the first initial signal line 41 , and the third break shielding block 63 is connected to the first power line 71 .

[0308] This embodiment provides a display substrate, which not only has the technical effects of the display substrate shown in Figure 7, but also provides a third fracture shielding block 63 on the first power line 71, so that there are shielding blocks above and below the first fracture K1 to shield the first fracture K1, which can further eliminate the difference in film layers in different areas, is conducive to eliminating shadows, and further avoids the poor appearance of the display substrate.

[0309] Figure 27 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 27, the display substrate structure of this embodiment is substantially the same as that shown in Figure 25, except that the third fracture shielding block 63 shields the first fracture K1 from above, and no first fracture shielding block is provided below the first fracture K1.

[0310] In an exemplary embodiment, the structures of the second conductive layer, the third conductive layer and the fourth conductive layer of this embodiment are basically the same as those of the embodiment shown in Figure 25, except that the first fracture shielding block is not set on the first initial signal line 41 in the second conductive layer, the third fracture shielding block 63 serves as the fracture shielding structure of the present disclosure, and the first power line 71 serves as the constant potential signal line of the present disclosure.

[0311] This embodiment provides a display substrate. By setting a third fracture blocking block 63 on the first power line 71, the third fracture blocking block 63 can block the first fracture K1 from above, which is beneficial to eliminating shadows and avoiding poor appearance of the display substrate. At the same time, it simplifies the structure of the second conductive layer, which is beneficial to improving the transmittance.

[0312] FIG28 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure. As shown in FIG28 , the display substrate structure of this embodiment is substantially the same as that shown in FIG7 , except that, whereas the first data connection line 81 in the embodiment of FIG7 is located between the second scan signal line 22 and the first initial signal line 41 , the first data connection line 81 in this embodiment is located on the side of the first initial signal line 41 away from the second scan signal line 22 .

[0313] In an exemplary embodiment, the structure of the second conductive layer of this embodiment is basically the same as that of the embodiment shown in Figure 7, except that the position of the first initial signal line 41 is close to the second scanning signal line 22 and away from the third scanning signal line 23, that is, relative to the embodiment of Figure 7, the position of the first initial signal line 41 of this embodiment is moved up.

[0314] In an exemplary embodiment, the distance between the first initial signal line 41 and the second scanning signal line 22 in this embodiment is smaller than the distance between the first initial signal line 41 and the second scanning signal line 22 in the embodiment of Figure 7 , the extension length of the first initial connection block 41-1 in the second direction Y in this embodiment is greater than the extension length of the first initial connection block 41-1 in the second direction Y in the embodiment of Figure 7 , and no first fracture blocking block is set on the first initial signal line 41.

[0315] In an exemplary embodiment, the structure of the third conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG7 , except that the first data link line 81 may be located between the third scanning signal line 23 and the first initial signal line 41 , that is, the first data link line 81 is located on a side of the first initial signal line 41 away from the second scanning signal line 22 . Relative to the embodiment of FIG7 , the position of the first data link line 81 of this embodiment is moved downward.

[0316] In an exemplary embodiment, the orthographic projection of the first data connection line 81 in the embodiment of FIG. 7 does not overlap with the orthographic projection of the first initial connection block 41 - 1 on the substrate. In this embodiment, the orthographic projection of the first data connection line 81 on the substrate at least partially overlaps with the orthographic projection of the first initial connection block 41 - 1 on the substrate.

[0317] In the exemplary embodiment, the structure of the fourth conductive layer of this embodiment is substantially the same as that of the embodiment shown in FIG7 . Because the first power line 71 is a zigzag line of variable width, the position of the first data connection line 81 is shifted downward, so that the first break K1 corresponds to the position of the first power line 71 with the largest width. The first power line 71 serves as both the break shielding structure of the present disclosure and the constant potential signal line of the present disclosure. The orthographic projection of the first break K1 on the substrate can be located within the range of the orthographic projection of the first power line 71 on the substrate.

[0318] This embodiment provides a display substrate. By adjusting the positions of the first initial signal line 41 and the first data connection line 81, the first break K1 corresponds to the position with the larger width in the first power line 71. The first power line 71 serves as both the break shielding structure of the present disclosure and the constant potential signal line of the present disclosure. The first power line 71 can shield the first break K1 from above, which is beneficial to eliminating shadows and avoiding poor appearance of the display substrate. There is no need to additionally widen the first power line 71, which will not affect the transmittance. The structure of the second conductive layer can be simplified, which is beneficial to improving the transmittance.

[0319] In some possible implementations, the embodiment shown in FIG28 may be expanded accordingly. For example, a first break shielding block may be provided in the second conductive layer, and the first break shielding block may be provided on a side of the first initial signal line 41 close to the third scanning signal line 23, with the orthographic projection of the first break K1 on the substrate being within the range of the orthographic projection of the first break shielding block on the substrate. This is not limited in the present disclosure.

[0320] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. For example, in multiple embodiments, the first fracture shielding block can be set in the first conductive layer, and the first fracture shielding block shields the first fracture from below. For another example, in multiple embodiments, the second fracture shielding block can be set in the first conductive layer or the third conductive layer, and the second fracture shielding block shields the second fracture from below. The present disclosure does not limit this.

[0321] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0322] The present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units, at least one first data connection line extending along a first direction, and at least one second data connection line extending along a second direction, wherein the first direction and the second direction intersect; at least one circuit unit includes a pixel driving circuit, a data signal line, and at least one constant potential signal line, wherein the data signal line is configured to provide a data signal to the pixel driving circuit, the constant potential signal line is configured to provide a constant potential signal to the pixel driving circuit, the data signal line is connected to the first data connection line, and the first data connection line is connected to the second data connection line; at least one circuit unit also includes at least one first break and at least one break shielding structure, wherein the first break is provided on the first data connection line and cuts off the first data connection line, and the break shielding structure is connected to the constant potential signal line; the preparation method may include:

[0323] Multiple conductive layers are formed on the substrate, the first data connection line is arranged in a conductive layer, and the fracture shielding structure is arranged in any one conductive layer or multiple conductive layers other than the conductive layer where the first data connection line is located, and the orthographic projection of the first fracture on the substrate and the orthographic projection of the fracture shielding structure on the substrate at least partially overlap.

[0324] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0325] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising, in a direction parallel to the display substrate, a plurality of circuit units, at least one first data connection line extending along a first direction, and at least one second data connection line extending along a second direction, wherein the first direction and the second direction intersect; at least one circuit unit comprising a pixel driving circuit, a data signal line, and at least one constant potential signal line, wherein the data signal line is configured to provide a data signal to the pixel driving circuit, the constant potential signal line is configured to provide a constant potential signal to the pixel driving circuit, the data signal line is connected to the first data connection line, and the first data connection line is connected to the second data connection line. connection; at least one circuit unit also includes at least one first break and at least one break shielding structure, the first break is arranged on the first data connection line and cuts off the first data connection line, and the break shielding structure is connected to the constant potential signal line; in a direction perpendicular to the display substrate, the display substrate at least includes a plurality of conductive layers arranged on a base, the first data connection line is arranged in a conductive layer, and the break shielding structure is arranged in any one conductive layer or multiple conductive layers other than the conductive layer where the first data connection line is located; the orthographic projection of the first break on the base at least partially overlaps with the orthographic projection of the break shielding structure on the base.

2. The display substrate according to claim 1, wherein At least one fracture shielding structure includes a first fracture shielding block, the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the first fracture shielding block on the substrate, and the first fracture shielding block is arranged in the conductive layer where the first data connection line is located, close to the side of the substrate.

3. The display substrate according to claim 2, wherein: The multiple conductive layers include at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the first data connection line is arranged in the third conductive layer, and the first fracture shielding block is arranged in the first conductive layer and / or the second conductive layer.

4. The display substrate according to claim 2, wherein: At least one constant potential signal line includes a first initial signal line, and the pixel driving circuit includes at least a first transistor and a second transistor, the gate electrode of the first transistor is connected to the second scanning signal line, the first pole of the first transistor is connected to the first initial signal line, the gate electrode of the second transistor is connected to the third scanning signal line, and the first pole of the second transistor is connected to the second pole of the first transistor; in at least one circuit unit, the first initial signal line is arranged between the second scanning signal line and the third scanning signal line, and the first fracture shielding block is connected to the first initial signal line.

5. The display substrate according to claim 4, wherein: In at least one circuit unit, the first data connection line is arranged between the second scanning signal line and the first initial signal line, and the first break shielding block is arranged on a side of the first initial signal line close to the second scanning signal line.

6. The display substrate according to claim 4, wherein: The first transistor includes at least a first active layer, the second transistor includes at least a second active layer, the second region of the first active layer is connected to the first region of the second active layer, and in at least one circuit unit, the orthographic projection of the first fracture blocking block on the substrate at least partially overlaps with the orthographic projection of the second region of the first active layer on the substrate.

7. The display substrate according to claim 2, wherein: At least one constant potential signal line includes a second initial signal line, and the pixel driving circuit includes at least a third transistor and a seventh transistor as driving transistors, the gate electrode of the seventh transistor is connected to the first scanning signal line, and the first electrode of the seventh transistor is connected to the second initial signal line; in at least one circuit unit, the second initial signal line is arranged on the side of the first scanning signal line away from the third transistor, and the first fracture blocking block is connected to the second initial signal line.

8. The display substrate according to claim 7, wherein: In at least one circuit unit, the first data connection line is arranged between the first scanning signal line and the second initial signal line, and the first break shielding block is arranged on a side of the second initial signal line close to the first scanning signal line.

9. The display substrate according to claim 2, wherein: At least one first break is provided between circuit units adjacent to each other in the first direction, and at least one first break blocking block is provided between circuit units adjacent to each other in the first direction.

10. The display substrate according to claim 1, wherein At least one circuit unit also includes at least one second break and at least one second break blocking block, the second break is arranged on the second data connection line and cuts off the second data connection line, and the orthographic projection of the second break on the substrate at least partially overlaps with the orthographic projection of the second break blocking block on the substrate.

11. The display substrate according to claim 10, wherein: The multiple conductive layers include at least a first conductive layer arranged on a substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the second data connection line is arranged in the fourth conductive layer, and the second fracture shielding block is arranged in any one conductive layer or multiple conductive layers among the first conductive layer, the second conductive layer and the third conductive layer.

12. The display substrate according to claim 10, wherein: At least one constant potential signal line includes a first initial signal line, which is configured to provide a first initial signal to the pixel driving circuit. In at least one circuit unit, the second break shielding block is connected to the first initial signal line.

13. The display substrate according to claim 10, wherein: At least one constant potential signal line includes a second initial signal line, which is configured to provide a second initial signal to the pixel driving circuit. In at least one circuit unit, the second break shielding block is connected to the second initial signal line.

14. The display substrate according to claim 10, wherein: At least one second break is provided between circuit units adjacent to each other in the first direction, and at least one second break blocking block is provided between circuit units adjacent to each other in the first direction.

15. The display substrate according to any one of claims 1 to 14, wherein: At least one fracture shielding structure includes a third fracture shielding block, the orthographic projection of the first fracture on the substrate at least partially overlaps with the orthographic projection of the third fracture shielding block on the substrate, and the third fracture shielding block is arranged in the conductive layer on the side of the conductive layer where the first data connection line is located away from the substrate.

16. The display substrate according to claim 15, wherein: The multiple conductive layers include at least a first conductive layer arranged on a substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the first data connection line is arranged in the third conductive layer, and the third fracture blocking block is arranged in the fourth conductive layer.

17. The display substrate according to claim 15, wherein: At least one constant potential signal line includes a first power line, and the first power line is configured to provide a first power signal to the pixel driving circuit; in at least one circuit unit, the third break shielding block is connected to the first power line.

18. The display substrate according to claim 15, wherein: At least one constant potential signal line includes a second power line, and the second power line is configured to provide a second power signal to the light-emitting device; in at least one circuit unit, the third break blocking block is connected to the second power line.

19. The display substrate according to claim 1, wherein At least one circuit unit also includes a first power line, which is configured to provide a first power signal to the pixel driving circuit, and the first power line simultaneously serves as the break shielding structure and the constant potential signal line; the orthographic projection of the first break on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and the first power line is arranged in a conductive layer on the side of the conductive layer where the first data connection line is located away from the substrate.

20. The display substrate according to claim 19, wherein: The pixel driving circuit includes at least a first transistor and a second transistor, wherein a gate electrode of the first transistor is connected to a second scanning signal line, a first electrode of the first transistor is connected to a first initial signal line, a gate electrode of the second transistor is connected to a third scanning signal line, and a first electrode of the second transistor is connected to a second electrode of the first transistor; In at least one circuit unit, the first initial signal line is arranged between the second scanning signal line and the third scanning signal line, and the first data connection line is arranged between the first initial signal line and the third scanning signal line.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

22. A method for preparing a display substrate, the display substrate comprising a plurality of circuit units, at least one first data connection line extending along a first direction, and at least one second data connection line extending along a second direction, the first direction and the second direction intersecting; at least one circuit unit comprising a pixel driving circuit, a data signal line, and a constant potential signal line, the data signal line being configured to provide a data signal to the pixel driving circuit, the constant potential signal line being configured to provide a constant potential signal to the pixel driving circuit, the data signal line being connected to the first data connection line, and the first data connection line being connected to the second data connection line; at least one circuit unit further comprising at least one first break and at least one break shielding structure, the first break being provided on the first data connection line and truncating the first data connection line, the break shielding structure being connected to the constant potential signal line; the preparation method comprising: Multiple conductive layers are formed on the substrate, the first data connection line is arranged in a conductive layer, and the fracture shielding structure is arranged in any one conductive layer or multiple conductive layers other than the conductive layer where the first data connection line is located, and the orthographic projection of the first fracture on the substrate and the orthographic projection of the fracture shielding structure on the substrate at least partially overlap.

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