Phase synchronization circuit and semiconductor integrated circuit

Abstract

The present invention makes it possible to optimize the pulse width of an injection pulse while suppressing an increase in circuit scale.　This phase synchronization circuit is provided with: an injection lock unit that resets an oscillation output on the basis of an injection pulse; and a calibration unit that calibrates the pulse width of the injection pulse on the basis of the pulse width of the injection pulse and frequency information of the oscillation output. The calibration unit may calibrate the pulse width of the injection pulse on the basis of a comparison result between a first voltage generated on the basis of the pulse width of the injection pulse and a second voltage generated on the basis of a ratio relative to the period of the oscillation output.

Description

Phase locked loop circuit and semiconductor integrated circuit

[0001] The present technology relates to a phase locked loop circuit and a semiconductor integrated circuit. More specifically, the present technology relates to a phase locked loop circuit and a semiconductor integrated circuit capable of injection locking.

[0002] In a phase-locked loop, injection locking is sometimes used to reset the accumulated jitter of the oscillation output. In this case, the pulse width of the injection pulse is optimized to ensure that the injection locking is effective. For example, a phase-locked loop that calibrates the pulse width of the injection pulse based on a current comparison has been disclosed (see, for example, Non-Patent Document 1).

[0003] C. -L. Wei, T. -K. Kuan and S. -I. Liu, "A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 6, pp. 548-552, June 2015, doi: 10.1109 / TCSII.2015.2407753.

[0004] However, in the above-mentioned conventional technology, it is necessary to incorporate a plurality of current sources that generate currents corresponding to the multiplication factor of the PLL (Phase Locked Loop), which may lead to an increase in the scale of the circuit.

[0005] This technology was developed in light of these circumstances, and aims to enable optimization of the pulse width of the injection pulse while suppressing an increase in circuit size.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a phase-locked loop circuit including an injection lock unit that resets an oscillation output based on an injection pulse, and a calibration unit that calibrates the pulse width of the injection pulse based on information about the pulse width of the injection pulse and the frequency of the oscillation output, thereby providing an effect that the pulse width of the injection pulse is calibrated to be optimized based on the frequency of the oscillation output.

[0007] In the first aspect, the calibration unit may calibrate the pulse width of the injection pulse based on a comparison result between a first voltage generated based on the pulse width of the injection pulse and a second voltage generated based on a ratio to the period of the oscillation output, thereby achieving an effect that the pulse width of the injection pulse optimized according to the frequency of the oscillation output is set based on the ratio to the period of the oscillation output.

[0008] In addition, in the first aspect, the calibration circuit may further include a pulse generating unit that generates an injection pulse whose pulse width is set based on a code and whose amplitude is set based on a power supply voltage, and the calibration unit may include a comparator that compares the first voltage with the second voltage, and a code searching unit that searches for the code based on a comparison result by the comparator and outputs the code to the pulse generating unit. This brings about an effect that the pulse width of the injection pulse is optimized based on the voltage comparison result.

[0009] In the first aspect, the code search unit may search for a current code based on a previously searched code and an output of the comparator, thereby providing an effect that the pulse width of the injection pulse is changed based on the output of one comparator.

[0010] In addition, in the first aspect, the power supply voltage regulator may further include a low-pass filter that smooths the injection pulse generated by the pulse generating unit to generate a DC voltage and outputs the DC voltage as the first voltage, a first conversion unit that converts the level of the power supply voltage based on the reciprocal of a value obtained by dividing the period of the injection pulse by the period of the oscillation output, and a second conversion unit that converts a result of the conversion by the first conversion unit to a level corresponding to the proportion and outputs the level as the second voltage. This provides the effect of optimizing the pulse width of the injection pulse while canceling the effect of fluctuations in the amplitude of the injection pulse due to fluctuations in the power supply voltage.

[0011] In the first aspect, the power supply voltage regulator may further include a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generator, a first converter that converts the level of the DC voltage based on a value obtained by dividing the period of the injection pulse by the period of the oscillation output and outputs the converted value as the first voltage, and a second converter that converts the level of the power supply voltage to a level corresponding to the proportion and outputs the converted value as the second voltage. This provides the effect of optimizing the pulse width of the injection pulse while preventing the second voltage input to the comparator from being reduced in level.

[0012] In the first aspect, the power supply voltage regulator may further include a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generator, a first converter that converts the level of the DC voltage based on frequency multiplication information and outputs the converted DC voltage as the first voltage, a second converter that converts the level of the power supply voltage to a level corresponding to the percentage, and a third converter that converts a result of the conversion by the second converter based on the frequency multiplication information and outputs the converted DC voltage as the second voltage. This provides the effect of optimizing the pulse width of the injection pulse while preventing the second voltage input to the comparator from being reduced in level.

[0013] In the first aspect, the frequency multiplication information may be a value obtained by dividing the period of the injection pulse by the period of the oscillation output. This brings about an effect that level conversion of the power supply voltage is realized based on the frequency multiplication information.

[0014] In the first aspect, each of the first conversion unit and the second conversion unit may include at least one of a ladder resistor and an inverting amplifier, thereby achieving voltage level conversion while suppressing an increase in circuit size.

[0015] In addition, in the first aspect, the injection lock unit may include a switch that sets the oscillation output to ground potential based on the injection pulse, thereby providing an effect that the accumulation of jitter in the oscillation output is reset based on the injection pulse.

[0016] A second aspect of the present invention is a semiconductor integrated circuit including an injection lock unit formed on a semiconductor chip and configured to reset an oscillation output based on an injection pulse, and a calibration unit formed on the semiconductor chip and configured to calibrate the pulse width of the injection pulse based on information about the pulse width of the injection pulse and the frequency of the oscillation output, thereby providing the effect of calibrating the pulse width of the injection pulse so as to be optimized according to the frequency of the oscillation output.

[0017] 1 is a block diagram showing an example of a configuration of a phase locked loop circuit according to a first embodiment; FIG. 2 is a block diagram showing an example of a configuration of a calibration unit according to the first embodiment; FIG. 3 is a timing chart showing a relationship between a clock signal and a pulse signal of the phase locked loop circuit according to the first embodiment; FIG. 4 is a diagram showing a first example of an oscillation circuit according to the first embodiment; FIG. 5 is a diagram showing a second example of an oscillation circuit according to the first embodiment; FIG. 6 is a diagram showing a third example of an oscillation circuit according to the first embodiment; FIG. 7 is a diagram showing a first example of a conversion unit applied to the calibration unit according to the first embodiment; FIG. 8 is a diagram showing a second example of a conversion unit applied to the calibration unit according to the first embodiment; FIG. 9 is a diagram showing a third example of a conversion unit applied to the calibration unit according to the first embodiment; FIG. 10 is a diagram showing a fifth example of a conversion unit applied to the calibration unit according to the first embodiment; FIG. 11 is a diagram showing a sixth example of a conversion unit applied to the calibration unit according to the first embodiment; FIG. 12 is a diagram showing a seventh example of a conversion unit applied to the calibration unit according to the first embodiment; FIG. 13 is a flowchart showing a first example of an update process of a pulse width setting code according to the first embodiment; FIG. 14 is a flowchart showing a second example of an update process of a pulse width setting code according to the first embodiment; FIG. 15 is a block diagram showing an example of a configuration of a calibration unit according to the third embodiment; Fig. 10 is a block diagram showing a configuration example of an imaging device to which a phase locked loop circuit according to a fourth embodiment is applied. Fig. 11 is a block diagram showing a configuration example of a solid-state imaging device according to a fourth embodiment. Fig. 12 is a perspective view showing an example of stacking of pixel array units according to a fifth embodiment. Fig. 13 is a block diagram showing a schematic configuration example of a vehicle control system. Fig. 14 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0018] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which conversion based on the ratio to the period of the oscillation output is performed on the input side of the power supply voltage) 2. Second embodiment (an example in which conversion based on the ratio to the period of the oscillation output is performed on the input side of the injection pulse) 3. Third embodiment (an example in which conversion based on the numerator of the ratio to the period of the oscillation output is performed on the input side of the injection pulse, and conversion based on the denominator of the ratio to the period of the oscillation output is performed on the input side of the power supply voltage) 4. Fourth embodiment (an example in which a phase-locked loop is applied to an imaging device) 5. Fifth embodiment (an example in which pixel array units are stacked) 6. Example of application to a moving body

[0019] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of a phase locked loop circuit according to a first embodiment.

[0020] In the figure, a phase locked loop (PLL) generates a clock signal CLK based on a PLL (Phase Locked Loop), which can use injection locking to reset the accumulated jitter of the oscillation output.

[0021] The phase locked loop includes a frequency control section 100, an oscillation circuit 103, a pulse generation section 105, a calibration section 106, and an injection section 107. The frequency control section 100, the oscillation circuit 103, the pulse generation section 105, the calibration section 106, and the injection section 107 may be configured as a semiconductor integrated circuit formed on a semiconductor chip.

[0022] The oscillation circuit 103 generates a clock signal CLK based on the oscillation operation. At this time, the clock signal CLK generated by the oscillation circuit 103 is fed back to the phase comparator 101.

[0023] The frequency control unit 100 controls the oscillation frequency of the oscillation circuit 103 based on the reference clock REF and the frequency multiplication information FCW. The frequency control unit 100 includes a phase comparator 101 and a loop filter .

[0024] The phase comparator 101 compares the phase of the reference clock REF with the phase of the clock signal CLK and controls the oscillation frequency of the oscillator circuit 103 so that the phases of the reference clock REF and the clock signal CLK coincide. At this time, the phase comparator 101 can set the frequency of the clock signal CLK based on the frequency multiplication information FCW so that the frequency of the reference clock REF is multiplied. The frequency multiplication information FCW can be set to a value obtained by dividing the period of the injection pulse PLS by the period of the clock signal CLK.

[0025] The loop filter 102 applies a control signal corresponding to the differential signal output from the phase comparator 101 to the oscillation circuit 103 .

[0026] The pulse generating unit 105 generates an injection pulse PLS and outputs it to the calibration unit 106 and the injection unit 107. At this time, the pulse generating unit 105 can set the pulse width TS of the injection pulse PLS based on the pulse width setting code COD. The pulse generating unit 105 can also set the amplitude AM of the injection pulse PLS based on the power supply voltage VDD. At this time, the power supply for the pulse generating unit 105 can be supplied from the power supply voltage VDD.

[0027] The calibration unit 106 can calibrate the pulse width TS of the injection pulse PLS based on the pulse width TS of the injection pulse PLS and frequency information of the clock signal CLK. The frequency information of the clock signal CLK may include frequency multiplication information FCW or frequency information of the reference clock REF. For example, the calibration unit 106 may calibrate the pulse width TS of the injection pulse PLS based on a comparison result between a voltage generated based on the pulse width TS of the injection pulse PLS and a voltage generated based on a ratio to the period of the clock signal CLK. This calibration can optimize the pulse width TS of the injection pulse PLS so that the injection lock of the oscillation circuit 103 operates effectively.

[0028] The injection unit 107 resets the oscillation output of the oscillation circuit 103 based on the injection pulse PLS. The reset of the oscillation output of the oscillation circuit 103 may involve setting the output node of the clock signal CLK to a fixed potential. The injection unit 107 includes a switch 104.

[0029] The switch 104 switches between on and off based on the injection pulse PLS. When the switch 104 is turned on, the oscillation output of the oscillation circuit 103 can be reset.

[0030] FIG. 2 is a block diagram illustrating an example of the configuration of the calibration unit according to the first embodiment.

[0031] In the figure, the calibration section 106 includes a low-pass filter 111 , conversion sections 112 and 113 , a comparator 114 , and a code search section 115 .

[0032] The low-pass filter 111 generates a DC voltage by smoothing the injection pulse PLS generated by the pulse generating unit 105, and outputs the DC voltage to the comparator 114 as a detection voltage VP.

[0033] The conversion unit 112 converts the level of the power supply voltage VDD based on the reciprocal of the value obtained by dividing the period of the injection pulse PLS by the period of the clock signal CLK, and outputs the converted level to the conversion unit 113. The reciprocal of the value obtained by dividing the period of the injection pulse PLS by the period of the clock signal CLK can be set to 1 / FCW. In this case, the output level of the conversion unit 112 can be set to 1 / FCW of the level of the power supply voltage VDD.

[0034] Conversion unit 113 converts the conversion result from conversion unit 112 to a level corresponding to a ratio RA relative to the period of clock signal CLK, and outputs the result as reference voltage VR to comparator 114. The ratio RA relative to the period of clock signal CLK can be set to y / x. In this case, the output level of conversion unit 113 can be set to y / x, which is the output level of conversion unit 112. x and y may be integers.

[0035] The converters 112 and 113 can be configured with an integer multiplication circuit, a fractional multiplication circuit, or a combination thereof. The integer multiplication circuit or fractional multiplication circuit can be configured with a non-inverting amplifier circuit, a ladder resistor, or a combination thereof.

[0036] The comparator 114 compares the detection voltage VP output from the low-pass filter 111 with the reference voltage VR output from the conversion unit 113 , and outputs the comparison result to the code search unit 115 .

[0037] The code search unit 115 registers the pulse width setting code COD. The pulse width setting code COD specifies the pulse width TS of the injection pulse PLS. The pulse width TS of the injection pulse PLS may be set, for example, in tens or hundreds of stages. At this time, the code search unit 115 can search for the current pulse width setting code COD based on the previously searched pulse width setting code COD and the output of the comparator 114, and output the current pulse width setting code COD to the pulse generation unit 105. The search for the pulse width setting code COD may be a binary search.

[0038] FIG. 3 is a timing chart showing the relationship between the clock signal and the pulse signal of the phase locked loop circuit according to the first embodiment.

[0039] In the figure, the clock signal CLK is generated by multiplying the reference clock REF based on the frequency multiplication information FCW. Here, the period TK of the clock signal CLK can be given by TK=TR / FCW, where TR is the period of the reference clock REF. Furthermore, if the amplitudes of the reference clock REF and the clock signal CLK are equal to the power supply voltage VDD, the smoothed DC levels of the reference clock REF and the clock signal CLK can be given by VDD / 2.

[0040] In the case of a synchronizing pulse PLK having a period equal to the period TK of the clock signal CLK, the DC level of the smoothed synchronizing pulse PLK can be given by VDD / FCW. In this case, the output level of the conversion unit 112 is equal to the DC level of the synchronizing pulse PLK.

[0041] The pulse width TS of the injection pulse PLS is set to y / x of the period TK of the same period pulse PLK. Here, the DC level of the smoothed injection pulse PLS can be given by VDD / FCW·y / x. At this time, the output level of the conversion unit 113 is equal to y / x of the DC level of the same period pulse PLK.

[0042] The comparator 114 compares the DC level of the smoothed injection pulse PLS with the output level of the conversion unit 113. Therefore, the pulse width TS of the injection pulse PLS can be set so that the DC level of the smoothed injection pulse PLS coincides with VDD / FCW·y / x, and the pulse width TS of the injection pulse PLS can be adjusted based on the values ​​of x and y.

[0043] 4 is a diagram showing a first example of an oscillator circuit according to the first embodiment, in which a ring oscillator 103A is used in the oscillator circuit 103.

[0044] In the figure, a ring oscillator 103A has a plurality (an odd number) of inverters 201 to 203 connected in multiple stages, and the output of the last inverter 203 is fed back to the input of the first inverter 201. The inverter 203 outputs a clock signal CLK.

[0045] A variable current source 204 is connected to the power supply of each of the inverters 201 to 203. The variable current source 204 adjusts the driving force of each of the inverters 201 to 203, and can change the period of the clock signal CLK.

[0046] A switch 104 is connected to one of the outputs of each of the inverters 201 to 203. The switch 104 sets one of the outputs of each of the inverters 201 to 203 to the ground potential based on the injection pulse PLS. By setting one of the outputs of each of the inverters 201 to 203 to the ground potential, it is possible to reset the accumulation of jitter in the clock signal CLK.

[0047] 5 is a diagram showing a second example of the oscillator circuit according to the first embodiment, in which a differential ring oscillator 103B is used in the oscillator circuit 103.

[0048] In the figure, differential ring oscillator 103B includes a plurality (an even number) of inverters 211 to 214. In this case, the front-stage inverters 211 and 212 are cross-coupled to the rear-stage inverters 213 and 214. The output of the rear-stage inverter 213 is fed back to the input of the front-stage inverter 211, and the output of the rear-stage inverter 214 is fed back to the input of the front-stage inverter 212. A clock signal CLK is output from the inverters 213 and 214.

[0049] A variable current source 215 is connected to the power supply of each of the inverters 211 to 214. The variable current source 215 adjusts the driving force of each of the inverters 211 to 214, and can change the cycle of the clock signal CLK.

[0050] A switch 104 is connected between the outputs of the inverters 213 and 214. Based on an injection pulse PLS, the switch 104 shorts out the outputs of the inverters 213 and 214. By shorting out the outputs of the inverters 213 and 214, it is possible to reset the accumulation of jitter in the clock signal CLK.

[0051] 6 is a diagram showing a third example of the oscillation circuit according to the first embodiment. In this diagram, an example in which an LC oscillator 103C is used in the oscillation circuit 103 is shown.

[0052] In the figure, an LC oscillator 103C generates an oscillation signal based on resonance between an inductor 241 and a capacitor 242. The LC oscillator 103C includes an inductor 241, a capacitor 242, transistors 243 and 244, and a variable current source 245. The transistors 243 and 244 are N-channel field effect transistors.

[0053] The inductor 241 and the capacitor 242 are connected in parallel to each other. The drains of the transistors 243 and 244 are connected to both ends of the capacitor 242. The drain of the transistor 243 is connected to the gate of the transistor 244, and the drain of the transistor 244 is connected to the gate of the transistor 243. The drain of the transistor 244 outputs the clock signal CLK.

[0054] The sources of the transistors 243 and 244 are connected to the ground potential via a variable current source 245. The variable current source 245 adjusts the current flowing through the transistors 243 and 244, thereby changing the cycle of the clock signal CLK.

[0055] The drain of the transistor 244 is connected to the switch 104. The switch 104 sets the output of the LC oscillator 103C to the ground potential based on the injection pulse PLS. By setting the output of the LC oscillator 103C to the ground potential, it is possible to reset the accumulation of jitter in the clock signal CLK.

[0056] FIG. 7 is a diagram illustrating a first example of a conversion unit applied to the calibration unit according to the first embodiment.

[0057] In the figure, for example, an FCW multiplier circuit can be used for the conversion units 112 and 113. The FCW multiplier circuit can be configured with a non-inverting amplifier NZ1. In this case, an operational amplifier P1 is provided in the non-inverting amplifier NZ1. The output of the operational amplifier P1 is connected to the inverting input of the operational amplifier P1 via a resistor R2. The inverting input of the operational amplifier P1 is grounded via a variable resistor R1. An input voltage Vin is input to the non-inverting input of the operational amplifier P1. An output voltage Vo is output from the operational amplifier P1.

[0058] In this case, Vo can be given as Vo = (1 + R1 / R2) Vin. If R1 = m × R2, Vo = (1 + m) Vin, and m = FCW - 1. In this case, m can be set by changing R1 according to FCW.

[0059] FIG. 8 is a diagram illustrating a second example of the conversion unit applied to the calibration unit according to the first embodiment.

[0060] In the figure, for example, a 1 / FCW multiplier circuit can be used for the conversion unit 112. The 1 / FCW multiplier circuit can be configured with a non-inverting amplifier NZ2. In this case, an operational amplifier P11 is provided in the non-inverting amplifier NZ2. The output of the operational amplifier P11 is connected to the inverting input of the operational amplifier P11 via a variable resistor R12. The inverting input of the operational amplifier P11 is grounded via a resistor R11. An input voltage Vin is input to the non-inverting input of the operational amplifier P11. An output voltage Vo is output from the operational amplifier P11.

[0061] In this case, Vo can be given by Vo = R11 / (R11 + R12)Vin. If R12 = m × R11, Vo = 1 / (1 + m)Vin, and m = FCW - 1. In this case, m can be set by changing R1 according to FCW.

[0062] FIG. 9 is a diagram illustrating a third example of the conversion unit applied to the calibration unit according to the first embodiment.

[0063] In the figure, the conversion unit 112 can use, for example, a 1 / FCW multiplier circuit. The 1 / FCW multiplier circuit can be configured with a ladder resistor RD1. In this case, the ladder resistor RD1 can be provided with resistors equal to the number of FCWs. For example, the ladder resistor RD1 can be provided with resistors R21 to R25. The resistors R21 to R25 are connected in series. The ladder resistor RD1 can be connected between nodes N0 and N5. The node N0 can be set to ground potential, and the node N5 can be set to power supply potential. Nodes N1 to N4 are provided at the connection points of the resistors R21 to R25, respectively. The nodes N0 to N5, which are used to input the input voltage Vin and output the output voltage Vo, are switchable. For example, the input voltage Vin can be input to node N3, and the output voltage Vo can be output from node N1. The value of each resistor R21 to R25 can be set to R.

[0064] At this time, by applying the input voltage Vin to the node Nm, a voltage divided by m resistors is output, and Vo=1 / m·Vin.

[0065] FIG. 10 is a diagram illustrating a fourth example of the conversion unit applied to the calibration unit according to the first embodiment.

[0066] In the figure, the conversion unit 113 can be, for example, a y / x multiplication circuit. The y / x multiplication circuit can be configured with ladder resistors RD1 and RD2. A ladder resistor RD2 is connected downstream of the ladder resistor RD1. For example, ladder resistor RD2 can be provided with resistors R31 to R35. The resistors R31 to R35 are connected in series. The ladder resistor RD2 can be connected between nodes M0 and M5. The node M0 can be set to ground potential, and the node M5 can be set to power supply potential. Nodes M1 to M4 are provided at the connection points of the resistors R31 to R35, respectively. The nodes N0 to N5 used to input the input voltage Vin and the nodes M0 to M5 used to output the output voltage Vo are switchable. For example, the input voltage Vin can be input to node N5, and the output voltage Vo can be output from node M2. The value of each resistor R21 to R25 can be set to, for example, 2 / 5·R.

[0067] In this case, the combined resistance of the two resistors of ladder resistor RD1 and all the resistors of ladder resistor RD2 can be set to R. In ladder resistor RD1, the input voltage Vin is divided by four resistors, with VN1 being 1 / 4·Vin, VN3 being 2 / 4·Vin, and VN31 being 1 / 4·Vin. Here, VN1 is the voltage at node N1, VN3 is the voltage at node N3, and VN31 is the voltage between nodes N1 and N3.

[0068] Furthermore, VN31 is divided by five resistors using ladder resistor RD2. In this case, VN1 is 1 / 4·Vin, VN3 is 2 / 4·Vin, and VM21 is 1 / 5·1 / 4·Vin=1 / 20·Vin. However, VM21 is the voltage between nodes M1 and M2. Therefore, Vo=VMm=VMm0+VNn0=m / 20·Vin+n / 4·Vin. However, VMm is the voltage at node Mm, VMm0 is the voltage between nodes Mm and M0, and VNn0 is the voltage between nodes Nn and N0, with 0≦m≦5 and 0≦n≦5.

[0069] The cascode connection of the ladder resistors RD1 and RD2 allows the input voltage Vin to be adjusted in 1 / 20 steps. The steps can be further subdivided by increasing the number of stages or the number of resistors per stage. Because the ladder resistors RD1 and RD2 are composed only of resistors, power consumption can be reduced.

[0070] FIG. 11 is a diagram illustrating a fifth example of the conversion unit applied to the calibration unit according to the first embodiment.

[0071] In the figure, for example, an FCW multiplier circuit can be used for the conversion units 112 and 113. The FCW multiplier circuit can be configured with a non-inverting amplifier NZ3 and ladder resistors RD1 and RD2. A ladder resistor RD1 is connected downstream of the non-inverting amplifier NZ3, and a ladder resistor RD2 is connected downstream of the ladder resistor RD1.

[0072] In this case, the non-inverting amplifier NZ3 is provided with an operational amplifier P41. The output of the operational amplifier P41 is connected to the inverting input of the operational amplifier P41 via a resistor R42. The inverting input of the operational amplifier P41 is grounded via a resistor R41. An input voltage Vin is input to the non-inverting input of the operational amplifier P41. An intermediate voltage Vm is output from the operational amplifier P41. The output of the operational amplifier P41 is connected to a node N5.

[0073] In this case, the non-inverting amplifier NZ3 can form an x-multiplication circuit. The cascode connection of the ladder resistors RD1 and RD2 can form a y / x-multiplication circuit. Here, R41 / (R41+R42) can be used, and Vm = xVin can be set. The stage following the non-inverting amplifier NZ3 can be a variable resistor voltage divider circuit that can be changed in 1 / x steps. In this case, Vo = y / x Vm = y / x xVin = yVin, and y can be set to FCW. Here, x can be a fixed value and y can be a variable value.

[0074] FIG. 12 is a diagram illustrating a sixth example of the conversion unit applied to the calibration unit according to the first embodiment.

[0075] In the figure, for example, a 1 / FCW multiplier circuit can be used for the conversion unit 112, and for example, a y / x multiplier circuit can be used for the conversion unit 113. The y / x multiplier circuit can have the configuration shown in FIG. 10. The 1 / FCW multiplier circuit can be configured with a ladder resistor RD3. A ladder resistor RD1 is connected to the rear stage of the ladder resistor RD3. A ladder resistor RD2 is connected to the rear stage of the ladder resistor RD1.

[0076] For example, the ladder resistor RD3 includes resistors R41 to R53. The resistors R41 to R53 are connected in series. The ladder resistor RD3 can be connected between nodes E0 and E13. Node E0 can be set to ground potential, and node E13 can be set to power supply potential. Nodes E1 to E12 are provided at the connection points of the resistors R41 to R53, respectively. Nodes E8 to E13, which are used to input the input voltage Vin, and nodes M0 to M5, which are used to output the reference voltage VR, are switchable. For example, the input voltage Vin can be input to node E10, the output voltage Vo can be passed to the subsequent stage from node E1, and the reference voltage VR can be output from node M0. The value of each resistor R41 to R53 can be set to, for example, R. In this case, if Vin=VDD, then Vo=1 / 10·VDD and VR=1 / 4·Vin=1 / 40·VDD.

[0077] Here, REF=1 GHz, CLK=10 GHz, and the pulse width TS of the injection pulse PLS is set to 25% of the period TK of the clock signal CLK. In this case, FCW=10, y=5, and x=20 can be set.

[0078] With these settings, the calibration unit 106 applies feedback so as to satisfy VP=5 / 200·VDD=25 ps / 1000 ps·VDD. Therefore, an injection pulse PLS having a width (25 ps) that is 25% of the 10 GHz period (100 ps) is generated at 1 GHz (period=1000 ps).

[0079] FIG. 13 is a diagram illustrating a seventh example of the conversion unit applied to the calibration unit according to the first embodiment.

[0080] In the figure, for example, a 1 / FCW multiplier circuit can be used for the conversion unit 112. For example, a y / x multiplier circuit can be used for the conversion unit 113. The 1 / FCW multiplier circuit and the y / x multiplier circuit can have the configuration shown in FIG.

[0081] Here, an input voltage Vin is input to node E12, an output voltage Vo is passed from node E1 to the subsequent stage, and a reference voltage VR is output from node M4. In this case, if Vin=VDD, then Vo=1 / 12·VDD and VR=4 / 20·Vin=4 / 240·VDD.

[0082] Here, REF=500 MHz, CLK=6 GHz, and 20% of the period TK of the clock signal CLK can be set as follows: FCW=12, y=4, and x=20.

[0083] With these settings, the calibration unit 106 applies feedback so as to satisfy VP=4 / 240·VDD=33 ps / 2000 ps·VDD. Therefore, an injection pulse PLS having a width (33 ps) that is 20% of the 6 GHz period (167 ps) is generated at 500 MHz (period=2000 ps).

[0084] FIG. 14 is a flowchart illustrating a first example of the process of updating the pulse width setting code according to the first embodiment.

[0085] In the figure, the code search unit 115 outputs a pulse width setting code COD to the pulse generation unit 105. At this time, the pulse generation unit 105 outputs an injection pulse PLS having a pulse width TS specified by the pulse width setting code COD (S101). Note that the code search unit 115 can assign consecutive integers to the pulse width setting code COD. The pulse generation unit 105 can increase the pulse width TS as the pulse width setting code COD increases.

[0086] Next, the code search unit 115 detects whether or not the relationship VP>VR exists based on the output result of the comparator 114 (S102). At this time, if the output result of the comparator 114 is a logical value of 1, the code search unit 115 can detect that the relationship VP>VR exists, and if the output result of the comparator 114 is a logical value of 0, the code search unit 115 can detect that the relationship VP>VR does not exist.

[0087] If the relationship VP>VR exists, the code search unit 115 decrements the pulse width setting code COD by 1 and returns to step S101 (S103). On the other hand, if the relationship VP>VR does not exist, the code search unit 115 increments the pulse width setting code COD by 1 and returns to step S101 (S104).

[0088] FIG. 15 is a flowchart illustrating a second example of the process of updating the pulse width setting code according to the first embodiment.

[0089] In the figure, the code search unit 115 determines whether the conditions mid≠top and mid≠btm are satisfied (S201). top is the maximum value of the pulse width setting code COD, btm is the minimum value of the pulse width setting code COD, and mid=(top+btm) / 2. If the conditions mid≠top and mid≠btm are not satisfied, the code search unit 115 terminates the processing. On the other hand, if the conditions mid≠top and mid≠btm are satisfied, the code search unit 115 sets the pulse width setting code COD to mid (S202).

[0090] Next, the code search unit 115 outputs the pulse width setting code COD to the pulse generation unit 105. At this time, the pulse generation unit 105 outputs an injection pulse PLS having a pulse width TS specified by the pulse width setting code COD (S203).

[0091] Next, the code search unit 115 detects whether or not the relationship VP>VR exists based on the output result of the comparator 114 (S204). If the relationship VP>VR exists, the code search unit 115 assigns mid to top and proceeds to step S207 (S205). On the other hand, if the relationship VP>VR does not exist, the code search unit 115 assigns mid to btm and proceeds to step S207 (S206).

[0092] Next, the chord search unit 115 calculates mid=(top+btm) / 2 and returns to step S203 (S207).

[0093] As described above, in the first embodiment, the level of 1 / FCW of the power supply voltage VDD is converted to a level corresponding to the ratio RA of the period of the clock signal CLK, and input as the reference voltage VR to the comparator 114. This makes it possible to generate the reference voltage VR for calibrating the pulse width TS of the injection pulse PLS based on the level conversion of integer and fractional multiples. This makes it possible to optimize the pulse width TS of the injection pulse PLS used for injection locking while suppressing an increase in circuit size.

[0094] Furthermore, the calibration unit 106 generates a reference voltage VR based on the level of the power supply voltage VDD, thereby enabling the reference voltage VR to follow fluctuations in the amplitude AM of the injection pulse PLS that correspond to fluctuations in the power supply voltage VDD, thereby improving the calibration accuracy of the pulse width TS of the injection pulse PLS.

[0095] 2. Second Embodiment In the first embodiment described above, the level of 1 / FCW of the power supply voltage VDD is converted to a level that is a ratio RA to the period of the clock signal CLK. In this second embodiment, the injection pulse PLS converts the smoothed DC level to a level of 1 / FCW, and converts the level of the power supply voltage VDD to a level that is a ratio RA to the period of the clock signal CLK.

[0096] FIG. 16 is a block diagram illustrating an example of the configuration of a calibration unit according to the second embodiment.

[0097] In the figure, the calibration unit 206 includes a conversion unit 121 instead of the conversion unit 112 of the calibration unit 106 of the first embodiment described above. The other configuration of the calibration unit 206 is the same as the configuration of the calibration unit 106 of the first embodiment described above.

[0098] The conversion unit 121 is connected to the rear stage of the low-pass filter 111. At this time, the output of the low-pass filter 111 is input to the comparator 114 via the conversion unit 121. On the other hand, the output of the conversion unit 113 is input to the comparator 114 without passing through the conversion unit 121.

[0099] The conversion unit 121 converts the output level of the low-pass filter 111 based on the value obtained by dividing the period of the injection pulse PLS by the period of the clock signal CLK, and inputs the converted level to the comparator 114. Here, the conversion unit 121 can set the output level of the low-pass filter 111 to FCW times the normalized value. The comparator 114 compares the output level output from the conversion unit 121 with the output level output from the conversion unit 113, and outputs the comparison result to the code search unit 115.

[0100] As described above, in the second embodiment, the injection pulse PLS converts the smoothed DC level to a level that is FCW times higher, and converts the level of the power supply voltage VDD to a level that is a proportion RA to the period of the clock signal CLK. This allows the injection pulse PLS to increase the smoothed DC level before inputting it to the comparator 114, and also prevents a decrease in the reference voltage VR input to the comparator 114. This makes it possible to increase the input to the comparator 114, thereby improving the comparison accuracy of the comparator 114.

[0101] 3. Third Embodiment In the first embodiment described above, the level of 1 / FCW of the power supply voltage VDD is converted to a level that is a ratio RA to the period of the clock signal CLK. In this third embodiment, the injection pulse PLS converts the smoothed DC level to a level that is a numerator multiple of FCW, and converts the level of the power supply voltage VDD multiplied by FCW to a level that is a ratio RA to the period of the clock signal CLK.

[0102] FIG. 17 is a block diagram illustrating an example of the configuration of a calibration unit according to the third embodiment.

[0103] In the figure, the calibration unit 306 includes conversion units 112A and 112B instead of the conversion unit 112 of the calibration unit 106 of the first embodiment described above. The rest of the configuration of the calibration unit 306 is the same as the configuration of the calibration unit 106 of the first embodiment described above.

[0104] Conversion unit 112A is connected to the rear stage of low-pass filter 111. At this time, the output of low-pass filter 111 is input to comparator 114 via conversion unit 112A. Conversion unit 112B is connected to the rear stage of conversion unit 113. At this time, the output of conversion unit 113 is input to comparator 114 via conversion unit 112B.

[0105] The conversion unit 112A converts the output level of the low-pass filter 111 to a level that is a multiple of the numerator of the FCW and inputs it to the comparator 114. The conversion unit 112B converts the output level of the conversion unit 113 to a level that is a multiple of the denominator of the FCW and inputs it to the comparator 114. At this time, the comparator 114 compares the output level output from the conversion unit 112A with the output level output from the conversion unit 112B and outputs the comparison result to the code search unit 115.

[0106] As described above, in the third embodiment, the injection pulse PLS converts the smoothed DC level to a level that is a multiple of the numerator of FCW, and converts the level of the power supply voltage VDD corresponding to the ratio RA of the period of the clock signal CLK to a level that is a multiple of the denominator of FCW. This makes it possible to increase the smoothed DC level of the injection pulse PLS based on the integral multiple amplification operation before inputting it to the comparator 114, and also makes it possible to prevent a decrease in the reference voltage VR input to the comparator 114. This makes it possible to increase the input to the comparator 114 while suppressing the complexity of the circuit configuration, thereby improving the comparison accuracy of the comparator 114.

[0107] Furthermore, even if the FCW or the value obtained by dividing the period of the clock signal CLK by the period of the pulse signal PLS is a decimal, a fraction representing that decimal or the fraction closest to the decimal can be prepared, and the numerator and denominator of that fraction can be used to accommodate cases where the FCW is not an integer. For example, in a typical design (during injection), the settings are CLK = 13.5 GHz and REF = PLS = 0.5 GHz, so PLS period / CLK period = 27, which can be accommodated by implementing the first embodiment described above. On the other hand, increasing the PLS frequency results in a faster, more stable smoothed voltage, allowing for faster completion of calibration. In this case, if you want CLK = 13.5 GHz and PLS = 2 GHz only during calibration, the PLS period / CLK period = 6.75, which is a decimal. In such cases, instead of using the decimal value, you can prepare an improper fraction whose numerator and denominator are integers.

[0108] 4. Fourth Embodiment In the first embodiment described above, the level of 1 / FCW of the power supply voltage VDD is converted to a level corresponding to the ratio RA to the period of the clock signal CLK. In this fourth embodiment, a phase locked loop circuit is applied to an imaging device.

[0109] FIG. 18 is a block diagram illustrating an example of the configuration of an imaging apparatus according to the fourth embodiment.

[0110] In the figure, the imaging device 400 includes an optical system 401, a solid-state imaging device 402, an imaging control unit 403, an image processing unit 404, a storage unit 405, a display unit 406, and an operation unit 407. The imaging control unit 403, the image processing unit 404, the storage unit 405, the display unit 406, and the operation unit 407 are connected to one another via a bus 408. The imaging device 400 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0111] The optical system 401 causes light from a subject to be incident on the solid-state imaging device 402, and forms an optical image on the light receiving surface of the solid-state imaging device 402. The optical system 401 may include, for example, a focus lens, a zoom lens, an aperture, etc. The optical system 401 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0112] The solid-state imaging device 402 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. In this case, the solid-state imaging device 402 may support CDS (Correlated Double Sampling) readout or DDS readout. Each pixel may include a single photodiode or multiple photodiodes with different sensitivities. The solid-state imaging device 402 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 402 may also be a LOFIC image sensor.

[0113] The imaging control unit 403 controls imaging by the solid-state imaging device 402 based on instructions from the operation unit 407. At this time, the imaging control unit 403 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 402.

[0114] The image processing unit 404 performs image processing based on the output from the solid-state imaging device 402. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 404 may include a processor that executes processing based on software.

[0115] The storage unit 405 stores images captured by the solid-state imaging device 402 and stores imaging parameters of the solid-state imaging device 402. The storage unit 405 can also store a program that operates the imaging device 400 based on software. The storage unit 405 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0116] The display unit 406 displays captured images, various information that supports the image capturing operation, etc. The display unit 406 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0117] The operation unit 407 provides a user interface for operating the imaging device 400. The operation unit 407 may include, for example, buttons, dials, and switches provided on the imaging device 400. The operation unit 407 may be configured as a touch panel together with the display unit 406.

[0118] Depending on the configuration of the imaging device 400, some of the above functions may not be present, or conversely, the imaging device 400 may further include functions that are not disclosed.

[0119] FIG. 19 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fourth embodiment.

[0120] In the figure, the solid-state imaging device 402 includes a pixel array section 411 , a vertical scanning circuit 412 , a column readout circuit 413 , a column signal processing section 414 , a horizontal scanning circuit 415 , and a control circuit 416 .

[0121] The pixel array unit 411 includes a plurality of pixels 420. The pixels 420 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). Each pixel 420 can form a source follower with the column readout circuit 413 when reading out a signal. Each pixel 420 is connected to a horizontal drive line 431 for each row and to a vertical signal line 432 for each column. The horizontal drive line 431 drives each pixel 420 for each row when reading out a signal from each pixel 420. The vertical signal line 432 transmits a potential based on a current flowing when reading out a signal from the pixel 420 to the column signal processing unit 414 for each column.

[0122] Each pixel 420 may be a single pixel, a four-pixel shared pixel, or an eight-pixel shared pixel. The pixels 420 may be arranged in a Bayer array or a quad-Bayer array. The light received by each pixel 420 may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0123] The vertical scanning circuit 412 scans the pixels 420 to be read in the column direction. The vertical scanning circuit 412 may be configured using a vertical register.

[0124] The column readout circuit 413 can form a source follower between itself and each pixel 420 when reading out a signal from the pixel 420. At this time, the column readout circuit 413 can change the potential of the vertical signal line 432 based on the charge held in the pixel 420.

[0125] The column signal processing unit 414 processes signals transmitted in the column direction from each pixel 420. For example, the column signal processing unit 414 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel 420. The column signal processing unit 414 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel 420, and output an imaging signal Gout.

[0126] The column signal processing unit 414 includes a column ADC unit 414A. The column ADC unit 414A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 414A can perform AD conversion for each column based on the comparison result between the pixel signal read from the pixel 420 and the reference signal.

[0127] The horizontal scanning circuit 415 scans the pixels 420 to be read in the row direction. The horizontal scanning circuit 415 may be configured using a horizontal register.

[0128] The control circuit 416 controls the vertical scanning circuit 412, the column readout circuit 413, the column signal processing unit 414, and the horizontal scanning circuit 415. For example, the control circuit 416 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 413, and the processing timing of the column signal processing unit 414. In this case, the control circuit 416 can coordinate the vertical scanning circuit 412, the column readout circuit 413, the column signal processing unit 414, and the horizontal scanning circuit 415 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0129] In this way, in the fourth embodiment, a phase-locked loop circuit capable of injection locking is applied to an imaging device, which makes it possible to improve the accuracy of the clock used in the solid-state imaging device while suppressing an increase in circuit size.

[0130] 5. Fifth Embodiment In the first embodiment described above, a phase locked loop circuit is applied to an imaging device. In this fifth embodiment, semiconductor chips each having a pixel array section in which pixels are arranged in a matrix are stacked.

[0131] FIG. 20 is a perspective view showing an example of a stack of pixel array units according to the fifth embodiment.

[0132] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0133] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0134] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillation circuit 928 are formed in the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The oscillation circuit 928 can be provided with any of the phase locked loop circuits described in the first to third embodiments.

[0135] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0136] As described above, in the fifth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0137] 6. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0138] FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0139] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 21 , the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0140] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0141] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0142] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0143] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0144] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0145] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0146] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0147] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0148] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 21, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0149] FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.

[0150] In FIG. 22, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0151] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0152] 22 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0153] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0154] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0155] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0156] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0157] The above describes an example of a vehicle control system to which the technology disclosed herein can be applied. The technology disclosed herein can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031 among the above-described configurations. Specifically, for example, the phase-locked loop circuit of the above-described embodiment can be applied to the drivetrain control unit 12010, body system control unit 12020, outside vehicle information detection unit 12030, inside vehicle information detection unit 12040, integrated control unit 12050, and image capture unit 12031. Applying the technology disclosed herein to the vehicle control system 12000 can improve the accuracy of clocks used for various processes while suppressing an increase in circuit size.

[0158] In addition, the phase locked loop circuit according to any one of the first to third embodiments described above can be applied to an imaging device, and may also be applied to electronic circuits used in communication devices, display devices, data processing devices, control devices, measuring devices, printing devices, etc.

[0159] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0160] The present technology may also be configured as follows: (1) A phase locked loop circuit comprising: an injection lock unit that resets an oscillation output based on an injection pulse; and a calibration unit that calibrates the pulse width of the injection pulse based on the pulse width of the injection pulse and frequency information of the oscillation output. (2) The phase locked loop circuit according to (1), wherein the calibration unit calibrates the pulse width of the injection pulse based on a comparison result between a first voltage generated based on the pulse width of the injection pulse and a second voltage generated based on a ratio to a period of the oscillation output. (3) The phase locked loop circuit according to (2), further comprising: a pulse generating unit that generates an injection pulse whose pulse width is set based on a code and whose amplitude is set based on a power supply voltage, wherein the calibration unit comprises: a comparator that compares the first voltage with the second voltage; and a code searching unit that searches for the code based on the comparison result by the comparator and outputs the code to the pulse generating unit. (4) The phase locked loop circuit according to (3), wherein the code search unit searches for a current code based on a previously searched code and an output of the comparator. (5) The phase locked loop circuit according to (3) or (4), further comprising: a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generation unit and outputs the DC voltage as the first voltage; a first conversion unit that converts the level of the power supply voltage based on the reciprocal of a value obtained by dividing a period of the injection pulse by a period of the oscillation output; and a second conversion unit that converts a result of the conversion by the first conversion unit to a level corresponding to the proportion and outputs the level as the second voltage. (6) The phase locked loop circuit according to (3) or (4), further comprising: a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generating unit; a first conversion unit that converts the level of the DC voltage based on a value obtained by dividing the period of the injection pulse by the period of the oscillation output and outputs the converted DC voltage as the first voltage; and a second conversion unit that converts the level of the power supply voltage to a level corresponding to the percentage and outputs the converted DC voltage as the second voltage.(7) The phase locked loop circuit according to (3) or (4), further comprising: a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generating unit; a first conversion unit that converts the level of the DC voltage based on frequency multiplication information and outputs the DC voltage as the first voltage; a second conversion unit that converts the level of the power supply voltage to a level corresponding to the percentage; and a third conversion unit that converts a result of the conversion by the second conversion unit based on the frequency multiplication information and outputs the result as the second voltage. (8) The phase locked loop circuit according to any of (5) to (7), wherein the frequency multiplication information is a value obtained by dividing the period of the injection pulse by the period of the oscillation output. (9) The phase locked loop circuit according to any of (5) to (8), wherein each of the first conversion unit and the second conversion unit comprises at least one of a ladder resistor and an inverting amplifier. (10) The phase locked loop circuit according to any of (1) to (9), wherein the injection lock unit comprises a switch that sets the oscillation output to ground potential based on the injection pulse. (11) A semiconductor integrated circuit comprising: an injection lock unit formed on a semiconductor chip and resetting an oscillation output based on an injection pulse; and a calibration unit formed on the semiconductor chip and calibrating the pulse width of the injection pulse based on the pulse width of the injection pulse and frequency information of the oscillation output.

[0161] 100 Frequency control section 101 Phase comparator 102 Loop filter 103 Oscillator circuit 104 Switch 105 Pulse generation section 106 Calibration section 107 Injection section

Claims

1. A phase-locked loop circuit comprising: an injection lock unit that resets an oscillation output based on an injection pulse; and a calibration unit that calibrates the pulse width of the injection pulse based on the pulse width of the injection pulse and frequency information of the oscillation output.

2. The phase-locked loop circuit according to claim 1, wherein the calibration unit calibrates the pulse width of the injection pulse based on a comparison result between a first voltage generated based on the pulse width of the injection pulse and a second voltage generated based on a ratio to the period of the oscillation output.

3. The phase locked loop circuit according to claim 2, further comprising a pulse generating unit that generates an injection pulse whose pulse width is set based on a code and whose amplitude is set based on a power supply voltage, wherein the calibration unit comprises: a comparator that compares the first voltage with the second voltage; and a code searching unit that searches for the code based on the comparison result by the comparator and outputs the code to the pulse generating unit.

4. The phase locked loop circuit according to claim 3, wherein said code search section searches for a current code based on a previously searched code and the output of said comparator.

5. The phase locked loop circuit according to claim 3, further comprising: a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generating unit and outputs the DC voltage as the first voltage; a first conversion unit that converts the level of the power supply voltage based on the reciprocal of the value obtained by dividing the period of the injection pulse by the period of the oscillation output; and a second conversion unit that converts the result of the conversion by the first conversion unit to a level corresponding to the proportion and outputs the level as the second voltage.

6. The phase locked loop circuit according to claim 3, further comprising: a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generating section; a first conversion section that converts the level of the DC voltage based on a value obtained by dividing the period of the injection pulse by the period of the oscillation output, and outputs the converted DC voltage as the first voltage; and a second conversion section that converts the level of the power supply voltage to a level corresponding to the proportion, and outputs the converted DC voltage as the second voltage.

7. The phase locked loop circuit according to claim 3, further comprising: a low-pass filter that generates a DC voltage by smoothing the injection pulse generated by the pulse generating section; a first conversion section that converts the level of the DC voltage based on frequency multiplication information and outputs the result as the first voltage; a second conversion section that converts the level of the power supply voltage to a level corresponding to the proportion; and a third conversion section that converts a result of the conversion by the second conversion section based on the frequency multiplication information and outputs the result as the second voltage.

8. The phase locked loop circuit according to claim 5, wherein the frequency multiplication information is a value obtained by dividing the period of the injection pulse by the period of the oscillation output.

9. The phase locked loop circuit according to claim 5, wherein each of the first conversion section and the second conversion section comprises at least one of a ladder resistor and an inverting amplifier.

10. The phase locked loop circuit according to claim 1, wherein the injection locking section includes a switch that sets the oscillation output to ground potential based on the injection pulse.

11. A semiconductor integrated circuit comprising: an injection lock unit formed on a semiconductor chip that resets an oscillation output based on an injection pulse; and a calibration unit formed on the semiconductor chip that calibrates the pulse width of the injection pulse based on the pulse width of the injection pulse and frequency information of the oscillation output.

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