Array substrate, driving method therefor, display panel and display device

Abstract

An array substrate, a driving method therefor, a display panel and a display device. The array substrate comprises a display area (AA) and a non-display area (BB) on at least one side of the display area (AA); a plurality of gate lines (G1-G8), which extend in a row direction (X) and are arranged in a column direction (Y) in the display area (AA); a plurality of pixels (PX), which are arranged in an array in the display area (AA), wherein pixels (PX) in the same row are electrically connected to two gate lines, two gate lines are comprised between two adjacent rows of pixels (PX), at least one column of pixels (PX) is taken as a group, gate lines corresponding to odd-numbered groups of pixels (PX1) in the same row are different from gate lines corresponding to even-numbered groups of pixels (PX2) in the same row, and gate lines corresponding to odd-numbered groups of pixels (PX1) in each row are located on the same side of the row, and gate lines corresponding to even-numbered groups of pixels (PX2) in the row are located on the other side of the row; and a gate driving circuit, which is located in the non-display area (BB), the gate driving circuit comprising a plurality of shift registers (GOA1-GOA9) arranged in cascade, wherein a first-stage shift register (GOA1) is electrically connected to the first gate line (G1), a (2q+1)th-stage shift register is electrically connected to the 2qth gate line, and a 2qth-stage shift register is electrically connected to the (2q+1)th gate line, and q is a positive integer.

Description

Array substrate, its driving method, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, its driving method, a display panel, and a display device. Background Technology

[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays.

[0003] Summary of the Invention

[0004] The array substrate, its driving method, display panel, and display device provided in this disclosure are specifically as follows:

[0005] On one hand, embodiments of this disclosure provide an array substrate, including:

[0006] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0007] Multiple grid lines extend along the row direction and are arranged along the column direction in the display area;

[0008] Multiple pixels are arranged in an array in the display area, with each row of pixels corresponding to two gate lines, and two gate lines between adjacent rows of pixels; at least one column of pixels forms a group, and the gate lines corresponding to the odd-numbered pixels in a row are different from those corresponding to the even-numbered pixels; the gate lines corresponding to the odd-numbered pixels in each row are located on the same side of each row, and the gate lines corresponding to the even-numbered pixels are located on the other side of each row;

[0009] A gate driving circuit is located in the non-display area. The gate driving circuit includes multiple shift registers arranged in cascade. The first-stage shift register is electrically connected to the first gate line, the (2q+1)-stage shift register is electrically connected to the 2q-stage gate line, and the 2q-stage shift register is electrically connected to the (2q+1)-stage gate line, where q is a positive integer.

[0010] In some embodiments, in the array substrate provided in the present disclosure, the q-th shift register is cascaded with the (q+p)-th shift register, and the 1-th shift register, the (2q+1)-th shift register, and the 2q-th shift register are arranged sequentially along the column direction, where p is an integer greater than or equal to 2.

[0011] In some embodiments, the array substrate provided in this disclosure further includes a plurality of data lines extending along the column direction and arranged along the row direction in the display area;

[0012] The pixel includes multiple sub-pixels. Sub-pixels in the same column are electrically connected to the same data line. An odd number of pixels and an even number of pixels form a cycle. Within the cycle, the data line corresponding to the nth column of the sub-pixel is connected to the data line corresponding to the (n+m)th column of the sub-pixel. Here, n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

[0013] In some embodiments, in the array substrate provided in the present disclosure, two columns of pixels form a group, or four columns of pixels form a group.

[0014] In some embodiments, the array substrate provided in this disclosure further includes multiple clock signal lines located in the non-display area. The clock signal lines include 6 lines, and the i-th clock signal line is coupled to the clock signal terminal of the [6(j-1)+i]-th stage shift register, where i is an integer greater than or equal to 1 and less than or equal to 6, and j is a positive integer.

[0015] On the other hand, embodiments of this disclosure provide a driving method for the array substrate described above, comprising:

[0016] Within one frame, the first-level shift register loads the scan voltage for the first gate line, the (2q+1)-level shift register loads the scan voltage for the second-q gate line, and the second-q-level shift register loads the scan voltage for the (2q+1)-level gate line. Data voltages of the same polarity are loaded onto the sub-pixels contained in the pixel in a single-column or double-column manner.

[0017] On the other hand, embodiments of this disclosure provide an array substrate, including:

[0018] A substrate, the substrate including a display area;

[0019] Multiple gate lines extend along the row direction and are arranged along the column direction in the display area, and the gate lines are electrically connected to the clock signal lines;

[0020] Multiple pixels are arranged in an array in the display area, with each row of pixels corresponding to two gate lines, and two gate lines between adjacent rows of pixels; at least one column of pixels forms a group, and the gate lines corresponding to odd-numbered pixels in the same row are different from the gate lines corresponding to even-numbered pixels; one of the two gate lines corresponding to odd-numbered pixels and the two gate lines corresponding to even-numbered pixels in each adjacent row is located between the two adjacent rows, and the other is located on both sides of the two adjacent rows.

[0021] In some embodiments, the array substrate provided in this disclosure further includes a plurality of data lines extending along the column direction and arranged along the row direction in the display area;

[0022] The pixel includes multiple sub-pixels. Sub-pixels in the same column are electrically connected to the same data line. An odd number of pixels and an even number of pixels form a cycle. Within the cycle, the data line corresponding to the nth column of the sub-pixel is connected to the data line corresponding to the (n+m)th column of the sub-pixel. Here, n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

[0023] In some embodiments, in the array substrate provided in the present disclosure, two columns of pixels form a group, or four columns of pixels form a group.

[0024] In some embodiments, in the array substrate provided in the present disclosure, the substrate further includes a non-display area located on at least one side of the display area, and the array substrate further includes a gate driving circuit located in the non-display area. The gate driving circuit includes a plurality of shift registers cascaded together. The plurality of shift registers are arranged along the column direction in the order from the first-stage shift register to the last-stage shift register, wherein the s-th stage shift register is electrically connected to the s-th gate line, and s is a positive integer.

[0025] In some embodiments, the array substrate provided in this disclosure further includes multiple clock signal lines located in the non-display area, wherein the i-th clock signal line is coupled to the clock signal terminal of the [k*(j-1)+i]-th stage shift register, k is the total number of clock signal lines, i is an integer greater than or equal to 1 and less than or equal to k, and j is a positive integer.

[0026] On the other hand, embodiments of this disclosure provide a driving method for the above-mentioned array substrate, including:

[0027] Within one frame, scan voltage is applied to the grid lines line by line, and data voltage of the same polarity is applied to the sub-pixels contained in the pixel in a single-column or double-column manner.

[0028] On the other hand, this disclosure provides a display panel, including the array substrate described above.

[0029] On the other hand, this disclosure provides a display device including the display panel described above. Attached Figure Description

[0030] Figure 1 is a schematic diagram of a pixel structure in a related technology;

[0031] Figure 2 is a schematic diagram of the pixel architecture shown in Figure 1 under the red background;

[0032] Figure 3 is a schematic diagram of the corresponding data voltage waveform when the red screen shown in Figure 2 is displayed;

[0033] Figure 4 is a schematic diagram of another pixel structure in related technologies;

[0034] Figure 5 is a schematic diagram of the pixel architecture shown in Figure 4 under the red background;

[0035] Figure 6 is a schematic diagram of the corresponding data voltage waveform when the red screen shown in Figure 5 is displayed;

[0036] Figure 7 is the equivalent circuit diagram of the pixel architecture shown in Figure 4;

[0037] Figure 8 is a schematic diagram of the charging of the pixel electrode in Figure 4, which is controlled by the odd-numbered or even-numbered gate line.

[0038] Figure 9 is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0039] Figure 10 is a schematic diagram of a pixel structure of an array substrate provided in an embodiment of the present disclosure within a cycle;

[0040] Figure 11 is a schematic diagram of a gate driving circuit provided in an embodiment of this disclosure;

[0041] Figure 12 is a schematic diagram of another structure of the gate driving circuit provided in an embodiment of this disclosure;

[0042] Figure 13 is a schematic diagram of another structure of the gate driving circuit provided in an embodiment of this disclosure;

[0043] Figure 14 is a schematic diagram of another structure of the gate driving circuit provided in an embodiment of this disclosure;

[0044] Figure 15 is a schematic diagram of the charging of the pixel electrode in Figure 10, which is controlled by the odd-numbered or even-numbered gate line.

[0045] Figure 16 is a schematic diagram of another pixel structure of the array substrate provided in an embodiment of the present disclosure in one cycle;

[0046] Figure 17 is a schematic diagram of the pixel architecture shown in Figure 10 using H2line flip-drive;

[0047] Figure 18 is a schematic diagram of the pixel architecture shown in Figure 16 using H2line flip-drive;

[0048] Figure 19 is a schematic diagram of the pixel architecture shown in Figure 16 using H2line flip-drive in a one-dot screen;

[0049] Figure 20 is a schematic diagram of another pixel structure of the array substrate provided in an embodiment of the present disclosure in one cycle;

[0050] Figure 21 is a schematic diagram of another structure of the gate driving circuit provided in an embodiment of this disclosure;

[0051] Figure 22 is a schematic diagram of another structure of the gate driving circuit provided in an embodiment of this disclosure;

[0052] Figure 23 is a schematic diagram of another pixel structure of the array substrate provided in an embodiment of the present disclosure in one cycle;

[0053] Figure 24 is a schematic diagram of the pixel architecture shown in Figure 20 using H2line flip-drive;

[0054] Figure 25 is a schematic diagram of the pixel architecture shown in Figure 23 using H2line flip-drive;

[0055] Figure 26 is a schematic diagram of the pixel architecture shown in Figure 23 using H2line flip-drive in a one-dot screen;

[0056] Figure 27 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0057] Figure 28 is a schematic diagram of the structure of the display device provided in an embodiment of this disclosure. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics; sharp corners illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; they are merely illustrative of the content of this disclosure. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0059] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0060] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0061] To reduce costs, related products adopt a dual-gate-Z architecture, as shown in Figure 1. This effectively reduces the number of bonding leads for data lines, thereby reducing the number of chip-on-flip (COF) driver chips. However, the existing architecture leads to insufficient charging when displaying solid colors. This charging rate issue becomes increasingly prominent as high-end products demand higher refresh rates. Figure 2 is a schematic diagram of a solid color display using the dual-gate-Z architecture shown in Figure 1. The diagram uses a red image as an example, where Y indicates that the red sub-pixel R is not at the L0 gray level, and N indicates that the green sub-pixel G and blue sub-pixel B are at the L0 gray level. Figure 3 is a schematic diagram of the corresponding data voltage waveforms when displaying the red image shown in Figure 2. Da1 to Da6 represent the data voltages of data lines D1 to D6, respectively, and Vcom represents the common voltage. As can be seen from Figure 3, each sub-pixel R lacks pre-charging (pre-charging means pre-charging a certain amount of voltage before the pixel voltage is fully charged). Similar issues exist for other solid or mixed colors.

[0062] To address the charging rate issue of the dual-gate product shown in Figure 1, a Dual Gate architecture was invented, as shown in Figure 4. In this architecture, the data line D1 corresponding to the first column sub-pixel is connected to the data line D7 corresponding to the seventh column sub-pixel, ensuring that the first and seventh column sub-pixels are controlled by the same data voltage. Similarly, the data line D3 corresponding to the second column sub-pixel is connected to the data line D8 corresponding to the eighth column sub-pixel, again ensuring that the second and eighth column sub-pixels are controlled by the same data voltage, and so on. The waveforms of a solid color image (e.g., a red image) and its data voltage are shown in Figures 5 and 6. As can be seen from Figures 5 and 6, each red sub-pixel R undergoes pre-charging, and similarly, other solid or mixed colors also undergo pre-charging, thus solving the problem of insufficient charging rate in high refresh rate products.

[0063] Analysis of the architecture shown in Figure 4 reveals that the first six columns of sub-pixels are controlled by even-numbered row gate lines G_E (G2, G4, G6, etc.), while the last six columns are controlled by odd-numbered row gate lines G_O (G1, G2, G5, etc.), arranged periodically. Furthermore, the scan voltage gN (e.g., g1 to g8) output by the Nth-level shift register GOAN is provided to the Nth gate line (e.g., gate lines G1 to G8 from the 1st to the 8th). The equivalent circuit diagram of the pixel architecture shown in Figure 4 is shown in Figure 7. The first six columns of sub-pixels are referred to as p_column 1, and the last six columns as p_column 2. From the equivalent circuit diagram 7, it can be seen that the sub-pixel charging voltage (specifically, the charging voltage of the pixel electrodes contained in the sub-pixel) is affected not only by charging-related factors, such as the storage capacitor Cst, the liquid crystal capacitor Clc, and the charging and discharging performance of the transistor TFT, but also by coupling capacitance, especially the coupling capacitance between the pixel electrode and the gate line, i.e., the influence of Cgs and Cgs' as shown in the diagram. Wherein, Cgs is the coupling capacitance between the current row of gate lines and the current row of pixel electrodes, and Cgs' is the coupling capacitance between the adjacent row of gate lines and the current row of pixel electrodes. It can be understood that the same row of pixel electrodes is affected by the two rows of gate lines above and below in spatial position, and the magnitude of the influence is called ΔVp and ΔVp', respectively.

[0064] Because of the voltage jumps in the gate lines, Cgs and Cgs' will cause changes in the pixel voltage. However, this change differs significantly between the charging time and the period outside the charging time; it recovers during the charging time but not outside of it. A schematic diagram of pixel electrode charging is shown in Figure 8. Figure 8 illustrates an example using a gate drive circuit (GOA) architecture with 6 clock signal lines (i.e., 6CLK) and a gate line open time of 3H, where H is the charging time for one row of pixels.

[0065] The pixel voltage change process of column P1, controlled by even-numbered row gate lines G_E, is as follows: During the initial charging phase, the voltage rapidly rises to the pre-charge voltage. Then, influenced by the coupling capacitor Cgs' of the odd-numbered row gate line GO above, the pixel voltage is momentarily pulled down when the odd-numbered row gate line G_O is turned off. However, since pixel charging is not yet complete, the pixel voltage recovers to the pre-charge voltage. Influenced by the coupling capacitor Cgs of this row gate line, the pixel voltage drops by ΔVp when this row gate line is turned off. Since this row gate line is already off, it cannot recover. In summary, influenced by Cgs and Cgs', the final voltage drop in column P1 is ΔVp.

[0066] Similarly, the pixel voltage change process of column P2 controlled by the odd-numbered row gate line G_O is as follows: During the initial charging stage, the voltage quickly rises to the pre-charge voltage. Then, influenced by the coupling capacitor Cgs' of the next even-numbered row gate line G_E, the even-numbered row gate line G_E has an upward pull effect on the pixel voltage when it opens. However, since the pixel charging is not yet complete, the pixel voltage will return to the pre-charge voltage. Influenced by the coupling capacitor Cgs' of this row gate line, the pixel voltage will drop by ΔVp when this row gate line closes. Since this row gate line is already closed, it cannot recover. Influenced by the coupling capacitor Cgs' of the even-numbered row gate line G_E, the pixel voltage will drop by ΔVp' when it closes. Since this even-numbered row gate line G_E is already closed, it cannot recover. Therefore, influenced by Cgs and Cgs', the final voltage drop of column P2 is (ΔVp + ΔVp').

[0067] Based on the above analysis, it can be seen that the final pixel voltage of the sub-pixels of column P1 and column P2 in the architecture shown in Figure 4 is significantly different, with a difference of ΔVp', resulting in a macroscopic defect of periodic vertical lines.

[0068] To at least improve the aforementioned technical problems existing in related technologies, this disclosure provides an array substrate. Figure 9 is a structural schematic diagram of the array substrate provided in this disclosure, Figure 10 is a structural schematic diagram of the array substrate provided in this disclosure within one cycle, and Figures 11 to 14 are structural schematic diagrams of the gate driving circuit in the array substrate provided in this disclosure. Figures 11 and 13 show that a gate driving circuit is provided only at one end of the gate line, while Figures 12 and 14 show that gate driving circuits are provided at both ends of the gate line. As can be seen from Figures 9 to 14, the array substrate provided in this disclosure includes:

[0069] Substrate 101 includes a display area AA and a non-display area BB located on at least one side of the display area AA;

[0070] Multiple grid lines (e.g., G1 to G8) extend along the row direction X and are arranged along the column direction Y in the display area AA;

[0071] Multiple pixels PX are arranged in an array in the display area AA. Each row of pixels PX corresponds to two gate lines (e.g., G1 and G2, G3 and G4, G5 and G6, G7 and G8). Optionally, each pixel PX includes multiple sub-pixels (e.g., red sub-pixel R, blue sub-pixel B, green sub-pixel G, etc.). The pixel electrode of each sub-pixel corresponds to a gate line via a transistor. In this disclosure, the gate line corresponding to a pixel PX refers to the gate line electrically connected to the transistor electrically connected to the pixel PX. Optionally, two gate lines (e.g., G2 and G8) are included between two adjacent rows of pixels PX. G3, G4 and G5, G6 and G7); at least one column of pixels PX is a group, and the gate lines corresponding to the odd number of pixels PX1 in the same row (e.g., G2, G4, G6, G8) are different from the gate lines corresponding to the even number of pixels PX2 (e.g., G1, G3, G5, G7); the gate lines corresponding to the odd number of pixels PX1 in each row (e.g., G2, G4, G6, G8) are located on the same side of each row (e.g., the bottom side), and the gate lines corresponding to the even number of pixels PX2 (e.g., G1, G3, G5, G7) are located on the other side of each row (e.g., the top side);

[0072] The gate driving circuit, located in the non-display area BB, includes multiple cascaded shift registers (e.g., GOA1 to GOA9). The first-stage shift register GOA1 is electrically connected to the first gate line G1, the (2q+1)th-stage shift register is electrically connected to the 2qth gate line, and the 2qth-stage shift register is electrically connected to the (2q+1)th gate line, where q is a positive integer. For example, the third-stage shift register GOA3 is electrically connected to the second gate line G2, and the second-stage shift register... Register GOA2 is electrically connected to the third gate line G3; the fifth-stage shift register GOA5 is electrically connected to the fourth gate line G4, and the fourth-stage shift register GOA4 is electrically connected to the fifth gate line G5; the seventh-stage shift register GOA7 is electrically connected to the sixth gate line G6, and the sixth-stage shift register GOA6 is electrically connected to the seventh gate line G7; the ninth-stage shift register GOA9 is electrically connected to the eighth gate line G8, and the eighth-stage shift register GOA8 is electrically connected to the ninth gate line G9.

[0073] It should be noted that in this disclosure, the Nth (N is a positive integer) level shift register GOAN refers to the Nth shift register opened within a frame, that is, N represents the opening order of the shift registers during the operation of the gate drive circuit. For example, the opening order of shift register GOAN is earlier than the opening order of shift register GOA(N+1). In terms of physical arrangement, as shown in Figures 13 and 14, this disclosure can place shift register GOAN before shift register GOA(N+1); or as shown in Figures 11 and 12, it can place shift register GOAN after shift register GOA(N+1). Optionally, this disclosure uses gN (e.g., g1 to g9) to represent the scan voltage provided to the gate line by the output signal terminal Gout of the Nth level shift register GOAN (e.g., the 1st to 9th level shift registers).

[0074] Taking the first pixel P1, which belongs to the odd-numbered pixel PX1, and the second pixel P2, which belongs to the even-numbered pixel PX2, in the second row of Figure 10 as examples, the pixel charging diagram is shown in Figure 15.

[0075] The second pixel P2 is controlled by the second scan signal g2 on the third gate line G3. Influenced by the coupling capacitors of the third gate line G3 and the fourth gate line G4, its pixel voltage changes as follows: ① During the initial charging stage, it rapidly rises to the pre-charge voltage; ② Due to the influence of the coupling capacitor Cgs of the third gate line G3, when the third gate line G3 is closed, the pixel voltage drops by a value of ΔVp. Since the third gate line G3 is closed at this time, it cannot recover; ③ Due to the influence of the coupling capacitor Cgs' of the fourth gate line G4, the instantaneous rise has an upward pull effect on the pixel voltage, with a value of ΔVp'. Since the fourth gate line G4 is closed at this time, it cannot recover. ② and ③ occur at the same time point, as distinguished in the diagram; ④ Due to the influence of the coupling capacitor Cgs' of the fourth gate line G4, the instantaneous drop has a downward pull effect on the pixel voltage, with a value of ΔVp'. Since the fourth gate line G4 is closed at this time, it cannot recover. In summary, due to the influence of Cgs and Cgs', the final voltage drop of the second pixel P2 is (ΔVp+ΔVp'-ΔVp'), i.e., Vp. The main reason for the difference from the architecture shown in Figure 4 is that the charging times of the second scan signal g2 on the third gate line G3 and the fifth scan signal g5 on the fourth gate line G4 do not overlap.

[0076] Similarly, the first pixel P1 is controlled by the fifth scan signal g5 on the fourth gate line G4. Affected by the coupling voltages of the fourth gate line G4 and the third gate line G3, its pixel voltage changes as follows: ① In the initial charging stage, it quickly rises to the pre-charge voltage. Then, affected by the pull-down effect of the second scan signal g2 on the third gate line G3, the voltage drops by ΔVp'. However, since charging is not yet complete, it quickly recovers; this is not shown in the diagram. ② Affected by the coupling capacitance Cgs of the fourth gate line G4, when the fourth gate line G4 in this row is closed, the pixel voltage drops by ΔVp. Since the fourth gate line G4 is already closed at this time, it cannot recover. Therefore, affected by Cgs and Cgs', the final voltage drop of the first pixel P1 is ΔVp.

[0077] As can be seen from the above, the voltage change of the first pixel P1 and the second pixel P2 due to the influence of Cgs and Cgs' is ΔVp. Therefore, it can effectively solve the vertical stripe defects caused by the different voltage changes between different pixels PX. Furthermore, this disclosure only requires interchanging the driving order of the 2qth gate line and the (2q+1)th gate line, without changing the pixel layout within the display area AA, making it easy to implement.

[0078] In some embodiments, in the display substrate provided in the present disclosure, as shown in FIG11 and FIG12, a first-level shift register, a (2q+1)-level shift register, and a second-q-level shift register can be arranged sequentially along the column direction Y. For example, a first-level shift register GOA1, a third-level shift register GOA3, a second-level shift register GOA2, a fifth-level shift register GOA5, a fourth-level shift register GOA4, a seventh-level shift register GOA7, and a sixth-level shift register GOA6 can be sequentially arranged along the column direction Y. The ninth-stage shift register GOA9, etc., allows the first-stage shift register GOA1 to be in the same row as the first-row pixel PX, the (2q+1)th-stage shift register to be in the same row as the second-row pixel PX, and the second-row shift register to be in the same row as the (2q+1)th-row pixel PX. Electrical connections between the first-stage shift register GOA1 and the first gate line G1, the (2q+1)th-stage shift register and the second-row gate line, and the second-row shift register and the (2q+1)th-row gate line can be achieved without wiring. Furthermore, since the structures of each shift register are identical, this disclosure does not affect the basic internal design of the gate drive circuit; only the connection positions between the shift registers and multiple clock signal lines need to be adjusted, thus having virtually no impact on the overall layout design of the gate drive circuit. Optionally, as shown in Figures 11 to 14, the multiple clock signal lines located in the non-display area BB in this disclosure include clock signal lines CLK1 to CLK6, which are the first to sixth clock signal lines. Optionally, the i-th clock signal line is coupled to the clock signal terminal CLK of the [6(j-1)+i]-th stage shift register, where i is an integer greater than or equal to 1 and less than or equal to 6, and j is a positive integer.

[0079] In some embodiments, as shown in Figures 13 and 14, this disclosure may further arrange a first-level shift register, a second-level shift register, and a (2q+1)-level shift register sequentially along the column direction Y. For example, a first-level shift register GOA1, a second-level shift register GOA2, a third-level shift register GOA3, a fourth-level shift register GOA4, a fifth-level shift register GOA5, a sixth-level shift register GOA6, a seventh-level shift register GOA7, and an eighth-level shift register GOA8 may be arranged sequentially along the column direction Y. This allows the Nth-level shift register GOA1 to be located in the same row as the Nth row pixel PX. In this case, the external wiring of the output signal terminal Gout of the second-level shift register needs to be crossed with the external wiring of the output signal terminal Gout of the (2q+1)-level shift register to facilitate the electrical connection between the (2q+1)-level shift register and the 2q gate line, as well as the electrical connection between the second-level shift register and the (2q+1) gate line. Furthermore, since the shift registers have the same structure, this disclosure does not affect the basic design of the gate drive circuit. Only the connection relationship between the shift register and multiple gate lines needs to be adjusted, so it does not affect the overall layout design of the gate drive circuit.

[0080] In some embodiments, in the gate drive circuits shown in Figures 11 to 14, the q-th stage shift register and the (q+p)-th stage shift register can be cascaded, where p is an integer greater than or equal to 2. Specifically, the cascaded output terminal Gout_C of the q-th stage shift register is electrically connected to the input signal terminal IN of the (q+p)-th stage shift register, as illustrated in the figures with p=3 as an example. Optionally, the cascaded output terminal Gout_C of the (q+p')-th stage shift register of this disclosure is electrically connected to the reset signal terminal Rpu of the q-th stage shift register, as illustrated in the figures with p=3 as an example. The example given is p'=4. In some embodiments, the clock signal terminal CLK, the first power supply terminal VDD1, the second power supply terminal VDD2, the first reference signal terminal LVGL, the second reference signal terminal VGL, and the reset signal terminal TR of each shift register (e.g., GOA1 to GOA9) can be electrically connected to the corresponding signal lines CLK1 to 6, VD1, VDD2, LVGL, VGL, and STV0, respectively. The input signal terminal IN of the first to third level shift registers GOA1 to 3 can be electrically connected to the frame start signal terminal STV1.

[0081] In some embodiments, as shown in FIG10 and FIG16, the array substrate provided in the present disclosure may further include multiple data lines (e.g., D1 to D12) extending along the column direction Y and arranged along the row direction X in the display area AA; the pixel PX includes multiple sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B, etc.), and the sub-pixels in the same column (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B, etc.) are electrically connected to the same data line (e.g., D1 to D12). An adjacent odd-numbered pixel PX1 and an even-numbered pixel PX2 constitute a cycle period. In the cycle period, the data line corresponding to the nth column sub-pixel is connected to the data line corresponding to the (n+m)th column sub-pixel, where n is greater than or equal to 1 and less than or equal to the number of columns of sub-pixels in a group of pixels PX, and m is the number of columns of sub-pixels in a group of pixels PX.

[0082] For example, in Figure 10, two columns of pixels PX form a group, and there are four columns of pixels PX and 12 columns of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B, etc.) in one cycle, 1≤n≤6, m=6, that is, the data line D1 corresponding to the first column of sub-pixels is connected to the data line D7 corresponding to the seventh column of sub-pixels, the data line D2 corresponding to the second column of sub-pixels is connected to the data line D8 corresponding to the eighth column of sub-pixels, the data line D3 corresponding to the third column of sub-pixels is connected to the data line D9 corresponding to the ninth column of sub-pixels, the data line D4 corresponding to the fourth column of sub-pixels is connected to the data line D10 corresponding to the tenth column of sub-pixels, the data line D5 corresponding to the fifth column of sub-pixels is connected to the data line D11 corresponding to the eleventh column of sub-pixels, and the data line D6 corresponding to the sixth column of sub-pixels is connected to the data line D12 corresponding to the twelfth column of sub-pixels.

[0083] For example, in Figure 16, 4 columns of pixels PX form a group, and there are 8 columns of pixels PX and 24 columns of sub-pixels (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B, etc.) in one cycle. 1≤n≤12, m=12, that is, the data line D1 corresponding to the 1st column of sub-pixels is connected to the data line D13 corresponding to the 13th column of sub-pixels, the data line D2 corresponding to the 2nd column of sub-pixels is connected to the data line D14 corresponding to the 14th column of sub-pixels, the data line D3 corresponding to the 3rd column of sub-pixels is connected to the data line D15 corresponding to the 15th column of sub-pixels, the data line D4 corresponding to the 4th column of sub-pixels is connected to the data line D16 corresponding to the 16th column of sub-pixels, and the data line D5 corresponding to the 5th column of sub-pixels is connected to the data line D17 corresponding to the 17th column of sub-pixels. The data lines corresponding to the sub-pixels in the following columns are connected: D6 of the 6th column is connected to D18 of the 18th column; D7 of the 7th column is connected to D19 of the 19th column; D8 of the 8th column is connected to D20 of the 20th column; D9 of the 9th column is connected to D21 of the 21st column; D10 of the 10th column is connected to D22 of the 22nd column; D11 of the 11th column is connected to D23 of the 23rd column; and D12 of the 12th column is connected to D24 of the 24th column.

[0084] In Figure 10, with 12 columns of sub-pixels as a cycle, and the Mth (1≤M≤6) data line connected to the (M+6)th data line within one cycle, the data lines can only achieve one-line flipping, meaning the polarity of the data voltage on the data line is (+, -, +, -, +, -, ...). The H2line flipping method cannot be used, meaning the polarity of the data voltage on the data line is (+, -, -, +, +, -, -, +, ...). As shown in Figure 17, when the architecture shown in Figure 10 uses H2line flipping, the polarity of the display area AA in the row direction X is not uniformly arranged (the polarity in a minimum cycle, per column, is +, -, -, +, +, -, +, -, -, +, +, -, -, +, +, -, -, +, -, +, -, +, -, +, -, -, +, ...). That is, there are intervals between two columns with the same polarity and intervals between one column with the same polarity. When Figure 16 uses 24 sub-pixels as a cycle, it can simultaneously support both one-line flip and H2line flip designs. When H2line flip is used, the polarity of the display area AA in the row direction X is uniformly arranged (+, -, -, +, +, -, -, +, +, -, -, +, +, -, -, +, +, -, -, +, +, -, -, +, +, -, -, +, with every two columns having the same polarity, as shown in Figure 18.

[0085] The combination of the two drivers can effectively avoid image quality issues caused by certain special screen types, such as one-dot screens, where every other RGB pixel is lit. In this design, an H2line flip driver can be used to effectively avoid lateral crosstalk (H-Crosstalk) caused by fluctuations in the common voltage VCOM due to differences in data voltage polarity. As shown in Figure 19, subpixels filled with dot patterns are lit, while those not filled with dot patterns are not. In a one-dot screen (a common scenario for many end-users, where image quality is crucial, such as the common Excel Crosstalk screen), the pixel architecture shown in Figure 16 ensures that all lit pixels in the same row receive the same amount of positive (+) data voltage (e.g., Da1, Da4, Da5, Da8, Da9, Da12) and negative (-) data voltage (e.g., Da2, Da3, Da6, Da7, Da10, Da11). This ensures that fluctuations in data voltage cancel out the coupling of the common voltage VCOM, eliminating the risk of crosstalk.

[0086] Accordingly, this disclosure also provides a driving method for an array substrate including the pixel architecture shown in Figures 10 and 16, comprising:

[0087] Within one frame, a first-level shift register applies a scan voltage to the first gate line, a (2q+1)-level shift register applies a scan voltage to the second q gate lines, and a second q-level shift register applies a scan voltage to the (2q+1)th gate line. Data voltages of the same polarity are applied to the sub-pixels of a pixel in a single-column or double-column manner. Applying data voltages of the same polarity to the sub-pixels of a pixel in a single-column manner is equivalent to applying data voltage using a one-line flip method; applying data voltages of the same polarity to the sub-pixels of a pixel in a double-column manner is equivalent to applying data voltage using an H2line flip method. Optionally, the array substrate shown in Figure 10 uses one-line flip driving, while the array substrate shown in Figure 16 can use either one-line flip driving or H2line flip driving. Furthermore, using H2line flip driving can effectively improve the display quality of a one-dot image.

[0088] In some embodiments, this disclosure provides an array substrate including the pixel architecture shown in FIG20. FIG21 and FIG22 are schematic diagrams of a gate driving circuit structure corresponding to the pixel architecture shown in FIG20. In FIG20 to FIG22, the s-th stage shift register of the gate driving circuit is electrically connected to the s-th gate line, where s is a positive integer; the i-th clock signal line is coupled to the clock signal terminal of the [k*(j-1)+i]-th stage shift register, where k (e.g., i=6) is the total number of clock signal lines, i is an integer greater than or equal to 1 and less than or equal to k, and j is a positive integer. Furthermore, in Figure 20, at least one column of pixels PX is grouped together. The gate lines corresponding to the odd-numbered pixel PX1 (e.g., G2, G3, G6, G7) in the same row are different from the gate lines corresponding to the even-numbered pixel PX2 (e.g., G1, G4, G5, G8). One of the two gate lines corresponding to the odd-numbered pixel PX1 (e.g., G2 and G3, G4 and G5, G6 and G7) and the two gate lines corresponding to the even-numbered pixel PX2 (e.g., G1 and G4, G5 and G8) in each adjacent row (e.g., G2 and G3, G4 and G5, G6 and G7) is located between the two adjacent rows, and the other (e.g., G1 and G4, G5 and G8) is located on both sides of the two adjacent rows. This makes the pixels PX in each row of the odd-numbered pixel PX1 driven alternately by the even-odd row gate lines, and the pixels PX in each row of the even-numbered pixel PX2 driven alternately by the odd-even row gate lines.

[0089] Based on the analysis of Figure 4 above, it can be seen that the final pixel voltage difference between pixels PX controlled by odd-numbered row gate lines and pixels PX controlled by even-numbered row gate lines is ΔVp'. In Figure 20, pixels PX controlled by odd-numbered and even-numbered row gate lines are alternately set in both the row direction X and the column direction Y, so that the pixel voltage difference ΔVp' is arranged in a cross pattern, thus neutralizing the pixel brightness difference and eliminating the vertical stripe problem; and it does not change the pixel aperture ratio.

[0090] In some embodiments, as shown in FIG20, two columns of pixels PX are grouped together, or as shown in FIG23, four columns of pixels PX are grouped together. In both FIG20 and FIG23, a cycle is defined as an adjacent odd-numbered group of pixels PX1 and an even-numbered group of pixels PX2. Within the cycle, the data line corresponding to the nth column of sub-pixels is connected to the data line corresponding to the (n+m)th column of sub-pixels, where n is greater than or equal to 1 and less than or equal to the number of columns of sub-pixels in a group, and m is the number of columns of sub-pixels in a group. Since the electrical connection relationship between data lines in FIG20 is the same as that in FIG10, and the electrical connection relationship between data lines in FIG23 is the same as that in FIG16, the electrical connection relationship between data lines in FIG20 and FIG23 will not be described again here.

[0091] In some embodiments, as shown in Figure 24, the pixel architecture shown in Figure 20 is not suitable for H2line flip-mode driving; however, as shown in Figures 25 and 26, the pixel architecture shown in Figure 23 is suitable for H2line flip-mode driving and can solve the crosstalk problem caused by common voltage fluctuations in one-dot images. For specific principles, please refer to the relevant descriptions in Figures 17 to 19, which will not be elaborated upon here.

[0092] Accordingly, for the array substrates shown in Figures 20 and 23, the driving method includes:

[0093] Within one frame, scanning voltage is applied to the grid lines one by one, and data voltages of the same polarity are applied to the sub-pixels contained in the pixel in a manner of single-column (i.e., one-line flip) or double-column (i.e., H2line flip) interval. Optionally, the array substrate shown in Figure 20 adopts one-line flip driving, and the array substrate shown in Figure 23 can adopt either one-line flip driving or H2line flip driving. In the case of adopting H2line flip driving, the display quality of the one dot screen can be effectively improved.

[0094] Based on the same inventive concept, this disclosure provides a display panel, as shown in FIG27, including the array substrate 001 provided in this disclosure embodiment and a counter substrate 002 disposed opposite to the array substrate 001. Optionally, as shown in FIG27, the display panel provided in this disclosure embodiment may further have a liquid crystal layer 003 disposed between the array substrate 001 and the counter substrate 002, a first polarizer 004 disposed on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 disposed on the side of the counter substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0095] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG28, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0096] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0097] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0098] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0099] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple grid lines extend along the row direction and are arranged along the column direction in the display area; Multiple pixels are arranged in an array in the display area, with each row of pixels corresponding to two gate lines, and two gate lines between adjacent rows of pixels; at least one column of pixels forms a group, and the gate lines corresponding to odd-numbered pixels in a row are different from those corresponding to even-numbered pixels; the gate lines corresponding to odd-numbered pixels in each row are located on the same side of each row, and the gate lines corresponding to even-numbered pixels are located on the other side of each row; A gate driving circuit is located in the non-display area. The gate driving circuit includes multiple shift registers arranged in cascade. The first-stage shift register is electrically connected to the first gate line, the (2q+1)-stage shift register is electrically connected to the 2q-stage gate line, and the 2q-stage shift register is electrically connected to the (2q+1)-stage gate line, where q is a positive integer.

2. The array substrate as claimed in claim 1, wherein, The q-th shift register is cascaded with the (q+p)-th shift register, and the 1st-th shift register, the (2q+1)-th shift register, and the 2q-th shift register are arranged sequentially along the column direction, where p is an integer greater than or equal to 2.

3. The array substrate as described in claim 1 or 2, wherein, It also includes multiple data lines that extend along the column direction and are arranged along the row direction in the display area; The pixel includes multiple sub-pixels. Sub-pixels in the same column are electrically connected to the same data line. An odd number of pixels and an even number of pixels form a cycle. Within the cycle, the data line corresponding to the nth column of the sub-pixel is connected to the data line corresponding to the (n+m)th column of the sub-pixel. Here, n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

4. The array substrate according to any one of claims 1 to 3, wherein, The pixels in two columns are grouped together, or the pixels in four columns are grouped together.

5. The array substrate according to any one of claims 1 to 4, wherein, It also includes multiple clock signal lines located in the non-display area. The clock signal lines include 6 lines. The i-th clock signal line is coupled to the clock signal terminal of the [6(j-1)+i]-th stage shift register. i is an integer greater than or equal to 1 and less than or equal to 6, and j is a positive integer.

6. A driving method for an array substrate as described in any one of claims 1 to 5, wherein, include: Within one frame, the first-level shift register loads the scan voltage for the first gate line, the (2q+1)-level shift register loads the scan voltage for the second-q gate line, and the second-q-level shift register loads the scan voltage for the (2q+1)-level gate line. Data voltages of the same polarity are loaded onto the sub-pixels contained in the pixel in a single-column or double-column manner.

7. An array substrate, wherein, include: A substrate, the substrate including a display area; Multiple grid lines extend along the row direction and are arranged along the column direction in the display area; Multiple pixels are arranged in an array in the display area, with each row of pixels corresponding to two gate lines, and two gate lines between adjacent rows of pixels; at least one column of pixels forms a group, and the gate lines corresponding to odd-numbered pixels in the same row are different from the gate lines corresponding to even-numbered pixels; one of the two gate lines corresponding to odd-numbered pixels and the two gate lines corresponding to even-numbered pixels in each adjacent row is located between the two adjacent rows, and the other is located on both sides of the two adjacent rows.

8. The array substrate as claimed in claim 7, wherein, It also includes multiple data lines that extend along the column direction and are arranged along the row direction in the display area; The pixel includes multiple sub-pixels. Sub-pixels in the same column are electrically connected to the same data line. An odd number of pixels and an even number of pixels form a cycle. Within the cycle, the data line corresponding to the nth column of the sub-pixel is connected to the data line corresponding to the (n+m)th column of the sub-pixel. Here, n is greater than or equal to 1 and less than or equal to the number of columns of the sub-pixels in a group of pixels, and m is the number of columns of the sub-pixels in a group of pixels.

9. The array substrate as claimed in claim 8, wherein, The pixels in two columns are grouped together, or the pixels in four columns are grouped together.

10. The array substrate according to any one of claims 7 to 9, wherein, The substrate further includes a non-display area located on at least one side of the display area, and the array substrate further includes a gate driving circuit located in the non-display area. The gate driving circuit includes a plurality of shift registers cascaded together. The plurality of shift registers are arranged along the column direction in the order from the first-stage shift register to the last-stage shift register, wherein the s-th stage shift register is electrically connected to the s-th gate line, and s is a positive integer.

11. The array substrate as claimed in claim 10, wherein, It also includes multiple clock signal lines located in the non-display area, with the i-th clock signal line coupled to the clock signal terminal of the [k*(j-1)+i]-th stage shift register, where k is the total number of clock signal lines, i is an integer greater than or equal to 1 and less than or equal to k, and j is a positive integer.

12. A driving method for an array substrate as described in any one of claims 7 to 11, wherein, include: Within one frame, scan voltage is applied to the grid lines line by line, and data voltage of the same polarity is applied to the sub-pixels contained in the pixel in a single-column or double-column manner.

13. A display panel, wherein, include: The array substrate as described in any one of claims 1 to 5, 7 to 11.

14. A display device, wherein, Includes the display panel as described in claim 13.

Images