I / O driver and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide an I / O driver and an electronic device, used for improving the performance of an I / O driver. The I / O driver comprises a pull-up circuit, a pull-down circuit and an input / output end. The pull-up circuit is coupled between a power supply voltage end and the input / output end and is used for generating a pull-up voltage on the basis of a first control signal. The pull-down circuit is coupled between a reference ground voltage end and the input / output end and is used for generating a pull-down voltage on the basis of a second control signal. The input / output end is used for outputting the pull-up voltage and the pull-down voltage. A transistor in the pull-up circuit and / or the pull-down circuit is a three-dimensional field effect transistor. A two-dimensional field effect transistor is replaced with the three-dimensional field effect transistor, improving the performance of the I / O driver, and reducing the area of the I / O driver.

Description

I / O drivers, electronic devices

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 29, 2024, with application number 202410236121.X and invention name “I / O driver, electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to an I / O driver and an electronic device. Background Art

[0003] Memory can generally be categorized as either random access memory (RAM) or read-only memory (ROM). RAM is typically a volatile memory element that loses stored data when power is lost. ROM is typically a non-volatile memory element that retains stored data even when power is lost. Types of RAM include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0004] In DRAM design, signal integrity has a direct impact on DRAM performance in advanced high-speed data rate environments. Signal integrity is directly related to the performance of the DRAM's input / output (I / O) drivers. To optimize I / O driver performance, those skilled in the art use off-chip driver (OCD) technology, supported by metal oxide semiconductor (MOS) field-effect transistors, to calibrate the pull-up and pull-down capabilities of the I / O drivers, thereby improving I / O driver performance. However, the presence of MOS field-effect transistors can affect the impedance matching and signal characteristics of the I / O drivers.

[0005] Summary of the Invention

[0006] Embodiments of the present application provide an I / O driver and an electronic device for improving the performance of the I / O driver.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present application, an I / O driver is provided, comprising: a pull-up circuit, a pull-down circuit, and an input / output terminal. The pull-up circuit is coupled between a power supply voltage terminal and the input / output terminal, and is configured to generate a first voltage in response to a first control signal. The first voltage is, for example, a high-level voltage (e.g., a power supply voltage) indicating a pulled-up potential. The pull-down circuit is coupled between a reference ground voltage terminal and the input / output terminal, and is configured to generate a second voltage in response to a second control signal. The second voltage is, for example, a low-level voltage (e.g., a reference ground voltage) indicating a pulled-down potential. The input / output terminal is configured to output the first and second voltages. The pull-up circuit comprises a first transistor, a control electrode of the first transistor being configured to receive the first control signal, a first electrode of the first transistor being coupled to the power supply voltage terminal, and a second electrode of the first transistor being coupled to the input / output terminal. The pull-down circuit comprises a second transistor, a control electrode of the second transistor being configured to receive the second control signal, a first electrode of the second transistor being coupled to the reference ground voltage terminal, and a second electrode of the second transistor being coupled to the input / output terminal. The first transistor is a three-dimensional field-effect transistor, or the second transistor is a three-dimensional field-effect transistor, or both the first and second transistors are three-dimensional field-effect transistors.

[0009] Because the first transistor and / or the second transistor are three-dimensional field-effect transistors, which occupy a smaller area than two-dimensional field-effect transistors, replacing MOS transistors in conventional pull-up and / or pull-down circuits with three-dimensional field-effect transistors can reduce the area overhead of the I / O driver. In particular, since the data transmission interface and the command transmission interface in the memory are each coupled to an I / O driver (i.e., the memory includes multiple I / O drivers), the area savings are significant. Furthermore, resistors coupled to the three-dimensional field-effect transistors are no longer required in the pull-up and pull-down circuits, simplifying the structures of the pull-up and pull-down circuits. Furthermore, by utilizing the high linearity and low total drain capacitance of three-dimensional field-effect transistors to replace MOS transistors in conventional pull-up and / or pull-down circuits, excellent linearity and reduced I / O interface capacitance can be achieved at the I / O driver, significantly improving I / O interface speed, reducing power consumption, and optimizing multiple performance indicators. In addition, the 3D field effect transistor is a back-end transistor and is usually made in a metal layer closer to the pad. The connection between the 3D field effect transistor and the pad is shorter, which can reduce parasitic capacitance and parasitic resistance.

[0010] In a possible implementation, the pull-up circuit includes a plurality of first transistors. Using a plurality of first transistors instead of a single first transistor can not only achieve current stability but also suppress mismatch problems.

[0011] In one possible implementation, the pull-down circuit includes a plurality of second transistors. Using a plurality of second transistors instead of a single second transistor can not only achieve current stability but also suppress mismatch problems.

[0012] In one possible implementation, the I / O driver further includes a trimming control circuit, and the pull-up circuit further includes a pull-up trimming circuit. The pull-up trimming circuit is connected in series with one or more first transistors; and the pull-up trimming circuit is further coupled to the trimming control circuit.

[0013] As current high-speed memories demand ever-increasing speed, the accuracy and linearity of impedance matching vary across different processes, voltages, and temperatures, significantly impacting I / O driver speed. Simply adjusting the impedance matching of the pull-up and pull-down circuits within the calibration circuitry itself sometimes fails to meet the required accuracy. By implementing a trim control circuit and a pull-up trimming circuit, further fine-tuning the pull-up circuit impedance is achieved, improving impedance matching performance and boosting DRAM speed and yield.

[0014] In one possible implementation, the I / O driver further includes a trimming control circuit, and the pull-down circuit further includes a pull-down trimming circuit. The pull-down trimming circuit is connected in series with one or more second transistors; the pull-down trimming circuit is further coupled to the trimming control circuit. By providing the trimming control circuit and the pull-down trimming circuit, further fine-tuning of the pull-down circuit impedance can be achieved, thereby further improving impedance matching performance and increasing DRAM speed and yield.

[0015] In one possible implementation, the pull-up trimming circuit includes a plurality of third transistors, which are three-dimensional field-effect transistors. The three-dimensional field-effect transistors can save the area of ​​the I / O driver.

[0016] In one possible implementation, the pull-down trimming circuit includes a plurality of fourth transistors, which are three-dimensional field-effect transistors. The three-dimensional field-effect transistors can save the area of ​​the I / O driver.

[0017] In one possible implementation, the trimming control circuit includes a test decoding circuit, a programming voltage generating circuit, an anti-fuse circuit, a latched pull-up signal circuit, and a latched pull-down signal circuit. The test decoding circuit receives a first compensation signal and outputs a programming selection signal; the programming voltage generating circuit is used to generate a programming voltage; the anti-fuse circuit includes a plurality of fifth transistors, each of which is a three-dimensional field-effect transistor; the control electrodes of the fifth transistors are coupled to the programming voltage generating circuit, the first electrodes of the fifth transistors are coupled to the test decoding circuit, and the second electrodes of the fifth transistors are coupled to the latched pull-up signal circuit and the latched pull-down signal circuit, respectively; the output of the latched pull-up signal circuit is coupled to the pull-up trimming circuit; and the output of the latched pull-down signal circuit is coupled to the pull-down trimming circuit. This is a structurally simple implementation.

[0018] In one possible implementation, the programming voltage generation circuit includes an oscillator and a charge pump. The oscillator is used to receive a power supply voltage and output an oscillation signal, while the charge pump is used to receive the oscillation signal and output the programming voltage. This is a simple implementation.

[0019] In one possible implementation, the trimming control circuit further includes a programming voltage terminal coupled to the control electrode of the fifth transistor. The programming voltage terminal can serve as a backup external voltage port. When the programming voltage generation circuit fails to properly provide the programming voltage, the programming voltage terminal can be used to provide the programming voltage, thereby ensuring normal operation of the circuit.

[0020] In one possible implementation, the trim control circuit further includes an address multiplexing circuit coupled between the test decoding circuit and the antifuse circuit. Because the provision of a fifth transistor increases the area of ​​the I / O driver, the number of fifth transistors is typically reduced to save area. However, the I / O driver requires a large address range, which can lead to a mismatch between a small number of fifth transistors and a large number of addresses. By providing an address multiplexing circuit between the test decoding circuit and the antifuse circuit, the I / O driver can continue to operate normally even in the event of a mismatch between the address and the number.

[0021] In one possible implementation, the I / O driver further includes a compensation circuit configured to output a first compensation signal. The compensation circuit detects the impact of the process on the impedance of the pull-up circuit and the pull-down circuit and compensates for it through the trimming control circuit. This allows for more refined adjustment of the impedance of the pull-up circuit and the pull-down circuit, further improving signal integrity.

[0022] In one possible implementation, the compensation circuit includes a process sensor, an analog-to-digital converter, a decoder, and a code position adjuster. The process sensor is used to detect the process and generate a first compensation signal. The analog-to-digital converter is used to convert the first compensation signal into a first digital signal. The decoder is used to receive the first digital signal and output a first decoded signal. The code position adjuster is used to receive the first decoded signal and output the first compensation signal. This is a simple implementation.

[0023] In one possible implementation, the I / O driver further includes a pre-driver circuit configured to output a first pull-up signal and a first pull-down signal; the first control signal includes the first pull-up signal, and the second control signal includes the first pull-down signal. This is a simple implementation.

[0024] In one possible implementation, the I / O driver further includes a compensation circuit configured to output a second compensation signal, and the pre-driver circuit is configured to receive the second compensation signal. By adding the compensation circuit to the I / O driver, the effects of voltage and temperature on the impedance of the pull-up and pull-down circuits can be calibrated from the pre-driver circuit side, thereby ensuring impedance matching between the pull-up and pull-down circuits to a greater extent and further improving signal integrity.

[0025] In one possible implementation, the compensation circuit includes a temperature sensor, an analog-to-digital converter, a decoder, and a code position adjuster. The temperature sensor is used to detect temperature and generate a second compensation signal. The analog-to-digital converter is further used to convert the second compensation signal into a second digital signal. The decoder is further used to receive the second digital signal and output a second decoded signal. The code position adjuster is further used to receive the second decoded signal and output a second compensation signal. This is a simple implementation.

[0026] In one possible implementation, the I / O driver further includes a calibration circuit; the calibration circuit is coupled to a power supply voltage terminal, a reference ground voltage terminal, a pull-up threshold voltage terminal, a pull-down threshold voltage terminal, and a calibration reference voltage terminal, and is configured to output a second pull-up signal and a second pull-down signal; the first control signal further includes a second pull-up signal, and the second control signal further includes a second pull-down signal. Because the resistors connected to the input / output terminals (the equivalent resistances of the pull-up circuit and the pull-down circuit) are used to improve signal integrity, precise resistance values ​​are required. Due to variations in process, voltage, and temperature, the equivalent resistance values ​​of the pull-up circuit and the pull-down circuit are not precise. By providing a calibration circuit, the equivalent resistances of the pull-up circuit and the pull-down circuit can be calibrated, thereby improving signal integrity and supporting higher data rates.

[0027] In one possible implementation, the pull-up circuit further includes a first logic operation circuit configured to receive a first pull-up signal and a second pull-up signal and output the first signal; the control electrode of the first transistor is coupled to the output of the first logic operation circuit. The pull-down circuit further includes a second logic operation circuit configured to receive the first pull-down signal and the second pull-down signal and output the second signal; the control electrode of the second transistor is coupled to the output of the second logic operation circuit. This is a structurally simple implementation.

[0028] According to a second aspect of an embodiment of the present application, an electronic device is provided, including an I / O driver and a circuit board, wherein the I / O driver is arranged on the circuit board; the I / O driver includes the I / O driver of the first aspect.

[0029] The electronic device provided in the second aspect of the embodiment of the present application includes the I / O driver provided in the first aspect, and its beneficial effects are the same as those of the I / O driver provided in the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1A is a diagram illustrating an electronic device according to an embodiment of the present invention;

[0031] FIG1B is an architectural diagram of a memory provided in an embodiment of the present application;

[0032] FIG2 is an architecture diagram of an I / O driver provided in an embodiment of the present application;

[0033] FIG3 is an architecture diagram of an I / O driver provided in an embodiment of the present application;

[0034] FIG4 is an architecture diagram of an I / O driver provided in an embodiment of the present application;

[0035] FIG5 is an architecture diagram of an I / O driver provided in an embodiment of the present application;

[0036] FIG6 is an architecture diagram of an I / O driver provided in an embodiment of the present application;

[0037] FIG7 is an architectural diagram of an I / O driver provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0039] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0040] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative descriptions and clarifications, and may change accordingly according to changes in the orientation of the components in the drawings.

[0041] In the embodiments of this application, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, "connection" can mean fixed connection, detachable connection, or integration; it can mean direct connection or indirect connection through an intermediate medium. In addition, the term "coupling" can mean direct electrical connection or indirect electrical connection through an intermediate medium. The term "contact" can mean direct contact or indirect contact through an intermediate medium.

[0042] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0043] The transistors involved in the embodiments of the present application may be metal oxide semiconductor (MOS) field effect transistors (hereinafter referred to as MOS transistors). In the embodiments of the present application, the control terminal of the transistor may refer to the gate of the transistor; in one possible embodiment, the first terminal of the transistor may refer to the source, and the second terminal may refer to the drain; in another possible embodiment, the first terminal of the transistor may refer to the drain, and the second terminal may refer to the source.

[0044] The embodiment of the present application provides an electronic device, which is, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, and a communication electronic product. Among them, consumer electronic products are such as mobile phones, tablet computers, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products are such as smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products are such as car navigation systems, car-mounted high-density digital video discs (DVDs), etc. Financial terminal products are such as automated teller machines (ATMs), self-service terminals, etc. Communication electronic products are such as communication equipment such as servers, memories, radars, base stations, etc. The embodiment of the present application does not impose any special restrictions on the specific forms of the above-mentioned electronic devices.

[0045] FIG1A is an architecture diagram of an electronic device provided in an embodiment of the present application.

[0046] Take an electronic device as an example. As shown in FIG1A , the electronic device 1 includes components such as a memory 11 , a processor 12 , an input device 13 , and an output device 14 .

[0047] Those skilled in the art will understand that the architecture of the electronic device 1 shown in FIG1A does not constitute a limitation on the electronic device 1. The electronic device 1 may include more or fewer components than those shown in FIG1A, or may combine some of the components shown in FIG1A, or may have a different arrangement of components than that shown in FIG1A.

[0048] The memory 11 is used to store software programs and modules. The memory 11 mainly includes a program storage area and a data storage area. The program storage area can store and back up an operating system, at least one application required for a function (such as a sound playback function, an image playback function, etc.). The data storage area can store data created based on the use of the electronic device 1 (such as audio data, image data, a phone book, etc.). The memory 11 may include, for example, random access memory (RAM), dynamic random access memory (DRAM), read-only memory (ROM), etc., wherein the random access memory may include, for example, ferroelectric memory, phase change memory, or magnetic memory.

[0049] The processor 12 is the control center of the electronic device 1. It connects the various components of the electronic device 1 using various interfaces and lines. By running or executing software programs and / or modules stored in the memory 11 and accessing data stored in the memory 11, it performs various functions of the electronic device 1 and processes data, thereby monitoring the entire electronic device 1. The processor 12 is, for example, a controller chip.

[0050] The input device 13 is used to receive input digital or character information and generate key signal input related to user settings and function control of the electronic device. For example, the input device 13 may include a touch screen or other input devices. The input digital or character information received by the input device 13 and the key signal input related to user settings and function control of the electronic device may be stored in the memory 11.

[0051] The output device 14 is used to output the input of the input device 13 and output a signal corresponding to the data in the memory 11. For example, the output device 14 outputs a sound signal or a video signal.

[0052] FIG1B is an architectural diagram of a memory provided in an embodiment of the present application.

[0053] Memory 11 is exemplified. Memory 11 can be, for example, a DRAM chip. As shown in FIG1B , memory 11 includes a substrate, a memory array disposed on the substrate, a controller (or logic circuit), and an input / output (I / O) interface. The I / O interface is used to implement signal transmission between memory 11 and a system bus.

[0054] The I / O interface includes an I / O driver 10 , which is used to receive a data signal data output by the controller and transmit data to a processor 12 (eg, a controller chip) in the electronic device 1 through the I / O interface under the control of the controller.

[0055] In the design of memory 11, in advanced high-speed data rate environments, signal integrity may be affected by impedance mismatch between the channel path from memory 11 to processor 12 and the I / O driver 10. Furthermore, variations in process-voltage-volume-temperature (PVT) can also alter the electrical characteristics of the I / O driver 10, causing deviations from the desired signal level.

[0056] In some embodiments, an off-chip driver (OCD) technology supported by MOS transistors is used to calibrate the pull-up capability and the pull-down capability of the I / O driver 10 .

[0057] For example, an N-type MOS transistor + resistor Res is usually used to design the OCD. By adjusting the sizes of different transistors in the I / O driver 10 and the number of transistors in operation, impedance matching is performed on the channel path.

[0058] Due to the impedance variation caused by the non-ideal linearity of MOS transistors, the total gate capacitance (cgg) of the transistors in the I / O driver 10 is large, resulting in a large I / O interface capacitance (Cio). The resistance Res also varies with PVT. Furthermore, the parasitic capacitance and resistance (RC) generated by the interconnections between the various devices in the I / O driver 10 also affect the final impedance matching and signal characteristics. This makes impedance matching between the channel path and the I / O driver 10 still a significant challenge.

[0059] FIG2 is an architectural diagram of an I / O driver provided in an embodiment of the present application.

[0060] An embodiment of the present application provides an I / O driver. As shown in FIG2 , the I / O driver 10 includes an off-chip driver (OCD). The OCD includes a pull-up circuit 20 , a pull-down circuit 30 , and an input / output terminal IO.

[0061] In the embodiment of the present application, the input / output end (or input / output pad, input / output pin, etc.) IO can be, for example, an interface for transmitting data (data in or out, DQ) or an interface for transmitting commands (command, CA).

[0062] The pull-up circuit 20 is coupled between the power supply voltage terminal VDD and the input / output terminal IO and is configured to generate a first voltage in response to a first control signal U. The first voltage is, for example, a high-level voltage (e.g., a power supply voltage) indicating a pull-up potential. The pull-down circuit 30 is coupled between the reference ground voltage terminal VSS and the input / output terminal IO and is configured to generate a second voltage in response to a second control signal D. The second voltage is, for example, a low-level voltage (e.g., a reference ground voltage) indicating a pull-down potential. The input / output terminal IO is configured to output the aforementioned first and second voltages.

[0063] The I / O driver 10 may include a pull-up circuit 20, or may include multiple pull-up circuits 20. FIG2 illustrates an example of an I / O driver 10 including multiple pull-up circuits 20. The I / O driver 10 may include a pull-down circuit 30, or may include multiple pull-down circuits 30. FIG2 illustrates an example of an I / O driver 10 including multiple pull-down circuits 30.

[0064] The pull-up circuit 20 includes a first transistor J1, wherein a control electrode of the first transistor J1 is configured to receive a first control signal U. The control electrode of the first transistor J1 may directly or indirectly receive the first control signal U. A first electrode of the first transistor J1 is coupled to a power supply voltage terminal VDD, and a second electrode of the first transistor J1 is coupled to an input / output terminal IO.

[0065] The pull-up circuit 20 may include a first transistor J1, or the pull-up circuit 20 may include multiple first transistors J1. For example, as shown in FIG2 , the pull-up circuit 20 includes multiple first transistors J1 coupled in parallel, and the multiple first transistors J1 may be arranged in an array, for example. One or more first transistors J1, for example, form a pull-up adaptive impedance (ZQ) generating circuit (adaptive zone qualifier generation). When the pull-up circuit 20 includes multiple first transistors J1, the multiple first transistors J1 are controlled by the same first control signal U, and the first control signal U can be understood as a signal string. For example, the first control signal U is a 6-bit coding.

[0066] Using multiple first transistors J1 instead of a single first transistor J1 can not only achieve current stability but also suppress mismatch problems.

[0067] When the I / O driver 10 includes multiple pull-up circuits 20, each pull-up circuit 20 may include one or more first transistors J1. The first transistors J1 in the same pull-up circuit 20 are coupled in parallel, while the first transistors J1 in different pull-up circuits 20 are not coupled in parallel. The first transistors J1 in different pull-up circuits 20 can be coupled to the same power supply voltage terminal VDD and the same input / output terminal IO, but the control electrodes of the first transistors J1 in different pull-up circuits 20 are not coupled, that is, the multiple pull-up circuits 20 do not receive the same first control signal U.

[0068] The pull-down circuit 30 includes a second transistor J2 , a control electrode of which is used to receive a second control signal D, a first electrode of which is coupled to the reference ground voltage terminal VSS, and a second electrode of which is coupled to the input / output terminal IO.

[0069] The pull-down circuit 30 may include a second transistor J2, or may include multiple second transistors J2. For example, as shown in FIG2 , the pull-down circuit 30 includes multiple second transistors J2 coupled in parallel, and the multiple second transistors J2 may be arranged in an array, for example. One or more second transistors J2 may form a pull-down adaptive ZQ generation circuit, for example. When the pull-down circuit 30 includes multiple second transistors J2, the multiple second transistors J2 are controlled by the same second control signal D, and the second control signal D may be understood as a signal string. For example, the second control signal D is a 6-bit encoding.

[0070] Using multiple second transistors J2 instead of a single second transistor J2 can not only achieve current stability but also suppress the imbalance problem.

[0071] When the I / O driver 10 includes multiple pull-down circuits 30, each pull-down circuit 30 may include one or more second transistors J2. The second transistors J2 in the same pull-down circuit 30 are coupled in parallel, while the second transistors J2 in different pull-down circuits 30 are not coupled in parallel. The second transistors J2 in different pull-down circuits 30 may be coupled to the same reference ground voltage terminal VSS and the same input / output terminal IO, but the control electrodes of the second transistors J2 in different pull-down circuits 30 are not coupled, that is, the multiple pull-down circuits 30 do not receive the same second control signal D.

[0072] In some embodiments, the first transistor J1 is a three-dimensional field effect transistor.

[0073] In some other embodiments, the second transistor J2 is a three-dimensional field effect transistor.

[0074] In some other embodiments, as shown in FIG. 2 , both the first transistor J1 and the second transistor J2 are three-dimensional field effect transistors.

[0075] The 3D field effect transistor may also be referred to as a backend of line (BEOL) transistor. For example, the 3D field effect transistor may be a junction field-effect transistor (JFET).

[0076] Because the first transistor J1 or the second transistor J2 is a three-dimensional field-effect transistor, which occupies a smaller area than a two-dimensional field-effect transistor, replacing the MOS transistors in the pull-up circuit 20 and / or pull-down circuit 30 in a conventional OCD with a three-dimensional field-effect transistor can reduce the area overhead of the I / O driver 10. In particular, the data transmission interface DQ and the command transmission interface CA are each coupled to the I / O driver 10, resulting in a significant area saving. Furthermore, the pull-up circuit 20 and the pull-down circuit 30 do not need resistors coupled to the three-dimensional field-effect transistors, simplifying the structures of the pull-up circuit 20 and the pull-down circuit 30. Furthermore, by leveraging the high linearity and low total drain capacitance (Cdd) of three-dimensional field-effect transistors, replacing the MOS transistors in the pull-up circuit 20 and / or pull-down circuit 30 in a conventional OCD with them can achieve excellent linearity and reduced I / O interface capacitance (Cio) at the I / O driver 10, significantly improving I / O interface speed, reducing power consumption, and optimizing multiple performance indicators. In addition, the 3D field-effect transistor is a back-end transistor and is usually fabricated on a metal layer closer to the pad. The connection between the 3D field-effect transistor and the pad is shorter, which can reduce parasitic capacitance and parasitic resistance.

[0077] FIG3 is an architecture diagram of an I / O driver provided in an embodiment of the present application.

[0078] In some embodiments, as shown in FIG3 , the I / O driver 10 further includes a pre-driver circuit 40. The pre-driver circuit 40 can, for example, receive internal data and output a first pull-up signal U1 and a first pull-down signal D1. The first control signal U includes the first pull-up signal U1, and the second control signal D includes the first pull-down signal D1.

[0079] For example, the present embodiment does not limit the structure of the driving circuit 40, and the related art and the driving circuit 40 are applicable to the present embodiment. For example, the first pull-up signal U1 and the first pull-down signal D1 are 6-bit coding.

[0080] In some embodiments, the off-chip system includes multiple pull-up circuits 20, and the pre-driver circuit 40 is used to output multiple first pull-up signals U1. The off-chip system includes multiple pull-down circuits 30, and the pre-driver circuit 40 is used to output multiple first pull-down signals D1.

[0081] In some embodiments, as shown in FIG3 , the first control signal U further includes a first pull-up signal U1 and a second pull-up signal U2. The pull-up circuit 20 further includes a first logic operation circuit 21, which is configured to receive the first pull-up signal U1 and the second pull-up signal U2 and output a first signal. The control electrode of the first transistor J1 is coupled to the output terminal of the first logic operation circuit 21 and is configured to receive the first signal to control the number of times the first transistor J1 is turned on, thereby achieving impedance matching.

[0082] For example, the first control signal U is a 6-bit code. A one-bit instruction can control a group of transistors. Each group includes one or more first transistors J1 coupled in parallel. Instructions of different bits control different groups of transistors.

[0083] For example, the first logic operation circuit 21 includes a first NAND gate and a first inverter. The two input terminals of the first NAND gate are respectively used to receive the first pull-up signal U1 and the second pull-up signal U2. The first NAND gate performs a NAND operation on the first pull-up signal U1 and the second pull-up signal U2 and outputs the result to the first inverter. The first inverter inverts the received signal and outputs the result as the first signal.

[0084] Alternatively, for example, the first logic operation circuit 21 includes a first AND gate, and the two input ends of the first AND gate are used to receive the first pull-up signal U1 and the second pull-up signal U2 respectively. After the first AND gate performs an AND operation on the first pull-up signal U1 and the second pull-up signal U2, the operation result is output as the first signal.

[0085] Of course, the above is merely an illustration of the pull-up circuit 20 provided in the embodiment of the present application, and is not intended to limit the pull-up circuit 20 in the embodiment of the present application.

[0086] The second pull-up signal U2 can be understood as a calibration signal. After performing an AND operation on the internally indicated first pull-up signal U1 and the calibrated second pull-up signal U2, the accuracy of impedance matching can be improved.

[0087] In some embodiments, as shown in FIG3 , the second control signal D includes a first pull-down signal D1 and a second pull-down signal D2. The pull-down circuit 30 further includes a second logic operation circuit 31, which is configured to receive the first pull-down signal D1 and the second pull-down signal D2 and output a second signal. The control electrode of the second transistor J2 is coupled to the output of the second logic operation circuit 31 and is configured to receive the second signal to control the number of times the second transistor J2 is turned on, thereby achieving impedance matching.

[0088] For example, the second control signal D is a 6-bit code. A one-bit instruction can control a group of transistors. Each group includes one or more second transistors J2 coupled in parallel. Instructions of different bits control different groups of transistors.

[0089] For example, the second logic operation circuit 31 includes a second NAND gate and a second inverter. The two input terminals of the second NAND gate are respectively used to receive the first pull-down signal D1 and the second pull-down signal D2. The second NAND gate performs a NAND operation on the first pull-down signal D1 and the second pull-down signal D2 and outputs the result to the second inverter. The second inverter inverts the received signal and outputs the result as the second signal.

[0090] Alternatively, for example, the second logic operation circuit 31 includes a second AND gate, and the two input ends of the second AND gate are used to receive the first pull-down signal D1 and the second pull-down signal D2 respectively. After the second AND gate performs an AND operation on the first pull-down signal D1 and the second pull-down signal D2, the operation result is output as the second signal.

[0091] Of course, the above is merely an illustration of the pull-down circuit 30 provided in the embodiment of the present application, and is not intended to limit the pull-down circuit 30 in the embodiment of the present application.

[0092] The second pull-down signal D2 can be understood as a calibration signal. After performing an AND operation on the internally indicated first pull-down signal D1 and the calibrated second pull-down signal D2, the accuracy of impedance matching can be improved.

[0093] In some embodiments, as shown in FIG. 3 , the I / O driver 10 further includes a calibration circuit 50 . The calibration circuit 50 may be, for example, a ZQ calibration circuit known in the art.

[0094] Calibration circuit 50 is coupled to power supply voltage terminal VDD, reference ground voltage terminal VSS, pull-up threshold voltage terminal Vref-u, pull-down threshold voltage terminal Vref-d, and calibration reference voltage terminal ZQ, and is configured to output the aforementioned second pull-up signal and second pull-down signal. Calibration circuit 50 is configured to receive a calibration start signal and then, based on the calibration start signal, awaken the circuit modules used for calibration. For example, a ZQ calibration start command may be issued when the DRAM is powered on.

[0095] The calibration circuit 50 may be any ZQ calibration circuit in the related art. The embodiment of the present application does not limit the structure of the calibration circuit 50 , and FIG3 is only a schematic diagram.

[0096] In some embodiments, as shown in FIG3 , the calibration circuit 50 includes a pull-up driver 51 , a first counter 52 , a first comparator 53 , a pull-down driver 54 , a second counter 55 , a second comparator 56 , and a resistor R.

[0097] The pull-up driver 51 is a driver circuit that provides pull-up impedance matching for the I / O driver 10, while the pull-down driver 54 is a driver circuit that provides pull-down impedance matching for the I / O driver 10. The first transistor J1 and the second transistor J2 primarily match the channel impedance by the number of switches in the array. The first counter 52 is used to select the number of first transistors J1 in the pull-up circuit 20, and the second counter 55 is used to select the number of second transistors J2 in the pull-down circuit 30. The first comparator 53 is used to determine whether to activate the pull-up driver 51, while the second comparator 56 is used to determine whether to activate the pull-down driver 54. The pre-driver circuit 40 is used to select the number of pull-up circuits 20 and pull-down circuits 30 and serves as a connection circuit between the data signal output by the controller and the pull-up and pull-down drivers 51 and 52.

[0098] The pull-up driver 51 and the pull-down driver 54 are coupled in series between the power supply voltage terminal VDD and the reference ground voltage terminal VSS. The pull-up driver 51 is located near the power supply voltage terminal VDD, and the pull-down driver 54 is located near the reference ground voltage terminal VSS. A first input of a first comparator 53 is coupled between the pull-up driver 51 and the pull-down driver 54. A second input of the first comparator 53 is coupled to the pull-up threshold voltage terminal Vref-u. An output of the first comparator 53 is coupled to a first counter 52. The first counter 52 is also coupled to the pull-up driver 51 and the pull-up circuit 20. A resistor R is coupled between the calibration reference voltage terminal ZQ and the power supply voltage terminal VDD. A first input of a second comparator 56 is coupled to the calibration reference voltage terminal ZQ. A second input of the second comparator 56 is coupled to the pull-down threshold voltage terminal Vref-d. An output of the second comparator 56 is coupled to a second counter 55. The second counter 55 is also coupled to the pull-down driver 54 and the pull-down circuit 30.

[0099] For example, the calibration circuit 50 is used to receive a calibration start signal, and then, based on the calibration start signal, wake up the target circuit module for calibration (here, the pull-up driver 51 and the pull-down driver 54). When the memory 11 is in the power-on state, a calibration start signal can be issued. After the operation is completed by the internal first counter 52, the first comparator 53, the second counter 55 and the second comparator 56, the second pull-up signal U2 required by the corresponding pull-up circuit 20 and the second pull-down signal D2 required by the pull-down circuit 30 are output.

[0100] Because the resistors connected to the input / output terminals IO (the equivalent resistances of the pull-up circuits 20 and 30) are used to improve signal integrity, precise resistance values ​​are required. Due to PVT variations, the equivalent resistances of the pull-up circuits 20 and 30 are not precise. By providing a calibration circuit 50, the equivalent resistances of the pull-up circuits 20 and 30 can be calibrated, thereby improving signal integrity and supporting higher data rates.

[0101] FIG4 is an architectural diagram of an I / O driver provided in an embodiment of the present application.

[0102] In some embodiments, as shown in FIG4 , the I / O driver 10 further includes a compensation circuit 60 configured to output a second compensation signal, and the pre-driver circuit 40 configured to receive the second compensation signal. The second pull-up signal U2 and the second pull-down signal D2 output by the pre-driver circuit 40 are compensated signals to compensate for temperature errors.

[0103] The compensation circuit 60 may be, for example, a temperature compensation circuit or a PVT compensation circuit. The embodiment of the present application does not limit the structure of the compensation circuit 60 , and all compensation circuits in related technologies are applicable to the embodiment of the present application.

[0104] In some embodiments, as shown in FIG. 4 , the compensation circuit 60 includes a temperature sensor (TS) 61 , a digital to analog converter (DAC) 62 , a decoder 63 , and a trimming code 64 .

[0105] The temperature sensor 61 is used to detect temperature and generate a second compensation signal. The temperature sensor 61 senses temperature changes through self-sensing, that is, after starting the compensation circuit 60, internal self-regulation can be achieved. The analog-to-digital converter 62 is also used to convert the second compensation signal (analog signal) obtained by temperature sensing into a second digital signal. The decoder 63 is also used to receive the second digital signal and output a second decoded signal. The code position adjuster 64 is also used to receive the second decoded signal and output the above-mentioned second compensation signal. The decoder 63 and the code position adjuster 64 feed back the temperature compensation to the pre-driver circuit 40.

[0106] For example, the analog-to-digital converter 62 is coupled to the output end of the temperature sensor 61 , the decoder 63 is coupled to the output end of the analog-to-digital converter 62 , and the code bit adjuster 64 is coupled to the output end of the decoder 63 .

[0107] By adding the compensation circuit 60 to the I / O driver 10, the influence of voltage and temperature on the impedance of the pull-up circuit 20 and the pull-down circuit 30 can be calibrated from the side of the pre-driver circuit 40, thereby ensuring the impedance matching of the pull-up circuit 20 and the pull-down circuit 30 to a greater extent and further improving the signal integrity.

[0108] FIG5 is an architectural diagram of an I / O driver provided in an embodiment of the present application.

[0109] In some embodiments, as shown in FIG. 5 , the I / O driver 10 further includes a trimming control circuit 70 . The trimming control circuit 70 is configured to output a trimming control signal, for example.

[0110] The pull-up circuit 20 further includes a pull-up trimming circuit 22, which is connected in series with one or more first transistors J1. The pull-up trimming circuit 22 is also coupled to the trimming control circuit 70. For example, the pull-up trimming circuit 22 is configured to receive a trimming control signal output by the trimming control circuit 70 to adjust the impedance of the path of the first transistors J1 connected in series with the pull-up trimming circuit 22.

[0111] For example, in FIG5 , only one first transistor J1 is coupled in series with the pull-up trimming circuit 22. Alternatively, more than one first transistor J1 may be coupled in series with the pull-up trimming circuit 22. Multiple first transistors J1 may be coupled to the same pull-up trimming circuit 22, or multiple first transistors J1 may be coupled to different pull-up trimming circuits 22. The pull-up trimming circuit 22 may be located between the first electrode of the first transistor J1 and the power supply voltage terminal VDD, or between the second electrode of the first transistor J1 and the input / output terminal IO.

[0112] For example, the pull-up trimming circuit 22 includes one or more third transistors J3, each of which is a three-dimensional field-effect transistor. The third transistors J3 can be turned on or off under the control of a trimming control signal output by the trimming control circuit 70. The plurality of third transistors J3 can be located, for example, around the periphery of the first transistor J1 array.

[0113] The pull-down circuit 30 further includes a pull-down trimming circuit 32, which is connected in series with one or more second transistors J2. The pull-down trimming circuit 32 is also coupled to the trimming control circuit 70. For example, the pull-down trimming circuit 32 is configured to receive a trimming control signal output by the trimming control circuit 70 to adjust the impedance of the path of the second transistors J2 connected in series with the pull-down trimming circuit 32.

[0114] For example, in FIG5 , only one second transistor J2 is coupled in series with the pull-down trimming circuit 32. Alternatively, more than one second transistor J2 may be coupled in series with each of the pull-down trimming circuits 32. Multiple second transistors J2 may be coupled to the same pull-down trimming circuit 32, or multiple second transistors J2 may be coupled to different pull-down trimming circuits 32. The pull-down trimming circuit 32 may be located between the first electrode of the second transistor J2 and the reference ground voltage terminal VSS, or between the second electrode of the second transistor J2 and the input / output terminal IO.

[0115] For example, the pull-down trimming circuit 32 includes one or more fourth transistors J4, each of which is a three-dimensional field-effect transistor. The fourth transistors J4 can be turned on or off under the control of a trimming control signal output by the trimming control circuit 70. The plurality of fourth transistors J4 can be located, for example, around the periphery of the second transistor array J2.

[0116] In other embodiments, the I / O driver 10 may also only include the pull-up trimming circuit 22 or the pull-down trimming circuit 32 .

[0117] Because current high-speed DRAMs are increasingly demanding higher speeds, the accuracy and linearity of impedance matching vary under different PVT conditions, significantly impacting the speed of the I / O driver 10. Impedance matching control of the pull-up circuit 20 and the pull-down circuit 30 performed solely on the calibration circuit 50 side sometimes fails to meet required accuracy. By providing a trimming control circuit 70, a pull-up trimming circuit 22, and a pull-down trimming circuit 32, further refined impedance control of the pull-up circuit 20 and the pull-down circuit 30 is achieved, further improving impedance matching performance and increasing DRAM speed and yield.

[0118] In some embodiments, as shown in FIG. 5 , the trim control circuit 70 includes a test decoder circuit 71 , a programming voltage generating circuit 72 , an anti-fuse circuit 73 , a latched signal pull-up circuit 74 , and a latched signal pull-down circuit 75 .

[0119] The test decoding circuit 71 receives the first compensation signal and outputs a programming selection signal. The programming selection signal is used to determine the number of transistors to be programmed in the anti-fuse circuit 73. The programming voltage generating circuit 72 is configured to generate a programming voltage. For example, the programming voltage generating circuit 72 receives a power supply voltage from the power supply voltage terminal VDD and raises the power supply voltage to a high voltage sufficient for programming.

[0120] For example, the anti-fuse circuit 73 includes a plurality of fifth transistors J5, each of which is a three-dimensional field-effect transistor. The control electrode of the fifth transistor J5 is coupled to the programming voltage generating circuit 72, the first electrode of the fifth transistor J5 is coupled to the test decoding circuit 71, and the second electrode of the fifth transistor J5 is coupled to the latch pull-up signal circuit 74 and the latch pull-down signal circuit 75, respectively. When the difference between the programming voltage received by the control electrode of the fifth transistor J5 and the voltage received by the first electrode of the fifth transistor J5 reaches the breakdown voltage of the fifth transistor J5, the fifth transistor J5 is programmed to be equivalent to a resistor. Before programming, the fifth transistor J5 can be equivalent to a capacitor.

[0121] The output end of the latch pull-up signal circuit 74 is coupled to the pull-up adjustment circuit 22 (the control terminal of the third transistor J3). The signal output by the latch pull-up signal circuit 74 is used to control the number of times the third transistor J3 is turned on, thereby further fine-tuning the resistance of the pull-up circuit 20.

[0122] The output end of the latched pull-down signal circuit 75 is coupled to the pull-down adjustment circuit 32 (the control terminal of the fourth transistor J4). The signal output by the latched pull-down signal circuit 75 is used to control the number of times the fourth transistor J4 is turned on, thereby further fine-tuning the resistance of the pull-down circuit 30.

[0123] The test decoding circuit 71 is used to identify and decode the first compensation signal to select the number of fifth transistors J5 to be programmed. The programming voltage generation circuit 72 provides sufficient voltage for programming the fifth transistor J5. The latched pull-up signal circuit 74 and the latched pull-down signal circuit 75 cache the programming code. By storing the address of the programmed fifth transistor J5 in the latched pull-up signal circuit 74, the switch address of the third transistor J3 can be determined to adjust the impedance of the pull-up circuit 20. By storing the address of the programmed fifth transistor J5 in the latched pull-down signal circuit 75, the switch address of the fourth transistor J4 can be determined to adjust the impedance of the pull-down circuit 30.

[0124] For example, the latch pull-up signal circuit 74 can be multiplexed into the latch pull-down signal circuit 75 , and the two can be the same circuit or two circuits.

[0125] FIG6 is an architectural diagram of an I / O driver provided in an embodiment of the present application.

[0126] In some embodiments, as shown in FIG6 , the compensation circuit 60 is further configured to output the first compensation signal required by the test decoding circuit 71 .

[0127] For example, the compensation circuit 60 further includes process sensors 65 for detecting the process and generating a first compensation signal. The analog-to-digital converter 62 is further configured to receive the first compensation signal and convert the first compensation signal into a first digital signal. The decoder 63 is further configured to receive the first digital signal and output a first decoded signal. The code position adjuster 64 is further configured to receive the first decoded signal and output a first compensation signal.

[0128] The process sensor 66 determines the process corner of the I / O driver 10, determining whether it is a standard process (typical corner, tt), a fast process (fast corner, ff), or a slow process (ss). The sensor then feeds back the compensation corresponding to the process detection result to the trimming control circuit 70. The trimming control circuit 70 then programs the fifth transistor J5, outputting different programming codes depending on the process corner.

[0129] By detecting the impact of the process on the impedance of the pull-up circuit 20 and the pull-down circuit 30 through the compensation circuit 60 and performing compensation from the trimming control circuit 70 side, the impedance of the pull-up circuit 20 and the pull-down circuit 30 can be adjusted more finely, further improving signal integrity.

[0130] In some embodiments, as shown in FIG. 6 , the programming voltage generating circuit 72 includes an oscillator 721 and a charge pump 722 .

[0131] The oscillator 721 is used to receive the power supply voltage from the power supply voltage terminal VDD and output an oscillation signal; the charge pump 722 is used to receive the oscillation signal and output a programming voltage.

[0132] Usually, the required programming voltage is higher than the power supply voltage. The voltage can be increased by providing an oscillator 721 and a charge pump 722 inside the I / O driver 10, which has a simple structure.

[0133] In some embodiments, the trim control circuit 70 further includes an address multiplexing circuit (address mux) 76 . The address multiplexing circuit 76 is coupled between the test decoding circuit 71 and the anti-fuse circuit 73 .

[0134] Because the provision of the fifth transistor J5 increases the area of ​​the I / O driver 10, the number of fifth transistors J5 is typically reduced to save area. However, the I / O driver 10 requires a large address range, which can lead to a mismatch between the number of fifth transistors J5 and the large number of addresses. By providing an address multiplexing circuit 76 between the test decoding circuit 71 and the anti-fuse circuit 73, the I / O driver 10 can continue to operate normally even in the event of an address-to-number mismatch.

[0135] In some embodiments, the trimming control circuit 70 further includes a programming voltage terminal V, which is coupled to the control electrode of the fifth transistor J5.

[0136] The programming voltage terminal V can be used as a spare external voltage port. When the programming voltage generating circuit 72 cannot normally provide the programming voltage, the programming voltage can be provided through the programming voltage terminal V to ensure the normal operation of the circuit.

[0137] FIG7 is an architectural diagram of an I / O driver provided in an embodiment of the present application.

[0138] In some embodiments, as shown in FIG. 7 , the I / O driver 10 may include a trim control circuit 70 but not a calibration circuit 50 .

[0139] The above are only specific embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An input / output (I / O) driver, characterized in that: include: a pull-up circuit, coupled between the power supply voltage terminal and the input / output terminal, for generating a first voltage according to a first control signal; a pull-down circuit, the pull-down circuit being coupled between the reference ground voltage terminal and the input / output terminal, and configured to generate a second voltage according to a second control signal; The input / output terminal is used to output the first voltage and the second voltage; The pull-up circuit includes a first transistor; the pull-down circuit includes a second transistor; and at least one of the first transistor and the second transistor is a three-dimensional field effect transistor.

2. The I / O driver according to claim 1, wherein: The pull-up circuit includes a plurality of the first transistors; and / or, The pull-down circuit includes a plurality of second transistors.

3. The I / O driver according to claim 1 or 2, wherein: The I / O driver also includes a trimming control circuit; The pull-up circuit further includes a pull-up trimming circuit; the pull-up trimming circuit is connected in series with one or more first transistors; the pull-up trimming circuit is further coupled to the trimming control circuit; and / or, The pull-down circuit further includes a pull-down trimming circuit; the pull-down trimming circuit is connected in series with one or more second transistors; and the pull-down trimming circuit is further coupled to the trimming control circuit.

4. The I / O driver according to claim 3, wherein: The pull-up adjustment circuit includes a plurality of third transistors; the third transistors are three-dimensional field effect transistors; and / or, The pull-down trimming circuit includes a plurality of fourth transistors; the fourth transistors are three-dimensional field effect transistors.

5. The I / O driver according to claim 3 or 4, characterized in that: The trimming control circuit includes a test decoding circuit, a programming voltage generating circuit, an anti-fuse circuit, a latch pull-up signal circuit, and a latch pull-down signal circuit; The test decoding circuit receives the first compensation signal and outputs a burn selection signal; The programming voltage generating circuit is used to generate a programming voltage; The anti-fuse circuit includes a plurality of fifth transistors, wherein the fifth transistors are three-dimensional field effect transistors; A control electrode of the fifth transistor is coupled to the programming voltage generating circuit, a first electrode of the fifth transistor is coupled to the test decoding circuit, and a second electrode of the fifth transistor is coupled to the latch pull-up signal circuit and the latch pull-down signal circuit respectively; The output end of the latch pull-up signal circuit is coupled to the pull-up adjustment circuit; The output end of the latch pull-down signal circuit is coupled to the pull-down trimming circuit.

6. The I / O driver according to claim 5, wherein: The programming voltage generating circuit includes an oscillator and a charge pump; The oscillator is used to receive a power supply voltage and output an oscillation signal; The charge pump is used to receive the oscillation signal and output the programming voltage.

7. The I / O driver according to claim 5 or 6, characterized in that: The trimming control circuit further includes a programming voltage terminal coupled to the control electrode of the fifth transistor.

8. The I / O driver according to any one of claims 5 to 7, characterized in that: The trimming control circuit further includes an address multiplexing circuit; The address multiplexing circuit is coupled between the test decoding circuit and the anti-fuse circuit.

9. The I / O driver according to any one of claims 5 to 8, wherein: The I / O driver further includes a compensation circuit; the compensation circuit is configured to output the first compensation signal.

10. The I / O driver according to claim 9, wherein: The compensation circuit includes a process sensor, an analog-to-digital converter, a decoder, and a code position adjuster; The process sensor is used to detect the process and generate a first compensation signal; The analog-to-digital converter is used to convert the first compensation signal into a first digital signal; The decoder is used to receive the first digital signal and output a first decoded signal; The code bit adjuster is used to receive the first decoded signal and output the first compensation signal.

11. The I / O driver according to any one of claims 1 to 10, characterized in that: The I / O driver also includes a pre-driver circuit; The pre-driver circuit is used to output a first pull-up signal and a first pull-down signal; the first control signal includes the first pull-up signal, and the second control signal includes the first pull-down signal.

12. The I / O driver according to claim 11, wherein: The I / O driver further includes a compensation circuit, wherein the compensation circuit is configured to output a second compensation signal, and the pre-driving circuit is configured to receive the second compensation signal.

13. The I / O driver according to claim 12, wherein: The compensation circuit includes a temperature sensor, an analog-to-digital converter, a decoder, and a code position adjuster; The temperature sensor is used to detect temperature and generate a second compensation signal; The analog-to-digital converter is further configured to convert the second compensation signal into a second digital signal; The decoder is further configured to receive the second digital signal and output a second decoded signal; The code bit adjuster is further configured to receive the second decoded signal and output the second compensation signal.

14. The I / O driver according to any one of claims 1 to 13, characterized in that: The I / O driver further includes a calibration circuit; The calibration circuit is coupled to the power supply voltage terminal, the reference ground voltage terminal, the pull-up threshold voltage terminal, the pull-down threshold voltage terminal, and the calibration reference voltage terminal, and is configured to output a second pull-up signal and a second pull-down signal; The first control signal further includes the second pull-up signal, and the second control signal further includes the second pull-down signal.

15. The I / O driver according to claim 14, wherein: The pull-up circuit further includes a first logic operation circuit, the first logic operation circuit being configured to receive the first pull-up signal and the second pull-up signal and output a first signal; a control electrode of the first transistor being coupled to the output terminal of the first logic operation circuit, a first electrode of the first transistor being coupled to the power supply voltage terminal, and a second electrode of the first transistor being coupled to the input / output terminal; The pull-down circuit also includes a second logic operation circuit, which is used to receive the first pull-down signal and the second pull-down signal and output a second signal; the control electrode of the second transistor is coupled to the output end of the second logic operation circuit, the first electrode of the second transistor is coupled to the reference ground voltage end, and the second electrode of the second transistor is coupled to the input / output end.

16. An electronic device, characterized in that: It comprises an I / O driver and a circuit board, wherein the I / O driver is arranged on the circuit board; the I / O driver comprises the I / O driver according to any one of claims 1 to 15.

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