Master-slave switching interface structure of server, and application apparatus thereof

Abstract

The embodiments of the present invention relate to the technical field of computer systems and storage. Provided are a master-slave switching interface structure of a server and an application apparatus thereof. The master-slave switching interface structure comprises: at least two input / output interfaces and a routing and switching processor, wherein the routing and switching processor comprises: a clock buffer module connected to a first clock input source pin, a local clock module connected to a second clock input source pin, and a switch module connected to the first clock input source pin, a first clock output pin and a clock connection pin; the input / output interfaces are connected to the routing and switching processor, and one of the input / output interfaces is a target master-slave switching detection interface; and the routing and switching processor is configured to detect a connection status of the target master-slave switching detection interface, and switch a clock transmission direction of the target master-slave switching detection interface on the basis of the connection status. By means of the embodiments of the present invention, the connection of a plurality of servers can be realized, and master apparatuses and slave apparatuses can be automatically identified, thereby achieving the expansion of the apparatuses.

Description

A master-slave switching interface structure of a server and its application device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a Chinese patent application filed with the Patent Office of China on February 28, 2024, with application number 202410223849.9 and application name “A master-slave switching interface structure of a server and its application device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of computer systems and storage technology, and in particular to a master-slave switching interface structure of a server, a server connection topology system, a distributed server cluster system, an electronic device and a non-volatile readable storage medium. Background Art

[0004] With the increasing maturity of computer expansion hardware technologies such as CXL (Computer Express Link), a large number of devices such as CXL interfaces are being used in AI (Artificial Intelligence) servers. However, due to the limited space, internal device capacity, and computing power of a single computer, it is difficult to fully meet user needs. As a result, when connecting to a server, manual identification and setting of the master and slave devices is required to determine the device interface signal transmission direction.

[0005] Summary of the Invention

[0006] In view of the above problems, embodiments of the present application are proposed to provide a master-slave switching interface structure of a server, a server connection topology system, a distributed server cluster system, an electronic device and a non-volatile readable storage medium that overcome the above problems or at least partially solve the above problems.

[0007] In order to solve the above problems, in the first aspect of the present application, the embodiment of the present application discloses a master-slave switching interface structure of a server,

[0008] The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor, the routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module,

[0009] The clock buffer module is connected to the first clock input source pin.

[0010] A local clock module connected to the second clock input source pin;

[0011] A switch module connected to the first clock input source pin, the first clock output pin, and the clock connection pin;

[0012] The input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface;

[0013] The routing and switching processor is configured to detect a connection state of a target master-slave switching detection interface and switch a clock transmission direction of the target master-slave switching detection interface based on the connection state.

[0014] Optionally, the routing and switching processor further includes a plurality of general-purpose input and output pins; the input and output interface includes a first pin and a second pin; the first pin is disconnected from the second pin; the first pin is connected to the general-purpose input and output pin, and the second pin is grounded.

[0015] Optionally, the input / output interface further includes: a first pull-up resistor,

[0016] One end of the first pull-up resistor is connected to the preset power supply, and the other end is connected to the first pin and the general input / output pin.

[0017] Optionally, it also includes: a cable connected to the input and output interface, the cable including: a short-circuited third pin and a fourth pin; when the cable is connected to the input and output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

[0018] Optionally, the routing switching processor is configured to determine that the input and output interfaces are connected to other servers in the cascade server when a high level is detected, and switch the clock transmission direction of the target master-slave switching detection interface to upload; when a low level is detected, switch the clock transmission direction of the target master-slave switching detection interface to download.

[0019] Optionally, the routing and switching processor is configured to perform port scanning on general-purpose input and output pins to determine the connection status of the target master-slave switching detection interface; when the connection status is accessed, the clock transmission direction of the target master-slave switching detection interface is switched to upload; when the connection status is empty, the clock transmission direction of the target master-slave switching detection interface is switched to download.

[0020] Optionally, when the clock transmission direction of the target master-slave switching detection interface is downloading, the clock cache module is connected to the clock connection pin through the switch module; when the clock transmission direction of the target master-slave switching detection interface is uploading, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.

[0021] Optionally, the switch module is a single-pole double-throw switch device.

[0022] A first input terminal of the single-pole double-throw switch device is connected to a first clock input source pin;

[0023] The second input terminal of the single-pole double-throw switch device is connected to the first clock output pin;

[0024] The output end of the single-pole double-throw switch device is connected to the clock connection pin.

[0025] Optionally, when the clock transmission direction of the target master-slave switching detection interface is data download, the first input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected; when the clock transmission direction of the target master-slave switching detection interface is data upload, the second input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected.

[0026] Optionally, the target master-slave switching detection interface further includes:

[0027] The signal receiving pin and the switch module are configured so that when the clock transmission direction of the target master-slave switching detection interface is data download, the switch module is connected to the clock connection pin and receives the signal.

[0028] Optionally, the signal receiving pin is configured to receive a clock reset signal, and the clock reset signal is configured to reset the output signal of the first clock output pin.

[0029] Optionally, the master-slave switching interface structure is applied to a computer quick connection device.

[0030] In the second aspect of the present application, an embodiment of the present application discloses a server connection topology system, including multiple cascade servers, which are deployed with the master-slave switching interface structure as above, and the cascade servers are connected to each other through their own master-slave switching interface structure.

[0031] Optionally, the cascaded servers are connected via cables, and the cables include:

[0032] Plug, connected to the master-slave switching interface structure;

[0033] A second pull-up resistor connects one of the pins of the header to a preset power source and is configured to place the pin at a high level.

[0034] Optionally, when the cable is connected to the master-slave switching interface structure, the master-slave switching interface structure is in a high level state; when the cable is not connected to the master-slave switching interface structure, the master-slave switching interface structure is in a low level state.

[0035] Optionally, the server connection topology system further includes:

[0036] The master-slave switching processor is configured to detect the level state of the master-slave switching interface structure and set the clock transmission direction of the master-slave switching interface structure.

[0037] Optionally, when there is a newly added cascade server, the master-slave switching interface structure of the newly added cascade server is connected to the master-slave switching interface structures of other cascade servers through a cable.

[0038] In a third aspect of the present application, an embodiment of the present application discloses a distributed server cluster system, including the above server connection topology system.

[0039] In the fourth aspect of the present application, an embodiment of the present application further discloses an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, and when the computer program is executed by the processor, the master-slave switching interface structure as above is implemented.

[0040] In the fifth aspect of the present application, an embodiment of the present application further discloses a non-volatile readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the master-slave switching interface structure as described above is implemented.

[0041] The embodiments of the present application include the following advantages:

[0042] The embodiment of the present application is deployed on a server through a master-slave switching interface structure. The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor. The routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module. The clock buffer module is connected to the first clock input source pin, and the local clock module is connected to the second clock input source pin; the switch module is connected to the first clock input source pin, the first clock output pin and the clock connection pin; the input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface; the routing switching processor is configured to detect the connection status of the target master-slave switching detection interface and switch the clock transmission direction of the target master-slave switching detection interface based on the connection status; the connection of multiple servers can be conveniently realized without changing the computer hardware and software settings, and the master and slave devices can be automatically identified, and the clock hand transmission direction of the target master-slave switching detection interface can be switched, so as to facilitate the expansion of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a structural system diagram of an embodiment of a master-slave switching interface structure of a server of the present application;

[0044] FIG2 is a schematic diagram of the connection between an input and output interface and a cable of the present application;

[0045] FIG3 is a schematic diagram of signal transmission of the present application;

[0046] FIG4 is a structural system diagram of an embodiment of a server connection topology system of the present application;

[0047] FIG5 is a structural block diagram of an electronic device provided in an embodiment of the present application;

[0048] FIG6 is a structural block diagram of a non-volatile readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0050] 1 , a structural system diagram of an embodiment of a master-slave switching interface structure of a server of the present application is shown. The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor. The routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module, and a local clock module.

[0051] The clock buffer module is connected to the first clock input source pin.

[0052] A local clock module connected to the second clock input source pin;

[0053] A switch module connected to the first clock input source pin, the first clock output pin, and the clock connection pin;

[0054] The input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface;

[0055] The routing and switching processor is configured to detect a connection state of a target master-slave switching detection interface and switch a clock transmission direction of the target master-slave switching detection interface based on the connection state.

[0056] In embodiments of the present application, a master-slave switching interface structure can be deployed in a server. The master-slave switching interface structure can be used in high-speed signal connections and extensions such as CXL and PCIe (Peripheral Component Interconnect Express), and can also be used in other application scenarios where signal direction is automatically switched, with corresponding hardware settings for the interface.

[0057] The master-slave switching interface structure includes at least two input and output interfaces and a routing switching processor. The routing switching processor may include multiple pins, the number of which is greater than the number of input and output interfaces. The input and output interface may be connected to one of the pins in the routing switching processor, and different input and output interfaces are connected to different pins in the routing switching processor. One of the at least two input and output interfaces is a target master-slave switching detection interface; it is connected to other servers through the target master-slave switching detection interface, and the target master-slave switching detection interface may be connected to other servers or may be left vacant. When there is no next-level computer connected, the interface acts as a normal slave device interface, i.e., a Slave interface, with a data flow direction of Downstream, and is used to connect to a slave device; when there is a next-level computer connected, the interface acts as a master device interface, i.e., a Host interface, with a data flow direction of Upstream.

[0058] The clock buffer module is connected to the first clock input source pin and can read the time signal cached by the host. The local clock module is connected to the second clock input source pin and can generate a local time signal. The switch module is connected to the first clock input source pin, the first clock output pin, and the clock connection pin, respectively, and switches on and off based on different situations.

[0059] The routing switch processor can detect the connection status of the target master-slave switch detection interface to determine whether the server is the master device or the slave device. Based on the connection status, the clockwise transmission direction of the target master-slave switch detection interface is switched, thereby actively connecting to the cascade server.

[0060] In some optional embodiments of the present application, the routing and switching processor includes multiple general-purpose input and output pins; the input and output interface includes a first pin and a second pin; the first pin is disconnected from the second pin; the first pin is connected to the general-purpose input and output pin, and the second pin is grounded.

[0061] In an embodiment of the present application, the routing switch processor includes multiple general-purpose input / output (GPIO) pins. Each input / output interface includes a first pin and a second pin. The first and second pins are used solely to distinguish between two different pins of the input / output interface and do not limit their functions or scope of use. The first pin is disconnected from the second pin, but not short-circuited. The first pin is connected to the general-purpose input / output pin, thereby connecting the input / output interface to the routing switch processor, and the second pin is grounded.

[0062] Furthermore, the input / output interface further includes: a first pull-up resistor, one end of the first pull-up resistor is connected to a preset power supply, and the other end of the first pull-up resistor is connected to the first pin and the general input / output pin.

[0063] A first pull-up resistor may also be provided in the input / output interface. One end of the first pull-up resistor is connected to a preset power source, and the other end is connected to the first pin and the general-purpose input / output pin. This ensures that when the second pin and the first pin are connected to form a loop, the input / output interface is in a low-level state. Conversely, when the second pin and the first pin are disconnected, the input / output interface is in a low-level state.

[0064] Furthermore, the master-slave switching interface structure also includes: a cable connected to the input and output interface, the cable including: a short-circuited third pin and a fourth pin; when the cable is connected to the input and output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

[0065] Referring to FIG. 2 , the cable short-circuits the third and fourth pins of the card; when the cable is connected to the input / output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

[0066] As shown in Figure 2, when no CXL cable is plugged into MCIO (Memory Card I / O) port 0 on the computer motherboard, the PRSNT (Presence Signal) signal is high due to the pull-up resistor. When a CXL cable is plugged in, the PRSNT signal goes low because it passes through the mth pin of the MCIO socket, the mth pin of the MCIO plug, the nth pin of the MCIO plug, the nth pin of the MCIO socket, and finally to ground.

[0067] Because the PRSNT signal changes in level when a CXL cable is inserted or removed from the socket, and is fed into the CXL Switch component's GPIO pins, the CXL Switch component can use this signal change to determine whether a CXL cable is connected. When a CXL cable is connected to MCIO port 0, it becomes an upstream port connected to the upstream computer. When no CXL cable is connected, it becomes a downstream port connected to other CXL slave devices.

[0068] Correspondingly, when the routing switching processor detects a high level, it determines that the input and output interfaces are connected to other servers in the cascade server, and switches the clockwise transmission direction of the target master-slave switching detection interface to data upload; when a low level is detected, it switches the clockwise transmission direction of the target master-slave switching detection interface to data download.

[0069] That is, the state of the target master-slave switching detection interface can be detected at a level by directly using an existing physical detection method, thereby quickly and simply detecting the port state, determining the transmission direction of the port, and facilitating the switching of the master and slave devices.

[0070] In addition, the routing and switching processor is used to perform port scanning on general-purpose input and output pins to determine the connection status of the target master-slave switching detection interface; when the connection status is accessed, the clockwise transmission direction of the target master-slave switching detection interface is switched to data upload; when the connection status is empty, the clockwise transmission direction of the target master-slave switching detection interface is switched to data download.

[0071] The connection status of the target master-slave switching detection interface can be detected by utilizing port detection, and the connection status can be determined directly from the bottom-level control process, so that the port connection status can be detected faster and more actively, which facilitates the switching of master and slave devices.

[0072] Specifically, when the clock hand transmission direction of the target master-slave switching detection interface is data download, the clock cache module is connected to the clock connection pin through the switch module; when the clock hand transmission direction of the target master-slave switching detection interface is data upload, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.

[0073] Furthermore, the switch module is a single-pole double-throw switch device.

[0074] A first input terminal of the single-pole double-throw switch device is connected to a first clock input source pin;

[0075] The second input terminal of the single-pole double-throw switch device is connected to the first clock output pin;

[0076] The output end of the single-pole double-throw switch device is connected to the clock connection pin.

[0077] In practical applications, the switch module can be a single-pole double-throw switch device having a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the first clock input source pin, the second input terminal is connected to the first clock output pin, and the output terminal is connected to the clock connection pin. Based on the conduction status, the first input terminal can be connected to the output terminal, or the second input terminal can be connected to the output terminal.

[0078] Furthermore, when the clockwise transmission direction of the target master-slave switching detection interface is data download, the first input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected; when the clockwise transmission direction of the target master-slave switching detection interface is data upload, the second input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected.

[0079] That is, the switching of two signals can be achieved through a single-pole double-throw switch device, which can reduce the use of devices and reduce material costs.

[0080] In some optional embodiments of the present application, the target master-slave switching detection interface further includes:

[0081] The signal receiving pin and the switch module are used to connect the switch module to the clock connection pin and receive the signal when the clock transmission direction of the target master-slave switching detection interface is data download.

[0082] The target master-slave switching detection interface may include a signal receiving pin, which is connected to the switch module and can be linked with the switch module. When the clock transmission direction of the target master-slave switching detection interface is data download, the switch module is connected to the clock connection pin and receives the signal.

[0083] Furthermore, the signal receiving pin is used to receive a clock reset signal, and the clock reset signal is used to reset the output signal of the first clock output pin.

[0084] A clock reset signal may be received through a signal receiving pin and transmitted to a corresponding pin to reset the output signal of the first clock output pin.

[0085] In summary, the clock information transmission part of the target master-slave switching detection interface can be used to transmit the clock signal, and the clock reset signal can also be transmitted to achieve multiplexing, thereby further reducing complexity and improving practicality.

[0086] To this end, Figure 3 is used as an example to illustrate:

[0087] When no CXL cable is plugged into MCIO port 0, the PRSNT signal (presence signal) is high. MCIO port 0 and the other MCIO ports function as downstream interfaces connected to CXL slave devices. The CXL reference clock is generated by the local clock generator via clock transmission path B, which synchronizes the clock buffer with data source port 1 and sends it to the n+1 ports from MCIO port 0 to port n. The clock output from clock output 0 of the clock buffer is connected to MCIO port 0 via the P3-P1 path of the SPDT (single-pole double-throw) analog switch.

[0088] When a CXL cable is plugged into MCIO port 0, the PRSNT signal is low. MCIO port 0 then functions as an upstream port connected to the CXL master (i.e., MCIO port n on the upstream computer). The other MCIO ports function as downstream ports connected to CXL slaves. MCIO port 0 receives the clock signal from the CXL master (i.e., MCIO port n on the upstream computer). The clock is transmitted along path A, passing through the P1-P2 path of the SPDT analog switch and input source 0 of the clock buffer. The clock buffer synchronizes the clock and transmits it to the other n MCIO ports, excluding MCIO port 0 (because the P1-P3 path of the SPDT analog switch is disconnected).

[0089] Similarly, the clock reset signal of MCIO interface 0 also achieves transmission direction change through the same method. That is, when MCIO interface 0 serves as a downstream interface, the clock reset signal is sent by the local clock to the slave device on MCIO interface 0; when MCIO interface 0 serves as an upstream interface, the reset signal is sent by the CXL master device (that is, MCIO interface n of the upstream computer) to MCIO interface 0 and then to the local computer.

[0090] In some optional embodiments of the present application, the master-slave switching interface structure is applied to a computer quick connection device.

[0091] The master-slave switching interface structure of the embodiment of the present application can be applied to a computer quick connection device, that is, to implement master-slave device identification and switching in the computer quick connection device. In the current context of big data and the ever-increasing storage demand, even if computer quick connection devices are continuously added to a cluster, master-slave switching can be quickly implemented in the link to which the new computer quick connection device is connected, allowing efficient access to the computer quick connection device.

[0092] The embodiment of the present application is deployed on any server in the cascade server through a master-slave switching interface structure. The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor. The input and output interfaces are connected to the routing switching processor, and one of the input and output interfaces is a target master-slave switching detection interface; the routing switching processor is used to detect the connection status of the target master-slave switching detection interface and switch the clockwise transmission direction of the target master-slave switching detection interface based on the connection status; it is convenient to realize the connection of multiple servers without changing the computer hardware and software settings, and can automatically identify the master and slave devices and switch the clockwise transmission direction of the target master-slave switching detection interface, so as to facilitate the expansion of the device.

[0093] 4 , a structural system diagram of a server connection topology system embodiment of the present application is shown. The server connection topology system includes multiple cascade servers, and the cascade servers are deployed with the master-slave switching interface structure as above. The cascade servers are connected to each other through their own master-slave switching interface structure.

[0094] In an embodiment of the present application, a server connection topology system includes multiple cascade servers, each of which is deployed with a master-slave switching interface structure of the cascade server as described above, and each of the cascade servers is connected to each other through its own master-slave switching interface structure. As shown in Figure 4, when the input and output interfaces in the master-slave switching interface structure are vacant, the input and output interfaces 0 to the input and output interfaces n of each computer are connected as downstream interfaces to slave devices such as CXL (for example, to a CXL memory expansion card, etc.); when the input and output interfaces in the master-slave switching interface structure are connected to other servers, the input and output interface 0 of the computer is connected to the upper-level computer as an upstream interface, for example, the input and output interface 0 of computer B in Figure 4 is connected to the input and output interface n of the upstream computer A. At this time, computer A acts as the master device and computer B is the slave device; the other input and output interfaces are still connected to other slave devices as downstream interfaces.

[0095] In some optional embodiments of the present application, the cascaded servers are connected via a cable, which includes: a plug connected to the master-slave switching interface structure; a second pull-up resistor connecting one of the pins of the plug to a preset power supply to set the pin to a high level.

[0096] In an embodiment of the present application, the cascaded servers can be connected via a cable. A cable can include a plug and a second pull-up resistor. The plug matches the pin type of the master-slave switching interface structure. The plug can be connected to the master-slave switching interface structure; the second pull-up resistor can be connected to one of the pins of the plug, and the second pull-up resistor can also be connected to a power supply, that is, the pin of the plug connected to the second pull-up resistor is set to a high level, so that when connected to the master-slave switching interface structure, the interface level in the master-slave switching interface structure can be set to a high level.

[0097] Specifically, when the cable is connected to the master-slave switching interface structure, the master-slave switching interface structure is in a high level state; when the cable is not connected to the master-slave switching interface structure, the master-slave switching interface structure is in a low level state.

[0098] In addition, when a new cascade server needs to be expanded, it can be connected by using cables and a master-slave switching interface structure. When there is a new cascade server, the master-slave switching interface structure of the new cascade server is connected to the master-slave switching interface structure of other cascade servers through cables.

[0099] In some optional embodiments of the present application, the server connection topology system further includes:

[0100] The master-slave switching processor is used to detect the level state of the master-slave switching interface structure and set the clockwise transmission direction of the master-slave switching interface structure.

[0101] In an embodiment of the present application, the server connection topology system may further include a master-slave switching processor. The master-slave switching processor may detect the level status of the master-slave switching interface structure, determine whether the cascaded server is a master device or a slave device based on the high and low levels, and set the clockwise transmission direction of the master-slave switching interface structure to achieve active identification and master-slave switching.

[0102] Furthermore, the master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor, the routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module,

[0103] The clock buffer module is connected to the first clock input source pin.

[0104] A local clock module connected to the second clock input source pin;

[0105] A switch module connected to the first clock input source pin, the first clock output pin, and the clock connection pin;

[0106] The input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface;

[0107] The routing and switching processor is used to detect the connection status of the target master-slave switching detection interface and switch the clock transmission direction of the target master-slave switching detection interface based on the connection status.

[0108] Optionally, the routing and switching processor further includes a plurality of general-purpose input and output pins; the input and output interface includes a first pin and a second pin; the first pin is disconnected from the second pin; the first pin is connected to the general-purpose input and output pin, and the second pin is grounded.

[0109] Optionally, the input / output interface further includes: a first pull-up resistor,

[0110] One end of the first pull-up resistor is connected to the preset power supply, and the other end is connected to the first pin and the general input / output pin.

[0111] Optionally, it also includes: a cable connected to the input and output interface, the cable including: a short-circuited third pin and a fourth pin; when the cable is connected to the input and output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

[0112] Optionally, the routing switching processor is used to determine that the input and output interfaces are connected to other servers in the cascade server when a high level is detected, and switch the clock transmission direction of the target master-slave switching detection interface to upload; when a low level is detected, switch the clock transmission direction of the target master-slave switching detection interface to download.

[0113] Optionally, the routing and switching processor is used to perform port scanning on general-purpose input and output pins to determine the connection status of the target master-slave switching detection interface; when the connection status is accessed, the clock transmission direction of the target master-slave switching detection interface is switched to upload; when the connection status is empty, the clock transmission direction of the target master-slave switching detection interface is switched to download.

[0114] Optionally, when the clock transmission direction of the target master-slave switching detection interface is downloading, the clock cache module is connected to the clock connection pin through the switch module; when the clock transmission direction of the target master-slave switching detection interface is uploading, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.

[0115] Optionally, the switch module is a single-pole double-throw switch device.

[0116] A first input terminal of the single-pole double-throw switch device is connected to a first clock input source pin;

[0117] The second input terminal of the single-pole double-throw switch device is connected to the first clock output pin;

[0118] The output end of the single-pole double-throw switch device is connected to the clock connection pin.

[0119] Optionally, when the clock transmission direction of the target master-slave switching detection interface is data download, the first input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected; when the clock transmission direction of the target master-slave switching detection interface is data upload, the second input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected.

[0120] Optionally, the target master-slave switching detection interface further includes:

[0121] The signal receiving pin and the switch module are used to connect the switch module to the clock connection pin and receive the signal when the clock transmission direction of the target master-slave switching detection interface is data download.

[0122] Optionally, the signal receiving pin is used to receive a clock reset signal, and the clock reset signal is used to reset the output signal of the first clock output pin.

[0123] Optionally, the master-slave switching interface structure is applied to a computer quick connection device.

[0124] It should be noted that for the sake of simplicity, the embodiments of the present application are described as a series of action combinations. However, those skilled in the art should be aware that the embodiments of the present application are not limited by the order of the actions described, because according to the embodiments of the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0125] The embodiment of the present application also discloses a distributed server cluster system, including the above server connection topology system.

[0126] The server connection topology system includes multiple cascade servers. The cascade servers are deployed with the master-slave switching interface structure as above. The servers are connected to each other through their own master-slave switching interface structure.

[0127] A distributed server cluster system can link multiple server topologies to form integrated processing for a single business. By distributing tasks and data across multiple nodes in the server topology, a distributed server cluster system achieves resource sharing, load balancing, high availability, and high performance, along with strong scalability and fault tolerance. This enables the distributed server cluster system to handle large amounts of data and highly concurrent requests.

[0128] Optionally, the cascaded servers are connected via cables, and the cables include:

[0129] Plug, connected to the master-slave switching interface structure;

[0130] The second pull-up resistor connects one of the pins of the header to a preset power source to set the pin to a high level.

[0131] Optionally, when the cable is connected to the master-slave switching interface structure, the master-slave switching interface structure is in a high level state; when the cable is not connected to the master-slave switching interface structure, the master-slave switching interface structure is in a low level state.

[0132] Optionally, the server connection topology system further includes:

[0133] The master-slave switching processor is used to detect the level state of the master-slave switching interface structure and set the clockwise transmission direction of the master-slave switching interface structure.

[0134] Optionally, when there is a newly added cascade server, the master-slave switching interface structure of the newly added cascade server is connected to the master-slave switching interface structures of other cascade servers through a cable.

[0135] The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor, and the routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module.

[0136] The clock buffer module is connected to the first clock input source pin.

[0137] A local clock module connected to the second clock input source pin;

[0138] A switch module connected to the first clock input source pin, the first clock output pin, and the clock connection pin;

[0139] The input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface;

[0140] The routing and switching processor is used to detect the connection status of the target master-slave switching detection interface and switch the clock transmission direction of the target master-slave switching detection interface based on the connection status.

[0141] Optionally, the routing and switching processor further includes a plurality of general-purpose input and output pins; the input and output interface includes a first pin and a second pin; the first pin is disconnected from the second pin; the first pin is connected to the general-purpose input and output pin, and the second pin is grounded.

[0142] Optionally, the input / output interface further includes: a first pull-up resistor,

[0143] One end of the first pull-up resistor is connected to the preset power supply, and the other end is connected to the first pin and the general input / output pin.

[0144] Optionally, it also includes: a cable connected to the input and output interface, the cable including: a short-circuited third pin and a fourth pin; when the cable is connected to the input and output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

[0145] Optionally, the routing switching processor is used to determine that the input and output interfaces are connected to other servers in the cascade server when a high level is detected, and switch the clock transmission direction of the target master-slave switching detection interface to upload; when a low level is detected, switch the clock transmission direction of the target master-slave switching detection interface to download.

[0146] Optionally, the routing and switching processor is used to perform port scanning on general-purpose input and output pins to determine the connection status of the target master-slave switching detection interface; when the connection status is accessed, the clock transmission direction of the target master-slave switching detection interface is switched to upload; when the connection status is empty, the clock transmission direction of the target master-slave switching detection interface is switched to download.

[0147] Optionally, when the clock transmission direction of the target master-slave switching detection interface is downloading, the clock cache module is connected to the clock connection pin through the switch module; when the clock transmission direction of the target master-slave switching detection interface is uploading, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.

[0148] Optionally, the switch module is a single-pole double-throw switch device.

[0149] A first input terminal of the single-pole double-throw switch device is connected to a first clock input source pin;

[0150] The second input terminal of the single-pole double-throw switch device is connected to the first clock output pin;

[0151] The output end of the single-pole double-throw switch device is connected to the clock connection pin.

[0152] Optionally, when the clock transmission direction of the target master-slave switching detection interface is data download, the first input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected; when the clock transmission direction of the target master-slave switching detection interface is data upload, the second input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected.

[0153] Optionally, the target master-slave switching detection interface further includes:

[0154] The signal receiving pin and the switch module are used to connect the switch module to the clock connection pin and receive the signal when the clock transmission direction of the target master-slave switching detection interface is data download.

[0155] Optionally, the signal receiving pin is used to receive a clock reset signal, and the clock reset signal is used to reset the output signal of the first clock output pin.

[0156] Optionally, the master-slave switching interface structure is applied to a computer quick connection device.

[0157] 5 , an embodiment of the present application further provides an electronic device, including:

[0158] The processor 501 and the storage medium 502 store a computer program executable by the processor 501. When the electronic device is running, the processor 501 executes the computer program to implement a master-slave switching interface structure as in any one of the embodiments of the present application.

[0159] The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor, the routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module,

[0160] The clock buffer module is connected to the first clock input source pin.

[0161] A local clock module connected to the second clock input source pin;

[0162] A switch module connected to the first clock input source pin, the first clock output pin, and the clock connection pin;

[0163] The input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface;

[0164] The routing and switching processor is used to detect the connection status of the target master-slave switching detection interface and switch the clock transmission direction of the target master-slave switching detection interface based on the connection status.

[0165] Optionally, the routing and switching processor further includes a plurality of general-purpose input and output pins; the input and output interface includes a first pin and a second pin; the first pin is disconnected from the second pin; the first pin is connected to the general-purpose input and output pin, and the second pin is grounded.

[0166] Optionally, the input / output interface further includes: a first pull-up resistor,

[0167] One end of the first pull-up resistor is connected to the preset power supply, and the other end is connected to the first pin and the general input / output pin.

[0168] Optionally, it also includes: a cable connected to the input and output interface, the cable including: a short-circuited third pin and a fourth pin; when the cable is connected to the input and output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

[0169] Optionally, the routing switching processor is used to determine that the input and output interfaces are connected to other servers in the cascade server when a high level is detected, and switch the clock transmission direction of the target master-slave switching detection interface to upload; when a low level is detected, switch the clock transmission direction of the target master-slave switching detection interface to download.

[0170] Optionally, the routing and switching processor is used to perform port scanning on general-purpose input and output pins to determine the connection status of the target master-slave switching detection interface; when the connection status is accessed, the clock transmission direction of the target master-slave switching detection interface is switched to upload; when the connection status is empty, the clock transmission direction of the target master-slave switching detection interface is switched to download.

[0171] Optionally, when the clock transmission direction of the target master-slave switching detection interface is downloading, the clock cache module is connected to the clock connection pin through the switch module; when the clock transmission direction of the target master-slave switching detection interface is uploading, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.

[0172] Optionally, the switch module is a single-pole double-throw switch device.

[0173] A first input terminal of the single-pole double-throw switch device is connected to a first clock input source pin;

[0174] The second input terminal of the single-pole double-throw switch device is connected to the first clock output pin;

[0175] The output end of the single-pole double-throw switch device is connected to the clock connection pin.

[0176] Optionally, when the clock transmission direction of the target master-slave switching detection interface is data download, the first input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected; when the clock transmission direction of the target master-slave switching detection interface is data upload, the second input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected.

[0177] Optionally, the target master-slave switching detection interface further includes:

[0178] The signal receiving pin and the switch module are used to connect the switch module to the clock connection pin and receive the signal when the clock transmission direction of the target master-slave switching detection interface is data download.

[0179] Optionally, the signal receiving pin is used to receive a clock reset signal, and the clock reset signal is used to reset the output signal of the first clock output pin.

[0180] Optionally, the master-slave switching interface structure is applied to a computer quick connection device.

[0181] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage. Alternatively, the memory may be at least one storage device located away from the processor.

[0182] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0183] 6 , an embodiment of the present application further provides a non-volatile readable storage medium 601 , on which a computer program is stored. When the computer program is executed by a processor, a master-slave switching interface structure as in any one of the embodiments of the present application is executed.

[0184] The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor, the routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module,

[0185] The clock buffer module is connected to the first clock input source pin.

[0186] A local clock module connected to the second clock input source pin;

[0187] A switch module connected to the first clock input source pin, the first clock output pin, and the clock connection pin;

[0188] The input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface;

[0189] The routing and switching processor is used to detect the connection status of the target master-slave switching detection interface and switch the clock transmission direction of the target master-slave switching detection interface based on the connection status.

[0190] Optionally, the routing and switching processor further includes a plurality of general-purpose input and output pins; the input and output interface includes a first pin and a second pin; the first pin is disconnected from the second pin; the first pin is connected to the general-purpose input and output pin, and the second pin is grounded.

[0191] Optionally, the input / output interface further includes: a first pull-up resistor,

[0192] One end of the first pull-up resistor is connected to the preset power supply, and the other end is connected to the first pin and the general input / output pin.

[0193] Optionally, it also includes: a cable connected to the input and output interface, the cable including: a short-circuited third pin and a fourth pin; when the cable is connected to the input and output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

[0194] Optionally, the routing switching processor is used to determine that the input and output interfaces are connected to other servers in the cascade server when a high level is detected, and switch the clock transmission direction of the target master-slave switching detection interface to upload; when a low level is detected, switch the clock transmission direction of the target master-slave switching detection interface to download.

[0195] Optionally, the routing and switching processor is used to perform port scanning on general-purpose input and output pins to determine the connection status of the target master-slave switching detection interface; when the connection status is accessed, the clock transmission direction of the target master-slave switching detection interface is switched to upload; when the connection status is empty, the clock transmission direction of the target master-slave switching detection interface is switched to download.

[0196] Optionally, when the clock transmission direction of the target master-slave switching detection interface is downloading, the clock cache module is connected to the clock connection pin through the switch module; when the clock transmission direction of the target master-slave switching detection interface is uploading, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.

[0197] Optionally, the switch module is a single-pole double-throw switch device.

[0198] A first input terminal of the single-pole double-throw switch device is connected to a first clock input source pin;

[0199] The second input terminal of the single-pole double-throw switch device is connected to the first clock output pin;

[0200] The output end of the single-pole double-throw switch device is connected to the clock connection pin.

[0201] Optionally, when the clock transmission direction of the target master-slave switching detection interface is data download, the first input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected; when the clock transmission direction of the target master-slave switching detection interface is data upload, the second input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected.

[0202] Optionally, the target master-slave switching detection interface further includes:

[0203] The signal receiving pin and the switch module are used to connect the switch module to the clock connection pin and receive the signal when the clock transmission direction of the target master-slave switching detection interface is data download.

[0204] Optionally, the signal receiving pin is used to receive a clock reset signal, and the clock reset signal is used to reset the output signal of the first clock output pin.

[0205] Optionally, the master-slave switching interface structure is applied to a computer quick connection device.

[0206] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0207] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0208] The present application embodiment is described with reference to the flow chart and / or block diagram of the method, terminal device (system), and computer program product according to the embodiment of the present application. It should be understood that each process and / or box in the flow chart and / or block diagram and the combination of the process and / or box in the flow chart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device produce a device for realizing the function specified in one process or multiple processes and / or one box or multiple boxes of the flow chart.

[0209] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0210] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce computer-implemented processing, so that the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0211] Although preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic inventive concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0212] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0213] The above is a detailed introduction to the master-slave switching interface structure of a server, a server connection topology system, a distributed server cluster system, an electronic device and a non-volatile readable storage medium provided by this application. Specific examples are used in this article to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method of this application and its core idea; at the same time, for general technical personnel in this field, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A master-slave switching interface structure of a server, characterized in that: The master-slave switching interface structure includes: at least two input and output interfaces and a routing switching processor, wherein the routing switching processor includes: a first clock input source pin, a second clock input source pin, a first clock output pin, a clock connection pin, a switch module, a clock buffer module and a local clock module. The clock buffer module is connected to the first clock input source pin, The local clock module is connected to the second clock input source pin; The switch module is connected to the first clock input source pin, the first clock output pin, and the clock connection pin; The input and output interfaces are connected to the switch module, and one of the input and output interfaces is a target master-slave switching detection interface; The routing and switching processor is configured to detect a connection status of the target master-slave switching detection interface, and switch a clock transmission direction of the target master-slave switching detection interface based on the connection status.

2. The master-slave switching interface structure according to claim 1, characterized in that: The routing switch processor further includes a plurality of general-purpose input and output pins; the input and output interface includes a first pin and a second pin; the first pin is disconnected from the second pin; The first pin is connected to the general-purpose input / output pin, and the second pin is grounded.

3. The master-slave switching interface structure according to claim 2, characterized in that: The input-output interface further includes: a first pull-up resistor, One end of the first pull-up resistor is connected to a preset power supply, and the other end is connected to the first pin and the general input / output pin.

4. The master-slave switching interface structure according to claim 3, characterized in that: Also includes: A cable connected to the input / output interface, the cable comprising: a short-circuited third pin and a fourth pin; When the cable is connected to the input / output interface, the third pin is connected to the first pin, and the fourth pin is connected to the second pin.

5. The master-slave switching interface structure according to claim 4, characterized in that: The routing and switching processor is configured to, when detecting a high level, determine that the input and output interface is connected to other servers in the cascade server, and switch the clock transmission direction of the target master-slave switching detection interface to upload; When a low level is detected, the clock transmission direction of the target master-slave switching detection interface is switched to downloading.

6. The master-slave switching interface structure according to claim 2, characterized in that: The routing and switching processor is configured to perform port scanning on the general-purpose input and output pins to determine the connection status of the target master-slave switching detection interface; when the connection status is connected, switch the clock transmission direction of the target master-slave switching detection interface to upload; When the connection state is empty, the clock transmission direction of the target master-slave switching detection interface is switched to downloading.

7. The master-slave switching interface structure according to claim 5, characterized in that: When the clock transmission direction of the target master-slave switching detection interface is downloading, the clock cache module is connected to the clock connection pin through the switch module; when the clock transmission direction of the target master-slave switching detection interface is uploading, the local clock module is connected to the clock connection pin through the second clock input source pin, the first clock output pin, and the switch module.

8. The master-slave switching interface structure according to claim 7, characterized in that: The switch module is a single-pole double-throw switch device. The first input terminal of the single-pole double-throw switch device is connected to the first clock input source pin; The second input terminal of the single-pole double-throw switch device is connected to the first clock output pin; The output end of the single-pole double-throw switch device is connected to the clock connection pin.

9. The master-slave switching interface structure according to claim 8, characterized in that: When the clock transmission direction of the target master-slave switching detection interface is data download, the first input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected; when the clock transmission direction of the target master-slave switching detection interface is data upload, the second input end of the single-pole double-throw switch device and the output end of the single-pole double-throw switch device are connected.

10. The master-slave switching interface structure according to claim 7, characterized in that: The target master-slave switching detection interface also includes: The signal receiving pin and the switch module are configured so that when the clock transmission direction of the target master-slave switching detection interface is data download, the switch module is connected to the clock connection pin and receives the signal.

11. The master-slave switching interface structure according to claim 10, characterized in that: The signal receiving pin is configured to receive a clock reset signal, and the clock reset signal is configured to reset the output signal of the first clock output pin.

12. The master-slave switching interface structure according to claim 1, characterized in that: The master-slave switching interface structure is applied to computer quick connection equipment.

13. A server connection topology system, characterized in that: It comprises a plurality of cascade servers, wherein the cascade servers are deployed with the master-slave switching interface structure according to any one of claims 1 to 12, and the cascade servers are connected to each other through their own master-slave switching interface structure.

14. The server connection topology system according to claim 13, characterized in that: The cascade servers are connected via cables, and the cables include: A plug connected to the master-slave switching interface structure; The second pull-up resistor connects one of the pins of the plug to a preset power source and is configured to place the pin at a high level.

15. The server connection topology system according to claim 14, characterized in that: When the cable is connected to the master-slave switching interface structure, the master-slave switching interface structure is in a high level state; when the cable is not connected to the master-slave switching interface structure, the master-slave switching interface structure is in a low level state.

16. The server connection topology system according to claim 14, characterized in that: The server connection topology system further includes: The master-slave switching processor is configured to detect the level state of the master-slave switching interface structure and set the clock transmission direction of the master-slave switching interface structure.

17. The server connection topology system according to claim 14, characterized in that: When there is a newly added cascade server, the master-slave switching interface structure of the newly added cascade server is connected to the master-slave switching interface structures of other cascade servers through the cable.

18. A distributed server cluster system, characterized in that: The invention comprises a server connection topology system as described in any one of claims 13 to 17.

19. An electronic device, characterized in that: The device comprises a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the master-slave switching interface structure according to any one of claims 1 to 12 is implemented.

20. A non-volatile readable storage medium, characterized in that: The non-volatile readable storage medium stores a computer program, and when the computer program is executed by a processor, the master-slave switching interface structure according to any one of claims 1 to 12 is implemented.

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