Signal transmission method and apparatus

Abstract

A signal transmission method and apparatus, relating to the technical field of communications and capable of enhancing the transmission robustness of traditional signal fields under the condition of minimizing changes to the transmission mode of the traditional signal fields, thereby improving communication performance. The method comprises: a sending end device acquiring a first field; and sending an encoded first field to a receiving end device, wherein the first field comprises a first check bit and a second check bit; the first check bit is a check bit among a plurality of bits in a first bit set other than the first check bit, and the second check bit is a check bit among all bits in the first bit set; or the first check bit and the second check bit are check bits among all bits in the first bit set other than the first check bit; and the first bit set comprises all bits in the first field that are located before the second check bit.

Description

Signal transmission method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 26, 2024, with application number 202410211637.9 and application name “Signal Transmission Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a signal transmission method and device. Background Art

[0003] In a communication system, a transmitting device may encode a legacy signal (L-SIG) field using a 64-state convolutional code with a code rate of 1 / 2. Correspondingly, a receiving device may decode the encoded L-SIG field using a convolutional code decoder with a code rate of 1 / 2.

[0004] Since the L-SIG field includes a 12-bit length information subfield, the actual code rate of the L-SIG field is 1 / 4 (i.e., the ratio of the number of bits of the length information subfield to the number of bits of the encoded L-SIG field (i.e., 48 bits)). If the encoded L-SIG field is further decoded using a convolutional code decoder with a code rate of 1 / 2, the transmission robustness of the L-SIG field will be reduced.

[0005] Therefore, how to improve the transmission robustness of the L-SIG field without changing the transmission method of the L-SIG field as much as possible is an urgent problem to be solved. Summary of the Invention

[0006] The present application provides a signal transmission method and apparatus that can improve the transmission robustness of the L-SIG field while minimizing changes to the transmission mode of the L-SIG field, thereby improving communication performance.

[0007] In a first aspect, a signal transmission method is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself, or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the transmitting device. The method includes: the transmitting device obtains a first field; and sends the encoded first field to the receiving device. The first field includes a first check bit and a second check bit; the first check bit is a check bit of multiple bits in the first bit set except the first check bit, and the second check bit is a check bit of all bits in the first bit set; or the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; the first bit set includes all bits in the first field that are located before the second check bit.

[0008] Based on the above scheme, different from the first field including the second check bit, and the second check bit is the check bit of all bits in the first bit set, in the present application, on the one hand, the first field may also include the first check bit on the basis of including the second check bit, so that the first check bit and the second check bit can be the check bits of all bits in the first bit set except the first check bit, and the transmission robustness of the first field can be improved as much as possible without changing the transmission mode of the first field; on the other hand, the second check bit can still be the check bit of all bits in the first bit set, and on this basis, the first check bit can be the check bit of multiple bits in the first bit set except the first check bit, and multiple bits can be checked again, which can further improve the transmission robustness of the first field, thereby improving the communication performance.

[0009] In a second aspect, a signal transmission method is provided, which can be executed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself, or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the receiving device. The method includes: the receiving device receives information to be decoded from the sending device; based on a first check bit and a second check bit, the information to be decoded is checked to obtain a decoded first field. The information to be decoded includes a first check bit and a second check bit; the first check bit is a check bit of multiple bits in the first bit set except the first check bit, and the second check bit is a check bit of all bits in the first bit set; or the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; the first bit set includes all bits in the first field that are located before the second check bit.

[0010] Based on the above scheme, different from the first field including the second check bit, and the second check bit is the check bit of all the bits in the first bit set, in the present application, on the one hand, the first field may also include the first check bit on the basis of including the second check bit, and the receiving end device may check all the bits in the first bit set except the first check bit according to the first check bit and the second check bit, so as to determine the first field, and the transmission robustness of the first field may be improved as much as possible without changing the transmission mode of the first field; on the other hand, the receiving end device may still check the first bit set according to the second check bit, and on this basis, may use the first check bit to check multiple bits in the first bit set except the first check bit again, which may further improve the transmission robustness of the first field, thereby improving the communication performance.

[0011] In combination with the first aspect and the second aspect, in a possible implementation, the multiple bits in the first bit set other than the first check bit include multiple bits in the first bit set located after the first check bit.

[0012] Based on this possible implementation, in order to determine a limited range of multiple bits excluding the first check bit in the first bit set, the first check bit can be used as the check bit of the multiple bits, providing a feasible solution for determining multiple bits.

[0013] In combination with the first aspect and the second aspect, in a possible implementation, the number of the multiple bits is any one of the following: 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0014] Based on this possible implementation, the number of the multiple bits can be any of the above, which can increase the diversity of the multiple bit design and improve the flexibility of determining the multiple bits.

[0015] In combination with the first and second aspects, in one possible implementation, when the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit, the cyclical redundancy check (CRC) polynomials corresponding to the first check bit and the second check bit satisfy the following formula: p(x)=0x7=1+x+x 2 .

[0016] Based on this possible implementation, the bit values ​​of the first check bit and the second check bit can be determined by the above polynomial, and then the receiving device can determine whether the transmission of the first field is accurate through the bit values ​​of the first check bit and the second check bit, so as to improve the transmission robustness of the first field.

[0017] In combination with the first aspect and the second aspect, in one possible implementation, the multiple bits include the seventh bit, the ninth bit, the eleventh bit, the thirteenth bit, the fifteenth bit, and the seventeenth bit of the first field; or, the multiple bits include the sixth bit, the eighth bit, the tenth bit, the twelfth bit, the fourteenth bit, and the sixteenth bit of the first field.

[0018] Based on this possible implementation, two feasible solutions are provided for determining a plurality of bits.

[0019] In combination with the first aspect and the second aspect, in a possible implementation, the first field is an L-SIG field.

[0020] Based on this possible implementation, a scenario in which the first field can be implemented is provided, that is, the first field can be an L-SIG field, and the L-SIG field can include a first check bit on the basis of including the second check bit, thereby improving the transmission robustness of the L-SIG field.

[0021] In a third aspect, a signal transmission method is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself, or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the transmitting device. The method includes: the transmitting device obtains a first field; and sends the encoded first field to the receiving device. The first field includes a first check bit, a second check bit, and a third check bit; the first check bit, the second check bit, and the third check bit are check bits for all bits in the first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit.

[0022] Based on the above scheme, different from the first field including the second check bit, and the second check bit is the check bit of all the bits in the first bit set, in the present application, the first field may also include the first check bit and the third check bit on the basis of including the second check bit, so that the first check bit, the second check bit, and the third check bit can be the check bits of all the bits in the first bit set except the first check bit and the third check bit. The transmission robustness of the first field can be improved as much as possible without changing the transmission mode of the first field, thereby improving the communication performance.

[0023] In a fourth aspect, a signal transmission method is provided, which can be executed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself, or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or a logic module or software that can realize all or part of the functions of the receiving device. The method includes: the receiving device receives information to be decoded from the sending device; based on the first check bit, the second check bit, and the third check bit, the information to be decoded is checked to obtain a decoded first field. The information to be decoded includes the first check bit, the second check bit, and the third check bit; the first check bit, the second check bit, and the third check bit are check bits of all bits in the first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit.

[0024] Based on the above scheme, different from the first field including the second check bit, and the second check bit is the check bit of all the bits in the first bit set, in the present application, the first field may also include the first check bit and the third check bit on the basis of including the second check bit. The receiving end device can perform check bits on all the bits in the first bit set except the first check bit and the third check bit based on the first check bit, the second check bit, and the third check bit. The transmission robustness of the first field can be improved as much as possible without changing the transmission mode of the first field, thereby improving the communication performance.

[0025] In combination with the third aspect and the fourth aspect, in one possible implementation, the polynomial of the cyclic redundancy check CRC corresponding to the first check bit, the second check bit, and the third check bit satisfies the following formula: p(x)=0x67=1+x+x 2 +x 5 +x 6 .

[0026] Based on this possible implementation, the bit values ​​of the first check bit, the second check bit, and the third check bit can be determined by the above-mentioned CRC polynomial, and then the receiving device can determine whether the transmission of the first field is accurate through the bit values ​​of the first check bit, the second check bit, and the third check bit, so as to improve the transmission robustness of the first field.

[0027] In combination with the third aspect and the fourth aspect, in a possible implementation, the first field is an L-SIG field.

[0028] Based on this possible implementation, a scenario in which the first field can be implemented is provided, that is, the first field can be an L-SIG field, and the L-SIG field can include a first check bit on the basis of including the second check bit, thereby improving the transmission robustness of the L-SIG field.

[0029] In combination with the third aspect and the fourth aspect, in a possible implementation, when the first field is an L-SIG field, the third check bit is one or more bits of a rate information subfield in the L-SIG field.

[0030] Based on this possible implementation, a selectable range can be provided for determining the third parity bit in the L-SIG field, which can increase the diversity of the third parity bit design and improve the flexibility of determining the third bit.

[0031] In combination with the first, second, third and fourth aspects, in a possible implementation, when the first field is an L-SIG field, the first check bit is the fifth bit of the L-SIG field.

[0032] Based on this possible implementation, the first parity bit may be a reserved subfield of the L-SIG field, providing a feasible solution for determining the first parity bit of the L-SIG field.

[0033] In combination with the first, second, third and fourth aspects, in a possible implementation, when the first field is an L-SIG field, the second check bit is the eighteenth bit of the L-SIG field.

[0034] Based on this possible implementation, the second parity bit is the original parity subfield in the L-SIG field, which provides a feasible solution for determining the second parity bit of the L-SIG field.

[0035] In a fifth aspect, a communication device is provided for implementing the method of the first aspect. The communication device may be the transmitting end device of the first aspect, or a device or component included in the transmitting end device, such as a chip.

[0036] The communication device includes modules, units, or means corresponding to the above-mentioned method, which can be implemented by hardware, software, or hardware executing corresponding software implementation. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions.

[0037] In some possible implementations, the communication device may include a processing module and a transceiver module. The transceiver module may include a sending module and a receiving module, respectively used to implement the sending and receiving functions in the above-mentioned first aspect and any possible implementation thereof. The processing module may be used to implement the processing functions in the above-mentioned first aspect and any possible implementation thereof. Exemplarily, the processing module is used to obtain a first field; wherein the first field includes a first check bit and a second check bit; the first check bit is a check bit of multiple bits in the first bit set except the first check bit, and the second check bit is a check bit of all bits in the first bit set; or, the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; the first bit set includes all bits in the first field that are located before the second check bit; the transceiver module is used to send the encoded first field to the receiving device.

[0038] Optionally, the transceiver module and processing module of the communication device in the fifth aspect can also perform the corresponding functions in the above-mentioned first aspect or any possible implementation of the first aspect. Please refer to the detailed description in the method example for details. The beneficial effects that can be achieved can also be referred to the above-mentioned related content.

[0039] In a sixth aspect, a communication device is provided for implementing the method of the second aspect. The communication device may be the receiving device of the second aspect, or a device or component included in the receiving device, such as a chip.

[0040] The communication device includes modules, units, or means corresponding to the above-mentioned method, which can be implemented by hardware, software, or hardware executing corresponding software implementation. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions.

[0041] In some possible implementations, the communication device may include a processing module and a transceiver module. The transceiver module may include a sending module and a receiving module, respectively used to implement the sending and receiving functions in the above-mentioned second aspect and any possible implementation thereof. The processing module may be used to implement the processing functions in the above-mentioned second aspect and any possible implementation thereof. Exemplarily, the transceiver module is used to receive information to be decoded from a transmitting device; wherein the information to be decoded includes a first check bit and a second check bit; the first check bit is a check bit of multiple bits in the first bit set except the first check bit, and the second check bit is a check bit of all bits in the first bit set; or, the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; the first bit set includes all bits in the first field that are located before the second check bit; the processing module is used to check the information to be decoded based on the first check bit and the second check bit to obtain the decoded first field.

[0042] Optionally, the transceiver module and processing module of the communication device in the sixth aspect can also perform the corresponding functions in the above-mentioned second aspect or any possible implementation of the second aspect. Please refer to the detailed description in the method example for details. The beneficial effects that can be achieved can also be referred to the above-mentioned related content.

[0043] In a seventh aspect, a communication device is provided for implementing the method of the third aspect. The communication device may be the transmitting end device of the third aspect, or a device or component included in the transmitting end device, such as a chip.

[0044] The communication device includes modules, units, or means corresponding to the above-mentioned method, which can be implemented by hardware, software, or hardware executing corresponding software implementation. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions.

[0045] In some possible implementations, the communication device may include a processing module and a transceiver module. The transceiver module may include a sending module and a receiving module, respectively used to implement the sending and receiving functions in the above-mentioned third aspect and any possible implementation thereof. The processing module may be used to implement the processing functions in the above-mentioned third aspect and any possible implementation thereof. Exemplarily, the processing module is used to obtain a first field; wherein the first field includes a first check bit, a second check bit, and a third check bit; the first check bit, the second check bit, and the third check bit are check bits of all bits in the first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit; the transceiver module is used to send the encoded first field to the receiving device.

[0046] Optionally, the transceiver module and processing module of the communication device in the seventh aspect can also perform the corresponding functions in the above-mentioned third aspect or any possible implementation of the third aspect. Please refer to the detailed description in the method example for details. The beneficial effects that can be achieved can also be referred to the above-mentioned related content.

[0047] In an eighth aspect, a communication device is provided for implementing the method of the fourth aspect. The communication device may be the receiving device of the fourth aspect, or a device or component included in the receiving device, such as a chip.

[0048] The communication device includes modules, units, or means corresponding to the above-mentioned method, which can be implemented by hardware, software, or hardware executing corresponding software implementation. The hardware or software includes one or more modules or units corresponding to the above-mentioned functions.

[0049] In some possible implementations, the communication device may include a processing module and a transceiver module. The transceiver module may include a sending module and a receiving module, which are respectively used to implement the sending and receiving functions in the above-mentioned fourth aspect and any possible implementation thereof. The processing module may be used to implement the processing functions in the above-mentioned fourth aspect and any possible implementation thereof. Exemplarily, the transceiver module is used to receive information to be decoded from a transmitting device; wherein the information to be decoded includes a first check bit, a second check bit, and a third check bit; the first check bit, the second check bit, and the third check bit are check bits of all bits in the first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit; the processing module is used to check the information to be decoded based on the first check bit, the second check bit, and the third check bit to obtain the decoded first field.

[0050] Optionally, the transceiver module and processing module of the communication device in the eighth aspect can also perform the corresponding functions in the above-mentioned fourth aspect or any possible implementation of the fourth aspect. Please refer to the detailed description in the method example for details. The beneficial effects that can be achieved can also be found in the above-mentioned related content.

[0051] In a ninth aspect, a communication device is provided, comprising: at least one processor, the processor being configured to enable the communication device to execute the method described in any one of the above aspects or any possible implementation of any one of the aspects by executing computer instructions stored in a memory or through a logic circuit. The communication device may be a transmitting end device in the first aspect or any possible implementation of the first aspect, or a device or component included in the transmitting end device, such as a chip; or the communication device may be a receiving end device in the second aspect or any possible implementation of the second aspect, or a device or component included in the receiving end device, such as a chip; or the communication device may be a transmitting end device in the third aspect or any possible implementation of the third aspect, or a device or component included in the transmitting end device, such as a chip; or the communication device may be a receiving end device in the fourth aspect or any possible implementation of the fourth aspect, or a device or component included in the receiving end device, such as a chip.

[0052] In some possible implementations, the communication device further includes a memory for storing computer instructions and / or configuration files of logic circuits. Optionally, the memory is integrated with the processor, or the memory is independent of the processor.

[0053] In a tenth aspect, a communication device is provided, comprising: a processor and a communication interface; the communication interface is used to input and / or output signals; the processor is used to execute a computer program or instruction so that the communication device executes the method described in any of the above aspects. The communication device can be a transmitting end device in the first aspect or any possible implementation of the first aspect, or a device or component included in the transmitting end device, such as a chip; or the communication device can be a receiving end device in the second aspect or any possible implementation of the second aspect, or a device or component included in the receiving end device, such as a chip; or the communication device can be a transmitting end device in the third aspect or any possible implementation of the third aspect, or a device or component included in the transmitting end device, such as a chip; or the communication device can be a receiving end device in the fourth aspect or any possible implementation of the fourth aspect, or a device or component included in the receiving end device, such as a chip.

[0054] In some possible implementations, the communication interface is an interface circuit for reading and writing computer instructions. For example, the interface circuit is used to receive computer execution instructions (computer execution instructions are stored in a memory, may be read directly from the memory, or may pass through other devices) and transmit them to the processor.

[0055] In some possible implementations, the communication interface is used to communicate with a module outside the communication device.

[0056] In some possible implementations, the communication device may be a chip or a chip system. When the device is a chip system, the chip system may include the chip, or may include the chip and other discrete devices.

[0057] In the eleventh aspect, a communication device is provided, comprising: a logic circuit and an interface circuit; the interface circuit is used to input information and / or output information; the logic circuit is used to execute the method described in any of the above aspects, and process and / or generate output information based on the input information. The communication device can be a transmitting end device in the first aspect or any possible implementation of the first aspect, or a device or component included in the transmitting end device, such as a chip; or the communication device can be a receiving end device in the third aspect or any possible implementation of the third aspect, or a device or component included in the receiving end device, such as a chip; or the communication device can be a transmitting end device in the fourth aspect or any possible implementation of the fourth aspect, or a device or component included in the transmitting end device, such as a chip; or the communication device can be a receiving end device in the second aspect or any possible implementation of the second aspect, or a device or component included in the receiving end device, such as a chip.

[0058] In a twelfth aspect, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the method described in any one of the above aspects is executed.

[0059] In a thirteenth aspect, a computer program product is provided, which, when executed by a processor, enables the method described in any one of the above aspects to be executed.

[0060] It can be understood that when the communication device provided in any one of the fifth to eleventh aspects is a chip, the above-mentioned sending action / function can be understood as output information, and the above-mentioned receiving action / function can be understood as input information.

[0061] Among them, the technical effects brought about by any implementation method of the fifth to thirteenth aspects can refer to the technical effects brought about by the above-mentioned first aspect or any possible implementation of the first aspect, or refer to the technical effects brought about by the above-mentioned second aspect or any possible implementation of the second aspect, or refer to the technical effects brought about by the above-mentioned third aspect or any possible implementation of the third aspect, or refer to the technical effects brought about by the above-mentioned fourth aspect or any possible implementation of the fourth aspect, and no further details will be given here.

[0062] In the fourteenth aspect, a communication system is provided, which includes the transmitting device described in the first aspect or any possible implementation of the first aspect and the receiving device described in the second aspect or any possible implementation of the second aspect; or, the system includes the transmitting device described in the third aspect or any possible implementation of the third aspect and the receiving device described in the fourth aspect or any possible implementation of the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG1 is a schematic diagram of an encoder provided in an embodiment of the present application;

[0064] FIG2 is a schematic diagram of a generator polynomial corresponding to an encoder provided in an embodiment of the present application;

[0065] FIG3 is a schematic diagram of the structure of a protocol data unit provided in an embodiment of the present application;

[0066] FIG4 is a schematic diagram of the structure of an L-SIG field provided in an embodiment of the present application;

[0067] FIG5 is a schematic diagram of a communication system provided in an embodiment of the present application;

[0068] FIG6 is a schematic diagram of a communication system provided in an embodiment of the present application;

[0069] FIG7 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0070] FIG8 is an interactive schematic diagram of a signal transmission method provided in an embodiment of the present application;

[0071] FIG9 is an interactive schematic diagram of a signal transmission method provided in an embodiment of the present application;

[0072] FIG10 is a schematic diagram of a simulation of a different decoding algorithm provided in an embodiment of the present application;

[0073] FIG11 is a schematic diagram of a simulation of a different decoding algorithm provided in an embodiment of the present application;

[0074] FIG12 is a schematic diagram of a simulation of a different decoding algorithm provided in an embodiment of the present application;

[0075] FIG13 is a schematic diagram of a simulation of a different decoding algorithm provided in an embodiment of the present application;

[0076] FIG14 is a schematic diagram of a simulation of a different decoding algorithm provided in an embodiment of the present application;

[0077] FIG15 is a schematic structural diagram of a transmitting end device provided in an embodiment of the present application;

[0078] FIG16 is a schematic structural diagram of a receiving device provided in an embodiment of the present application;

[0079] FIG17 is a schematic structural diagram of another communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0080] The following describes in detail the implementation of the embodiments of the present application in conjunction with the accompanying drawings.

[0081] In the description of this application, unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship, for example, A / B can represent A or B; "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural.

[0082] In the description of this application, unless otherwise specified, "plurality" means two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0083] In addition, to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first" and "second" do not limit the quantity or execution order, and the words "first" and "second" do not necessarily mean different.

[0084] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner to facilitate understanding.

[0085] It will be understood that the “embodiment” mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It will be understood that in the various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0086] It is understood that some optional features in the embodiments of the present application may, in certain scenarios, be implemented independently of other features, such as the solution on which they are currently based, to solve corresponding technical problems and achieve corresponding effects. They may also be combined with other features in certain scenarios as needed. Accordingly, the devices provided in the embodiments of the present application may also implement these features or functions accordingly, which will not be described in detail here.

[0087] In this application, unless otherwise specified, the same or similar parts between the various embodiments can be referenced to each other. In the various embodiments of this application, unless otherwise specified and there is no logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships. The following description of the embodiments of this application does not constitute a limitation on the scope of protection of this application.

[0088] In order to facilitate understanding of the technical solutions of the embodiments of the present application, a brief introduction to the relevant technologies of the present application is first given as follows.

[0089] 1) Channel Coding Scheme

[0090] IEEE (Institute of Electrical and Electronics Engineers) 802.11n / ac / ax / be wireless local area networks (WLANs) focus on improving user experience in high-bandwidth scenarios. They enable high-speed, reliable transmission of data, video, and other services using limited frequency and power resources. Consequently, they can improve average user throughput and the energy efficiency of battery-powered devices through highly reliable and efficient channel coding schemes.

[0091] Among them, in the field of channel coding, Turbo code and low-density parity check code (LDPC) are two relatively mature and widely used channel codes. Both have performance close to the Shannon limit and are widely used in the communication field.

[0092] Among them, LDPC code has become the standard channel coding scheme for low-frequency, short-range WLAN communication systems such as IEEE 802.11n / ac / ax, and has become a mandatory channel coding scheme when 802.11ax has a bandwidth greater than or equal to 40MHz.

[0093] In addition, since the early 802.11 WLAN transmission standard was proposed, binary convolutional code (BCC) has been retained as a mandatory channel coding scheme.

[0094] BCC is widely used for encoding and decoding the signal (SIG) field and data portion of the physical frame header. As of the 802.11ax standard, BCC remains the mandatory and only encoding method for fields like the SIG due to its forward compatibility and low encoding complexity.

[0095] 802.11ax defines channel coding for the data portion as follows: When BCC is used for channel coding of the data portion, the number of encoders operating simultaneously may be one; LDPC may be used for channel coding of high-efficiency (HE)-physical protocol data units (PPDUs) (i.e., 802.11ax physical layer data frames) transmitted with 484 resource units (RUs), 996 RUs, and 2×996 RUs; LDPC is the only channel coding method for HE-PPDUs with modulation and coding schemes (MCS) of 10 and 11; BCC may be used for channel coding of HE-PPDUs with MCSs of 0-9 and less than or equal to four spatial streams (i.e., multiple-input and multi-output (MIMO) data streams); and BCC may be used for channel coding when the RU size is less than or equal to 242 subcarriers.

[0096] 2) BCC

[0097] BCC was first proposed by Elias in 1955. In 1967, Andrew J. Viterbi invented an efficient decoding algorithm, namely, the Viterbi decoding algorithm, which has become a widely used convolutional code decoder.

[0098] Among them, the BCC code is called a convolutional code because the data is slidingly correlated with the binary polynomial. It is a channel code with memory.

[0099] Among them, the encoding rule of BCC is to encode k information bits into n bits. The encoded n codewords are not only related to the current k information bits input, but also to the previous L-1 information bits, where L is the constraint length of the convolutional code.

[0100] Wherein, n, k, and L are positive integers.

[0101] In one possible design, the convolutional code used in the WLAN transmission standard is a BCC code rate of 1 / 2, where k = 1 and n = 2. As shown in Figure 1 below, the encoder has six shift registers (represented by Tb in the figure) and a constraint length of 7 (i.e., L = 7).

[0102] When one information bit is input, two information bits can be output (e.g., one input information bit K i (K i Generate two codeword bits A for one information bit in the bit sequence K i (A i is a codeword bit in the bit sequence A) and B i (B i is a codeword bit in the bit sequence B), that is, the two information bits obtained by encoding are not only related to the current input information bit, but also related to the previous 6 input information bits (for example, the output information bit sequence can be (A1, B1, A2, B2, ..., A i ,B i ,…)).

[0103] Among them, the encoder shown in Figure 1 can be specifically represented by its generating polynomial, that is, in octal form [133,171], where the binary coefficient sequence corresponding to 133 is [1011011], and the binary coefficient sequence corresponding to 171 is [1111001]. The generating polynomial corresponding to the encoder can be shown in Figure 2 below.

[0104] 1 and 2 , before convolution coding is performed, the values ​​in the shift registers can all be set to 0, and at the end of coding, 6 zeros need to be added to reset the 6 shift registers of the encoder to 0.

[0105] 3) SIG field

[0106] Among them, the SIG field may include an L-SIG field and an RL-SIG field, and the positions of the L-SIG field and the short legacy (RL)-SIG field in an ultra high throughput (EHT)-PPDU may be as shown in FIG. 3 below.

[0107] Among them, the EHT-PPDU may include a legacy short training field (L-short training field, L-STF) (the duration of the L-STF is 8 μs), a legacy long training field (L-long training field, L-LTF) (the duration of the L-LTF is 8 μs), an L-SIG field (the duration of the L-SIG field is 4 μs), an RL-SIG field (the duration of the RL-SIG field is 4 μs), an ultra-signal (U-SIG) field (the duration of the U-SIG field is 4 μs), a high-throughput signal (EHT-SIG) field (the duration of the EHT-SIG field is 4 μs), an ultra-high throughput short training field (EHT-STF) (the duration of the EHT-STF is 4 μs), one or more ultra-high throughput long and short training fields (EHT-LTF) (the duration of one or more EHT-LTFs can be determined according to the number of EHT-LTF fields and the duration of each EHT-LTF field), and data.

[0108] The L-SIG field is used to indicate the coding rate and the length of the EHT-PPDU, and the RL-SIG field is used to distinguish whether the physical frame in which the PPDU is located is an 802.11ax physical frame.

[0109] Exemplarily, the L-SIG field can be as shown in Figure 4 below. The information bit sequence in the L-SIG field consists of 24 bits, and the L-SIG field includes a code rate information subfield, a reserved subfield (such as R in Figure 4), a length information subfield, a check subfield (such as CRC in Figure 4), and a padding subfield.

[0110] Among them, the rate information subfield occupies four bits of the L-SIG field (i.e., the first bit to the fourth bit of the L-SIG field (in this case, the starting bit of the L-SIG field is the first bit), which can also be described as the zeroth bit to the third bit (i.e., bit [0]-bit [3]) (in this case, the starting bit of the L-SIG field is the zeroth bit)). The bit sequence in the code rate information subfield is fixed and is 1101.

[0111] Among them, the reserved subfield occupies one bit of the L-SIG field (i.e., the fifth bit of the L-SIG field (in this case, the starting bit of the L-SIG field is the first bit), and can also be described as the fourth bit (i.e., bit [4]) (in this case, the starting bit of the L-SIG field is the zeroth bit)).

[0112] Among them, the length information subfield occupies twelve bits of the L-SIG field (i.e., the sixth bit to the seventeenth bit of the L-SIG field (in this case, the starting bit of the L-SIG field is the first bit), and can also be described as the fifth bit value sixth bit (such as bit [5]-bit

[0016] ) (in this case, the starting bit of the L-SIG field is the zeroth bit)).

[0113] Among them, the check subfield occupies one bit of the L-SIG field (that is, the eighteenth bit of the L-SIG field (in this case, the starting bit of the L-SIG field is the first bit), and can also be described as the seventeenth bit (that is, bit

[0017] ) (in this case, the starting bit of the L-SIG field is the zeroth bit)).

[0114] Optionally, the check bits may be used to perform parity check on the first seventeen bits of the L-SIG field.

[0115] Among them, the padding subfield occupies six bits of the L-SIG field (i.e., the 19th bit to the 24th bit of the L-SIG field (in this case, the starting bit of the L-SIG field is the first bit), which can also be described as the 18th bit to the 23rd bit (i.e., bit

[0018] -bit

[0023] (in this case, the starting bit of the L-SIG field is the zeroth bit)).

[0116] It can be understood that the bit sequence of the padding subfield can be 000000, that is, the padding subfield is used to reset the convolutional code encoder to an all-zero state after the encoding is completed.

[0117] 4) L-SIG field encoding and decoding

[0118] The L-SIG field may be encoded by a 64-state convolutional code with a code rate of 1 / 2 (such as the convolutional codes shown in FIG1 and FIG2 ), thereby obtaining a 48-encoded bit sequence.

[0119] Since the L-SIG field includes a 12-bit length information subfield (the actual code rate of the L-SIG field is 1 / 4 (i.e., the ratio of the number of bits of the length information subfield to the number of bits of the encoded L-SIG field (i.e., 48 bits)), if the encoded L-SIG field is further decoded using a convolutional code decoder with a code rate of 1 / 2, the transmission reliability of the L-SIG field will be reduced.

[0120] Therefore, the present application provides a signal transmission method, the method comprising: a transmitting device obtaining a first field; and transmitting the encoded first field to a receiving device. The first field includes a first parity bit and a second parity bit; the first parity bit is a parity bit of multiple bits in a first bit set excluding the first parity bit, and the second parity bit is a parity bit of all bits in the first bit set; or the first parity bit and the second parity bit are parity bits of all bits in the first bit set excluding the first parity bit; and the first bit set includes all bits in the first field that are located before the second parity bit.

[0121] In the embodiment of the present application, unlike the first field including the second check bit, and the second check bit is the check bit of all the bits in the first bit set, in the present application, on the one hand, the first field may further include the first check bit on the basis of including the second check bit, so that the first check bit and the second check bit can be the check bits of all the bits in the first bit set except the first check bit, and the transmission robustness of the first field can be improved as much as possible without changing the transmission mode of the first field; on the other hand, the second check bit can still be the check bit of all the bits in the first bit set, and on this basis, the first check bit can be the check bit of multiple bits in the first bit set except the first check bit, and multiple bits can be checked again, which can further improve the transmission robustness of the first field, thereby improving the communication performance.

[0122] The signal transmission method provided in the embodiment of the present application is applicable to WLANs that support IEEE-related standards, including: 802.11a / b / g standards, 802.11n standards, 802.11ac standards, 802.11ax standards, 802.11be standards, 802.11bn standards / UHR standards / WiFi8 standards, 802.11ad standards, 802.11ay standards, 802.11bf standards / sensing standards, UWB standards / 802.15 standards, etc., without limitation.

[0123] For example, as shown in Figure 5, which is a schematic diagram of the structure of a communication system provided by the present application, the communication system may include a transmitting device and a receiving device.

[0124] Among them, the sending end device can be any access point (AP) device or station (STA) device in the communication system shown in Figure 6, and the receiving end device can be any access point device or station device in the communication system shown in Figure 6.

[0125] Figure 6 is a schematic diagram of a communication system provided in an embodiment of the present application. As shown in Figure 6, the communication system may include access point devices and site devices; wherein, one or more access point devices can communicate with one or more site devices, the access point device can also communicate with one or more other access point devices, and the site device can also communicate with one or more other site devices.

[0126] For example, as shown in (a) of FIG6 , the access point device may communicate with one site device, or, as shown in (b) of FIG6 , the access point device may communicate with at least two site devices (such as site device 1, site device 2, and site device 3).

[0127] The access point device may be an AP, and the station device may be a STA.

[0128] Exemplarily, the AP can be a device that supports multiple WLAN standards such as the 802.11be standard or the future wireless fidelity (Wi-Fi) standard; it can also be a device that supports the 802.11a / b / g standard, 802.11n standard, 802.11ac standard, 802.11ax standard, 802.11be standard, 802.11bn standard / UHR standard / WiFi8 standard, without limitation.

[0129] For example, an AP can be a terminal device equipped with a Wi-Fi chip, a network device, a communications server, a router, a switch, a bridge, or a computer. APs can also serve as access points for mobile users to wired networks. They are primarily deployed in homes, buildings, and campuses, with a typical coverage radius of tens to hundreds of meters. They can also be deployed outdoors. An AP acts as a bridge between wired and wireless networks, connecting wireless network clients and then connecting the wireless network to the Ethernet.

[0130] Exemplarily, a STA may be a device that supports multiple WLAN standards, such as the 802.11be standard or future Wi-Fi standards; or a device that supports the 802.11a / b / g standard, 802.11n standard, 802.11ac standard, 802.11ax standard, 802.11be standard, 802.11bn standard / UHR standard / WiFi8 standard, without limitation.

[0131] For example, a STA can be a wireless communication chip, wireless sensor, wireless communication terminal, communication server, router, switch, bridge, computer, etc. For example, a STA can be a mobile phone supporting Wi-Fi communication function, a tablet supporting Wi-Fi communication function, a set-top box supporting Wi-Fi communication function, a smart TV supporting Wi-Fi communication function, a smart wearable device supporting Wi-Fi communication function, an in-vehicle communication device supporting Wi-Fi communication function, a computer supporting Wi-Fi communication function, etc., without limitation.

[0132] It should be noted that the communication system described in the embodiment of the present application is intended to more clearly illustrate the technical solution of the embodiment of the present application, and does not constitute a limitation on the technical solution provided in the embodiment of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.

[0133] In specific implementations, the transmitting device or receiving device shown in Figure 5 can adopt the structure shown in Figure 7, or include the components shown in Figure 7. Figure 7 is a schematic diagram of the structure of a communication device 70 provided in an embodiment of the present application. The communication device 70 can be a transmitting device or a chip or system-on-chip in the transmitting device; it can also be a receiving device or a chip or system-on-chip in the receiving device.

[0134] As shown in FIG7 , the communication device 70 includes one or more processors 701. Furthermore, the communication device 70 may also include a communication bus 702 and at least one communication interface 704 ( FIG7 is merely exemplary, and the communication device 70 includes a communication interface 704 and one processor 701 for illustration). Optionally, the communication device 70 may also include a memory 703.

[0135] Processor 701 can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application, or a processing core for processing data (e.g., computer program instructions). The processor can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.

[0136] In a specific implementation, as an embodiment, the processor 701 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 7 .

[0137] Communication bus 702 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Such buses may be classified as address buses, data buses, and control buses. For ease of illustration, FIG7 shows only one thick line, but this does not imply a single bus or type of bus. Communication bus 702 is used to connect the various components within communication device 70, enabling communication and interaction between the various components within communication device 70.

[0138] The communication interface 704 may be a transceiver module for communicating with other devices or a communication network, such as Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). For example, the communication interface 704 may be a device such as a transceiver or a transceiver. Alternatively, the communication interface 704 may be a transceiver circuit within the processor 701 for implementing signal input and output to the processor.

[0139] The memory 703 may be a device having a storage function. For example, it may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a communication bus 702. The memory may also be integrated with the processor.

[0140] Exemplarily, the memory 703 is used to store computer-executable instructions for executing the solution of the present application, and the execution is controlled by the processor 701. The processor 701 is used to execute the computer-executable instructions stored in the memory 703, thereby implementing the method provided in the embodiment of the present application.

[0141] Alternatively, optionally, in an embodiment of the present application, the processor 701 may also perform processing-related functions in the method provided in the following embodiments of the present application, and the communication interface 704 is responsible for communicating with other devices or communication networks, which is not specifically limited in the embodiments of the present application.

[0142] Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application code, which is not specifically limited in the embodiments of the present application.

[0143] In a specific implementation, as an embodiment, the communication device 70 may further include an output device 705 and an input device 706. The output device 705 communicates with the processor 701 and can display information in a variety of ways. For example, the output device 705 can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device 706 communicates with the processor 701 and can receive user input in a variety of ways. For example, the input device 706 can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0144] It should be noted that the composition structure shown in Figure 7 does not constitute a limitation on the communication device. In addition to the components shown in Figure 7, the communication device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0145] The signal transmission method provided by the embodiment of the present application will be described below in conjunction with the accompanying drawings. It is understood that in the embodiment of the present application, the transmitting end device or the receiving end device can perform some or all of the steps in the embodiment of the present application. These steps or operations are merely examples, and the embodiment of the present application can also perform other operations or variations of various operations. In addition, the various steps can be performed in a different order than those presented in the embodiment of the present application, and it is possible that not all operations in the embodiment of the present application need to be performed.

[0146] FIG8 is an interaction diagram of a signal transmission method provided by the present application. The signal transmission method is described by taking the interaction between a transmitting device and a receiving device as an example. For example, referring to FIG8 , the signal transmission method includes the following steps:

[0147] S801: The sending device obtains a first field.

[0148] The first field includes a first check bit and a second check bit.

[0149] The second check bit is carried in the check subfield of the first field.

[0150] It can be understood that the check subfield can be used to check all bits in the first field before the check subfield, or it can be understood that the check subfield is the check bit of all bits in the first field before the check subfield.

[0151] It can be understood that when the check subfield occupies one bit of the first field, the second check bit is one bit; or when the check field occupies multiple bits of the first field, the second check bit is multiple bits.

[0152] Exemplarily, when the check subfield occupies one bit of the first field, the second check bit is the one bit; when the check subfield occupies at least one bit of the first field, for example, taking the check subfield occupies two bits of the first field (such as bit 11 and bit 12) as an example, the second check bit can be bit 11 and bit 12.

[0153] For ease of understanding, this application is described by taking the second check bit as one bit as an example.

[0154] The first check bit is carried in a reserved subfield in the first field.

[0155] It can be understood that when the reserved subfield occupies one bit of the first field, the first check bit can be one bit; or, when the reserved subfield occupies multiple bits of the first field, the first check bit can be one bit or multiple bits, without limitation.

[0156] Exemplarily, when the reserved subfield occupies one bit of the first field, the second check bit is the one bit; when the reserved subfield occupies at least two bits of the first field, the first check bit can be one bit or multiple bits. For example, taking the reserved subfield occupying two bits of the first field (such as bit 21 and bit 22) as an example, the first check bit can be bit 21, or the first check bit can be bit 22, or the first check bit can be bit 21 and bit 22.

[0157] For ease of understanding, this application is described using an example in which the first check bit is one bit.

[0158] Based on the above description of the first check bit and the second check bit, this application proposes two possible check methods:

[0159] In a first check method, the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit.

[0160] The first bit set includes all bits in the first field that are located before the second check bit.

[0161] For example, taking the starting bit as bit [0] and the second check bit as bit

[0017] in the first field as an example, the first bit set includes bit [0], bit [1], ..., bit

[0016] .

[0162] The bit values ​​of the first check bit and the second check bit can be determined by a CRC polynomial, and the CRC polynomial corresponding to the first check bit and the second check bit (which can be referred to as a first CRC polynomial) can satisfy the following formula: p(x)=0x7=1+x+x 2 .

[0163] Exemplarily, the bit values ​​of all bits in the first bit set except the first check bit may be divided by the first CRC polynomial, and the remainder obtained is the bit value of the first check bit and the second check bit.

[0164] For example, when the above remainder is 00, the bit value of the first check bit can be 0, and the bit value of the second check bit can be 0; or, when the above remainder is 10, the bit value of the first check bit can be 1, and the bit value of the second check bit can be 0; or, when the above remainder is 01, the bit value of the first check bit can be 0, and the bit value of the second check bit can be 1; or, when the above remainder is 11, the bit value of the first check bit can be 1, and the bit value of the second check bit can be 1.

[0165] Based on this verification method, the bit values ​​of the first check bit and the second check bit can be determined by the above polynomial, and then the receiving device can determine whether the transmission of the first field is accurate through the bit values ​​of the first check bit and the second check bit, so as to improve the transmission robustness of the first field.

[0166] In a second verification method, the first check bit is a check bit of a plurality of bits in the first bit set except the first check bit, and the second check bit is a check bit of all bits in the first bit set.

[0167] It can be understood that the multiple bits in the first bit set excluding the first check bit may be at least two arbitrary bits in the first bit set excluding the first check bit.

[0168] For ease of understanding, the multiple bits in the first bit set excluding the first check bit may be referred to as the second bit set, or referred to as all bits in the second bit set.

[0169] For example, taking the example where the first bit set includes bit [0]-bit

[0016] and the first check bit is bit [4], the second bit set may include bit [0]-bit [3] and at least two bits from bit [5]-bit

[0016] , such as the second bit set may include bit [0] and bit [3].

[0170] It is understandable that the bit value of the first check bit may be determined first, and then the bit value of the second check bit may be determined.

[0171] Among them, for the first check bit being the check bit of all bits in the second bit set, the first check bit can check all bits in the second bit set. This application proposes two possible implementations for determining the bit value of the first check bit:

[0172] In a first possible implementation, the bit value of the first parity bit can be determined by performing a parity check on all bits in the second bit set using the first parity bit. That is, when the first parity bit performs an odd parity check on all bits in the second bit set, if the number of 1s in the bit values ​​of all bits in the second bit set is an even number, the bit value of the first parity bit is 1; if the number of 1s in the bit values ​​of all bits in the second bit set is an odd number, the bit value of the first parity bit is 0. Alternatively, when the first parity bit performs an even parity check on all bits in the second bit set, if the number of 1s in the bit values ​​of all bits in the second bit set is an odd number, the bit value of the first parity bit is 1; if the number of 1s in the bit values ​​of all bits in the second bit set is an even number, the bit value of the first parity bit is 0.

[0173] In a second possible implementation, the bit value of the first check bit can be determined by a CRC polynomial, that is, the CRC polynomial corresponding to the first check bit (which can be called a second CRC polynomial) can satisfy the following formula: p(x)=0x3=1+x.

[0174] Exemplarily, the bit values ​​of all bits in the second bit set may be divided by the second CRC polynomial, and the remainder obtained is the bit value of the first check bit.

[0175] For example, when the remainder is 0, the bit value of the first check bit may be 0; or, when the remainder is 1, the bit value of the first check bit may be 1.

[0176] Among them, for the second check bit being a check bit for all bits in the first bit set, the second check bit can check all bits in the first bit set (including the first check bit, and the bit value of the first check bit has been determined). This application proposes two possible implementations for determining the bit value of the second check bit:

[0177] In a first possible implementation, the bit value of the second parity bit can be determined by performing a parity check on all bits in the first bit set using the second parity bit. That is, when the first parity bit performs an odd parity check on all bits in the second bit set, if the number of 1s in the bit values ​​of all bits in the first bit set is an even number, the bit value of the second parity bit is 1; if the number of 1s in the bit values ​​of all bits in the first bit set is an odd number, the bit value of the second parity bit is 0. Alternatively, when the second parity bit performs an even parity check on all bits in the first bit set, if the number of 1s in the bit values ​​of all bits in the first bit set is an odd number, the bit value of the second parity bit is 1; if the number of 1s in the bit values ​​of all bits in the first bit set is an even number, the bit value of the second parity bit is 0.

[0178] In a second possible implementation, the bit value of the second check bit can be determined by a CRC polynomial, that is, the CRC polynomial corresponding to the second check bit (which can be called a second CRC polynomial) can satisfy the following formula: p(x)=0x3=1+x.

[0179] Exemplarily, the bit values ​​of all bits in the first bit set may be divided by the first CRC polynomial, and the remainder obtained is the bit value of the second check bit.

[0180] For example, when the remainder is 0, the bit value of the second check bit may be 0; or, when the remainder is 1, the bit value of the second check bit may be 1.

[0181] Optionally, the first field may be a field having a reserved subfield.

[0182] It can be understood that the reserved subfield may occupy one bit of the first field or multiple bits of the first field, without limitation.

[0183] The first field may be a SIG field, further, the first field may be an L-SIG field, or the first field may be an RL-SIG field.

[0184] It can be understood that the present application provides multiple scenarios in which the first field can be implemented, that is, the first field can be an L-SIG field or an RL-SIG field. The L-SIG field or the RL-SIG field can include the first check bit on the basis of including the second check bit, thereby improving the transmission robustness of the L-SIG field or the RL-SIG field.

[0185] In a possible embodiment, the first field may be an L-SIG field, and the L-SIG field may be as shown in FIG. 4 above.

[0186] Among them, for the position of the first check bit in the L-SIG field, the first check bit can be the fifth bit of the L-SIG field (in this case, the starting bit of the first field is the first bit, and the fifth bit is a reserved subfield of the L-SIG field); or, the first check bit can be the fourth bit of the L-SIG field (i.e., bit [4]) (in this case, the starting bit of the first field is the zeroth bit (i.e., bit [0]), and the bit [4] is a reserved subfield of the L-SIG field).

[0187] Among them, for the position of the second check bit in the L-SIG field, the second check bit can be the eighteenth bit of the L-SIG field (in this case, the starting bit of the first field is the first bit, and the eighteenth bit is the check subfield of the L-SIG field); or, the second check bit is the seventeenth bit of the L-SIG field (i.e., bit

[0017] ) (in this case, the starting bit of the first field is the zeroth bit (i.e., bit [0]), and bit

[0017] is the check subfield of the L-SIG field).

[0188] S802: The transmitting device sends the encoded first field to the receiving device; correspondingly, the receiving device receives the information to be decoded from the transmitting device.

[0189] The transmitting device may encode the first field through BCC to obtain the encoded first field.

[0190] Exemplarily, the transmitting device may encode the first field using BCC with a code rate of 1 / 2.

[0191] Furthermore, the transmitting device may map and transmit the encoded first field.

[0192] Exemplarily, the transmitting device may map and send the first field in the time domain, or the transmitting device may map and send the first field in the frequency domain, or the transmitting device may map and send the first field in the time-frequency domain, without limitation.

[0193] S803: The receiving end device verifies the information to be decoded according to the first check bit and the second check bit to obtain the decoded first field.

[0194] The receiving device may decode the information to be decoded according to a decoding algorithm.

[0195] Among them, for the first verification method in S801, the receiving device can divide the bit values ​​of all bits in the first bit set except the first check bit by the bit values ​​of the first check bit and the second check bit. If the remainder is 0, it indicates that the first field is transmitted correctly; otherwise, it indicates that the first field is transmitted incorrectly.

[0196] It is understandable that if the receiving device determines that the first field is transmitted erroneously, it may notify the transmitting device to retransmit the first field or perform error correction on the first field to improve the transmission robustness of the first field.

[0197] Among them, for the second verification method in S801, the receiving device can divide the bit value of all bits in the first bit set by the first check bit, and the remainder can be called the first remainder. If the first remainder is 0, the bit value of all bits in the second bit set can be further divided by the second check bit, and the resulting remainder can be called the second remainder. If the second remainder is 0, it indicates that the transmission of the first field is correct; if the second remainder is not 0, it indicates that the transmission of all bits in the second bit set is erroneous.

[0198] If the first remainder is not 0, it indicates that the transmission of the first field is erroneous. The bit values ​​of all bits in the second bit set can be further divided by the second check bit. The resulting remainder can be called the second remainder. If the second remainder is 0, it indicates that all bits in the second bit set are transmitted correctly. If the second remainder is not 0, it indicates that the transmission of all bits in the first bit set except the second bit set is erroneous.

[0199] It is understandable that, when it is determined that the first field is transmitted erroneously, the receiving device can more accurately determine the bit of the transmission error, thereby further improving the transmission robustness of the first field.

[0200] Optionally, the receiving device may decode the information to be decoded according to a Viterbi decoding algorithm, or the receiving device may decode the information to be decoded according to a convolutional code soft-input soft-output (SISO) decoding algorithm, or the receiving device may decode the information to be decoded according to a list decoding algorithm.

[0201] It is understood that the convolutional code SISO decoding algorithm has the ability to calculate information at the output and utilize one or more bits of prior information, while the list decoding algorithm can also use fixed bits of prior information.

[0202] The computational complexity of the convolutional code SISO decoding algorithm is roughly twice that of the Viterbi decoding algorithm, while the computational complexity of the list decoding algorithm can be determined based on the parameter "maximum weak confidence (MaxWeak)" and the specific signal-to-noise ratio (SNR).

[0203] Here, MaxWeak refers to the maximum number of weak confidence positions that need to be considered in the decoding process. In this application, the maximum number of weak confidence positions can be understood as the number of check bits.

[0204] It is understandable that the value of the parameter Maxweak (ie the maximum number of weak confidence positions that need to be considered during the decoding process) cannot exceed the number of check bits.

[0205] Based on the signal transmission method shown in Figure 8 above, different from the first field including the second check bit, and the second check bit is the check bit of all bits in the first bit set, in the present application, on the one hand, the first field may also include the first check bit on the basis of including the second check bit, so that the first check bit and the second check bit can be the check bits of all bits in the first bit set except the first check bit, and the transmission robustness of the first field can be improved as much as possible without changing the transmission mode of the first field; on the other hand, the second check bit can still be the check bit of all bits in the first bit set, and on this basis, the first check bit can be the check bit of multiple bits in the first bit set except the first check bit, and multiple bits can be checked again, which can further improve the transmission robustness of the first field, thereby improving the communication performance.

[0206] Based on the above S801 description of multiple bits in the first bit set except the first check bit (i.e., all bits in the second bit set), the number of all bits in the second bit set can be one or more of the following: 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0207] It is understandable that the number of all bits in the second bit set can be any of the above, which can increase the diversity of the design of the second bit set and improve the flexibility of determining the second bit set.

[0208] In a first possible design, all bits in the second bit set may be any at least two bits from all bits in the first bit set excluding the first parity bit. For example, taking the first bit set including bits [0]-bit

[0016] as an example, assuming the first parity bit is bit [4], then, when the number of all bits in the second bit set is 2, the second bit set may include bit [0] and bit [1], or the second bit set may include bit [0] and bit [2], or the second bit set may include bit [0] and bit [3], or the second bit set may include bit [0] and bit [5] (bit [4] is the first parity bit, so bit [4] is avoided), etc.

[0209] In a second possible design, all bits in the second bit set may be a plurality of bits located after the first parity bit in the first bit set (the plurality of bits is still at least two bits). For example, taking the first bit set including bits [0]-bits

[0016] as an example, assuming that the first parity bit is bit [4], then, when the number of all bits in the second bit set is 2, the second bit set may include bit [5] and bit [6], or the second bit set may include bit [5] and bit [7], or the second bit set may include bit [5] and bit [8], etc.

[0210] Based on the second possible design, in order to determine the limited range of all bits in the second bit set, that is, all bits except the first check bit in the first bit set are narrowed down to multiple bits in the first bit set located after the first check bit. This can more effectively check the first field, improve the transmission robustness of the first field, and provide a feasible solution for determining all bits in the second bit set.

[0211] Based on the above two possible designs, the present application proposes a method for determining all bits in the second bit set. Taking the first bit set including bit [0]-bit

[0016] and the total number of bits in the second bit set as an example, assuming that the first check bit is bit [4], the first bit can be determined to be bit [0] first, and the second bit can be the bit after bit [0]. For example, the second bit set includes bit [0] and bit [1], or includes bit [0] and bit [2], ..., or includes bit [0] and bit

[0016] . Alternatively, the first bit can be determined to be bit [1] first, and the second bit can be the bit after bit [1]. For example, the second bit set includes bit [1] and bit [2], or includes bit [1] and bit [3], ..., or includes bit [1] and bit

[0017] . And so on. All bits in the second bit set can be determined in any case.

[0212] It is understandable that when determining all bits in the second bit set, the first check bit (such as bit [4]) needs to be avoided.

[0213] Based on the above description of all bits in the second bit set, the number of all bits in the second bit set may be 6. This application proposes two possible embodiments for determining the specific six bits:

[0214] In one possible embodiment, when the starting bit of the first field is the first bit, the second bit set may include the seventh bit, the ninth bit, the eleventh bit, the thirteenth bit, the fifteenth bit, and the seventeenth bit of the first field; or, when the starting bit of the first field is the zeroth bit (i.e., bit [0]), the second bit set may include the sixth bit (i.e., bit [6]), the eighth bit (i.e., bit [8]), the tenth bit (i.e., bit

[0010] ), the twelfth bit (i.e., bit

[0012] ), the fourteenth bit (i.e., bit

[0014] ), and the sixteenth bit (i.e., bit

[0016] ) of the first field.

[0215] For example, taking the first field as the L-SIG field, all bits in the first bit set in the L-SIG field can be bit [0]-bit

[0016] , and the second bit set can be represented by a pattern (each bit in the pattern corresponds to the position of a bit in the second bit set in the first bit set), for example, the pattern corresponding to the second bit set can be 00000010101010101; or, when the pattern does not include the first check bit, the pattern corresponding to the second bit set can be 0000010101010101.

[0216] In another possible embodiment, when the starting bit of the first field is the first bit, the second bit set may include the sixth bit, the eighth bit, the tenth bit, the twelfth bit, the fourteenth bit, and the sixteenth bit of the first field; or, when the starting bit of the first field is the zeroth bit (i.e., bit [0]), the second bit set may include the fifth bit (i.e., bit [5]), the seventh bit (i.e., bit [7]), the ninth bit (i.e., bit [9]), the eleventh bit (i.e., bit

[0011] ), the thirteenth bit (i.e., bit

[0013] ), and the fifteenth bit (i.e., bit

[0015] ) of the first field.

[0217] For example, taking the first field as the L-SIG field, all bits in the first bit set in the L-SIG field can be bit [0]-bit

[0016] , and the second bit set can be represented by a pattern (each bit in the pattern corresponds to the position of a bit in the second bit set in the first bit set), for example, the pattern corresponding to the second bit set can be 00000101010101010; or, when the pattern does not include the first check bit, the pattern corresponding to the second bit set can be 0000101010101010.

[0218] It can be understood that the sending device and the receiving device can determine all the bits in the second bit set based on a predefined pattern, or the sending device can determine the pattern based on the actual communication scenario or communication situation, and send the first indication information to the receiving device so that the receiving device determines all the bits in the second bit set based on the first indication information.

[0219] Specifically, the sending end device sends the first indication information to the receiving end device; correspondingly, the receiving end device receives the first indication information from the sending end device.

[0220] The first indication information is used to indicate positions of all bits in the second bit set in the first bit set.

[0221] In an example, taking the first indication information as an index of a pattern, assuming that there are 2 patterns (such as pattern 1 is 00000010101010101, and pattern 2 is 00000101010101010), the first indication information can be 1 bit. When the bit value is 0, it can represent pattern 1. Further, the receiving device can determine that the pattern is 00000010101010101, and determine that the second bit set includes the sixth bit, eighth bit, tenth bit, twelfth bit, fourteenth bit, and sixteenth bit of the first field; when the bit value is 1, it can represent pattern 2. Further, the receiving device can determine that the pattern is 00000101010101010, and determine that the second bit set includes the fifth bit, seventh bit, ninth bit, eleventh bit, thirteenth bit, and fifteenth bit of the first field. Alternatively, when the bit value is 1, it can represent pattern 1, and further, the receiving device can determine that the pattern is 00000010101010101, and determine that the second bit set includes the sixth bit, eighth bit, tenth bit, twelfth bit, fourteenth bit, and sixteenth bit of the first field; when the bit value is 0, it can represent pattern 2, and further, the receiving device can determine that the pattern is 00000101010101010, and determine that the second bit set includes the fifth bit, seventh bit, ninth bit, eleventh bit, thirteenth bit, and fifteenth bit of the first field.

[0222] In another example, taking the first indication information as a bit map as an example, when the bit map is 00000010101010101, the receiving device can determine that the second bit set includes the sixth bit, eighth bit, tenth bit, twelfth bit, fourteenth bit, and sixteenth bit of the first field; when the bit map is 00000101010101010, the receiving device can determine that the second bit set includes the fifth bit, seventh bit, ninth bit, eleventh bit, thirteenth bit, and fifteenth bit of the first field.

[0223] In the above two examples, the starting bit of the first field is the zeroth bit (ie, bit [0]), and the patterns both include the first check bit.

[0224] For the six bits in the second bit set determined above, the positions of all bits in the second bit set in the first field may be explicitly indicated.

[0225] Based on the signal transmission method shown in FIG8 , different from the first field including the first check bit and the second check bit, the present application further proposes a signal transmission method in which the first field includes the first check bit, the second check bit, and the third check bit, which can further improve the transmission robustness of the first field and improve the communication performance. The specific steps can be shown in FIG9 below:

[0226] S901: The sending device obtains a first field.

[0227] The first field includes a first check bit, a second check bit, and a third check bit.

[0228] The first check bit and the second check bit may refer to the description of the first bit and the second bit in S801, which will not be repeated here.

[0229] Among them, the third check bit is carried in a subfield with a fixed bit value in the first field. For example, the bit value of the rate information subfield in the L-SIG field (i.e., 1101) is fixed, and the third check bit can be carried in the rate information subfield in the L-SIG field.

[0230] It can be understood that the third check bit may be one or more bits in the rate information subfield, or may be all bits in the rate information subfield.

[0231] For example, the third check bit may be the first four bits of the L-SIG field (i.e., the rate information subfield), or the third check bit may be any three bits in the rate information subfield, or the third check bit may be any two bits in the rate information subfield, or the third check bit may be any one bit in the rate information subfield.

[0232] It can be understood that when the third check bit is the first four bits of the L-SIG field, the L-SIG field does not include the rate information subfield; when the third check bit is at most three bits of the first four bits of the L-SIG field, the L-SIG field may include the rate information subfield, and the rate information subfield at this time may occupy bits of the first four bits other than the third check bit.

[0233] The above method for determining the third parity bit can provide a selectable range for determining the third parity bit in the L-SIG field, thereby increasing the diversity of the third parity bit design and improving the flexibility of determining the third bit.

[0234] For ease of understanding, this application is explained using an example in which the third check bit is four bits.

[0235] The first check bit, the second check bit, and the third check bit are check bits of all bits in the first bit set except the first check bit and the third check bit.

[0236] The first bit set may refer to the description of the first bit set in S801 above, which will not be described in detail here.

[0237] Optionally, the bit values ​​of the first check bit, the second check bit, and the third check bit can be determined by a CRC polynomial, that is, the CRC polynomial corresponding to the first check bit, the second check bit, and the third check bit (which can be called a third CRC polynomial) can satisfy the following formula: p(x)=0x67=1+x+x 2 +x 5 +x 6 .

[0238] Exemplarily, the bit values ​​of all bits in the first bit set except the first check bit and the third check bit can be divided by the third CRC polynomial, and the remainder obtained is the bit value of the first check bit, the second check bit, and the third check bit.

[0239] Among them, the first four bit values ​​of the remainder correspond to the bit value of the third check bit, the fifth bit value of the remainder (that is, the starting bit value of the remainder is the first bit value) corresponds to the bit value of the first check bit, and the last bit value of the remainder corresponds to the bit value of the second check bit.

[0240] For example, when the above remainder is 000000, the bit value of the third check bit can be 0000, the bit value of the first check bit can be 0, and the bit value of the second check bit can be 0; or, when the above remainder is 100000, the bit value of the third check bit can be 1000, the bit value of the first check bit can be 0, and the bit value of the second check bit can be 0; or, when the above remainder is 010001, the bit value of the third check bit can be 0100, the bit value of the first check bit can be 0, and the bit value of the second check bit can be 1; when the above remainder is 010110, the bit value of the third check bit can be 0101, the bit value of the first check bit can be 1, and the bit value of the second check bit can be 0.

[0241] It can be understood that the bit values ​​of the first check bit, the second check bit, and the third check bit can be determined by the third CRC polynomial, and then the receiving device can determine whether the transmission of the first field is accurate through the bit values ​​of the first check bit, the second check bit, and the third check bit, so as to improve the transmission robustness of the first field.

[0242] S902: The transmitting device sends the encoded first field to the receiving device; correspondingly, the receiving device receives the information to be decoded from the transmitting device.

[0243] Among them, S902 can refer to the above description of S802 and will not be repeated here.

[0244] S903: The receiving end device verifies the information to be decoded according to the first check bit, the second check bit, and the third check bit to obtain the decoded first field.

[0245] The receiving device may decode the information to be decoded according to a decoding algorithm.

[0246] Among them, the receiving device can divide the bit value of all bits in the first bit set except the first check bit and the second check bit by the bit value of the third check bit, the first check bit, and the second check bit. If the remainder is 0, it indicates that the first field is transmitted correctly; otherwise, it indicates that the first field is transmitted incorrectly.

[0247] It is understandable that if the receiving device determines that the first field is transmitted erroneously, it may notify the transmitting device to retransmit the first field or perform error correction on the first field to improve the transmission robustness of the first field.

[0248] The receiving end device decodes the information to be decoded according to the decoding algorithm, which can be referred to the description of S803 above and will not be repeated here.

[0249] Based on the signal transmission method shown in Figure 9 above, different from the first field including the second check bit, and the second check bit is the check bit of all bits in the first bit set, in the present application, the first field may also include the first check bit and the third check bit on the basis of including the second check bit, so that the first check bit, the second check bit, and the third check bit can be the check bits of all bits in the first bit set except the first check bit and the third check bit. The transmission robustness of the first field can be improved as much as possible without changing the transmission method of the first field, thereby improving the communication performance.

[0250] Based on the signal transmission method shown in Figures 8 and 9 above, taking the first field as the L-SIG field as an example, the present application performs the following several possible simulations and describes the above technical effects in detail based on the simulation results.

[0251] In a first possible simulation, the decoding performance corresponding to different decoding algorithms can be determined, as shown in Figure 10 below. The horizontal axis represents SNR (dB), and the vertical axis represents the frame erase ratio (FER) (i.e., when the error detection function of the receiving device indicates that there is a misalignment in a frame, the frame is defined as erased, and the FER is defined as the ratio of the number of erased frames to the total number of received frames). In this simulation, the second parity bit is the parity subfield of the L-SIG field (i.e., the second parity bit can perform parity check on the first 17 bits of the L-SIG field). The L-SIG field includes a reserved subfield and a rate information subfield, and is decoded using different decoding algorithms.

[0252] W0 represents the decoding performance curve of the Viterbi decoding algorithm. The parameter Maxweak of the Viterbi decoding algorithm is set to 0 (i.e., the second check bit is not used for check during the decoding process). At the same time, the Viterbi decoding algorithm does not use the five fixed bits of prior information of the rate information subfield and the reserved subfield.

[0253] Among them, W1 represents the decoding performance curve of decoding by the convolutional code SISIO decoding algorithm, and the parameter Maxweak of the convolutional code SISO decoding algorithm is set to 0 (that is, the second check bit is not used for verification during the decoding process), but the convolutional code SISO decoding algorithm uses the rate information subfield and the reserved subfield, which are a total of 5 fixed bits of prior information.

[0254] W2 represents the decoding performance curve for decoding using the convolutional code list decoding algorithm. The parameter Maxweak of the convolutional code list decoding algorithm is set to 1 (i.e., the second check bit is used for check during the decoding process). However, the convolutional code list decoding algorithm does not use the five fixed bits of prior information of the rate information subfield and the reserved subfield.

[0255] Among them, W3 represents the decoding performance curve of decoding using the convolutional code list decoding algorithm. Different from W2, the convolutional code list decoding algorithm corresponding to W3 uses a priori information of 5 fixed bits, namely the rate information subfield and the reserved subfield.

[0256] It is understandable that when the FER is determined, the SNR of W0 is the smallest and the SNR of W3 is the largest. For example, when FER=10 -3When W3 is used as the decoder, the SNR of W3 is approximately 0.35 dB higher than that of W0, and the SNR of W2 is approximately 0.15 dB higher than that of W0. That is, the decoding algorithm corresponding to W3 (i.e., the decoding algorithm that uses the second parity bit for verification and utilizes the prior information of the fixed information bits) can achieve a performance gain of approximately 0.35 dB compared to the decoding algorithm corresponding to W0 (i.e., the decoding algorithm that does not use the second parity bit for verification and does not utilize the prior information of the fixed information bits), while the decoding algorithm corresponding to W1 (i.e., the decoding algorithm that does not use the second parity bit for verification but utilizes the prior information of the fixed information bits) can achieve a performance gain of approximately 0.15 dB compared to the decoding algorithm corresponding to W0 (i.e., the decoding algorithm that does not use the second parity bit for verification and does not utilize the prior information of the fixed information bits).

[0257] In addition, when decoding is performed using the convolutional code list decoding algorithm, the SNR is larger, that is, the decoding performance is better.

[0258] In a second possible simulation, the decoding performance corresponding to different decoding algorithms and different decoding algorithm parameters can be determined, as shown in Figure 11 below, where the horizontal axis is SNR and the vertical axis is FER. In this simulation, the second check bit is the check subfield of the L-SIG field.

[0259] Among them, W0, W1, W2, and W3 are consistent with W0, W1, W2, and W3 in the first possible simulation described above.

[0260] Among them, W4-1 and W4-2 represent the decoding performance curves of decoding using the convolutional code list decoding algorithm. The parameter Maxweak of the convolutional code list decoding algorithm is set to 2 (that is, the first check bit (the first check bit is the reserved subfield of the L-SIG field) and the second check bit are used for verification during the decoding process, and all bits in the second bit set are any six bits in the first bit set. At this time, the L-SIG field still includes the rate information subfield). The convolutional code list decoding algorithm corresponding to W4-1 does not use the prior information of the four fixed bits of the rate information subfield. The convolutional code list decoding algorithm corresponding to W4-2 uses the prior information of the four fixed bits of the rate information subfield.

[0261] Among them, W5 represents the decoding performance curve of decoding by the convolutional code list decoding algorithm, and the parameter Maxweak of the convolutional code list decoding algorithm is set to 6 (that is, the first check bit (the first check bit is the reserved subfield of the L-SIG field), the second check bit, and the third check bit (the third check bit is the rate information subfield of the L-SIG field) are used for verification during the decoding process).

[0262] It is understandable that when the FER is determined, the SNR of W0 is the smallest and the SNR of W5 is the largest. For example, when FER=10-3 When , the SNR of W5 is about 1.2dB higher than that of W0, and the SNR of W4-2 is about 0.9dB higher than that of W0. That is, the decoding algorithm corresponding to W5 (that is, the convolutional code list decoding algorithm with the parameter Maxweak set to 6) can obtain a performance gain of about 1.2dB compared with the decoding algorithm corresponding to W0 (that is, the decoding algorithm that does not use the second check bit for verification and does not use the prior information of the fixed information bit); the decoding algorithm corresponding to W4-2 (that is, the list decoding algorithm with the parameter Maxweak set to 2 and using the prior information of the fixed information bit) can obtain a performance gain of about 0.9dB compared with W0 (that is, the decoding algorithm that does not use the second check bit for verification and does not use the prior information of the fixed information bit).

[0263] In addition, the decoding performance corresponding to the verification method proposed in this application (i.e., the decoding performance corresponding to W4-1, W4-2, and W5) is better than the decoding performance corresponding to W0, W1, W2, and W3. At the same time, the decoding performance of W4-2 is close to the decoding performance of W5.

[0264] In a third possible simulation, the corresponding decoding performance can be determined when the first parity bit is the parity bit of all bits in different second bit sets. As shown in Figure 12 below, the horizontal axis represents the number of tests and the vertical axis represents the FER. In this simulation, the signal-to-noise ratio is fixed at 2.5dB, the first parity bit is the reserved subfield of the L-SIG field, the second parity bit is the parity subfield of the L-SIG field, and decoding is performed using the convolutional list decoding algorithm (i.e., using the four fixed bits of prior information of the rate information subfield in the L-SIG field). Four error patterns are tested during the convolutional code list decoding process.

[0265] Among them, the first check bit is any two bits (that is, the number in the solid box is 2), four bits (that is, the number in the solid box is 4), six bits (that is, the number in the solid box is 6), eight bits (that is, the number in the solid box is 8), or ten bits (that is, the number in the solid box is 10) of all the bits in the first bit set except the first check bit, or the first check bit is any six bits (that is, the number in the dotted box is 6), eight bits (that is, the number in the dotted box is 8), or ten bits (that is, the number in the dotted box is 10) of all the bits in the first bit set located after the first check bit.

[0266] As can be seen from FIG12 , when the first parity bit is any six, eight, or ten parity bits among all the bits following the first parity bit in the first bit set, the FER is small, that is, the decoding performance is better. In addition, when the first parity bit is any six parity bits among all the bits following the first parity bit in the first bit set, the FER is minimum, that is, the decoding performance is optimal.

[0267] In a fourth possible simulation, the decoding performance corresponding to different decoding algorithms and different decoding algorithm parameters can be determined, as shown in Figure 13 below, with the horizontal axis showing SNR and the vertical axis showing FER. In this simulation, the second parity bit is the parity subfield of the L-SIG field.

[0268] Among them, W0, W1, W2, and W3 are consistent with W0, W1, W2, and W3 in the first possible simulation described above.

[0269] Among them, W4-1 and W4-2 are consistent with W4-1 and W4-2 in the above second possible simulation.

[0270] Among them, W4-3 represents the decoding performance curve of decoding using the convolutional code list decoding algorithm. The parameter Maxweak of the convolutional code list decoding algorithm is set to 2 (i.e., during the decoding process, the first parity bit (the first parity bit is the parity subfield of the L-SIG field) and the second parity bit are used for parity, and the second bit set includes the seventh bit, the ninth bit, the eleventh bit, the thirteenth bit, the fifteenth bit, and the seventeenth bit of the first field. At this time, the L-SIG field still includes the rate information subfield), and the convolutional code list decoding algorithm uses the four fixed bits of prior information of the rate information subfield.

[0271] As can be seen from FIG13 , when the SNR is fixed, the FER corresponding to W4-3 is the smallest, that is, the decoding performance is optimal.

[0272] It can be understood that compared with the decoding performance corresponding to W0, W1, W2, W3, W4-1, or W4-2, the decoding performance is optimal when the total number of bits in the second bit set is 6 and the second bit set includes the seventh bit, ninth bit, eleventh bit, thirteenth bit, fifteenth bit, and seventeenth bit of the first field.

[0273] In a fifth possible simulation, the decoding performance corresponding to different decoding algorithms and parameters can be determined, as shown in Figure 14 below, where the horizontal axis is SNR and the vertical axis is FER. In this simulation, the second parity bit is the parity subfield of the L-SIG field.

[0274] Among them, W0, W1, W2, and W3 are consistent with W0, W1, W2, and W3 in the first possible simulation described above.

[0275] Among them, W4-1 and W4-2 are consistent with W4-1 and W4-2 in the above second possible simulation.

[0276] Among them, W4-4 is different from W4-3 in the fourth possible simulation only in that all the bits in the second bit set are different, that is, the second bit set includes the sixth bit, eighth bit, tenth bit, twelfth bit, fourteenth bit, and sixteenth bit of the first field.

[0277] As can be seen from FIG14 , when the SNR is fixed, the FER corresponding to W4-4 is the smallest, that is, the decoding performance is optimal.

[0278] It can be understood that compared with the decoding performance corresponding to W0, W1, W2, W3, W4-1, or W4-2, the decoding performance is optimal when the total number of bits in the second bit set is 6 and the second bit set includes the seventh bit, ninth bit, eleventh bit, thirteenth bit, fifteenth bit, and seventeenth bit of the first field.

[0279] It should be noted that the various embodiments of this application can be implemented independently or in combination, without limitation. Unless otherwise specified or there is a logical conflict, the terms and / or descriptions of the different embodiments provided in this application are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0280] It is understood that in the embodiments of the present application, the execution subject may perform some or all of the steps in the embodiments of the present application. These steps or operations are merely examples, and the embodiments of the present application may also perform other operations or variations of various operations. In addition, the various steps may be performed in a different order than those presented in the embodiments of the present application, and it is possible that not all operations in the embodiments of the present application need to be performed.

[0281] The above mainly introduces the solutions provided by this application from the perspective of interaction between various devices. Accordingly, this application also provides a communication device, which is used to implement the various methods described above. The communication device can be the sending end device in the above method embodiments, or a device including the above sending end device, or a component that can be used for the sending end device; alternatively, the communication device can be the sending end device involved in the above method embodiments, or a device including the sending end device, or a component that can be used for the sending end device.

[0282] It is understandable that, in order to realize the above functions, the communication device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0283] The embodiment of the present application can divide the functional modules of the communication device according to the above method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. In actual implementation, there may be other division methods.

[0284] In one implementation scenario, taking the communication device as the transmitting end device in the above method embodiment as an example, FIG15 shows a schematic structural diagram of a transmitting end device 150. The transmitting end device 150 includes a processing module 1501 and a transceiver module 1502.

[0285] In some embodiments, the transmitting device 150 may further include a storage module (not shown in FIG. 15 ) for storing program instructions and data.

[0286] In some embodiments, the transceiver module 1502, which may also be referred to as a transceiver unit, is configured to implement a transmitting and / or receiving function. The transceiver module 1502 may be composed of a transceiver circuit, a transceiver, a transceiver, or a communication interface.

[0287] In some embodiments, the transceiver module 1502 may include a receiving module and a sending module, which are respectively used to execute the receiving and sending steps performed by the sending end device in the above method embodiments, and / or used to support other processes of the technology described in this document; the processing module 1501 may be used to execute the processing steps (such as determination, generation, etc.) performed by the sending end device in the above method embodiments, and / or used to support other processes of the technology described in this document.

[0288] An exemplary processing module 1501 is used to obtain a first field; wherein the first field includes a first check bit and a second check bit; the first check bit is a check bit of multiple bits in the first bit set except the first check bit, and the second check bit is a check bit of all bits in the first bit set; or, the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; the first bit set includes all bits in the first field that are located before the second check bit; the transceiver module 1502 is used to send the encoded first field to the receiving device.

[0289] Another exemplary embodiment, the processing module 1501 is used to obtain the first field; wherein the first field includes a first check bit, a second check bit, and a third check bit; the first check bit, the second check bit, and the third check bit are check bits of all bits in the first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit; the transceiver module 1502 is used to send the encoded first field to the receiving device.

[0290] In this application, the transmitting device 150 is presented in the form of various functional modules divided in an integrated manner. The "module" here can refer to a specific application-specific integrated circuit (ASIC), a circuit, a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions.

[0291] In some embodiments, in terms of hardware implementation, those skilled in the art may conceive that the transmitting device 150 may take the form of the communication apparatus 70 shown in FIG. 7 .

[0292] As an example, the functions / implementation process of the processing module 1501 in FIG15 can be implemented by the processor 701 in the communication device 70 shown in FIG7 calling the computer-executable instructions stored in the memory 703. The functions / implementation process of the transceiver module 1502 in FIG15 can be implemented by the communication interface 704 in the communication device 70 shown in FIG7.

[0293] In some embodiments, when the transmitting device 150 in Figure 15 is a chip or a chip system, the function / implementation process of the transceiver module 1502 can be implemented through the input and output interface (or communication interface) of the chip or chip system, and the function / implementation process of the processing module 1501 can be implemented through the processor (or processing circuit) of the chip or chip system.

[0294] Since the transmitting device 150 provided in this embodiment can execute the above method, the technical effects that can be obtained can refer to the above method embodiments and will not be repeated here.

[0295] In another implementation scenario, taking the communication device as the receiving end device in the above method embodiment as an example, FIG16 shows a schematic structural diagram of a receiving end device 160. The receiving end device 160 includes a processing module 1601 and a transceiver module 1602.

[0296] In some embodiments, the receiving device 160 may further include a storage module (not shown in FIG. 16 ) for storing program instructions and data.

[0297] In some embodiments, the transceiver module 1602, which may also be referred to as a transceiver unit, is configured to implement a transmitting and / or receiving function. The transceiver module 1602 may be composed of a transceiver circuit, a transceiver, a transceiver, or a communication interface.

[0298] In some embodiments, the transceiver module 1602 may include a receiving module and a sending module, which are respectively used to execute the receiving and sending steps performed by the receiving device in the above method embodiments, and / or used to support other processes of the technology described in this document; the processing module 1601 may be used to execute the processing steps (such as determination, generation, etc.) performed by the receiving device in the above method embodiments, and / or used to support other processes of the technology described in this document.

[0299] An exemplary transceiver module 1602 is used to receive information to be decoded from a sending end device; wherein the information to be decoded includes a first check bit and a second check bit; the first check bit is a check bit of multiple bits in a first bit set except the first check bit, and the second check bit is a check bit of all bits in the first bit set; or, the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; the first bit set includes all bits in the first field that are located before the second check bit; the processing module 1601 is used to verify the information to be decoded based on the first check bit and the second check bit to obtain the decoded first field.

[0300] Another exemplary embodiment is a transceiver module 1602, which is used to receive information to be decoded from a transmitting device; wherein the information to be decoded includes a first check bit, a second check bit, and a third check bit; the first check bit, the second check bit, and the third check bit are check bits of all bits in the first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit; the processing module 1601 is used to verify the information to be decoded based on the first check bit, the second check bit, and the third check bit to obtain the decoded first field.

[0301] In this application, the receiving device 160 is presented in the form of various functional modules divided in an integrated manner. The "module" here can refer to a specific application-specific integrated circuit (ASIC), a circuit, a processor and memory that executes one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions.

[0302] In some embodiments, in terms of hardware implementation, those skilled in the art may conceive that the receiving device 160 may take the form of the communication device 70 shown in FIG. 7 .

[0303] As an example, the functions / implementation process of the processing module 1601 in FIG16 can be implemented by the processor 701 in the communication device 70 shown in FIG7 calling the computer-executable instructions stored in the memory 703. The functions / implementation process of the transceiver module 1602 in FIG16 can be implemented by the communication interface 704 in the communication device 70 shown in FIG7.

[0304] In some embodiments, when the receiving device 160 in Figure 16 is a chip or a chip system, the function / implementation process of the transceiver module 1602 can be implemented through the input and output interface (or communication interface) of the chip or chip system, and the function / implementation process of the processing module 1601 can be implemented through the processor (or processing circuit) of the chip or chip system.

[0305] Since the receiving device 160 provided in this embodiment can execute the above method, the technical effects that can be obtained can refer to the above method embodiments and will not be repeated here.

[0306] As a possible product form, the transmitting device or receiving device described in the embodiments of the present application can also be implemented using the following: one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gate logic, discrete hardware components, any other suitable circuits, or any combination of circuits that can perform the various functions described throughout this application.

[0307] As another possible product form, the transmitting device or receiving device described in the embodiment of the present application can be implemented by a general bus architecture. For ease of explanation, refer to Figure 17, which is a structural diagram of a communication device 170 provided in an embodiment of the present application. The communication device 170 includes a processor 1701 and a transceiver 1702. The communication device 170 can be a transmitting device, or a chip or module therein; or, the communication device 170 can be a receiving device, or a chip or module therein. Figure 17 only shows the main components of the communication device 170. In addition to the processor 1701 and the transceiver 1702, the communication device may further include a memory 1703.

[0308] Optionally, processor 1701 is primarily used to process communication protocols and communication data, as well as control the entire communication device, execute software programs, and process software program data. Memory 1703 is primarily used to store software programs and data. Transceiver 1702 may include a transmitting module, a receiving module, a radio frequency circuit, and an antenna. The transmitting module is primarily used to transmit baseband signals, the receiving module is primarily used to receive baseband signals, and the radio frequency circuit is primarily used to convert baseband signals into radio frequency signals and process radio frequency signals. The antenna is primarily used to transmit and receive radio frequency signals in the form of electromagnetic waves.

[0309] Optionally, the processor 1701 , the transceiver 1702 , and the memory 1703 may be connected via a communication bus.

[0310] When the communication device is turned on, the processor 1701 can read the software program in the memory 1703, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be sent wirelessly, the processor 1701 performs baseband processing on the data to be sent, outputs the baseband signal to the sending module, and then outputs it to the radio frequency circuit through the sending module. The radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal to the outside in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the receiving module. The receiving module outputs it to the processor 1701, and the processor 1701 converts the baseband signal into data and processes the data.

[0311] In another implementation, the RF circuit and antenna may be provided independently of the processor performing baseband processing. For example, in a distributed scenario, the RF circuit and antenna may be remotely arranged independent of the communication device.

[0312] In some embodiments, the present application also provides a communication device, which includes a processor, configured to implement the method in any of the above method embodiments. The communication device may be a transmitting device or a receiving device in the above method embodiments.

[0313] As a possible implementation, the communication device further includes a memory. The memory is used to store necessary computer programs and data. The computer program may include instructions, and the processor may invoke the instructions in the computer program stored in the memory to instruct the communication device to execute any of the above-described method embodiments. Of course, the memory may not be located in the communication device.

[0314] As another possible implementation, the communication device also includes an interface circuit, which is a code / data read / write interface circuit, and the interface circuit is used to receive computer execution instructions (computer execution instructions are stored in a memory, may be read directly from the memory, or may pass through other devices) and transmit them to the processor.

[0315] As another possible implementation, the communication device further includes a communication interface, where the communication interface is used to communicate with a module outside the communication device.

[0316] It can be understood that the communication device can be a chip or a chip system. When the communication device is a chip system, it can be composed of chips or include chips and other discrete devices. The embodiments of the present application do not specifically limit this.

[0317] The present application also provides a computer-readable storage medium having a computer program or instruction stored thereon, which implements the functions of any of the above method embodiments when executed by a computer.

[0318] The present application also provides a computer program product, which implements the functions of any of the above method embodiments when executed by a computer.

[0319] Those skilled in the art will appreciate that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and units may refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0320] It is understood that the systems, devices, and methods described in this application may also be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be through some interface, indirect coupling or communication connection of devices or units, and may be electrical, mechanical, or other forms.

[0321] The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Components shown as units may or may not be physical units. Some or all of these units may be selected to achieve the objectives of this embodiment as needed.

[0322] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0323] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes (or functions) described in the embodiments of the present application are implemented. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state drive (SSD)). In the embodiment of the present application, the computer may include the aforementioned device.

[0324] Although the present application is described herein with reference to various embodiments, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims in the process of implementing the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may implement several functions listed in the claims.

Claims

1. A signal transmission method, characterized in that: include: Obtain a first field; wherein the first field includes a first check bit and a second check bit; The first parity bit is a parity bit of a plurality of bits in a first bit set excluding the first parity bit, and the second parity bit is a parity bit of all bits in the first bit set; or, The first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; The first bit set includes all bits in the first field that are located before the second check bit; The encoded first field is sent to a receiving device.

2. A signal transmission method, characterized in that: include: Receiving information to be decoded from a transmitting end device; wherein the information to be decoded includes a first check bit and a second check bit; The first parity bit is a parity bit of a plurality of bits in a first bit set excluding the first parity bit, and the second parity bit is a parity bit of all bits in the first bit set; or, The first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit; The first bit set includes all bits in the first field that are located before the second check bit; The information to be decoded is verified according to the first check bit and the second check bit to obtain a decoded first field.

3. The method according to claim 1 or 2, characterized in that The multiple bits in the first bit set excluding the first check bit include multiple bits in the first bit set located after the first check bit.

4. The method according to any one of claims 1 to 3, characterized in that The number of the multiple bits is any one of the following: 2, 3, 4, 5, 6, 7, 8, 9, or 10.

5. The method according to any one of claims 1 to 4, characterized in that The plurality of bits include the seventh bit, the ninth bit, the eleventh bit, the thirteenth bit, the fifteenth bit, and the seventeenth bit of the first field; or, The plurality of bits include a sixth bit, an eighth bit, a tenth bit, a twelfth bit, a fourteenth bit, and a sixteenth bit of the first field.

6. The method according to any one of claims 1 to 5, characterized in that When the first check bit and the second check bit are check bits of all bits in the first bit set except the first check bit, The polynomials of the cyclic redundancy check CRC corresponding to the first check bit and the second check bit satisfy the following formula: p(x)=0x7=1+x+x^2.

7. The method according to any one of claims 1 to 6, characterized in that The first field is a legacy signal L-SIG field.

8. A signal transmission method, characterized in that: include: Obtain a first field; wherein the first field includes a first check bit, a second check bit, and a third check bit; The first check bit, the second check bit, and the third check bit are check bits of all bits in a first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit; The encoded first field is sent to a receiving device.

9. A signal transmission method, characterized in that: include: Receiving information to be decoded from a transmitting end device; wherein the information to be decoded includes a first check bit, a second check bit, and a third check bit; The first check bit, the second check bit, and the third check bit are check bits of all bits in a first bit set except the first check bit and the third check bit; the first bit set includes all bits in the first field that are located before the second check bit; The information to be decoded is verified according to the first check bit, the second check bit, and the third check bit to obtain a decoded first field.

10. The method according to claim 8 or 9, characterized in that The polynomials of the cyclic redundancy check CRC corresponding to the first check bit, the second check bit, and the third check bit satisfy the following formula: p(x)=0x67=1+x+x^2+x^5+x^6.

11. The method according to any one of claims 8 to 10, characterized in that: The first field is a legacy signal L-SIG field.

12. The method according to any one of claims 8 to 11, characterized in that When the first field is an L-SIG field, the third check bit is one or more bits of a rate information subfield in the L-SIG field.

13. The method according to any one of claims 1 to 12, characterized in that When the first field is an L-SIG field, the first check bit is the fifth bit of the L-SIG field.

14. The method according to any one of claims 1 to 13, characterized in that When the first field is an L-SIG field, the second check bit is the eighteenth bit of the L-SIG field.

15. A communication device, characterized in that: include: a processing module, configured to obtain a first field; wherein the first field includes a first parity bit and a second parity bit; the first parity bit is a parity bit of a plurality of bits in a first bit set excluding the first parity bit, and the second parity bit is a parity bit of all bits in the first bit set; or, the first parity bit and the second parity bit are parity bits of all bits in the first bit set excluding the first parity bit; and the first bit set includes all bits in the first field that are located before the second parity bit; The transceiver module is used to send the encoded first field to a receiving device.

16. A communication device, characterized in that: include: a transceiver module, configured to receive information to be decoded from a transmitting end device; wherein the information to be decoded includes a first parity bit and a second parity bit; the first parity bit is a parity bit of multiple bits in a first bit set excluding the first parity bit, and the second parity bit is a parity bit of all bits in the first bit set; or, the first parity bit and the second parity bit are parity bits of all bits in the first bit set excluding the first parity bit; and the first bit set includes all bits in the first field that are located before the second parity bit; A processing module is configured to verify the information to be decoded according to the first check bit and the second check bit to obtain a decoded first field.

17. A communication device, characterized in that: include: a processing module, configured to obtain a first field; wherein the first field includes a first parity bit, a second parity bit, and a third parity bit; the first parity bit, the second parity bit, and the third parity bit are parity bits of all bits in a first bit set except the first parity bit and the third parity bit; and the first bit set includes all bits in the first field that are located before the second parity bit; The transceiver module is used to send the encoded first field to a receiving device.

18. A communication device, characterized in that: include: a transceiver module, configured to receive information to be decoded from a transmitting device; wherein the information to be decoded includes a first check bit, a second check bit, and a third check bit; the first check bit, the second check bit, and the third check bit are check bits of all bits in a first bit set except the first check bit and the third check bit; and the first bit set includes all bits in the first field that are located before the second check bit; The processing module is configured to verify the information to be decoded according to the first check bit, the second check bit, and the third check bit to obtain a decoded first field.

19. A communication device, characterized in that: The communication device includes a processor; the processor is used to run a computer program or instruction, or to use a logic circuit to enable the communication device to perform the signal transmission method as described in any one of claims 1, 3-7, 13-14, or to enable the communication device to perform the signal transmission method as described in any one of claims 2-7, 13-14, or to enable the communication device to perform the signal transmission method as described in any one of claims 8, 10-14, or to enable the communication device to perform the signal transmission method as described in any one of claims 9-14.

20. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions or programs. When the computer instructions or programs are run on a computer, the signal transmission method as described in any one of claims 1, 3-7, 13-14 is executed, or the signal transmission method as described in any one of claims 2-7, 13-14 is executed, or the signal transmission method as described in any one of claims 8, 10-14 is executed, or the signal transmission method as described in any one of claims 9-14 is executed.

21. A computer program product, characterized in that The computer program product includes computer instructions; when part or all of the computer instructions are executed, the signal transmission method as described in any one of claims 1, 3-7, 13-14 is executed, or the signal transmission method as described in any one of claims 2-7, 13-14 is executed, or the signal transmission method as described in any one of claims 8, 10-14 is executed, or the signal transmission method as described in any one of claims 9-14 is executed.

22. A chip, characterized in that: include: a memory for storing computer program instructions; A processor, configured to execute the computer program instructions so that the communication device including the chip performs the signal transmission method described in any one of claims 1, 3-7, 13-14, or so that the communication device including the chip performs the signal transmission method described in any one of claims 2-7, or so that the communication device including the chip performs the signal transmission method described in any one of claims 8, 10-14, or so that the communication device including the chip performs the signal transmission method described in any one of claims 9-14.

23. A communication system, characterized in that: The communication system includes a transmitting device and a receiving device; wherein the transmitting device is used to execute the signal transmission method as described in any one of claims 1, 3-7, 13-14, and the receiving device is used to execute the signal transmission method as described in any one of claims 2-7; or, the transmitting device is used to execute the signal transmission method as described in any one of claims 8, 10-14, and the receiving device is used to execute the signal transmission method as described in any one of claims 9-14.

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