Compiling method and apparatus, device, storage medium, and program product

Abstract

A compiling method and apparatus, a device, a storage medium, and a program product. The compiling method comprises: unrolling an instruction sequence in a loop BB to generate multiple BBs and multiple DAGs corresponding to the multiple BBs, wherein the multiple BBs comprise an instruction sequence unrolled at least three times, and the multiple DAGs are used for indicating a data dependency relationship between instructions in the multiple BBs (810); performing window scheduling on the basis of the multiple BBs, and determining a target scheduling window and a scheduling result corresponding to the target scheduling window, wherein the window scheduling is used for dividing the instruction sequence in the loop BB into two parts on the basis of the scheduling window, such that the instruction sequence of the second part in a current loop and the instruction sequence of the first part in the next loop are synchronously executed, the target scheduling window is a scheduling window of which the execution time satisfies a time condition, and the execution time is the time required for executing instructions in the window and calculated on the basis of the data dependency relationship in the multiple DAGs (820); and on the basis of the scheduling result corresponding to the target scheduling window, performing compiling to obtain a target code of the loop BB in a target program (830).

Description

Compilation method, device, equipment, storage medium and program product

[0001] Related applications

[0002] This application claims priority to Chinese patent application number 2024102347547, filed on February 29, 2024, entitled “Compilation Method, Apparatus, Device and Storage Medium,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of compilers, and in particular to a compilation method, a compilation device, a computer device, a computer-readable storage medium, and a computer program product. Background Art

[0004] In recent years, the rapid development of artificial intelligence (AI) has brought revolutionary technological changes to many fields, such as natural language processing, computer vision, e-commerce, smart cities, and drug research and development.

[0005] To build a complete application ecosystem, it is necessary to design and develop a supporting AI toolchain, of which the AI ​​compiler is a key component. The AI ​​compiler compiles the AI ​​model's algorithm into executable machine code, generating a target program that can run on the AI ​​chip based on the AI ​​model's program.

[0006] However, the basic computing unit operators of AI models contain a large number of loop instruction structures, which consume a large portion of the AI ​​chip's execution time. To reduce the execution time of loop instruction structures, soft pipelining optimization was introduced to optimize the compilation algorithm for loop instruction structures. Summary of the Invention

[0007] The present application provides a compilation method, a compilation apparatus, a computer device, a computer-readable storage medium, and a computer program product.

[0008] In one aspect, the present application provides a compilation method, which is executed by a computer device, and the method includes:

[0009] Loop-unrolling an instruction sequence in a loop BB (Basic Block) to generate a multiple BB and a multiple DAG (Directed Acyclic Graph) corresponding to the multiple BB; the multiple BB includes the instruction sequence looped at least three times, and the multiple DAG is used to indicate data dependencies between instructions in the multiple BB;

[0010] Window scheduling is performed based on the multiple BBs, and a target scheduling window and a scheduling result corresponding to the target scheduling window are determined; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required to execute the instructions in the window calculated based on the data dependency relationship in the multiple DAGs; and

[0011] According to the scheduling result corresponding to the target scheduling window, the target code of the loop BB in the target program is compiled.

[0012] In another aspect, a compilation device is provided, the device comprising:

[0013] a loop module, configured to loop-unroll an instruction sequence in a loop basic block (BB) to generate a multiple BB and a multiple directed acyclic graph (DAG) corresponding to the multiple BB; the multiple BB includes the instruction sequence looped at least three times, and the multiple DAG indicates data dependencies between instructions in the multiple BB;

[0014] a scheduling module configured to perform window scheduling based on the multiple BBs, determine a target scheduling window, and determine a scheduling result corresponding to the target scheduling window; the window scheduling is configured to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time satisfies a time condition, and the execution time is the time required to execute instructions within the window, calculated based on data dependencies in the multiple DAGs; and

[0015] The compiling module is used to compile the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0016] On the other hand, a computer device is provided. The computer device includes: a processor and a memory. The memory stores a computer program. The computer program is loaded and executed by the processor to implement the above compilation method.

[0017] On the other hand, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the above compilation method.

[0018] In another aspect, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the above-described compilation method. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the disclosed drawings without any creative work.

[0020] FIG1 is a schematic diagram of a processing procedure of an AI compiler provided in one embodiment of the present application;

[0021] FIG2 is a schematic diagram of pseudo code of a table scheduling algorithm provided by one embodiment of the present application;

[0022] FIG3 is a schematic diagram of a modular scheduling algorithm provided by one embodiment of the present application;

[0023] FIG4 is a flow chart of a modular scheduling algorithm provided by one embodiment of the present application;

[0024] FIG5 is a schematic diagram of a window scheduling algorithm provided by an embodiment of the present application;

[0025] FIG6 is a schematic diagram of a window scheduling algorithm provided by an embodiment of the present application;

[0026] FIG7 is a schematic diagram of a terminal device provided by an embodiment of the present application;

[0027] FIG8 is a flowchart of a compilation method provided by an embodiment of the present application;

[0028] FIG9 is a schematic diagram of a window scheduling algorithm provided by one embodiment of the present application;

[0029] FIG10 is a flowchart of a compilation method provided by an embodiment of the present application;

[0030] FIG11 is a flowchart of a compilation method provided by an embodiment of the present application;

[0031] FIG12 is a flowchart of a compilation method provided by one embodiment of the present application;

[0032] FIG13 is a flowchart of a compilation method provided by one embodiment of the present application;

[0033] FIG14 is a schematic diagram of a specific compilation example provided by one embodiment of the present application;

[0034] FIG15 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0035] FIG16 is a schematic diagram of a specific compilation example provided by one embodiment of the present application;

[0036] FIG17 is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0037] FIG18 is a schematic diagram of a specific compilation example provided by one embodiment of the present application;

[0038] FIG19 is a schematic diagram of a specific compilation example provided by one embodiment of the present application;

[0039] FIG20 is a schematic diagram of a specific compilation example provided by one embodiment of the present application;

[0040] FIG21 is a schematic diagram of a specific compilation example provided by one embodiment of the present application;

[0041] FIG22 is an application diagram provided by an embodiment of the present application;

[0042] FIG23 is a schematic diagram of an application effect provided by an embodiment of the present application;

[0043] FIG24 is a structural block diagram of a compiling device provided by one embodiment of the present application;

[0044] FIG25 is a structural block diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0046] First, a brief introduction is given to the terms involved in the embodiments of this application.

[0047] AI refers to technologies that can represent human intelligence through ordinary computer programs. AI is a new technical science that studies and develops theories, methods, techniques, and application systems for simulating, extending, and expanding human intelligence.

[0048] Artificial Intelligence (AI) refers to the theories, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, to perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that seeks to understand the essence of intelligence and produce new intelligent machines that can respond in a manner similar to human intelligence. AI also involves studying the design principles and implementation methods of various intelligent machines, enabling them to possess the capabilities of perception, reasoning, and decision-making.

[0049] Artificial intelligence (AI) technology is a comprehensive discipline encompassing a wide range of fields, encompassing both hardware and software technologies. Foundational AI technologies generally include sensors, specialized AI chips, cloud computing, distributed storage, big data processing, pre-trained models, operating / interaction systems, and mechatronics. Pre-trained models, also known as large models or basic models, can be fine-tuned and widely applied to downstream tasks across various AI disciplines. AI software technologies primarily encompass computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0050] With the research and progress of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned driving, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (Artificial Intelligence Gene rated Content, AIGC), conversational interaction, smart medical care, smart customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0051] Operator: Operator is the basic computing unit of machine learning models.

[0052] Software Pipelining: It is a type of loop instruction scheduling algorithm in the compiler field.

[0053] Modulo Scheduling: It is a classic soft-pipeline algorithm in the field of compilers.

[0054] List Scheduling: It is a type of non-loop instruction scheduling method in the compiler field and is the basic scheduling algorithm in the compiler.

[0055] Basic Block (BB): In the compiler, a block represents a linearly executed instruction. A BB has a single entry instruction and a single exit instruction. The compiler breaks down a program into a combination of basic blocks.

[0056] DAG (Directed Acyclic Graph): A directed graph is considered a directed acyclic graph if there are no edges from any vertex back to that vertex. In this application, a DAG is used to indicate dependencies between instructions. For example, if instruction A generates data and passes it to instruction B via a register, then in the DAG, there is a directed edge from node A to node B. The weight of this directed edge is the minimum number of ticks (delay) between instruction A emitting the data and passing it to instruction B.

[0057] II (Initiation Interval): refers to the time difference between the start of execution of the corresponding instructions of two loops in modular scheduling.

[0058] Heuristic Algorithms: In contrast to optimization algorithms, heuristic algorithms do not mathematically solve optimization problems. Instead, they are constructed based on intuition or experience and are widely used in the compiler field. This application uses a heuristic method to find a set of offset positions for the scheduling window.

[0059] Stall cycle: This refers to the number of processor cycles during which pipeline execution is paused due to data or resource conflicts. In window scheduling, the number of stall cycles introduced between cycles must be calculated for each table scheduling result.

[0060] AI compilers are domain-specific compilers used to convert machine learning models in various formats into a compiler intermediate representation (IR), optimize it, and ultimately generate executable code for the corresponding hardware platform. AI compilers typically use a classic front-end and back-end architecture to connect the models generated by the machine learning framework with the underlying chip. Figure 1 shows the overall structure of an AI compiler.

[0061] In Figure 1, the AI ​​compiler reads a machine learning model 101 generated from a machine learning framework such as TensorFlow or Pytorch. The AI ​​compiler first performs model parsing 102 on the front end of the model 101, parsing it into a high-level IR (Intermediate Representation) (usually a computational graph), and then performs target-independent optimization (optimization independent of the target hardware) 103, such as arithmetic simplification, operator fusion, etc., and outputs the optimized high-level IR. Next, it enters the back-end target-related optimization 104, such as dedicated instruction mapping, memory allocation, memory access latency hiding, etc., and outputs device-related low-level IR; finally, it enters the back-end code generation stage 105 to generate a target program 106 that can run on the AI ​​chip.

[0062] The compilation method provided in this application is in the code generation stage 105 in the AI ​​compiler.

[0063] During the code generation phase, the AI ​​compiler divides the acquired high-level computer language code into multiple basic blocks (BBs), which are linear segments of program code. For each BB, the compiler schedules the code within it, generating an instruction sequence. The compiler then packages the instructions within the sequence, generating multiple instruction packets. Each instruction packet is then converted into a series of binary data of fixed or variable length. These converted instruction packets are then sent to the hardware (AI chip) for execution, completing the BB compilation process. The AI ​​chip processes one instruction packet in parallel per clock cycle.

[0064] Instruction Scheduling: Instruction scheduling reorders the order in which instructions are issued, increasing the parallelism of instruction execution and reducing the total execution time of operators. Instruction scheduling is subject to various constraints when selecting instructions, such as instruction dependencies, hardware resources, and registers. The primary goal of instruction scheduling is to minimize pipeline stalls and find the optimal solution within these constraints.

[0065] Instruction scheduling optimization algorithms include table scheduling algorithm, modulo scheduling algorithm and window scheduling algorithm.

[0066] Table scheduling is a method for adjusting instruction order based on a greedy and heuristic algorithm. The algorithm uses basic blocks as the base interval and continuously selects and adjusts the instruction order within this interval based on conditions such as instruction dependencies and hardware resource usage. Figure 2 shows the pseudocode of the table scheduling algorithm provided by related art.

[0067] In Figure 2, Op represents an instruction, and D represents the directed acyclic graph of instruction dependencies, D = (N, E), where N is a node representing an instruction, and E is an edge representing the minimum distance between two nodes. The variable Cycle is the simulated hardware clock cycle, initialized to 1, and increments during code execution. Whenever Cycle+1 occurs, all instructions completed in the previous Cycle are deleted from the Active list, and each successor node of these instructions in D is checked, and available instructions are moved to the Ready list. The Ready list contains all instructions that can be used in the current Cycle without affecting the correctness of continuous execution, and is initialized to all child nodes of the parent node in D. The Active list contains all instructions that can actually be emitted at the current time.

[0068] The modular scheduling algorithm is a type of soft pipelining algorithm. Soft pipelining is a crucial optimization stage in the code generation process of the AI ​​compiler's backend. Operators, the fundamental computing units of AI models, contain numerous loop instruction structures, which consume a significant portion of chip execution time. Soft pipelining optimization is a type of compilation algorithm specifically designed to optimize loop instruction structures. Currently, the mainstream soft pipelining optimization algorithm in the industry is the modular scheduling algorithm. Its main algorithmic concept is shown in Figure 3.

[0069] In Figure 3, assume that a loop instruction structure has a total of N iterations. The instruction sequence in its core loop takes T beats per iteration, where T can be divided into three equal segments. In part (A) of Figure 3, each iteration begins after the previous iteration completes. Each iteration is represented by I(n), where n∈[0, 1, 2, ..., N-2, N-1]. For a loop, each equally divided segment of code is represented by S(n). In Figure 3, each segment of code is divided into three segments, i.e., n∈[0, 1, 2]. The code after modular scheduling is shown in part (B) of Figure 3, where the instructions of the I(n+1) iteration can begin execution in advance without waiting for the I(n) iteration to complete. The time difference between the start of execution of I(n) and I(n+1) is called the start interval II. II equals the number of beats a segment of code occupies in a loop. In part (B) of Figure 3, II = T / 3. Analyzing the folded loops reveals a stable code structure, as shown in Figure 3 (C). This section shows the code structure after modular scheduling. It consists of three phases: the fill phase, which includes the code at the beginning of the first two loops; the core phase, which includes code from three consecutive loops; and the drain phase, which includes code from the end of the last two loops.

[0070] For a specific instruction in a loop, if it issues on beat K relative to the first instruction in that loop, then its issue time in the folded core phase is T = K mod II. This is the origin of the name modulo scheduling. For example, if instruction A before folding issues on beat 16 relative to the first instruction in the loop, and II is 10 beats, then after folding, instruction A will issue on beat 6, and the core loop execution time will also be compressed to 10 beats.

[0071] The basic algorithm flow of modular scheduling is shown in Figure 4.

[0072] Step 401, start.

[0073] Step 402: Construct a directed acyclic graph (DAG). A DAG (directed acyclic graph) is constructed based on the input instructions. The DAG is used to represent the dependency relationship between instructions.

[0074] Step 403: Calculate scheduling parameters, such as the initial and maximum values ​​of the start interval, the depth and height of nodes in the DAG graph, etc.

[0075] Step 404: Sort the instructions. Adjust the scheduling order of the instructions based on the node-related parameters calculated in step 403.

[0076] Step 405: traverse the start intervals in sequence, starting from the initial start interval, and try to find a reasonable scheduling result in sequence until the start interval reaches the maximum value.

[0077] Step 406: Use a search algorithm to traverse the instructions and calculate the scheduling result. Search each instruction in order to see if it can be successfully scheduled, that is, if the instruction does not have resource conflicts or unreasonable dependencies with the scheduled instructions.

[0078] Step 407: Determine whether to stop searching. If yes, go to step 408; if not, go back to step 405.

[0079] Step 408: Determine whether the scheduling is successful. If the scheduling is successful, execute step 409; if the scheduling is unsuccessful, execute step 410.

[0080] Step 409: Adjust the code. If the scheduling is successful, a complete code structure is generated according to the scheduling result, including the filling stage, the core stage, and the emptying stage.

[0081] Step 410: End. Scheduling fails, and the original code remains unchanged.

[0082] Window scheduling is also a soft pipelining algorithm. Compared to modular scheduling, it has a high scheduling success rate and guaranteed performance in AI accelerator architectures with high resource conflicts.

[0083] As shown in Figure 5 (A), assuming that loop BB has M instructions, and window scheduling selects an offset position K to establish a scheduling window, the scheduling window will contain MK instructions in cycle n-1 and K instructions in cycle n. These instructions in the scheduling window are table-scheduled. If the execution time of the scheduled instructions is the shortest, the current scheduling result is the optimal result. Finally, after traversing all offset positions, as shown in Figure 5 (B), the final code consisting of the prolog (filling phase), kernel (core phase), and epilog (draining phase) is generated according to the optimal window offset position.

[0084] Window scheduling can be equivalent to a modular scheduling algorithm that is fixedly divided into two segments. This is the basis for window scheduling to improve instruction-level parallelism and achieve better performance.

[0085] Modulo scheduling algorithms typically use a greedy algorithm to search for instruction schedules. Given an II, the algorithm sequentially attempts to schedule all instructions between times 0 and (II-1). Modulo scheduling succeeds if all instructions can be dispatched at such times that all data dependencies between them are satisfied and the hardware resources used by the instructions do not conflict.

[0086] The problem with modular scheduling is that as the number of instructions to be scheduled increases and resource conflicts between instructions increase, the greedy algorithm's search capabilities are insufficient, often failing to schedule successfully. Using more complex search algorithms, such as backtracking, increases algorithm complexity exponentially, and the compilation process often fails due to excessive time consumption.

[0087] For AI accelerators, hardware instructions are often complex, sharing many hardware resources, making conflicts very likely. Furthermore, instruction execution takes a long time, often requiring more than 10 cycles to output a result, further increasing the difficulty of scheduling algorithms. Therefore, using modular scheduling in AI accelerator operator development often results in scheduling failures.

[0088] Because modulo scheduling is prone to failure, we attempted to use the aforementioned window scheduling in the AI ​​compiler. Window scheduling effectively addresses the issue of modulo scheduling failures, as the table scheduling algorithm used by window scheduling when traversing offsets consistently produces a scheduling result, and the performance difference is comparable to that of modulo scheduling.

[0089] However, window scheduling is also a complex scheduling algorithm. Traditional window scheduling methods have two problems:

[0090] Problem (1) After the scheduling window is moved, the DoubleDAG needs to be updated. In order to establish the dependency between instructions in two cycles, it is necessary to copy two instructions from the original BB and create a new BB (DoubleBB). Then, a DAG is created for this new BB, which is called DoubleDAG, to describe the dependency between instructions in the scheduling window. After each scheduling window is moved, the instructions before the scheduling window offset position need to be connected to the end of the DoubleDAG, that is, the DoubleDAG needs to be updated synchronously to ensure that the DoubleDAG contains the dependency of all instructions in the scheduling window.

[0091] The main purpose of updating the DoubleDAG is that by folding the instruction nodes before the scheduling window to the nodes below the DoubleDAG, the compiler can establish dependencies between instructions that are defined across loops and use the same registers.

[0092] As shown in Figure 6, the shaded area represents the scheduling window 107. When the scheduling window 107 moves to the position in Figure 6, all instructions before the scheduling window 107 (including instruction B') need to be moved from the original position in the DoubleDAG to the new position below the DoubleDAG. Note that no instruction movement actually occurs here, only the DoubleDAG is updated. At this time, instruction A and instruction B' have a new direct data dependency relationship, and instruction B and instruction B' correspond to the same instruction, so the emission time is the same. At this time, the data dependency relationship between instruction A and instruction B' can be used to determine the data dependency relationship between instruction A and instruction B, and then determine the Stall Cycle (pause time) that needs to be added after the table scheduling is completed.

[0093] The calculation formula for Stall Cycle (pause time) is as follows:

[0094] Stall Cycle=DefCycle+Latency(A,B)-MaxCycle-UseCycle

[0095] Here, DefCycle is the time instruction A is issued; Latency(A,B) is the delay between the data output by instruction A and the input to instruction B; MaxCycle is the time when all instructions in the scheduling window have completed execution; and UseCycle is the time instruction B is issued. This formula means that if instruction A outputs data in the current cycle and transmits it to instruction B in the next cycle, if the latency relationship is not met, then additional stall cycles are required.

[0096] For example, if loop BB is scheduled according to the scheduling window shown in FIG6 , then before executing instruction B of the second loop, it is necessary to ensure that instruction A' of the first loop is executed and the data reaches instruction B (that is, the emission time of instruction A' of the first loop plus the delay time of instruction A' must be before the emission time of instruction B of the second loop). If this relationship is not satisfied, it is necessary to increase the Stall Cycle to increase the execution time of the scheduling window, thereby delaying the start time of instruction B of the second loop, to ensure that the data of instruction A' of the first loop can be passed to instruction B of the second loop.

[0097] In the above process, appending an instruction to the lower part of DoubleDAG requires complex graph operations and a large amount of computation.

[0098] Problem (2) Moving the window instruction by instruction is inefficient. Although the above window scheduling algorithm includes a limit for early exit, the window movement process is still performed instruction by instruction. In actual applications, this is still very time-consuming, and the difference between two adjacent offset instructions is often not significant. Therefore, the search efficiency of the instruction-by-instruction sliding window is low.

[0099] In order to solve the above problem (1), the present application proposes a compilation method, which is a method for implementing compilation based on multiple DAGs.

[0100] Figure 7 shows a schematic diagram of a terminal device provided by an exemplary embodiment of the present application. The compilation method provided by this embodiment of the present application is executed by terminal device 700, which can be a mobile phone, computer, intelligent voice interaction device, smart home appliance, in-vehicle terminal, etc. The terminal device has a compiler installed, and the compilation method provided by this embodiment of the present application is executed by the compiler in the terminal device.

[0101] FIG8 shows a flowchart of a compilation method provided by an exemplary embodiment of the present application. The method is illustrated by an example in which the method is executed by a compiler in the terminal device shown in FIG8 . The method includes the following steps.

[0102] Step 810 , loop-unroll the instruction sequence in the loop BB to generate a multiple BB and a multiple DAG corresponding to the multiple BB; the multiple BB includes an instruction sequence that loops at least three times, and the multiple DAG is used to indicate the data dependency between the instructions in the multiple BB.

[0103] Exemplarily, the loop BB can be a loop BB in an AI model. An AI model can include at least one loop BB, and each loop BB can be compiled using the method provided in the embodiments of the present application. Optionally, an operator in an AI model can include at least one loop BB.

[0104] A loop block (BB) has only a single entry instruction and a single end instruction, and includes a loop body that is repeatedly executed. A loop block (BB) may refer to a loop core BB, which has only one loop body. When a second loop body is nested within a first loop body and no other loop bodies are nested within the second loop body, the second loop body may be the loop core BB (the loop body includes at least one instruction). Exemplarily, the total number of instructions within the loop block (BB) is less than a threshold, and the loop block (BB) does not contain assembly instructions or other instructions with side effects (modification or predetermined state).

[0105] A loop BB contains a repetitive sequence of instructions, known as the loop body. This sequence of instructions is executed repeatedly until a termination condition is met. A loop BB has only one entry instruction and one exit instruction: the entry instruction starts the loop, and the exit instruction ends it.

[0106] Loop unrolling a loop BB means copying the loop BB multiple times to obtain multiple BBs. Multiple BBs include instruction sequences that iterate the loop BB at least three times. For example, copying the loop BB three times yields a triple BB. This means the loop BB includes the loop BBs of the first iteration, the second iteration, and the third iteration. Each of these three iterations is obtained by copying the original loop BB.

[0107] For example, if a loop BB includes instruction A, instruction B, and instruction C, then the multiple BB obtained after copying it three times includes: instruction A, instruction B, instruction C, instruction A', instruction B', instruction C', instruction A", instruction B", and instruction C. Among them, instruction A, instruction A', and instruction A" correspond to instruction A; instruction B, instruction B', and instruction B" correspond to instruction B; and instruction C, instruction C', and instruction C" correspond to instruction C.

[0108] A multi-fold DAG is constructed based on the data input and output relationships of each instruction indicated in the multi-fold BB, as well as the delay time of each instruction. The multi-fold DAG includes the data dependencies and delay time of each instruction in the multi-fold BB.

[0109] In a multi-fold DAG, each instruction in a multi-fold BB corresponds to a node. When the output data of instruction A is the input data of instruction B, a directed line segment will be used in the multi-fold DAG to connect node A corresponding to instruction A and node B corresponding to instruction B. The directed line segment points from node A to node B, and the weight value on the directed line segment is the delay time corresponding to instruction A.

[0110] Among them, data dependencies include: dependent relationships and dependent relationships. Dependent relationships refer to which other instructions the instruction depends on (that is, the output data of the instruction needs to be input into other instructions as input data), and dependent relationships refer to which other instructions the instruction depends on (that is, the input data of the instruction is the output data of other instructions).

[0111] An instruction can have at least one data dependency, which is represented as a directed line in a multi-DAG. When there is a directed line between node A (instruction A) and node B (instruction B) in a multi-DAG, it indicates that there is a data dependency between instruction A and instruction B. When the directed line is from node A to node B, it indicates that instruction A is dependent on instruction B (the input data of instruction B is the output data of instruction A).

[0112] Each data dependency has a corresponding latency. Specifically, the weight of each directed segment in a multi-dimensional DAG is the latency. For example, if the directed segment between instructions A and B is labeled with a weight of 1, it means that the output data from instruction A needs to wait one tick before being transmitted to instruction B. For example, the latency is determined by instruction A and the hardware resources that execute it.

[0113] Based on the data dependencies in the multiple DAGs, we can determine the emission time of each instruction within a scheduling window. This in turn determines the target emission time when all instructions within the scheduling window have completed execution, as well as the target pause time. The target pause time is designed to ensure that the input data required by each instruction in the next cycle reaches the instruction before its emission time. Therefore, we can calculate the execution time of each scheduling window based on the multiple DAGs, and select the scheduling window with the shortest execution time as the final target scheduling window.

[0114] Step 820: Window scheduling is performed based on multiple BBs to determine a target scheduling window and the scheduling result corresponding to the target scheduling window. Window scheduling is used to split the instruction sequence in the loop BB into two parts based on the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop. The target scheduling window is a scheduling window whose execution time meets the time condition. The execution time is the time required to execute the instructions in the window, calculated based on the data dependencies in the multiple DAGs.

[0115] Optionally, after obtaining multiple BBs and multiple DAGs, multiple scheduling windows can be tested on the multiple BBs. Based on the instruction execution time in each scheduling window, a target scheduling window with an execution time that meets the required time conditions (time conditions) can be selected. For example, the time conditions can include: the shortest execution time, the execution time close to the target value, or the longest execution time.

[0116] Exemplarily, during window scheduling, the scheduling window's sliding range starts from the first instruction of the first loop and ends at the last instruction of the second loop. That is, the scheduling window slides only within the instruction sequences of the first two loops. The third loop in the multi-time BB is used to generate the multi-time DAG. Thus, when the scheduling window slides to the instruction in the second loop, the execution time of the scheduling window can be calculated based on the data dependencies between the instructions in the second and third loops.

[0117] Step 830: Compile and obtain the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0118] For example, after determining the target scheduling window, the loop BB is compiled according to the scheduling result corresponding to the target scheduling window, so that the running time of the compiled target code can be minimized, thereby improving the compilation and running efficiency of the loop BB.

[0119] In this embodiment, the multi-DAG method can be, for example, a TripleDAG method. As shown in Figure 9 , before instruction scheduling, a TripleBB and the corresponding TripleDAG are established. During the sliding scheduling window, there is no need to adjust or update the TripleDAG because all dependencies are already built in the TripleDAG. Therefore, the stall cycles introduced by instructions A and B can be directly calculated, thus avoiding the problem of updating the DAG during the scheduling process.

[0120] For example, as shown in Figure 9, the shaded area represents scheduling window 107. When scheduling window 107 moves to the position shown in Figure 9, the data dependencies of all instructions within the scheduling window need to be obtained to calculate the stall cycle. At this time, the data dependency of instructions A and B' in the TripleDAG can be directly determined based on the data dependency of instructions A and B', given that instructions B and B' correspond to the same instruction and have the same emission time. Furthermore, based on the data dependency of instructions A and B, the stall cycle (pause time) that needs to be added after the table scheduling is completed is determined.

[0121] As can be seen, because TripleDAG already contains the data dependency relationship between instructions A and B, there is no need to update TripleDAG after each scheduling window movement. The data dependency relationship between instructions A and B can be directly queried from TripleDAG, and then the data dependency relationship between instructions A and B can be determined. This greatly reduces the amount of computation and improves the computational efficiency of the stall cycle.

[0122] In summary, the method provided in the embodiments of the present application provides a soft-pipelining algorithm for compiling loop BBs in AI models. A window scheduling algorithm is used to split the loop BB into two parts, allowing the instructions in the first part of the next loop to execute synchronously with the instructions in the second part of the current loop, saving instruction execution time. To find the optimal split position and minimize execution time, the loop BB is replicated three times to obtain multiple BBs and multiple DAGs. Multiple scheduling windows are tried on the multiple BBs, and the scheduling results corresponding to each scheduling window are determined. The scheduling window box selects the instructions in the second part of the first loop BB and the instructions in the second loop BB. Based on the data dependencies of the instructions indicated in the multiple DAGs, the execution time required for the two parts of the instructions in each scheduling window to execute synchronously is calculated. The scheduling window with the shortest execution time is then selected from the multiple scheduling windows as the final target scheduling window. The split position corresponding to the target scheduling window is the optimal split position. Compiling the loop BB according to the scheduling results corresponding to the target scheduling window can improve the compilation efficiency of the loop BB and minimize the execution time of the target code of the compiled target program.

[0123] The loops in the operator are usually expanded 4 or 8 times, and the number of instructions is usually 100-200. In this case, moving the scheduling window instruction by instruction is very inefficient. Moreover, due to the large number of repeated instructions, the scheduling results of two adjacent windows are often the same or very different. Therefore, to solve the above problem (2), this application uses a different heuristic method to provide a more efficient search offset position.

[0124] FIG10 shows a flowchart of a compilation method provided by an exemplary embodiment of the present application. This method is illustrated by an example executed by a compiler in the terminal device shown in FIG7 . Window scheduling is performed based on multiple BBs, and a target scheduling window is determined, including:

[0125] Step 821: Determine candidate offset positions based on multiple BBs, traverse each candidate offset position, and determine the traversed position; the candidate scheduling window selects a window instruction sequence in the multiple BBs, and the window instruction sequence includes the second part of the instruction sequence in the first cycle and the first part of the instruction sequence in the second cycle in the multiple BBs; the second part of the instruction sequence and the first part of the instruction sequence are sequentially connected in the multiple BBs.

[0126] Exemplarily, the window length of the scheduling window is equal to the total number of instructions in the cycle BB. For example, if the cycle BB includes 10 instructions, the window length of the scheduling window is equal to 10 instructions.

[0127] If a loop BB consists of 10 instructions, theoretically, there can be 10 candidate scheduling windows. Starting from the first instruction of the first loop, each instruction can be the first instruction of a candidate scheduling window. That is, with a sliding step of one instruction, the sliding scheduling window can slide from the first instruction of the first loop to the last instruction of the first loop, resulting in a total of 10 candidate scheduling windows. By calculating the execution time corresponding to each of the 10 candidate scheduling windows, the candidate scheduling window with the shortest execution time can be selected as the target scheduling window. The sliding step is also known as the offset step.

[0128] However, when the number of instructions in a loop BB is large, for example, 100 or 1000 instructions, determining the candidate scheduling window using the above method requires calculating the execution time 100 or 1000 times, respectively, which is computationally intensive. Furthermore, for loop BBs with a large number of instructions, the execution time differences between adjacent candidate scheduling windows are small. Therefore, the present embodiment employs a heuristic algorithm to determine the sliding step size of the candidate scheduling window, determining the offset step size based on the number of instructions in the loop BB. The larger the number of instructions, the larger the offset step size.

[0129] For example, the offset step of the scheduling window is determined according to the total number of instructions in the loop BB, and the candidate offset position is determined according to the offset step. The candidate offset position may refer to the first instruction in the candidate scheduling window.

[0130] In this embodiment, dynamically adjusting the offset step size based on the number of instructions in the loop BB effectively reduces the search space and speeds up the determination of the scheduling window. Determining the sliding step size of candidate scheduling windows through a heuristic algorithm more intelligently adapts to the characteristics of different loop structures, avoiding blind searches and thus reducing computational overhead during the scheduling process.

[0131] In one embodiment, determining the offset step size of the scheduling window according to the total number of instructions in the loop BB includes:

[0132] Obtain multiple preset quantity ranges, the multiple preset quantity ranges correspond to multiple offset steps one by one, and the multiple offset steps increase sequentially; from the multiple preset quantity ranges, determine the target quantity range in which the total number of instructions is located, and use the offset step corresponding to the target quantity range as the offset step of the scheduling window.

[0133] The plurality of preset quantity ranges may be at least two preset quantity ranges, each preset quantity range corresponding to one offset step. A preset quantity range includes an upper limit value and a lower limit value, as well as values ​​between the upper limit value and the lower limit value. For example, if the upper limit value of a preset quantity range is a first value and the lower limit value is 0, then the preset quantity range is a range from 0 to the first value.

[0134] In multiple preset quantity ranges, the upper limit of one preset quantity range can be used as the lower limit of another preset quantity range, and the lower limit of one preset quantity range can be used as the upper limit of another preset quantity range. For example, the lower limit of one preset quantity range is a first value and the upper limit is a second value, while the lower limit of another preset quantity range is the second value and the upper limit is a third value.

[0135] From multiple preset quantity ranges, it can be determined which preset quantity range the total number of instructions falls within. The preset quantity range in which the total number of instructions falls is the target quantity range. The offset step size corresponding to the target quantity range is used as the offset step size of the scheduling window.

[0136] Optionally, there are five preset quantity ranges and five step sizes. The first preset quantity range is a quantity range smaller than the first value, i.e., its upper limit is the first value. This preset quantity range corresponds to the first step size. The second preset quantity range has a lower limit of the first value and an upper limit of the second value. This preset quantity range corresponds to the second step size. The third preset quantity range has a lower limit of the second value and an upper limit of the third value. This preset quantity range corresponds to the third step size. The fourth preset quantity range has a lower limit of the third value and an upper limit of the fourth value. This preset quantity range corresponds to the fourth step size. The fifth preset quantity range has a lower limit of the fourth value and an upper limit of the fifth value. This preset quantity range corresponds to the fifth step size. Thus: if the total number of instructions is less than or equal to the first value, the offset step size is determined to be the first step size. If the total number of instructions is greater than the first value and less than or equal to the second value, the offset step size is determined to be the second step size. If the total number of instructions is greater than the second value and less than or equal to the third value, the offset step size is determined to be the third step size. If the total number of instructions is greater than the third value and less than or equal to the fourth value, the offset step size is determined to be the fourth step size. When the total number of instructions is greater than the fourth value, the offset step is determined to be the fifth step.

[0137] Among them, the first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step length, the second step length, the third step length, the fourth step length and the fifth step length increase in sequence.

[0138] For example, the first value is 10, the second value is 20, the third value is 30, and the fourth value is 40. The first step length is 1, the second step length is 2, the third step length is 4, the fourth step length is 8, and the fifth step length is 16. If the loop BB includes 33 instructions, the offset step length is 8, and the starting positions of the candidate scheduling windows are the 1st instruction, the 9th instruction, the 17th instruction, the 25th instruction, and the 33rd instruction, respectively, resulting in five candidate scheduling windows. Subsequently, any one of the five candidate scheduling windows can be selected to execute step 221.

[0139] In one embodiment, a heuristic algorithm with adaptive step size is used, for example:

[0140] (1) When the total number of instructions in the loop BB is less than or equal to M, the offset step size of the scheduling window is adjusted to 1;

[0141] (2) When the total number of instructions is greater than M and less than or equal to 2M, the offset step size of the scheduling window is adjusted to 2;

[0142] (3) When the total number of instructions is greater than 2M and less than or equal to 3M, the offset step size of the scheduling window is adjusted to 4;

[0143] (4) When the total number of instructions is greater than 3M and less than or equal to 4M, the offset step size of the scheduling window is adjusted to 6;

[0144] (5) When the total number of instructions is greater than 4M, the offset step of the scheduling window is adjusted to 8.

[0145] After testing, when the appropriate M value is selected, the compilation speed is increased by more than 50%-60%, and the performance degradation does not exceed 5%.

[0146] In this embodiment, by matching the total number of instructions with a preset range, a larger step size is used for loops with a large number of instructions, while a smaller step size is used for loops with a small number of instructions. This allows the offset step size of the scheduling window to be dynamically adjusted. Furthermore, this dynamic matching allows the scheduling scheme to adapt to loop structures of varying sizes (such as small loops, medium loops, or large nested loops), thereby improving the algorithm's versatility.

[0147] Exemplarily, other methods can also be used to determine the candidate offset positions. For example, the predetermined instructions in the loop BB are used as candidate offset positions. The predetermined instructions can be instructions with a long execution time or instructions with a long delay time. For example, the predetermined instructions can be inverse instructions, exponential instructions, etc. By using the instruction with the longest delay time as the first instruction in the candidate scheduling window, other instructions can be executed synchronously with the first instruction, thereby shortening the execution time of the candidate scheduling window. Optionally, this method can be combined with the above-mentioned heuristic algorithm method, for example, determining the offset step of the scheduling window based on the total number of instructions in the loop BB, determining the first group of candidate offset positions based on the offset step; and determining the second group of candidate offset positions based on the predetermined instructions in the loop BB.

[0148] Exemplarily, candidate offset positions may also be determined based on predetermined data dependencies. For example, if instruction x is dependent on n instructions, then when n is greater than a threshold, instruction x may be selected as a candidate offset position. Alternatively, if instruction x is dependent on m instructions, then when m is greater than a threshold, instruction x may be selected as a candidate offset position. Similarly, this method may combine at least one of the aforementioned heuristic algorithms and predetermined instructions to determine candidate offset positions.

[0149] For example, a neural network model can be used to obtain candidate offset positions. For example, the neural network model can be trained to predict candidate offset positions. After training, the neural network model can be used to output candidate offset positions based on multiple BB inputs. Similarly, this method can combine at least one of the aforementioned heuristic algorithms, predetermined instructions, and predetermined data dependencies to determine candidate offset positions.

[0150] Step 822: Use a table scheduling algorithm to schedule the window instruction sequence in the candidate scheduling window to obtain a scheduling result corresponding to the candidate scheduling window.

[0151] Exemplarily, a table scheduling algorithm is used for the instruction sequence in the candidate scheduling window to obtain a table scheduling result after table scheduling.

[0152] For example, if a loop BB contains 10 instructions, a candidate scheduling window might include the last 6 instructions of the first loop BB and the first 4 instructions of the second loop BB. After table scheduling, the table scheduling algorithm adjusts the order of the 10 instructions based on the data dependencies of each instruction, resulting in a scheduled instruction sequence (the scheduling result). The order of the scheduled instruction sequence may differ from the order of the instruction sequence within the candidate scheduling window.

[0153] The method provided in this application can be used in an AI compiler toolchain, located in the backend code generation module of the AI ​​compiler. Typical application scenarios include AI compilers used with AI chips. This method can significantly accelerate the compilation time of operator core loops.

[0154] In addition, the method provided in this application can also be used in traditional compilers to speed up the compilation time of the core loop generated by the compiler backend.

[0155] As shown in Figure 11 , the input to this system is the instruction sequence in a loop core BB (loop BB) 1108. Loop core BB 1108 must meet the following constraints: the loop body consists of only one BB, not multiple BBs; the number of instructions in a BB must be within a certain range; and the BB should not contain assembly or other side-effect instructions (such as those that modify the machine's intended state).

[0156] The fast window scheduler 1109 is the core facility of this application. It schedules the input instructions based on the input loop core instruction sequence using the window scheduling algorithm provided by this application. It requires the establishment of auxiliary data structures such as TripleBB and TripleDAG, and uses heuristic algorithms to improve window traversal efficiency. This reduces the compilation time of window scheduling while ensuring the performance of generated code.

[0157] The instruction scheduling result 1110 generated by the fast window scheduler 1109 includes the scheduled instruction, the time when the instruction is issued, the stage to which the instruction belongs, the optimal II obtained by scheduling, and the offset step of the corresponding scheduling window.

[0158] The soft-pipelined instruction expander 1111 is a basic module typically provided by the compiler. It uses the instruction scheduling results 1110 to first generate the core BB (execution time II) after window scheduling. It then adds the prologue (filling) and epilogue (draining) logic to ultimately generate the correct soft-pipelined code.

[0159] This application improves the traditional DoubleBB window scheduling algorithm. The main process is shown in Figure 12 and includes the following steps:

[0160] Step 1201: Back up the original BB to OriBB.

[0161] Step 1202: Copy the backup OriBB three times to generate a new TripleBB and generate a corresponding TripleDAG.

[0162] Step 1203: Obtain a set of window offset values ​​using a heuristic algorithm; extract a window offset value and obtain a scheduling window on TripleBB accordingly.

[0163] Step 1204: Use table scheduling to schedule the instructions in the scheduling window. Table scheduling is a basic functional module provided by the compiler.

[0164] Step 1205: Analyze the scheduling results of the table scheduling using TripleDAG, and store the analyzed results in a corresponding data structure.

[0165] Step 1206: If the search for all offset positions is completed, proceed to step 1207; otherwise, return to step 1203 to search for the next offset value.

[0166] Step 1207 : Analyze the rationality of the scheduling result, such as whether the execution time after scheduling is improved, etc. If it is reasonable, proceed to step 1209 ; otherwise, proceed to step 1208 .

[0167] Step 1208: Use OriBB to restore the original cycle BB.

[0168] Step 1209 : using the soft pipeline instruction expander provided by the compiler, obtain the corresponding soft pipeline code according to the scheduling result of the scheduling window.

[0169] At this point, the processing process of the fast soft pipelining algorithm based on window scheduling is completed.

[0170] The main purpose of analyzing the table scheduling results in step 1205 of the above process is to determine the launch time of each instruction and the overall execution time of the sequence of instructions (i.e., the corresponding II) from the scheduled instruction sequence output by the table scheduling. This execution time includes the target launch time and pause time of the instruction sequence.

[0171] Step 823: Calculate the execution time corresponding to the candidate scheduling window based on the scheduling result and the multiple DAGs.

[0172] The execution time of instructions within a candidate scheduling window can be determined based on the target launch time and target pause time corresponding to the candidate scheduling window. For example, the execution time of instructions within a candidate scheduling window is equal to the sum of the target launch time and the target pause time. The target launch time can be the time when the last instruction in the candidate scheduling window completes execution after table scheduling. The target pause time and target launch time are the maximum or average of the pause times corresponding to each instruction in the candidate scheduling window, or any of the pause times that meet the time threshold.

[0173] Exemplarily, the target launch time corresponding to the candidate scheduling window is calculated according to the scheduling result, the target pause time corresponding to the candidate scheduling window is calculated according to the scheduling result and multiple DAGs, and the sum of the target launch time and the target pause time is determined as the execution time corresponding to the candidate scheduling window.

[0174] In one embodiment, the algorithm process for calculating the command target launch time is shown in FIG13 , and includes the following steps.

[0175] Step 1301: Obtain a DAG generated during table scheduling, where the DAG consists of instructions in a scheduling window; obtain an instruction resource manager provided by the compiler, where the instruction resource manager is responsible for checking whether there is a resource conflict between instructions.

[0176] Among them, instructions are executed by hardware resources in the AI ​​chip. One instruction can be executed by one or more hardware resources. When the hardware resources corresponding to an instruction are occupied by other instructions, there is a resource conflict between the instruction and other instructions. When the hardware resources corresponding to the instruction are not occupied by other instructions, there is no resource conflict between the instruction and other instructions.

[0177] Optionally, if there is a resource conflict between the instruction and other instructions at the current transmission time, the transmission time of the instruction may be adjusted, and detection continues to be performed to determine whether there is a resource conflict at the new transmission time.

[0178] Step 1302: Initialize the current time to 0 beats.

[0179] Step 1303: Take an instruction from the instruction sequence scheduled by the table.

[0180] Step 1304 determines whether the instruction should be issued at the current moment. Through DAG analysis, if there is no predecessor instruction, or the predecessor instruction has already been issued, and the current moment is greater than or equal to the predecessor instruction issuance time plus the corresponding data delay, then the instruction can be issued at the current moment, and the process proceeds to step 1306; otherwise, the process proceeds to step 1305. The predecessor instruction is the instruction that provides the input data for the current instruction. For example, if instruction A outputs data a, which is the input data that instruction B depends on, that is, if instruction B's input data is data a and instruction B's output data is data b, then instruction A is instruction B's predecessor instruction.

[0181] Step 1305: add one beat to the current moment.

[0182] Step 1306: Use the instruction resource manager to determine whether there is a resource conflict between the current instruction and the previously scheduled instruction. If there is no resource conflict, proceed to step 1307; otherwise, proceed to step 1305.

[0183] Step 1307: The current moment is the time of issuing the current instruction, and the resources occupied by the current instruction are recorded in the instruction resource manager.

[0184] Step 1308: If all instructions have been traversed, go to step 1309; otherwise, go to step 1303.

[0185] Step 1309: After all instructions have been traversed, the current time plus 1 is the target launch time of the instruction sequence.

[0186] In this embodiment, the target launch time of an instruction is calculated based on the scheduling results, accurately reflecting the hardware startup time of the instruction, thereby maximizing the parallelism of hardware resources and reducing resource idle time. The target pause time of an instruction is calculated based on the scheduling results and multiple DAGs, accurately reflecting delays caused by data dependencies or resource conflicts. By combining the target launch time and target pause time, the total execution time of the candidate scheduling window can be accurately calculated, ensuring the comprehensiveness and accuracy of the time calculation.

[0187] Furthermore, the use of multiple DAGs accurately captures data dependencies between instructions, preventing underestimation or overestimation of latency when calculating pause times. Calculating launch and pause times based on scheduling results effectively avoids conflicts with hardware resources like registers and functional units, improving hardware resource utilization and ensuring the feasibility of scheduling solutions.

[0188] In one embodiment, calculating the target launch time corresponding to the candidate scheduling window based on the scheduling result includes: determining the launch time of each instruction in the scheduling result, and determining the target launch time corresponding to the candidate scheduling window based on the launch time of each instruction.

[0189] The emission time of each instruction in the scheduling result may be determined, at least one emission time may be screened out from the emission time of each instruction, and a target emission time corresponding to the candidate scheduling window may be determined based on the screened emission time.

[0190] In this embodiment, the maximum emission time may be screened out from the emission time of each instruction, and the target emission time corresponding to the candidate scheduling window may be determined according to the maximum emission time.

[0191] In this embodiment, the transmission time of each instruction that reaches the preset time can be screened out, and the average of the screened transmission times can be used as the target transmission time. Alternatively, any one of the screened transmission times can be used as the target transmission time.

[0192] In this embodiment, by determining the launch time of each instruction in the scheduling results, the startup time of each instruction on the hardware can be accurately reflected. This fine-grained calculation method can capture the execution details of each instruction, thereby providing accurate data support for subsequent scheduling optimization. By summarizing the launch time of each instruction, the target launch time of the candidate scheduling window can be accurately calculated, thereby providing a quantitative basis for the execution efficiency of the scheduling window. Furthermore, by calculating the launch time of each instruction in real time, the scheduling strategy can be dynamically adjusted to ensure the optimality of the scheduling solution.

[0193] In one embodiment, the method for calculating the target launch time includes: initializing the current time to 0; repeatedly executing the following steps 1) to 3), traversing all instructions in the scheduling results, determining the launch time corresponding to each instruction, and adding one to the maximum launch time to determine the target launch time.

[0194] Step 1) Obtain the i-th instruction from the scheduling result port, where i is a positive integer; if the i-th instruction is allowed to be issued at the current moment and there is no resource conflict between the i-th instruction and the scheduled instructions, determine the current moment as the issuance time of the i-th instruction.

[0195] For example, when the i-th instruction is allowed to be emitted at the current moment, and the input data on which the i-th instruction depends has arrived (that is, the current moment satisfies the delay time of the instruction on which the i-th instruction depends), and there is no resource conflict between the i-th instruction and the scheduled instructions, the current moment is determined to be the emission time of the i-th instruction.

[0196] Step 2) When the i-th instruction is not allowed to be issued at the current moment, or when the i-th instruction conflicts with a scheduled instruction in terms of resources, the current moment is determined to be incremented by one.

[0197] Step 3), when i is not equal to n, let i be equal to i+1, where n is the number of all instructions.

[0198] In this embodiment, by checking whether the current time allows the instruction to be issued and whether there are resource conflicts, the issuance time of each instruction can be dynamically adjusted to ensure the accuracy of time calculation. When determining the instruction issuance time, checking whether there are resource conflicts with scheduled instructions can effectively avoid conflicts with hardware resources (such as registers, functional units, etc.). By dynamically adjusting the issuance time, the parallelism of hardware resources can be maximized.

[0199] By sequentially traversing each instruction in the scheduling results, we ensure that the issuance time of each instruction is strictly checked, thereby improving the execution efficiency of the scheduling window. When the current time does not allow the instruction to be issued or there is a resource conflict, the current time is dynamically updated to ensure that the instruction can be issued at the earliest possible time.

[0200] In one embodiment, a target pause time corresponding to a candidate scheduling window is calculated based on the scheduling result and multiple DAGs: the target pause time is initialized to 0; and steps 1> to 3> are repeatedly executed to traverse all instructions in the scheduling result.

[0201] Step 1>, obtain the i-th instruction from the scheduling result, where i is a positive integer.

[0202] Step 2>: when the i-th instruction corresponds to a pause time and the pause time is greater than the target pause time, the pause time is determined as a new target pause time.

[0203] If the i-th instruction has no pause time, continue to step 3>. Alternatively, if the i-th instruction has a pause time but the pause time is not greater than the target pause time, continue to step 3>.

[0204] Step 3>, when i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

[0205] The pause time is calculated based on the data dependency corresponding to the i-th instruction in the multi-DAG.

[0206] The process of calculating the instruction pause time is shown in FIG14 , and includes the following steps.

[0207] Step 1401: Acquire the TripleDAG initially established for window scheduling.

[0208] Step 1402: Initialize the target pause time to 0 beats.

[0209] Step 1403: Take an instruction from the instruction sequence scheduled by the table.

[0210] Step 1404 determines whether the current instruction will generate a pause time. The determination is based on calculating the instruction's Stall Cycle (pause time) based on the instruction's data dependencies in the TripleDAG. If the Stall Cycle is greater than 0, proceed to step 1405; otherwise, proceed to step 1403.

[0211] Step 1405: The Stall Cycle calculated according to the Stall Cycle calculation formula is the stall time caused by the current instruction.

[0212] Step 1406: If the current pause time is greater than the target pause time, the target pause time is updated with the current pause time.

[0213] Step 1407: When all instructions are traversed, go to step 1408; otherwise go to step 1403.

[0214] Step 1408: Obtain the target pause time of the instruction sequence.

[0215] In this embodiment, the pause time of each instruction is calculated using multiple DAGs, accurately reflecting the data dependencies between instructions and ensuring the accuracy of pause time calculation. During the traversal process, if the pause time of an instruction is found to be greater than the current target pause time, the target pause time is updated to ensure that the final target pause time is the maximum pause time among all instructions. By traversing all instructions in the scheduling results, the pause time of each instruction is checked, thus avoiding missing potential delays.

[0216] In one embodiment, the i-th instruction has a data dependency relationship with the x-th instruction, where x is a positive integer; and the method further includes:

[0217] Determine the delay time of the ith instruction, where the delay time is the delay time required for the data output by the ith instruction to be input to the xth instruction; determine the pause time corresponding to the ith instruction based on the target emission time, the emission time and delay time of the ith instruction, and the emission time of the xth instruction.

[0218] Assume that the i-th instruction and the x-th instruction have a data dependency, where x is a positive integer. The pause time for the i-th instruction is calculated as follows: The sum of the i-th instruction's launch time and the delay time is calculated to obtain a first value; the delay time is the delay time required for the data output by the i-th instruction to be input to the x-th instruction; the difference between the first value and the target launch time is calculated to obtain a second value; and the difference between the second value and the launch time of the x-th instruction is calculated to obtain the pause time corresponding to the i-th instruction.

[0219] That is, the pause time = the issuance time of the i-th instruction + the delay time for the output data of the i-th instruction to reach the x-th instruction - the time when all instructions in the candidate scheduling window are executed (target issuance time) - the issuance time of the x-th instruction.

[0220] In this embodiment, by determining the delay time between the i-th instruction and the x-th instruction, the impact of data dependencies on pause time can be accurately quantified, effectively reducing the waiting time between instructions, thereby improving the execution efficiency of the scheduling window. By combining the target launch time, the launch time of the i-th instruction, the delay time, and the launch time of the x-th instruction, the pause time of the i-th instruction can be dynamically calculated, ensuring the accuracy of the time calculation. Furthermore, by comprehensively considering the target launch time, the launch time, and the delay time, the ultimately selected scheduling window can be ensured to have the shortest execution time, thereby ensuring the optimality of the scheduling solution.

[0221] In one embodiment, an example of determining instruction dependencies based on a multiple DAG is provided. Assume that a loop BB includes instructions 1 and 2, and the multiple BB includes the following: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2, obtained by copying the loop BB; the multiple DAG indicates that second instruction 1 depends on first instruction 2, and third instruction 1 depends on second instruction 2; and the candidate scheduling window includes second instruction 1 and second instruction 2. If the i-th instruction is second instruction 2, then based on the indication in the multiple DAG that third instruction 1 depends on second instruction 2, it is determined that second instruction 2 has a data dependency with second instruction 1.

[0222] Step 824: If the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as the new stored value.

[0223] For example, the initial value of the stored value can be set to a maximum value, such as 999. The stored value is the minimum execution time of the currently calculated candidate scheduling windows. If the execution time of the currently calculated candidate scheduling window is not less than the stored value, it means that the current candidate scheduling window is not the scheduling window with the shortest execution time, and the execution time of the next candidate scheduling window will be calculated.

[0224] Exemplarily, determine whether all candidate offset positions have been traversed. If not, select a candidate offset position from the untraversed candidate offset positions to continue executing step 221. If the traversal is completed, end and obtain the target scheduling window and the execution time corresponding to the target scheduling window.

[0225] In this embodiment, by combining the second portion of the instruction sequence of the first loop in a multiple BB with the first portion of the instruction sequence of the second loop into a window instruction sequence, it is possible to effectively exploit parallelism between instructions. This combination allows the second portion of the instructions in the current loop to be executed simultaneously with the first portion of the instructions in the next loop, thereby reducing the waiting time between instructions and improving overall execution efficiency.

[0226] By traversing candidate offset positions in multiple BBs, we can fully explore possible scheduling windows and ensure the optimal scheduling solution. Using a table scheduling algorithm to schedule window instruction sequences can efficiently arrange the execution order of instructions and reduce delays caused by resource conflicts and data dependencies.

[0227] By calculating the execution time of candidate scheduling windows using multiple DAGs, we can accurately reflect the data dependencies between instructions and ensure the reliability of time calculations. By comparing the execution time of candidate scheduling windows with stored values, we can dynamically update the optimal scheduling window, ensuring that the final selected scheduling window has the shortest execution time.

[0228] In this embodiment, the method further includes: if the execution time is not less than the stored value, executing a traversal for the next candidate offset position. This pre-set traversal and dynamic update mechanism reduces reliance on manual intervention, making the scheduling process more automated. Furthermore, traversing all candidate offset positions ensures that no potentially optimal scheduling windows are missed.

[0229] In summary, the method provided by the embodiments of the present application provides a soft-pipelining algorithm for compiling loop BBs in AI models. A window scheduling algorithm is used to split the loop BB into two parts, front and back, so that the instructions in the front portion of the next loop are executed synchronously with the instructions in the back portion of the current loop, saving instruction execution time. To find the optimal split position and minimize execution time, the loop BB is replicated three times to obtain multiple BBs and multiple DAGs. Multiple scheduling windows are then tested on the multiple BBs. The scheduling window is used to select the instructions in the back portion of the first loop BB and the front portion of the second loop BB. The execution time required for the two parts of the instructions to execute synchronously within each scheduling window is calculated based on the data dependencies of the instructions indicated in the multiple DAGs. The scheduling window with the shortest execution time is then selected from the multiple scheduling windows as the final target scheduling window. The split position corresponding to the target scheduling window is the optimal split position. Compiling the loop BB according to the scheduling results from the target scheduling window can improve the compilation efficiency of the loop BB and minimize the execution time of the target code of the compiled target program.

[0230] The following is an exemplary embodiment of the method provided by this application to illustrate the application process of this application. An operator loop core (loop BB) is selected and, after a series of compiler processing, reaches the soft pipelining stage. Its instruction sequence is shown in FIG15 .

[0231] Instruction names are represented by uppercase strings, such as PHI, VLD, and VNEG. Registers are represented by the "%" character followed by a lowercase string or number, such as %1 and %2. Constants are represented directly by numbers. Instructions that output data to registers use "=" to link the output register to the instruction name. Input registers and constants follow the instruction name, separated by a comma. Note that the PHI instruction is a compiler pseudo-instruction used to represent code as a static single assignment and does not participate in window scheduling.

[0232] As shown in Figure 16, the original loop BB is expanded into a TripleBB. During the expansion, the used registers must be updated synchronously. Specifically, the first and second instructions in Figure 15 (the PHI instructions are not copied) and the remaining nine instructions are copied three times, resulting in the 29 instructions shown in Figure 16 (two PHI instructions plus 3 × 9 loop instructions).

[0233] In the TripleBB sequence shown in Figure 16, data is passed between instructions and between instructions and memory via registers. Data transfer between instructions is represented by a directed acyclic graph. The corresponding TripleBB TripleDAG is shown in Figure 17.

[0234] In Figure 17, the instruction sequence is converted into nodes in chronological order, with the node numbers corresponding to the input order. A directed edge is added between instructions that transfer data, with its weight representing the number of delays in the data transfer. For example, the weight of the directed edge between nodes 0 and 2 is 1, indicating that the instruction corresponding to node 2 must be issued at least one beat after the instruction corresponding to node 0. The directed edge between nodes represents the data transfer from the source node to the destination node in this loop. In the following description, nodes and instructions can be considered equivalent, with a one-to-one correspondence between the two.

[0235] Next, we use a heuristic algorithm to calculate the set of window offsets. Based on the heuristic algorithm described above, assuming M = 10 and the total number of instructions in the current loop BB is 11, we can calculate the scheduling window offset step size to be 2. Therefore, the set of scheduling window offset positions is {0, 2, 4}.

[0236] Taking the node offset position 4 as an example, the instruction sequence with an offset position of 4 and a scheduling window length of 9 is intercepted from Figure 16. The obtained scheduling window includes the instruction sequence shown in Figure 18 (the first two PHI instructions do not participate in the window scheduling, so when the offset position is 4, the first instruction in the corresponding scheduling window is instruction 7).

[0237] The instructions in the scheduling window shown in Figure 18 are table-scheduled. The resulting instruction sequence is shown in Figure 19, where the order of multiple instructions has changed:

[0238] Next, TripleDAG analyzes the instruction sequence (shown in Figure 19) after scheduling (the result of table scheduling). For example, VADDS_f32 depends on the VEXP_f32 instruction, which is issued on beat 5, with a relative latency of 10 beats. Therefore, the earliest possible time for VADDS_f32 to be issued is beat 15. Since the current time is beat 16, it can be issued. Resource conflicts with other scheduled instructions are then determined, ultimately determining its target time for issuance is beat 16. At this point, all instructions have been analyzed, so the target time for the instruction sequence is beat 17.

[0239] Next, we determine the pause time of the instruction sequence. Using VADDS_f32 as an example, according to the Stall Cycle calculation formula, Stall Cycle = 16 + 3 - 16 - 0 = 3 beats. At this point, all instructions have been analyzed, and the final pause time is 3 beats. Therefore, the final II is 17 + 3 = 20 beats, corresponding to an offset of 4. The detailed scheduling results are shown in Figure 20.

[0240] Similarly, when the offset position of the scheduling window is 0 and 2, the II obtained are 22 beats and 15 beats respectively. It can be seen that the II when the offset position is 2 is the shortest. Therefore, the scheduling result when the offset position is 2 is taken as the final scheduling result of the window scheduling.

[0241] Finally, based on the scheduling results, the soft pipeline instruction expander provided by the compiler generates the prologue, kernel and epilogue parts.

[0242] Figure 21 shows the kernel instructions. Note that the soft pipeline instruction expander has updated the PHI instructions based on the code semantics, while other instructions remain consistent with the previously scheduled results.

[0243] As an example, we use Swish, a common operator in neural networks, to analyze in detail the application effects of the method provided in this application. To improve instruction parallelism, the core loop of Swish was unrolled eight times in advance. The following compares the effects of using modulo scheduling, DoubleBB window scheduling, and the method of this application. The specific test parameter settings are shown in Table 1 in Figure 22.

[0244] Under the above test parameters, each algorithm was executed 5 times and the average time consumed was calculated. The results are shown in Table 2 in Figure 23.

[0245] As can be seen from the above results, on the AI ​​accelerator, the modular scheduling algorithm experienced a search failure and timeout after 8 swish operator expansions, resulting in scheduling failure. DoubleBB window scheduling requires traversing all offset positions and has a high algorithmic complexity, resulting in a runtime of 1.44 seconds. In contrast, the proposed method took 0.38 seconds, reducing compilation time by 73.6%. Both DoubleBB window scheduling and the proposed method searched for 50 beats of II, resulting in consistent performance in the generated code.

[0246] In addition, the large-scale test results of local projects are basically the same. Compared with DoubleBB window scheduling, the compilation time of the method of this application can be reduced by 60% to 80%, and the core loop execution performance is slightly reduced by less than 5%.

[0247] Therefore, the method of the present application can solve the problem of module scheduling failure in complex compilation scenarios; at the same time, compared with classic window scheduling, it can significantly reduce compilation time while ensuring that code performance remains basically unchanged.

[0248] FIG24 shows a block diagram of a compiling device provided by an exemplary embodiment of the present application, the device comprising:

[0249] Loop module 2401 is used to loop-unroll an instruction sequence in a loop basic block BB to generate a multiple BB and a multiple directed acyclic graph (DAG) corresponding to the multiple BB; the multiple BB includes an instruction sequence that loops at least three times; the multiple DAG is used to indicate data dependencies between instructions in the multiple BB;

[0250] Scheduling module 2402 is used to perform window scheduling based on multiple BBs, determine a target scheduling window, and determine the scheduling result corresponding to the target scheduling window. Window scheduling is used to split the instruction sequence in the loop BB into two parts based on the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop. The target scheduling window is a scheduling window whose execution time meets the time condition. The execution time is the time required to execute the instructions in the window, calculated based on the data dependencies in the multiple DAGs.

[0251] The compiling module 2403 is used to compile and obtain the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0252] In an optional embodiment, the scheduling module 2402 is used to determine a candidate offset position based on multiple BBs and traverse each candidate offset position; determine a candidate scheduling window corresponding to the traversed candidate offset position; the candidate scheduling window selects a window instruction sequence in the multiple BBs, and the window instruction sequence includes the second part of the instruction sequence in the first loop and the first part of the instruction sequence in the second loop in the multiple BBs; the second part of the instruction sequence and the first part of the instruction sequence are sequentially connected in the multiple BBs; use a table scheduling algorithm to schedule the window instruction sequence in the candidate scheduling window to obtain a scheduling result corresponding to the candidate scheduling window; calculate the execution time corresponding to the candidate scheduling window based on the scheduling result and the multiple DAG; when the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as the new stored value.

[0253] In an optional embodiment, the scheduling module 2402 is configured to execute a traversal of the next candidate offset position when the execution time is not less than the stored value.

[0254] In an optional embodiment, the scheduling module 2402 is used to calculate the target launch time corresponding to the candidate scheduling window based on the scheduling results; calculate the target pause time corresponding to the candidate scheduling window based on the scheduling results and multiple DAGs; and determine the execution time corresponding to the candidate scheduling window by combining the target launch time and the target pause time.

[0255] In an optional embodiment, the scheduling module 2402 is configured to determine the emission time of each instruction in the scheduling result, and determine the target emission time corresponding to the candidate scheduling window based on the emission time of each instruction.

[0256] In an optional embodiment, the scheduling module 2402 is used to obtain the i-th instruction from the scheduling result port, where i is a positive integer; when the i-th instruction is allowed to be issued at the current time and there is no resource conflict between the i-th instruction and the scheduled instructions, the current time is determined to be the issuance time of the i-th instruction.

[0257] In an optional embodiment, the scheduling module 2402 is used to update the current time when the i-th instruction is not allowed to be issued at the current time, or when there is a resource conflict between the i-th instruction and the scheduled instruction; when i is not equal to n, set i equal to i+1, and return to the step of obtaining the i-th instruction from the scheduling result and continue execution, where n is the number of all instructions in the scheduling result.

[0258] In an optional embodiment, the scheduling module 2402 is configured to traverse all instructions in the scheduling result and obtain the i-th instruction from the traversed scheduling result, where i is a positive integer; if the i-th instruction has a pause time corresponding to it and the pause time is greater than the target pause time, determine the pause time as a new target pause time; if i is not equal to n, set i to i+1, where n is the number of all instructions;

[0259] The pause time is calculated based on the data dependency corresponding to the i-th instruction in the multi-DAG.

[0260] In an optional embodiment, the scheduling module 2402 is used to determine the delay time of the i-th instruction, where the delay time is the delay time required for the data output by the i-th instruction to be input to the x-th instruction; and determine the pause time corresponding to the i-th instruction based on the target emission time, the emission time and delay time of the i-th instruction, and the emission time of the x-th instruction.

[0261] In an optional embodiment, the i-th instruction has a data dependency relationship with the x-th instruction, where x is a positive integer;

[0262] Scheduling module 2402 is configured to calculate the sum of the emission time of the ith instruction and the delay time to obtain a first value; the delay time is the delay time required for the data output by the ith instruction to be input to the xth instruction; calculate the difference between the first value and the maximum emission time to obtain a second value; and calculate the difference between the second value and the emission time of the xth instruction to obtain a pause time corresponding to the ith instruction.

[0263] In an optional embodiment, the loop BB includes instruction 1 and instruction 2, and the multiple BB includes: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2 obtained by copying the loop BB; in the multiple DAG, it is indicated that: second instruction 1 depends on first instruction 2, and third instruction 1 depends on second instruction 2; and the candidate scheduling window includes second instruction 1 and second instruction 2.

[0264] The scheduling module 2402 is configured to determine, when the i-th instruction is the second instruction 2, that the second instruction 2 has a data dependency relationship with the second instruction 1 according to the indication in the multiple DAG that the third instruction 1 depends on the second instruction 2.

[0265] In an optional embodiment, the scheduling module 2402 is configured to determine an offset step size of the scheduling window according to the total number of instructions in the loop BB; and determine a candidate offset position according to the offset step size.

[0266] In an optional embodiment, the scheduling module 2402 is configured to obtain a plurality of preset number ranges, wherein the plurality of preset number ranges correspond to a plurality of offset step sizes, and the plurality of offset step sizes are increased in sequence;

[0267] A target quantity range for the total number of instructions is determined from a plurality of preset quantity ranges, and an offset step corresponding to the target quantity range is used as an offset step of the scheduling window.

[0268] In an optional embodiment, the scheduling module 2402 is used to determine the offset step size as the first step size when the total number of instructions is less than or equal to the first value; determine the offset step size as the second step size when the total number of instructions is greater than the first value and less than or equal to the second value; determine the offset step size as the third step size when the total number of instructions is greater than the second value and less than or equal to the third value; determine the offset step size as the fourth step size when the total number of instructions is greater than the third value and less than or equal to the fourth value; and determine the offset step size as the fifth step size when the total number of instructions is greater than the fourth value; wherein the first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step size, the second step size, the third step size, the fourth step size and the fifth step size increase in sequence.

[0269] FIG25 shows a block diagram of a computer device 2100 according to an exemplary embodiment of the present application. Computer device 2100 may be a portable mobile terminal, such as a smartphone, tablet computer, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop computer, or desktop computer. Computer device 2100 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other similar names.

[0270] Typically, the computer device 2100 includes a processor 2101 and a memory 2102 .

[0271] The processor 2101 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 2101 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 2101 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 2101 may be integrated with a GPU (Graphics Processing Unit, video encoder), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 2101 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0272] The memory 2102 may include one or more computer-readable storage media, which may be non-transitory. The memory 2102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 2102 is used to store at least one instruction, which is used to be executed by the processor 2101 to implement the compilation method provided in the method embodiment of the present application.

[0273] In some embodiments, computer device 2100 may optionally include a peripheral device interface 2103 and at least one peripheral device. Processor 2101, memory 2102, and peripheral device interface 2103 may be connected via a bus or signal lines. Each peripheral device may be connected to peripheral device interface 2103 via a bus, signal lines, or circuit boards. For example, the peripheral device may include at least one of a radio frequency circuit 2104, a display screen 2105, a camera assembly 2106, an audio circuit 2107, and a power supply 2108.

[0274] The peripheral device interface 2103 can be used to connect at least one I / O (Input / Output)-related peripheral device to the processor 2101 and the memory 2102. In some embodiments, the processor 2101, the memory 2102, and the peripheral device interface 2103 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 2101, the memory 2102, and the peripheral device interface 2103 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0275] The RF circuit 2104 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 2104 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 2104 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals. Optionally, the RF circuit 2104 includes an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The RF circuit 2104 can communicate with other terminals via at least one wireless communication protocol. Such wireless communication protocols include, but are not limited to, the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 2104 may also include circuitry related to Near Field Communication (NFC), which is not limited in this application.

[0276] The display screen 2105 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 2105 is a touch screen display, the display screen 2105 also has the ability to collect touch signals on the surface or above the surface of the display screen 2105. The touch signal can be input as a control signal to the processor 2101 for processing. In this case, the display screen 2105 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, there can be one display screen 2105, which is set on the front panel of the computer device 2100; in other embodiments, there can be at least two display screens 2105, which are respectively set on different surfaces of the computer device 2100 or in a folding design; in other embodiments, the display screen 2105 can be a flexible display screen, which is set on the curved surface or folding surface of the computer device 2100. Even more, the display screen 2105 can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 2105 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0277] The camera assembly 2106 is used to capture images or videos. Optionally, the camera assembly 2106 includes a front camera and a rear camera. Typically, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 2106 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0278] The audio circuit 2107 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals that are input into the processor 2101 for processing, or input into the radio frequency circuit 2104 to achieve voice communication. For the purpose of stereo sound collection or noise reduction, there may be multiple microphones, each located in different parts of the computer device 2100. The microphone may also be an array microphone or an omnidirectional collection microphone. The speaker is used to convert electrical signals from the processor 2101 or the radio frequency circuit 2104 into sound waves. The speaker may be a traditional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert electrical signals into sound waves audible to humans, but also convert electrical signals into sound waves inaudible to humans for purposes such as distance measurement. In some embodiments, the audio circuit 2107 may also include a headphone jack.

[0279] Power supply 2108 is used to power various components in computer device 2100. Power supply 2108 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 2108 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, while a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be configured to support fast charging technology.

[0280] In some embodiments, the computer device 2100 further includes one or more sensors 2109 , including but not limited to an acceleration sensor 2110 , a gyroscope sensor 2111 , a pressure sensor 2112 , an optical sensor 2113 , and a proximity sensor 2114 .

[0281] The accelerometer 2110 can detect the magnitude of acceleration along the three coordinate axes of the coordinate system established by the computer device 2100. For example, the accelerometer 2110 can be used to detect the components of gravity acceleration along the three coordinate axes. The processor 2101 can control the display screen 2105 to display the user interface in a landscape or portrait view based on the gravity acceleration signal collected by the accelerometer 2110. The accelerometer 2110 can also be used to collect game or user motion data.

[0282] The gyroscope sensor 2111 can detect the orientation and rotation angle of the computer device 2100. It can also work with the accelerometer 2110 to collect 3D motions of the user on the computer device 2100. Based on the data collected by the gyroscope sensor 2111, the processor 2101 can implement the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0283] The pressure sensor 2112 can be installed on the side frame of the computer device 2100 and / or below the display screen 2105. When the pressure sensor 2112 is installed on the side frame of the computer device 2100, it can detect the user's grip signal of the computer device 2100. The processor 2101 can perform left-hand or right-hand recognition or shortcut operations based on the grip signal collected by the pressure sensor 2112. When the pressure sensor 2112 is installed below the display screen 2105, the processor 2101 controls the operational controls on the UI interface based on the user's pressure operation on the display screen 2105. The operational controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.

[0284] Optical sensor 2113 is used to detect ambient light intensity. In one embodiment, processor 2101 can control the display brightness of display screen 2105 based on the ambient light intensity detected by optical sensor 2113. For example, when the ambient light intensity is high, the display brightness of display screen 2105 is increased; when the ambient light intensity is low, the display brightness of display screen 2105 is decreased. In another embodiment, processor 2101 can also dynamically adjust the shooting parameters of camera assembly 2106 based on the ambient light intensity detected by optical sensor 2113.

[0285] Proximity sensor 2114, also known as a distance sensor, is typically located on the front panel of computer device 2100. Proximity sensor 2114 is used to detect the distance between the user and the front of computer device 2100. In one embodiment, when proximity sensor 2114 detects that the distance between the user and the front of computer device 2100 is gradually decreasing, processor 2101 controls display screen 2105 to switch from a screen-on state to a screen-off state. When proximity sensor 2114 detects that the distance between the user and the front of computer device 2100 is gradually increasing, processor 2101 controls display screen 2105 to switch from a screen-off state to a screen-on state.

[0286] Those skilled in the art will understand that the structure shown in FIG. 25 does not constitute a limitation on the computer device 2100 , and may include more or fewer components than shown, or combine certain components, or adopt a different component arrangement.

[0287] The present application also provides a computer-readable storage medium, wherein the storage medium stores at least one instruction, at least one program, code set, or instruction set, and the at least one instruction, at least one program, code set, or instruction set is loaded and executed by a processor to implement the compilation method provided by the above method embodiment. The present application provides a computer program product or computer program, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the compilation method provided by the above method embodiment.

[0288] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0289] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0290] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0291] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A compilation method, characterized in that: Executed by a computer device, the method includes: Loop-unrolling an instruction sequence in a loop basic block BB to generate a multiple BB and a multiple directed acyclic graph DAG corresponding to the multiple BB; the multiple BB includes the instruction sequence looped at least three times, and the multiple DAG is used to indicate data dependencies between instructions in the multiple BB; Window scheduling is performed based on the multiple BBs, and a target scheduling window and a scheduling result corresponding to the target scheduling window are determined; the window scheduling is used to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required to execute the instructions in the window calculated based on the data dependency relationship in the multiple DAGs; and According to the scheduling result corresponding to the target scheduling window, the target code of the loop BB in the target program is compiled.

2. The method according to claim 1, characterized in that The performing window scheduling based on the multiple BBs and determining a target scheduling window includes: Determine a candidate offset position based on the multiple BB, traverse each candidate offset position, and determine a candidate scheduling window corresponding to the traversed candidate offset position; select a window instruction sequence from the candidate scheduling window in the multiple BB, the window instruction sequence including the second portion of the instruction sequence in the first cycle and the first portion of the instruction sequence in the second cycle in the multiple BB; the second portion of the instruction sequence and the first portion of the instruction sequence are sequentially connected in the multiple BB; Schedule the window instruction sequence in the candidate scheduling window using a table scheduling algorithm to obtain a scheduling result corresponding to the candidate scheduling window; Calculating the execution time corresponding to the candidate scheduling window according to the scheduling result and the multiple DAGs; and In a case where the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as a new stored value.

3. The method according to claim 2, characterized in that The method further comprises: When the execution time is not less than the stored value, a traversal is performed for the next candidate offset position.

4. The method according to claim 2, characterized in that The calculating the execution time corresponding to the candidate scheduling window according to the scheduling result and the multiple DAGs includes: Calculating a target transmission time corresponding to the candidate scheduling window according to the scheduling result; Calculating a target pause time corresponding to the candidate scheduling window according to the scheduling result and the multiple DAGs; and An execution time corresponding to the candidate scheduling window is determined according to the target transmission time and the target pause time.

5. The method according to claim 4, characterized in that Calculating the target transmission time corresponding to the candidate scheduling window according to the scheduling result includes: Determine the emission time of each instruction in the scheduling result, and determine the target emission time corresponding to the candidate scheduling window according to the emission time of each instruction.

6. The method according to claim 5, characterized in that Determining the emission time of each instruction in the scheduling result includes: Obtaining the i-th instruction from the scheduling result, where i is a positive integer; and When the current time allows the issuance of the i-th instruction and there is no resource conflict between the i-th instruction and scheduled instructions, the current time is determined as the issuance time of the i-th instruction.

7. The method according to claim 6, characterized in that The method further comprises: If the current time does not allow the issuance of the i-th instruction, or if the i-th instruction conflicts with a scheduled instruction, updating the current time; and If i is not equal to n, set i to i+1, and return to the step of obtaining the i-th instruction from the scheduling result and continue execution, where n is the number of all instructions in the scheduling result.

8. The method according to claim 4, characterized in that The calculating, according to the scheduling result and the multiple DAGs, a target pause time corresponding to the candidate scheduling window includes: Traverse all instructions in the scheduling result, and obtain the i-th instruction from the traversed scheduling result, where i is a positive integer; If the i-th instruction corresponds to a pause time and the pause time is greater than the target pause time, the pause time is determined as the new target pause time; If i is not equal to n, let i be equal to i+1, where n is the number of all instructions; and The pause time is calculated based on the data dependency corresponding to the i-th instruction in the multiple DAG.

9. The method according to claim 8, characterized in that The i-th instruction has a data dependency relationship with the x-th instruction, where x is a positive integer; and the method further includes: Determine a delay time of the i-th instruction, where the delay time is a delay time required for data output from the i-th instruction to be input to the x-th instruction; The pause time corresponding to the i-th instruction is determined according to the target emission time, the emission time and delay time of the i-th instruction, and the emission time of the x-th instruction.

10. The method according to claim 9, characterized in that The loop BB includes instruction 1 and instruction 2, and the multiple BB includes: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2 obtained by copying the loop BB; in the multiple DAG, it is indicated that: the second instruction 1 depends on the first instruction 2, and the third instruction 1 depends on the second instruction 2; the candidate scheduling window includes the second instruction 1 and the second instruction 2; The method further comprises: In a case where the i-th instruction is the second instruction two, according to the indication in the multiple DAG that the third instruction one depends on the second instruction two, it is determined that the second instruction two has the data dependency relationship with the second instruction one.

11. The method according to any one of claims 2 to 10, characterized in that: The method further comprises: Determining the offset step size of the scheduling window according to the total number of instructions in the loop BB; and The candidate offset position is determined according to the offset step size.

12. The method according to claim 11, characterized in that Determining the offset step size of the scheduling window according to the total number of instructions in the loop BB includes: Acquire multiple preset quantity ranges, wherein the multiple preset quantity ranges correspond to multiple offset step sizes one by one, and the multiple offset step sizes increase in sequence; A target quantity range in which the total number of instructions is located is determined from the multiple preset quantity ranges, and an offset step corresponding to the target quantity range is used as an offset step of the scheduling window.

13. A compiling device, characterized in that: The device comprises: a loop module, configured to loop-unroll an instruction sequence in a loop basic block (BB) to generate a multiple BB and a multiple directed acyclic graph (DAG) corresponding to the multiple BB; the multiple BB includes the instruction sequence looped at least three times; and the multiple DAG indicates data dependencies between instructions in the multiple BB; a scheduling module configured to perform window scheduling based on the multiple BBs, determine a target scheduling window, and determine a scheduling result corresponding to the target scheduling window; the window scheduling is configured to divide the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time satisfies a time condition, and the execution time is the time required to execute instructions within the window, calculated based on data dependencies in the multiple DAGs; and The compiling module is used to compile the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

14. A computer device, characterized in that: The computer device includes: a processor and a memory, the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the compilation method according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the compilation method according to any one of claims 1 to 12.

16. A computer program product, characterized in that The computer program product stores a computer program, and the computer program is loaded and executed by a processor to implement the compilation method according to any one of claims 1 to 12.

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