Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device includes a silicon carbide substrate having: a first main surface; a second main surface opposite the first main surface; and, in a plan view perpendicular to the first main surface, an active region and a terminus region surrounding the active region. The silicon carbide substrate includes: a first semiconductor region having a first conductivity type; and a plurality of second semiconductor regions provided in the first semiconductor region and having a second conductivity type. The plurality of second semiconductor regions: extend along a first axis parallel to the first main surface, in the active region and the terminus region; and extend along a second axis parallel to the first main surface and perpendicular to the first axis. The second semiconductor regions each include: a first region in the active region; and a second region in the terminus region. The first width of the first region along the first axis is narrower than the second width of the second region along the first axis.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2024-030928 filed on March 1, 2024, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] Conventionally, silicon carbide semiconductor devices having a superjunction structure have been disclosed.

[0004] International Publication No. 2022 / 118976

[0005] T. Masuda, et al., "Edge termination design with strong process robustness for 1.2 kV-class 4H-SiC super junction V-groove MOSFETs", Proc. 32nd Int. Symp. Power Semiconductor Devices and ICs (ISPSD), pp. 166-169, Sep. 2020.

[0006] A silicon carbide semiconductor device according to the present disclosure comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, the silicon carbide substrate having a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, the plurality of second semiconductor regions being aligned in the active region and the termination region along a first axis parallel to the first main surface and extending along a second axis parallel to the first main surface and perpendicular to the first axis, the second semiconductor region having a first region in the active region and a second region in the termination region, and a first width of the first region along the first axis being narrower than a second width of the second region along the first axis.

[0007] FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device according to an embodiment. FIG. 3 is a diagram showing the configuration of a p-type region near the boundary between the active region and a termination region of the silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view showing the configuration of the termination region of the silicon carbide semiconductor device according to an embodiment. FIG. 6 is a cross-sectional view (part 1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIG. 7 is a cross-sectional view (part 2) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIG. 8 is a cross-sectional view (part 3) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0008] [Problem to be Solved by the Present Disclosure] A silicon carbide semiconductor device having a superjunction structure includes an active region and a termination region surrounding the active region. The active region and the termination region are provided with a parallel structure in which p-pillars and n-pillars are alternately arranged. In a silicon carbide semiconductor device having a superjunction structure, the parallel structure is uniformly formed in the active region and the termination region surrounding the active region. This makes it difficult to achieve a difference in breakdown voltage between the active region and the termination region.

[0009] An object of the present disclosure is to provide a silicon carbide semiconductor device in which the breakdown voltage of the active region can be made lower than the breakdown voltage of the termination region.

[0010] [Advantages of the Present Disclosure] According to the present disclosure, the breakdown voltage of the active region can be made lower than the breakdown voltage of the termination region.

[0011] The embodiments for carrying out the invention are described below.

[0012] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be assigned the same reference numerals, and the same description will not be repeated. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of the silicon carbide semiconductor device. The XY plane view is referred to as a plan view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the −Z direction may be referred to as downward, lower side, or bottom.

[0013] [1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region. The silicon carbide substrate includes a first semiconductor region having a first conductivity type and a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, the plurality of second semiconductor regions being aligned within the active region and the termination region along a first axis parallel to the first main surface and extending along a second axis parallel to the first main surface and perpendicular to the first axis. The second semiconductor region includes a first region in the active region and a second region in the termination region, and a first width of the first region along the first axis is narrower than a second width of the second region along the first axis. In this case, the breakdown voltage of the active region can be made lower than that of the termination region. This allows leakage current during avalanche breakdown to be evenly distributed in the active region. As a result, the avalanche resistance can be improved.

[0014] [2] In [1], the second semiconductor region may have a third region between the first region and the second region, and a third width of the third region along the first axis may increase from the first region toward the second region. In this case, electric field concentration at the boundary between the first region and the second region is easily reduced.

[0015] [3] In [2], the length of the third region along the second axis may be greater than twice the difference between the second width and the first width, which makes it easier to reduce electric field concentration at the boundary between the first and second regions.

[0016] [4] In any of [1] to [3], the second semiconductor regions may be arranged at a constant pitch along the first axis. In this case, leakage current during avalanche breakdown is more likely to be uniformly distributed in the active region.

[0017] [5] In any one of [1] to [4], the silicon carbide substrate may have a third semiconductor region having the second conductivity type, the third semiconductor region being provided in the active region and the termination region and constituting the first main surface, and the second semiconductor regions may be electrically connected to the third semiconductor region. In this case, a p-type region serves as a source potential, thereby reducing feedback capacitance between the gate electrode and the drain electrode.

[0018] [Details of Embodiments of the Present Disclosure] [Configuration of Silicon Carbide Semiconductor Device] The embodiments of the present disclosure relate to a so-called vertical MOS (Metal Oxide Semiconductor) field effect transistor (FET) using silicon carbide. The MOS FET is an example of a silicon carbide semiconductor device.

[0019] FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device according to an embodiment. FIG. 3 is a diagram showing the configuration of a p-type region near the boundary between the active region and a termination region of the silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing the configuration of the active region of the silicon carbide semiconductor device according to an embodiment. FIG. 5 is a cross-sectional view showing the configuration of the termination region of the silicon carbide semiconductor device according to an embodiment. FIG. 2 corresponds to region II in FIG. 1. FIG. 3 corresponds to region III in FIG. 1. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 corresponds to a cross-sectional view taken along line V-V in FIG. 1.

[0020] As shown in Figures 1 to 5, the silicon carbide semiconductor device 100 according to the embodiment has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a barrier metal film 84, a source electrode 60, and a drain electrode 70.

[0021] Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1. First main surface 1 and second main surface 2 are parallel to the XY plane, and first main surface 1 is in the +Z direction when viewed from second main surface 2. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40. Silicon carbide epitaxial layer 40 includes first main surface 1. Silicon carbide single crystal substrate 50 includes second main surface 2. Silicon carbide epitaxial layer 40 is on silicon carbide single crystal substrate 50. Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 include hexagonal silicon carbide of polytype 4H, for example. Silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has n-type conductivity (first conductivity type).

[0022] Silicon carbide substrate 10 has an active region 110 and a termination region 120. Active region 110 has, for example, a rectangular shape with rounded corners in a plan view perpendicular to first main surface 1. Active region 110 may also have a square shape with rounded corners in a plan view. Termination region 120 surrounds active region 110 in a plan view. Termination region 120 is provided around active region 110 in a plan view.

[0023] The silicon carbide epitaxial layer 40 has a drift region 11 , a body region 12 , a source region 13 , a current spreading region 14 , a p-type region 16 for superjunction, a contact region 18 , and a p-type connection region 19 .

[0024] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50. Drift region 11 is an example of a first semiconductor region.

[0025] The current spreading region 14 contains n-type impurities such as phosphorus and has n-type conductivity. The current spreading region 14 is provided on the drift region 11. The lower end surface of the current spreading region 14 contacts the upper end surface of the drift region 11.

[0026] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity (second conductivity type). The body region 12 is located within the active region 110. The body region 12 is provided on the current spreading region 14. The lower end surface of the body region 12 contacts the upper end surface of the current spreading region 14.

[0027] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is located within the active region 110. The source region 13 is provided on the body region 12. The lower end surface of the source region 13 contacts the upper end surface of the body region 12. The source region 13 includes the first main surface 1.

[0028] The first main surface 1 is provided with a plurality of gate trenches 5 defined by side surfaces 3 and a bottom surface 4. The gate trenches 5 are provided in the active region 110. The gate trenches 5 extend, for example, along the X-axis. The plurality of gate trenches 5 are provided at regular intervals (first pitch P1) along the Y-axis. The side surfaces 3 penetrate the source region 13, the body region 12, the current spreading region 14, and part of the drift region 11, and reach the drift region 11. The bottom surface 4 is continuous with the side surfaces 3. The bottom surface 4 is located in the drift region 11. The bottom surface 4 is, for example, parallel to the first main surface 1 and the second main surface 2. The side surfaces 3 are, for example, inclined with respect to a plane including the bottom surface 4.

[0029] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 is located within the active region 110. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 includes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the Y axis. The contact regions 18 and the source regions 13 may be alternately provided along the X axis between two gate trenches 5 adjacent to each other along the Y axis. The contact region 18 may be provided in the termination region 120. The contact region 18 is an example of a third semiconductor region.

[0030] The p-type region 16 contains p-type impurities such as aluminum and has p-type conductivity. The p-type region 16 is located in the active region 110 and the termination region 120. The p-type region 16 is located in the drift region 11. The p-type regions 16 extend along the X-axis and are aligned along the Y-axis. The p-type regions 16 extend parallel to the gate trench 5. The p-type regions 16 may be aligned at a constant pitch along the Y-axis. In this case, leakage current during avalanche breakdown is more likely to be uniformly distributed in the active region 110. The p-type regions 16 may be aligned in a stripe pattern. The p-type regions 16 may extend along the Y-axis and be aligned along the X-axis. The p-type regions 16 may extend perpendicular to the gate trench 5. The effective concentration of the p-type impurities in the p-type region 16 is, for example, 1×10 １６ cm －３ 5x10 or more １７ cm －３ The p-type region 16 is an example of a second semiconductor region. The Y-axis is an example of a first axis, and the X-axis is an example of a second axis.

[0031] P-type region 16 includes first region 16 a, second region 16 b, and third region 16 c. First region 16 a is located within active region 110. Second region 16 b and third region 16 c are located within termination region 120. Third region 16 c is located between first region 16 a and second region 16 b.

[0032] The first width W1 of the first region 16a along the Y-axis may be narrower than the second width W2 of the second region 16b along the Y-axis. In this case, the breakdown voltage of the active region 110 can be made lower than the breakdown voltage of the termination region 120. This allows the leakage current during avalanche breakdown to be evenly distributed in the active region 110. As a result, the avalanche breakdown capability can be improved.

[0033] The third width W3 of the third region 16c along the Y axis may increase from the first region 16a toward the second region 16b. In this case, electric field concentration at the boundary between the first region 16a and the second region 16b is easily reduced. The third width W3 may increase continuously from the first region 16a toward the second region 16b.

[0034] The length L3 of the third region 16c along the X-axis may be greater than twice the difference between the second width W2 and the first width W1. That is, the relationship L3 > 2 × (W2 - W1) may be satisfied. In this case, electric field concentration at the boundary between the first region 16a and the second region 16b is easily reduced.

[0035] The p-type region 16 is located between adjacent gate trenches 5 along the Y-axis in a plan view perpendicular to the first main surface 1. The p-type region 16 is farther from the gate trench 5. The p-type region 16 is farther from the gate trench 5 along the Y-axis than the body region 12. The p-type region 16 overlaps the contact region 18 in a plan view perpendicular to the first main surface 1.

[0036] The p-type connection region 19 contains p-type impurities such as aluminum and has p-type conductivity. The p-type connection region 19 is located within the active region 110 and within the termination region 120. The p-type connection region 19 is located between the p-type region 16 and the contact region 18. The lower end surface of the p-type connection region 19 contacts the upper end surface of the p-type region 16. The upper end surface of the p-type connection region 19 contacts the source region 13 and the contact region 18. The p-type connection region 19 electrically connects the p-type region 16 and the contact region 18. In this case, the p-type region 16 is at the source potential, thereby reducing the feedback capacitance between the gate electrode 82 and the drain electrode 70. The effective concentration of the p-type impurity in the p-type connection region 19 is, for example, 1×10 １６ cm －３ 5x10 or more １７ cm －３ The following is the result.

[0037] The p-type connection region 19 is located between adjacent gate trenches 5 along the Y-axis in a plan view perpendicular to the first main surface 1. The p-type connection region 19 is farther from the gate trench 5. The p-type connection region 19 is farther from the gate trench 5 along the Y-axis than the body region 12 is. The p-type connection region 19 overlaps with the p-type region 16 and the contact region 18 in a plan view perpendicular to the first main surface 1. Side surfaces of the p-type connection region 19 contact the drift region 11, the current spreading region 14, and the body region 12. The width of the p-type connection region 19 along the Y-axis may be wider than the width of the p-type region 16 along the Y-axis.

[0038] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 includes, for example, silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0039] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is formed of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is provided inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the X-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap with multiple gate trenches 5.

[0040] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is formed of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0041] Contact holes 90 are provided in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the Y axis. The contact holes 90 are provided so that the gate trench 5 is located between adjacent contact holes 90 along the Y axis. The contact holes 90 extend along the X axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0042] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is formed of a material containing, for example, titanium nitride (TiN).

[0043] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 and a source wiring 62. The contact electrode 61 is provided in the contact hole 90. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is formed of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be formed of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13 and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is formed of a material containing, for example, aluminum.

[0044] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is formed of a material containing nickel silicide, for example. The drain electrode 70 may be formed of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0045] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity. The effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM).

[0046] In the present disclosure, the first width W1, the second width W2, the third width W3, and the length L3 can be measured using, for example, a scanning electron microscope (SEM).

[0047] [Method of Manufacturing Silicon Carbide Semiconductor Device] Next, a method of manufacturing silicon carbide semiconductor device 100 will be described. Figures 6 to 8 are cross-sectional views showing the method of manufacturing silicon carbide semiconductor device 100 according to the embodiment. Figure 7 is a cross-sectional view showing the configuration of active region 110. Figure 8 is a cross-sectional view showing the configuration of termination region 120.

[0048] First, as shown in Fig. 6, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0049] 7 and 8 , ions are implanted into silicon carbide epitaxial layer 40 to form p-type region 16. The ion implantation for forming p-type region 16 involves channeling implantation of p-type impurities such as aluminum. The upper end surface of p-type region 16 is spaced apart from the upper surface of silicon carbide epitaxial layer 40.

[0050] Next, ions are implanted into the silicon carbide epitaxial layer 40 to form the body region 12, source region 13, current diffusion region 14, contact region 18, and p-type connection region 19. The remaining portion of the silicon carbide epitaxial layer 40 becomes the drift region 11. Next, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a barrier metal film 84, a source electrode 60, and a drain electrode 70 are formed (see FIGS. 4 and 5 ).

[0051] In this manner, silicon carbide semiconductor device 100 can be manufactured.

[0052] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0053] REFERENCE SIGNS LIST 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 12 Body region 13 Source region 14 Current diffusion region 16 P-type region 16a First region 16b Second region 16c Third region 18 Contact region 19 P-type connection region 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 90 Contact hole 100 Silicon carbide semiconductor device 110 Active region 120 Termination region L3 Length P1 First pitch W1 First width W2 Second width W3 Third width

Claims

1. A silicon carbide semiconductor device comprising: a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region and a termination region surrounding the active region, wherein the silicon carbide substrate has: a first semiconductor region having a first conductivity type; and a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, wherein the plurality of second semiconductor regions are aligned in the active region and the termination region along a first axis parallel to the first main surface and extend along a second axis parallel to the first main surface and perpendicular to the first axis, wherein the second semiconductor region has a first region in the active region and a second region in the termination region, and a first width of the first region along the first axis is narrower than a second width of the second region along the first axis.

2. The silicon carbide semiconductor device according to claim 1, wherein the second semiconductor region has a third region located between the first region and the second region, and a third width of the third region along the first axis increases from the first region toward the second region.

3. The silicon carbide semiconductor device according to claim 2, wherein a length of said third region along said second axis is greater than twice the value of the difference between said second width and said first width.

4. The silicon carbide semiconductor device according to claim 1, wherein the plurality of second semiconductor regions are provided at a constant pitch along the first axis.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the silicon carbide substrate has a third semiconductor region having the second conductivity type, the third semiconductor region being provided within the active region and the termination region and constituting the first main surface, and the plurality of second semiconductor regions being electrically connected to the third semiconductor region.

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