Semiconductor device

Abstract

This semiconductor device achieves an improvement in gate withstand voltage and a reduction in on resistance. The semiconductor device comprises: first conductivity-type first semiconductor layer and second semiconductor layer; a plurality of second conductivity-type third semiconductor layers; a first conductivity-type fourth semiconductor layer that is interposed between the plurality of third semiconductor layers; a second conductivity-type fifth semiconductor layer that is interposed between the plurality of third semiconductor layers; a first conductivity-type sixth semiconductor layer; a second conductivity-type seventh semiconductor layer that has higher concentration than the third semiconductor layer; a plurality of first trenches that penetrate the fifth semiconductor layer and the sixth semiconductor layer and form a fin structure, the first trenches having bottom corners, in a longitudinal direction, in the third semiconductor layer; a second trench that connects the plurality of first trenches; a gate electrode that is in contact with a gate insulating film formed in the first trench and the second trench and is embedded in the first trench and the second trench; a drain electrode that is connected to the first semiconductor layer; and a source electrode that is connected to the sixth semiconductor layer and the seventh semiconductor layer.

Description

Semiconductor Devices

[0001] The present invention relates to the structure of a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device having a trench-type gate electrode structure.

[0002] In the field of SiC power semiconductors, development is underway on a SiC-MOSFET with an element structure called a "trench MOSFET" in which current flows vertically. However, a high electric field concentrates in one part of the element, which accelerates degradation, making improving durability an important issue.

[0003] As background art in this technical field, there is, for example, a technology such as that disclosed in Patent Document 1. Patent Document 1 discloses "a buried gate type semiconductor device that reduces the gate spacing as much as possible, improves channel density to realize low on-resistance, prevents a decrease in breakdown voltage due to electric field concentration near the bottom surface of the gate, and also achieves both prevention of a decrease in breakdown voltage and good off-state characteristics."

[0004] Furthermore, Patent Document 2 discloses a "MOSFET having a trench formed in a direction perpendicular to a source contact region formed in a stripe shape in a plan view, and having a gate electrode embedded in the trench via an insulating film."

[0005] JP 2004-207289 A JP 2023-45561 A

[0006] In trench MOSFETs in which a fin structure is formed perpendicular to the source contact, as described in Patent Documents 1 and 2, the on-resistance can be reduced by reducing the trench pitch and increasing the trench density. Also, by covering the corners of the trench bottom perpendicular to the source contact with the body layer, the electric field between the drain and gate applied to the gate oxide film at the trench bottom can be alleviated, allowing the device to be used as a high-voltage device.

[0007] However, due to its structure, the gate electrodes embedded in the trenches must be connected across the trenches, which causes an electric field to concentrate on the gate oxide film at the corners of the upper part of the trench, making it more susceptible to dielectric breakdown.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a semiconductor device having a trench gate electrode structure that can achieve both an improvement in gate breakdown voltage and a reduction in on-resistance.

[0009] In order to solve the above problems, the present invention provides a semiconductor device including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a plurality of third semiconductor layers of a second conductivity type formed on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type formed on the second semiconductor layer and sandwiched between the plurality of third semiconductor layers, a fifth semiconductor layer of a second conductivity type formed on the fourth semiconductor layer and sandwiched between the plurality of third semiconductor layers, a sixth semiconductor layer of the first conductivity type formed on the third semiconductor layer and the fifth semiconductor layer, and a sixth semiconductor layer of the first conductivity type formed on the third semiconductor layer and having a higher concentration than the third semiconductor layer. a seventh semiconductor layer of a different conductivity type; first trenches which penetrate the fifth semiconductor layer and the sixth semiconductor layer and form a fin structure, the first trenches being a plurality of trenches with their longitudinal bottom corners located within the third semiconductor layer; second trenches which connect the plurality of first trenches; a gate insulating film formed inside the first trench and the second trench; gate electrodes which are in contact with the gate insulating film and embedded inside the first trench and the second trench; a drain electrode electrically connected to the first semiconductor layer; and a source electrode electrically connected to the sixth semiconductor layer and the seventh semiconductor layer.

[0010] According to the present invention, it is possible to realize a semiconductor device having a trench gate electrode structure that can achieve both an improvement in gate breakdown voltage and a reduction in on-resistance.

[0011] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments.

[0012] 1A is a plan view schematically illustrating a trench structure of a semiconductor device according to a first embodiment of the present invention; １ -X １ 1A. ２ -X ２1A to 1C. A-A' cross-sectional view. A-B ... ３ -X ３ 4A. ４ -X ４ 7A is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention; FIG. 7B is a cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention; FIG. 7C is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention; FIG. 7D is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention; FIG. 7E is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention; ５ -X ５ 9A. A diagram showing a modification of FIG. 7A. A diagram showing a modification of FIG. 7A. A diagram showing a modification of FIG. 7A. A plan view schematically showing the structure of a gate wiring lead-out portion of a semiconductor device according to Example 8 of the present invention. A CC' cross-sectional view of FIG. 9A. A diagram showing a modification of FIG. 9A. A DD' cross-sectional view of FIG. 10A. A diagram showing a schematic cross-sectional structure of a conventional fin-structure trench MOSFET. An EE' cross-sectional view of FIG. 11A. An FF' cross-sectional view of FIG. 11B.

[0013] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and detailed description of overlapping parts will be omitted.

[0014] In the following description, the first conductivity type is assumed to be N-type and the second conductivity type is assumed to be P-type, but this is not limitative and the reverse is also possible.

[0015] First, in order to make the present invention easier to understand, the structure of the above-mentioned conventional semiconductor device and its problems will be described with reference to FIGS. 11A to 11C.

[0016] Fig. 11A is a diagram schematically showing a cross-sectional structure of a conventional fin-structure trench MOSFET, Fig. 11B is a cross-sectional view taken along the line EE' in Fig. 11A, and Fig. 11C is a cross-sectional view taken along the line FF' in Fig. 11B.

[0017] As described above, in a conventional trench MOSFET in which a fin structure is formed in a direction perpendicular to the source contact, as shown in Fig. 11B, the gate electrode 12 embedded in the trench 10 has a structure that connects across the trenches 10. Therefore, an electric field concentrates on the gate insulating film 11 at the corners of the upper part of the trench 10, making it prone to dielectric breakdown.

[0018] Next, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1A to 1E.

[0019] 1A is a plan view schematically showing a trench structure of a semiconductor device 1 according to a first embodiment of the present invention. １ -X １ 1C is a cross-sectional view of the X′ cross section of FIG. ２ -X ２ 1D is a cross-sectional view taken along line AA' in FIGS. 1A to 1C. FIG. 1E is a cross-sectional view taken along line BB' in FIGS. 1A to 1C.

[0020] 1A and 1E, the semiconductor device 1 of this embodiment has a plurality of first trenches (fin-type trenches) 10 that form a fin structure, and second trenches (connection trenches) 18 that are disposed between the first trenches 10 and connect the first trenches 10. A gate insulating film 11 is formed inside the first trenches 10 and the second trenches 18, and a gate electrode (polysilicon film) 12 is embedded in contact with the gate insulating film 11.

[0021] As shown in FIG. 1B , the semiconductor device 1 includes a first semiconductor layer 3 of a first conductivity type that serves as a drain layer, a second semiconductor layer 4 of the first conductivity type that is formed on the first semiconductor layer 3 and serves as a drift layer, a plurality of third semiconductor layers 5 of the second conductivity type that are formed on the second semiconductor layer 4 and serve as a body layer, and a fourth semiconductor layer 6 of the first conductivity type that is formed on the second semiconductor layer 4, is sandwiched between the plurality of third semiconductor layers 5, and serves as a JFET layer.

[0022] As shown in FIG. 1C , the semiconductor device 1 also includes a fifth semiconductor layer 7 of the second conductivity type that is formed on the fourth semiconductor layer 6, is sandwiched between a plurality of third semiconductor layers 5, and serves as a channel layer; a sixth semiconductor layer 8 of the first conductivity type that is formed on the third semiconductor layer 5 and the fifth semiconductor layer 7 and serves as a first source layer; and a seventh semiconductor layer 9 of the second conductivity type that is formed on the third semiconductor layer 5, has a higher concentration than the third semiconductor layer 5, and serves as a body contact layer.

[0023] As shown in FIGS. 1B and 1D , the semiconductor device 1 also includes first trenches (fin-type trenches) 10, which are a plurality of trenches that penetrate the fifth semiconductor layer 7 and the sixth semiconductor layer 8 and form a fin structure, and whose bottom corners in the longitudinal direction are located within the third semiconductor layer 5.

[0024] As shown in FIGS. 1A and 1C, the semiconductor device 1 also includes second trenches (connection trenches) 18 that connect the plurality of first trenches 10 together.

[0025] As shown in FIGS. 1B to 1D , the semiconductor device 1 also includes a gate insulating film 11 formed inside the first trench 10 and the second trench 18, and a gate electrode 12 made of a polysilicon film that is in contact with the gate insulating film 11 and embedded inside the first trench 10 and the second trench 18.

[0026] Each of the first semiconductor layer (drain layer) 3, the second semiconductor layer (drift layer) 4, the third semiconductor layer (body layer) 5, the fourth semiconductor layer (JFET layer) 6, the fifth semiconductor layer (channel layer) 7, the sixth semiconductor layer (first source layer) 8, and the seventh semiconductor layer (body contact layer) 9 described above is formed by implanting N-type impurities or P-type impurities into the semiconductor substrate 2 by ion implantation.

[0027] 1B to 1D, the interlayer insulating film 13 formed on the upper part of the gate electrode 12 is emphasized. However, unlike the conventional fin-structure trench MOSFET shown in FIGS. 11A to 11C, the gate electrode 12 is not formed above the surface of the semiconductor substrate 2, and the upper surface of the gate electrode 12 is substantially flush with the upper surfaces of the sixth semiconductor layer (first source layer) 8 and the seventh semiconductor layer (body contact layer) 9.

[0028] A drain electrode (not shown) is formed on the surface of the first semiconductor layer (drain layer) 3 opposite to the second semiconductor layer (drift layer) 4 side (i.e., the back surface of the semiconductor substrate 2), and is electrically connected to the first semiconductor layer (drain layer) 3.

[0029] An interlayer insulating film 13 is formed on the surface of the semiconductor substrate 2 so as to cover the sixth semiconductor layer (first source layer) 8, the seventh semiconductor layer (body contact layer) 9, the first trench 10, and the second trench 18.

[0030] In the interlayer insulating film 13 , contact holes 14 are formed that penetrate the interlayer insulating film 13 and reach the sixth semiconductor layer (first source layer) 8 and the seventh semiconductor layer (body contact layer) 9 .

[0031] In the contact hole 14, a barrier metal 15 and a contact 16 are buried in this order from the bottom up, and the barrier metal 15 and the contact 16 serve as a source contact, which will be described later.

[0032] A metal film 17 serving as a source electrode is formed on the interlayer insulating film 13. The contact 16 is formed by filling the inside of the contact hole 14 with the metal film 17 when the metal film 17 is formed on the interlayer insulating film 13.

[0033] The metal film (source electrode) 17 is electrically connected to the sixth semiconductor layer (first source layer) 8 and the seventh semiconductor layer (body contact layer) 9 via a barrier metal 15 and a contact 16 which are source contacts.

[0034] The semiconductor device 1 of this embodiment is configured as described above, and by burying the gate electrode 12 in the first trench 10 and the second trench 18, an electric field is less likely to be applied to the corner portions at the top of the trench, thereby improving the gate breakdown voltage.

[0035] This makes it possible to improve the gate breakdown voltage and reduce the on-resistance at the same time in a semiconductor device having a trench gate electrode structure.

[0036] As shown in FIG. 1C , the second trench (connection trench) 18 is located in the third semiconductor layer (body layer) 5 and is not in contact with the fifth semiconductor layer (channel layer) 7 .

[0037] The fifth semiconductor layer (channel layer) 7 is connected to the third semiconductor layer (body layer) 5 on both the left and right sides, which stabilizes the potential of the channel layer and makes it easier to stabilize the device operation.

[0038] Furthermore, since the second trench (connection trench) 18 is covered with the third semiconductor layer (body layer) 5, an electric field is not applied directly from the drain, and even a high-voltage element can operate without any problems.

[0039] In addition, the electric field applied between the gate and source when the element is turned on can be alleviated by depleting the third semiconductor layer (body layer) 5, and the boundary portion between the second trench (connection trench) 18 and the first trench (fin-type trench) 10, where the electric field is likely to concentrate, can also be protected from the electric field.

[0040] Second Embodiment A semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 2A and 2B.

[0041] 2A and 2B are cross-sectional views schematically showing the trench structure of the semiconductor device 1 of this embodiment, and correspond to FIGS. 1B and 1C of Example 1, respectively. Fig. 2A has basically the same configuration as Fig. 1B.

[0042] As shown in FIG. 2B , the semiconductor device 1 of this embodiment differs from that of Example 1 ( FIG. 1C ) in that the second trench (connection trench) 18 is in contact only with layers of the same conductivity type as the third semiconductor layer (body layer) 5.

[0043] In Example 1 ( FIG. 1C ), the second trench 18 is in contact with the third semiconductor layer (body layer) 5 of the second conductivity type and the seventh semiconductor layer (body contact layer) 9 of the second conductivity type, and is also in contact with the sixth semiconductor layer (first source layer) 8 of the first conductivity type.

[0044] On the other hand, in this embodiment ( FIG. 2B ), the second trench 18 is in contact with the third semiconductor layer (body layer) 5 of the second conductivity type and the seventh semiconductor layer (body contact layer) 9 of the second conductivity type, but is not in contact with the sixth semiconductor layer (first source layer) 8 of the first conductivity type.

[0045] The boundary between the second trench (connection trench) 18 and the first trench (fin-type trench) 10 is prone to electric field concentration, raising concerns that a parasitic channel may be formed around the second trench (connection trench) 18; however, because the second trench (connection trench) 18 is in contact only with the same conductive layer as the third semiconductor layer (body layer) 5, a parasitic channel is prevented from being formed, making it easier to achieve stable operation.

[0046] Furthermore, the entire surface of the second trench (connection trench) 18 can be protected from the electric field applied between the gate and source when the element is turned on.

[0047] Third Embodiment A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 3A and 3B.

[0048] 3A and 3B are cross-sectional views schematically showing the trench structure of the semiconductor device 1 of this embodiment, and correspond to FIGS. 1B and 1C of the first embodiment, respectively.

[0049] As shown in FIG. 3B , the semiconductor device 1 of this embodiment differs from that of Example 1 ( FIG. 1C ) in that the second trench (connection trench) 18 is in contact with both the third semiconductor layer (body layer) 5 and the fifth semiconductor layer (channel layer) 7.

[0050] By disposing the second trench (connection trench) 18 in contact with the fifth semiconductor layer (channel layer) 7 , a channel can also be formed in a part of the second trench (connection trench) 18 .

[0051] Furthermore, as shown in FIG. 3A, the longitudinal length of the first trench (fin-type trench) 10 can be shortened compared to Example 1 (FIG. 1B) and Example 2 (FIG. 2A), thereby increasing the cell density and reducing the on-resistance.

[0052] Furthermore, as shown in FIG. 3B, a part of the second trench (connection trench) 18 contacts the third semiconductor layer (body layer) 5, and an electric field protection effect can also be obtained.

[0053] A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 4A to 4C.

[0054] 4A is a plan view schematically showing the trench structure of the semiconductor device 1 of this embodiment. ３ -X ３ 4C is a cross-sectional view of the X′ cross section of FIG. ４ -X ４ 4A to 4C correspond to FIGS. 1A, 1B, and 1C of the first embodiment, respectively.

[0055] As shown in FIG. 4C , the semiconductor device 1 of this embodiment differs from Example 1 ( FIG. 1C ) in that the second trench (connection trench) 18 is in contact with the fifth semiconductor layer (channel layer) 7 and is not in contact with the third semiconductor layer (body layer) 5.

[0056] By disposing the second trench (connection trench) 18 in contact with the fifth semiconductor layer (channel layer) 7, a part of the second trench (connection trench) 18 also functions as a channel.

[0057] Furthermore, as shown in FIG. 4B, the longitudinal length of the first trench (fin trench) 10 can be shortened compared to Example 1 (FIG. 1B) and Example 2 (FIG. 2A), thereby increasing the cell density.

[0058] Furthermore, as shown in FIG. 4A , in a structure in which the spacing between the first trenches (fin trenches) 10 is wider than the connection width between the second trenches (connection trenches) 18 and the first trenches (fin trenches) 10, the channel ratio of the second trenches (connection trenches) 18 increases, and the on-resistance can be reduced.

[0059] A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 5A and 5B.

[0060] 5A and 5B are cross-sectional views schematically showing the trench structure of the semiconductor device 1 of this embodiment, and correspond to FIGS. 4B and 4C of the fourth embodiment, respectively.

[0061] As shown in FIGS. 5A and 5B , in the semiconductor device 1 of this embodiment, the fourth semiconductor layer (JFET layer) is different from that of Example 4 ( FIGS. 4B and 4C ) in that it has a first layer 6 directly below a fifth semiconductor layer (channel layer) 7, and a second layer 6 a formed directly below the first layer 6 and having a width narrower than that of the first layer 6.

[0062] In the structure of Example 4 (FIGS. 4B and 4C), the fourth semiconductor layer (JFET layer) 6 needs to have a certain width in order to form the second trench (connection trench) 18 and ensure the channel width. However, the wider the width of the fourth semiconductor layer (JFET layer) 6, the stronger the electric field between the drain and gate becomes, which raises the concern that dielectric breakdown may become more likely.

[0063] Therefore, in this embodiment (FIGS. 5A and 5B), a first layer 6 for ensuring the channel width and a second layer 6a for electric field protection are provided.

[0064] Sixth Embodiment A semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 6A and 6B.

[0065] 6A and 6B are cross-sectional views schematically showing the trench structure of the semiconductor device 1 of this embodiment, and correspond to FIGS. 4B and 4C of the fourth embodiment, respectively.

[0066] As shown in FIGS. 6A and 6B , in the semiconductor device 1 of this embodiment, the third semiconductor layer (body layer) is arranged by being divided into at least three pieces (reference numerals 5 and 5 a in FIGS. 6A and 6B ), the fourth semiconductor layer (JFET layer) is arranged by being divided into at least two pieces (reference numeral 6 in FIGS. 6A and 6B ), and each of the fourth semiconductor layers (JFET layers) 6 is arranged by being sandwiched between each of the third semiconductor layers (body layers) 5 and 5 a, and the second trench (connection trench) 18 is located in the third semiconductor layer (body layer) 5 a that is located at the center of the third semiconductor layer (body layer) 5 and 5 a that is arranged by being divided into three pieces, and is not in contact with the fifth semiconductor layer (channel layer) 7, which is different from Example 4 ( FIGS. 4B and 4C ).

[0067] The third semiconductor layer (body layer) 5a is formed simultaneously with the third semiconductor layer (body layer) 5, and two seventh semiconductor layers (body contact layers) 9 are formed simultaneously on both sides of the second trench (connection trench) 18 on the third semiconductor layer (body layer) 5a, and the second trench (connection trench) 18 is in contact only with these two seventh semiconductor layers (body contact layers) 9 and the third semiconductor layer (body layer) 5a.

[0068] There is a concern that the channel density may decrease to some extent and the on-resistance may increase by providing the second trench (connection trench) 18. In addition, if the width of the fourth semiconductor layer (JFET layer) 6 is increased to increase the channel density, there is a concern that the electric field applied to the gate insulating film 11 may increase.

[0069] Therefore, in this embodiment, the third semiconductor layer (body layer) 5 is divided into at least three parts, and two third semiconductor layers (body layers) 5 and a third semiconductor layer (body layer) 5a located in the middle thereof are provided, thereby maintaining the electric field protection of the gate insulating film 11, and by providing a second trench (connection trench) 18 in the third semiconductor layer (body layer) 5a, the channel density can be increased efficiently.

[0070] Furthermore, since the second trench (connection trench) 18 is located in the third semiconductor layer (body layer) 5a, the third semiconductor layer (body layer) 5a contacts the fifth semiconductor layer (channel layer) 7, which stabilizes the potential of the third semiconductor layer (body layer) 5a and makes it easier to stabilize device operation.

[0071] Furthermore, although there is no need to cover the upper part of the second trench (connection trench) 18 with a layer of the same conductivity type as the third semiconductor layer (body layer) 5a, covering it with a layer of the same conductivity type can eliminate the parasitic channel of the second trench (connection trench) 18 and can also alleviate the electric field applied to the gate insulating film 11 during on operation.

[0072] A semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIGS. 7A to 8C.

[0073] 7A is a plan view schematically showing the source contact structure of the semiconductor device 1 of this embodiment. ５ -X ５ 8A to 8C are cross-sectional views each showing a modification of FIG. 7A.

[0074] In this embodiment, a specific configuration example of the source contact portion of the semiconductor device 1 described in the first to sixth embodiments will be described.

[0075] For example, as shown in FIGS. 7A and 7B, P + layer 19 and an eighth semiconductor layer (N + layer) 20, and adjacent P + layer 19 and the eighth semiconductor layer (N + The source contact 21 may be formed across the layer 20 .

[0076] Also, as shown in FIG. 8A, P + layer 19 and the eighth semiconductor layer (N + layer) 20 are formed into a fin shape, and the adjacent P + layer 19 and the eighth semiconductor layer (N + The layers 20 may be arranged in a staggered pattern (alternately). + layer 19 and the eighth semiconductor layer (N + A source contact 21 is formed across the silicon dioxide layer 20 .

[0077] Also, as shown in FIG. 8B, one P +Layer 19 is made up of two eighth semiconductor layers (N + layer) 20, + layer 19 and the eighth semiconductor layer (N + layer) 20, and the adjacent P + layer 19 and the eighth semiconductor layer (N + The source contact 21 may be formed across the layer 20 .

[0078] Also, as shown in FIG. 8C, P + The layer 19 is divided into a plurality of P + The eighth semiconductor layer (N + In this case, P + layer 19 and the eighth semiconductor layer (N + A source contact 21 is formed across the silicon dioxide layer 20 .

[0079] Although the seventh semiconductor layer (body contact layer) 9 is not shown in FIG. 7B, + The layer 19 may be the seventh semiconductor layer (body contact layer) 9 .

[0080] That is, the source contact 21 that connects the metal film (source electrode) 17 to the sixth semiconductor layer (first source layer) 8 and the seventh semiconductor layer (body contact layer) 9 is formed in contact with the seventh semiconductor layer (body contact layer) 9 and the sixth semiconductor layer (first source layer) 8, and is formed in contact with the eighth semiconductor layer (N + The layer 20 may be connected to the other layer 20.

[0081] Eighth Embodiment A semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIGS. 9A to 10B.

[0082] Fig. 9A is a plan view schematically showing the structure of the gate wiring lead-out portion of the semiconductor device 1 of this embodiment. Fig. 9B is a cross-sectional view taken along CC' in Fig. 9A. Fig. 10A is a diagram showing a modified example of Fig. 9A. Fig. 10B is a cross-sectional view taken along DD' in Fig. 10A.

[0083] This example describes a specific example of the configuration of the gate lead-out portion of the semiconductor device 1 described in Examples 1 to 6. By embedding the gate electrode in the trench, the electric field at the corner portion of the upper part of the trench can be alleviated, but wiring to the embedded gate electrode is necessary for the device configuration, and an example of such wiring is presented.

[0084] 9A and 9B, a trench 22 for a lead-out wiring 23 is provided, and a contact hole 14 is opened above the lead-out wiring trench 22. Since the gate electrode 12 remains buried, there is no concern about electric field concentration in the wiring portion.

[0085] 10A and 10B , a trench 22 for a lead-out wiring 23 may be provided, and a gate electrode pad (gate electrode lead-out pad 24) for wiring contact may be provided therein for wiring. Although electric field concentration occurs at the corners of the upper part of the trench, the electric field can be somewhat alleviated by covering the upper part of the trench with the third semiconductor layer (body layer) 5.

[0086] The present invention is not limited to the above-described embodiments, but includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations.

[0087] REFERENCE SIGNS LIST 1...Semiconductor device 2...Semiconductor substrate 3...First semiconductor layer (drain layer) 4...Second semiconductor layer (drift layer) 5, 5a...Third semiconductor layer (body layer) 6, 6a...Fourth semiconductor layer (JFET layer) 7...Fifth semiconductor layer (channel layer) 8...Sixth semiconductor layer (first source layer) 9...Seventh semiconductor layer (body contact layer) 10...First trench (fin trench) 11...Gate insulating film 12...Gate electrode (polysilicon film) 13...Interlayer insulating film 14...Contact hole 15...Barrier metal 16...Contact 17...Metal film (source electrode) 18...Second trench (connection trench) 19...P + Layer 20...Eighth semiconductor layer (N + layer) 21...source contact 22...trenches for lead wiring 23...lead wiring 24...gate electrode lead pad 25...P layer (or N layer) 26...N layer (or P layer).

Claims

a fourth semiconductor layer of a first conductivity type formed on the second semiconductor layer and sandwiched between the plurality of third semiconductor layers; a fifth semiconductor layer of a second conductivity type formed on the fourth semiconductor layer and sandwiched between the plurality of third semiconductor layers; a sixth semiconductor layer of a first conductivity type formed on the third semiconductor layer and the fifth semiconductor layer; a seventh semiconductor layer of a second conductivity type formed on the third semiconductor layer and having a higher concentration than the third semiconductor layer; a plurality of first trenches that penetrate the fifth semiconductor layer and the sixth semiconductor layer and form a fin structure, the bottom corners of which in the longitudinal direction are within the third semiconductor layer; a second trench connecting the plurality of first trenches; and a gate insulating film formed inside the first trench and the second trench. a gate electrode in contact with the gate insulating film and embedded inside the first trench and the second trench; a drain electrode electrically connected to the first semiconductor layer; and a source electrode electrically connected to the sixth semiconductor layer and the seventh semiconductor layer.

2. A semiconductor device according to claim 1, wherein the second trench is located in the third semiconductor layer and is not in contact with the fifth semiconductor layer.

3. A semiconductor device according to claim 2, wherein the second trench is in contact only with a layer of the same conductivity type as the third semiconductor layer.

4. A semiconductor device according to claim 1, wherein the second trench is in contact with both the third semiconductor layer and the fifth semiconductor layer.

5. A semiconductor device according to claim 1, wherein the second trench is in contact with the fifth semiconductor layer and is not in contact with the third semiconductor layer.

6. A semiconductor device according to claim 5, wherein the fourth semiconductor layer has a first layer below the fifth semiconductor layer, and a second layer formed below the first layer and having a width narrower than that of the first layer.

7. A semiconductor device according to claim 1, wherein the third semiconductor layer is divided into at least three parts, the fourth semiconductor layer is divided into at least two parts, and each of the fourth semiconductor layers is sandwiched between two of the third semiconductor layers, and the second trench is located in the third semiconductor layer located at the center of the three third semiconductor layers, and is not in contact with the fifth semiconductor layer.

8. A semiconductor device according to claim 1, wherein the upper surface of the gate electrode is substantially flush with the upper surfaces of the sixth semiconductor layer and the seventh semiconductor layer.

9. A semiconductor device according to claim 1, wherein the source contact connecting the source electrode to the sixth semiconductor layer and the seventh semiconductor layer is connected to the seventh semiconductor layer and an eighth semiconductor layer formed in contact with the sixth semiconductor layer and having a higher concentration than the sixth semiconductor layer.

10. A semiconductor device according to claim 1, wherein the lead wiring for the gate electrode is buried inside a trench for the lead wiring that is different from the first trench and the second trench.

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